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8993e54b | 1 | /* |
3b74e7ec | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
8993e54b | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
8993e54b RJ |
5 | */ |
6 | ||
7 | /* | |
72601d04 | 8 | * MPC5121ADS board configuration file |
8993e54b RJ |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
72601d04 | 14 | #define CONFIG_MPC5121ADS 1 |
10e99d8f | 15 | |
8993e54b | 16 | /* |
72601d04 | 17 | * Memory map for the MPC5121ADS board: |
8993e54b RJ |
18 | * |
19 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
20 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
21 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
22 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
5f91db7f JR |
23 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
24 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) | |
25 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
8993e54b RJ |
26 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
27 | */ | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 /* E300 Family */ | |
0e1bad47 | 33 | |
2ae18241 WD |
34 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
35 | ||
0e1bad47 | 36 | /* video */ |
7d3053fb TT |
37 | #ifdef CONFIG_FSL_DIU_FB |
38 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) | |
e69e520f | 39 | #define CONFIG_CMD_BMP |
e69e520f TT |
40 | #define CONFIG_VIDEO_LOGO |
41 | #define CONFIG_VIDEO_BMP_LOGO | |
0e1bad47 | 42 | #endif |
8993e54b | 43 | |
5f91db7f | 44 | /* CONFIG_PCI is defined at config time */ |
8993e54b | 45 | |
72601d04 | 46 | #ifdef CONFIG_MPC5121ADS_REV2 |
6d0f6bcf | 47 | #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ |
f31c49db | 48 | #else |
6d0f6bcf | 49 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
f31c49db | 50 | #endif |
8993e54b | 51 | |
0e1bad47 | 52 | #define CONFIG_MISC_INIT_R |
8993e54b | 53 | |
6d0f6bcf | 54 | #define CONFIG_SYS_IMMR 0x80000000 |
8993e54b | 55 | |
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
57 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
8993e54b RJ |
58 | |
59 | /* | |
60 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
61 | */ | |
72601d04 | 62 | #ifdef CONFIG_MPC5121ADS_REV2 |
6d0f6bcf | 63 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
f31c49db | 64 | #else |
6d0f6bcf | 65 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
f31c49db | 66 | #endif |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
68 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
b9947bbb | 69 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
8993e54b | 70 | |
5d937e8b AG |
71 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
72 | ||
8993e54b | 73 | /* DDR Controller Configuration |
b1b54e35 WD |
74 | * |
75 | * SYS_CFG: | |
76 | * [31:31] MDDRC Soft Reset: Diabled | |
77 | * [30:30] DRAM CKE pin: Enabled | |
78 | * [29:29] DRAM CLK: Enabled | |
79 | * [28:28] Command Mode: Enabled (For initialization only) | |
80 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
81 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
82 | * [20:19] Read Test: DON'T USE | |
83 | * [18:18] Self Refresh: Enabled | |
84 | * [17:17] 16bit Mode: Disabled | |
85 | * [16:13] Ready Delay: 2 | |
86 | * [12:12] Half DQS Delay: Disabled | |
87 | * [11:11] Quarter DQS Delay: Disabled | |
88 | * [10:08] Write Delay: 2 | |
89 | * [07:07] Early ODT: Disabled | |
90 | * [06:06] On DIE Termination: Disabled | |
91 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
92 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
93 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
94 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
95 | * [01:01] FIFO Overlfow Enabled: Enabled | |
96 | * [00:00] FIFO Underflow Enabled: Enabled | |
97 | * TIME_CFG0 | |
98 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
99 | * [15:8] DRAM Command Time: 0 CSB clocks | |
100 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
101 | * TIME_CFG1 | |
102 | * [31:26] DRAM tRFC: | |
103 | * [25:21] DRAM tWR1: | |
104 | * [20:17] DRAM tWRT1: | |
105 | * [16:11] DRAM tDRR: | |
106 | * [10:05] DRAM tRC: | |
107 | * [04:00] DRAM tRAS: | |
108 | * TIME_CFG2 | |
109 | * [31:28] DRAM tRCD: | |
110 | * [27:23] DRAM tFAW: | |
111 | * [22:19] DRAM tRTW1: | |
112 | * [18:15] DRAM tCCD: | |
113 | * [14:10] DRAM tRTP: | |
114 | * [09:05] DRAM tRP: | |
115 | * [04:00] DRAM tRPA | |
116 | */ | |
72601d04 | 117 | #ifdef CONFIG_MPC5121ADS_REV2 |
054197ba | 118 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 |
120 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 | |
f31c49db | 121 | #else |
054197ba MS |
122 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 |
123 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 | |
124 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 | |
f31c49db | 125 | #endif |
054197ba | 126 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E |
6d0f6bcf | 127 | |
a5aa3998 MS |
128 | #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 |
129 | #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 | |
130 | #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 | |
131 | ||
054197ba MS |
132 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
133 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
134 | #define CONFIG_SYS_DDRCMD_EM2 0x01020000 | |
135 | #define CONFIG_SYS_DDRCMD_EM3 0x01030000 | |
136 | #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 | |
137 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 | |
a5aa3998 MS |
138 | |
139 | #define DDRCMD_EMR_OCD(pr, ohm) ( \ | |
140 | (1 << 24) | /* MDDRC Command Request */ \ | |
141 | (1 << 16) | /* MODE Reg BA[2:0] */ \ | |
142 | (0 << 12) | /* Outputs 0=Enabled */ \ | |
143 | (0 << 11) | /* RDQS */ \ | |
144 | (1 << 10) | /* DQS# */ \ | |
145 | (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ | |
146 | /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ | |
147 | ((ohm & 0x2) << 5)| /* Rtt1 */ \ | |
148 | (0 << 3) | /* additive posted CAS# */ \ | |
149 | ((ohm & 0x1) << 2)| /* Rtt0 */ \ | |
150 | (0 << 0) | /* Output Drive Strength */ \ | |
151 | (0 << 0)) /* DLL Enable 0=Normal */ | |
152 | ||
153 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) | |
154 | #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) | |
155 | ||
156 | #define DDRCMD_MODE_REG(cas, wr) ( \ | |
157 | (1 << 24) | /* MDDRC Command Request */ \ | |
158 | (0 << 16) | /* MODE Reg BA[2:0] */ \ | |
159 | ((wr-1) << 9)| /* Write Recovery */ \ | |
160 | (cas << 4) | /* CAS */ \ | |
161 | (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ | |
162 | (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ | |
163 | ||
164 | #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) | |
165 | #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) | |
166 | #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) | |
8993e54b RJ |
167 | |
168 | /* DDR Priority Manager Configuration */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
170 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
171 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
172 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
173 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
174 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
175 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
176 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
177 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
178 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
179 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
180 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
181 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
182 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
183 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
184 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
185 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
186 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
187 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
188 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
189 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
190 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
191 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
8993e54b RJ |
192 | |
193 | /* | |
194 | * NOR FLASH on the Local Bus | |
195 | */ | |
f31c49db | 196 | #undef CONFIG_BKUP_FLASH |
6d0f6bcf | 197 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 198 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
f31c49db | 199 | #ifdef CONFIG_BKUP_FLASH |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
201 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ | |
f31c49db | 202 | #else |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ |
204 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
f31c49db | 205 | #endif |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
207 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
208 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
209 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
8993e54b | 210 | |
6d0f6bcf | 211 | #undef CONFIG_SYS_FLASH_CHECKSUM |
8993e54b | 212 | |
229549a5 SR |
213 | /* |
214 | * NAND FLASH | |
13946925 | 215 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) |
229549a5 | 216 | */ |
7d4450a9 WD |
217 | #define CONFIG_CMD_NAND /* enable NAND support */ |
218 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
229549a5 SR |
219 | #define CONFIG_NAND_MPC5121_NFC |
220 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
221 | ||
222 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
229549a5 SR |
223 | #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ |
224 | ||
225 | /* | |
226 | * Configuration parameters for MPC5121 NAND driver | |
227 | */ | |
228 | #define CONFIG_FSL_NFC_WIDTH 1 | |
229 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
230 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
231 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
232 | ||
8993e54b RJ |
233 | /* |
234 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
235 | * window is 64KB | |
236 | */ | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_CPLD_BASE 0x82000000 |
238 | #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ | |
676c6691 AG |
239 | #define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE |
240 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE | |
8993e54b | 241 | |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
243 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
8993e54b | 244 | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ |
246 | #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
247 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ | |
8993e54b RJ |
248 | |
249 | /* Use SRAM for initial stack */ | |
6d0f6bcf | 250 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ |
553f0982 | 251 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */ |
8993e54b | 252 | |
25ddd1fb | 253 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 254 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8993e54b | 255 | |
14d0a02a | 256 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ |
229549a5 | 257 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
0e1bad47 | 258 | #ifdef CONFIG_FSL_DIU_FB |
6d0f6bcf | 259 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
0e1bad47 | 260 | #else |
6d0f6bcf | 261 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
0e1bad47 | 262 | #endif |
8993e54b RJ |
263 | |
264 | /* | |
265 | * Serial Port | |
266 | */ | |
267 | #define CONFIG_CONS_INDEX 1 | |
8993e54b RJ |
268 | |
269 | /* | |
270 | * Serial console configuration | |
271 | */ | |
272 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
bfb31279 | 273 | #define CONFIG_SYS_PSC3 |
8993e54b RJ |
274 | #if CONFIG_PSC_CONSOLE != 3 |
275 | #error CONFIG_PSC_CONSOLE must be 3 | |
276 | #endif | |
277 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8993e54b RJ |
279 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
280 | ||
281 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
282 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
283 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
284 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
285 | ||
286 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
8993e54b | 287 | |
e5f53864 AG |
288 | /* |
289 | * Clocks in use | |
290 | */ | |
291 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
292 | CLOCK_SCCR1_DDR_EN | \ | |
293 | CLOCK_SCCR1_FEC_EN | \ | |
294 | CLOCK_SCCR1_LPC_EN | \ | |
295 | CLOCK_SCCR1_NFC_EN | \ | |
296 | CLOCK_SCCR1_PATA_EN | \ | |
297 | CLOCK_SCCR1_PCI_EN | \ | |
298 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
299 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
300 | CLOCK_SCCR1_TPR_EN) | |
301 | ||
302 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ | |
303 | CLOCK_SCCR2_I2C_EN | \ | |
304 | CLOCK_SCCR2_MEM_EN | \ | |
305 | CLOCK_SCCR2_SPDIF_EN | \ | |
306 | CLOCK_SCCR2_USB1_EN | \ | |
307 | CLOCK_SCCR2_USB2_EN) | |
308 | ||
5f91db7f JR |
309 | /* |
310 | * PCI | |
311 | */ | |
312 | #ifdef CONFIG_PCI | |
842033e6 | 313 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5f91db7f JR |
314 | |
315 | /* | |
316 | * General PCI | |
317 | */ | |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 |
319 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
320 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
321 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) | |
322 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
323 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
324 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
325 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
326 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
5f91db7f | 327 | |
5f91db7f JR |
328 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
329 | ||
330 | #endif | |
331 | ||
8993e54b RJ |
332 | /* I2C */ |
333 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
8993e54b | 334 | #define CONFIG_I2C_MULTI_BUS |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
336 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
8993e54b | 337 | #if 0 |
6d0f6bcf | 338 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
8993e54b RJ |
339 | #endif |
340 | ||
abfbd0ae MM |
341 | /* |
342 | * IIM - IC Identification Module | |
343 | */ | |
83306927 | 344 | #undef CONFIG_FSL_IIM |
abfbd0ae | 345 | |
80020120 GB |
346 | /* |
347 | * EEPROM configuration | |
348 | */ | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ |
350 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
351 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ | |
352 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ | |
80020120 | 353 | |
8993e54b RJ |
354 | /* |
355 | * Ethernet configuration | |
356 | */ | |
357 | #define CONFIG_MPC512x_FEC 1 | |
8993e54b RJ |
358 | #define CONFIG_PHY_ADDR 0x1 |
359 | #define CONFIG_MII 1 /* MII PHY management */ | |
f31c49db | 360 | #define CONFIG_FEC_AN_TIMEOUT 1 |
ef11df6b | 361 | #define CONFIG_HAS_ETH0 |
8993e54b | 362 | |
8993e54b RJ |
363 | /* |
364 | * Configure on-board RTC | |
365 | */ | |
f31c49db | 366 | #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ |
6d0f6bcf | 367 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8993e54b | 368 | |
29c6fbe0 DD |
369 | /* |
370 | * USB Support | |
371 | */ | |
29c6fbe0 DD |
372 | |
373 | #if defined(CONFIG_CMD_USB) | |
374 | #define CONFIG_USB_EHCI /* Enable EHCI Support */ | |
375 | #define CONFIG_USB_EHCI_FSL /* On a FSL platform */ | |
376 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ | |
377 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
378 | #define CONFIG_EHCI_IS_TDI | |
29c6fbe0 DD |
379 | #endif |
380 | ||
8993e54b RJ |
381 | /* |
382 | * Environment | |
383 | */ | |
5a1aceb0 | 384 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8993e54b | 385 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 386 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 387 | #define CONFIG_ENV_SIZE 0x2000 |
f31c49db | 388 | #ifdef CONFIG_BKUP_FLASH |
0e8d1586 | 389 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ |
f31c49db | 390 | #else |
0e8d1586 | 391 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
f31c49db | 392 | #endif |
8993e54b RJ |
393 | |
394 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
395 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
396 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8993e54b RJ |
397 | |
398 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 399 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8993e54b | 400 | |
7d4450a9 | 401 | #define CONFIG_CMD_DATE |
7d4450a9 | 402 | #define CONFIG_CMD_EEPROM |
7d4450a9 WD |
403 | #define CONFIG_CMD_IDE |
404 | #define CONFIG_CMD_JFFS2 | |
e27f3a6e | 405 | #define CONFIG_CMD_REGINFO |
7d4450a9 | 406 | |
abfbd0ae | 407 | #undef CONFIG_CMD_FUSE |
e27f3a6e | 408 | |
8993e54b | 409 | #if defined(CONFIG_PCI) |
e27f3a6e | 410 | #define CONFIG_CMD_PCI |
8993e54b RJ |
411 | #endif |
412 | ||
7d4450a9 WD |
413 | /* |
414 | * Dynamic MTD partition support | |
415 | */ | |
416 | #define CONFIG_CMD_MTDPARTS | |
417 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
418 | #define CONFIG_FLASH_CFI_MTD | |
419 | #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" | |
420 | ||
421 | /* | |
422 | * NOR flash layout: | |
423 | * | |
424 | * FC000000 - FEABFFFF 42.75 MiB User Data | |
425 | * FEAC0000 - FFABFFFF 16 MiB Root File System | |
426 | * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel | |
427 | * FFEC0000 - FFEFFFFF 256 KiB Device Tree | |
428 | * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env | |
429 | * | |
430 | * NAND flash layout: one big partition | |
431 | */ | |
432 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ | |
433 | "16m(rootfs)," \ | |
434 | "4m(kernel)," \ | |
435 | "256k(dtb)," \ | |
436 | "1m(u-boot);" \ | |
437 | "mpc5121.nand:-(data)" | |
438 | ||
29c6fbe0 DD |
439 | #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) |
440 | ||
70a4da45 RK |
441 | #define CONFIG_DOS_PARTITION |
442 | #define CONFIG_MAC_PARTITION | |
443 | #define CONFIG_ISO_PARTITION | |
29c6fbe0 | 444 | |
29c6fbe0 DD |
445 | #define CONFIG_SUPPORT_VFAT |
446 | ||
70a4da45 RK |
447 | #endif /* defined(CONFIG_CMD_IDE) */ |
448 | ||
8993e54b | 449 | /* |
6d0f6bcf JCPV |
450 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
451 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set | |
8993e54b RJ |
452 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
453 | * to chapter 36 of the MPC5121e Reference Manual. | |
454 | */ | |
66ffb188 | 455 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
6d0f6bcf | 456 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
8993e54b RJ |
457 | |
458 | /* | |
459 | * Miscellaneous configurable options | |
460 | */ | |
6d0f6bcf JCPV |
461 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
462 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8993e54b | 463 | |
e27f3a6e | 464 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 465 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8993e54b | 466 | #else |
6d0f6bcf | 467 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8993e54b RJ |
468 | #endif |
469 | ||
6d0f6bcf JCPV |
470 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
471 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
472 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8993e54b RJ |
473 | |
474 | /* | |
475 | * For booting Linux, the board info and command line data | |
9f530d59 | 476 | * have to be in the first 256 MB of memory, since this is |
8993e54b RJ |
477 | * the maximum mapped by the Linux kernel during initialization. |
478 | */ | |
9f530d59 | 479 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
8993e54b RJ |
480 | |
481 | /* Cache Configuration */ | |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
483 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
e27f3a6e | 484 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 485 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
8993e54b RJ |
486 | #endif |
487 | ||
6d0f6bcf | 488 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
e2b66fe4 | 489 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) |
6d0f6bcf | 490 | #define CONFIG_SYS_HID2 HID2_HBE |
8993e54b | 491 | |
31d82672 BB |
492 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
493 | ||
e27f3a6e | 494 | #ifdef CONFIG_CMD_KGDB |
8993e54b | 495 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
8993e54b RJ |
496 | #endif |
497 | ||
498 | /* | |
499 | * Environment Configuration | |
500 | */ | |
66ffb188 | 501 | #define CONFIG_TIMESTAMP |
8993e54b | 502 | |
72601d04 | 503 | #define CONFIG_HOSTNAME mpc5121ads |
b3f44c21 | 504 | #define CONFIG_BOOTFILE "mpc5121ads/uImage" |
8b3637c6 | 505 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
8993e54b | 506 | |
8d103071 | 507 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
8993e54b | 508 | |
8993e54b RJ |
509 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
510 | ||
511 | #define CONFIG_BAUDRATE 115200 | |
512 | ||
513 | #define CONFIG_PREBOOT "echo;" \ | |
5b0b2b6f | 514 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
8993e54b RJ |
515 | "echo" |
516 | ||
517 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d103071 | 518 | "u-boot_addr_r=200000\0" \ |
51e46e28 WD |
519 | "kernel_addr_r=600000\0" \ |
520 | "fdt_addr_r=880000\0" \ | |
521 | "ramdisk_addr_r=900000\0" \ | |
8d103071 | 522 | "u-boot_addr=FFF00000\0" \ |
7d4450a9 | 523 | "kernel_addr=FFAC0000\0" \ |
51e46e28 | 524 | "fdt_addr=FFEC0000\0" \ |
7d4450a9 | 525 | "ramdisk_addr=FEAC0000\0" \ |
72601d04 WD |
526 | "ramdiskfile=mpc5121ads/uRamdisk\0" \ |
527 | "u-boot=mpc5121ads/u-boot.bin\0" \ | |
528 | "bootfile=mpc5121ads/uImage\0" \ | |
529 | "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ | |
51e46e28 | 530 | "rootpath=/opt/eldk/ppc_6xx\n" \ |
8993e54b | 531 | "netdev=eth0\0" \ |
8d103071 | 532 | "consdev=ttyPSC0\0" \ |
8993e54b RJ |
533 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
534 | "nfsroot=${serverip}:${rootpath}\0" \ | |
535 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
536 | "addip=setenv bootargs ${bootargs} " \ | |
537 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
538 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8d103071 WD |
539 | "addtty=setenv bootargs ${bootargs} " \ |
540 | "console=${consdev},${baudrate}\0" \ | |
8993e54b | 541 | "flash_nfs=run nfsargs addip addtty;" \ |
a99715b8 | 542 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
8993e54b | 543 | "flash_self=run ramargs addip addtty;" \ |
8d103071 WD |
544 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
545 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
546 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
547 | "run nfsargs addip addtty;" \ | |
548 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
549 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
550 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
a99715b8 | 551 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
8d103071 | 552 | "run ramargs addip addtty;" \ |
5b0b2b6f | 553 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
a99715b8 | 554 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
8d103071 WD |
555 | "update=protect off ${u-boot_addr} +${filesize};" \ |
556 | "era ${u-boot_addr} +${filesize};" \ | |
557 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
558 | "upd=run load update\0" \ | |
8993e54b RJ |
559 | "" |
560 | ||
8993e54b RJ |
561 | #define CONFIG_BOOTCOMMAND "run flash_self" |
562 | ||
ef11df6b | 563 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
281ff9a4 GB |
564 | |
565 | #define OF_CPU "PowerPC,5121@0" | |
ef11df6b | 566 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
281ff9a4 | 567 | #define OF_TBCLK (bd->bi_busfreq / 4) |
ac915283 | 568 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
281ff9a4 | 569 | |
70a4da45 RK |
570 | /*----------------------------------------------------------------------- |
571 | * IDE/ATA stuff | |
572 | *----------------------------------------------------------------------- | |
573 | */ | |
574 | ||
575 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
576 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
577 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
578 | ||
579 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
580 | #define CONFIG_IDE_PREINIT | |
581 | ||
582 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
583 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
584 | ||
585 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3b74e7ec | 586 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() |
70a4da45 RK |
587 | |
588 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
589 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
590 | ||
591 | /* Offset for normal register accesses */ | |
592 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
593 | ||
594 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
595 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
596 | ||
597 | /* Interval between registers */ | |
598 | #define CONFIG_SYS_ATA_STRIDE 4 | |
599 | ||
3b74e7ec | 600 | #define ATA_BASE_ADDR get_pata_base() |
70a4da45 RK |
601 | |
602 | /* | |
603 | * Control register bit definitions | |
604 | */ | |
605 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
606 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
607 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
608 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
609 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
610 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
611 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
612 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
613 | ||
8993e54b | 614 | #endif /* __CONFIG_H */ |