[people/ms/u-boot.git] / include / configs / mx31pdk.h

/*
 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
 *
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the Freescale i.MX31 PDK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
#define CONFIG_MX31			/* in a mx31 */

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_MACH_TYPE	MACH_TYPE_MX31_3DS

#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE
#define CONFIG_HW_WATCHDOG
#define CONFIG_MXC_GPIO

#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

/* PMIC Controller */
#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
#define CONFIG_PMIC_FSL
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	2
#define CONFIG_FSL_PMIC_CLK	1000000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN	32
#define CONFIG_RTC_MC13XXX

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX		1
#define CONFIG_BAUDRATE			115200

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_BOOTZ

/*
 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
 * that CFG_NO_FLASH is undefined).
 */
#undef CONFIG_CMD_IMLS

#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTDELAY	3

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
	"bootcmd=run bootcmd_net\0"					\
	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
	"prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; "		\
		"nand erase 0x0 0x40000; "				\
		"nand write 0x81000000 0x0 0x40000\0"

#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	0xB6000000
#define CONFIG_SMC911X_32_BIT

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_SYS_PROMPT	"MX31PDK U-Boot > "
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
				sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS	16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x80010000

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x81000000

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_GBL_DATA_OFFSET)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
/* No NOR flash present */
#define CONFIG_SYS_NO_FLASH

#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_OFFSET_REDUND	0x60000
#define CONFIG_ENV_SIZE			(128 * 1024)

/*
 * NAND driver
 */
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

/* NAND configuration for the NAND_SPL */

/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x30000
/* Load U-Boot to this address */
#define CONFIG_SYS_NAND_U_BOOT_DST	0x87f00000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST

#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0


/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP		0x074B0BF5
#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
				 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
				 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
				 PDR0_MCU_PODF(0))
#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
				 PLL_MFN(12))

#define ESDMISC_MDDR_SETUP	0x00000004
#define ESDMISC_MDDR_RESET_DL	0x0000000c
#define ESDCFG0_MDDR_SETUP	0x006ac73a

#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
#define ESDCTL_RW		ESDCTL_SETTINGS

#endif /* __CONFIG_H */
Commit	Line	Data
8449f287 ML	1	/*
	2	* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
	3	*
	4	* (C) Copyright 2004
	5	* Texas Instruments.
	6	* Richard Woodruff <r-woodruff2@ti.com>
	7	* Kshitij Gupta <kshitij@ti.com>
	8	*
	9	* Configuration settings for the Freescale i.MX31 PDK board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
86271115	33	#include <asm/arch/imx-regs.h>
38a8b3ea	34
8449f287	35	/* High Level Configuration Options */
e89f1f91 FE	36	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
e89f1f91 FE	37	#define CONFIG_MX31 /* in a mx31 */
8449f287 ML	38
	39	#define CONFIG_DISPLAY_CPUINFO
	40	#define CONFIG_DISPLAY_BOARDINFO
	41
e89f1f91 FE	42	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	43	#define CONFIG_SETUP_MEMORY_TAGS
	44	#define CONFIG_INITRD_TAG
8449f287	45
9aa3c6a1 FE	46	#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
9aa3c6a1 FE	47
d08e5ca3	48	#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
8449f287	49	#define CONFIG_SKIP_LOWLEVEL_INIT
d08e5ca3	50	#endif
8449f287 ML	51
	52	/*
	53	* Size of malloc() pool
	54	*/
38a8b3ea	55	#define CONFIG_SYS_MALLOC_LEN (2CONFIG_ENV_SIZE + 2 128 * 1024)
8449f287 ML	56
	57	/*
	58	* Hardware drivers
	59	*/
	60
e89f1f91	61	#define CONFIG_MXC_UART
40f6fffe	62	#define CONFIG_MXC_UART_BASE UART1_BASE
b73850f7	63	#define CONFIG_HW_WATCHDOG
6f2a4be9	64	#define CONFIG_MXC_GPIO
8449f287	65
e89f1f91 FE	66	#define CONFIG_HARD_SPI
e89f1f91 FE	67	#define CONFIG_MXC_SPI
8449f287	68	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	69	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
8449f287	70
877a438a SB	71	/* PMIC Controller */
	72	#define CONFIG_PMIC
	73	#define CONFIG_PMIC_SPI
	74	#define CONFIG_PMIC_FSL
dfe5e14f SB	75	#define CONFIG_FSL_PMIC_BUS 1
	76	#define CONFIG_FSL_PMIC_CS 2
	77	#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95	78	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
877a438a	79	#define CONFIG_FSL_PMIC_BITLEN 32
4e8b7544	80	#define CONFIG_RTC_MC13XXX
8449f287	81
8449f287 ML	82	/* allow to overwrite serial and ethaddr */
	83	#define CONFIG_ENV_OVERWRITE
	84	#define CONFIG_CONS_INDEX 1
	85	#define CONFIG_BAUDRATE 115200
8449f287 ML	86
	87	/***********************************************************
	88	* Command definition
	89	***********************************************************/
	90
	91	#include <config_cmd_default.h>
	92
	93	#define CONFIG_CMD_MII
	94	#define CONFIG_CMD_PING
fc971028	95	#define CONFIG_CMD_DHCP
8449f287 ML	96	#define CONFIG_CMD_SPI
8449f287 ML	97	#define CONFIG_CMD_DATE
38a8b3ea	98	#define CONFIG_CMD_NAND
0c23d84c	99	#define CONFIG_CMD_BOOTZ
8449f287 ML	100
	101	/*
	102	* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
	103	* that CFG_NO_FLASH is undefined).
	104	*/
	105	#undef CONFIG_CMD_IMLS
	106
9660e442	107	#define CONFIG_BOARD_LATE_INIT
b73850f7	108
8449f287 ML	109	#define CONFIG_BOOTDELAY 3
	110
	111	#define CONFIG_EXTRA_ENV_SETTINGS \
	112	"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
	113	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
	114	"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	115	"bootcmd=run bootcmd_net\0" \
	116	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
38a8b3ea ML	117	"tftpboot 0x81000000 uImage-mx31; bootm\0" \
	118	"prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
	119	"nand erase 0x0 0x40000; " \
	120	"nand write 0x81000000 0x0 0x40000\0"
8449f287	121
e89f1f91	122	#define CONFIG_SMC911X
736fead8	123	#define CONFIG_SMC911X_BASE 0xB6000000
e89f1f91	124	#define CONFIG_SMC911X_32_BIT
8449f287 ML	125
	126	/*
	127	* Miscellaneous configurable options
	128	*/
	129	#define CONFIG_SYS_LONGHELP /* undef to save memory */
b6e6ebbf	130	#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > "
8449f287 ML	131	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	132	/* Print Buffer Size */
	133	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	134	sizeof(CONFIG_SYS_PROMPT)+16)
	135	/* max number of command args */
	136	#define CONFIG_SYS_MAXARGS 16
	137	/* Boot Argument Buffer Size */
	138	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	139
	140	/* memtest works on */
	141	#define CONFIG_SYS_MEMTEST_START 0x80000000
304e49e6	142	#define CONFIG_SYS_MEMTEST_END 0x80010000
8449f287 ML	143
	144	/* default load address */
	145	#define CONFIG_SYS_LOAD_ADDR 0x81000000
	146
	147	#define CONFIG_SYS_HZ 1000
	148
e89f1f91	149	#define CONFIG_CMDLINE_EDITING
8449f287	150
8449f287 ML	151	/*-----------------------------------------------------------------------
	152	* Physical Memory Map
	153	*/
	154	#define CONFIG_NR_DRAM_BANKS 1
	155	#define PHYS_SDRAM_1 CSD0_BASE
	156	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
e89f1f91	157	#define CONFIG_BOARD_EARLY_INIT_F
8449f287	158
ed3df72d FE	159	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	160	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	161	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
026ca659 FE	162	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	163	GENERATED_GBL_DATA_SIZE)
	164	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	165	CONFIG_SYS_GBL_DATA_OFFSET)
ed3df72d	166
8449f287 ML	167	/*-----------------------------------------------------------------------
	168	* FLASH and environment organization
	169	*/
	170	/* No NOR flash present */
e89f1f91	171	#define CONFIG_SYS_NO_FLASH
8449f287	172
e89f1f91	173	#define CONFIG_ENV_IS_IN_NAND
38a8b3ea ML	174	#define CONFIG_ENV_OFFSET 0x40000
	175	#define CONFIG_ENV_OFFSET_REDUND 0x60000
	176	#define CONFIG_ENV_SIZE (128 * 1024)
8449f287	177
38a8b3ea ML	178	/*
	179	* NAND driver
	180	*/
	181	#define CONFIG_NAND_MXC
	182	#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
	183	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	184	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	185	#define CONFIG_MXC_NAND_HWECC
	186	#define CONFIG_SYS_NAND_LARGEPAGE
8449f287	187
d08e5ca3 ML	188	/* NAND configuration for the NAND_SPL */
	189
	190	/* Start copying real U-boot from the second page */
	191	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
	192	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
	193	/* Load U-Boot to this address */
	194	#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
	195	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	196
	197	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	198	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	199	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	200	#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
	201	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	202
	203
	204	/* Configuration of lowlevel_init.S (clocks and SDRAM) */
	205	#define CCM_CCMR_SETUP 0x074B0BF5
	206	#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) \| PDR0_PER_PODF(7) \| \
	207	PDR0_HSP_PODF(3) \| PDR0_NFC_PODF(5) \| \
	208	PDR0_IPG_PODF(1) \| PDR0_MAX_PODF(3) \| \
	209	PDR0_MCU_PODF(0))
	210	#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) \| PLL_MFD(51) \| PLL_MFI(10) \| \
	211	PLL_MFN(12))
	212
	213	#define ESDMISC_MDDR_SETUP 0x00000004
	214	#define ESDMISC_MDDR_RESET_DL 0x0000000c
	215	#define ESDCFG0_MDDR_SETUP 0x006ac73a
	216
	217	#define ESDCTL_ROW_COL (ESDCTL_SDE \| ESDCTL_ROW(2) \| ESDCTL_COL(2))
	218	#define ESDCTL_SETTINGS (ESDCTL_ROW_COL \| ESDCTL_SREFR(3) \| \
	219	ESDCTL_DSIZ(2) \| ESDCTL_BL(1))
	220	#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL \| ESDCTL_CMD_PRECHARGE)
	221	#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL \| ESDCTL_CMD_AUTOREFRESH)
	222	#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL \| ESDCTL_CMD_LOADMODEREG)
	223	#define ESDCTL_RW ESDCTL_SETTINGS
	224
8449f287	225	#endif /* __CONFIG_H */