projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 887e2ec9 | 1 | /* |
| fc84a849 | 2 | * (C) Copyright 2006-2008 |
| 887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * | |
| 5 | * (C) Copyright 2006 | |
| 6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
| 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
| 8 | * | |
| 1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 887e2ec9 SR |
10 | */ |
| 11 | ||
| 214398d9 | 12 | /* |
| e802594b | 13 | * sequoia.h - configuration for Sequoia & Rainier boards |
| 214398d9 | 14 | */ |
| 887e2ec9 SR |
15 | #ifndef __CONFIG_H |
| 16 | #define __CONFIG_H | |
| 17 | ||
| 214398d9 | 18 | /* |
| 887e2ec9 | 19 | * High Level Configuration Options |
| 214398d9 | 20 | */ |
| e802594b | 21 | /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ |
| 854bc8da | 22 | #ifndef CONFIG_RAINIER |
| 214398d9 | 23 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
| 72675dc6 | 24 | #define CONFIG_HOSTNAME sequoia |
| 854bc8da | 25 | #else |
| 214398d9 | 26 | #define CONFIG_440GRX 1 /* Specific PPC440GRx */ |
| 72675dc6 | 27 | #define CONFIG_HOSTNAME rainier |
| 854bc8da | 28 | #endif |
| 214398d9 LJ |
29 | #define CONFIG_440 1 /* ... PPC440 family */ |
| 30 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 72675dc6 | 31 | |
| 2ae18241 WD |
32 | #ifndef CONFIG_SYS_TEXT_BASE |
| 33 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
| 34 | #endif | |
| 35 | ||
| 72675dc6 SR |
36 | /* |
| 37 | * Include common defines/options for all AMCC eval boards | |
| 38 | */ | |
| 39 | #include "amcc-common.h" | |
| 40 | ||
| e3b8c78b | 41 | /* Detect Sequoia PLL input clock automatically via CPLD bit */ |
| 6d0f6bcf | 42 | #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \ |
| 193b4a3b | 43 | 33333333 : 33000000) |
| 887e2ec9 | 44 | |
| bc778812 AG |
45 | /* |
| 46 | * Define this if you want support for video console with radeon 9200 pci card | |
| 14d0a02a | 47 | * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case |
| bc778812 AG |
48 | */ |
| 49 | #undef CONFIG_VIDEO | |
| 50 | ||
| 51 | #ifdef CONFIG_VIDEO | |
| d25dfe08 SR |
52 | /* |
| 53 | * 44x dcache supported is working now on sequoia, but we don't enable | |
| 54 | * it yet since it needs further testing | |
| 55 | */ | |
| 214398d9 | 56 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
| d25dfe08 SR |
57 | #endif |
| 58 | ||
| 214398d9 LJ |
59 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 60 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
| 887e2ec9 | 61 | |
| 214398d9 LJ |
62 | /* |
| 63 | * Base addresses -- Note these are effective addresses where the actual | |
| 64 | * resources get mapped (not physical addresses). | |
| 65 | */ | |
| 6d0f6bcf JCPV |
66 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003 |
| 67 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
| 68 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ | |
| 69 | #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */ | |
| 70 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
| 71 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE | |
| 72 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
| 73 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
| 74 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
| 75 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
| 76 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
| 887e2ec9 | 77 | |
| 6d0f6bcf JCPV |
78 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
| 79 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
| 80 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
| 81 | #define CONFIG_SYS_BCSR_BASE 0xc0000000 | |
| 887e2ec9 | 82 | |
| 214398d9 | 83 | /* |
| 887e2ec9 | 84 | * Initial RAM & stack pointer |
| 214398d9 | 85 | */ |
| 887e2ec9 | 86 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
| 6d0f6bcf | 87 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
| 553f0982 | 88 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
| 25ddd1fb | 89 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 800eb096 | 90 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
| 887e2ec9 | 91 | |
| 214398d9 | 92 | /* |
| 887e2ec9 | 93 | * Serial Port |
| 214398d9 | 94 | */ |
| 550650dd | 95 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 6d0f6bcf | 96 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
| 887e2ec9 | 97 | |
| 214398d9 | 98 | /* |
| 887e2ec9 | 99 | * Environment |
| 214398d9 | 100 | */ |
| d873133f SR |
101 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
| 102 | #define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */ | |
| 103 | #define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */ | |
| 104 | #elif defined(CONFIG_SYS_RAMBOOT) | |
| 105 | #define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */ | |
| 106 | #define CONFIG_ENV_SIZE (8 << 10) | |
| 107 | /* | |
| 108 | * In RAM-booting version, we have no environment storage. So we need to | |
| 109 | * provide at least preliminary MAC addresses for the 4xx EMAC driver to | |
| 110 | * register the interfaces. Those two addresses are generated via the | |
| 111 | * tools/gen_eth_addr tool and should only be used in a closed laboratory | |
| 112 | * environment. | |
| 113 | */ | |
| 114 | #define CONFIG_ETHADDR 4a:56:49:22:3e:43 | |
| 115 | #define CONFIG_ETH1ADDR 02:93:53:d5:06:98 | |
| 887e2ec9 | 116 | #else |
| d873133f | 117 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */ |
| 887e2ec9 | 118 | #endif |
| 887e2ec9 | 119 | |
| d873133f | 120 | #if defined(CONFIG_CMD_FLASH) |
| 214398d9 | 121 | /* |
| 887e2ec9 | 122 | * FLASH related |
| 214398d9 | 123 | */ |
| 6d0f6bcf | 124 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 00b1883a | 125 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 887e2ec9 | 126 | |
| 6d0f6bcf | 127 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 887e2ec9 | 128 | |
| 6d0f6bcf JCPV |
129 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 130 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
| 887e2ec9 | 131 | |
| 6d0f6bcf JCPV |
132 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 133 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 887e2ec9 | 134 | |
| 6d0f6bcf JCPV |
135 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 136 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
| 887e2ec9 | 137 | |
| 6d0f6bcf JCPV |
138 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 139 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
| 887e2ec9 | 140 | |
| 5a1aceb0 | 141 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 0e8d1586 | 142 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| 6d0f6bcf | 143 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
| 0e8d1586 | 144 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| 887e2ec9 SR |
145 | |
| 146 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
147 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 148 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 887e2ec9 | 149 | #endif |
| d873133f | 150 | #endif /* CONFIG_CMD_FLASH */ |
| 887e2ec9 | 151 | |
| 887e2ec9 SR |
152 | /* |
| 153 | * IPL (Initial Program Loader, integrated inside CPU) | |
| 154 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
| 155 | * | |
| 156 | * SPL (Secondary Program Loader) | |
| 157 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
| 158 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
| 159 | * controller and the NAND controller so that the special U-Boot image can be | |
| 160 | * loaded from NAND to SDRAM. | |
| 161 | * | |
| 162 | * NUB (NAND U-Boot) | |
| 163 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
| 164 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
| 165 | * | |
| 166 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
| 167 | * set up. While still running from cache, I experienced problems accessing | |
| 168 | * the NAND controller. sr - 2006-08-25 | |
| 169 | */ | |
| 6d0f6bcf JCPV |
170 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
| 171 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
| 172 | #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
| 173 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
| 174 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ | |
| 214398d9 | 175 | /* this addr */ |
| 6d0f6bcf | 176 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) |
| 887e2ec9 SR |
177 | |
| 178 | /* | |
| 179 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
| 180 | */ | |
| 6d0f6bcf JCPV |
181 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
| 182 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ | |
| 887e2ec9 SR |
183 | |
| 184 | /* | |
| 185 | * Now the NAND chip has to be defined (no autodetection used!) | |
| 186 | */ | |
| 6d0f6bcf JCPV |
187 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
| 188 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
| 189 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
| 190 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
| 191 | #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
| 192 | ||
| 193 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
| 194 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
| 6d0f6bcf | 195 | #define CONFIG_SYS_NAND_OOBSIZE 16 |
| 6d0f6bcf | 196 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} |
| 9d909604 | 197 | |
| 51bfee19 | 198 | #ifdef CONFIG_ENV_IS_IN_NAND |
| d12ae808 SR |
199 | /* |
| 200 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
| 201 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
| 202 | */ | |
| 6d0f6bcf JCPV |
203 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 204 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
| 0e8d1586 | 205 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| 887e2ec9 SR |
206 | #endif |
| 207 | ||
| 214398d9 | 208 | /* |
| 887e2ec9 | 209 | * DDR SDRAM |
| 214398d9 | 210 | */ |
| 6d0f6bcf | 211 | #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ |
| d873133f SR |
212 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ |
| 213 | !defined(CONFIG_SYS_RAMBOOT) | |
| 214398d9 | 214 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
| 02388983 | 215 | #endif |
| 6d0f6bcf | 216 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
| 14f73ca6 | 217 | /* 440EPx errata CHIP 11 */ |
| 887e2ec9 | 218 | |
| 214398d9 | 219 | /* |
| 887e2ec9 | 220 | * I2C |
| 214398d9 | 221 | */ |
| 6d0f6bcf | 222 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 887e2ec9 | 223 | |
| 6d0f6bcf JCPV |
224 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| 225 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
| 226 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 227 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 228 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 887e2ec9 | 229 | |
| cfc25874 SR |
230 | /* I2C bootstrap EEPROM */ |
| 231 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 | |
| 232 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
| 233 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
| 234 | ||
| 887e2ec9 | 235 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
| 214398d9 LJ |
236 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
| 237 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
| 238 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
| 6d0f6bcf JCPV |
239 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
| 240 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
| 241 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
| 887e2ec9 | 242 | |
| 72675dc6 SR |
243 | /* |
| 244 | * Default environment variables | |
| 245 | */ | |
| 887e2ec9 | 246 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 72675dc6 SR |
247 | CONFIG_AMCC_DEF_ENV \ |
| 248 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
| 249 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
| 250 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
| 251 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
| 4ef62514 SR |
252 | "kernel_addr=FC000000\0" \ |
| 253 | "ramdisk_addr=FC180000\0" \ | |
| 887e2ec9 | 254 | "" |
| 887e2ec9 SR |
255 | |
| 256 | #define CONFIG_M88E1111_PHY 1 | |
| 257 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 887e2ec9 SR |
258 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
| 259 | ||
| 214398d9 | 260 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
| 887e2ec9 SR |
261 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 262 | ||
| 263 | #define CONFIG_HAS_ETH0 | |
| 887e2ec9 SR |
264 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 265 | #define CONFIG_PHY1_ADDR 1 | |
| 266 | ||
| 267 | /* USB */ | |
| 854bc8da | 268 | #ifdef CONFIG_440EPX |
| 559e2c87 CZ |
269 | |
| 270 | #undef CONFIG_USB_EHCI /* OHCI by default */ | |
| 271 | ||
| 272 | #ifdef CONFIG_USB_EHCI | |
| 273 | #define CONFIG_USB_EHCI_PPC4XX | |
| 274 | #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 | |
| 275 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 276 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN | |
| 277 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
| 559e2c87 | 278 | #else /* CONFIG_USB_EHCI */ |
| 2d146843 | 279 | #define CONFIG_USB_OHCI_NEW |
| 6d0f6bcf | 280 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
| 2d146843 | 281 | |
| 6d0f6bcf JCPV |
282 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
| 283 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
| 284 | #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST | |
| 285 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
| 286 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 559e2c87 | 287 | #endif |
| 887e2ec9 | 288 | |
| 559e2c87 | 289 | #define CONFIG_USB_STORAGE |
| 887e2ec9 SR |
290 | /* Comment this out to enable USB 1.1 device */ |
| 291 | #define USB_2_0_DEVICE | |
| 292 | ||
| 854bc8da SR |
293 | #endif /* CONFIG_440EPX */ |
| 294 | ||
| 887e2ec9 SR |
295 | /* Partitions */ |
| 296 | #define CONFIG_MAC_PARTITION | |
| 297 | #define CONFIG_DOS_PARTITION | |
| 298 | #define CONFIG_ISO_PARTITION | |
| 299 | ||
| 079a136c | 300 | /* |
| 72675dc6 | 301 | * Commands additional to the ones defined in amcc-common.h |
| 079a136c | 302 | */ |
| cfc25874 | 303 | #define CONFIG_CMD_CHIP_CONFIG |
| 46da1e96 | 304 | #define CONFIG_CMD_DTT |
| 46da1e96 | 305 | #define CONFIG_CMD_FAT |
| 46da1e96 | 306 | #define CONFIG_CMD_NAND |
| 46da1e96 | 307 | #define CONFIG_CMD_PCI |
| 46da1e96 JL |
308 | #define CONFIG_CMD_SDRAM |
| 309 | ||
| 310 | #ifdef CONFIG_440EPX | |
| 311 | #define CONFIG_CMD_USB | |
| 312 | #endif | |
| 313 | ||
| 9de469bd | 314 | #ifndef CONFIG_RAINIER |
| 6d0f6bcf | 315 | #define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU |
| 9de469bd | 316 | #else |
| 6d0f6bcf | 317 | #define CONFIG_SYS_POST_FPU_ON 0 |
| 9de469bd | 318 | #endif |
| 887e2ec9 | 319 | |
| 9a929170 SR |
320 | /* |
| 321 | * Don't run the memory POST on the NAND-booting version. It will | |
| 322 | * overwrite part of the U-Boot image which is already loaded from NAND | |
| 323 | * to SDRAM. | |
| 324 | */ | |
| d873133f | 325 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) |
| 9a929170 SR |
326 | #define CONFIG_SYS_POST_MEMORY_ON 0 |
| 327 | #else | |
| 328 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY | |
| 329 | #endif | |
| 330 | ||
| a11e0696 | 331 | /* POST support */ |
| 6d0f6bcf JCPV |
332 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
| 333 | CONFIG_SYS_POST_CPU | \ | |
| 334 | CONFIG_SYS_POST_ETHER | \ | |
| 9a929170 | 335 | CONFIG_SYS_POST_FPU_ON | \ |
| 6d0f6bcf | 336 | CONFIG_SYS_POST_I2C | \ |
| 9a929170 | 337 | CONFIG_SYS_POST_MEMORY_ON | \ |
| 6d0f6bcf JCPV |
338 | CONFIG_SYS_POST_SPR | \ |
| 339 | CONFIG_SYS_POST_UART) | |
| 340 | ||
| a11e0696 | 341 | #define CONFIG_LOGBUFFER |
| 6d0f6bcf | 342 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
| a11e0696 | 343 | |
| 6d0f6bcf | 344 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
| a11e0696 | 345 | |
| 887e2ec9 SR |
346 | #define CONFIG_SUPPORT_VFAT |
| 347 | ||
| 214398d9 | 348 | /* |
| 887e2ec9 | 349 | * PCI stuff |
| 214398d9 | 350 | */ |
| 887e2ec9 | 351 | /* General PCI */ |
| 214398d9 | 352 | #define CONFIG_PCI /* include pci support */ |
| 842033e6 | 353 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| 214398d9 | 354 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 6d0f6bcf | 355 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ |
| 214398d9 | 356 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 6d0f6bcf JCPV |
357 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ |
| 358 | /* CONFIG_SYS_PCI_MEMBASE */ | |
| 887e2ec9 | 359 | /* Board-specific PCI */ |
| 6d0f6bcf JCPV |
360 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 361 | #define CONFIG_SYS_PCI_MASTER_INIT | |
| a760b020 | 362 | #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ |
| 887e2ec9 | 363 | |
| 6d0f6bcf JCPV |
364 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 365 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
| 887e2ec9 | 366 | |
| 214398d9 | 367 | /* |
| 887e2ec9 | 368 | * External Bus Controller (EBC) Setup |
| 214398d9 | 369 | */ |
| 887e2ec9 SR |
370 | |
| 371 | /* | |
| 372 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
| 373 | */ | |
| d873133f SR |
374 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ |
| 375 | !defined(CONFIG_SYS_RAMBOOT) | |
| 6d0f6bcf | 376 | #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ |
| 214398d9 | 377 | /* Memory Bank 0 (NOR-FLASH) initialization */ |
| 6d0f6bcf JCPV |
378 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
| 379 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
| 887e2ec9 | 380 | |
| 214398d9 | 381 | /* Memory Bank 3 (NAND-FLASH) initialization */ |
| 6d0f6bcf JCPV |
382 | #define CONFIG_SYS_EBC_PB3AP 0x018003c0 |
| 383 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
| 887e2ec9 | 384 | #else |
| 6d0f6bcf | 385 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
| 214398d9 | 386 | /* Memory Bank 3 (NOR-FLASH) initialization */ |
| 6d0f6bcf JCPV |
387 | #define CONFIG_SYS_EBC_PB3AP 0x03017200 |
| 388 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
| 887e2ec9 | 389 | |
| 214398d9 | 390 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
| 6d0f6bcf JCPV |
391 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
| 392 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
| 887e2ec9 SR |
393 | #endif |
| 394 | ||
| 214398d9 | 395 | /* Memory Bank 2 (CPLD) initialization */ |
| 6d0f6bcf JCPV |
396 | #define CONFIG_SYS_EBC_PB2AP 0x24814580 |
| 397 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000) | |
| 887e2ec9 | 398 | |
| 6d0f6bcf | 399 | #define CONFIG_SYS_BCSR5_PCI66EN 0x80 |
| 5a5958b7 | 400 | |
| 214398d9 | 401 | /* |
| 43a2b0e7 | 402 | * NAND FLASH |
| 214398d9 | 403 | */ |
| 6d0f6bcf | 404 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 6d0f6bcf JCPV |
405 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
| 406 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
| 43a2b0e7 | 407 | |
| 214398d9 | 408 | /* |
| b05e8bf5 LJ |
409 | * PPC440 GPIO Configuration |
| 410 | */ | |
| 411 | /* test-only: take GPIO init from pcs440ep ???? in config file */ | |
| 6d0f6bcf | 412 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| b05e8bf5 LJ |
413 | { \ |
| 414 | /* GPIO Core 0 */ \ | |
| 415 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
| 416 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
| 417 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
| 418 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
| 419 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
| 420 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
| 421 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
| 422 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
| 423 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
| 424 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
| 425 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
| 426 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
| 427 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
| 428 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
| 429 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \ | |
| 430 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ | |
| 431 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ | |
| 432 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ | |
| 433 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ | |
| 434 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ | |
| 435 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
| 436 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
| 437 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
| 438 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
| 439 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ | |
| 440 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ | |
| 441 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
| 442 | {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
| 443 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \ | |
| 444 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
| 445 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
| 446 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
| 447 | }, \ | |
| 448 | { \ | |
| 449 | /* GPIO Core 1 */ \ | |
| 450 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
| 451 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
| eab10073 SF |
452 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ |
| 453 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
| 454 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
| 455 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
| 456 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \ | |
| 457 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \ | |
| b05e8bf5 LJ |
458 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ |
| 459 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
| 460 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
| 461 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
| 462 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
| 463 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
| 464 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
| 465 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
| 466 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
| 467 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
| 468 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
| 469 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
| 470 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
| 471 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
| 472 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
| 473 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
| 474 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
| 475 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
| 476 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
| 477 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
| 478 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
| 479 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
| 480 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
| 481 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
| 482 | } \ | |
| 483 | } | |
| 484 | ||
| bc778812 AG |
485 | #ifdef CONFIG_VIDEO |
| 486 | #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ | |
| 487 | #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ | |
| 488 | #define VIDEO_IO_OFFSET 0xe8000000 | |
| 6d0f6bcf | 489 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| bc778812 AG |
490 | #define CONFIG_VIDEO_SW_CURSOR |
| 491 | #define CONFIG_VIDEO_LOGO | |
| 492 | #define CONFIG_CFB_CONSOLE | |
| 493 | #define CONFIG_SPLASH_SCREEN | |
| 494 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 495 | #define CONFIG_CMD_BMP | |
| 496 | #endif | |
| 497 | ||
| 214398d9 | 498 | #endif /* __CONFIG_H */ |