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1/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
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8#ifndef _TEGRA_COMMON_H_
9#define _TEGRA_COMMON_H_
1ace4022 10#include <linux/sizes.h>
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11#include <linux/stringify.h>
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
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17#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
18
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19#include <asm/arch/tegra.h> /* get chip and board defs */
20
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21/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
22#ifndef CONFIG_ARM64
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23#define CONFIG_SYS_TIMER_RATE 1000000
24#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
f41f0a19 25#endif
31df9893 26
f01b631f 27#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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28
29/* Environment */
30#define CONFIG_ENV_VARS_UBOOT_CONFIG
31#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
32
f01b631f 33/*
bfcf46db 34 * NS16550 Configuration
f01b631f 35 */
1874626b 36#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
f01b631f 37
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38/*
39 * Common HW configuration.
40 * If this varies between SoCs later, move to tegraNN-common.h
41 * Note: This is number of devices, not max device ID.
42 */
43#define CONFIG_SYS_MMC_MAX_DEVICE 4
44
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45/*
46 * select serial console configuration
47 */
48#define CONFIG_CONS_INDEX 1
49
50/* allow to overwrite serial and ethaddr */
51#define CONFIG_ENV_OVERWRITE
f01b631f 52
f01b631f 53/* turn on command-line edit/hist/auto */
f01b631f 54#define CONFIG_COMMAND_HISTORY
f01b631f 55
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56/*
57 * Increasing the size of the IO buffer as default nfsargs size is more
58 * than 256 and so it is not possible to edit it
59 */
64a4fe74 60#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
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61/* Print Buffer Size */
62#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
63 sizeof(CONFIG_SYS_PROMPT) + 16)
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64#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
65
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66/* Boot Argument Buffer Size */
67#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
68
69#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
70#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
71
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72/*-----------------------------------------------------------------------
73 * Physical Memory Map
74 */
bbc1b99e 75#define CONFIG_NR_DRAM_BANKS 2
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76#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
77#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
78
79#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
80#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
81
82#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
83
84#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
85#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
86#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
87 CONFIG_SYS_INIT_RAM_SIZE - \
88 GENERATED_GBL_DATA_SIZE)
89
f01b631f 90#define CONFIG_CMD_ENTERRCM
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91
92/* Defines for SPL */
f01b631f 93#define CONFIG_SPL_FRAMEWORK
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94#define CONFIG_SPL_BOARD_INIT
95#define CONFIG_SPL_NAND_SIMPLE
6ebc3461 96#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
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97 CONFIG_SPL_TEXT_BASE)
98#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
99
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100/* Misc utility code */
101#define CONFIG_BOUNCE_BUFFER
3efff99f 102#define CONFIG_CRC32_VERIFY
dd7f65f6 103
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104#ifndef CONFIG_SPL_BUILD
105#include <config_distro_defaults.h>
68295a48 106#define CONFIG_FAT_WRITE
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107#endif
108
f01b631f 109#endif /* _TEGRA_COMMON_H_ */