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f01b631f TW |
1 | /* |
2 | * (C) Copyright 2010-2012 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f01b631f TW |
6 | */ |
7 | ||
bfcf46db TW |
8 | #ifndef _TEGRA_COMMON_H_ |
9 | #define _TEGRA_COMMON_H_ | |
1ace4022 | 10 | #include <linux/sizes.h> |
f01b631f TW |
11 | #include <linux/stringify.h> |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ | |
f01b631f TW |
17 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
18 | ||
f01b631f TW |
19 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
20 | ||
f41f0a19 TR |
21 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
22 | #ifndef CONFIG_ARM64 | |
31df9893 RH |
23 | #define CONFIG_SYS_TIMER_RATE 1000000 |
24 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE | |
f41f0a19 | 25 | #endif |
31df9893 | 26 | |
f01b631f TW |
27 | /* |
28 | * Display CPU and Board information | |
29 | */ | |
30 | #define CONFIG_DISPLAY_CPUINFO | |
31 | #define CONFIG_DISPLAY_BOARDINFO | |
32 | ||
33 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
f01b631f TW |
34 | |
35 | /* Environment */ | |
36 | #define CONFIG_ENV_VARS_UBOOT_CONFIG | |
37 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ | |
38 | ||
f01b631f | 39 | /* |
bfcf46db | 40 | * NS16550 Configuration |
f01b631f | 41 | */ |
858530a8 | 42 | #define CONFIG_TEGRA_SERIAL |
858530a8 | 43 | #define CONFIG_SYS_NS16550 |
f01b631f | 44 | |
f175603f SW |
45 | /* |
46 | * Common HW configuration. | |
47 | * If this varies between SoCs later, move to tegraNN-common.h | |
48 | * Note: This is number of devices, not max device ID. | |
49 | */ | |
50 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 | |
51 | ||
f01b631f TW |
52 | /* |
53 | * select serial console configuration | |
54 | */ | |
55 | #define CONFIG_CONS_INDEX 1 | |
56 | ||
57 | /* allow to overwrite serial and ethaddr */ | |
58 | #define CONFIG_ENV_OVERWRITE | |
59 | #define CONFIG_BAUDRATE 115200 | |
60 | ||
f01b631f | 61 | /* turn on command-line edit/hist/auto */ |
f01b631f | 62 | #define CONFIG_COMMAND_HISTORY |
f01b631f | 63 | |
11d9c030 | 64 | /* turn on commonly used storage-related commands */ |
11d9c030 | 65 | #define CONFIG_PARTITION_UUIDS |
11d9c030 SW |
66 | #define CONFIG_CMD_PART |
67 | ||
f01b631f TW |
68 | #define CONFIG_SYS_NO_FLASH |
69 | ||
70 | #define CONFIG_CONSOLE_MUX | |
71 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
86bd20b0 SW |
72 | #ifndef CONFIG_SPL_BUILD |
73 | #define CONFIG_SYS_STDIO_DEREGISTER | |
74 | #endif | |
f01b631f | 75 | |
f01b631f TW |
76 | /* |
77 | * Increasing the size of the IO buffer as default nfsargs size is more | |
78 | * than 256 and so it is not possible to edit it | |
79 | */ | |
80 | #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ | |
81 | /* Print Buffer Size */ | |
82 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
83 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
0859b49d | 84 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
f01b631f TW |
85 | /* Boot Argument Buffer Size */ |
86 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
87 | ||
88 | #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) | |
89 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) | |
90 | ||
6527268d | 91 | #ifndef CONFIG_ARM64 |
9dacbb27 | 92 | #ifndef CONFIG_SPL_BUILD |
4270d5af | 93 | #define CONFIG_USE_ARCH_MEMCPY |
9dacbb27 | 94 | #endif |
6527268d | 95 | #endif |
4270d5af | 96 | |
f01b631f TW |
97 | /*----------------------------------------------------------------------- |
98 | * Physical Memory Map | |
99 | */ | |
bbc1b99e | 100 | #define CONFIG_NR_DRAM_BANKS 2 |
f01b631f TW |
101 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
102 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ | |
103 | ||
104 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE | |
105 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
106 | ||
107 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ | |
108 | ||
109 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE | |
110 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN | |
111 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
112 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
113 | GENERATED_GBL_DATA_SIZE) | |
114 | ||
115 | #define CONFIG_TEGRA_GPIO | |
116 | #define CONFIG_CMD_GPIO | |
117 | #define CONFIG_CMD_ENTERRCM | |
f01b631f TW |
118 | |
119 | /* Defines for SPL */ | |
f01b631f TW |
120 | #define CONFIG_SPL_FRAMEWORK |
121 | #define CONFIG_SPL_RAM_DEVICE | |
122 | #define CONFIG_SPL_BOARD_INIT | |
123 | #define CONFIG_SPL_NAND_SIMPLE | |
6ebc3461 | 124 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ |
f01b631f TW |
125 | CONFIG_SPL_TEXT_BASE) |
126 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 | |
127 | ||
128 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
129 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
130 | #define CONFIG_SPL_SERIAL_SUPPORT | |
131 | #define CONFIG_SPL_GPIO_SUPPORT | |
132 | ||
dd7f65f6 | 133 | #define CONFIG_SYS_GENERIC_BOARD |
026baff7 SW |
134 | #define CONFIG_BOARD_EARLY_INIT_F |
135 | #define CONFIG_BOARD_LATE_INIT | |
3efff99f | 136 | |
a885f852 SW |
137 | /* Misc utility code */ |
138 | #define CONFIG_BOUNCE_BUFFER | |
3efff99f | 139 | #define CONFIG_CRC32_VERIFY |
dd7f65f6 | 140 | |
68cf64db SW |
141 | #ifndef CONFIG_SPL_BUILD |
142 | #include <config_distro_defaults.h> | |
143 | #endif | |
144 | ||
f01b631f | 145 | #endif /* _TEGRA_COMMON_H_ */ |