[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#if defined(CONFIG_MACH_PH1_SLD3)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_NUM_CH2 1

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x20000000
#define CONFIG_SDRAM1_BASE	0xc0000000
#define CONFIG_SDRAM1_SIZE	0x20000000
#define CONFIG_SDRAM2_BASE	0xc0000000
#define CONFIG_SDRAM2_SIZE	0x10000000
#endif

#if defined(CONFIG_MACH_PH1_LD4)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x10000000
#define CONFIG_SDRAM1_BASE	0x90000000
#define CONFIG_SDRAM1_SIZE	0x10000000
#endif

#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x20000000
#define CONFIG_SDRAM1_BASE	0xa0000000
#define CONFIG_SDRAM1_SIZE	0x20000000
#endif

#if defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x10000000
#define CONFIG_SDRAM1_BASE	0x90000000
#define CONFIG_SDRAM1_SIZE	0x10000000
#endif

#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

/*
 * Support card address map
 */
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
# define CONFIG_SUPPORT_CARD_BASE	0x03f00000
# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00090000)
# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
#endif

#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
# define CONFIG_SUPPORT_CARD_BASE	0x08000000
# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00401630)
# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00200000)
#endif

#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK		12288000
#define CONFIG_SYS_NS16550_REG_SIZE	-2
#endif

/* TODO: move to Kconfig and device tree */
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif

#define CONFIG_SMC911X

#define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_CACHELINE_SIZE	32

/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

/*
 * uncomment the following to disable FLASH related code.
 */
/* #define CONFIG_SYS_NO_FLASH */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for out supoort card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2

/* serial console configuration */
#define CONFIG_BAUDRATE			115200

#define CONFIG_SYS_GENERIC_BOARD

#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE				0x2000
#define CONFIG_ENV_OFFSET			0x0
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000

/*
 * By default, ARP timeout is 5 sec.
 * The first ARP request does not seem to work.
 * So we need to retry ARP request anyway.
 * We want to shrink the interval until the second ARP request.
 */
#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */

#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_MACH_PH1_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

#define CONFIG_BOOTDELAY			3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	"tftpboot; bootm;"

#define CONFIG_BOOTARGS		" earlyprintk loglevel=8"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=run add_default_bootargs &&" \
		"bootm $fit_addr\0" \
	"nandboot=run add_default_bootargs &&" \
		"nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=run add_default_bootargs &&" \
		"tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0"
#else
#define CONFIG_BOOTFILE			"uImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
	"kernel_addr=0x00200000\0" \
	"kernel_addr_r=0x84200000\0" \
	"kernel_size=0x00800000\0" \
	"ramdisk_addr=0x00a00000\0" \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"norboot=run add_default_bootargs &&" \
		"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
	"nandboot=run add_default_bootargs &&" \
		"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"tftpboot=run add_default_bootargs &&" \
		"tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot u-boot-spl.bin &&"			\
		"nand write $loadaddr 0 0x00010000 &&"		\
		"tftpboot u-boot-dtb.img &&"			\
		"nand write $loadaddr 0x00010000 0x000f0000\0"	\
	"add_default_bootargs=setenv bootargs $bootargs"	\
		" console=ttyS0,$baudrate\0"			\
	LINUXBOOT_ENV_SETTINGS

/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT

#define CONFIG_HAVE_ARM_SECURE

/* Memory Size & Mapping */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SDRAM0_BASE

#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
/* Thre is no memory hole */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
#else
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE)
#endif

#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
	defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#define CONFIG_SPL_STACK		(0x0ff08000)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT

#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000

#define CONFIG_SPL_MAX_FOOTPRINT		0x10000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
f8f35944	2	* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	/* U-boot - Common settings for UniPhier Family */
	8
	9	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	10	#define __CONFIG_UNIPHIER_COMMON_H__
	11
3365b4eb	12	#if defined(CONFIG_MACH_PH1_SLD3)
f5d0b9b2	13	#define CONFIG_DDR_NUM_CH0 2
3365b4eb MY	14	#define CONFIG_DDR_NUM_CH1 1
3365b4eb MY	15	#define CONFIG_DDR_NUM_CH2 1
f5d0b9b2 MY	16
	17	/* Physical start address of SDRAM */
	18	#define CONFIG_SDRAM0_BASE 0x80000000
	19	#define CONFIG_SDRAM0_SIZE 0x20000000
3365b4eb	20	#define CONFIG_SDRAM1_BASE 0xc0000000
f5d0b9b2	21	#define CONFIG_SDRAM1_SIZE 0x20000000
3365b4eb MY	22	#define CONFIG_SDRAM2_BASE 0xc0000000
3365b4eb MY	23	#define CONFIG_SDRAM2_SIZE 0x10000000
f5d0b9b2 MY	24	#endif
	25
	26	#if defined(CONFIG_MACH_PH1_LD4)
	27	#define CONFIG_DDR_NUM_CH0 1
	28	#define CONFIG_DDR_NUM_CH1 1
	29
	30	/* Physical start address of SDRAM */
	31	#define CONFIG_SDRAM0_BASE 0x80000000
	32	#define CONFIG_SDRAM0_SIZE 0x10000000
	33	#define CONFIG_SDRAM1_BASE 0x90000000
	34	#define CONFIG_SDRAM1_SIZE 0x10000000
	35	#endif
	36
3365b4eb MY	37	#if defined(CONFIG_MACH_PH1_PRO4)
	38	#define CONFIG_DDR_NUM_CH0 2
	39	#define CONFIG_DDR_NUM_CH1 2
	40
	41	/* Physical start address of SDRAM */
	42	#define CONFIG_SDRAM0_BASE 0x80000000
	43	#define CONFIG_SDRAM0_SIZE 0x20000000
	44	#define CONFIG_SDRAM1_BASE 0xa0000000
	45	#define CONFIG_SDRAM1_SIZE 0x20000000
	46	#endif
	47
f5d0b9b2 MY	48	#if defined(CONFIG_MACH_PH1_SLD8)
	49	#define CONFIG_DDR_NUM_CH0 1
	50	#define CONFIG_DDR_NUM_CH1 1
	51
	52	/* Physical start address of SDRAM */
	53	#define CONFIG_SDRAM0_BASE 0x80000000
	54	#define CONFIG_SDRAM0_SIZE 0x10000000
	55	#define CONFIG_SDRAM1_BASE 0x90000000
	56	#define CONFIG_SDRAM1_SIZE 0x10000000
	57	#endif
	58
233e42a9 MY	59	#define CONFIG_I2C_EEPROM
	60	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	61
5894ca00 MY	62	/*
	63	* Support card address map
	64	*/
	65	#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
	66	# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
	67	# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
	68	# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
	69	# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
	70	#endif
	71
	72	#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
	73	# define CONFIG_SUPPORT_CARD_BASE 0x08000000
	74	# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
	75	# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
	76	# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
	77	#endif
	78
d064cbff	79	#ifdef CONFIG_SYS_NS16550_SERIAL
5894ca00 MY	80	#define CONFIG_SYS_NS16550
	81	#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
	82	#define CONFIG_SYS_NS16550_CLK 12288000
	83	#define CONFIG_SYS_NS16550_REG_SIZE -2
d064cbff	84	#endif
5894ca00	85
f5d0b9b2 MY	86	/* TODO: move to Kconfig and device tree */
	87	#if 0
	88	#define CONFIG_SYS_NS16550_SERIAL
	89	#endif
	90
	91	#define CONFIG_SMC911X
	92
5894ca00 MY	93	#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
	94	#define CONFIG_SMC911X_32_BIT
	95
5894ca00 MY	96	/*-----------------------------------------------------------------------
	97	* MMU and Cache Setting
	98	----------------------------------------------------------------------/
	99
	100	/* Comment out the following to enable L1 cache */
	101	/* #define CONFIG_SYS_ICACHE_OFF */
	102	/* #define CONFIG_SYS_DCACHE_OFF */
	103
53c45d4e MY	104	#define CONFIG_SYS_CACHELINE_SIZE 32
53c45d4e MY	105
5894ca00 MY	106	/* Comment out the following to enable L2 cache */
	107	#define CONFIG_UNIPHIER_L2CACHE_ON
	108
	109	#define CONFIG_DISPLAY_CPUINFO
	110	#define CONFIG_DISPLAY_BOARDINFO
08fda258	111	#define CONFIG_MISC_INIT_F
84ccd791	112	#define CONFIG_BOARD_EARLY_INIT_F
7a3620b2	113	#define CONFIG_BOARD_EARLY_INIT_R
5894ca00 MY	114	#define CONFIG_BOARD_LATE_INIT
	115
	116	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	117
	118	#define CONFIG_TIMESTAMP
	119
	120	/* FLASH related */
	121	#define CONFIG_MTD_DEVICE
	122
	123	/*
	124	* uncomment the following to disable FLASH related code.
	125	*/
	126	/* #define CONFIG_SYS_NO_FLASH */
	127
	128	#define CONFIG_FLASH_CFI_DRIVER
	129	#define CONFIG_SYS_FLASH_CFI
	130
	131	#define CONFIG_SYS_MAX_FLASH_SECT 256
	132	#define CONFIG_SYS_MONITOR_BASE 0
	133	#define CONFIG_SYS_FLASH_BASE 0
	134
	135	/*
	136	* flash_toggle does not work for out supoort card.
	137	* We need to use flash_status_poll.
	138	*/
	139	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	140
	141	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	142
7a3620b2	143	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
5894ca00 MY	144
	145	/* serial console configuration */
	146	#define CONFIG_BAUDRATE 115200
	147
	148	#define CONFIG_SYS_GENERIC_BOARD
	149
	150	#if !defined(CONFIG_SPL_BUILD)
	151	#define CONFIG_USE_ARCH_MEMSET
	152	#define CONFIG_USE_ARCH_MEMCPY
	153	#endif
	154
	155	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	156
	157	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	158	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	159	/* Print Buffer Size */
	160	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	161	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	162	/* Boot Argument Buffer Size */
	163	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	164
	165	#define CONFIG_CONS_INDEX 1
	166
	167	/*
	168	* For NAND booting the environment is embedded in the U-Boot image. Please take
	169	* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
	170	*/
	171	/* #define CONFIG_ENV_IS_IN_NAND */
	172	#define CONFIG_ENV_IS_NOWHERE
	173	#define CONFIG_ENV_SIZE 0x2000
	174	#define CONFIG_ENV_OFFSET 0x0
	175	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
	176
	177	/* Time clock 1MHz */
	178	#define CONFIG_SYS_TIMER_RATE 1000000
	179
	180	/*
	181	* By default, ARP timeout is 5 sec.
	182	* The first ARP request does not seem to work.
	183	* So we need to retry ARP request anyway.
	184	* We want to shrink the interval until the second ARP request.
	185	*/
	186	#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
	187
5894ca00 MY	188	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	189	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	190	#define CONFIG_SYS_NAND_ONFI_DETECTION
	191
	192	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	193
3365b4eb MY	194	#ifdef CONFIG_MACH_PH1_SLD3
	195	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	196	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	197	#else
5894ca00 MY	198	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	199	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	200	#endif
5894ca00 MY	201
	202	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	203
	204	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	205	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	206
495deb44	207	/* USB */
495deb44	208	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
53c45d4e	209	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44 MY	210	#define CONFIG_CMD_FAT
	211	#define CONFIG_FAT_WRITE
	212	#define CONFIG_DOS_PARTITION
	213
5894ca00 MY	214	/* memtest works on */
	215	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	216	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	217
	218	#define CONFIG_BOOTDELAY 3
	219	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
5894ca00 MY	220
	221	/*
	222	* Network Configuration
	223	*/
5894ca00 MY	224	#define CONFIG_SERVERIP 192.168.11.1
	225	#define CONFIG_IPADDR 192.168.11.10
	226	#define CONFIG_GATEWAYIP 192.168.11.1
	227	#define CONFIG_NETMASK 255.255.255.0
	228
	229	#define CONFIG_LOADADDR 0x84000000
	230	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	231
	232	#define CONFIG_CMDLINE_EDITING /* add command line history */
	233
	234	#define CONFIG_BOOTCOMMAND "run $bootmode"
	235
	236	#define CONFIG_ROOTPATH "/nfs/root/path"
	237	#define CONFIG_NFSBOOTCOMMAND \
	238	"setenv bootargs $bootargs root=/dev/nfs rw " \
	239	"nfsroot=$serverip:$rootpath " \
	240	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	241	"tftpboot; bootm;"
	242
ad6670ee	243	#define CONFIG_BOOTARGS " earlyprintk loglevel=8"
5894ca00	244
421376ae MY	245	#ifdef CONFIG_FIT
	246	#define CONFIG_BOOTFILE "fitImage"
	247	#define LINUXBOOT_ENV_SETTINGS \
	248	"fit_addr=0x00100000\0" \
	249	"fit_addr_r=0x84100000\0" \
	250	"fit_size=0x00f00000\0" \
	251	"norboot=run add_default_bootargs &&" \
	252	"bootm $fit_addr\0" \
	253	"nandboot=run add_default_bootargs &&" \
	254	"nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c MY	255	"bootm $fit_addr_r\0" \
	256	"tftpboot=run add_default_bootargs &&" \
	257	"tftpboot $fit_addr_r $bootfile &&" \
421376ae MY	258	"bootm $fit_addr_r\0"
	259	#else
	260	#define CONFIG_BOOTFILE "uImage"
	261	#define LINUXBOOT_ENV_SETTINGS \
	262	"fdt_addr=0x00100000\0" \
	263	"fdt_addr_r=0x84100000\0" \
	264	"fdt_size=0x00008000\0" \
e037db0c	265	"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
421376ae MY	266	"kernel_addr=0x00200000\0" \
	267	"kernel_addr_r=0x84200000\0" \
	268	"kernel_size=0x00800000\0" \
	269	"ramdisk_addr=0x00a00000\0" \
	270	"ramdisk_addr_r=0x84a00000\0" \
	271	"ramdisk_size=0x00600000\0" \
e037db0c	272	"ramdisk_file=rootfs.cpio.uboot\0" \
421376ae MY	273	"norboot=run add_default_bootargs &&" \
	274	"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
	275	"nandboot=run add_default_bootargs &&" \
	276	"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
	277	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
	278	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
e037db0c MY	279	"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	280	"tftpboot=run add_default_bootargs &&" \
	281	"tftpboot $kernel_addr_r $bootfile &&" \
	282	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
	283	"tftpboot $fdt_addr_r $fdt_file &&" \
421376ae MY	284	"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
	285	#endif
	286
	287	#define CONFIG_EXTRA_ENV_SETTINGS \
	288	"netdev=eth0\0" \
	289	"verify=n\0" \
	290	"nandupdate=nand erase 0 0x00100000 &&" \
	291	"tftpboot u-boot-spl.bin &&" \
	292	"nand write $loadaddr 0 0x00010000 &&" \
	293	"tftpboot u-boot-dtb.img &&" \
	294	"nand write $loadaddr 0x00010000 0x000f0000\0" \
	295	"add_default_bootargs=setenv bootargs $bootargs" \
	296	" console=ttyS0,$baudrate\0" \
	297	LINUXBOOT_ENV_SETTINGS
5894ca00	298
5894ca00 MY	299	/* Open Firmware flat tree */
	300	#define CONFIG_OF_LIBFDT
	301
	302	#define CONFIG_HAVE_ARM_SECURE
	303
	304	/* Memory Size & Mapping */
	305	#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
	306
	307	#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
	308	/* Thre is no memory hole */
	309	#define CONFIG_NR_DRAM_BANKS 1
	310	#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
	311	#else
	312	#define CONFIG_NR_DRAM_BANKS 2
	313	#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
	314	#endif
	315
3365b4eb MY	316	#if defined(CONFIG_MACH_PH1_SLD3) \|\| defined(CONFIG_MACH_PH1_LD4) \|\| \
3365b4eb MY	317	defined(CONFIG_MACH_PH1_SLD8)
f5d0b9b2 MY	318	#define CONFIG_SPL_TEXT_BASE 0x00040000
	319	#endif
	320	#if defined(CONFIG_MACH_PH1_PRO4)
	321	#define CONFIG_SPL_TEXT_BASE 0x00100000
	322	#endif
	323
ce3a6390	324	#define CONFIG_SPL_STACK (0x0ff08000)
8cddc279	325	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
5894ca00	326
a286039b MY	327	#define CONFIG_PANIC_HANG
a286039b MY	328
5894ca00	329	#define CONFIG_SPL_FRAMEWORK
499785b9	330	#define CONFIG_SPL_SERIAL_SUPPORT
5894ca00 MY	331	#define CONFIG_SPL_NAND_SUPPORT
	332
	333	#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
	334	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	335
	336	#define CONFIG_SPL_BOARD_INIT
	337
	338	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
	339
6a3cffe8 MY	340	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
6a3cffe8 MY	341
5894ca00	342	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */