[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#if defined(CONFIG_MACH_PH1_SLD3)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_NUM_CH2 1

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x20000000
#define CONFIG_SDRAM1_BASE	0xc0000000
#define CONFIG_SDRAM1_SIZE	0x20000000
#define CONFIG_SDRAM2_BASE	0xc0000000
#define CONFIG_SDRAM2_SIZE	0x10000000
#endif

#if defined(CONFIG_MACH_PH1_LD4)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x10000000
#define CONFIG_SDRAM1_BASE	0x90000000
#define CONFIG_SDRAM1_SIZE	0x10000000
#endif

#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x20000000
#define CONFIG_SDRAM1_BASE	0xa0000000
#define CONFIG_SDRAM1_SIZE	0x20000000
#endif

#if defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1

/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE	0x80000000
#define CONFIG_SDRAM0_SIZE	0x10000000
#define CONFIG_SDRAM1_BASE	0x90000000
#define CONFIG_SDRAM1_SIZE	0x10000000
#endif

#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

/*
 * Support card address map
 */
#define CONFIG_SUPPORT_CARD_BASE	0x43f00000
#define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
#define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00090000)
#define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x000b0000)

#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK		12288000
#define CONFIG_SYS_NS16550_REG_SIZE	-2
#endif

/* TODO: move to Kconfig and device tree */
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif

#define CONFIG_SMC911X

#define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_CACHELINE_SIZE	32

/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

/*
 * uncomment the following to disable FLASH related code.
 */
/* #define CONFIG_SYS_NO_FLASH */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for out supoort card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1

/* serial console configuration */
#define CONFIG_BAUDRATE			115200

#define CONFIG_SYS_GENERIC_BOARD

#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE				0x2000
#define CONFIG_ENV_OFFSET			0x0
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000

/*
 * By default, ARP timeout is 5 sec.
 * The first ARP request does not seem to work.
 * So we need to retry ARP request anyway.
 * We want to shrink the interval until the second ARP request.
 */
#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */

#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_MACH_PH1_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

#define CONFIG_BOOTDELAY			3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	"tftpboot; bootm;"

#define CONFIG_BOOTARGS		" earlyprintk loglevel=8"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=run add_default_bootargs &&" \
		"setexpr fit_addr $nor_base + $fit_addr &&" \
		"bootm $fit_addr\0" \
	"nandboot=run add_default_bootargs &&" \
		"nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=run add_default_bootargs &&" \
		"tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0"
#else
#define CONFIG_BOOTFILE			"uImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
	"kernel_addr=0x00200000\0" \
	"kernel_addr_r=0x84200000\0" \
	"kernel_size=0x00800000\0" \
	"ramdisk_addr=0x00a00000\0" \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"norboot=run add_default_bootargs &&" \
		"setexpr kernel_addr $nor_base + $kernel_addr &&" \
		"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
		"setexpr fdt_addr $nor_base + $fdt_addr &&" \
		"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
	"nandboot=run add_default_bootargs &&" \
		"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"tftpboot=run add_default_bootargs &&" \
		"tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"norbase=0x42000000\0"					\
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot u-boot-spl-dtb.bin &&"		\
		"nand write $loadaddr 0 0x00010000 &&"		\
		"tftpboot u-boot-dtb.img &&"			\
		"nand write $loadaddr 0x00010000 0x000f0000\0"	\
	"add_default_bootargs=setenv bootargs $bootargs"	\
		" console=ttyS0,$baudrate\0"			\
	LINUXBOOT_ENV_SETTINGS

/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT

/* Memory Size & Mapping */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SDRAM0_BASE

#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
/* Thre is no memory hole */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
#else
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE)
#endif

#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
	defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#define CONFIG_SPL_STACK		(0x0ff08000)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT

#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000

#define CONFIG_SPL_MAX_FOOTPRINT		0x10000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
f8f35944	2	* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	/* U-boot - Common settings for UniPhier Family */
	8
	9	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	10	#define __CONFIG_UNIPHIER_COMMON_H__
	11
3365b4eb	12	#if defined(CONFIG_MACH_PH1_SLD3)
f5d0b9b2	13	#define CONFIG_DDR_NUM_CH0 2
3365b4eb MY	14	#define CONFIG_DDR_NUM_CH1 1
3365b4eb MY	15	#define CONFIG_DDR_NUM_CH2 1
f5d0b9b2 MY	16
	17	/* Physical start address of SDRAM */
	18	#define CONFIG_SDRAM0_BASE 0x80000000
	19	#define CONFIG_SDRAM0_SIZE 0x20000000
3365b4eb	20	#define CONFIG_SDRAM1_BASE 0xc0000000
f5d0b9b2	21	#define CONFIG_SDRAM1_SIZE 0x20000000
3365b4eb MY	22	#define CONFIG_SDRAM2_BASE 0xc0000000
3365b4eb MY	23	#define CONFIG_SDRAM2_SIZE 0x10000000
f5d0b9b2 MY	24	#endif
	25
	26	#if defined(CONFIG_MACH_PH1_LD4)
	27	#define CONFIG_DDR_NUM_CH0 1
	28	#define CONFIG_DDR_NUM_CH1 1
	29
	30	/* Physical start address of SDRAM */
	31	#define CONFIG_SDRAM0_BASE 0x80000000
	32	#define CONFIG_SDRAM0_SIZE 0x10000000
	33	#define CONFIG_SDRAM1_BASE 0x90000000
	34	#define CONFIG_SDRAM1_SIZE 0x10000000
	35	#endif
	36
3365b4eb MY	37	#if defined(CONFIG_MACH_PH1_PRO4)
	38	#define CONFIG_DDR_NUM_CH0 2
	39	#define CONFIG_DDR_NUM_CH1 2
	40
	41	/* Physical start address of SDRAM */
	42	#define CONFIG_SDRAM0_BASE 0x80000000
	43	#define CONFIG_SDRAM0_SIZE 0x20000000
	44	#define CONFIG_SDRAM1_BASE 0xa0000000
	45	#define CONFIG_SDRAM1_SIZE 0x20000000
	46	#endif
	47
f5d0b9b2 MY	48	#if defined(CONFIG_MACH_PH1_SLD8)
	49	#define CONFIG_DDR_NUM_CH0 1
	50	#define CONFIG_DDR_NUM_CH1 1
	51
	52	/* Physical start address of SDRAM */
	53	#define CONFIG_SDRAM0_BASE 0x80000000
	54	#define CONFIG_SDRAM0_SIZE 0x10000000
	55	#define CONFIG_SDRAM1_BASE 0x90000000
	56	#define CONFIG_SDRAM1_SIZE 0x10000000
	57	#endif
	58
233e42a9 MY	59	#define CONFIG_I2C_EEPROM
	60	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	61
5894ca00 MY	62	/*
	63	* Support card address map
	64	*/
d5ed8c57	65	#define CONFIG_SUPPORT_CARD_BASE 0x43f00000
9879842c MY	66	#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
	67	#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
	68	#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
5894ca00	69
d064cbff	70	#ifdef CONFIG_SYS_NS16550_SERIAL
5894ca00 MY	71	#define CONFIG_SYS_NS16550
	72	#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
	73	#define CONFIG_SYS_NS16550_CLK 12288000
	74	#define CONFIG_SYS_NS16550_REG_SIZE -2
d064cbff	75	#endif
5894ca00	76
f5d0b9b2 MY	77	/* TODO: move to Kconfig and device tree */
	78	#if 0
	79	#define CONFIG_SYS_NS16550_SERIAL
	80	#endif
	81
	82	#define CONFIG_SMC911X
	83
5894ca00 MY	84	#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
	85	#define CONFIG_SMC911X_32_BIT
	86
5894ca00 MY	87	/*-----------------------------------------------------------------------
	88	* MMU and Cache Setting
	89	----------------------------------------------------------------------/
	90
	91	/* Comment out the following to enable L1 cache */
	92	/* #define CONFIG_SYS_ICACHE_OFF */
	93	/* #define CONFIG_SYS_DCACHE_OFF */
	94
53c45d4e MY	95	#define CONFIG_SYS_CACHELINE_SIZE 32
53c45d4e MY	96
5894ca00 MY	97	/* Comment out the following to enable L2 cache */
	98	#define CONFIG_UNIPHIER_L2CACHE_ON
	99
	100	#define CONFIG_DISPLAY_CPUINFO
	101	#define CONFIG_DISPLAY_BOARDINFO
08fda258	102	#define CONFIG_MISC_INIT_F
84ccd791	103	#define CONFIG_BOARD_EARLY_INIT_F
7a3620b2	104	#define CONFIG_BOARD_EARLY_INIT_R
5894ca00 MY	105	#define CONFIG_BOARD_LATE_INIT
	106
	107	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	108
	109	#define CONFIG_TIMESTAMP
	110
	111	/* FLASH related */
	112	#define CONFIG_MTD_DEVICE
	113
	114	/*
	115	* uncomment the following to disable FLASH related code.
	116	*/
	117	/* #define CONFIG_SYS_NO_FLASH */
	118
	119	#define CONFIG_FLASH_CFI_DRIVER
	120	#define CONFIG_SYS_FLASH_CFI
	121
	122	#define CONFIG_SYS_MAX_FLASH_SECT 256
	123	#define CONFIG_SYS_MONITOR_BASE 0
	124	#define CONFIG_SYS_FLASH_BASE 0
	125
	126	/*
	127	* flash_toggle does not work for out supoort card.
	128	* We need to use flash_status_poll.
	129	*/
	130	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	131
	132	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	133
9879842c	134	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
5894ca00 MY	135
	136	/* serial console configuration */
	137	#define CONFIG_BAUDRATE 115200
	138
	139	#define CONFIG_SYS_GENERIC_BOARD
	140
	141	#if !defined(CONFIG_SPL_BUILD)
	142	#define CONFIG_USE_ARCH_MEMSET
	143	#define CONFIG_USE_ARCH_MEMCPY
	144	#endif
	145
	146	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	147
	148	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	149	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	150	/* Print Buffer Size */
	151	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	152	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	153	/* Boot Argument Buffer Size */
	154	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	155
	156	#define CONFIG_CONS_INDEX 1
	157
	158	/*
	159	* For NAND booting the environment is embedded in the U-Boot image. Please take
	160	* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
	161	*/
	162	/* #define CONFIG_ENV_IS_IN_NAND */
	163	#define CONFIG_ENV_IS_NOWHERE
	164	#define CONFIG_ENV_SIZE 0x2000
	165	#define CONFIG_ENV_OFFSET 0x0
	166	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
	167
	168	/* Time clock 1MHz */
	169	#define CONFIG_SYS_TIMER_RATE 1000000
	170
	171	/*
	172	* By default, ARP timeout is 5 sec.
	173	* The first ARP request does not seem to work.
	174	* So we need to retry ARP request anyway.
	175	* We want to shrink the interval until the second ARP request.
	176	*/
	177	#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
	178
5894ca00 MY	179	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	180	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	181	#define CONFIG_SYS_NAND_ONFI_DETECTION
	182
	183	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	184
3365b4eb MY	185	#ifdef CONFIG_MACH_PH1_SLD3
	186	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	187	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	188	#else
5894ca00 MY	189	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	190	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	191	#endif
5894ca00 MY	192
	193	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	194
	195	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	196	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	197
495deb44	198	/* USB */
495deb44	199	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
53c45d4e	200	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44 MY	201	#define CONFIG_CMD_FAT
	202	#define CONFIG_FAT_WRITE
	203	#define CONFIG_DOS_PARTITION
	204
5894ca00 MY	205	/* memtest works on */
	206	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	207	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	208
	209	#define CONFIG_BOOTDELAY 3
	210	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
5894ca00 MY	211
	212	/*
	213	* Network Configuration
	214	*/
5894ca00 MY	215	#define CONFIG_SERVERIP 192.168.11.1
	216	#define CONFIG_IPADDR 192.168.11.10
	217	#define CONFIG_GATEWAYIP 192.168.11.1
	218	#define CONFIG_NETMASK 255.255.255.0
	219
	220	#define CONFIG_LOADADDR 0x84000000
	221	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	222
	223	#define CONFIG_CMDLINE_EDITING /* add command line history */
	224
	225	#define CONFIG_BOOTCOMMAND "run $bootmode"
	226
	227	#define CONFIG_ROOTPATH "/nfs/root/path"
	228	#define CONFIG_NFSBOOTCOMMAND \
	229	"setenv bootargs $bootargs root=/dev/nfs rw " \
	230	"nfsroot=$serverip:$rootpath " \
	231	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	232	"tftpboot; bootm;"
	233
ad6670ee	234	#define CONFIG_BOOTARGS " earlyprintk loglevel=8"
5894ca00	235
421376ae MY	236	#ifdef CONFIG_FIT
	237	#define CONFIG_BOOTFILE "fitImage"
	238	#define LINUXBOOT_ENV_SETTINGS \
	239	"fit_addr=0x00100000\0" \
	240	"fit_addr_r=0x84100000\0" \
	241	"fit_size=0x00f00000\0" \
	242	"norboot=run add_default_bootargs &&" \
d5ed8c57	243	"setexpr fit_addr $nor_base + $fit_addr &&" \
421376ae MY	244	"bootm $fit_addr\0" \
	245	"nandboot=run add_default_bootargs &&" \
	246	"nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c MY	247	"bootm $fit_addr_r\0" \
	248	"tftpboot=run add_default_bootargs &&" \
	249	"tftpboot $fit_addr_r $bootfile &&" \
421376ae MY	250	"bootm $fit_addr_r\0"
	251	#else
	252	#define CONFIG_BOOTFILE "uImage"
	253	#define LINUXBOOT_ENV_SETTINGS \
	254	"fdt_addr=0x00100000\0" \
	255	"fdt_addr_r=0x84100000\0" \
	256	"fdt_size=0x00008000\0" \
e037db0c	257	"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
421376ae MY	258	"kernel_addr=0x00200000\0" \
	259	"kernel_addr_r=0x84200000\0" \
	260	"kernel_size=0x00800000\0" \
	261	"ramdisk_addr=0x00a00000\0" \
	262	"ramdisk_addr_r=0x84a00000\0" \
	263	"ramdisk_size=0x00600000\0" \
e037db0c	264	"ramdisk_file=rootfs.cpio.uboot\0" \
421376ae	265	"norboot=run add_default_bootargs &&" \
d5ed8c57 MY	266	"setexpr kernel_addr $nor_base + $kernel_addr &&" \
	267	"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
	268	"setexpr fdt_addr $nor_base + $fdt_addr &&" \
421376ae MY	269	"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
	270	"nandboot=run add_default_bootargs &&" \
	271	"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
	272	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
	273	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
e037db0c MY	274	"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	275	"tftpboot=run add_default_bootargs &&" \
	276	"tftpboot $kernel_addr_r $bootfile &&" \
	277	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
	278	"tftpboot $fdt_addr_r $fdt_file &&" \
421376ae MY	279	"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
	280	#endif
	281
	282	#define CONFIG_EXTRA_ENV_SETTINGS \
	283	"netdev=eth0\0" \
	284	"verify=n\0" \
d5ed8c57	285	"norbase=0x42000000\0" \
421376ae	286	"nandupdate=nand erase 0 0x00100000 &&" \
f4e190e3	287	"tftpboot u-boot-spl-dtb.bin &&" \
421376ae MY	288	"nand write $loadaddr 0 0x00010000 &&" \
	289	"tftpboot u-boot-dtb.img &&" \
	290	"nand write $loadaddr 0x00010000 0x000f0000\0" \
	291	"add_default_bootargs=setenv bootargs $bootargs" \
	292	" console=ttyS0,$baudrate\0" \
	293	LINUXBOOT_ENV_SETTINGS
5894ca00	294
5894ca00 MY	295	/* Open Firmware flat tree */
	296	#define CONFIG_OF_LIBFDT
	297
5894ca00 MY	298	/* Memory Size & Mapping */
	299	#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
	300
	301	#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
	302	/* Thre is no memory hole */
	303	#define CONFIG_NR_DRAM_BANKS 1
	304	#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
	305	#else
	306	#define CONFIG_NR_DRAM_BANKS 2
	307	#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
	308	#endif
	309
3365b4eb MY	310	#if defined(CONFIG_MACH_PH1_SLD3) \|\| defined(CONFIG_MACH_PH1_LD4) \|\| \
3365b4eb MY	311	defined(CONFIG_MACH_PH1_SLD8)
f5d0b9b2 MY	312	#define CONFIG_SPL_TEXT_BASE 0x00040000
	313	#endif
	314	#if defined(CONFIG_MACH_PH1_PRO4)
	315	#define CONFIG_SPL_TEXT_BASE 0x00100000
	316	#endif
	317
ce3a6390	318	#define CONFIG_SPL_STACK (0x0ff08000)
8cddc279	319	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
5894ca00	320
a286039b MY	321	#define CONFIG_PANIC_HANG
a286039b MY	322
5894ca00	323	#define CONFIG_SPL_FRAMEWORK
499785b9	324	#define CONFIG_SPL_SERIAL_SUPPORT
5894ca00 MY	325	#define CONFIG_SPL_NAND_SUPPORT
	326
	327	#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
	328	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	329
	330	#define CONFIG_SPL_BOARD_INIT
	331
	332	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
	333
6a3cffe8 MY	334	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
6a3cffe8 MY	335
5894ca00	336	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */