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12916829 DF |
1 | /* |
2 | * Configuration for Versatile Express. Parts were derived from other ARM | |
3 | * configurations. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __VEXPRESS_AEMV8A_H | |
9 | #define __VEXPRESS_AEMV8A_H | |
10 | ||
f91afc4d | 11 | #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
261d2760 | 12 | #ifndef CONFIG_SEMIHOSTING |
f91afc4d | 13 | #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING |
261d2760 | 14 | #endif |
261d2760 DR |
15 | #define CONFIG_ARMV8_SWITCH_TO_EL1 |
16 | #endif | |
17 | ||
12916829 DF |
18 | #define CONFIG_REMAKE_ELF |
19 | ||
12916829 DF |
20 | #define CONFIG_SUPPORT_RAW_INITRD |
21 | ||
22 | /* Cache Definitions */ | |
23 | #define CONFIG_SYS_DCACHE_OFF | |
24 | #define CONFIG_SYS_ICACHE_OFF | |
25 | ||
26 | #define CONFIG_IDENT_STRING " vexpress_aemv8a" | |
27 | #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" | |
28 | ||
29 | /* Link Definitions */ | |
fc04b923 RH |
30 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ |
31 | defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) | |
261d2760 DR |
32 | /* ATF loads u-boot here for BASE_FVP model */ |
33 | #define CONFIG_SYS_TEXT_BASE 0x88000000 | |
34 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) | |
ffc10373 LW |
35 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
36 | #define CONFIG_SYS_TEXT_BASE 0xe0000000 | |
37 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) | |
261d2760 | 38 | #else |
03314f0e | 39 | #error "Unknown board variant" |
261d2760 | 40 | #endif |
12916829 | 41 | |
0d3012af RH |
42 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
43 | ||
12916829 DF |
44 | /* Flat Device Tree Definitions */ |
45 | #define CONFIG_OF_LIBFDT | |
46 | ||
12916829 DF |
47 | /* CS register bases for the original memory map. */ |
48 | #define V2M_PA_CS0 0x00000000 | |
49 | #define V2M_PA_CS1 0x14000000 | |
50 | #define V2M_PA_CS2 0x18000000 | |
51 | #define V2M_PA_CS3 0x1c000000 | |
52 | #define V2M_PA_CS4 0x0c000000 | |
53 | #define V2M_PA_CS5 0x10000000 | |
54 | ||
55 | #define V2M_PERIPH_OFFSET(x) (x << 16) | |
56 | #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) | |
57 | #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) | |
58 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) | |
59 | ||
60 | #define V2M_BASE 0x80000000 | |
61 | ||
12916829 DF |
62 | /* Common peripherals relative to CS7. */ |
63 | #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) | |
64 | #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) | |
65 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) | |
66 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) | |
67 | ||
ffc10373 LW |
68 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
69 | #define V2M_UART0 0x7ff80000 | |
70 | #define V2M_UART1 0x7ff70000 | |
71 | #else /* Not Juno */ | |
12916829 DF |
72 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
73 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) | |
74 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) | |
75 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) | |
ffc10373 | 76 | #endif |
12916829 DF |
77 | |
78 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) | |
79 | ||
80 | #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) | |
81 | #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) | |
82 | ||
83 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) | |
84 | #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) | |
85 | ||
86 | #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) | |
87 | ||
88 | #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) | |
89 | ||
90 | /* System register offsets. */ | |
91 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) | |
92 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) | |
93 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) | |
94 | ||
95 | /* Generic Timer Definitions */ | |
96 | #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ | |
97 | ||
98 | /* Generic Interrupt Controller Definitions */ | |
c71645ad DF |
99 | #ifdef CONFIG_GICV3 |
100 | #define GICD_BASE (0x2f000000) | |
101 | #define GICR_BASE (0x2f100000) | |
102 | #else | |
261d2760 | 103 | |
fc04b923 RH |
104 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ |
105 | defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) | |
261d2760 DR |
106 | #define GICD_BASE (0x2f000000) |
107 | #define GICC_BASE (0x2c000000) | |
ffc10373 LW |
108 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
109 | #define GICD_BASE (0x2C010000) | |
110 | #define GICC_BASE (0x2C02f000) | |
261d2760 | 111 | #else |
03314f0e | 112 | #error "Unknown board variant" |
261d2760 | 113 | #endif |
03314f0e | 114 | #endif /* !CONFIG_GICV3 */ |
12916829 | 115 | |
12916829 | 116 | /* Size of malloc() pool */ |
5bcae13e | 117 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) |
12916829 | 118 | |
b31f9d7a LW |
119 | /* Ethernet Configuration */ |
120 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO | |
121 | /* The real hardware Versatile express uses SMSC9118 */ | |
122 | #define CONFIG_SMC911X 1 | |
123 | #define CONFIG_SMC911X_32_BIT 1 | |
124 | #define CONFIG_SMC911X_BASE (0x018000000) | |
125 | #else | |
126 | /* The Vexpress64 simulators use SMSC91C111 */ | |
3865ceb7 BS |
127 | #define CONFIG_SMC91111 1 |
128 | #define CONFIG_SMC91111_BASE (0x01A000000) | |
b31f9d7a | 129 | #endif |
12916829 DF |
130 | |
131 | /* PL011 Serial Configuration */ | |
d280ea00 | 132 | #define CONFIG_BAUDRATE 115200 |
d8bafe13 | 133 | #define CONFIG_CONS_INDEX 0 |
d280ea00 | 134 | #define CONFIG_PL01X_SERIAL |
12916829 | 135 | #define CONFIG_PL011_SERIAL |
ffc10373 LW |
136 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
137 | #define CONFIG_PL011_CLOCK 7273800 | |
138 | #else | |
12916829 | 139 | #define CONFIG_PL011_CLOCK 24000000 |
ffc10373 | 140 | #endif |
12916829 DF |
141 | |
142 | /* Command line configuration */ | |
143 | #define CONFIG_MENU | |
144 | /*#define CONFIG_MENU_SHOW*/ | |
145 | #define CONFIG_CMD_CACHE | |
67172528 TR |
146 | #define CONFIG_CMD_BOOTI |
147 | #define CONFIG_CMD_UNZIP | |
12916829 DF |
148 | #define CONFIG_CMD_DHCP |
149 | #define CONFIG_CMD_PXE | |
150 | #define CONFIG_CMD_ENV | |
12916829 | 151 | #define CONFIG_CMD_MII |
12916829 | 152 | #define CONFIG_CMD_PING |
12916829 DF |
153 | #define CONFIG_CMD_FAT |
154 | #define CONFIG_DOS_PARTITION | |
155 | ||
156 | /* BOOTP options */ | |
157 | #define CONFIG_BOOTP_BOOTFILESIZE | |
158 | #define CONFIG_BOOTP_BOOTPATH | |
159 | #define CONFIG_BOOTP_GATEWAY | |
160 | #define CONFIG_BOOTP_HOSTNAME | |
161 | #define CONFIG_BOOTP_PXE | |
162 | #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 | |
163 | ||
164 | /* Miscellaneous configurable options */ | |
165 | #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) | |
166 | ||
167 | /* Physical Memory Map */ | |
2d0cee1c | 168 | #define CONFIG_NR_DRAM_BANKS 2 |
12916829 | 169 | #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ |
2d0cee1c | 170 | #define PHYS_SDRAM_2 (0x880000000) |
30355708 LW |
171 | /* Top 16MB reserved for secure world use */ |
172 | #define DRAM_SEC_SIZE 0x01000000 | |
173 | #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE | |
2d0cee1c | 174 | #define PHYS_SDRAM_2_SIZE 0x180000000 |
30355708 LW |
175 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
176 | ||
177 | /* Enable memtest */ | |
178 | #define CONFIG_CMD_MEMTEST | |
179 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
180 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
12916829 DF |
181 | |
182 | /* Initial environment variables */ | |
10d1491b LW |
183 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
184 | /* | |
185 | * Defines where the kernel and FDT exist in NOR flash and where it will | |
186 | * be copied into DRAM | |
187 | */ | |
188 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ecbed5d6 RH |
189 | "kernel_name=norkern\0" \ |
190 | "kernel_alt_name=Image\0" \ | |
10d1491b | 191 | "kernel_addr=0x80000000\0" \ |
4a6bdb59 RH |
192 | "initrd_name=ramdisk.img\0" \ |
193 | "initrd_addr=0x84000000\0" \ | |
ecbed5d6 RH |
194 | "fdt_name=board.dtb\0" \ |
195 | "fdt_alt_name=juno\0" \ | |
10d1491b LW |
196 | "fdt_addr=0x83000000\0" \ |
197 | "fdt_high=0xffffffffffffffff\0" \ | |
198 | "initrd_high=0xffffffffffffffff\0" \ | |
199 | ||
200 | /* Assume we boot with root on the first partition of a USB stick */ | |
201 | #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ | |
492f24e8 | 202 | "root=/dev/sda2 rw " \ |
33665f7c | 203 | "rootwait "\ |
c0ae9703 RH |
204 | "earlyprintk=pl011,0x7ff80000 debug "\ |
205 | "user_debug=31 "\ | |
74e264b4 | 206 | "androidboot.hardware=juno "\ |
10d1491b LW |
207 | "loglevel=9" |
208 | ||
209 | /* Copy the kernel and FDT to DRAM memory and boot */ | |
210 | #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ | |
ecbed5d6 RH |
211 | "if test $? -eq 1; then "\ |
212 | " echo Loading ${kernel_alt_name} instead of "\ | |
213 | "${kernel_name}; "\ | |
214 | " afs load ${kernel_alt_name} ${kernel_addr};"\ | |
215 | "fi ; "\ | |
10d1491b | 216 | "afs load ${fdt_name} ${fdt_addr} ; " \ |
ecbed5d6 RH |
217 | "if test $? -eq 1; then "\ |
218 | " echo Loading ${fdt_alt_name} instead of "\ | |
219 | "${fdt_name}; "\ | |
220 | " afs load ${fdt_alt_name} ${fdt_addr}; "\ | |
221 | "fi ; "\ | |
10d1491b | 222 | "fdt addr ${fdt_addr}; fdt resize; " \ |
4a6bdb59 RH |
223 | "if afs load ${initrd_name} ${initrd_addr} ; "\ |
224 | "then "\ | |
225 | " setenv initrd_param ${initrd_addr}; "\ | |
226 | " else setenv initrd_param -; "\ | |
227 | "fi ; " \ | |
228 | "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" | |
10d1491b LW |
229 | |
230 | #define CONFIG_BOOTDELAY 1 | |
231 | ||
232 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP | |
261d2760 | 233 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
1fd0f92e | 234 | "kernel_name=Image\0" \ |
49995ffe | 235 | "kernel_addr=0x80000000\0" \ |
261d2760 | 236 | "initrd_name=ramdisk.img\0" \ |
49995ffe LW |
237 | "initrd_addr=0x88000000\0" \ |
238 | "fdt_name=devtree.dtb\0" \ | |
239 | "fdt_addr=0x83000000\0" \ | |
261d2760 DR |
240 | "fdt_high=0xffffffffffffffff\0" \ |
241 | "initrd_high=0xffffffffffffffff\0" | |
242 | ||
243 | #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ | |
244 | "0x1c090000 debug user_debug=31 "\ | |
245 | "loglevel=9" | |
246 | ||
49995ffe | 247 | #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ |
1fd0f92e | 248 | "smhload ${fdt_name} ${fdt_addr}; " \ |
c0ae9703 RH |
249 | "smhload ${initrd_name} ${initrd_addr} "\ |
250 | "initrd_end; " \ | |
1fd0f92e LW |
251 | "fdt addr ${fdt_addr}; fdt resize; " \ |
252 | "fdt chosen ${initrd_addr} ${initrd_end}; " \ | |
253 | "booti $kernel_addr - $fdt_addr" | |
261d2760 DR |
254 | |
255 | #define CONFIG_BOOTDELAY 1 | |
256 | ||
fc04b923 RH |
257 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM |
258 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
259 | "kernel_addr=0x80080000\0" \ | |
260 | "initrd_addr=0x84000000\0" \ | |
261 | "fdt_addr=0x83000000\0" \ | |
262 | "fdt_high=0xffffffffffffffff\0" \ | |
263 | "initrd_high=0xffffffffffffffff\0" | |
264 | ||
265 | #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ | |
266 | "0x1c090000 debug user_debug=31 "\ | |
267 | "androidboot.hardware=fvpbase "\ | |
268 | "root=/dev/vda2 rw "\ | |
269 | "rootwait "\ | |
270 | "loglevel=9" | |
271 | ||
272 | #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" | |
273 | ||
274 | #define CONFIG_BOOTDELAY 1 | |
275 | ||
261d2760 | 276 | #else |
03314f0e | 277 | #error "Unknown board variant" |
261d2760 | 278 | #endif |
12916829 DF |
279 | |
280 | /* Do not preserve environment */ | |
281 | #define CONFIG_ENV_IS_NOWHERE 1 | |
282 | #define CONFIG_ENV_SIZE 0x1000 | |
283 | ||
284 | /* Monitor Command Prompt */ | |
285 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
12916829 DF |
286 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
287 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
288 | #define CONFIG_SYS_HUSH_PARSER | |
12916829 DF |
289 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
290 | #define CONFIG_SYS_LONGHELP | |
5bcae13e | 291 | #define CONFIG_CMDLINE_EDITING |
12916829 DF |
292 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
293 | ||
14f264e6 LW |
294 | /* Flash memory is available on the Juno board only */ |
295 | #ifndef CONFIG_TARGET_VEXPRESS64_JUNO | |
296 | #define CONFIG_SYS_NO_FLASH | |
297 | #else | |
10d1491b | 298 | #define CONFIG_CMD_ARMFLASH |
14f264e6 LW |
299 | #define CONFIG_SYS_FLASH_CFI 1 |
300 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
f19f389f | 301 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
14f264e6 LW |
302 | #define CONFIG_SYS_FLASH_BASE 0x08000000 |
303 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ | |
304 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 | |
305 | ||
306 | /* Timeout values in ticks */ | |
307 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ | |
308 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ | |
309 | ||
310 | /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ | |
311 | #define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ | |
312 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ | |
313 | #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ | |
314 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ | |
315 | ||
316 | #endif | |
317 | ||
12916829 | 318 | #endif /* __VEXPRESS_AEMV8A_H */ |