]>
Commit | Line | Data |
---|---|---|
c2e49f70 RA |
1 | /* |
2 | * esd vme8349 U-Boot configuration file | |
3 | * Copyright (c) 2008, 2009 esd gmbh Hannover Germany | |
4 | * | |
2ae18241 | 5 | * (C) Copyright 2006-2010 |
c2e49f70 RA |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
8 | * reinhard.arlt@esd-electronics.de | |
9 | * Based on the MPC8349EMDS config. | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
c2e49f70 RA |
12 | */ |
13 | ||
14 | /* | |
15 | * vme8349 board configuration file. | |
16 | */ | |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
1dee9be6 RA |
21 | /* |
22 | * Top level Makefile configuration choices | |
23 | */ | |
2ae18241 | 24 | #ifdef CONFIG_CADDY2 |
1dee9be6 RA |
25 | #define VME_CADDY2 |
26 | #endif | |
27 | ||
c2e49f70 RA |
28 | /* |
29 | * High Level Configuration Options | |
30 | */ | |
31 | #define CONFIG_E300 1 /* E300 Family */ | |
c2e49f70 RA |
32 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
33 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ | |
34 | #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ | |
35 | ||
1dee9be6 RA |
36 | #define CONFIG_MISC_INIT_R |
37 | ||
c2e49f70 RA |
38 | /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ |
39 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ | |
40 | ||
2ae18241 WD |
41 | #define CONFIG_PCI_66M |
42 | #ifdef CONFIG_PCI_66M | |
c2e49f70 RA |
43 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
44 | #else | |
45 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
46 | #endif | |
47 | ||
48 | #ifndef CONFIG_SYS_CLK_FREQ | |
2ae18241 | 49 | #ifdef CONFIG_PCI_66M |
c2e49f70 RA |
50 | #define CONFIG_SYS_CLK_FREQ 66000000 |
51 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 | |
52 | #else | |
53 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
54 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 | |
55 | #endif | |
56 | #endif | |
57 | ||
58 | #define CONFIG_SYS_IMMR 0xE0000000 | |
59 | ||
60 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ | |
61 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
62 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
63 | ||
64 | /* | |
65 | * DDR Setup | |
66 | */ | |
67 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
68 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ | |
1dee9be6 RA |
69 | #define CONFIG_SPD_EEPROM |
70 | #define SPD_EEPROM_ADDRESS 0x54 | |
71 | #define CONFIG_SYS_READ_SPD vme8349_read_spd | |
c2e49f70 RA |
72 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ |
73 | ||
74 | /* | |
75 | * 32-bit data path mode. | |
76 | * | |
77 | * Please note that using this mode for devices with the real density of 64-bit | |
78 | * effectively reduces the amount of available memory due to the effect of | |
79 | * wrapping around while translating address to row/columns, for example in the | |
80 | * 256MB module the upper 128MB get aliased with contents of the lower | |
81 | * 128MB); normally this define should be used for devices with real 32-bit | |
82 | * data path. | |
83 | */ | |
84 | #undef CONFIG_DDR_32BIT | |
85 | ||
86 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ | |
87 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
88 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
2fef4020 JH |
89 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
90 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
c2e49f70 | 91 | #define CONFIG_DDR_2T_TIMING |
2fef4020 JH |
92 | #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ |
93 | | DDRCDR_ODT \ | |
94 | | DDRCDR_Q_DRN) | |
95 | /* 0x80080001 */ | |
c2e49f70 RA |
96 | |
97 | /* | |
98 | * FLASH on the Local Bus | |
99 | */ | |
100 | #define CONFIG_SYS_FLASH_CFI | |
101 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
1dee9be6 RA |
102 | #ifdef VME_CADDY2 |
103 | #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ | |
104 | #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ | |
105 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
7d6a0982 JH |
106 | BR_PS_16 | /* 16bit */ \ |
107 | BR_MS_GPCM | /* MSEL = GPCM */ \ | |
108 | BR_V) /* valid */ | |
109 | ||
110 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
111 | | OR_GPCM_XAM \ | |
112 | | OR_GPCM_CSNT \ | |
113 | | OR_GPCM_ACS_DIV2 \ | |
114 | | OR_GPCM_XACS \ | |
115 | | OR_GPCM_SCY_15 \ | |
116 | | OR_GPCM_TRLX_SET \ | |
117 | | OR_GPCM_EHTR_SET \ | |
118 | | OR_GPCM_EAD) | |
119 | /* 0xffc06ff7 */ | |
1dee9be6 | 120 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 121 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) |
1dee9be6 RA |
122 | #else |
123 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
124 | #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ | |
c2e49f70 | 125 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ |
7d6a0982 JH |
126 | BR_PS_16 | /* 16bit */ \ |
127 | BR_MS_GPCM | /* MSEL = GPCM */ \ | |
128 | BR_V) /* valid */ | |
129 | ||
130 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
131 | | OR_GPCM_XAM \ | |
132 | | OR_GPCM_CSNT \ | |
133 | | OR_GPCM_ACS_DIV2 \ | |
134 | | OR_GPCM_XACS \ | |
135 | | OR_GPCM_SCY_15 \ | |
136 | | OR_GPCM_TRLX_SET \ | |
137 | | OR_GPCM_EHTR_SET \ | |
138 | | OR_GPCM_EAD) | |
139 | /* 0xf8006ff7 */ | |
c2e49f70 | 140 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 141 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) |
1dee9be6 RA |
142 | #endif |
143 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
c2e49f70 | 144 | |
7d6a0982 JH |
145 | #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 |
146 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ | |
147 | | BR_PS_32 \ | |
148 | | BR_MS_GPCM \ | |
149 | | BR_V) | |
150 | /* 0xF0001801 */ | |
151 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | |
152 | | OR_GPCM_SETA) | |
153 | /* 0xfffc0208 */ | |
154 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE | |
155 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) | |
c2e49f70 RA |
156 | |
157 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
158 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ | |
159 | ||
160 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
161 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ | |
162 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ | |
163 | ||
c7357a2b | 164 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
c2e49f70 RA |
165 | |
166 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
167 | #define CONFIG_SYS_RAMBOOT | |
168 | #else | |
1dee9be6 | 169 | #undef CONFIG_SYS_RAMBOOT |
c2e49f70 RA |
170 | #endif |
171 | ||
172 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
173 | #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ | |
553f0982 | 174 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ |
c2e49f70 | 175 | |
553f0982 | 176 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 177 | GENERATED_GBL_DATA_SIZE) |
c2e49f70 RA |
178 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
179 | ||
180 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ | |
c8a90646 | 181 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ |
c2e49f70 RA |
182 | |
183 | /* | |
184 | * Local Bus LCRR and LBCR regs | |
1dee9be6 | 185 | * LCRR: no DLL bypass, Clock divider is 4 |
c2e49f70 RA |
186 | * External Local Bus rate is |
187 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
188 | */ | |
c7190f02 | 189 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
c2e49f70 RA |
190 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
191 | ||
192 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ | |
193 | ||
194 | /* | |
195 | * Serial Port | |
196 | */ | |
197 | #define CONFIG_CONS_INDEX 1 | |
c2e49f70 RA |
198 | #define CONFIG_SYS_NS16550_SERIAL |
199 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
200 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
201 | ||
202 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
c7357a2b | 203 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
c2e49f70 RA |
204 | |
205 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
206 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
207 | ||
208 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
a059e90e | 209 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
c2e49f70 | 210 | |
c2e49f70 | 211 | /* I2C */ |
00f792e0 HS |
212 | #define CONFIG_SYS_I2C |
213 | #define CONFIG_SYS_I2C_FSL | |
214 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
215 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
216 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
217 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
218 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
219 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
220 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
efaf6f1b | 221 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
c2e49f70 RA |
222 | |
223 | #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ | |
224 | ||
225 | /* TSEC */ | |
226 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
227 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) | |
228 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
229 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) | |
230 | ||
231 | /* | |
232 | * General PCI | |
233 | * Addresses are mapped 1-1. | |
234 | */ | |
235 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
236 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
237 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
238 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
239 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
240 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
241 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
242 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
243 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
244 | ||
245 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
246 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
247 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
248 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
249 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
250 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
251 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
252 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
253 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
254 | ||
255 | #if defined(CONFIG_PCI) | |
256 | ||
257 | #define PCI_64BIT | |
258 | #define PCI_ONE_PCI1 | |
259 | #if defined(PCI_64BIT) | |
260 | #undef PCI_ALL_PCI1 | |
261 | #undef PCI_TWO_PCI1 | |
262 | #undef PCI_ONE_PCI1 | |
263 | #endif | |
264 | ||
1dee9be6 | 265 | #ifndef VME_CADDY2 |
1dee9be6 | 266 | #endif |
c2e49f70 RA |
267 | |
268 | #undef CONFIG_EEPRO100 | |
269 | #undef CONFIG_TULIP | |
270 | ||
271 | #if !defined(CONFIG_PCI_PNP) | |
272 | #define PCI_ENET0_IOADDR 0xFIXME | |
273 | #define PCI_ENET0_MEMADDR 0xFIXME | |
274 | #define PCI_IDSEL_NUMBER 0xFIXME | |
275 | #endif | |
276 | ||
1dee9be6 RA |
277 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
278 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
279 | ||
c2e49f70 RA |
280 | #endif /* CONFIG_PCI */ |
281 | ||
282 | /* | |
283 | * TSEC configuration | |
284 | */ | |
1dee9be6 | 285 | #ifdef VME_CADDY2 |
1dee9be6 | 286 | #else |
c2e49f70 | 287 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
1dee9be6 | 288 | #endif |
c2e49f70 RA |
289 | |
290 | #if defined(CONFIG_TSEC_ENET) | |
c2e49f70 | 291 | |
1dee9be6 | 292 | #define CONFIG_GMII /* MII PHY management */ |
c2e49f70 RA |
293 | #define CONFIG_TSEC1 |
294 | #define CONFIG_TSEC1_NAME "TSEC0" | |
295 | #define CONFIG_TSEC2 | |
296 | #define CONFIG_TSEC2_NAME "TSEC1" | |
297 | #define CONFIG_PHY_M88E1111 | |
298 | #define TSEC1_PHY_ADDR 0x08 | |
299 | #define TSEC2_PHY_ADDR 0x10 | |
300 | #define TSEC1_PHYIDX 0 | |
301 | #define TSEC2_PHYIDX 0 | |
302 | #define TSEC1_FLAGS TSEC_GIGABIT | |
303 | #define TSEC2_FLAGS TSEC_GIGABIT | |
304 | ||
305 | /* Options are: TSEC[0-1] */ | |
306 | #define CONFIG_ETHPRIME "TSEC0" | |
307 | ||
308 | #endif /* CONFIG_TSEC_ENET */ | |
309 | ||
310 | /* | |
311 | * Environment | |
312 | */ | |
313 | #ifndef CONFIG_SYS_RAMBOOT | |
c2e49f70 RA |
314 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) |
315 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
316 | #define CONFIG_ENV_SIZE 0x2000 | |
317 | ||
318 | /* Address and size of Redundant Environment Sector */ | |
319 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
320 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
321 | ||
322 | #else | |
c2e49f70 RA |
323 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
324 | #define CONFIG_ENV_SIZE 0x2000 | |
325 | #endif | |
326 | ||
327 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
328 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
329 | ||
330 | /* | |
331 | * BOOTP options | |
332 | */ | |
333 | #define CONFIG_BOOTP_BOOTFILESIZE | |
334 | #define CONFIG_BOOTP_BOOTPATH | |
335 | #define CONFIG_BOOTP_GATEWAY | |
336 | #define CONFIG_BOOTP_HOSTNAME | |
337 | ||
338 | /* | |
339 | * Command line configuration. | |
340 | */ | |
c2e49f70 RA |
341 | #define CONFIG_SYS_RTC_BUS_NUM 0x01 |
342 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 | |
343 | #define CONFIG_RTC_RX8025 | |
c2e49f70 | 344 | |
c2e49f70 RA |
345 | /* Pass Ethernet MAC to VxWorks */ |
346 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 | |
347 | ||
348 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
349 | ||
350 | /* | |
351 | * Miscellaneous configurable options | |
352 | */ | |
353 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
354 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
c2e49f70 | 355 | |
c2e49f70 RA |
356 | /* |
357 | * For booting Linux, the board info and command line data | |
9f530d59 | 358 | * have to be in the first 256 MB of memory, since this is |
c2e49f70 RA |
359 | * the maximum mapped by the Linux kernel during initialization. |
360 | */ | |
9f530d59 | 361 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ |
c2e49f70 RA |
362 | |
363 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ | |
364 | ||
365 | #define CONFIG_SYS_HRCW_LOW (\ | |
366 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
367 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
368 | HRCWL_CSB_TO_CLKIN |\ | |
369 | HRCWL_VCO_1X2 |\ | |
370 | HRCWL_CORE_TO_CSB_2X1) | |
371 | ||
372 | #if defined(PCI_64BIT) | |
373 | #define CONFIG_SYS_HRCW_HIGH (\ | |
374 | HRCWH_PCI_HOST |\ | |
375 | HRCWH_64_BIT_PCI |\ | |
376 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
377 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
378 | HRCWH_CORE_ENABLE |\ | |
379 | HRCWH_FROM_0X00000100 |\ | |
380 | HRCWH_BOOTSEQ_DISABLE |\ | |
381 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
382 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
383 | HRCWH_TSEC1M_IN_GMII |\ | |
384 | HRCWH_TSEC2M_IN_GMII) | |
385 | #else | |
386 | #define CONFIG_SYS_HRCW_HIGH (\ | |
387 | HRCWH_PCI_HOST |\ | |
388 | HRCWH_32_BIT_PCI |\ | |
389 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
390 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
391 | HRCWH_CORE_ENABLE |\ | |
392 | HRCWH_FROM_0X00000100 |\ | |
393 | HRCWH_BOOTSEQ_DISABLE |\ | |
394 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
395 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
396 | HRCWH_TSEC1M_IN_GMII |\ | |
397 | HRCWH_TSEC2M_IN_GMII) | |
398 | #endif | |
399 | ||
400 | /* System IO Config */ | |
401 | #define CONFIG_SYS_SICRH 0 | |
402 | #define CONFIG_SYS_SICRL SICRL_LDP_A | |
403 | ||
404 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
1a2e203b KP |
405 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
406 | HID0_ENABLE_INSTRUCTION_CACHE) | |
c2e49f70 RA |
407 | |
408 | #define CONFIG_SYS_HID2 HID2_HBE | |
409 | ||
410 | #define CONFIG_SYS_GPIO1_PRELIM | |
411 | #define CONFIG_SYS_GPIO1_DIR 0x00100000 | |
412 | #define CONFIG_SYS_GPIO1_DAT 0x00100000 | |
413 | ||
414 | #define CONFIG_SYS_GPIO2_PRELIM | |
415 | #define CONFIG_SYS_GPIO2_DIR 0x78900000 | |
416 | #define CONFIG_SYS_GPIO2_DAT 0x70100000 | |
417 | ||
418 | #define CONFIG_HIGH_BATS /* High BATs supported */ | |
419 | ||
420 | /* DDR @ 0x00000000 */ | |
72cd4087 | 421 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
422 | BATL_MEMCOHERENCE) |
423 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ | |
424 | BATU_VS | BATU_VP) | |
425 | ||
426 | /* PCI @ 0x80000000 */ | |
427 | #ifdef CONFIG_PCI | |
842033e6 | 428 | #define CONFIG_PCI_INDIRECT_BRIDGE |
72cd4087 | 429 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
430 | BATL_MEMCOHERENCE) |
431 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ | |
432 | BATU_VS | BATU_VP) | |
72cd4087 | 433 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
434 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
435 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ | |
436 | BATU_VS | BATU_VP) | |
437 | #else | |
438 | #define CONFIG_SYS_IBAT1L (0) | |
439 | #define CONFIG_SYS_IBAT1U (0) | |
440 | #define CONFIG_SYS_IBAT2L (0) | |
441 | #define CONFIG_SYS_IBAT2U (0) | |
442 | #endif | |
443 | ||
444 | #ifdef CONFIG_MPC83XX_PCI2 | |
72cd4087 | 445 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
446 | BATL_MEMCOHERENCE) |
447 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ | |
448 | BATU_VS | BATU_VP) | |
72cd4087 | 449 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
450 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
451 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ | |
452 | BATU_VS | BATU_VP) | |
453 | #else | |
454 | #define CONFIG_SYS_IBAT3L (0) | |
455 | #define CONFIG_SYS_IBAT3U (0) | |
456 | #define CONFIG_SYS_IBAT4L (0) | |
457 | #define CONFIG_SYS_IBAT4U (0) | |
458 | #endif | |
459 | ||
460 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
72cd4087 | 461 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
c2e49f70 RA |
462 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
463 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ | |
464 | BATU_VS | BATU_VP) | |
465 | ||
72cd4087 | 466 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) |
c2e49f70 RA |
467 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
468 | ||
469 | #if (CONFIG_SYS_DDR_SIZE == 512) | |
470 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ | |
72cd4087 | 471 | BATL_PP_RW | BATL_MEMCOHERENCE) |
c2e49f70 RA |
472 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ |
473 | BATU_BL_256M | BATU_VS | BATU_VP) | |
474 | #else | |
475 | #define CONFIG_SYS_IBAT7L (0) | |
476 | #define CONFIG_SYS_IBAT7U (0) | |
477 | #endif | |
478 | ||
479 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
480 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
481 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
482 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
483 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
484 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
485 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
486 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
487 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
488 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
489 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
490 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
491 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
492 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
493 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
494 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
495 | ||
c2e49f70 RA |
496 | #if defined(CONFIG_CMD_KGDB) |
497 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
c2e49f70 RA |
498 | #endif |
499 | ||
500 | /* | |
501 | * Environment Configuration | |
502 | */ | |
503 | #define CONFIG_ENV_OVERWRITE | |
504 | ||
505 | #if defined(CONFIG_TSEC_ENET) | |
506 | #define CONFIG_HAS_ETH0 | |
507 | #define CONFIG_HAS_ETH1 | |
508 | #endif | |
509 | ||
510 | #define CONFIG_HOSTNAME VME8349 | |
8b3637c6 | 511 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
b3f44c21 | 512 | #define CONFIG_BOOTFILE "uImage" |
c2e49f70 | 513 | |
79f516bc | 514 | #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ |
c2e49f70 | 515 | |
c2e49f70 RA |
516 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
517 | "netdev=eth0\0" \ | |
518 | "hostname=vme8349\0" \ | |
519 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
520 | "nfsroot=${serverip}:${rootpath}\0" \ | |
521 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
522 | "addip=setenv bootargs ${bootargs} " \ | |
523 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
524 | ":${hostname}:${netdev}:off panic=1\0" \ | |
525 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
526 | "flash_nfs=run nfsargs addip addtty;" \ | |
527 | "bootm ${kernel_addr}\0" \ | |
528 | "flash_self=run ramargs addip addtty;" \ | |
529 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
530 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
531 | "bootm\0" \ | |
532 | "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ | |
533 | "update=protect off fff00000 fff3ffff; " \ | |
534 | "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ | |
535 | "upd=run load update\0" \ | |
79f516bc | 536 | "fdtaddr=780000\0" \ |
c2e49f70 RA |
537 | "fdtfile=vme8349.dtb\0" \ |
538 | "" | |
539 | ||
c7357a2b JH |
540 | #define CONFIG_NFSBOOTCOMMAND \ |
541 | "setenv bootargs root=/dev/nfs rw " \ | |
542 | "nfsroot=$serverip:$rootpath " \ | |
543 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
544 | "$netdev:off " \ | |
545 | "console=$consoledev,$baudrate $othbootargs;" \ | |
546 | "tftp $loadaddr $bootfile;" \ | |
547 | "tftp $fdtaddr $fdtfile;" \ | |
548 | "bootm $loadaddr - $fdtaddr" | |
c2e49f70 RA |
549 | |
550 | #define CONFIG_RAMBOOTCOMMAND \ | |
c7357a2b JH |
551 | "setenv bootargs root=/dev/ram rw " \ |
552 | "console=$consoledev,$baudrate $othbootargs;" \ | |
553 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
554 | "tftp $loadaddr $bootfile;" \ | |
555 | "tftp $fdtaddr $fdtfile;" \ | |
556 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
c2e49f70 RA |
557 | |
558 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
559 | ||
1dee9be6 RA |
560 | #ifndef __ASSEMBLY__ |
561 | int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, | |
562 | unsigned char *buffer, int len); | |
563 | #endif | |
564 | ||
c2e49f70 | 565 | #endif /* __CONFIG_H */ |