projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c2e49f70 RA |
1 | /* |
| 2 | * esd vme8349 U-Boot configuration file | |
| 3 | * Copyright (c) 2008, 2009 esd gmbh Hannover Germany | |
| 4 | * | |
| 2ae18241 | 5 | * (C) Copyright 2006-2010 |
| c2e49f70 RA |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 7 | * | |
| 8 | * reinhard.arlt@esd-electronics.de | |
| 9 | * Based on the MPC8349EMDS config. | |
| 10 | * | |
| 3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
| c2e49f70 RA |
12 | */ |
| 13 | ||
| 14 | /* | |
| 15 | * vme8349 board configuration file. | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef __CONFIG_H | |
| 19 | #define __CONFIG_H | |
| 20 | ||
| fdfaa29e KP |
21 | #define CONFIG_SYS_GENERIC_BOARD |
| 22 | #define CONFIG_DISPLAY_BOARDINFO | |
| 23 | ||
| 1dee9be6 RA |
24 | /* |
| 25 | * Top level Makefile configuration choices | |
| 26 | */ | |
| 2ae18241 | 27 | #ifdef CONFIG_CADDY2 |
| 1dee9be6 RA |
28 | #define VME_CADDY2 |
| 29 | #endif | |
| 30 | ||
| c2e49f70 RA |
31 | /* |
| 32 | * High Level Configuration Options | |
| 33 | */ | |
| 34 | #define CONFIG_E300 1 /* E300 Family */ | |
| c2e49f70 RA |
35 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
| 36 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ | |
| 37 | #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ | |
| 38 | ||
| 2ae18241 WD |
39 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 40 | ||
| 1dee9be6 RA |
41 | #define CONFIG_MISC_INIT_R |
| 42 | ||
| c2e49f70 RA |
43 | #define CONFIG_PCI |
| 44 | /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ | |
| 45 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ | |
| 46 | ||
| 2ae18241 WD |
47 | #define CONFIG_PCI_66M |
| 48 | #ifdef CONFIG_PCI_66M | |
| c2e49f70 RA |
49 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
| 50 | #else | |
| 51 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
| 52 | #endif | |
| 53 | ||
| 54 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 2ae18241 | 55 | #ifdef CONFIG_PCI_66M |
| c2e49f70 RA |
56 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 57 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 | |
| 58 | #else | |
| 59 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
| 60 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 | |
| 61 | #endif | |
| 62 | #endif | |
| 63 | ||
| 64 | #define CONFIG_SYS_IMMR 0xE0000000 | |
| 65 | ||
| 66 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ | |
| 67 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
| 68 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
| 69 | ||
| 70 | /* | |
| 71 | * DDR Setup | |
| 72 | */ | |
| 73 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 74 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ | |
| 1dee9be6 RA |
75 | #define CONFIG_SPD_EEPROM |
| 76 | #define SPD_EEPROM_ADDRESS 0x54 | |
| 77 | #define CONFIG_SYS_READ_SPD vme8349_read_spd | |
| c2e49f70 RA |
78 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ |
| 79 | ||
| 80 | /* | |
| 81 | * 32-bit data path mode. | |
| 82 | * | |
| 83 | * Please note that using this mode for devices with the real density of 64-bit | |
| 84 | * effectively reduces the amount of available memory due to the effect of | |
| 85 | * wrapping around while translating address to row/columns, for example in the | |
| 86 | * 256MB module the upper 128MB get aliased with contents of the lower | |
| 87 | * 128MB); normally this define should be used for devices with real 32-bit | |
| 88 | * data path. | |
| 89 | */ | |
| 90 | #undef CONFIG_DDR_32BIT | |
| 91 | ||
| 92 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ | |
| 93 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 94 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 2fef4020 JH |
95 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
| 96 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
| c2e49f70 | 97 | #define CONFIG_DDR_2T_TIMING |
| 2fef4020 JH |
98 | #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ |
| 99 | | DDRCDR_ODT \ | |
| 100 | | DDRCDR_Q_DRN) | |
| 101 | /* 0x80080001 */ | |
| c2e49f70 RA |
102 | |
| 103 | /* | |
| 104 | * FLASH on the Local Bus | |
| 105 | */ | |
| 106 | #define CONFIG_SYS_FLASH_CFI | |
| 107 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 1dee9be6 RA |
108 | #ifdef VME_CADDY2 |
| 109 | #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ | |
| 110 | #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ | |
| 111 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
| 7d6a0982 JH |
112 | BR_PS_16 | /* 16bit */ \ |
| 113 | BR_MS_GPCM | /* MSEL = GPCM */ \ | |
| 114 | BR_V) /* valid */ | |
| 115 | ||
| 116 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
| 117 | | OR_GPCM_XAM \ | |
| 118 | | OR_GPCM_CSNT \ | |
| 119 | | OR_GPCM_ACS_DIV2 \ | |
| 120 | | OR_GPCM_XACS \ | |
| 121 | | OR_GPCM_SCY_15 \ | |
| 122 | | OR_GPCM_TRLX_SET \ | |
| 123 | | OR_GPCM_EHTR_SET \ | |
| 124 | | OR_GPCM_EAD) | |
| 125 | /* 0xffc06ff7 */ | |
| 1dee9be6 | 126 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
| 7d6a0982 | 127 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) |
| 1dee9be6 RA |
128 | #else |
| 129 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
| 130 | #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ | |
| c2e49f70 | 131 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ |
| 7d6a0982 JH |
132 | BR_PS_16 | /* 16bit */ \ |
| 133 | BR_MS_GPCM | /* MSEL = GPCM */ \ | |
| 134 | BR_V) /* valid */ | |
| 135 | ||
| 136 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
| 137 | | OR_GPCM_XAM \ | |
| 138 | | OR_GPCM_CSNT \ | |
| 139 | | OR_GPCM_ACS_DIV2 \ | |
| 140 | | OR_GPCM_XACS \ | |
| 141 | | OR_GPCM_SCY_15 \ | |
| 142 | | OR_GPCM_TRLX_SET \ | |
| 143 | | OR_GPCM_EHTR_SET \ | |
| 144 | | OR_GPCM_EAD) | |
| 145 | /* 0xf8006ff7 */ | |
| c2e49f70 | 146 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
| 7d6a0982 | 147 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) |
| 1dee9be6 RA |
148 | #endif |
| 149 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
| c2e49f70 | 150 | |
| 7d6a0982 JH |
151 | #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 |
| 152 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ | |
| 153 | | BR_PS_32 \ | |
| 154 | | BR_MS_GPCM \ | |
| 155 | | BR_V) | |
| 156 | /* 0xF0001801 */ | |
| 157 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | |
| 158 | | OR_GPCM_SETA) | |
| 159 | /* 0xfffc0208 */ | |
| 160 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE | |
| 161 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) | |
| c2e49f70 RA |
162 | |
| 163 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 164 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ | |
| 165 | ||
| 166 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 167 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ | |
| 168 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ | |
| 169 | ||
| c7357a2b | 170 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| c2e49f70 RA |
171 | |
| 172 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
| 173 | #define CONFIG_SYS_RAMBOOT | |
| 174 | #else | |
| 1dee9be6 | 175 | #undef CONFIG_SYS_RAMBOOT |
| c2e49f70 RA |
176 | #endif |
| 177 | ||
| 178 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 179 | #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ | |
| 553f0982 | 180 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ |
| c2e49f70 | 181 | |
| 553f0982 | 182 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 25ddd1fb | 183 | GENERATED_GBL_DATA_SIZE) |
| c2e49f70 RA |
184 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 185 | ||
| 186 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ | |
| c8a90646 | 187 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ |
| c2e49f70 RA |
188 | |
| 189 | /* | |
| 190 | * Local Bus LCRR and LBCR regs | |
| 1dee9be6 | 191 | * LCRR: no DLL bypass, Clock divider is 4 |
| c2e49f70 RA |
192 | * External Local Bus rate is |
| 193 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 194 | */ | |
| c7190f02 | 195 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
| c2e49f70 RA |
196 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 197 | ||
| 198 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ | |
| 199 | ||
| 200 | /* | |
| 201 | * Serial Port | |
| 202 | */ | |
| 203 | #define CONFIG_CONS_INDEX 1 | |
| c2e49f70 RA |
204 | #define CONFIG_SYS_NS16550 |
| 205 | #define CONFIG_SYS_NS16550_SERIAL | |
| 206 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 207 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 208 | ||
| 209 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| c7357a2b | 210 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| c2e49f70 RA |
211 | |
| 212 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
| 213 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
| 214 | ||
| 215 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
| a059e90e | 216 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| c2e49f70 RA |
217 | /* Use the HUSH parser */ |
| 218 | #define CONFIG_SYS_HUSH_PARSER | |
| c2e49f70 RA |
219 | |
| 220 | /* pass open firmware flat tree */ | |
| 221 | #define CONFIG_OF_LIBFDT | |
| 222 | #define CONFIG_OF_BOARD_SETUP | |
| 223 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 224 | ||
| 225 | /* I2C */ | |
| 00f792e0 HS |
226 | #define CONFIG_SYS_I2C |
| 227 | #define CONFIG_SYS_I2C_FSL | |
| 228 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 229 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 230 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 231 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 232 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 233 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 234 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| efaf6f1b | 235 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
| c2e49f70 RA |
236 | |
| 237 | #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ | |
| 238 | ||
| 239 | /* TSEC */ | |
| 240 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
| 241 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) | |
| 242 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
| 243 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) | |
| 244 | ||
| 245 | /* | |
| 246 | * General PCI | |
| 247 | * Addresses are mapped 1-1. | |
| 248 | */ | |
| 249 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
| 250 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 251 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 252 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 253 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 254 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 255 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
| 256 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 257 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 258 | ||
| 259 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
| 260 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
| 261 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 262 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
| 263 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
| 264 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 265 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
| 266 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
| 267 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 268 | ||
| 269 | #if defined(CONFIG_PCI) | |
| 270 | ||
| 271 | #define PCI_64BIT | |
| 272 | #define PCI_ONE_PCI1 | |
| 273 | #if defined(PCI_64BIT) | |
| 274 | #undef PCI_ALL_PCI1 | |
| 275 | #undef PCI_TWO_PCI1 | |
| 276 | #undef PCI_ONE_PCI1 | |
| 277 | #endif | |
| 278 | ||
| 1dee9be6 | 279 | #ifndef VME_CADDY2 |
| 1dee9be6 RA |
280 | #endif |
| 281 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| c2e49f70 RA |
282 | |
| 283 | #undef CONFIG_EEPRO100 | |
| 284 | #undef CONFIG_TULIP | |
| 285 | ||
| 286 | #if !defined(CONFIG_PCI_PNP) | |
| 287 | #define PCI_ENET0_IOADDR 0xFIXME | |
| 288 | #define PCI_ENET0_MEMADDR 0xFIXME | |
| 289 | #define PCI_IDSEL_NUMBER 0xFIXME | |
| 290 | #endif | |
| 291 | ||
| 1dee9be6 RA |
292 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 293 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
| 294 | ||
| c2e49f70 RA |
295 | #endif /* CONFIG_PCI */ |
| 296 | ||
| 297 | /* | |
| 298 | * TSEC configuration | |
| 299 | */ | |
| 1dee9be6 | 300 | #ifdef VME_CADDY2 |
| 1dee9be6 | 301 | #else |
| c2e49f70 | 302 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
| 1dee9be6 | 303 | #endif |
| c2e49f70 RA |
304 | |
| 305 | #if defined(CONFIG_TSEC_ENET) | |
| c2e49f70 | 306 | |
| 1dee9be6 | 307 | #define CONFIG_GMII /* MII PHY management */ |
| c2e49f70 RA |
308 | #define CONFIG_TSEC1 |
| 309 | #define CONFIG_TSEC1_NAME "TSEC0" | |
| 310 | #define CONFIG_TSEC2 | |
| 311 | #define CONFIG_TSEC2_NAME "TSEC1" | |
| 312 | #define CONFIG_PHY_M88E1111 | |
| 313 | #define TSEC1_PHY_ADDR 0x08 | |
| 314 | #define TSEC2_PHY_ADDR 0x10 | |
| 315 | #define TSEC1_PHYIDX 0 | |
| 316 | #define TSEC2_PHYIDX 0 | |
| 317 | #define TSEC1_FLAGS TSEC_GIGABIT | |
| 318 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 319 | ||
| 320 | /* Options are: TSEC[0-1] */ | |
| 321 | #define CONFIG_ETHPRIME "TSEC0" | |
| 322 | ||
| 323 | #endif /* CONFIG_TSEC_ENET */ | |
| 324 | ||
| 325 | /* | |
| 326 | * Environment | |
| 327 | */ | |
| 328 | #ifndef CONFIG_SYS_RAMBOOT | |
| 329 | #define CONFIG_ENV_IS_IN_FLASH | |
| 330 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) | |
| 331 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
| 332 | #define CONFIG_ENV_SIZE 0x2000 | |
| 333 | ||
| 334 | /* Address and size of Redundant Environment Sector */ | |
| 335 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
| 336 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 337 | ||
| 338 | #else | |
| 339 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ | |
| 340 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
| 341 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 342 | #define CONFIG_ENV_SIZE 0x2000 | |
| 343 | #endif | |
| 344 | ||
| 345 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 346 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 347 | ||
| 348 | /* | |
| 349 | * BOOTP options | |
| 350 | */ | |
| 351 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 352 | #define CONFIG_BOOTP_BOOTPATH | |
| 353 | #define CONFIG_BOOTP_GATEWAY | |
| 354 | #define CONFIG_BOOTP_HOSTNAME | |
| 355 | ||
| 356 | /* | |
| 357 | * Command line configuration. | |
| 358 | */ | |
| c2e49f70 RA |
359 | #define CONFIG_CMD_I2C |
| 360 | #define CONFIG_CMD_MII | |
| 361 | #define CONFIG_CMD_PING | |
| 362 | #define CONFIG_CMD_DATE | |
| 363 | #define CONFIG_SYS_RTC_BUS_NUM 0x01 | |
| 364 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 | |
| 365 | #define CONFIG_RTC_RX8025 | |
| 366 | #define CONFIG_CMD_TSI148 | |
| 367 | ||
| 368 | #if defined(CONFIG_PCI) | |
| 369 | #define CONFIG_CMD_PCI | |
| 370 | #endif | |
| 371 | ||
| 372 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 373 | #undef CONFIG_CMD_ENV | |
| c2e49f70 RA |
374 | #endif |
| 375 | ||
| 376 | #define CONFIG_CMD_ELF | |
| 377 | /* Pass Ethernet MAC to VxWorks */ | |
| 378 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 | |
| 379 | ||
| 380 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 381 | ||
| 382 | /* | |
| 383 | * Miscellaneous configurable options | |
| 384 | */ | |
| 385 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 386 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| c2e49f70 RA |
387 | |
| 388 | #if defined(CONFIG_CMD_KGDB) | |
| 389 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 390 | #else | |
| 391 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 392 | #endif | |
| 393 | ||
| 394 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 395 | #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ | |
| 396 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ | |
| c2e49f70 RA |
397 | |
| 398 | /* | |
| 399 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 400 | * have to be in the first 256 MB of memory, since this is |
| c2e49f70 RA |
401 | * the maximum mapped by the Linux kernel during initialization. |
| 402 | */ | |
| 9f530d59 | 403 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ |
| c2e49f70 RA |
404 | |
| 405 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ | |
| 406 | ||
| 407 | #define CONFIG_SYS_HRCW_LOW (\ | |
| 408 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
| 409 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 410 | HRCWL_CSB_TO_CLKIN |\ | |
| 411 | HRCWL_VCO_1X2 |\ | |
| 412 | HRCWL_CORE_TO_CSB_2X1) | |
| 413 | ||
| 414 | #if defined(PCI_64BIT) | |
| 415 | #define CONFIG_SYS_HRCW_HIGH (\ | |
| 416 | HRCWH_PCI_HOST |\ | |
| 417 | HRCWH_64_BIT_PCI |\ | |
| 418 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 419 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 420 | HRCWH_CORE_ENABLE |\ | |
| 421 | HRCWH_FROM_0X00000100 |\ | |
| 422 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 423 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 424 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 425 | HRCWH_TSEC1M_IN_GMII |\ | |
| 426 | HRCWH_TSEC2M_IN_GMII) | |
| 427 | #else | |
| 428 | #define CONFIG_SYS_HRCW_HIGH (\ | |
| 429 | HRCWH_PCI_HOST |\ | |
| 430 | HRCWH_32_BIT_PCI |\ | |
| 431 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 432 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
| 433 | HRCWH_CORE_ENABLE |\ | |
| 434 | HRCWH_FROM_0X00000100 |\ | |
| 435 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 436 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 437 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 438 | HRCWH_TSEC1M_IN_GMII |\ | |
| 439 | HRCWH_TSEC2M_IN_GMII) | |
| 440 | #endif | |
| 441 | ||
| 442 | /* System IO Config */ | |
| 443 | #define CONFIG_SYS_SICRH 0 | |
| 444 | #define CONFIG_SYS_SICRL SICRL_LDP_A | |
| 445 | ||
| 446 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
| 1a2e203b KP |
447 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
| 448 | HID0_ENABLE_INSTRUCTION_CACHE) | |
| c2e49f70 RA |
449 | |
| 450 | #define CONFIG_SYS_HID2 HID2_HBE | |
| 451 | ||
| 452 | #define CONFIG_SYS_GPIO1_PRELIM | |
| 453 | #define CONFIG_SYS_GPIO1_DIR 0x00100000 | |
| 454 | #define CONFIG_SYS_GPIO1_DAT 0x00100000 | |
| 455 | ||
| 456 | #define CONFIG_SYS_GPIO2_PRELIM | |
| 457 | #define CONFIG_SYS_GPIO2_DIR 0x78900000 | |
| 458 | #define CONFIG_SYS_GPIO2_DAT 0x70100000 | |
| 459 | ||
| 460 | #define CONFIG_HIGH_BATS /* High BATs supported */ | |
| 461 | ||
| 462 | /* DDR @ 0x00000000 */ | |
| 72cd4087 | 463 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
| c2e49f70 RA |
464 | BATL_MEMCOHERENCE) |
| 465 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ | |
| 466 | BATU_VS | BATU_VP) | |
| 467 | ||
| 468 | /* PCI @ 0x80000000 */ | |
| 469 | #ifdef CONFIG_PCI | |
| 842033e6 | 470 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 72cd4087 | 471 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ |
| c2e49f70 RA |
472 | BATL_MEMCOHERENCE) |
| 473 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ | |
| 474 | BATU_VS | BATU_VP) | |
| 72cd4087 | 475 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ |
| c2e49f70 RA |
476 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 477 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ | |
| 478 | BATU_VS | BATU_VP) | |
| 479 | #else | |
| 480 | #define CONFIG_SYS_IBAT1L (0) | |
| 481 | #define CONFIG_SYS_IBAT1U (0) | |
| 482 | #define CONFIG_SYS_IBAT2L (0) | |
| 483 | #define CONFIG_SYS_IBAT2U (0) | |
| 484 | #endif | |
| 485 | ||
| 486 | #ifdef CONFIG_MPC83XX_PCI2 | |
| 72cd4087 | 487 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ |
| c2e49f70 RA |
488 | BATL_MEMCOHERENCE) |
| 489 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ | |
| 490 | BATU_VS | BATU_VP) | |
| 72cd4087 | 491 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ |
| c2e49f70 RA |
492 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 493 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ | |
| 494 | BATU_VS | BATU_VP) | |
| 495 | #else | |
| 496 | #define CONFIG_SYS_IBAT3L (0) | |
| 497 | #define CONFIG_SYS_IBAT3U (0) | |
| 498 | #define CONFIG_SYS_IBAT4L (0) | |
| 499 | #define CONFIG_SYS_IBAT4U (0) | |
| 500 | #endif | |
| 501 | ||
| 502 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
| 72cd4087 | 503 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
| c2e49f70 RA |
504 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 505 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ | |
| 506 | BATU_VS | BATU_VP) | |
| 507 | ||
| 72cd4087 | 508 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) |
| c2e49f70 RA |
509 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 510 | ||
| 511 | #if (CONFIG_SYS_DDR_SIZE == 512) | |
| 512 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ | |
| 72cd4087 | 513 | BATL_PP_RW | BATL_MEMCOHERENCE) |
| c2e49f70 RA |
514 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ |
| 515 | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 516 | #else | |
| 517 | #define CONFIG_SYS_IBAT7L (0) | |
| 518 | #define CONFIG_SYS_IBAT7U (0) | |
| 519 | #endif | |
| 520 | ||
| 521 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 522 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 523 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 524 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 525 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 526 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 527 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 528 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 529 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 530 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 531 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 532 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 533 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 534 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 535 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 536 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 537 | ||
| c2e49f70 RA |
538 | #if defined(CONFIG_CMD_KGDB) |
| 539 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
| c2e49f70 RA |
540 | #endif |
| 541 | ||
| 542 | /* | |
| 543 | * Environment Configuration | |
| 544 | */ | |
| 545 | #define CONFIG_ENV_OVERWRITE | |
| 546 | ||
| 547 | #if defined(CONFIG_TSEC_ENET) | |
| 548 | #define CONFIG_HAS_ETH0 | |
| 549 | #define CONFIG_HAS_ETH1 | |
| 550 | #endif | |
| 551 | ||
| 552 | #define CONFIG_HOSTNAME VME8349 | |
| 8b3637c6 | 553 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
| b3f44c21 | 554 | #define CONFIG_BOOTFILE "uImage" |
| c2e49f70 | 555 | |
| 79f516bc | 556 | #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ |
| c2e49f70 RA |
557 | |
| 558 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
| 559 | #undef CONFIG_BOOTARGS /* boot command will set bootargs */ | |
| 560 | ||
| 1dee9be6 | 561 | #define CONFIG_BAUDRATE 9600 |
| c2e49f70 RA |
562 | |
| 563 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 564 | "netdev=eth0\0" \ | |
| 565 | "hostname=vme8349\0" \ | |
| 566 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 567 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 568 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 569 | "addip=setenv bootargs ${bootargs} " \ | |
| 570 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 571 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 572 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 573 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 574 | "bootm ${kernel_addr}\0" \ | |
| 575 | "flash_self=run ramargs addip addtty;" \ | |
| 576 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 577 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 578 | "bootm\0" \ | |
| 579 | "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ | |
| 580 | "update=protect off fff00000 fff3ffff; " \ | |
| 581 | "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ | |
| 582 | "upd=run load update\0" \ | |
| 79f516bc | 583 | "fdtaddr=780000\0" \ |
| c2e49f70 RA |
584 | "fdtfile=vme8349.dtb\0" \ |
| 585 | "" | |
| 586 | ||
| c7357a2b JH |
587 | #define CONFIG_NFSBOOTCOMMAND \ |
| 588 | "setenv bootargs root=/dev/nfs rw " \ | |
| 589 | "nfsroot=$serverip:$rootpath " \ | |
| 590 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
| 591 | "$netdev:off " \ | |
| 592 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 593 | "tftp $loadaddr $bootfile;" \ | |
| 594 | "tftp $fdtaddr $fdtfile;" \ | |
| 595 | "bootm $loadaddr - $fdtaddr" | |
| c2e49f70 RA |
596 | |
| 597 | #define CONFIG_RAMBOOTCOMMAND \ | |
| c7357a2b JH |
598 | "setenv bootargs root=/dev/ram rw " \ |
| 599 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 600 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 601 | "tftp $loadaddr $bootfile;" \ | |
| 602 | "tftp $fdtaddr $fdtfile;" \ | |
| 603 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| c2e49f70 RA |
604 | |
| 605 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 606 | ||
| 1dee9be6 RA |
607 | #ifndef __ASSEMBLY__ |
| 608 | int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, | |
| 609 | unsigned char *buffer, int len); | |
| 610 | #endif | |
| 611 | ||
| c2e49f70 | 612 | #endif /* __CONFIG_H */ |