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Commit | Line | Data |
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84c7204b MS |
1 | /* |
2 | * Configuration for Xilinx ZynqMP | |
3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. | |
4 | * Michal Simek <michal.simek@xilinx.com> | |
5 | * | |
6 | * Based on Configuration for Versatile Express | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #ifndef __XILINX_ZYNQMP_H | |
12 | #define __XILINX_ZYNQMP_H | |
13 | ||
14 | #define CONFIG_REMAKE_ELF | |
15 | ||
16 | /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ | |
17 | ||
18 | #define CONFIG_SYS_NO_FLASH | |
19 | ||
84c7204b MS |
20 | /* Generic Interrupt Controller Definitions */ |
21 | #define CONFIG_GICV2 | |
22 | #define GICD_BASE 0xF9010000 | |
23 | #define GICC_BASE 0xF9020000 | |
24 | ||
d759512f MS |
25 | #define CONFIG_SYS_ALT_MEMTEST |
26 | #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 | |
27 | ||
8d59d7f6 MS |
28 | #ifndef CONFIG_NR_DRAM_BANKS |
29 | # define CONFIG_NR_DRAM_BANKS 2 | |
30 | #endif | |
31 | #define CONFIG_SYS_MEMTEST_START 0 | |
32 | #define CONFIG_SYS_MEMTEST_END 1000 | |
84c7204b MS |
33 | |
34 | /* Have release address at the end of 256MB for now */ | |
35 | #define CPU_RELEASE_ADDR 0xFFFFFF0 | |
36 | ||
37 | /* Cache Definitions */ | |
222b2129 | 38 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
84c7204b | 39 | |
15c3eb53 MS |
40 | #if !defined(CONFIG_IDENT_STRING) |
41 | # define CONFIG_IDENT_STRING " Xilinx ZynqMP" | |
42 | #endif | |
84c7204b | 43 | |
8d59d7f6 | 44 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE |
84c7204b | 45 | |
84c7204b | 46 | /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ |
713b6164 MS |
47 | #if !defined(COUNTER_FREQUENCY) |
48 | # define COUNTER_FREQUENCY 100000000 | |
49 | #endif | |
84c7204b MS |
50 | |
51 | /* Size of malloc() pool */ | |
16fa00a7 | 52 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000) |
84c7204b MS |
53 | |
54 | /* Serial setup */ | |
636ac181 MS |
55 | #define CONFIG_ARM_DCC |
56 | #define CONFIG_CPU_ARMV8 | |
57 | #define CONFIG_ZYNQ_SERIAL | |
84c7204b MS |
58 | |
59 | #define CONFIG_CONS_INDEX 0 | |
60 | #define CONFIG_BAUDRATE 115200 | |
61 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
62 | { 4800, 9600, 19200, 38400, 57600, 115200 } | |
63 | ||
64 | /* Command line configuration */ | |
65 | #define CONFIG_CMD_ENV | |
84c7204b | 66 | #define CONFIG_DOS_PARTITION |
07654ba1 | 67 | #define CONFIG_EFI_PARTITION |
5cb24200 | 68 | #define CONFIG_MP |
84c7204b | 69 | |
cb7ea820 MS |
70 | /* BOOTP options */ |
71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_GATEWAY | |
74 | #define CONFIG_BOOTP_HOSTNAME | |
75 | #define CONFIG_BOOTP_MAY_FAIL | |
76 | #define CONFIG_BOOTP_SERVERIP | |
77 | ||
ce0335f2 | 78 | #if defined(CONFIG_ZYNQ_SDHCI) |
84c7204b MS |
79 | # define CONFIG_MMC |
80 | # define CONFIG_GENERIC_MMC | |
81 | # define CONFIG_SDHCI | |
f3bd7280 MS |
82 | # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ |
83 | # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 | |
84 | # endif | |
46f68e68 MS |
85 | #endif |
86 | ||
87 | #if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB) | |
84c7204b | 88 | # define CONFIG_FAT_WRITE |
84c7204b MS |
89 | #endif |
90 | ||
78cb965a SDPP |
91 | #ifdef CONFIG_NAND_ARASAN |
92 | # define CONFIG_CMD_NAND | |
93 | # define CONFIG_CMD_NAND_LOCK_UNLOCK | |
94 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
95 | # define CONFIG_SYS_NAND_SELF_INIT | |
96 | # define CONFIG_SYS_NAND_ONFI_DETECTION | |
97 | # define CONFIG_MTD_DEVICE | |
98 | #endif | |
99 | ||
84c7204b MS |
100 | /* Miscellaneous configurable options */ |
101 | #define CONFIG_SYS_LOAD_ADDR 0x8000000 | |
102 | ||
16fa00a7 | 103 | #if defined(CONFIG_ZYNQMP_USB) |
0f676767 SDPP |
104 | #define CONFIG_USB_XHCI_DWC3 |
105 | #define CONFIG_USB_XHCI | |
106 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
107 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
0f676767 SDPP |
108 | #define CONFIG_USB_STORAGE |
109 | #define CONFIG_USB_XHCI_ZYNQMP | |
110 | ||
16fa00a7 SDPP |
111 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 |
112 | #define DFU_DEFAULT_POLL_TIMEOUT 300 | |
113 | #define CONFIG_USB_FUNCTION_DFU | |
114 | #define CONFIG_DFU_RAM | |
16fa00a7 | 115 | #define CONFIG_USB_CABLE_CHECK |
16fa00a7 SDPP |
116 | #define CONFIG_CMD_THOR_DOWNLOAD |
117 | #define CONFIG_USB_FUNCTION_THOR | |
118 | #define CONFIG_THOR_RESET_OFF | |
119 | #define DFU_ALT_INFO_RAM \ | |
120 | "dfu_ram_info=" \ | |
0e43140b | 121 | "setenv dfu_alt_info " \ |
1b19daf4 SDPP |
122 | "Image ram $kernel_addr $kernel_size\\\\;" \ |
123 | "system.dtb ram $fdt_addr $fdt_size\0" \ | |
16fa00a7 SDPP |
124 | "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ |
125 | "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" | |
126 | ||
127 | #define DFU_ALT_INFO \ | |
128 | DFU_ALT_INFO_RAM | |
129 | #endif | |
130 | ||
131 | #if !defined(DFU_ALT_INFO) | |
132 | # define DFU_ALT_INFO | |
133 | #endif | |
134 | ||
84c7204b MS |
135 | /* Initial environment variables */ |
136 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
137 | "kernel_addr=0x80000\0" \ | |
138 | "fdt_addr=0x7000000\0" \ | |
139 | "fdt_high=0x10000000\0" \ | |
407b76f9 | 140 | CONFIG_KERNEL_FDT_OFST_SIZE \ |
2d9925bc MS |
141 | "sdbootdev=0\0"\ |
142 | "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ | |
143 | "load mmc $sdbootdev:$partid $kernel_addr Image && " \ | |
144 | "booti $kernel_addr - $fdt_addr\0" \ | |
16fa00a7 | 145 | DFU_ALT_INFO |
84c7204b | 146 | |
84c7204b MS |
147 | #define CONFIG_PREBOOT "run bootargs" |
148 | #define CONFIG_BOOTCOMMAND "run $modeboot" | |
5cfd9182 | 149 | #define CONFIG_BOOTDELAY 3 |
84c7204b MS |
150 | |
151 | #define CONFIG_BOARD_LATE_INIT | |
152 | ||
153 | /* Do not preserve environment */ | |
154 | #define CONFIG_ENV_IS_NOWHERE 1 | |
155 | #define CONFIG_ENV_SIZE 0x1000 | |
156 | ||
157 | /* Monitor Command Prompt */ | |
158 | /* Console I/O Buffer Size */ | |
159 | #define CONFIG_SYS_CBSIZE 2048 | |
84c7204b MS |
160 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
161 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
84c7204b MS |
162 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
163 | #define CONFIG_SYS_LONGHELP | |
164 | #define CONFIG_CMDLINE_EDITING | |
165 | #define CONFIG_SYS_MAXARGS 64 | |
166 | ||
cb7ea820 | 167 | /* Ethernet driver */ |
596e5782 | 168 | #if defined(CONFIG_ZYNQ_GEM) |
cb7ea820 | 169 | # define CONFIG_NET_MULTI |
cb7ea820 MS |
170 | # define CONFIG_MII |
171 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
cb7ea820 | 172 | # define CONFIG_PHY_MARVELL |
f96fe2c0 | 173 | # define CONFIG_PHY_NATSEMI |
bf146325 | 174 | # define CONFIG_PHY_TI |
c4c96f2b | 175 | # define CONFIG_PHY_GIGE |
e2928f32 | 176 | # define PHY_ANEG_TIMEOUT 20000 |
cb7ea820 MS |
177 | #endif |
178 | ||
2594e03c SDPP |
179 | /* I2C */ |
180 | #if defined(CONFIG_SYS_I2C_ZYNQ) | |
2594e03c SDPP |
181 | # define CONFIG_SYS_I2C |
182 | # define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 | |
183 | # define CONFIG_SYS_I2C_ZYNQ_SLAVE 0 | |
184 | #endif | |
185 | ||
2594e03c SDPP |
186 | /* EEPROM */ |
187 | #ifdef CONFIG_ZYNQMP_EEPROM | |
188 | # define CONFIG_CMD_EEPROM | |
189 | # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
190 | # define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
191 | # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
192 | # define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
193 | # define CONFIG_SYS_EEPROM_SIZE (64 * 1024) | |
194 | #endif | |
195 | ||
6fe6f135 MS |
196 | #ifdef CONFIG_AHCI |
197 | #define CONFIG_LIBATA | |
198 | #define CONFIG_SCSI_AHCI | |
199 | #define CONFIG_SCSI_AHCI_PLAT | |
679b994a | 200 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 |
6fe6f135 MS |
201 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
202 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
203 | CONFIG_SYS_SCSI_MAX_LUN) | |
204 | #define CONFIG_CMD_SCSI | |
205 | #endif | |
206 | ||
84c7204b MS |
207 | #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) |
208 | ||
209 | #define CONFIG_CMD_BOOTI | |
210 | #define CONFIG_CMD_UNZIP | |
211 | ||
212 | #define CONFIG_BOARD_EARLY_INIT_R | |
213 | #define CONFIG_CLOCKS | |
214 | ||
215 | #endif /* __XILINX_ZYNQMP_H */ |