Merge branch 'master' of git://git.denx.de/u-boot-ubi

diff --git a/Kconfig b/Kconfig
index 4b462166656074d5979dee513b80c5c1c1deac02..817f4f08a02f0806a0d1d63c04e0e1e6829abf07 100644 (file)
--- a/Kconfig
+++ b/Kconfig
@@ -183,6 +183,11 @@ config FIT
          verified boot (secure boot using RSA). This option enables that
          feature.
 
+config SPL_FIT
+       bool "Support Flattened Image Tree within SPL"
+       depends on FIT
+       depends on SPL
+
 config FIT_VERBOSE
        bool "Display verbose messages on FIT boot"
        depends on FIT
@@ -205,6 +210,12 @@ config FIT_SIGNATURE
          format support in this case, enable it using
          CONFIG_IMAGE_FORMAT_LEGACY.
 
+config SPL_FIT_SIGNATURE
+       bool "Enable signature verification of FIT firmware within SPL"
+       depends on SPL_FIT
+       depends on SPL_DM
+       select SPL_RSA
+
 config FIT_BEST_MATCH
        bool "Select the best match for the kernel device tree"
        depends on FIT

diff --git a/README b/README
index 1d0b946977b22cc9a746515d4a9779b68b6bd64b..03bed180591a7a0cafd003f53b889991c183741e 100644 (file)
--- a/README
+++ b/README
@@ -4824,6 +4824,11 @@ Low Level (hardware related) configuration options:
                other boot loader or by a debugger which performs
                these initializations itself.
 
+- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+               [ARM926EJ-S only] This allows just the call to lowlevel_init()
+               to be skipped. The normal CPU15 init (such as enabling the
+               instruction cache) is still performed.
+
 - CONFIG_SPL_BUILD
                Modifies the behaviour of start.S when compiling a loader
                that is executed before the actual U-Boot. E.g. when

diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index b6f7724931ceab6dd674b56920e9134a4fe62c28..42e7f22b28ddb4ea2db55b6eef8c5558bbb3ecf6 100644 (file)
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -10,6 +10,46 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
+#ifdef CONFIG_ISA_ARCV2
+
+/*
+ * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
+ * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
+ *
+ * Explicit barrier provided by DMB instruction
+ *  - Operand supports fine grained load/store/load+store semantics
+ *  - Ensures that selected memory operation issued before it will complete
+ *    before any subsequent memory operation of same type
+ *  - DMB guarantees SMP as well as local barrier semantics
+ *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
+ *    UP: barrier(), SMP: smp_*mb == *mb)
+ *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
+ *    in the general case. Plus it only provides full barrier.
+ */
+
+#define mb()   asm volatile("dmb 3\n" : : : "memory")
+#define rmb()  asm volatile("dmb 1\n" : : : "memory")
+#define wmb()  asm volatile("dmb 2\n" : : : "memory")
+
+#else
+
+/*
+ * ARCompact based cores (ARC700) only have SYNC instruction which is super
+ * heavy weight as it flushes the pipeline as well.
+ * There are no real SMP implementations of such cores.
+ */
+
+#define mb()   asm volatile("sync\n" : : : "memory")
+#endif
+
+#ifdef CONFIG_ISA_ARCV2
+#define __iormb()              rmb()
+#define __iowmb()              wmb()
+#else
+#define __iormb()              do { } while (0)
+#define __iowmb()              do { } while (0)
+#endif
+
 /*
  * Given a physical address and a length, return a virtual address
  * that can be used to access the memory range with the caching
@@ -72,18 +112,6 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
        return w;
 }
 
-#define readb __raw_readb
-
-static inline u16 readw(const volatile void __iomem *addr)
-{
-       return __le16_to_cpu(__raw_readw(addr));
-}
-
-static inline u32 readl(const volatile void __iomem *addr)
-{
-       return __le32_to_cpu(__raw_readl(addr));
-}
-
 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
 {
        __asm__ __volatile__("stb%U1    %0, %1\n"
@@ -108,10 +136,6 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr)
                             : "memory");
 }
 
-#define writeb __raw_writeb
-#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
-#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
-
 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
 {
        __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
@@ -184,6 +208,45 @@ static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
        return longlen;
 }
 
+/*
+ * MMIO can also get buffered/optimized in micro-arch, so barriers needed
+ * Based on ARM model for the typical use case
+ *
+ *     <ST [DMA buffer]>
+ *     <writel MMIO "go" reg>
+ *  or:
+ *     <readl MMIO "status" reg>
+ *     <LD [DMA buffer]>
+ *
+ * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
+ */
+#define readb(c)               ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)               ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)               ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)            ({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c)            ({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c)            ({ __iowmb(); writel_relaxed(v,c); })
+
+/*
+ * Relaxed API for drivers which can handle barrier ordering themselves
+ *
+ * Also these are defined to perform little endian accesses.
+ * To provide the typical device register semantics of fixed endian,
+ * swap the byte order for Big Endian
+ *
+ * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
+ */
+#define readb_relaxed(c)       __raw_readb(c)
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+                                       __raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+                                       __raw_readl(c)); __r; })
+
+#define writeb_relaxed(v,c)    __raw_writeb(v,c)
+#define writew_relaxed(v,c)    __raw_writew((__force u16) cpu_to_le16(v),c)
+#define writel_relaxed(v,c)    __raw_writel((__force u32) cpu_to_le32(v),c)
+
 #define out_arch(type, endian, a, v)   __raw_write##type(cpu_to_##endian(v), a)
 #define in_arch(type, endian, a)       endian##_to_cpu(__raw_read##type(a))
 

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index d1fb66153771a607a56afde1bc67bbe95dab743d..b6ec83112cd8aa5264d9572c9ef97fbf0f9462ce 100644 (file)
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -209,6 +209,9 @@ void cache_init(void)
        read_decode_cache_bcr_arcv2();
 
        if (ioc_exists) {
+               flush_dcache_all();
+               invalidate_dcache_all();
+
                /* IO coherency base - 0x8z */
                write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
                /* IO coherency aperture size - 512Mb: 0x8z-0xAz */
@@ -417,13 +420,10 @@ void flush_cache(unsigned long start, unsigned long size)
 
 void invalidate_dcache_all(void)
 {
-#ifdef CONFIG_ISA_ARCV2
-       if (!ioc_exists)
-#endif
-               __dc_entire_op(OP_INV);
+       __dc_entire_op(OP_INV);
 
 #ifdef CONFIG_ISA_ARCV2
-       if (slc_exists && !ioc_exists)
+       if (slc_exists)
                __slc_entire_op(OP_INV);
 #endif
 }

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e75c4c0fa6df5a2f9f8a928458d2f290ec6e5205..80a3f93ad9d329672dfa10a02bf31d02508476bd 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -441,6 +441,10 @@ config TARGET_TI816X_EVM
        select CPU_V7
        select SUPPORT_SPL
 
+config TARGET_BCM23550_W1D
+       bool "Support bcm23550_w1d"
+       select CPU_V7
+
 config TARGET_BCM28155_AP
        bool "Support bcm28155_ap"
        select CPU_V7
@@ -557,6 +561,10 @@ config RMOBILE
        bool "Renesas ARM SoCs"
        select CPU_V7
 
+config TARGET_S32V234EVB
+       bool "Support s32v234evb"
+       select ARM64
+
 config ARCH_SNAPDRAGON
        bool "Qualcomm Snapdragon SoCs"
        select ARM64
@@ -898,6 +906,7 @@ source "board/armadeus/apf27/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
+source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
@@ -929,6 +938,7 @@ source "board/freescale/mx53ard/Kconfig"
 source "board/freescale/mx53evk/Kconfig"
 source "board/freescale/mx53loco/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
+source "board/freescale/s32v234evb/Kconfig"
 source "board/freescale/vf610twr/Kconfig"
 source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"

diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 3ebdfddc8098a4de195166de4f30c43fdba1f07b..2f8fd6acc20e52b1e18d5049a1db78e9f09bc425 100644 (file)
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -82,6 +82,7 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * Jump to board specific initialization... The Mask ROM will have already initialized
         * basic memory.  Go here to bump up clock rate and handle wake up conditions.
@@ -89,5 +90,6 @@ cpu_init_crit:
        mov     ip, lr          /* persevere link reg across call */
        bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
+#endif
        mov     pc, lr          /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 69cabebed91edbba882b5b7821f22aaaa3969bcc..3ada6d026fa9d37036a0bf0978e4f0c22930d9de 100644 (file)
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -135,6 +135,7 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependend, you will
@@ -143,7 +144,7 @@ cpu_init_crit:
        mov     ip, lr
 
        bl      lowlevel_init
-
        mov     lr, ip
+#endif
        mov     pc, lr
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index a6af0fcb36eef20d0bb650d9b5b3419b685f46df..229862079a329ac8639aeef2884d395c439e1f71 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -167,9 +167,9 @@ const char *get_imx_type(u32 imxtype)
 {
        switch (imxtype) {
        case MXC_CPU_MX23:
-               return "23";    /* Quad-Plus version of the mx6 */
+               return "23";
        case MXC_CPU_MX28:
-               return "28";    /* Dual-Plus version of the mx6 */
+               return "28";
        default:
                return "??";
        }

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index f05113da9df21ff5a28ebc644fc83bf5399f8606..959d1ed86d8af82c62a1f497aa90c50d3f109318 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -101,11 +101,13 @@ flush_dcache:
 #endif
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
        bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
+#endif
        mov     pc, lr          /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 214cd8cbd9070f36feaa046bcd56f163fe245ae7..51053c32dc11dd54aa2c9c21be917fc1c2b57028 100644 (file)
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -90,11 +90,13 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
        bl      lowlevel_init   /* go setup memory */
        mov     lr, ip          /* restore link */
+#endif
        mov     pc, lr          /* back to my caller */
 #endif

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 328c4b10e9768f67724f0ded8b1382f8dbafdcd5..0a5ac97df0d0a7f60ddda86952c75ab7a4e0520e 100644 (file)
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -38,6 +38,7 @@ obj-y += s5p-common/
 endif
 
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
+obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/

diff --git a/arch/arm/cpu/armv7/bcm235xx/Makefile b/arch/arm/cpu/armv7/bcm235xx/Makefile
new file mode 100644 (file)
index 0000000..7fdb263
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += clk-core.o
+obj-y  += clk-bcm235xx.o
+obj-y  += clk-sdio.o
+obj-y  += clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y  += clk-usb-otg.o

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
new file mode 100644 (file)
index 0000000..ce3d019
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
@@ -0,0 +1,573 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ *
+ * bcm235xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K               1000
+#define CLOCK_1M               (CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+       .clk    =       { \
+               .name   =       #clk_name, \
+               .parent =       clk_parent, \
+               .rate   =       clk_rate, \
+               .div    =       clk_div, \
+               .ops    =       &ref_clk_ops, \
+       }, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal,   0,              26  * CLOCK_1M, 1);
+DECLARE_REF_CLK(var_96m,       0,              96  * CLOCK_1M, 1);
+DECLARE_REF_CLK(ref_96m,       0,              96  * CLOCK_1M, 1);
+DECLARE_REF_CLK(ref_312m,      0,              312 * CLOCK_1M, 0);
+DECLARE_REF_CLK(ref_104m,      &ref_312m.clk,  104 * CLOCK_1M, 3);
+DECLARE_REF_CLK(ref_52m,       &ref_104m.clk,  52  * CLOCK_1M, 2);
+DECLARE_REF_CLK(ref_13m,       &ref_52m.clk,   13  * CLOCK_1M, 4);
+DECLARE_REF_CLK(var_312m,      0,              312 * CLOCK_1M, 0);
+DECLARE_REF_CLK(var_104m,      &var_312m.clk,  104 * CLOCK_1M, 3);
+DECLARE_REF_CLK(var_52m,       &var_104m.clk,  52  * CLOCK_1M, 2);
+DECLARE_REF_CLK(var_13m,       &var_52m.clk,   13  * CLOCK_1M, 4);
+
+struct refclk_lkup {
+       struct refclk *procclk;
+       const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+       MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+       MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+       MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+       MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+       int i;
+       struct refclk_lkup *tblp = refclk_str_tbl;
+       for (i = 0; i < refclk_entries; i++, tblp++) {
+               if (!(strcmp(name, tblp->name)))
+                       return tblp->procclk;
+       }
+       return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+       26 * CLOCK_1M,
+       52 * CLOCK_1M,
+       104 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       208 * CLOCK_1M,
+       312 * CLOCK_1M,
+       312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+       26 * CLOCK_1M,
+       52 * CLOCK_1M,
+       52 * CLOCK_1M,
+       52 * CLOCK_1M,
+       78 * CLOCK_1M,
+       104 * CLOCK_1M,
+       104 * CLOCK_1M,
+       156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+       26 * CLOCK_1M,
+       52 * CLOCK_1M,
+       78 * CLOCK_1M,
+       104 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+       26 * CLOCK_1M,
+       26 * CLOCK_1M,
+       39 * CLOCK_1M,
+       52 * CLOCK_1M,
+       52 * CLOCK_1M,
+       78 * CLOCK_1M
+};
+
+unsigned long esub_freq_tbl[8] = {
+       78 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       208 * CLOCK_1M,
+       208 * CLOCK_1M,
+       208 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+       .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+       .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+       .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+       .gate           = HW_SW_GATE(0x0358, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_52m",
+                                "ref_52m",
+                                "var_96m",
+                                "ref_96m"),
+       .sel            = SELECTOR(0x0a28, 0, 3),
+       .div            = DIVIDER(0x0a28, 4, 14),
+       .trig           = TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+       .gate           = HW_SW_GATE(0x035c, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_52m",
+                                "ref_52m",
+                                "var_96m",
+                                "ref_96m"),
+       .sel            = SELECTOR(0x0a2c, 0, 3),
+       .div            = DIVIDER(0x0a2c, 4, 14),
+       .trig           = TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+       .gate           = HW_SW_GATE(0x0364, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_52m",
+                                "ref_52m",
+                                "var_96m",
+                                "ref_96m"),
+       .sel            = SELECTOR(0x0a34, 0, 3),
+       .div            = DIVIDER(0x0a34, 4, 14),
+       .trig           = TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+       .gate           = HW_SW_GATE(0x0360, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_52m",
+                                "ref_52m",
+                                "var_96m",
+                                "ref_96m"),
+       .sel            = SELECTOR(0x0a30, 0, 3),
+       .div            = DIVIDER(0x0a30, 4, 14),
+       .trig           = TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+       .clocks         = CLOCKS("ref_32k"),
+       .gate           = SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+       .clocks         = CLOCKS("ref_32k"),
+       .gate           = SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+       .clocks         = CLOCKS("ref_32k"),
+       .gate           = SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+       .clocks         = CLOCKS("ref_32k"),
+       .gate           = SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data usb_otg_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+       .gate           = HW_SW_GATE(0x0458, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_104m",
+                                "ref_104m",
+                                "var_13m",
+                                "ref_13m"),
+       .sel            = SELECTOR(0x0a64, 0, 3),
+       .trig           = TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+       .gate           = HW_SW_GATE(0x045c, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_104m",
+                                "ref_104m",
+                                "var_13m",
+                                "ref_13m"),
+       .sel            = SELECTOR(0x0a68, 0, 3),
+       .trig           = TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+       .gate           = HW_SW_GATE(0x0484, 18, 2, 3),
+       .clocks         = CLOCKS("ref_crystal",
+                                "var_104m",
+                                "ref_104m",
+                                "var_13m",
+                                "ref_13m"),
+       .sel            = SELECTOR(0x0a84, 0, 3),
+       .trig           = TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+       .clk = {
+               .name = "kpm_ccu_clk",
+               .ops = &ccu_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .num_policy_masks = 1,
+       .policy_freq_offset = 0x00000008,
+       .freq_bit_shift = 8,
+       .policy_ctl_offset = 0x0000000c,
+       .policy0_mask_offset = 0x00000010,
+       .policy1_mask_offset = 0x00000014,
+       .policy2_mask_offset = 0x00000018,
+       .policy3_mask_offset = 0x0000001c,
+       .lvm_en_offset = 0x00000034,
+       .freq_id = 2,
+       .freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+       .clk = {
+               .name = "kps_ccu_clk",
+               .ops = &ccu_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+       },
+       .num_policy_masks = 2,
+       .policy_freq_offset = 0x00000008,
+       .freq_bit_shift = 8,
+       .policy_ctl_offset = 0x0000000c,
+       .policy0_mask_offset = 0x00000010,
+       .policy1_mask_offset = 0x00000014,
+       .policy2_mask_offset = 0x00000018,
+       .policy3_mask_offset = 0x0000001c,
+       .policy0_mask2_offset = 0x00000048,
+       .policy1_mask2_offset = 0x0000004c,
+       .policy2_mask2_offset = 0x00000050,
+       .policy3_mask2_offset = 0x00000054,
+       .lvm_en_offset = 0x00000034,
+       .freq_id = 2,
+       .freq_tbl = slave_axi_freq_tbl,
+};
+
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+       .clk = {
+               .name = "esub_ccu_clk",
+               .ops = &ccu_clk_ops,
+               .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+       },
+       .num_policy_masks = 1,
+       .policy_freq_offset = 0x00000008,
+       .freq_bit_shift = 8,
+       .policy_ctl_offset = 0x0000000c,
+       .policy0_mask_offset = 0x00000010,
+       .policy1_mask_offset = 0x00000014,
+       .policy2_mask_offset = 0x00000018,
+       .policy3_mask_offset = 0x0000001c,
+       .lvm_en_offset = 0x00000034,
+       .freq_id = 2,
+       .freq_tbl = esub_freq_tbl,
+};
+#endif
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+       .clk = {
+               .name = "usb_otg_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &usb_otg_ahb_data,
+};
+
+static struct bus_clock sdio1_ahb_clk = {
+       .clk = {
+               .name = "sdio1_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+       .clk = {
+               .name = "sdio2_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+       .clk = {
+               .name = "sdio3_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+       .clk = {
+               .name = "sdio4_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+       .clk = {
+               .name = "bsc1_apb_clk",
+               .parent = &kps_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+       },
+       .freq_tbl = slave_apb_freq_tbl,
+       .data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+       .clk = {
+               .name = "bsc2_apb_clk",
+               .parent = &kps_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+               },
+       .freq_tbl = slave_apb_freq_tbl,
+       .data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+       .clk = {
+               .name = "bsc3_apb_clk",
+               .parent = &kps_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+               },
+       .freq_tbl = slave_apb_freq_tbl,
+       .data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+       .clk = {
+               .name = "sdio1_clk",
+               .parent = &ref_52m.clk,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+       .clk = {
+               .name = "sdio2_clk",
+               .parent = &ref_52m.clk,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+       .clk = {
+               .name = "sdio3_clk",
+               .parent = &ref_52m.clk,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+       .clk = {
+               .name = "sdio4_clk",
+               .parent = &ref_52m.clk,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+       .clk = {
+               .name = "sdio1_sleep_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+       .clk = {
+               .name = "sdio2_sleep_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+       .clk = {
+               .name = "sdio3_sleep_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+       .clk = {
+               .name = "sdio4_sleep_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+       .clk = {
+               .name = "bsc1_clk",
+               .parent = &ref_13m.clk,
+               .rate = 13 * CLOCK_1M,
+               .div = 1,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+       },
+       .data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+       .clk = {
+               .name = "bsc2_clk",
+               .parent = &ref_13m.clk,
+               .rate = 13 * CLOCK_1M,
+               .div = 1,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+       },
+       .data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+       .clk = {
+               .name = "bsc3_clk",
+               .parent = &ref_13m.clk,
+               .rate = 13 * CLOCK_1M,
+               .div = 1,
+               .ops = &peri_clk_ops,
+               .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+       },
+       .data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+       /* Peripheral clocks */
+       CLK_LK(sdio1),
+       CLK_LK(sdio2),
+       CLK_LK(sdio3),
+       CLK_LK(sdio4),
+       CLK_LK(sdio1_sleep),
+       CLK_LK(sdio2_sleep),
+       CLK_LK(sdio3_sleep),
+       CLK_LK(sdio4_sleep),
+       CLK_LK(bsc1),
+       CLK_LK(bsc2),
+       CLK_LK(bsc3),
+       /* Bus clocks */
+       CLK_LK(usb_otg_ahb),
+       CLK_LK(sdio1_ahb),
+       CLK_LK(sdio2_ahb),
+       CLK_LK(sdio3_ahb),
+       CLK_LK(sdio4_ahb),
+       CLK_LK(bsc1_apb),
+       CLK_LK(bsc2_apb),
+       CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+       CLK_LK(esub_ccu),
+#endif
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
new file mode 100644 (file)
index 0000000..d263068
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+       int ret;
+       char *bscstr, *apbstr;
+
+       switch ((u32) base) {
+       case PMU_BSC_BASE_ADDR:
+               /* PMU clock is always enabled */
+               return 0;
+       case BSC1_BASE_ADDR:
+               bscstr = "bsc1_clk";
+               apbstr = "bsc1_apb_clk";
+               break;
+       case BSC2_BASE_ADDR:
+               bscstr = "bsc2_clk";
+               apbstr = "bsc2_apb_clk";
+               break;
+       case BSC3_BASE_ADDR:
+               bscstr = "bsc3_clk";
+               apbstr = "bsc3_apb_clk";
+               break;
+       default:
+               printf("%s: base 0x%p not found\n", __func__, base);
+               return -EINVAL;
+       }
+
+       /* Note that the bus clock must be enabled first */
+
+       ret = clk_get_and_enable(apbstr);
+       if (ret)
+               return ret;
+
+       ret = clk_get_and_enable(bscstr);
+       if (ret)
+               return ret;
+
+       return 0;
+}

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
new file mode 100644 (file)
index 0000000..2b5da6b
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ *
+ * bcm235xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
+#define WR_ACCESS_OFFSET       0       /* common to all clock blocks */
+#define POLICY_CTL_GO          1       /* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL      4       /* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+       int ret = 0;
+       struct clk *c;
+
+       debug("%s: %s\n", __func__, clkstr);
+
+       c = clk_get(clkstr);
+       if (c) {
+               ret = clk_enable(c);
+               if (ret)
+                       return ret;
+       } else {
+               printf("%s: Couldn't find %s\n", __func__, clkstr);
+               return -EINVAL;
+       }
+       return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear). Delay
+ * a microsecond after each read of the register. Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+       unsigned int tries;
+       u32 bit_mask = 1 << bit;
+
+       for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+               u32 val;
+               bool bit_val;
+
+               val = readl(base + offset);
+               bit_val = (val & bit_mask) ? 1 : 0;
+               if (bit_val == want)
+                       return 0;       /* success */
+               udelay(1);
+       }
+
+       debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+             __func__, base + offset, bit, want);
+
+       return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+       int ret = 0;
+       u32 reg;
+       struct peri_clock *peri_clk = to_peri_clk(c);
+       struct peri_clk_data *cd = peri_clk->data;
+       struct bcm_clk_gate *gate = &cd->gate;
+       void *base = (void *)c->ccu_clk_mgr_base;
+
+
+       debug("%s: %s\n", __func__, c->name);
+
+       clk_get_rate(c);        /* Make sure rate and sel are filled in */
+
+       /* enable access */
+       writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+       if (enable) {
+               debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+                     __func__, c->name, c->rate, c->div, c->sel,
+                     c->parent->rate);
+
+               /*
+                * clkgate - only software controllable gates are
+                * supported by u-boot which includes all clocks
+                * that matter. This avoids bringing in a lot of extra
+                * complexity as done in the kernel framework.
+                */
+               if (gate_exists(gate)) {
+                       reg = readl(base + cd->gate.offset);
+                       reg |= (1 << cd->gate.en_bit);
+                       writel(reg, base + cd->gate.offset);
+               }
+
+               /* div and pll select */
+               if (divider_exists(&cd->div)) {
+                       reg = readl(base + cd->div.offset);
+                       bitfield_replace(reg, cd->div.shift, cd->div.width,
+                                        c->div - 1);
+                       writel(reg, base + cd->div.offset);
+               }
+
+               /* frequency selector */
+               if (selector_exists(&cd->sel)) {
+                       reg = readl(base + cd->sel.offset);
+                       bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+                                        c->sel);
+                       writel(reg, base + cd->sel.offset);
+               }
+
+               /* trigger */
+               if (trigger_exists(&cd->trig)) {
+                       writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+                       /* wait for trigger status bit to go to 0 */
+                       ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+                       if (ret)
+                               return ret;
+               }
+
+               /* wait for running (status_bit = 1) */
+               ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+               if (ret)
+                       return ret;
+       } else {
+               debug("%s disable clock %s\n", __func__, c->name);
+
+               /* clkgate */
+               reg = readl(base + cd->gate.offset);
+               reg &= ~(1 << cd->gate.en_bit);
+               writel(reg, base + cd->gate.offset);
+
+               /* wait for stop (status_bit = 0) */
+               ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+       }
+
+       /* disable access */
+       writel(0, base + WR_ACCESS_OFFSET);
+
+       return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+       int ret = 0;
+       int i;
+       unsigned long diff;
+       unsigned long new_rate = 0, div = 1;
+       struct peri_clock *peri_clk = to_peri_clk(c);
+       struct peri_clk_data *cd = peri_clk->data;
+       const char **clock;
+
+       debug("%s: %s\n", __func__, c->name);
+       diff = rate;
+
+       i = 0;
+       for (clock = cd->clocks; *clock; clock++, i++) {
+               struct refclk *ref = refclk_str_to_clk(*clock);
+               if (!ref) {
+                       printf("%s: Lookup of %s failed\n", __func__, *clock);
+                       return -EINVAL;
+               }
+
+               /* round to the new rate */
+               div = ref->clk.rate / rate;
+               if (div == 0)
+                       div = 1;
+
+               new_rate = ref->clk.rate / div;
+
+               /* get the min diff */
+               if (abs(new_rate - rate) < diff) {
+                       diff = abs(new_rate - rate);
+                       c->sel = i;
+                       c->parent = &ref->clk;
+                       c->rate = new_rate;
+                       c->div = div;
+               }
+       }
+
+       debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+             c->name, c->rate, c->div, c->sel, c->parent->rate);
+       return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+       struct peri_clock *peri_clk = to_peri_clk(c);
+       struct peri_clk_data *cd = peri_clk->data;
+       void *base = (void *)c->ccu_clk_mgr_base;
+       int div = 1;
+       const char **clock;
+       struct refclk *ref;
+       u32 reg;
+
+       debug("%s: %s\n", __func__, c->name);
+       if (selector_exists(&cd->sel)) {
+               reg = readl(base + cd->sel.offset);
+               c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+       } else {
+               /*
+                * For peri clocks that don't have a selector, the single
+                * reference clock will always exist at index 0.
+                */
+               c->sel = 0;
+       }
+
+       if (divider_exists(&cd->div)) {
+               reg = readl(base + cd->div.offset);
+               div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+               div += 1;
+       }
+
+       clock = cd->clocks;
+       ref = refclk_str_to_clk(clock[c->sel]);
+       if (!ref) {
+               printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+               return 0;
+       }
+
+       c->parent = &ref->clk;
+       c->div = div;
+       c->rate = c->parent->rate / c->div;
+       debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+             c->parent->rate, div, c->sel, c->rate);
+
+       return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+       .enable = peri_clk_enable,
+       .set_rate = peri_clk_set_rate,
+       .get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+       struct ccu_clock *ccu_clk = to_ccu_clk(c);
+       void *base = (void *)c->ccu_clk_mgr_base;
+       int ret = 0;
+       u32 reg;
+
+       debug("%s: %s\n", __func__, c->name);
+       if (!enable)
+               return -EINVAL; /* CCU clock cannot shutdown */
+
+       /* enable access */
+       writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+       /* config enable for policy engine */
+       writel(1, base + ccu_clk->lvm_en_offset);
+
+       /* wait for bit to go to 0 */
+       ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+       if (ret)
+               return ret;
+
+       /* freq ID */
+       if (!ccu_clk->freq_bit_shift)
+               ccu_clk->freq_bit_shift = 8;
+
+       /* Set frequency id for each of the 4 policies */
+       reg = ccu_clk->freq_id |
+           (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+           (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+           (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+       writel(reg, base + ccu_clk->policy_freq_offset);
+
+       /* enable all clock mask */
+       writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+       writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+       writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+       writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+       if (ccu_clk->num_policy_masks == 2) {
+               writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+               writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+               writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+               writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+       }
+
+       /* start policy engine */
+       reg = readl(base + ccu_clk->policy_ctl_offset);
+       reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+       writel(reg, base + ccu_clk->policy_ctl_offset);
+
+       /* wait till started */
+       ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+       if (ret)
+               return ret;
+
+       /* disable access */
+       writel(0, base + WR_ACCESS_OFFSET);
+
+       return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+       struct ccu_clock *ccu_clk = to_ccu_clk(c);
+       debug("%s: %s\n", __func__, c->name);
+       c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+       return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+       .enable = ccu_clk_enable,
+       .get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+       struct bus_clock *bus_clk = to_bus_clk(c);
+       struct bus_clk_data *cd = bus_clk->data;
+       void *base = (void *)c->ccu_clk_mgr_base;
+       int ret = 0;
+       u32 reg;
+
+       debug("%s: %s\n", __func__, c->name);
+       /* enable access */
+       writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+       /* enable gating */
+       reg = readl(base + cd->gate.offset);
+       if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+               debug("%s already %s\n", c->name,
+                     enable ? "enabled" : "disabled");
+       else {
+               int want = (enable) ? 1 : 0;
+               reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+               if (enable)
+                       reg |= (1 << cd->gate.en_bit);
+               else
+                       reg &= ~(1 << cd->gate.en_bit);
+
+               writel(reg, base + cd->gate.offset);
+               ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+                              want);
+               if (ret)
+                       return ret;
+       }
+
+       /* disable access */
+       writel(0, base + WR_ACCESS_OFFSET);
+
+       return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+       struct bus_clock *bus_clk = to_bus_clk(c);
+       struct ccu_clock *ccu_clk;
+
+       debug("%s: %s\n", __func__, c->name);
+       ccu_clk = to_ccu_clk(c->parent);
+
+       c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+       c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+       return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+       .enable = bus_clk_enable,
+       .get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+       debug("%s: %s\n", __func__, c->name);
+       return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+       .enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+       debug("%s:\n", __func__);
+       return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+       int i;
+       struct clk_lookup *clk_tblp;
+
+       debug("%s: %s\n", __func__, con_id);
+
+       clk_tblp = arch_clk_tbl;
+       for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+               if (clk_tblp->con_id) {
+                       if (!con_id || strcmp(clk_tblp->con_id, con_id))
+                               continue;
+                       return clk_tblp->clk;
+               }
+       }
+       return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+       int ret = 0;
+
+       debug("%s: %s\n", __func__, c->name);
+       if (!c->ops || !c->ops->enable)
+               return -1;
+
+       /* enable parent clock first */
+       if (c->parent)
+               ret = clk_enable(c->parent);
+
+       if (ret)
+               return ret;
+
+       if (!c->use_cnt) {
+               c->use_cnt++;
+               ret = c->ops->enable(c, 1);
+       }
+
+       return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+       debug("%s: %s\n", __func__, c->name);
+       if (!c->ops || !c->ops->enable)
+               return;
+
+       if (c->use_cnt) {
+               c->use_cnt--;
+               c->ops->enable(c, 0);
+       }
+
+       /* disable parent */
+       if (c->parent)
+               clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+       unsigned long rate;
+
+       debug("%s: %s\n", __func__, c->name);
+       if (!c || !c->ops || !c->ops->get_rate)
+               return 0;
+
+       rate = c->ops->get_rate(c);
+       debug("%s: rate = %ld\n", __func__, rate);
+       return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+       int ret;
+
+       debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+       if (!c || !c->ops || !c->ops->set_rate)
+               return -EINVAL;
+
+       if (c->use_cnt)
+               return -EINVAL;
+
+       ret = c->ops->set_rate(c, rate);
+
+       return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.h b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
new file mode 100644 (file)
index 0000000..de9a1ef
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+       printf("Write [0x%p] = 0x%08x\n", addr, val);
+       *(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+       u32 val = *(u32 *)addr;
+       printf("Read  [0x%p] = 0x%08x\n", addr, val);
+       return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+       const char *dev_id;
+       const char *con_id;
+       struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+       int (*enable)(struct clk *c, int enable);
+       int (*set_rate)(struct clk *c, unsigned long rate);
+       unsigned long (*get_rate)(struct clk *c);
+       unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+       int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+struct clk {
+       struct clk *parent;
+       const char *name;
+       int use_cnt;
+       unsigned long rate;     /* in HZ */
+
+       /* programmable divider. 0 means fixed ratio to parent clock */
+       unsigned long div;
+
+       struct clk_src *src;
+       struct clk_ops *ops;
+
+       unsigned long ccu_clk_mgr_base;
+       int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX       ((u32)U8_MAX)
+
+#define BAD_CLK_INDEX          U8_MAX  /* Can't ever be valid */
+#define BAD_CLK_NAME           ((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE   U64_MAX
+
+/*
+ * Utility macros for object flag management. If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag)               BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag)      ((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag)    ((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag)     ((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag)     (!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate)              FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate)          FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate)  FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate)  FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate)       FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate)       FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate)                FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div)            FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div)          FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div)      (!divider_is_fixed(div) && \
+                                               (div)->frac_width > 0)
+
+#define selector_exists(sel)           ((sel)->width != 0)
+#define trigger_exists(trig)           FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+       bcm_clk_none,           /* undefined clock type */
+       bcm_clk_bus,
+       bcm_clk_core,
+       bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ *     A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ *     Enabling or disabling clocks with this type of gate is
+ *     managed automatically by the hardware. Such clocks can be
+ *     considered by the software to be enabled. The current status
+ *     of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ *     Auto-gating is not available for this type of clock.
+ *     Instead, software manages whether it's enabled by setting or
+ *     clearing the enable bit. The current gate status of a gate
+ *     under software control can be read from the gate status bit.
+ *     To ensure a change to the gating status is complete, the
+ *     status bit can be polled to verify that the gate has entered
+ *     the desired state.
+ * - selectable hardware or software gating
+ *     Gating for this type of clock can be configured to be either
+ *     under software or hardware control. Which type is in use is
+ *     determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+       u32 offset;             /* gate register offset */
+       u32 status_bit;         /* 0: gate is disabled; 0: gatge is enabled */
+       u32 en_bit;             /* 0: disable; 1: enable */
+       u32 hw_sw_sel_bit;      /* 0: hardware gating; 1: software gating */
+       u32 flags;              /* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ *   HW         means this gate can be auto-gated
+ *   SW         means the state of this gate can be software controlled
+ *   NO_DISABLE means this gate is (only) enabled if under software control
+ *   SW_MANAGED means the status of this gate is under software control
+ *   ENABLED    means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS      ((u32)1 << 0)   /* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW          ((u32)1 << 1)   /* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW          ((u32)1 << 2)   /* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE  ((u32)1 << 3)   /* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED  ((u32)1 << 4)   /* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED     ((u32)1 << 5)   /* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)      \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .status_bit = (_status_bit),                            \
+               .en_bit = (_en_bit),                                    \
+               .hw_sw_sel_bit = (_hw_sw_sel_bit),                      \
+               .flags = FLAG(GATE, HW)|FLAG(GATE, SW)|                 \
+                       FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|     \
+                       FLAG(GATE, EXISTS),                             \
+       }
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .status_bit = (_status_bit),                            \
+               .en_bit = (_en_bit),                                    \
+               .hw_sw_sel_bit = (_hw_sw_sel_bit),                      \
+               .flags = FLAG(GATE, HW)|FLAG(GATE, SW)|                 \
+                       FLAG(GATE, EXISTS),                             \
+       }
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)  \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .status_bit = (_status_bit),                            \
+               .en_bit = (_en_bit),                                    \
+               .hw_sw_sel_bit = (_hw_sw_sel_bit),                      \
+               .flags = FLAG(GATE, HW)|FLAG(GATE, SW)|                 \
+                       FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),      \
+       }
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)                    \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .status_bit = (_status_bit),                            \
+               .en_bit = (_en_bit),                                    \
+               .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|         \
+                       FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),         \
+       }
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit)                             \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .status_bit = (_status_bit),                            \
+               .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),             \
+       }
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock. Each divider can be either fixed or
+ * variable. If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider. If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register. The position of the field in the
+ * register is defined by its offset and width. The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider. Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point. Most variable dividers have zero
+ * fractional bits. Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only. (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values. A scaled value is one that's
+ * been left-shifted by the fractional width of a divider. Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified. To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate). In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+       union {
+               struct {        /* variable divider */
+                       u32 offset;     /* divider register offset */
+                       u32 shift;      /* field shift */
+                       u32 width;      /* field width */
+                       u32 frac_width; /* field fraction width */
+
+                       u64 scaled_div; /* scaled divider value */
+               };
+               u32 fixed;      /* non-zero fixed divider value */
+       };
+       u32 flags;              /* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ *   EXISTS means this divider exists
+ *   FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS       ((u32)1 << 0)   /* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED                ((u32)1 << 1)   /* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value)                                          \
+       {                                                               \
+               .fixed = (_value),                                      \
+               .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),            \
+       }
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width)                               \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .shift = (_shift),                                      \
+               .width = (_width),                                      \
+               .scaled_div = BAD_SCALED_DIV_VALUE,                     \
+               .flags = FLAG(DIV, EXISTS),                             \
+       }
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)             \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .shift = (_shift),                                      \
+               .width = (_width),                                      \
+               .frac_width = (_frac_width),                            \
+               .scaled_div = BAD_SCALED_DIV_VALUE,                     \
+               .flags = FLAG(DIV, EXISTS),                             \
+       }
+
+/*
+ * Clocks may have multiple "parent" clocks. If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use. The selected clock is indicated in a
+ * sub-field of a 32-bit selector register. The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks. Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+       u32 offset;             /* selector register offset */
+       u32 shift;              /* field shift */
+       u32 width;              /* field width */
+
+       u32 parent_count;       /* number of entries in parent_sel[] */
+       u32 *parent_sel;        /* array of parent selector values */
+       u8 clk_index;           /* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width)                              \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .shift = (_shift),                                      \
+               .width = (_width),                                      \
+               .clk_index = BAD_CLK_INDEX,                             \
+       }
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger. A trigger is defined by a single
+ * bit within a register. To signal a change, a 1 is written into
+ * that bit. To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger. In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+       u32 offset;             /* trigger register offset */
+       u32 bit;                /* trigger bit */
+       u32 flags;              /* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ *   EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS      ((u32)1 << 0)   /* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit)                                         \
+       {                                                               \
+               .offset = (_offset),                                    \
+               .bit = (_bit),                                          \
+               .flags = FLAG(TRIG, EXISTS),                            \
+       }
+
+struct bus_clk_data {
+       struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+       struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+       struct bcm_clk_gate gate;
+       struct bcm_clk_trig pre_trig;
+       struct bcm_clk_div pre_div;
+       struct bcm_clk_trig trig;
+       struct bcm_clk_div div;
+       struct bcm_clk_sel sel;
+       const char *clocks[];   /* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...)    { __VA_ARGS__, NULL, }
+#define NO_CLOCKS      { NULL, }       /* Must use of no parent clocks */
+
+struct refclk {
+       struct clk clk;
+};
+
+struct peri_clock {
+       struct clk clk;
+       struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+       struct clk clk;
+
+       int num_policy_masks;
+       unsigned long policy_freq_offset;
+       int freq_bit_shift;     /* 8 for most CCUs */
+       unsigned long policy_ctl_offset;
+       unsigned long policy0_mask_offset;
+       unsigned long policy1_mask_offset;
+       unsigned long policy2_mask_offset;
+       unsigned long policy3_mask_offset;
+       unsigned long policy0_mask2_offset;
+       unsigned long policy1_mask2_offset;
+       unsigned long policy2_mask2_offset;
+       unsigned long policy3_mask2_offset;
+       unsigned long lvm_en_offset;
+
+       int freq_id;
+       unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+       struct clk clk;
+       struct bus_clk_data *data;
+       unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+       struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+       return a == b;
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+       return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+       return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+       return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+       return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+       return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+int clk_get_and_enable(char *clkstr);

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
new file mode 100644 (file)
index 0000000..b0b92b9
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR                 ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD                             0xA5A500
+
+#define PLLE_POST_RESETB_ADDR          (ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR               (ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK             0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK       0x00000001
+
+#define PLL_LOCK_ADDR                  (ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK                    0x00000001
+
+#define ESW_SYS_DIV_ADDR               (ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK                    0x00000300
+#define ESW_SYS_DIV_DIV_MASK                           0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT            0x00000100
+#define ESW_SYS_DIV_DIV_SELECT                         0x4
+#define ESW_SYS_DIV_TRIGGER_MASK                       0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR                (ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK             0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK    0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT     0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK                        0x00000001
+
+#define PLL_MAX_RETRY  100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+       int rc = -1;
+       int retry_count = 0;
+       rc = clk_get_and_enable("esub_ccu_clk");
+
+       /* Enable Access to CCU registers */
+       writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+       writel(readl(PLLE_POST_RESETB_ADDR) &
+              ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+              PLLE_POST_RESETB_ADDR);
+
+       /* Take PLL out of reset and put into normal mode */
+       writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+              PLLE_RESETB_ADDR);
+
+       /* Wait for PLL lock */
+       rc = -1;
+       while (retry_count < PLL_MAX_RETRY) {
+               udelay(100);
+               if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+                       rc = 0;
+                       break;
+               }
+               retry_count++;
+       }
+
+       if (rc == -1) {
+               printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+                      __func__);
+               return -1;
+       }
+
+       writel(readl(PLLE_POST_RESETB_ADDR) |
+              PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+              PLLE_POST_RESETB_ADDR);
+
+       /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+       writel((readl(ESW_SYS_DIV_ADDR) &
+               ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+              ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+              ESW_SYS_DIV_ADDR);
+
+       writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+              ESW_SYS_DIV_ADDR);
+
+       /* Wait for trigger complete */
+       rc = -1;
+       retry_count = 0;
+       while (retry_count < PLL_MAX_RETRY) {
+               udelay(100);
+               if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+                       rc = 0;
+                       break;
+               }
+               retry_count++;
+       }
+
+       if (rc == -1) {
+               printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+                      __func__);
+               return -1;
+       }
+
+       /* switch Esub AXI clock to 208MHz */
+       writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+               ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+                 ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+                 ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+              ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+              ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+              ESUB_AXI_DIV_DEBUG_ADDR);
+
+       writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+              ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+              ESUB_AXI_DIV_DEBUG_ADDR);
+
+       /* Wait for trigger complete */
+       rc = -1;
+       retry_count = 0;
+       while (retry_count < PLL_MAX_RETRY) {
+               udelay(100);
+               if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+                     ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+                       rc = 0;
+                       break;
+               }
+               retry_count++;
+       }
+
+       if (rc == -1) {
+               printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+                      __func__);
+               return -1;
+       }
+
+       /* Disable Access to CCU registers */
+       writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+       return rc;
+}

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
new file mode 100644 (file)
index 0000000..b2ce6d6
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+       int ret;
+       struct clk *c;
+
+       char *clkstr;
+       char *slpstr;
+       char *ahbstr;
+
+       switch ((u32) base) {
+       case CONFIG_SYS_SDIO_BASE0:
+               clkstr = CONFIG_SYS_SDIO0 "_clk";
+               ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+               slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+               break;
+       case CONFIG_SYS_SDIO_BASE1:
+               clkstr = CONFIG_SYS_SDIO1 "_clk";
+               ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+               slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+               break;
+       case CONFIG_SYS_SDIO_BASE2:
+               clkstr = CONFIG_SYS_SDIO2 "_clk";
+               ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+               slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+               break;
+       case CONFIG_SYS_SDIO_BASE3:
+               clkstr = CONFIG_SYS_SDIO3 "_clk";
+               ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+               slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+               break;
+       default:
+               printf("%s: base 0x%p not found\n", __func__, base);
+               return -EINVAL;
+       }
+
+       ret = clk_get_and_enable(ahbstr);
+       if (ret)
+               return ret;
+
+       ret = clk_get_and_enable(slpstr);
+       if (ret)
+               return ret;
+
+       c = clk_get(clkstr);
+       if (c) {
+               ret = clk_set_rate(c, rate);
+               if (ret)
+                       return ret;
+
+               ret = clk_enable(c);
+               if (ret)
+                       return ret;
+       } else {
+               printf("%s: Couldn't find %s\n", __func__, clkstr);
+               return -EINVAL;
+       }
+       *actual_ratep = rate;
+       return 0;
+}

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
new file mode 100644 (file)
index 0000000..1d7c5af
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+       char *ahbstr;
+
+       switch ((u32) base) {
+       case HSOTG_BASE_ADDR:
+               ahbstr = "usb_otg_ahb_clk";
+               break;
+       default:
+               printf("%s: base 0x%p not found\n", __func__, base);
+               return -EINVAL;
+       }
+
+       return clk_get_and_enable(ahbstr);
+}

diff --git a/arch/arm/cpu/armv7/kona-common/Makefile b/arch/arm/cpu/armv7/kona-common/Makefile
index da225cb4f744248ca1c43fa92cab82e6b8378373..5167ebbef906176288e0257472b83e44ca00fa77 100644 (file)
--- a/arch/arm/cpu/armv7/kona-common/Makefile
+++ b/arch/arm/cpu/armv7/kona-common/Makefile
@@ -7,3 +7,4 @@
 obj-y  += s_init.o
 obj-y  += hwinit-common.o
 obj-y  += clk-stubs.o
+obj-${CONFIG_KONA_RESET_S} += reset.o

diff --git a/arch/arm/cpu/armv7/kona-common/reset.S b/arch/arm/cpu/armv7/kona-common/reset.S
new file mode 100644 (file)
index 0000000..220a1ec
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/reset.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+.globl reset_cpu
+reset_cpu:
+       ldr     r1, =0x35001f00
+       ldr     r2, [r1]
+       ldr     r4, =0x80000000
+       and     r4, r2, r4
+       ldr     r3, =0xA5A500
+       orr     r4, r4, r3
+       orr     r4, r4, #0x1
+
+       str     r4, [r1]
+
+       ldr     r1, =0x35001f04
+       ldr     r2, [r1]
+       ldr     r4, =0x80000000
+       and     r4, r2, r4
+       str     r4, [r1]
+
+_loop_forever:
+       b       _loop_forever

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index e6f227548afeae90487a3f8353daadb51adf7130..ff932aa7ed413332d40d7bf36a01d9b440f85c47 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -97,7 +97,7 @@ void enable_enet_clk(unsigned char enable)
 {
        u32 mask, *addr;
 
-       if (is_cpu_type(MXC_CPU_MX6UL)) {
+       if (is_mx6ul()) {
                mask = MXC_CCM_CCGR3_ENET_MASK;
                addr = &imx_ccm->CCGR3;
        } else {
@@ -117,7 +117,7 @@ void enable_uart_clk(unsigned char enable)
 {
        u32 mask;
 
-       if (is_cpu_type(MXC_CPU_MX6UL))
+       if (is_mx6ul())
                mask = MXC_CCM_CCGR5_UART_MASK;
        else
                mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +168,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+               if (is_mx6sx() || is_mx6ul()) {
                        mask = MXC_CCM_CCGR6_I2C4_MASK;
                        addr = &imx_ccm->CCGR6;
                } else {
@@ -279,7 +279,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
        switch (pll) {
        case PLL_BUS:
-               if (!is_cpu_type(MXC_CPU_MX6UL)) {
+               if (!is_mx6ul()) {
                        if (pfd_num == 3) {
                                /* No PFD3 on PPL2 */
                                return 0;
@@ -379,8 +379,8 @@ static u32 get_ipg_per_clk(void)
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);
-       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-           is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+       if (is_mx6sl() || is_mx6sx() ||
+           is_mx6dqp() || is_mx6ul()) {
                if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                        return MXC_HCLK; /* OSC 24Mhz */
        }
@@ -396,8 +396,7 @@ static u32 get_uart_clk(void)
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
 
-       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-           is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+       if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
                if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                        freq = MXC_HCLK;
        }
@@ -416,8 +415,7 @@ static u32 get_cspi_clk(void)
        cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
                     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-       if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
-           is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+       if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
                if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
                        return MXC_HCLK / (cspi_podf + 1);
        }
@@ -479,14 +477,13 @@ static u32 get_mmdc_ch0_clk(void)
 
        u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-           is_cpu_type(MXC_CPU_MX6SL)) {
+       if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
                podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
                        MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
                if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
                        per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
                                MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
-                       if (is_cpu_type(MXC_CPU_MX6SL)) {
+                       if (is_mx6sl()) {
                                if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
                                        freq = MXC_HCLK;
                                else
@@ -618,7 +615,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
        debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-       if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+       if (!is_mx6sx() && !is_mx6ul()) {
                debug("This chip not support lcd!\n");
                return;
        }
@@ -630,7 +627,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
                        return;
        }
 
-       if (is_cpu_type(MXC_CPU_MX6SX)) {
+       if (is_mx6sx()) {
                reg = readl(&imx_ccm->cscdr2);
                /* Can't change clocks when clock not from pre-mux */
                if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
@@ -711,7 +708,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
                                MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
                                ((postd - 1) <<
                                 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
-       } else if (is_cpu_type(MXC_CPU_MX6SX)) {
+       } else if (is_mx6sx()) {
                /* Setting LCDIF2 for i.MX6SX */
                if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
                        return;
@@ -737,7 +734,7 @@ int enable_lcdif_clock(u32 base_addr)
        u32 reg = 0;
        u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 
-       if (is_cpu_type(MXC_CPU_MX6SX)) {
+       if (is_mx6sx()) {
                if ((base_addr != LCDIF1_BASE_ADDR) &&
                    (base_addr != LCDIF2_BASE_ADDR)) {
                        puts("Wrong LCD interface!\n");
@@ -752,7 +749,7 @@ int enable_lcdif_clock(u32 base_addr)
                         MXC_CCM_CCGR3_DISP_AXI_MASK) :
                        (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
                         MXC_CCM_CCGR3_DISP_AXI_MASK);
-       } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+       } else if (is_mx6ul()) {
                if (base_addr != LCDIF1_BASE_ADDR) {
                        puts("Wrong LCD interface!\n");
                        return -EINVAL;
@@ -850,8 +847,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
                reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
        } else if (fec_id == 1) {
                /* Only i.MX6SX/UL support ENET2 */
-               if (!(is_cpu_type(MXC_CPU_MX6SX) ||
-                     is_cpu_type(MXC_CPU_MX6UL)))
+               if (!(is_mx6sx() || is_mx6ul()))
                        return -EINVAL;
                reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
                reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -1044,7 +1040,7 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF        0xa
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF        0xb
 
-       if (is_cpu_type(MXC_CPU_MX6SX))
+       if (is_mx6sx())
                lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
        else
                lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
@@ -1228,7 +1224,7 @@ static void disable_ldb_di_clock_sources(void)
        /* Make sure PFDs are disabled at boot. */
        reg = readl(&mxc_ccm->analog_pfd_528);
        /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
-       if (is_cpu_type(MXC_CPU_MX6DL))
+       if (is_mx6sdl())
                reg |= 0x80008080;
        else
                reg |= 0x80808080;
@@ -1251,7 +1247,7 @@ static void enable_ldb_di_clock_sources(void)
        int reg;
 
        reg = readl(&mxc_ccm->analog_pfd_528);
-       if (is_cpu_type(MXC_CPU_MX6DL))
+       if (is_mx6sdl())
                reg &= ~(0x80008080);
        else
                reg &= ~(0x80808080);

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 1e7ae289337fd665177cda4a6ddcf8b2c893798d..f151eec545ce025834a7a9f0a064a9ff2873aee3 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -888,8 +888,7 @@ void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
        ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {                                         \
-       if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
-           !is_cpu_type(MXC_CPU_MX6SL))                                  \
+       if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())                    \
                mmdc1->entry = value;                                     \
        } while (0)
 
@@ -1197,12 +1196,11 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
        u16 mem_speed = ddr3_cfg->mem_speed;
 
        mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-       if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
-           !is_cpu_type(MXC_CPU_MX6SL))
+       if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
                mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
        /* Limit mem_speed for MX6D/MX6Q */
-       if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+       if (is_mx6dq() || is_mx6dqp()) {
                if (mem_speed > 1066)
                        mem_speed = 1066; /* 1066 MT/s */
 
@@ -1221,7 +1219,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
         * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
         * up to 528 MHz, so reduce the clock to fit chip specs
         */
-       if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+       if (is_mx6dq() || is_mx6dqp()) {
                if (clock > 528)
                        clock = 528; /* 528 MHz */
        }

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index d4b22ad7f315072c8df91be9c3b214c15879eeb7..88fcfdc2aa61641534e18164af74854942d8cf66 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -108,6 +108,12 @@ u32 get_cpu_rev(void)
 #define OCOTP_CFG3_SPEED_1GHZ  2
 #define OCOTP_CFG3_SPEED_1P2GHZ        3
 
+/*
+ * For i.MX6UL
+ */
+#define OCOTP_CFG3_SPEED_528MHZ 1
+#define OCOTP_CFG3_SPEED_696MHZ 2
+
 u32 get_cpu_speed_grade_hz(void)
 {
        struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -120,17 +126,26 @@ u32 get_cpu_speed_grade_hz(void)
        val >>= OCOTP_CFG3_SPEED_SHIFT;
        val &= 0x3;
 
+       if (is_mx6ul()) {
+               if (val == OCOTP_CFG3_SPEED_528MHZ)
+                       return 528000000;
+               else if (val == OCOTP_CFG3_SPEED_696MHZ)
+                       return 69600000;
+               else
+                       return 0;
+       }
+
        switch (val) {
        /* Valid for IMX6DQ */
        case OCOTP_CFG3_SPEED_1P2GHZ:
-               if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+               if (is_mx6dq() || is_mx6dqp())
                        return 1200000000;
        /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
        case OCOTP_CFG3_SPEED_1GHZ:
                return 996000000;
        /* Valid for IMX6DQ */
        case OCOTP_CFG3_SPEED_850MHZ:
-               if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+               if (is_mx6dq() || is_mx6dqp())
                        return 852000000;
        /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
        case OCOTP_CFG3_SPEED_800MHZ:
@@ -278,7 +293,7 @@ static void clear_mmdc_ch_mask(void)
        reg = readl(&mxc_ccm->ccdr);
 
        /* Clear MMDC channel mask */
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+       if (is_mx6sx() || is_mx6ul() || is_mx6sl())
                reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
        else
                reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -444,8 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
        struct fuse_bank4_regs *fuse =
                        (struct fuse_bank4_regs *)bank->fuse_regs;
 
-       if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && 
-               dev_id == 1) {
+       if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
                u32 value = readl(&fuse->mac_addr2);
                mac[0] = value >> 24 ;
                mac[1] = value >> 16 ;
@@ -509,7 +523,7 @@ void s_init(void)
        u32 mask528;
        u32 reg, periph1, periph2;
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+       if (is_mx6sx() || is_mx6ul())
                return;
 
        /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 073bbc6d014e1d05e3bf13a981c5fc3544fc15fb..ef46c92b098b223f4499812413ac840874290568 100644 (file)
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -441,3 +441,11 @@ void s_init(void)
 
        return;
 }
+
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+       lcdif_power_down();
+#endif
+}
+

diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 026bf24ddcb4b3632cf582c36e701fb6e24607ff..4fb5ef95cbe98254b14c41396710939be223cc1c 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -14,8 +14,8 @@ config TARGET_DRA7XX_EVM
        bool "TI DRA7XX"
        select TI_I2C_BOARD_DETECT
 
-config TARGET_BEAGLE_X15
-       bool "BeagleBoard X15"
+config TARGET_AM57XX_EVM
+       bool "AM57XX"
        select TI_I2C_BOARD_DETECT
 
 endchoice

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5b91446a8db4fe4891d9a64579e4ed4bf29155a2..62dd275f7ee8debb00a0472af52d30fe2578eaed 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -364,82 +364,6 @@ struct vcores_data omap5430_volts_es2 = {
        .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
-struct vcores_data dra752_volts = {
-       .mpu.value      = VDD_MPU_DRA7,
-       .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
-       .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
-       .mpu.pmic       = &tps659038,
-       .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-       .eve.value      = VDD_EVE_DRA7,
-       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
-       .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .eve.addr       = TPS659038_REG_ADDR_SMPS45,
-       .eve.pmic       = &tps659038,
-       .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-       .gpu.value      = VDD_GPU_DRA7,
-       .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
-       .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
-       .gpu.pmic       = &tps659038,
-       .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-       .core.value     = VDD_CORE_DRA7,
-       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
-       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .core.addr      = TPS659038_REG_ADDR_SMPS7,
-       .core.pmic      = &tps659038,
-
-       .iva.value      = VDD_IVA_DRA7,
-       .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
-       .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .iva.addr       = TPS659038_REG_ADDR_SMPS8,
-       .iva.pmic       = &tps659038,
-       .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
-       .mpu.value      = VDD_MPU_DRA7,
-       .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
-       .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
-       .mpu.pmic       = &tps659038,
-       .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-       .core.value     = VDD_CORE_DRA7,
-       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
-       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .core.addr      = TPS65917_REG_ADDR_SMPS2,
-       .core.pmic      = &tps659038,
-
-       /*
-        * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
-        * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
-        */
-       .gpu.value      = VDD_GPU_DRA7,
-       .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
-       .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
-       .gpu.pmic       = &tps659038,
-       .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-       .eve.value      = VDD_EVE_DRA7,
-       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
-       .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .eve.addr       = TPS65917_REG_ADDR_SMPS3,
-       .eve.pmic       = &tps659038,
-       .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-       .iva.value      = VDD_IVA_DRA7,
-       .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
-       .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .iva.addr       = TPS65917_REG_ADDR_SMPS3,
-       .iva.pmic       = &tps659038,
-       .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -802,7 +726,6 @@ void __weak hw_data_init(void)
        case DRA752_ES2_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra7xx_dplls;
-       *omap_vcores = &dra752_volts;
        *ctrl = &dra7xx_ctrl;
        break;
 
@@ -810,7 +733,6 @@ void __weak hw_data_init(void)
        case DRA722_ES2_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra72x_dplls;
-       *omap_vcores = &dra722_volts;
        *ctrl = &dra7xx_ctrl;
        break;
 

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index b18094447b0601e8a7ff539c0b286c693c66d5da..691e5d3fe165c79af45826e24cda182560333e67 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -66,7 +66,9 @@ save_boot_params_ret:
        /* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_cp15
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        bl      cpu_init_crit
+#endif
 #endif
 
        bl      _main
@@ -250,7 +252,8 @@ skip_errata_621766:
        mov     pc, r5                  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+       !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 /*************************************************************************
  *
  * CPU_init_critical registers

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 1c85aa924db05108329c4982460cf68e8300523a..bf8644ccd2e70b6b066af38df530ed3342098c7d 100644 (file)
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -17,5 +17,6 @@ obj-y += transition.o
 obj-y  += fwcall.o
 
 obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
+obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 9a5a6b53f76aefd9bf7efbe163216fdb2a04a794..297687d3c6f216ee6e2225b0ae6d8a075717809c 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -636,6 +636,9 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
        u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+       u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
        unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -650,6 +653,15 @@ int timer_init(void)
        out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+       /*
+        * In certain Layerscape SoCs, the clock for each core's
+        * has an enable bit in the PMU Physical Core Time Base Enable
+        * Register (PCTBENR), which allows the watchdog to operate.
+        */
+       setbits_le32(pctbenr, 0xff);
+#endif
+
        /* Enable clock for timer
         * This is a global setting.
         */

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index f9323c1d289d999a88b30492c87963caaf5672d2..da5e052569c49bcd5bab96b0fee1cc2c981ebba7 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -121,6 +121,35 @@ mcboottimeout:     MC boot timeout in milliseconds. If this variable is not defined
 mcmemsize:     MC DRAM block size. If this variable is not defined, the value
                CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
+mcinitcmd:     This environment variable is defined to initiate MC and DPL deployment
+               from the location where it is stored(NOR, NAND, SD, SATA, USB)during
+               u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
+               will be null and MC will not be booted and DPL will not be applied
+               during U-boot booting.However the MC, DPC and DPL can be applied from
+               console independently.
+               The variable needs to be set from the console once and then on
+               rebooting the parameters set in the varible will automatically be
+               executed. The commmand is demostrated taking an example of mc boot
+               using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
+
+               cp.b 0xa0000000 0x580300000 $filesize
+               cp.b 0x80000000 0x580800000 $filesize
+               cp.b 0x90000000 0x580700000 $filesize
+
+               setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
+
+               If only linux is to be booted then the mcinitcmd environment should be set as
+
+               setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+
+               Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
+               MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
+               and 0x580700000 are addresses in NOR where these are copied. It is to be
+               noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+               can be replaced with the addresses of DDR to
+               which these will be copied in case of these binaries being stored in other
+               devices like SATA, USB, NAND, SD etc.
+
 Booting from NAND
 -------------------
 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.

diff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile
new file mode 100644 (file)
index 0000000..49774f6
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += generic.o
+obj-y += cpu.o

diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
new file mode 100644 (file)
index 0000000..dac12a2
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/mc_me_regs.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 cpu_mask(void)
+{
+       return readl(MC_ME_CS);
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#define S32V234_IRAM_BASE        0x3e800000UL
+#define S32V234_IRAM_SIZE        0x800000UL
+#define S32V234_DRAM_BASE1       0x80000000UL
+#define S32V234_DRAM_SIZE1       0x40000000UL
+#define S32V234_DRAM_BASE2       0xC0000000UL
+#define S32V234_DRAM_SIZE2       0x20000000UL
+#define S32V234_PERIPH_BASE      0x40000000UL
+#define S32V234_PERIPH_SIZE      0x40000000UL
+
+static struct mm_region s32v234_mem_map[] = {
+       {
+               .base = S32V234_IRAM_BASE,
+               .size = S32V234_IRAM_SIZE,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_OUTER_SHARE
+       }, {
+               .base = S32V234_DRAM_BASE1,
+               .size = S32V234_DRAM_SIZE1,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_OUTER_SHARE
+       }, {
+               .base = S32V234_PERIPH_BASE,
+               .size = S32V234_PERIPH_SIZE,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE
+                        /* TODO: Do we need these? */
+                        /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
+       }, {
+               .base = S32V234_DRAM_BASE2,
+               .size = S32V234_DRAM_SIZE2,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+                        PTE_BLOCK_OUTER_SHARE
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = s32v234_mem_map;
+
+#endif
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+       int numcores;
+       u32 mask;
+
+       mask = cpu_mask();
+       numcores = hweight32(cpu_mask());
+
+       /* Verify if M4 is deactivated */
+       if (mask & 0x1)
+               numcores--;
+
+       return numcores;
+}
+
+#if defined(CONFIG_ARCH_EARLY_INIT_R)
+int arch_early_init_r(void)
+{
+       int rv;
+       asm volatile ("dsb sy");
+       rv = fsl_s32v234_wake_seconday_cores();
+
+       if (rv)
+               printf("Did not wake secondary cores\n");
+
+       asm volatile ("sev");
+       return 0;
+}
+#endif /* CONFIG_ARCH_EARLY_INIT_R */

diff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h
new file mode 100644 (file)
index 0000000..402ac29
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/cpu.h
@@ -0,0 +1,8 @@
+/*
+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+u32 cpu_mask(void);
+int cpu_numcores(void);

diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c
new file mode 100644 (file)
index 0000000..7bb894e
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/generic.c
@@ -0,0 +1,350 @@
+/*
+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc_cgm_regs.h>
+#include <asm/arch/mc_me_regs.h>
+#include <asm/arch/mc_rgm_regs.h>
+#include <netdev.h>
+#include <div64.h>
+#include <errno.h>
+
+u32 get_cpu_rev(void)
+{
+       struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
+       u32 cpu = readl(&mscmir->cpxtype);
+
+       return cpu;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
+                            u32 pllfd, u32 selected_output)
+{
+       u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
+       u32 plldv_rfdphi_div = 0, fout = 0;
+       u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
+
+       if (selected_output > DFS_MAXNUMBER) {
+               return -1;
+       }
+
+       plldv_prediv =
+           (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
+       plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
+
+       pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
+
+       plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
+
+       /* The formula for VCO is from TR manual, rev. D */
+       vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
+
+       if (selected_output != 0) {
+               /* Determine the RFDPHI for PHI1 */
+               plldv_rfdphi_div =
+                   (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
+                   PLLDIG_PLLDV_RFDPHI1_OFFSET;
+               plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
+               if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
+                       dfs_portn =
+                           readl(DFS_DVPORTn(pll, selected_output - 1));
+                       dfs_mfi =
+                           (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
+                           DFS_DVPORTn_MFI_OFFSET;
+                       dfs_mfn =
+                           (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
+                           DFS_DVPORTn_MFI_OFFSET;
+                       fout = vco / (dfs_mfi + (dfs_mfn / 256));
+               } else {
+                       fout = vco / plldv_rfdphi_div;
+               }
+
+       } else {
+               /* Determine the RFDPHI for PHI0 */
+               plldv_rfdphi_div =
+                   (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
+                   PLLDIG_PLLDV_RFDPHI_OFFSET;
+               fout = vco / plldv_rfdphi_div;
+       }
+
+       return fout;
+
+}
+
+/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
+static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
+                           u32 selected_output)
+{
+       u32 plldv, pllfd;
+
+       plldv = readl(PLLDIG_PLLDV(pll));
+       pllfd = readl(PLLDIG_PLLFD(pll));
+
+       return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
+}
+
+static u32 get_mcu_main_clk(void)
+{
+       u32 coreclk_div;
+       u32 sysclk_sel;
+       u32 freq = 0;
+
+       sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
+       sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
+
+       coreclk_div =
+           readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
+       coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
+       coreclk_div += 1;
+
+       switch (sysclk_sel) {
+       case MC_CGM_SC_SEL_FIRC:
+               freq = FIRC_CLK_FREQ;
+               break;
+       case MC_CGM_SC_SEL_XOSC:
+               freq = XOSC_CLK_FREQ;
+               break;
+       case MC_CGM_SC_SEL_ARMPLL:
+               /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
+               freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
+               break;
+       case MC_CGM_SC_SEL_CLKDISABLE:
+               printf("Sysclk is disabled\n");
+               break;
+       default:
+               printf("unsupported system clock select\n");
+       }
+
+       return freq / coreclk_div;
+}
+
+static u32 get_sys_clk(u32 number)
+{
+       u32 sysclk_div, sysclk_div_number;
+       u32 sysclk_sel;
+       u32 freq = 0;
+
+       switch (number) {
+       case 3:
+               sysclk_div_number = 0;
+               break;
+       case 6:
+               sysclk_div_number = 1;
+               break;
+       default:
+               printf("unsupported system clock \n");
+               return -1;
+       }
+       sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
+       sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
+
+       sysclk_div =
+           readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
+           MC_CGM_SC_DCn_PREDIV_MASK;
+       sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
+       sysclk_div += 1;
+
+       switch (sysclk_sel) {
+       case MC_CGM_SC_SEL_FIRC:
+               freq = FIRC_CLK_FREQ;
+               break;
+       case MC_CGM_SC_SEL_XOSC:
+               freq = XOSC_CLK_FREQ;
+               break;
+       case MC_CGM_SC_SEL_ARMPLL:
+               /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
+               freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
+               break;
+       case MC_CGM_SC_SEL_CLKDISABLE:
+               printf("Sysclk is disabled\n");
+               break;
+       default:
+               printf("unsupported system clock select\n");
+       }
+
+       return freq / sysclk_div;
+}
+
+static u32 get_peripherals_clk(void)
+{
+       u32 aux5clk_div;
+       u32 freq = 0;
+
+       aux5clk_div =
+           readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
+           MC_CGM_ACn_DCm_PREDIV_MASK;
+       aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+       aux5clk_div += 1;
+
+       freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
+
+       return freq / aux5clk_div;
+
+}
+
+static u32 get_uart_clk(void)
+{
+       u32 auxclk3_div, auxclk3_sel, freq = 0;
+
+       auxclk3_sel =
+           readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
+       auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
+
+       auxclk3_div =
+           readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
+           MC_CGM_ACn_DCm_PREDIV_MASK;
+       auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+       auxclk3_div += 1;
+
+       switch (auxclk3_sel) {
+       case MC_CGM_ACn_SEL_FIRC:
+               freq = FIRC_CLK_FREQ;
+               break;
+       case MC_CGM_ACn_SEL_XOSC:
+               freq = XOSC_CLK_FREQ;
+               break;
+       case MC_CGM_ACn_SEL_PERPLLDIVX:
+               freq = get_peripherals_clk() / 3;
+               break;
+       case MC_CGM_ACn_SEL_SYSCLK:
+               freq = get_sys_clk(6);
+               break;
+       default:
+               printf("unsupported system clock select\n");
+       }
+
+       return freq / auxclk3_div;
+}
+
+static u32 get_fec_clk(void)
+{
+       u32 aux2clk_div;
+       u32 freq = 0;
+
+       aux2clk_div =
+           readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
+           MC_CGM_ACn_DCm_PREDIV_MASK;
+       aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+       aux2clk_div += 1;
+
+       freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
+
+       return freq / aux2clk_div;
+}
+
+static u32 get_usdhc_clk(void)
+{
+       u32 aux15clk_div;
+       u32 freq = 0;
+
+       aux15clk_div =
+           readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
+           MC_CGM_ACn_DCm_PREDIV_MASK;
+       aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+       aux15clk_div += 1;
+
+       freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
+
+       return freq / aux15clk_div;
+}
+
+static u32 get_i2c_clk(void)
+{
+       return get_peripherals_clk();
+}
+
+/* return clocks in Hz */
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+       switch (clk) {
+       case MXC_ARM_CLK:
+               return get_mcu_main_clk();
+       case MXC_PERIPHERALS_CLK:
+               return get_peripherals_clk();
+       case MXC_UART_CLK:
+               return get_uart_clk();
+       case MXC_FEC_CLK:
+               return get_fec_clk();
+       case MXC_I2C_CLK:
+               return get_i2c_clk();
+       case MXC_USDHC_CLK:
+               return get_usdhc_clk();
+       default:
+               break;
+       }
+       printf("Error: Unsupported function to read the frequency! \
+                       Please define it correctly!");
+       return -1;
+}
+
+/* Not yet implemented - int soc_clk_dump(); */
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+       u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
+
+       switch (cause) {
+       case F_SWT4:
+               return "WDOG";
+       case F_JTAG:
+               return "JTAG";
+       case F_FCCU_SOFT:
+               return "FCCU soft reaction";
+       case F_FCCU_HARD:
+               return "FCCU hard reaction";
+       case F_SOFT_FUNC:
+               return "Software Functional reset";
+       case F_ST_DONE:
+               return "Self Test done reset";
+       case F_EXT_RST:
+               return "External reset";
+       default:
+               return "unknown reset";
+       }
+
+}
+
+#define SRC_SCR_SW_RST                                 (1<<12)
+
+void reset_cpu(ulong addr)
+{
+       printf("Feature not supported.\n");
+};
+
+int print_cpuinfo(void)
+{
+       printf("CPU:   Freescale Treerunner S32V234 at %d MHz\n",
+              mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
+
+       return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t * bis)
+{
+       int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+       rc = fecmxc_initialize(bis);
+#endif
+
+       return rc;
+}
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
+#endif
+       return 0;
+}

diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 408b70dbc1fe2f336173c9933120b4d9a1be560b..f5318c90d123f8a5c66d6f297f32f4d88323ad3a 100644 (file)
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -96,6 +96,7 @@ cpu_init_crit:
        ldr     r1, cpuspeed
        str     r1, [r0, #PPCR]
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependend, you will
@@ -104,6 +105,7 @@ cpu_init_crit:
        mov     ip,     lr
        bl      lowlevel_init
        mov     lr,     ip
+#endif
 
        /*
         * disable MMU stuff and enable I-cache

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a8276138ab1849481e34098d06202418231e9849..0b2b26919614cbfb727429223c4eaea3f0bdbe1a 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-gurnard.dtb
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
@@ -114,7 +115,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               \
        socfpga_cyclone5_vining_fpga.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
-dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
+dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
+       am572x-idk.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
 dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \

diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts
new file mode 100644 (file)
index 0000000..b340551
--- /dev/null
+++ b/arch/arm/dts/am572x-idk.dts
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+       model = "TI AM5728 IDK";
+       compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
+                    "ti,dra7";
+
+       chosen {
+               stdout-path = &uart3;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x0 0x80000000>;
+       };
+
+       extcon_usb2: extcon_usb2 {
+               compatible = "linux,extcon-usb-gpio";
+               id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+       };
+
+       status-leds {
+               compatible = "gpio-leds";
+               cpu0-led {
+                       label = "status0:red:cpu0";
+                       gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+                       linux,default-trigger = "cpu0";
+               };
+
+               usr0-led {
+                       label = "status0:green:usr";
+                       gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               heartbeat-led {
+                       label = "status0:blue:heartbeat";
+                       gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+                       linux,default-trigger = "heartbeat";
+               };
+
+               cpu1-led {
+                       label = "status1:red:cpu1";
+                       gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+                       linux,default-trigger = "cpu1";
+               };
+
+               usr1-led {
+                       label = "status1:green:usr";
+                       gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               mmc0-led {
+                       label = "status1:blue:mmc0";
+                       gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+                       linux,default-trigger = "mmc0";
+               };
+       };
+};
+
+&omap_dwc3_2 {
+       extcon = <&extcon_usb2>;
+};
+
+&mmc1 {
+       status = "okay";
+       vmmc-supply = <&v3_3d>;
+       vmmc_aux-supply = <&ldo1_reg>;
+       bus-width = <4>;
+       cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};

diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
new file mode 100644 (file)
index 0000000..2805b68
--- /dev/null
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+       aliases {
+               rtc0 = &tps659038_rtc;
+               rtc1 = &rtc;
+       };
+
+       vmain: fixedregulator-vmain {
+               compatible = "regulator-fixed";
+               regulator-name = "VMAIN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       v3_3d: fixedregulator-v3_3d {
+               compatible = "regulator-fixed";
+               regulator-name = "V3_3D";
+               vin-supply = <&smps9_reg>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vtt_fixed: fixedregulator-vtt {
+               /* TPS51200 */
+               compatible = "regulator-fixed";
+               regulator-name = "vtt_fixed";
+               vin-supply = <&v3_3d>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+};
+
+&i2c1 {
+       status = "okay";
+       clock-frequency = <400000>;
+
+       tps659038: tps659038@58 {
+               compatible = "ti,tps659038";
+               reg = <0x58>;
+               interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
+                              &dra7_pmx_core 0x418>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               ti,system-power-controller;
+
+               tps659038_pmic {
+                       compatible = "ti,tps659038-pmic";
+                       regulators {
+                               smps12_reg: smps12 {
+                                       /* VDD_MPU */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps12";
+                                       regulator-min-microvolt = <850000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               smps3_reg: smps3 {
+                                       /* VDD_DDR EMIF1 EMIF2 */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps3";
+                                       regulator-min-microvolt = <1350000>;
+                                       regulator-max-microvolt = <1350000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               smps45_reg: smps45 {
+                                       /* VDD_DSPEVE on AM572 */
+                                       /* VDD_IVA + VDD_DSP on AM571 */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps45";
+                                       regulator-min-microvolt = <850000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               smps6_reg: smps6 {
+                                       /* VDD_GPU */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps6";
+                                       regulator-min-microvolt = <850000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               smps7_reg: smps7 {
+                                       /* VDD_CORE */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps7";
+                                       regulator-min-microvolt = <850000>;
+                                       regulator-max-microvolt = <1150000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               smps8_reg: smps8 {
+                                       /* 5728 - VDD_IVAHD */
+                                       /* 5718 - N.C. test point */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps8";
+                               };
+
+                               smps9_reg: smps9 {
+                                       /* VDD_3_3D */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "smps9";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               ldo1_reg: ldo1 {
+                                       /* VDDSHV8 - VSDMMC  */
+                                       /* NOTE: on rev 1.3a, data supply */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldo1";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                               };
+
+                               ldo2_reg: ldo2 {
+                                       /* VDDSH18V */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldo2";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               ldo3_reg: ldo3 {
+                                       /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldo3";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               ldo4_reg: ldo4 {
+                                       /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldo4";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               /* LDO5-8 unused */
+
+                               ldo9_reg: ldo9 {
+                                       /* VDD_RTC  */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldo9";
+                                       regulator-min-microvolt = <840000>;
+                                       regulator-max-microvolt = <1160000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               ldoln_reg: ldoln {
+                                       /* VDDA_1V8_PLL */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldoln";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               ldousb_reg: ldousb {
+                                       /* VDDA_3V_USB: VDDA_USBHS33 */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldousb";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               ldortc_reg: ldortc {
+                                       /* VDDA_RTC  */
+                                       vin-supply = <&vmain>;
+                                       regulator-name = "ldortc";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               regen1: regen1 {
+                                       /* VDD_3V3_ON */
+                                       regulator-name = "regen1";
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                               };
+
+                               regen2: regen2 {
+                                       /* Needed for PMIC internal resource */
+                                       regulator-name = "regen2";
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                               };
+                       };
+               };
+
+               tps659038_rtc: tps659038_rtc {
+                       compatible = "ti,palmas-rtc";
+                       interrupt-parent = <&tps659038>;
+                       interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+                       wakeup-source;
+               };
+
+               tps659038_pwr_button: tps659038_pwr_button {
+                       compatible = "ti,palmas-pwrbutton";
+                       interrupt-parent = <&tps659038>;
+                       interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                       wakeup-source;
+                       ti,palmas-long-press-seconds = <12>;
+               };
+
+               tps659038_gpio: tps659038_gpio {
+                       compatible = "ti,palmas-gpio";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+       };
+};
+
+&uart3 {
+       status = "okay";
+       interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
+                              &dra7_pmx_core 0x248>;
+};
+
+&rtc {
+       status = "okay";
+       ext-clk-src;
+};
+
+&mac {
+       status = "okay";
+       dual_emac;
+};
+
+&cpsw_emac0 {
+       phy_id = <&davinci_mdio>, <0>;
+       phy-mode = "rgmii";
+       dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+       phy_id = <&davinci_mdio>, <1>;
+       phy-mode = "rgmii";
+       dual_emac_res_vlan = <2>;
+};
+
+&usb2_phy1 {
+       phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+       phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+       dr_mode = "host";
+};
+
+&usb2 {
+       dr_mode = "otg";
+};
+
+&mmc2 {
+       status = "okay";
+       vmmc-supply = <&v3_3d>;
+       bus-width = <8>;
+       ti,non-removable;
+       max-frequency = <96000000>;
+};

diff --git a/arch/arm/dts/at91sam9g45-gurnard.dts b/arch/arm/dts/at91sam9g45-gurnard.dts
new file mode 100644 (file)
index 0000000..75c1e99
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45-gurnard.dts
@@ -0,0 +1,157 @@
+/*
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9g45.dtsi"
+
+/ {
+       model = "Bluewater Systems Gurnard";
+       compatible = "atmel,at91sam9g45", "atmel,at91sam9";
+
+       chosen {
+               bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               reg = <0x20000000 0x8000000>;
+       };
+
+       clocks {
+               slow_xtal {
+                       clock-frequency = <32768>;
+               };
+
+               main_xtal {
+                       clock-frequency = <18432000>;
+               };
+       };
+
+       ahb {
+               u-boot,dm-pre-reloc;
+
+               fb@0x00500000 {
+                       u-boot,dm-pre-reloc;
+                       status = "okay";
+                       display-timings {
+                               rev1 {
+                                       clock-frequency = <4166666>;
+                                       hactive = <480>;
+                                       vactive = <272>;
+                                       hfront-porch = <1>;
+                                       hback-porch = <1>;
+                                       hsync-len = <1>;
+                                       vback-porch = <4>;
+                                       vfront-porch = <2>;
+                                       vsync-len = <1>;
+                                       hsync-active = <0>;
+                                       vsync-active = <0>;
+                               };
+
+                               rev2 {
+                                       clock-frequency = <4166666>;
+                                       hactive = <480>;
+                                       vactive = <272>;
+                                       hfront-porch = <2>;
+                                       hback-porch = <2>;
+                                       hsync-len = <10>;
+                                       vback-porch = <2>;
+                                       vfront-porch = <2>;
+                                       vsync-len = <10>;
+                                       hsync-active = <0>;
+                                       vsync-active = <0>;
+                               };
+                       };
+               };
+
+               apb {
+                       pinctrl@fffff400 {
+                               board {
+                                       pinctrl_pck0_as_mck: pck0_as_mck {
+                                               atmel,pins =
+                                                       <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC1 periph B */
+                                       };
+
+                               };
+
+                               mmc0_slot1 {
+                                       pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                               atmel,pins =
+                                                       <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PC9 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+                       };
+
+                       dbgu: serial@ffffee00 {
+                               status = "okay";
+                       };
+
+                       macb0: ethernet@fffbc000 {
+                               phy-mode = "rmii";
+                               status = "okay";
+                       };
+
+                       mmc0: mmc@fff80000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0_slot1
+                                       &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               status = "okay";
+                               slot@1 {
+                                       reg = <1>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
+                               };
+                       };
+
+                       ssc0: ssc@fff9c000 {
+                               status = "okay";
+                               pinctrl-0 = <&pinctrl_ssc0_tx>;
+                       };
+
+                       spi0: spi@fffa4000 {
+                               cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+                               mtd_dataflash@0 {
+                                       compatible = "atmel,at45", "atmel,dataflash";
+                                       spi-max-frequency = <50000000>;
+                                       reg = <1>;
+                               };
+                       };
+
+                       shdwc@fffffd10 {
+                               atmel,wakeup-counter = <10>;
+                               atmel,wakeup-rtt-timer;
+                       };
+
+                       rtc@fffffd20 {
+                               atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+                               status = "okay";
+                       };
+
+                       watchdog@fffffd40 {
+                               status = "okay";
+                       };
+
+                       gpbr: syscon@fffffd60 {
+                               status = "okay";
+                       };
+               };
+
+               nand0: nand@40000000 {
+                       nand-bus-width = <8>;
+                       nand-ecc-mode = "hardware";
+                       nand-on-flash-bbt;
+                       status = "okay";
+               };
+
+               usb1: ehci@00800000 {
+                       atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+                       status = "okay";
+               };
+       };
+
+};

diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi
new file mode 100644 (file)
index 0000000..af8b708
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45.dtsi
@@ -0,0 +1,1335 @@
+/*
+ * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
+ *                    applies to AT91SAM9G45, AT91SAM9M10,
+ *                    AT91SAM9G46, AT91SAM9M11 SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+       model = "Atmel AT91SAM9G45 family SoC";
+       compatible = "atmel,at91sam9g45";
+       interrupt-parent = <&aic>;
+
+       aliases {
+               serial0 = &dbgu;
+               serial1 = &usart0;
+               serial2 = &usart1;
+               serial3 = &usart2;
+               serial4 = &usart3;
+               gpio0 = &pioA;
+               gpio1 = &pioB;
+               gpio2 = &pioC;
+               gpio3 = &pioD;
+               gpio4 = &pioE;
+               tcb0 = &tcb0;
+               tcb1 = &tcb1;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               ssc0 = &ssc0;
+               ssc1 = &ssc1;
+               pwm0 = &pwm0;
+       };
+       cpus {
+               #address-cells = <0>;
+               #size-cells = <0>;
+
+               cpu {
+                       compatible = "arm,arm926ej-s";
+                       device_type = "cpu";
+               };
+       };
+
+       memory {
+               reg = <0x70000000 0x10000000>;
+       };
+
+       clocks {
+               slow_xtal: slow_xtal {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
+
+               main_xtal: main_xtal {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
+
+               adc_op_clk: adc_op_clk{
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <300000>;
+               };
+       };
+
+       sram: sram@00300000 {
+               compatible = "mmio-sram";
+               reg = <0x00300000 0x10000>;
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               apb {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       aic: interrupt-controller@fffff000 {
+                               #interrupt-cells = <3>;
+                               compatible = "atmel,at91rm9200-aic";
+                               interrupt-controller;
+                               reg = <0xfffff000 0x200>;
+                               atmel,external-irqs = <31>;
+                       };
+
+                       ramc0: ramc@ffffe400 {
+                               compatible = "atmel,at91sam9g45-ddramc";
+                               reg = <0xffffe400 0x200>;
+                               clocks = <&ddrck>;
+                               clock-names = "ddrck";
+                       };
+
+                       ramc1: ramc@ffffe600 {
+                               compatible = "atmel,at91sam9g45-ddramc";
+                               reg = <0xffffe600 0x200>;
+                               clocks = <&ddrck>;
+                               clock-names = "ddrck";
+                       };
+
+                       pmc: pmc@fffffc00 {
+                               compatible = "atmel,at91sam9g45-pmc", "syscon";
+                               reg = <0xfffffc00 0x100>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               interrupt-controller;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #interrupt-cells = <1>;
+
+                               main_osc: main_osc {
+                                       compatible = "atmel,at91rm9200-clk-main-osc";
+                                       #clock-cells = <0>;
+                                       interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+                                       clocks = <&main_xtal>;
+                               };
+
+                               main: mainck {
+                                       compatible = "atmel,at91rm9200-clk-main";
+                                       #clock-cells = <0>;
+                                       clocks = <&main_osc>;
+                               };
+
+                               plla: pllack {
+                                       compatible = "atmel,at91rm9200-clk-pll";
+                                       #clock-cells = <0>;
+                                       interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+                                       clocks = <&main>;
+                                       reg = <0>;
+                                       atmel,clk-input-range = <2000000 32000000>;
+                                       #atmel,pll-clk-output-range-cells = <4>;
+                                       atmel,pll-clk-output-ranges = <745000000 800000000 0 0
+                                                                      695000000 750000000 1 0
+                                                                      645000000 700000000 2 0
+                                                                      595000000 650000000 3 0
+                                                                      545000000 600000000 0 1
+                                                                      495000000 555000000 1 1
+                                                                      445000000 500000000 2 1
+                                                                      400000000 450000000 3 1>;
+                               };
+
+                               plladiv: plladivck {
+                                       compatible = "atmel,at91sam9x5-clk-plldiv";
+                                       #clock-cells = <0>;
+                                       clocks = <&plla>;
+                               };
+
+                               utmi: utmick {
+                                       compatible = "atmel,at91sam9x5-clk-utmi";
+                                       #clock-cells = <0>;
+                                       interrupts-extended = <&pmc AT91_PMC_LOCKU>;
+                                       clocks = <&main>;
+                               };
+
+                               mck: masterck {
+                                       compatible = "atmel,at91rm9200-clk-master";
+                                       #clock-cells = <0>;
+                                       interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+                                       clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+                                       atmel,clk-output-range = <0 133333333>;
+                                       atmel,clk-divisors = <1 2 4 3>;
+                               };
+
+                               usb: usbck {
+                                       compatible = "atmel,at91sam9x5-clk-usb";
+                                       #clock-cells = <0>;
+                                       clocks = <&plladiv>, <&utmi>;
+                               };
+
+                               prog: progck {
+                                       compatible = "atmel,at91sam9g45-clk-programmable";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       interrupt-parent = <&pmc>;
+                                       clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+                                       prog0: prog0 {
+                                               #clock-cells = <0>;
+                                               reg = <0>;
+                                               interrupts = <AT91_PMC_PCKRDY(0)>;
+                                       };
+
+                                       prog1: prog1 {
+                                               #clock-cells = <0>;
+                                               reg = <1>;
+                                               interrupts = <AT91_PMC_PCKRDY(1)>;
+                                       };
+                               };
+
+                               systemck {
+                                       compatible = "atmel,at91rm9200-clk-system";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       ddrck: ddrck {
+                                               #clock-cells = <0>;
+                                               reg = <2>;
+                                               clocks = <&mck>;
+                                       };
+
+                                       uhpck: uhpck {
+                                               #clock-cells = <0>;
+                                               reg = <6>;
+                                               clocks = <&usb>;
+                                       };
+
+                                       pck0: pck0 {
+                                               #clock-cells = <0>;
+                                               reg = <8>;
+                                               clocks = <&prog0>;
+                                       };
+
+                                       pck1: pck1 {
+                                               #clock-cells = <0>;
+                                               reg = <9>;
+                                               clocks = <&prog1>;
+                                       };
+                               };
+
+                               periphck {
+                                       compatible = "atmel,at91rm9200-clk-peripheral";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       clocks = <&mck>;
+
+                                       pioA_clk: pioA_clk {
+                                               #clock-cells = <0>;
+                                               reg = <2>;
+                                       };
+
+                                       pioB_clk: pioB_clk {
+                                               #clock-cells = <0>;
+                                               reg = <3>;
+                                       };
+
+                                       pioC_clk: pioC_clk {
+                                               #clock-cells = <0>;
+                                               reg = <4>;
+                                       };
+
+                                       pioDE_clk: pioDE_clk {
+                                               #clock-cells = <0>;
+                                               reg = <5>;
+                                       };
+
+                                       trng_clk: trng_clk {
+                                               #clock-cells = <0>;
+                                               reg = <6>;
+                                       };
+
+                                       usart0_clk: usart0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <7>;
+                                       };
+
+                                       usart1_clk: usart1_clk {
+                                               #clock-cells = <0>;
+                                               reg = <8>;
+                                       };
+
+                                       usart2_clk: usart2_clk {
+                                               #clock-cells = <0>;
+                                               reg = <9>;
+                                       };
+
+                                       usart3_clk: usart3_clk {
+                                               #clock-cells = <0>;
+                                               reg = <10>;
+                                       };
+
+                                       mci0_clk: mci0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <11>;
+                                       };
+
+                                       twi0_clk: twi0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <12>;
+                                       };
+
+                                       twi1_clk: twi1_clk {
+                                               #clock-cells = <0>;
+                                               reg = <13>;
+                                       };
+
+                                       spi0_clk: spi0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <14>;
+                                       };
+
+                                       spi1_clk: spi1_clk {
+                                               #clock-cells = <0>;
+                                               reg = <15>;
+                                       };
+
+                                       ssc0_clk: ssc0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <16>;
+                                       };
+
+                                       ssc1_clk: ssc1_clk {
+                                               #clock-cells = <0>;
+                                               reg = <17>;
+                                       };
+
+                                       tcb0_clk: tcb0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <18>;
+                                       };
+
+                                       pwm_clk: pwm_clk {
+                                               #clock-cells = <0>;
+                                               reg = <19>;
+                                       };
+
+                                       adc_clk: adc_clk {
+                                               #clock-cells = <0>;
+                                               reg = <20>;
+                                       };
+
+                                       dma0_clk: dma0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <21>;
+                                       };
+
+                                       uhphs_clk: uhphs_clk {
+                                               #clock-cells = <0>;
+                                               reg = <22>;
+                                       };
+
+                                       lcd_clk: lcd_clk {
+                                               #clock-cells = <0>;
+                                               reg = <23>;
+                                       };
+
+                                       ac97_clk: ac97_clk {
+                                               #clock-cells = <0>;
+                                               reg = <24>;
+                                       };
+
+                                       macb0_clk: macb0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <25>;
+                                       };
+
+                                       isi_clk: isi_clk {
+                                               #clock-cells = <0>;
+                                               reg = <26>;
+                                       };
+
+                                       udphs_clk: udphs_clk {
+                                               #clock-cells = <0>;
+                                               reg = <27>;
+                                       };
+
+                                       aestdessha_clk: aestdessha_clk {
+                                               #clock-cells = <0>;
+                                               reg = <28>;
+                                       };
+
+                                       mci1_clk: mci1_clk {
+                                               #clock-cells = <0>;
+                                               reg = <29>;
+                                       };
+
+                                       vdec_clk: vdec_clk {
+                                               #clock-cells = <0>;
+                                               reg = <30>;
+                                       };
+                               };
+                       };
+
+                       rstc@fffffd00 {
+                               compatible = "atmel,at91sam9g45-rstc";
+                               reg = <0xfffffd00 0x10>;
+                               clocks = <&clk32k>;
+                       };
+
+                       pit: timer@fffffd30 {
+                               compatible = "atmel,at91sam9260-pit";
+                               reg = <0xfffffd30 0xf>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               clocks = <&mck>;
+                       };
+
+
+                       shdwc@fffffd10 {
+                               compatible = "atmel,at91sam9rl-shdwc";
+                               reg = <0xfffffd10 0x10>;
+                               clocks = <&clk32k>;
+                       };
+
+                       tcb0: timer@fff7c000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfff7c000 0x100>;
+                               interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+                               clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+                               clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+                       };
+
+                       tcb1: timer@fffd4000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfffd4000 0x100>;
+                               interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+                               clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+                               clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+                       };
+
+                       dma: dma-controller@ffffec00 {
+                               compatible = "atmel,at91sam9g45-dma";
+                               reg = <0xffffec00 0x200>;
+                               interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
+                               #dma-cells = <2>;
+                               clocks = <&dma0_clk>;
+                               clock-names = "dma_clk";
+                       };
+
+                       pinctrl@fffff200 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff200 0xfffff200 0xa00>;
+
+                               atmel,mux-mask = <
+                                     /*    A         B     */
+                                      0xffffffff 0xffc003ff  /* pioA */
+                                      0xffffffff 0x800f8f00  /* pioB */
+                                      0xffffffff 0x00000e00  /* pioC */
+                                      0xffffffff 0xff0c1381  /* pioD */
+                                      0xffffffff 0x81ffff81  /* pioE */
+                                     >;
+
+                               /* shared pinctrl settings */
+                               adc0 {
+                                       pinctrl_adc0_adtrg: adc0_adtrg {
+                                               atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad0: adc0_ad0 {
+                                               atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad1: adc0_ad1 {
+                                               atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad2: adc0_ad2 {
+                                               atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad3: adc0_ad3 {
+                                               atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad4: adc0_ad4 {
+                                               atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad5: adc0_ad5 {
+                                               atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad6: adc0_ad6 {
+                                               atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                                       pinctrl_adc0_ad7: adc0_ad7 {
+                                               atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                       };
+                               };
+
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                        AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+                                       };
+                               };
+
+                               i2c0 {
+                                       pinctrl_i2c0: i2c0-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA21 periph A TWCK0 */
+                                                        AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
+                                       };
+                               };
+
+                               i2c1 {
+                                       pinctrl_i2c1: i2c1-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A TWCK1 */
+                                                        AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
+                                       };
+                               };
+
+                               isi {
+                                       pinctrl_isi_data_0_7: isi-0-data-0-7 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
+                                                       AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
+                                                       AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
+                                                       AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
+                                                       AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
+                                                       AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
+                                                       AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
+                                                       AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
+                                                       AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
+                                                       AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
+                                                       AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
+                                       };
+
+                                       pinctrl_isi_data_8_9: isi-0-data-8-9 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
+                                                       AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
+                                       };
+
+                                       pinctrl_isi_data_10_11: isi-0-data-10-11 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
+                                                       AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
+                                       };
+                               };
+
+                               usart0 {
+                                       pinctrl_usart0: usart0-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB19 periph A with pullup */
+                                                        AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
+                                       };
+
+                                       pinctrl_usart0_rts: usart0_rts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
+                                       };
+
+                                       pinctrl_usart0_cts: usart0_cts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
+                                       };
+                               };
+
+                               uart1 {
+                                       pinctrl_usart1: usart1-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
+                                                        AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
+                                       };
+
+                                       pinctrl_usart1_rts: usart1_rts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
+                                       };
+
+                                       pinctrl_usart1_cts: usart1_cts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
+                                       };
+                               };
+
+                               usart2 {
+                                       pinctrl_usart2: usart2-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
+                                                        AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
+                                       };
+
+                                       pinctrl_usart2_rts: usart2_rts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC9 periph B */
+                                       };
+
+                                       pinctrl_usart2_cts: usart2_cts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
+                                       };
+                               };
+
+                               usart3 {
+                                       pinctrl_usart3: usart3-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
+                                                        AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PC8 gpio RDY pin pull_up*/
+                                                        AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               macb {
+                                       pinctrl_macb_rmii: macb_rmii-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A */
+                                                        AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A */
+                                                        AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
+                                                        AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
+                                                        AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
+                                                        AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
+                                                        AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA16 periph A */
+                                                        AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                        AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA18 periph A */
+                                                        AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
+                                       };
+
+                                       pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA6 periph B */
+                                                        AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA7 periph B */
+                                                        AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA8 periph B */
+                                                        AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA9 periph B */
+                                                        AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
+                                                        AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
+                                                        AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA29 periph B */
+                                                        AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A */
+                                                        AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
+                                                        AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA2 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
+                                                        AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
+                                                        AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA5 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
+                                                        AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+                                                        AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
+                                                        AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA9 periph A with pullup */
+                                       };
+                               };
+
+                               mmc1 {
+                                       pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA31 periph A */
+                                                        AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA22 periph A with pullup */
+                                                        AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA24 periph A with pullup */
+                                                        AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA25 periph A with pullup */
+                                                        AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA26 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA27 periph A with pullup */
+                                                        AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA28 periph A with pullup */
+                                                        AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA29 periph A with pullup */
+                                                        AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA30 periph A with pullup */
+                                       };
+                               };
+
+                               ssc0 {
+                                       pinctrl_ssc0_tx: ssc0_tx-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD0 periph A */
+                                                        AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD1 periph A */
+                                                        AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD2 periph A */
+                                       };
+
+                                       pinctrl_ssc0_rx: ssc0_rx-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD3 periph A */
+                                                        AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD4 periph A */
+                                                        AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD5 periph A */
+                                       };
+                               };
+
+                               ssc1 {
+                                       pinctrl_ssc1_tx: ssc1_tx-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A */
+                                                        AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A */
+                                                        AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
+                                       };
+
+                                       pinctrl_ssc1_rx: ssc1_rx-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD13 periph A */
+                                                        AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD14 periph A */
+                                                        AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
+                                       };
+                               };
+
+                               spi0 {
+                                       pinctrl_spi0: spi0-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A SPI0_MISO pin */
+                                                        AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A SPI0_MOSI pin */
+                                                        AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A SPI0_SPCK pin */
+                                       };
+                               };
+
+                               spi1 {
+                                       pinctrl_spi1: spi1-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A SPI1_MISO pin */
+                                                        AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A SPI1_MOSI pin */
+                                                        AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
+                                       };
+                               };
+
+                               tcb0 {
+                                       pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                               atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                               atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                               atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                               atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                               atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                               atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                               atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                               atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                               atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+                               };
+
+                               tcb1 {
+                                       pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                               atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                               atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                               atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                               atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                               atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                               atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                               atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                               atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                               atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+                               };
+
+                               fb {
+                                       pinctrl_fb: fb-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE0 periph A */
+                                                        AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE2 periph A */
+                                                        AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE3 periph A */
+                                                        AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE4 periph A */
+                                                        AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE5 periph A */
+                                                        AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE6 periph A */
+                                                        AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE7 periph A */
+                                                        AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE8 periph A */
+                                                        AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE9 periph A */
+                                                        AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE10 periph A */
+                                                        AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE11 periph A */
+                                                        AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE12 periph A */
+                                                        AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE13 periph A */
+                                                        AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE14 periph A */
+                                                        AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE15 periph A */
+                                                        AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE16 periph A */
+                                                        AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE17 periph A */
+                                                        AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE18 periph A */
+                                                        AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE19 periph A */
+                                                        AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE20 periph A */
+                                                        AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE21 periph A */
+                                                        AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE22 periph A */
+                                                        AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE23 periph A */
+                                                        AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE24 periph A */
+                                                        AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE25 periph A */
+                                                        AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE26 periph A */
+                                                        AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE27 periph A */
+                                                        AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE28 periph A */
+                                                        AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE29 periph A */
+                                                        AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
+                                       };
+                               };
+
+                               pioA: gpio@fffff200 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff200 0x200>;
+                                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                                       clocks = <&pioA_clk>;
+                               };
+
+                               pioB: gpio@fffff400 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                                       clocks = <&pioB_clk>;
+                               };
+
+                               pioC: gpio@fffff600 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                                       clocks = <&pioC_clk>;
+                               };
+
+                               pioD: gpio@fffff800 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                                       clocks = <&pioDE_clk>;
+                               };
+
+                               pioE: gpio@fffffa00 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffffa00 0x200>;
+                                       interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                                       clocks = <&pioDE_clk>;
+                               };
+                       };
+
+                       dbgu: serial@ffffee00 {
+                               compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+                               reg = <0xffffee00 0x200>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
+                               clocks = <&mck>;
+                               clock-names = "usart";
+                               status = "disabled";
+                       };
+
+                       usart0: serial@fff8c000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xfff8c000 0x200>;
+                               interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart0>;
+                               clocks = <&usart0_clk>;
+                               clock-names = "usart";
+                               status = "disabled";
+                       };
+
+                       usart1: serial@fff90000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xfff90000 0x200>;
+                               interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart1>;
+                               clocks = <&usart1_clk>;
+                               clock-names = "usart";
+                               status = "disabled";
+                       };
+
+                       usart2: serial@fff94000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xfff94000 0x200>;
+                               interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart2>;
+                               clocks = <&usart2_clk>;
+                               clock-names = "usart";
+                               status = "disabled";
+                       };
+
+                       usart3: serial@fff98000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xfff98000 0x200>;
+                               interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart3>;
+                               clocks = <&usart3_clk>;
+                               clock-names = "usart";
+                               status = "disabled";
+                       };
+
+                       macb0: ethernet@fffbc000 {
+                               compatible = "cdns,at91sam9260-macb", "cdns,macb";
+                               reg = <0xfffbc000 0x100>;
+                               interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb_rmii>;
+                               clocks = <&macb0_clk>, <&macb0_clk>;
+                               clock-names = "hclk", "pclk";
+                               status = "disabled";
+                       };
+
+                       trng@fffcc000 {
+                               compatible = "atmel,at91sam9g45-trng";
+                               reg = <0xfffcc000 0x4000>;
+                               interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
+                               clocks = <&trng_clk>;
+                       };
+
+                       i2c0: i2c@fff84000 {
+                               compatible = "atmel,at91sam9g10-i2c";
+                               reg = <0xfff84000 0x100>;
+                               interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_i2c0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               clocks = <&twi0_clk>;
+                               status = "disabled";
+                       };
+
+                       i2c1: i2c@fff88000 {
+                               compatible = "atmel,at91sam9g10-i2c";
+                               reg = <0xfff88000 0x100>;
+                               interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_i2c1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               clocks = <&twi1_clk>;
+                               status = "disabled";
+                       };
+
+                       ssc0: ssc@fff9c000 {
+                               compatible = "atmel,at91sam9g45-ssc";
+                               reg = <0xfff9c000 0x4000>;
+                               interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                               clocks = <&ssc0_clk>;
+                               clock-names = "pclk";
+                               status = "disabled";
+                       };
+
+                       ssc1: ssc@fffa0000 {
+                               compatible = "atmel,at91sam9g45-ssc";
+                               reg = <0xfffa0000 0x4000>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                               clocks = <&ssc1_clk>;
+                               clock-names = "pclk";
+                               status = "disabled";
+                       };
+
+                       adc0: adc@fffb0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "atmel,at91sam9g45-adc";
+                               reg = <0xfffb0000 0x100>;
+                               interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+                               clocks = <&adc_clk>, <&adc_op_clk>;
+                               clock-names = "adc_clk", "adc_op_clk";
+                               atmel,adc-channels-used = <0xff>;
+                               atmel,adc-vref = <3300>;
+                               atmel,adc-startup-time = <40>;
+                               atmel,adc-res = <8 10>;
+                               atmel,adc-res-names = "lowres", "highres";
+                               atmel,adc-use-res = "highres";
+
+                               trigger@0 {
+                                       reg = <0>;
+                                       trigger-name = "external-rising";
+                                       trigger-value = <0x1>;
+                                       trigger-external;
+                               };
+                               trigger@1 {
+                                       reg = <1>;
+                                       trigger-name = "external-falling";
+                                       trigger-value = <0x2>;
+                                       trigger-external;
+                               };
+
+                               trigger@2 {
+                                       reg = <2>;
+                                       trigger-name = "external-any";
+                                       trigger-value = <0x3>;
+                                       trigger-external;
+                               };
+
+                               trigger@3 {
+                                       reg = <3>;
+                                       trigger-name = "continuous";
+                                       trigger-value = <0x6>;
+                               };
+                       };
+
+                       isi@fffb4000 {
+                               compatible = "atmel,at91sam9g45-isi";
+                               reg = <0xfffb4000 0x4000>;
+                               interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
+                               clocks = <&isi_clk>;
+                               clock-names = "isi_clk";
+                               status = "disabled";
+                               port {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                               };
+                       };
+
+                       pwm0: pwm@fffb8000 {
+                               compatible = "atmel,at91sam9rl-pwm";
+                               reg = <0xfffb8000 0x300>;
+                               interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+                               #pwm-cells = <3>;
+                               clocks = <&pwm_clk>;
+                               status = "disabled";
+                       };
+
+                       mmc0: mmc@fff80000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfff80000 0x600>;
+                               interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+                               pinctrl-names = "default";
+                               dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
+                               dma-names = "rxtx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               clocks = <&mci0_clk>;
+                               clock-names = "mci_clk";
+                               status = "disabled";
+                       };
+
+                       mmc1: mmc@fffd0000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfffd0000 0x600>;
+                               interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
+                               pinctrl-names = "default";
+                               dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
+                               dma-names = "rxtx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               clocks = <&mci1_clk>;
+                               clock-names = "mci_clk";
+                               status = "disabled";
+                       };
+
+                       watchdog@fffffd40 {
+                               compatible = "atmel,at91sam9260-wdt";
+                               reg = <0xfffffd40 0x10>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               clocks = <&clk32k>;
+                               atmel,watchdog-type = "hardware";
+                               atmel,reset-type = "all";
+                               atmel,dbg-halt;
+                               status = "disabled";
+                       };
+
+                       spi0: spi@fffa4000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0xfffa4000 0x200>;
+                               interrupts = <14 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi0>;
+                               clocks = <&spi0_clk>;
+                               clock-names = "spi_clk";
+                               status = "disabled";
+                       };
+
+                       spi1: spi@fffa8000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0xfffa8000 0x200>;
+                               interrupts = <15 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi1>;
+                               clocks = <&spi1_clk>;
+                               clock-names = "spi_clk";
+                               status = "disabled";
+                       };
+
+                       usb2: gadget@fff78000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "atmel,at91sam9g45-udc";
+                               reg = <0x00600000 0x80000
+                                      0xfff78000 0x400>;
+                               interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+                               clocks = <&udphs_clk>, <&utmi>;
+                               clock-names = "pclk", "hclk";
+                               status = "disabled";
+
+                               ep0 {
+                                       reg = <0>;
+                                       atmel,fifo-size = <64>;
+                                       atmel,nb-banks = <1>;
+                               };
+
+                               ep1 {
+                                       reg = <1>;
+                                       atmel,fifo-size = <1024>;
+                                       atmel,nb-banks = <2>;
+                                       atmel,can-dma;
+                                       atmel,can-isoc;
+                               };
+
+                               ep2 {
+                                       reg = <2>;
+                                       atmel,fifo-size = <1024>;
+                                       atmel,nb-banks = <2>;
+                                       atmel,can-dma;
+                                       atmel,can-isoc;
+                               };
+
+                               ep3 {
+                                       reg = <3>;
+                                       atmel,fifo-size = <1024>;
+                                       atmel,nb-banks = <3>;
+                                       atmel,can-dma;
+                               };
+
+                               ep4 {
+                                       reg = <4>;
+                                       atmel,fifo-size = <1024>;
+                                       atmel,nb-banks = <3>;
+                                       atmel,can-dma;
+                               };
+
+                               ep5 {
+                                       reg = <5>;
+                                       atmel,fifo-size = <1024>;
+                                       atmel,nb-banks = <3>;
+                                       atmel,can-dma;
+                                       atmel,can-isoc;
+                               };
+
+                               ep6 {
+                                       reg = <6>;
+                                       atmel,fifo-size = <1024>;
+                                       atmel,nb-banks = <3>;
+                                       atmel,can-dma;
+                                       atmel,can-isoc;
+                               };
+                       };
+
+                       sckc@fffffd50 {
+                               compatible = "atmel,at91sam9x5-sckc";
+                               reg = <0xfffffd50 0x4>;
+
+                               slow_osc: slow_osc {
+                                       compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                       #clock-cells = <0>;
+                                       atmel,startup-time-usec = <1200000>;
+                                       clocks = <&slow_xtal>;
+                               };
+
+                               slow_rc_osc: slow_rc_osc {
+                                       compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                       #clock-cells = <0>;
+                                       atmel,startup-time-usec = <75>;
+                                       clock-frequency = <32768>;
+                                       clock-accuracy = <50000000>;
+                               };
+
+                               clk32k: slck {
+                                       compatible = "atmel,at91sam9x5-clk-slow";
+                                       #clock-cells = <0>;
+                                       clocks = <&slow_rc_osc &slow_osc>;
+                               };
+                       };
+
+                       rtc@fffffd20 {
+                               compatible = "atmel,at91sam9260-rtt";
+                               reg = <0xfffffd20 0x10>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               clocks = <&clk32k>;
+                               status = "disabled";
+                       };
+
+                       rtc@fffffdb0 {
+                               compatible = "atmel,at91rm9200-rtc";
+                               reg = <0xfffffdb0 0x30>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               clocks = <&clk32k>;
+                               status = "disabled";
+                       };
+
+                       gpbr: syscon@fffffd60 {
+                               compatible = "atmel,at91sam9260-gpbr", "syscon";
+                               reg = <0xfffffd60 0x10>;
+                               status = "disabled";
+                       };
+               };
+
+               fb0: fb@0x00500000 {
+                       compatible = "atmel,at91sam9g45-lcdc";
+                       reg = <0x00500000 0x1000>;
+                       interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_fb>;
+                       clocks = <&lcd_clk>, <&lcd_clk>;
+                       clock-names = "hclk", "lcdc_clk";
+                       status = "disabled";
+               };
+
+               nand0: nand@40000000 {
+                       compatible = "atmel,at91rm9200-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x40000000 0x10000000
+                              0xffffe200 0x200
+                             >;
+                       atmel,nand-addr-offset = <21>;
+                       atmel,nand-cmd-offset = <22>;
+                       atmel,nand-has-dma;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
+                       gpios = <&pioC 8 GPIO_ACTIVE_HIGH
+                                &pioC 14 GPIO_ACTIVE_HIGH
+                                0
+                               >;
+                       status = "disabled";
+               };
+
+               usb0: ohci@00700000 {
+                       compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                       reg = <0x00700000 0x100000>;
+                       interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+                       clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+                       clock-names = "ohci_clk", "hclk", "uhpck";
+                       status = "disabled";
+               };
+
+               usb1: ehci@00800000 {
+                       compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                       reg = <0x00800000 0x100000>;
+                       interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+                       clocks = <&utmi>, <&uhphs_clk>;
+                       clock-names = "usb_clk", "ehci_clk";
+                       status = "disabled";
+               };
+       };
+
+       i2c@0 {
+               compatible = "i2c-gpio";
+               gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
+                        &pioA 21 GPIO_ACTIVE_HIGH /* scl */
+                       >;
+               i2c-gpio,sda-open-drain;
+               i2c-gpio,scl-open-drain;
+               i2c-gpio,delay-us = <5>;        /* ~100 kHz */
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+};

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec278376910b6b5cde92aae91d97a9fd12cfb..0a7f1ffb2db39cac2caf62c10c7bf6c0f1b77d96 100644 (file)
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
        compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
        aliases {
+               spi0 = &qspi;
                spi1 = &dspi;
        };
 };
@@ -51,3 +52,16 @@
                reg = <2>;
        };
 };
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fs256s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c5a54e35f6df192471db4d43a4805aa327..68ed1338535c516512fac31cea2b2187210f2560 100644 (file)
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
                interrupts = <0 26 0x4>; /* Level high type */
                num-cs = <6>;
        };
+
+       qspi: quadspi@1550000 {
+               compatible = "fsl,vf610-qspi";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x0 0x20c0000 0x0 0x10000>,
+                       <0x0 0x20000000 0x0 0x10000000>;
+               reg-names = "QuadSPI", "QuadSPI-memory";
+               num-cs = <4>;
+       };
 };

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 8bbcc224546311213bf1ddccda9b0cb5981e89db..67318250607dd23604d2d799c4a4dff23764289b 100644 (file)
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,60 +17,55 @@
 
 #define hab_rvt_report_event_p                                 \
 (                                                              \
-       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
-         is_cpu_type(MXC_CPU_MX6D)) &&                         \
-         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       (is_mx6dqp()) ?                                         \
        ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
-       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
-        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
+       ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
+       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
        ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
        ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)        \
 )
 
 #define hab_rvt_report_status_p                                        \
 (                                                              \
-       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
-         is_cpu_type(MXC_CPU_MX6D)) &&                         \
-         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       (is_mx6dqp()) ?                                         \
+       ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
        ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
-       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
-        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
        ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
        ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)      \
 )
 
 #define hab_rvt_authenticate_image_p                           \
 (                                                              \
-       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
-         is_cpu_type(MXC_CPU_MX6D)) &&                         \
-         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       (is_mx6dqp()) ?                                         \
+       ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
        ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
-       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
-        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
        ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
        ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)    \
 )
 
 #define hab_rvt_entry_p                                                \
 (                                                              \
-       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
-         is_cpu_type(MXC_CPU_MX6D)) &&                         \
-         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       (is_mx6dqp()) ?                                         \
        ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
-       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
-        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
+       ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
+       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
        ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
        ((hab_rvt_entry_t *)HAB_RVT_ENTRY)                      \
 )
 
 #define hab_rvt_exit_p                                         \
 (                                                              \
-       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
-         is_cpu_type(MXC_CPU_MX6D)) &&                         \
-         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       (is_mx6dqp()) ?                                         \
+       ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
+       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
        ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
-       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
-        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
        ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
        ((hab_rvt_exit_t *)HAB_RVT_EXIT)                        \
 )
@@ -424,8 +419,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
                         */
                        /* Check MMU enabled */
                        if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
-                               if (is_cpu_type(MXC_CPU_MX6Q) ||
-                                   is_cpu_type(MXC_CPU_MX6D)) {
+                               if (is_mx6dq()) {
                                        /*
                                         * This won't work on Rev 1.0.0 of
                                         * i.MX6Q/D, since their ROM doesn't
@@ -434,10 +428,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
                                         */
                                        if (!is_mx6dqp())
                                                writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
-                               } else if (is_cpu_type(MXC_CPU_MX6DL) ||
-                                          is_cpu_type(MXC_CPU_MX6SOLO)) {
+                               } else if (is_mx6sdl()) {
                                        writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
-                               } else if (is_cpu_type(MXC_CPU_MX6SL)) {
+                               } else if (is_mx6sl()) {
                                        writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
                                }
                        }

diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index 15dab1d904239accc3676956ec5a8acbf3d8e444..3d2ce3a82e9addbd7a2ce735694b6a0b07b50d1c 100644 (file)
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,7 +44,7 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+       if (is_mx6sx() || is_mx7()) {
                /*
                 * Set all MPROTx to be non-bufferable, trusted for R/W,
                 * not forced to user-mode.
@@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable)
        writew(enable, &wdog1->wmcr);
        writew(enable, &wdog2->wmcr);
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-                       is_soc_type(MXC_SOC_MX7))
+       if (is_mx6sx() || is_mx6ul() || is_mx7())
                writew(enable, &wdog3->wmcr);
 #ifdef CONFIG_MX7D
        writew(enable, &wdog4->wmcr);

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 228d5f8f1cb75c88a39c79794607072da8942bb9..66137d148a7beea051b6ceccad2892259dd73f1b 100644 (file)
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 
 #if defined(CONFIG_MX6QDL)
        stride = 2;
-       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+       if (!is_mx6dq())
                p += 1;
 #else
        stride = 1;

diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index d174a463f88a70ed8d646a0e1c36e9f833d64e68..acf9831870c860fb4137e69b79f5c9524d933f73 100644 (file)
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,7 @@ int setup_sata(void)
        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
        int ret;
 
-       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+       if (!is_mx6dq() && !is_mx6dqp())
                return 1;
 
        ret = enable_sata_clock();

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 92c7218e699225ebf110845b6858cedf94903855..a01590ced2261c28d3ad9d02505eb7d6a9f58f70 100644 (file)
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
-       if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
-           (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-            is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
-            is_cpu_type(MXC_CPU_MX6UL))
+       if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+           is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
                return 1;
 
        return 0;
@@ -86,10 +84,7 @@ int timer_init(void)
                i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
                /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
-               if (is_cpu_type(MXC_CPU_MX6DL) ||
-                   is_cpu_type(MXC_CPU_MX6SOLO) ||
-                   is_cpu_type(MXC_CPU_MX6SX) ||
-                   is_cpu_type(MXC_CPU_MX6UL)) {
+               if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
                        i |= GPTCR_24MEN;
 
                        /* Produce 3Mhz clock */

diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h
new file mode 100644 (file)
index 0000000..da31f98
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM235XX_GPIO_H
+#define __ARCH_BCM235XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif

diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
new file mode 100644 (file)
index 0000000..90eb2ff
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM235XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR         0x3e016000
+#define BSC2_BASE_ADDR         0x3e017000
+#define BSC3_BASE_ADDR         0x3e018000
+#define GPIO2_BASE_ADDR                0x35003000
+#define HSOTG_BASE_ADDR                0x3f120000
+#define HSOTG_CTRL_BASE_ADDR   0x3f130000
+#define KONA_MST_CLK_BASE_ADDR 0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
+#define PMU_BSC_BASE_ADDR      0x3500d000
+#define SDIO1_BASE_ADDR                0x3f180000
+#define SDIO2_BASE_ADDR                0x3f190000
+#define SDIO3_BASE_ADDR                0x3f1a0000
+#define SDIO4_BASE_ADDR                0x3f1b0000
+#define TIMER_BASE_ADDR                0x3e00d000
+
+#define HSOTG_DCTL_OFFSET                                      0x00000804
+#define    HSOTG_DCTL_SFTDISCON_MASK                           0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET                            0x00000008
+#define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK                        0x00000002
+#define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK               0x00000001
+
+#endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 1cebe2fbb010736ae0e35a944773a025e3638701..df877ddc7dc0ec9c49787a4b8169285a18a6219d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -122,6 +122,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
          CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -176,6 +178,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
          CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357009a5deac414d80b4774aab750784dc68..8d12d6cb93fa6137e9380e1000e52c69522907d8 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR              0x023d0000
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
@@ -128,6 +129,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
 #define DCFG_RCWSR13                   0x130
 #define DCFG_RCWSR13_DSPI              (0 << 8)
+#define DCFG_RCWSR15                   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE         0X700100000ULL
 #define DCFG_DCSR_PORCR1               0x000
@@ -139,6 +142,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE              0x01fc0000
 #define SCFG_USB3PRM1CR                        0x000
+#define SCFG_QSPICLKCTLR       0x10
 
 #define TP_ITYP_AV             0x00000001      /* Initiator available */
 #define TP_ITYP_TYPE(x)        (((x) & 0x6) >> 1)      /* Initiator Type */

diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h
new file mode 100644 (file)
index 0000000..df92fb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/clock.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+       MXC_ARM_CLK = 0,
+       MXC_BUS_CLK,
+       MXC_PERIPHERALS_CLK,
+       MXC_UART_CLK,
+       MXC_USDHC_CLK,
+       MXC_FEC_CLK,
+       MXC_I2C_CLK,
+};
+enum pll_type {
+       ARM_PLL = 0,
+       PERIPH_PLL,
+       ENET_PLL,
+       DDR_PLL,
+       VIDEO_PLL,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void clock_init(void);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */

diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h
new file mode 100644 (file)
index 0000000..10a9a79
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/ddr.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
+#define __ARCH_ARM_MACH_S32V234_DDR_H__
+
+#define DDR0   0
+#define DDR1   1
+
+/* DDR offset in MSCR register */
+#define _DDR0_RESET    168
+#define _DDR0_CLK0     169
+#define _DDR0_CAS      170
+#define _DDR0_RAS      171
+#define _DDR0_WE_B     172
+#define _DDR0_CKE0     173
+#define _DDR0_CKE1     174
+#define _DDR0_CS_B0    175
+#define _DDR0_CS_B1    176
+#define _DDR0_BA0      177
+#define _DDR0_BA1      178
+#define _DDR0_BA2      179
+#define _DDR0_A0       180
+#define _DDR0_A1       181
+#define _DDR0_A2       182
+#define _DDR0_A3       183
+#define _DDR0_A4       184
+#define _DDR0_A5       185
+#define _DDR0_A6       186
+#define _DDR0_A7       187
+#define _DDR0_A8       188
+#define _DDR0_A9       189
+#define _DDR0_A10      190
+#define _DDR0_A11      191
+#define _DDR0_A12      192
+#define _DDR0_A13      193
+#define _DDR0_A14      194
+#define _DDR0_A15      195
+#define _DDR0_DM0      196
+#define _DDR0_DM1      197
+#define _DDR0_DM2      198
+#define _DDR0_DM3      199
+#define _DDR0_DQS0     200
+#define _DDR0_DQS1     201
+#define _DDR0_DQS2     202
+#define _DDR0_DQS3     203
+#define _DDR0_D0       204
+#define _DDR0_D1       205
+#define _DDR0_D2       206
+#define _DDR0_D3       207
+#define _DDR0_D4       208
+#define _DDR0_D5       209
+#define _DDR0_D6       210
+#define _DDR0_D7       211
+#define _DDR0_D8       212
+#define _DDR0_D9       213
+#define _DDR0_D10      214
+#define _DDR0_D11      215
+#define _DDR0_D12      216
+#define _DDR0_D13      217
+#define _DDR0_D14      218
+#define _DDR0_D15      219
+#define _DDR0_D16      220
+#define _DDR0_D17      221
+#define _DDR0_D18      222
+#define _DDR0_D19      223
+#define _DDR0_D20      224
+#define _DDR0_D21      225
+#define _DDR0_D22      226
+#define _DDR0_D23      227
+#define _DDR0_D24      228
+#define _DDR0_D25      229
+#define _DDR0_D26      230
+#define _DDR0_D27      231
+#define _DDR0_D28      232
+#define _DDR0_D29      233
+#define _DDR0_D30      234
+#define _DDR0_D31      235
+#define _DDR0_ODT0     236
+#define _DDR0_ODT1     237
+#define _DDR0_ZQ       238
+#define _DDR1_RESET    239
+#define _DDR1_CLK0     240
+#define _DDR1_CAS      241
+#define _DDR1_RAS      242
+#define _DDR1_WE_B     243
+#define _DDR1_CKE0     244
+#define _DDR1_CKE1     245
+#define _DDR1_CS_B0    246
+#define _DDR1_CS_B1    247
+#define _DDR1_BA0      248
+#define _DDR1_BA1      249
+#define _DDR1_BA2      250
+#define _DDR1_A0       251
+#define _DDR1_A1       252
+#define _DDR1_A2       253
+#define _DDR1_A3       254
+#define _DDR1_A4       255
+#define _DDR1_A5       256
+#define _DDR1_A6       257
+#define _DDR1_A7       258
+#define _DDR1_A8       259
+#define _DDR1_A9       260
+#define _DDR1_A10      261
+#define _DDR1_A11      262
+#define _DDR1_A12      263
+#define _DDR1_A13      264
+#define _DDR1_A14      265
+#define _DDR1_A15      266
+#define _DDR1_DM0      267
+#define _DDR1_DM1      268
+#define _DDR1_DM2      269
+#define _DDR1_DM3      270
+#define _DDR1_DQS0     271
+#define _DDR1_DQS1     272
+#define _DDR1_DQS2     273
+#define _DDR1_DQS3     274
+#define _DDR1_D0       275
+#define _DDR1_D1       276
+#define _DDR1_D2       277
+#define _DDR1_D3       278
+#define _DDR1_D4       279
+#define _DDR1_D5       280
+#define _DDR1_D6       281
+#define _DDR1_D7       282
+#define _DDR1_D8       283
+#define _DDR1_D9       284
+#define _DDR1_D10      285
+#define _DDR1_D11      286
+#define _DDR1_D12      287
+#define _DDR1_D13      288
+#define _DDR1_D14      289
+#define _DDR1_D15      290
+#define _DDR1_D16      291
+#define _DDR1_D17      292
+#define _DDR1_D18      293
+#define _DDR1_D19      294
+#define _DDR1_D20      295
+#define _DDR1_D21      296
+#define _DDR1_D22      297
+#define _DDR1_D23      298
+#define _DDR1_D24      299
+#define _DDR1_D25      300
+#define _DDR1_D26      301
+#define _DDR1_D27      302
+#define _DDR1_D28      303
+#define _DDR1_D29      304
+#define _DDR1_D30      305
+#define _DDR1_D31      306
+#define _DDR1_ODT0     307
+#define _DDR1_ODT1     308
+#define _DDR1_ZQ       309
+
+#endif

diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h
new file mode 100644 (file)
index 0000000..a42f6cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/imx-regs.h
@@ -0,0 +1,329 @@
+/*
+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR      0x3E800000 /* internal ram */
+#define IRAM_SIZE           0x00400000 /* 4MB */
+
+#define AIPS0_BASE_ADDR     (0x40000000UL)
+#define AIPS1_BASE_ADDR     (0x40080000UL)
+
+/* AIPS 0 */
+#define AXBS_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00000000)
+#define CSE3_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00001000)
+#define EDMA_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00002000)
+#define XRDC_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00004000)
+#define SWT0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0000A000)
+#define SWT1_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0000B000)
+#define STM0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC301_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00010000)
+#define GC3000_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00020000)
+#define DEC200_DECODER_BASE_ADDR               (AIPS0_BASE_ADDR + 0x00026000)
+#define DEC200_ENCODER_BASE_ADDR               (AIPS0_BASE_ADDR + 0x00027000)
+#define TWOD_ACE_BASE_ADDR                             (AIPS0_BASE_ADDR + 0x00028000)
+#define MIPI_CSI0_BASE_ADDR                            (AIPS0_BASE_ADDR + 0x00030000)
+#define DMAMUX0_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x00031000)
+#define ENET_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00032000)
+#define FLEXRAY_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x00034000)
+#define MMDC0_BASE_ADDR                                        (AIPS0_BASE_ADDR + 0x00036000)
+#define MEW0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00037000)
+#define MONITOR_DDR0_BASE_ADDR                 (AIPS0_BASE_ADDR + 0x00038000)
+#define MONITOR_CCI0_BASE_ADDR                 (AIPS0_BASE_ADDR + 0x00039000)
+#define PIT0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0003A000)
+#define MC_CGM0_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x0003C000)
+#define MC_CGM1_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x0003F000)
+#define MC_CGM2_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x00042000)
+#define MC_CGM3_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x00045000)
+#define MC_RGM_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00048000)
+#define MC_ME_BASE_ADDR                                        (AIPS0_BASE_ADDR + 0x0004A000)
+#define MC_PCU_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x0004B000)
+#define ADC0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0004D000)
+#define FLEXTIMER_BASE_ADDR                            (AIPS0_BASE_ADDR + 0x0004F000)
+#define I2C0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00051000)
+#define LINFLEXD0_BASE_ADDR                            (AIPS0_BASE_ADDR + 0x00053000)
+#define FLEXCAN0_BASE_ADDR                             (AIPS0_BASE_ADDR + 0x00055000)
+#define SPI0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00057000)
+#define SPI2_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00059000)
+#define CRC0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0005B000)
+#define USDHC_BASE_ADDR                                        (AIPS0_BASE_ADDR + 0x0005D000)
+#define OCOTP_CONTROLLER_BASE_ADDR             (AIPS0_BASE_ADDR + 0x0005F000)
+#define WKPU_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00063000)
+#define VIU0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00064000)
+#define HPSMI_SRAM_CONTROLLER_BASE_ADDR        (AIPS0_BASE_ADDR + 0x00068000)
+#define SIUL2_BASE_ADDR                                        (AIPS0_BASE_ADDR + 0x0006C000)
+#define SIPI_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00074000)
+#define LFAST_BASE_ADDR                                        (AIPS0_BASE_ADDR + 0x00078000)
+#define SSE_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00079000)
+#define SRC_SOC_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x0007C000)
+
+/* AIPS 1 */
+#define ERM_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000000000)
+#define MSCM_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000001000)
+#define SEMA42_BASE_ADDR                               (AIPS1_BASE_ADDR + 0X000002000)
+#define INTC_MON_BASE_ADDR                             (AIPS1_BASE_ADDR + 0X000003000)
+#define SWT2_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000004000)
+#define SWT3_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000005000)
+#define SWT4_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000006000)
+#define STM1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000007000)
+#define EIM_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000008000)
+#define APB_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000009000)
+#define XBIC_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000012000)
+#define MIPI_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000020000)
+#define DMAMUX1_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X000021000)
+#define MMDC1_BASE_ADDR                                        (AIPS1_BASE_ADDR + 0X000022000)
+#define MEW1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000023000)
+#define DDR1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000024000)
+#define CCI1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000025000)
+#define QUADSPI0_BASE_ADDR                             (AIPS1_BASE_ADDR + 0X000026000)
+#define PIT1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X00002A000)
+#define FCCU_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000030000)
+#define FLEXTIMER_FTM1_BASE_ADDR               (AIPS1_BASE_ADDR + 0X000036000)
+#define I2C1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000038000)
+#define I2C2_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X00003A000)
+#define LINFLEXD1_BASE_ADDR                            (AIPS1_BASE_ADDR + 0X00003C000)
+#define FLEXCAN1_BASE_ADDR                             (AIPS1_BASE_ADDR + 0X00003E000)
+#define SPI1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000040000)
+#define SPI3_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000042000)
+#define IPL_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000043000)
+#define CGM_CMU_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X000044000)
+#define PMC_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000048000)
+#define CRC1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X00004C000)
+#define TMU_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X00004E000)
+#define VIU1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000050000)
+#define JPEG_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000054000)
+#define H264_DEC_BASE_ADDR                             (AIPS1_BASE_ADDR + 0X000058000)
+#define H264_ENC_BASE_ADDR                             (AIPS1_BASE_ADDR + 0X00005C000)
+#define MEMU_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000060000)
+#define STCU_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000064000)
+#define SLFTST_CTRL_BASE_ADDR                  (AIPS1_BASE_ADDR + 0X000066000)
+#define MCT_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000068000)
+#define REP_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X00006A000)
+#define MBIST_CONTROLLER_BASE_ADDR             (AIPS1_BASE_ADDR + 0X00006C000)
+#define BOOT_LOADER_BASE_ADDR                  (AIPS1_BASE_ADDR + 0X00006F000)
+
+/* TODO Remove this after the IOMUX framework is implemented */
+#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
+
+/* MSCM interrupt router */
+#define MSCM_IRSPRC_CPn_EN             3
+#define MSCM_IRSPRC_NUM                        176
+#define MSCM_CPXTYPE_RYPZ_MASK         0xFF
+#define MSCM_CPXTYPE_RYPZ_OFFSET       0
+#define MSCM_CPXTYPE_PERS_MASK         0xFFFFFF00
+#define MSCM_CPXTYPE_PERS_OFFSET       8
+#define MSCM_CPXTYPE_PERS_A53          0x413533
+#define MSCM_CPXTYPE_PERS_CM4          0x434d34
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+       u32 bmr1;
+       u32 bmr2;
+       u32 gpr1_boot;
+       u32 reserved_0x00C[61];
+       u32 gpr1;
+       u32 gpr2;
+       u32 gpr3;
+       u32 gpr4;
+       u32 gpr5;
+       u32 gpr6;
+       u32 gpr7;
+       u32 reserved_0x11C[1];
+       u32 gpr9;
+       u32 gpr10;
+       u32 gpr11;
+       u32 gpr12;
+       u32 gpr13;
+       u32 gpr14;
+       u32 gpr15;
+       u32 gpr16;
+       u32 reserved_0x140[1];
+       u32 gpr17;
+       u32 gpr18;
+       u32 gpr19;
+       u32 gpr20;
+       u32 gpr21;
+       u32 gpr22;
+       u32 gpr23;
+       u32 gpr24;
+       u32 gpr25;
+       u32 gpr26;
+       u32 gpr27;
+       u32 reserved_0x16C[5];
+       u32 pcie_config1;
+       u32 ddr_self_ref_ctrl;
+       u32 pcie_config0;
+       u32 reserved_0x18C[4];
+       u32 soc_misc_config2;
+};
+
+/* SRC registers definitions */
+
+/* SRC_GPR1 */
+#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
+                                                                               (SRC_GPR1_PLL_OFFSET + (pll)) )
+#define SRC_GPR1_PLL_SOURCE_MASK       (0x1)
+
+#define SRC_GPR1_PLL_OFFSET                    (27)
+#define SRC_GPR1_FIRC_CLK_SOURCE       (0x0)
+#define SRC_GPR1_XOSC_CLK_SOURCE       (0x1)
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+       u32 mcr;
+       u32 recv0[55];
+       u32 ltmr64h;
+       u32 ltmr64l;
+       u32 recv1[6];
+       u32 ldval0;
+       u32 cval0;
+       u32 tctrl0;
+       u32 tflg0;
+       u32 ldval1;
+       u32 cval1;
+       u32 tctrl1;
+       u32 tflg1;
+       u32 ldval2;
+       u32 cval2;
+       u32 tctrl2;
+       u32 tflg2;
+       u32 ldval3;
+       u32 cval3;
+       u32 tctrl3;
+       u32 tflg3;
+       u32 ldval4;
+       u32 cval4;
+       u32 tctrl4;
+       u32 tflg4;
+       u32 ldval5;
+       u32 cval5;
+       u32 tctrl5;
+       u32 tflg5;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+       u32 cr;
+       u32 ir;
+       u32 to;
+       u32 wn;
+       u32 sr;
+       u32 co;
+       u32 sk;
+};
+
+/* UART */
+struct linflex_fsl {
+       u32 lincr1;
+       u32 linier;
+       u32 linsr;
+       u32 linesr;
+       u32 uartcr;
+       u32 uartsr;
+       u32 lintcsr;
+       u32 linocr;
+       u32 lintocr;
+       u32 linfbrr;
+       u32 linibrr;
+       u32 lincfr;
+       u32 lincr2;
+       u32 bidr;
+       u32 bdrl;
+       u32 bdrm;
+       u32 ifer;
+       u32 ifmi;
+       u32 ifmr;
+       u32 ifcr0;
+       u32 ifcr1;
+       u32 ifcr2;
+       u32 ifcr3;
+       u32 ifcr4;
+       u32 ifcr5;
+       u32 ifcr6;
+       u32 ifcr7;
+       u32 ifcr8;
+       u32 ifcr9;
+       u32 ifcr10;
+       u32 ifcr11;
+       u32 ifcr12;
+       u32 ifcr13;
+       u32 ifcr14;
+       u32 ifcr15;
+       u32 gcr;
+       u32 uartpto;
+       u32 uartcto;
+       u32 dmatxe;
+       u32 dmarxe;
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+       u32 cpxtype;            /* Processor x Type Register                    */
+       u32 cpxnum;             /* Processor x Number Register                  */
+       u32 cpxmaster;          /* Processor x Master Number Register   */
+       u32 cpxcount;           /* Processor x Count Register                   */
+       u32 cpxcfg0;            /* Processor x Configuration 0 Register */
+       u32 cpxcfg1;            /* Processor x Configuration 1 Register */
+       u32 cpxcfg2;            /* Processor x Configuration 2 Register */
+       u32 cpxcfg3;            /* Processor x Configuration 3 Register */
+       u32 cp0type;            /* Processor 0 Type Register                    */
+       u32 cp0num;             /* Processor 0 Number Register                  */
+       u32 cp0master;          /* Processor 0 Master Number Register   */
+       u32 cp0count;           /* Processor 0 Count Register                   */
+       u32 cp0cfg0;            /* Processor 0 Configuration 0 Register */
+       u32 cp0cfg1;            /* Processor 0 Configuration 1 Register */
+       u32 cp0cfg2;            /* Processor 0 Configuration 2 Register */
+       u32 cp0cfg3;            /* Processor 0 Configuration 3 Register */
+       u32 cp1type;            /* Processor 1 Type Register                    */
+       u32 cp1num;             /* Processor 1 Number Register                  */
+       u32 cp1master;          /* Processor 1 Master Number Register   */
+       u32 cp1count;           /* Processor 1 Count Register                   */
+       u32 cp1cfg0;            /* Processor 1 Configuration 0 Register */
+       u32 cp1cfg1;            /* Processor 1 Configuration 1 Register */
+       u32 cp1cfg2;            /* Processor 1 Configuration 2 Register */
+       u32 cp1cfg3;            /* Processor 1 Configuration 3 Register */
+       u32 reserved_0x060[232];
+       u32 ocmdr0;             /* On-Chip Memory Descriptor Register   */
+       u32 reserved_0x404[2];
+       u32 ocmdr3;             /* On-Chip Memory Descriptor Register   */
+       u32 reserved_0x410[28];
+       u32 tcmdr[4];           /* Generic Tightly Coupled Memory Descriptor Register   */
+       u32 reserved_0x490[28];
+       u32 cpce0;              /* Core Parity Checking Enable Register 0                               */
+       u32 reserved_0x504[191];
+       u32 ircp0ir;            /* Interrupt Router CP0 Interrupt Register                              */
+       u32 ircp1ir;            /* Interrupt Router CP1 Interrupt Register                              */
+       u32 reserved_0x808[6];
+       u32 ircpgir;            /* Interrupt Router CPU Generate Interrupt Register             */
+       u32 reserved_0x824[23];
+       u16 irsprc[176];        /* Interrupt Router Shared Peripheral Routing Control Register  */
+       u32 reserved_0x9e0[136];
+       u32 iahbbe0;            /* Gasket Burst Enable Register                                                 */
+       u32 reserved_0xc04[63];
+       u32 ipcge;              /* Interconnect Parity Checking Global Enable Register  */
+       u32 reserved_0xd04[3];
+       u32 ipce[4];            /* Interconnect Parity Checking Enable Register                 */
+       u32 reserved_0xd20[8];
+       u32 ipcgie;             /* Interconnect Parity Checking Global Injection Enable Register        */
+       u32 reserved_0xd44[3];
+       u32 ipcie[4];           /* Interconnect Parity Checking Injection Enable Register       */
+};
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */

diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h
new file mode 100644 (file)
index 0000000..5a05965
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/lpddr2.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
+#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
+
+/* definitions for LPDDR2 PAD values */
+#define LPDDR2_CLK0_PAD        \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+        SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 |                    \
+        SIUL2_MSCR_DCYCLE_TRIM_NONE)
+#define LPDDR2_CKEn_PAD        \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+        SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_CS_Bn_PAD       \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+        SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_DMn_PAD \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+        SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_DQSn_PAD        \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |        \
+        SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN |                                          \
+        SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
+#define LPDDR2_An_PAD  \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |        \
+        SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT               |       \
+        SIUL2_MSCR_PUS_100K_UP)
+#define LPDDR2_Dn_PAD  \
+       (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |        \
+        SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT               |       \
+        SIUL2_MSCR_PUS_100K_UP)
+
+#define _MDCTL                                                 0x03010000
+
+#define MMDC_MDSCR_CFG_VALUE                   0x00008000      /* Set MDSCR[CON_REQ] (configuration request) */
+#define MMDC_MDCFG0_VALUE                              0x464F61A5      /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
+#define MMDC_MDCFG1_VALUE                              0x00180E63      /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
+#define MMDC_MDCFG2_VALUE                              0x000000DD      /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
+#define MMDC_MDCFG3LP_VALUE                            0x001F099B      /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
+#define MMDC_MDOTC_VALUE                               0x00000000      /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
+#define MMDC_MDMISC_VALUE                              0x00001688      /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
+#define MMDC_MDOR_VALUE                                        0x00000010      /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
+#define MMDC_MPMUR0_VALUE                              0x00000800      /* Force delay line initialisation */
+#define MMDC_MDSCR_RST_VALUE                   0x003F8030      /* Reset command CS0 */
+#define MMDC_MPZQLP2CTL_VALUE                  0x1B5F0109      /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
+#define MMDC_MPZQHWCTRL_VALUE                  0xA0010003      /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
+#define MMDC_MDSCR_MR1_VALUE                   0xC2018030      /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
+#define MMDC_MDSCR_MR2_VALUE                   0x06028030      /* Configure MR2: RL=8, WL=4 */
+#define MMDC_MDSCR_MR3_VALUE                   0x01038030      /* Configure MR3: DS=34R */
+#define MMDC_MDSCR_MR10_VALUE                  0xFF0A8030      /* Configure MR10: Calibration at init */
+#define MMDC_MDASP_MODULE0_VALUE               0x0000007F      /* 2Gb, 256 MB memory so CS0 is 256 MB  (0x90000000) */
+#define MMDC_MPRDDLCTL_MODULE0_VALUE   0x4D4B4F4B      /* Read delay line offsets */
+#define MMDC_MPWRDLCTL_MODULE0_VALUE   0x38383737      /* Write delay line offsets */
+#define MMDC_MPDGCTRL0_MODULE0_VALUE   0x20000000      /* Read DQS gating control 0 (disabled) */
+#define MMDC_MPDGCTRL1_MODULE0_VALUE   0x00000000      /* Read DQS gating control 1 */
+#define MMDC_MDASP_MODULE1_VALUE               0x0000007F      /* 2Gb, 256 MB memory so CS0 is 256 MB  (0xD0000000) */
+#define MMDC_MPRDDLCTL_MODULE1_VALUE   0x4D4B4F4B      /* Read delay line offsets */
+#define MMDC_MPWRDLCTL_MODULE1_VALUE   0x38383737      /* Write delay line offsets */
+#define MMDC_MPDGCTRL0_MODULE1_VALUE   0x20000000      /* Read DQS gating control 0 (disabled) */
+#define MMDC_MPDGCTRL1_MODULE1_VALUE   0x00000000      /* Read DQS gating control 1 */
+#define MMDC_MDRWD_VALUE                               0x0F9F26D2      /* Read/write command delay - default used */
+#define MMDC_MDPDC_VALUE                               0x00020024      /* Power down control */
+#define MMDC_MDREF_VALUE                               0x30B01800      /* Refresh control */
+#define MMDC_MPODTCTRL_VALUE                   0x00000000      /* No ODT */
+#define MMDC_MDSCR_DEASSERT_VALUE                              0x00000000      /* Deassert the configuration request */
+
+/* set I/O pads for DDR */
+void lpddr2_config_iomux(uint8_t module);
+void config_mmdc(uint8_t module);
+
+#endif

diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
new file mode 100644 (file)
index 0000000..eb50475
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* MC_CGM registers definitions */
+/* MC_CGM_SC_SS */
+#define CGM_SC_SS(cgm_addr)                    ( ((cgm_addr) + 0x000007E4) )
+#define MC_CGM_SC_SEL_FIRC                     (0x0)
+#define MC_CGM_SC_SEL_XOSC                     (0x1)
+#define MC_CGM_SC_SEL_ARMPLL           (0x2)
+#define MC_CGM_SC_SEL_CLKDISABLE       (0xF)
+
+/* MC_CGM_SC_DCn */
+#define CGM_SC_DCn(cgm_addr,dc)                ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
+#define MC_CGM_SC_DCn_PREDIV(val)      (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
+#define MC_CGM_SC_DCn_PREDIV_MASK      (0x00070000)
+#define MC_CGM_SC_DCn_PREDIV_OFFSET    (16)
+#define MC_CGM_SC_DCn_DE                       (1 << 31)
+#define MC_CGM_SC_SEL_MASK                     (0x0F000000)
+#define MC_CGM_SC_SEL_OFFSET           (24)
+
+/* MC_CGM_ACn_DCm */
+#define CGM_ACn_DCm(cgm_addr,ac,dc)            ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
+#define MC_CGM_ACn_DCm_PREDIV(val)             (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
+
+/*
+ * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
+ * that the 5th bit is always ignored during writes if the current
+ * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
+ *
+ * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
+ *
+ * This should be changed if any problems occur.
+ */
+#define MC_CGM_ACn_DCm_PREDIV_MASK             (0x001F0000)
+#define MC_CGM_ACn_DCm_PREDIV_OFFSET   (16)
+#define MC_CGM_ACn_DCm_DE                              (1 << 31)
+
+/*
+ * MC_CGM_ACn_SC/MC_CGM_ACn_SS
+ */
+#define CGM_ACn_SC(cgm_addr,ac)                        ((cgm_addr + 0x00000800) + ((ac) * 0x20))
+#define CGM_ACn_SS(cgm_addr,ac)                        ((cgm_addr + 0x00000804) + ((ac) * 0x20))
+#define MC_CGM_ACn_SEL_MASK                            (0x07000000)
+#define MC_CGM_ACn_SEL_SET(source)             (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
+#define MC_CGM_ACn_SEL_OFFSET                  (24)
+
+#define MC_CGM_ACn_SEL_FIRC                            (0x0)
+#define MC_CGM_ACn_SEL_XOSC                            (0x1)
+#define MC_CGM_ACn_SEL_ARMPLL                  (0x2)
+/*
+ * According to the manual some PLL can be divided by X (X={1,3,5}):
+ * PERPLLDIVX, VIDEOPLLDIVX.
+ */
+#define MC_CGM_ACn_SEL_PERPLLDIVX              (0x3)
+#define MC_CGM_ACn_SEL_ENETPLL                 (0x4)
+#define MC_CGM_ACn_SEL_DDRPLL                  (0x5)
+#define MC_CGM_ACn_SEL_EXTSRCPAD               (0x7)
+#define MC_CGM_ACn_SEL_SYSCLK                  (0x8)
+#define MC_CGM_ACn_SEL_VIDEOPLLDIVX            (0x9)
+#define MC_CGM_ACn_SEL_PERCLK                  (0xA)
+
+/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
+#define PLLDIG_PLLDV(pll)                              ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
+#define PLLDIG_PLLDV_MFD(div)                  (PLLDIG_PLLDV_MFD_MASK & (div))
+#define PLLDIG_PLLDV_MFD_MASK                  (0x000000FF)
+
+/*
+ * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
+ * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
+ */
+#define PLLDIG_PLLDV_RFDPHI_SET(val)   (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
+#define PLLDIG_PLLDV_RFDPHI_MASK               (0x003F0000)
+#define PLLDIG_PLLDV_RFDPHI_MAXVALUE   (0x3F)
+#define PLLDIG_PLLDV_RFDPHI_OFFSET             (16)
+
+#define PLLDIG_PLLDV_RFDPHI1_SET(val)  (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
+#define PLLDIG_PLLDV_RFDPHI1_MASK              (0x7E000000)
+#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE  (0x3F)
+#define PLLDIG_PLLDV_RFDPHI1_OFFSET            (25)
+
+#define PLLDIG_PLLDV_PREDIV_SET(val)   (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
+#define PLLDIG_PLLDV_PREDIV_MASK               (0x00007000)
+#define PLLDIG_PLLDV_PREDIV_MAXVALUE   (0x7)
+#define PLLDIG_PLLDV_PREDIV_OFFSET             (12)
+
+/* PLLDIG PLL Fractional  Divide Register (PLLDIG_PLLFD) */
+#define PLLDIG_PLLFD(pll)                              ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
+#define PLLDIG_PLLFD_MFN_SET(val)              (PLLDIG_PLLFD_MFN_MASK & (val))
+#define PLLDIG_PLLFD_MFN_MASK                  (0x00007FFF)
+#define PLLDIG_PLLFD_SMDEN                             (1 << 30)
+
+/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
+#define PLLDIG_PLLCAL1(pll)                            ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
+#define PLLDIG_PLLCAL1_NDAC1_SET(val)  (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
+#define PLLDIG_PLLCAL1_NDAC1_OFFSET            (24)
+#define PLLDIG_PLLCAL1_NDAC1_MASK              (0x7F000000)
+
+/* Digital Frequency Synthesizer (DFS) */
+/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
+#define DFS0_BASE_ADDR                         (MC_CGM0_BASE_ADDR + 0x00000040)
+
+/* DFS DLL Program Register 1 */
+#define DFS_DLLPRG1(pll)                       (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
+
+#define DFS_DLLPRG1_V2IGC_SET(val)     (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
+#define DFS_DLLPRG1_V2IGC_OFFSET       (0)
+#define DFS_DLLPRG1_V2IGC_MASK         (0x00000007)
+
+#define DFS_DLLPRG1_LCKWT_SET(val)             (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
+#define DFS_DLLPRG1_LCKWT_OFFSET               (4)
+#define DFS_DLLPRG1_LCKWT_MASK                 (0x00000030)
+
+#define DFS_DLLPRG1_DACIN_SET(val)             (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
+#define DFS_DLLPRG1_DACIN_OFFSET               (6)
+#define DFS_DLLPRG1_DACIN_MASK                 (0x000001C0)
+
+#define DFS_DLLPRG1_CALBYPEN_SET(val)  (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
+#define DFS_DLLPRG1_CALBYPEN_OFFSET            (9)
+#define DFS_DLLPRG1_CALBYPEN_MASK              (0x00000200)
+
+#define DFS_DLLPRG1_VSETTLCTRL_SET(val)        (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
+#define DFS_DLLPRG1_VSETTLCTRL_OFFSET  (10)
+#define DFS_DLLPRG1_VSETTLCTRL_MASK            (0x00000C00)
+
+#define DFS_DLLPRG1_CPICTRL_SET(val)   (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
+#define DFS_DLLPRG1_CPICTRL_OFFSET             (12)
+#define DFS_DLLPRG1_CPICTRL_MASK               (0x00007000)
+
+/* DFS Control Register (DFS_CTRL) */
+#define DFS_CTRL(pll)                                  (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
+#define DFS_CTRL_DLL_LOLIE                             (1 << 0)
+#define DFS_CTRL_DLL_RESET                             (1 << 1)
+
+/* DFS Port Status Register (DFS_PORTSR) */
+#define DFS_PORTSR(pll)                                                (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
+/* DFS Port Reset Register (DFS_PORTRESET) */
+#define DFS_PORTRESET(pll)                                     (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
+#define DFS_PORTRESET_PORTRESET_SET(val)       (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
+#define DFS_PORTRESET_PORTRESET_MAXVAL         (0xF)
+#define DFS_PORTRESET_PORTRESET_MASK           (0x0000000F)
+#define DFS_PORTRESET_PORTRESET_OFFSET         (0)
+
+/* DFS Divide Register Portn (DFS_DVPORTn) */
+#define DFS_DVPORTn(pll,n)                     (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
+
+/*
+ * The mathematical formula for fdfs_clockout is the following:
+ * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
+ */
+#define DFS_DVPORTn_MFI_SET(val)       (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
+#define DFS_DVPORTn_MFN_SET(val)       (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
+#define DFS_DVPORTn_MFI_MASK           (0x0000FF00)
+#define DFS_DVPORTn_MFN_MASK           (0x000000FF)
+#define DFS_DVPORTn_MFI_MAXVAL         (0xFF)
+#define DFS_DVPORTn_MFN_MAXVAL         (0xFF)
+#define DFS_DVPORTn_MFI_OFFSET         (8)
+#define DFS_DVPORTn_MFN_OFFSET         (0)
+#define DFS_MAXNUMBER                          (4)
+
+#define DFS_PARAMS_Nr                          (3)
+
+/* Frequencies are in Hz */
+#define FIRC_CLK_FREQ                          (48000000)
+#define XOSC_CLK_FREQ                          (40000000)
+
+#define PLL_MIN_FREQ                           (650000000)
+#define PLL_MAX_FREQ                           (1300000000)
+
+#define ARM_PLL_PHI0_FREQ                      (1000000000)
+#define ARM_PLL_PHI1_FREQ                      (1000000000)
+/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
+#define ARM_PLL_PHI1_DFS1_EN           (1)
+#define ARM_PLL_PHI1_DFS1_MFI          (3)
+#define ARM_PLL_PHI1_DFS1_MFN          (194)
+/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
+#define ARM_PLL_PHI1_DFS2_EN           (1)
+#define ARM_PLL_PHI1_DFS2_MFI          (1)
+#define ARM_PLL_PHI1_DFS2_MFN          (170)
+/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
+#define ARM_PLL_PHI1_DFS3_EN           (1)
+#define ARM_PLL_PHI1_DFS3_MFI          (1)
+#define ARM_PLL_PHI1_DFS3_MFN          (170)
+#define ARM_PLL_PHI1_DFS_Nr                    (3)
+#define ARM_PLL_PLLDV_PREDIV           (2)
+#define ARM_PLL_PLLDV_MFD                      (50)
+#define ARM_PLL_PLLDV_MFN                      (0)
+
+#define PERIPH_PLL_PHI0_FREQ           (400000000)
+#define PERIPH_PLL_PHI1_FREQ           (100000000)
+#define PERIPH_PLL_PHI1_DFS_Nr         (0)
+#define PERIPH_PLL_PLLDV_PREDIV                (1)
+#define PERIPH_PLL_PLLDV_MFD           (30)
+#define PERIPH_PLL_PLLDV_MFN           (0)
+
+#define ENET_PLL_PHI0_FREQ                     (500000000)
+#define ENET_PLL_PHI1_FREQ                     (1000000000)
+/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
+#define ENET_PLL_PHI1_DFS1_EN          (1)
+#define ENET_PLL_PHI1_DFS1_MFI         (2)
+#define ENET_PLL_PHI1_DFS1_MFN         (219)
+/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
+#define ENET_PLL_PHI1_DFS2_EN          (1)
+#define ENET_PLL_PHI1_DFS2_MFI         (2)
+#define ENET_PLL_PHI1_DFS2_MFN         (219)
+/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
+#define ENET_PLL_PHI1_DFS3_EN          (1)
+#define ENET_PLL_PHI1_DFS3_MFI         (3)
+#define ENET_PLL_PHI1_DFS3_MFN         (32)
+/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
+#define ENET_PLL_PHI1_DFS4_EN          (1)
+#define ENET_PLL_PHI1_DFS4_MFI         (2)
+#define ENET_PLL_PHI1_DFS4_MFN         (0)
+#define ENET_PLL_PHI1_DFS_Nr           (4)
+#define ENET_PLL_PLLDV_PREDIV          (2)
+#define ENET_PLL_PLLDV_MFD                     (50)
+#define ENET_PLL_PLLDV_MFN                     (0)
+
+#define DDR_PLL_PHI0_FREQ                      (533000000)
+#define DDR_PLL_PHI1_FREQ                      (1066000000)
+/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
+#define DDR_PLL_PHI1_DFS1_EN           (1)
+#define DDR_PLL_PHI1_DFS1_MFI          (2)
+#define DDR_PLL_PHI1_DFS1_MFN          (33)
+/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
+#define DDR_PLL_PHI1_DFS2_EN           (1)
+#define DDR_PLL_PHI1_DFS2_MFI          (2)
+#define DDR_PLL_PHI1_DFS2_MFN          (33)
+/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
+#define DDR_PLL_PHI1_DFS3_EN           (1)
+#define DDR_PLL_PHI1_DFS3_MFI          (3)
+#define DDR_PLL_PHI1_DFS3_MFN          (11)
+#define DDR_PLL_PHI1_DFS_Nr                    (3)
+#define DDR_PLL_PLLDV_PREDIV           (2)
+#define DDR_PLL_PLLDV_MFD                      (53)
+#define DDR_PLL_PLLDV_MFN                      (6144)
+
+#define VIDEO_PLL_PHI0_FREQ                    (600000000)
+#define VIDEO_PLL_PHI1_FREQ                    (0)
+#define VIDEO_PLL_PHI1_DFS_Nr          (0)
+#define VIDEO_PLL_PLLDV_PREDIV         (1)
+#define VIDEO_PLL_PLLDV_MFD                    (30)
+#define VIDEO_PLL_PLLDV_MFN                    (0)
+
+#endif
+
+#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */

diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
new file mode 100644 (file)
index 0000000..a1172e0
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* MC_ME registers definitions */
+
+/* MC_ME_GS */
+#define MC_ME_GS                                               (MC_ME_BASE_ADDR + 0x00000000)
+
+#define MC_ME_GS_S_SYSCLK_FIRC                 (0x0 << 0)
+#define MC_ME_GS_S_SYSCLK_FXOSC                        (0x1 << 0)
+#define MC_ME_GS_S_SYSCLK_ARMPLL               (0x2 << 0)
+#define MC_ME_GS_S_STSCLK_DISABLE              (0xF << 0)
+#define MC_ME_GS_S_FIRC                                        (1 << 4)
+#define MC_ME_GS_S_XOSC                                        (1 << 5)
+#define MC_ME_GS_S_ARMPLL                              (1 << 6)
+#define MC_ME_GS_S_PERPLL                              (1 << 7)
+#define MC_ME_GS_S_ENETPLL                             (1 << 8)
+#define MC_ME_GS_S_DDRPLL                              (1 << 9)
+#define MC_ME_GS_S_VIDEOPLL                            (1 << 10)
+#define MC_ME_GS_S_MVR                                 (1 << 20)
+#define MC_ME_GS_S_PDO                                 (1 << 23)
+#define MC_ME_GS_S_MTRANS                              (1 << 27)
+#define MC_ME_GS_S_CRT_MODE_RESET              (0x0 << 28)
+#define MC_ME_GS_S_CRT_MODE_TEST               (0x1 << 28)
+#define MC_ME_GS_S_CRT_MODE_DRUN               (0x3 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN0               (0x4 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN1               (0x5 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN2               (0x6 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN3               (0x7 << 28)
+
+/* MC_ME_MCTL */
+#define MC_ME_MCTL                                             (MC_ME_BASE_ADDR + 0x00000004)
+
+#define MC_ME_MCTL_KEY                                 (0x00005AF0)
+#define MC_ME_MCTL_INVERTEDKEY                 (0x0000A50F)
+#define MC_ME_MCTL_RESET                               (0x0 << 28)
+#define MC_ME_MCTL_TEST                                        (0x1 << 28)
+#define MC_ME_MCTL_DRUN                                        (0x3 << 28)
+#define MC_ME_MCTL_RUN0                                        (0x4 << 28)
+#define MC_ME_MCTL_RUN1                                        (0x5 << 28)
+#define MC_ME_MCTL_RUN2                                        (0x6 << 28)
+#define MC_ME_MCTL_RUN3                                        (0x7 << 28)
+
+/* MC_ME_ME */
+#define MC_ME_ME                                               (MC_ME_BASE_ADDR + 0x00000008)
+
+#define MC_ME_ME_RESET_FUNC                            (1 << 0)
+#define MC_ME_ME_TEST                                  (1 << 1)
+#define MC_ME_ME_DRUN                                  (1 << 3)
+#define MC_ME_ME_RUN0                                  (1 << 4)
+#define MC_ME_ME_RUN1                                  (1 << 5)
+#define MC_ME_ME_RUN2                                  (1 << 6)
+#define MC_ME_ME_RUN3                                  (1 << 7)
+
+/* MC_ME_RUN_PCn */
+#define MC_ME_RUN_PCn(n)                               (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
+
+#define MC_ME_RUN_PCn_RESET                            (1 << 0)
+#define MC_ME_RUN_PCn_TEST                             (1 << 1)
+#define MC_ME_RUN_PCn_DRUN                             (1 << 3)
+#define MC_ME_RUN_PCn_RUN0                             (1 << 4)
+#define MC_ME_RUN_PCn_RUN1                             (1 << 5)
+#define MC_ME_RUN_PCn_RUN2                             (1 << 6)
+#define MC_ME_RUN_PCn_RUN3                             (1 << 7)
+
+/*
+ * MC_ME_RESET_MC/MC_ME_TEST_MC
+ * MC_ME_DRUN_MC
+ * MC_ME_RUNn_MC
+ */
+#define MC_ME_RESET_MC                                         (MC_ME_BASE_ADDR + 0x00000020)
+#define MC_ME_TEST_MC                                          (MC_ME_BASE_ADDR + 0x00000024)
+#define MC_ME_DRUN_MC                                          (MC_ME_BASE_ADDR + 0x0000002C)
+#define MC_ME_RUNn_MC(n)                                       (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
+
+#define MC_ME_RUNMODE_MC_SYSCLK(val)   (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
+#define MC_ME_RUNMODE_MC_SYSCLK_MASK   (0x0000000F)
+#define MC_ME_RUNMODE_MC_FIRCON                        (1 << 4)
+#define MC_ME_RUNMODE_MC_XOSCON                        (1 << 5)
+#define MC_ME_RUNMODE_MC_PLL(pll)              (1 << (6 + (pll)))
+#define MC_ME_RUNMODE_MC_MVRON                 (1 << 20)
+#define MC_ME_RUNMODE_MC_PDO                   (1 << 23)
+#define MC_ME_RUNMODE_MC_PWRLVL0               (1 << 28)
+#define MC_ME_RUNMODE_MC_PWRLVL1               (1 << 29)
+#define MC_ME_RUNMODE_MC_PWRLVL2               (1 << 30)
+
+/* MC_ME_DRUN_SEC_CC_I */
+#define MC_ME_DRUN_SEC_CC_I                                    (MC_ME_BASE_ADDR + 0x260)
+/* MC_ME_RUNn_SEC_CC_I */
+#define MC_ME_RUNn_SEC_CC_I(n)                         (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)      ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET  (4)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET  (8)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET  (12)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK             (0x3)
+
+/*
+ * ME_PCTLn
+ * Please note that these registers are 8 bits width, so
+ * the operations over them should be done using 8 bits operations.
+ */
+#define MC_ME_PCTLn_RUNPCm(n)                  ( (n) & MC_ME_PCTLn_RUNPCm_MASK )
+#define MC_ME_PCTLn_RUNPCm_MASK                        (0x7)
+
+/* DEC200 Peripheral Control Register          */
+#define MC_ME_PCTL39   (MC_ME_BASE_ADDR + 0x000000E4)
+/* 2D-ACE Peripheral Control Register          */
+#define MC_ME_PCTL40   (MC_ME_BASE_ADDR + 0x000000EB)
+/* ENET Peripheral Control Register            */
+#define MC_ME_PCTL50   (MC_ME_BASE_ADDR + 0x000000F1)
+/* DMACHMUX0 Peripheral Control Register       */
+#define MC_ME_PCTL49   (MC_ME_BASE_ADDR + 0x000000F2)
+/* CSI0 Peripheral Control Register                    */
+#define MC_ME_PCTL48   (MC_ME_BASE_ADDR + 0x000000F3)
+/* MMDC0 Peripheral Control Register           */
+#define MC_ME_PCTL54   (MC_ME_BASE_ADDR + 0x000000F5)
+/* FRAY Peripheral Control Register                    */
+#define MC_ME_PCTL52   (MC_ME_BASE_ADDR + 0x000000F7)
+/* PIT0 Peripheral Control Register                    */
+#define MC_ME_PCTL58   (MC_ME_BASE_ADDR + 0x000000F9)
+/* FlexTIMER0 Peripheral Control Register      */
+#define MC_ME_PCTL79   (MC_ME_BASE_ADDR + 0x0000010C)
+/* SARADC0 Peripheral Control Register         */
+#define MC_ME_PCTL77   (MC_ME_BASE_ADDR + 0x0000010E)
+/* LINFLEX0 Peripheral Control Register                */
+#define MC_ME_PCTL83   (MC_ME_BASE_ADDR + 0x00000110)
+/* IIC0 Peripheral Control Register                    */
+#define MC_ME_PCTL81   (MC_ME_BASE_ADDR + 0x00000112)
+/* DSPI0 Peripheral Control Register           */
+#define MC_ME_PCTL87   (MC_ME_BASE_ADDR + 0x00000114)
+/* CANFD0 Peripheral Control Register          */
+#define MC_ME_PCTL85   (MC_ME_BASE_ADDR + 0x00000116)
+/* CRC0 Peripheral Control Register                    */
+#define MC_ME_PCTL91   (MC_ME_BASE_ADDR + 0x00000118)
+/* DSPI2 Peripheral Control Register           */
+#define MC_ME_PCTL89   (MC_ME_BASE_ADDR + 0x0000011A)
+/* SDHC Peripheral Control Register                    */
+#define MC_ME_PCTL93   (MC_ME_BASE_ADDR + 0x0000011E)
+/* VIU0 Peripheral Control Register                    */
+#define MC_ME_PCTL100  (MC_ME_BASE_ADDR + 0x00000127)
+/* HPSMI Peripheral Control Register           */
+#define MC_ME_PCTL104  (MC_ME_BASE_ADDR + 0x0000012B)
+/* SIPI Peripheral Control Register                    */
+#define MC_ME_PCTL116  (MC_ME_BASE_ADDR + 0x00000137)
+/* LFAST Peripheral Control Register           */
+#define MC_ME_PCTL120  (MC_ME_BASE_ADDR + 0x0000013B)
+/* MMDC1 Peripheral Control Register           */
+#define MC_ME_PCTL162  (MC_ME_BASE_ADDR + 0x00000161)
+/* DMACHMUX1 Peripheral Control Register       */
+#define MC_ME_PCTL161  (MC_ME_BASE_ADDR + 0x00000162)
+/* CSI1 Peripheral Control Register                    */
+#define MC_ME_PCTL160  (MC_ME_BASE_ADDR + 0x00000163)
+/* QUADSPI0 Peripheral Control Register                */
+#define MC_ME_PCTL166  (MC_ME_BASE_ADDR + 0x00000165)
+/* PIT1 Peripheral Control Register                    */
+#define MC_ME_PCTL170  (MC_ME_BASE_ADDR + 0x00000169)
+/* FlexTIMER1 Peripheral Control Register      */
+#define MC_ME_PCTL182  (MC_ME_BASE_ADDR + 0x00000175)
+/* IIC2 Peripheral Control Register                    */
+#define MC_ME_PCTL186  (MC_ME_BASE_ADDR + 0x00000179)
+/* IIC1 Peripheral Control Register                    */
+#define MC_ME_PCTL184  (MC_ME_BASE_ADDR + 0x0000017B)
+/* CANFD1 Peripheral Control Register          */
+#define MC_ME_PCTL190  (MC_ME_BASE_ADDR + 0x0000017D)
+/* LINFLEX1 Peripheral Control Register                */
+#define MC_ME_PCTL188  (MC_ME_BASE_ADDR + 0x0000017F)
+/* DSPI3 Peripheral Control Register           */
+#define MC_ME_PCTL194  (MC_ME_BASE_ADDR + 0x00000181)
+/* DSPI1 Peripheral Control Register           */
+#define MC_ME_PCTL192  (MC_ME_BASE_ADDR + 0x00000183)
+/* TSENS Peripheral Control Register           */
+#define MC_ME_PCTL206  (MC_ME_BASE_ADDR + 0x0000018D)
+/* CRC1 Peripheral Control Register                    */
+#define MC_ME_PCTL204  (MC_ME_BASE_ADDR + 0x0000018F)
+/* VIU1 Peripheral Control Register            */
+#define MC_ME_PCTL208  (MC_ME_BASE_ADDR + 0x00000193)
+/* JPEG Peripheral Control Register            */
+#define MC_ME_PCTL212  (MC_ME_BASE_ADDR + 0x00000197)
+/* H264_DEC Peripheral Control Register        */
+#define MC_ME_PCTL216  (MC_ME_BASE_ADDR + 0x0000019B)
+/* H264_ENC Peripheral Control Register        */
+#define MC_ME_PCTL220  (MC_ME_BASE_ADDR + 0x0000019F)
+/* MBIST Peripheral Control Register   */
+#define MC_ME_PCTL236  (MC_ME_BASE_ADDR + 0x000001A9)
+
+/* Core status register */
+#define MC_ME_CS               (MC_ME_BASE_ADDR + 0x000001C0)
+
+#endif
+
+#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */

diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
new file mode 100644 (file)
index 0000000..f39e81b
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
+
+#define MC_RGM_DES                     (MC_RGM_BASE_ADDR)
+#define MC_RGM_FES                     (MC_RGM_BASE_ADDR + 0x300)
+#define MC_RGM_FERD                    (MC_RGM_BASE_ADDR + 0x310)
+#define MC_RGM_FBRE                    (MC_RGM_BASE_ADDR + 0x330)
+#define MC_RGM_FESS                    (MC_RGM_BASE_ADDR + 0x340)
+#define MC_RGM_DDR_HE                  (MC_RGM_BASE_ADDR + 0x350)
+#define MC_RGM_DDR_HS                  (MC_RGM_BASE_ADDR + 0x354)
+#define MC_RGM_FRHE                    (MC_RGM_BASE_ADDR + 0x358)
+#define MC_RGM_FREC                    (MC_RGM_BASE_ADDR + 0x600)
+#define MC_RGM_FRET                    (MC_RGM_BASE_ADDR + 0x607)
+#define MC_RGM_DRET                    (MC_RGM_BASE_ADDR + 0x60B)
+
+/* function reset sources mask */
+#define F_SWT4                         0x8000
+#define F_JTAG                         0x400
+#define F_FCCU_SOFT                    0x40
+#define F_FCCU_HARD                    0x20
+#define F_SOFT_FUNC                    0x8
+#define F_ST_DONE                      0x4
+#define F_EXT_RST                      0x1
+
+#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */

diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h
new file mode 100644 (file)
index 0000000..504aa68
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mmdc.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
+#define __ARCH_ARM_MACH_S32V234_MMDC_H__
+
+#define MMDC0                          0
+#define MMDC1                          1
+
+#define MMDC_MDCTL                     0x0
+#define MMDC_MDPDC                     0x4
+#define MMDC_MDOTC                     0x8
+#define MMDC_MDCFG0                    0xC
+#define MMDC_MDCFG1                    0x10
+#define MMDC_MDCFG2                    0x14
+#define MMDC_MDMISC                    0x18
+#define MMDC_MDSCR                     0x1C
+#define MMDC_MDREF                     0x20
+#define MMDC_MDRWD                     0x2C
+#define MMDC_MDOR                      0x30
+#define MMDC_MDMRR                     0x34
+#define MMDC_MDCFG3LP          0x38
+#define MMDC_MDMR4                     0x3C
+#define MMDC_MDASP                     0x40
+#define MMDC_MAARCR                    0x400
+#define MMDC_MAPSR                     0x404
+#define MMDC_MAEXIDR0          0x408
+#define MMDC_MAEXIDR1          0x40C
+#define MMDC_MADPCR0           0x410
+#define MMDC_MADPCR1           0x414
+#define MMDC_MADPSR0           0x418
+#define MMDC_MADPSR1           0x41C
+#define MMDC_MADPSR2           0x420
+#define MMDC_MADPSR3           0x424
+#define MMDC_MADPSR4           0x428
+#define MMDC_MADPSR5           0x42C
+#define MMDC_MASBS0                    0x430
+#define MMDC_MASBS1                    0x434
+#define MMDC_MAGENP                    0x440
+#define MMDC_MPZQHWCTRL                0x800
+#define MMDC_MPWLGCR           0x808
+#define MMDC_MPWLDECTRL0       0x80C
+#define MMDC_MPWLDECTRL1       0x810
+#define MMDC_MPWLDLST          0x814
+#define MMDC_MPODTCTRL         0x818
+#define MMDC_MPRDDQBY0DL       0x81C
+#define MMDC_MPRDDQBY1DL       0x820
+#define MMDC_MPRDDQBY2DL       0x824
+#define MMDC_MPRDDQBY3DL       0x828
+#define MMDC_MPDGCTRL0         0x83C
+#define MMDC_MPDGCTRL1         0x840
+#define MMDC_MPDGDLST0         0x844
+#define MMDC_MPRDDLCTL         0x848
+#define MMDC_MPRDDLST          0x84C
+#define MMDC_MPWRDLCTL         0x850
+#define MMDC_MPWRDLST          0x854
+#define MMDC_MPZQLP2CTL                0x85C
+#define MMDC_MPRDDLHWCTL       0x860
+#define MMDC_MPWRDLHWCTL       0x864
+#define MMDC_MPRDDLHWST0       0x868
+#define MMDC_MPRDDLHWST1       0x86C
+#define MMDC_MPWRDLHWST1       0x870
+#define MMDC_MPWRDLHWST2       0x874
+#define MMDC_MPWLHWERR         0x878
+#define MMDC_MPDGHWST0         0x87C
+#define MMDC_MPDGHWST1         0x880
+#define MMDC_MPDGHWST2         0x884
+#define MMDC_MPDGHWST3         0x888
+#define MMDC_MPPDCMPR1         0x88C
+#define MMDC_MPPDCMPR2         0x890
+#define MMDC_MPSWDAR0          0x894
+#define MMDC_MPSWDRDR0         0x898
+#define MMDC_MPSWDRDR1         0x89C
+#define MMDC_MPSWDRDR2         0x8A0
+#define MMDC_MPSWDRDR3         0x8A4
+#define MMDC_MPSWDRDR4         0x8A8
+#define MMDC_MPSWDRDR5         0x8AC
+#define MMDC_MPSWDRDR6         0x8B0
+#define MMDC_MPSWDRDR7         0x8B4
+#define MMDC_MPMUR0                    0x8B8
+#define MMDC_MPDCCR                    0x8C0
+
+#define MMDC_MPMUR0_FRC_MSR                    (1 << 11)
+#define MMDC_MPZQHWCTRL_ZQ_HW_FOR      (1 << 16)
+
+#endif

diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h
new file mode 100644 (file)
index 0000000..2e8c211
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/siul.h
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
+#define __ARCH_ARM_MACH_S32V234_SIUL_H__
+
+#include "ddr.h"
+
+#define SIUL2_MIDR1                            (SIUL2_BASE_ADDR + 0x00000004)
+#define SIUL2_MIDR2                            (SIUL2_BASE_ADDR + 0x00000008)
+#define SIUL2_DISR0                            (SIUL2_BASE_ADDR + 0x00000010)
+#define SIUL2_DIRER0                           (SIUL2_BASE_ADDR + 0x00000018)
+#define SIUL2_DIRSR0                           (SIUL2_BASE_ADDR + 0x00000020)
+#define SIUL2_IREER0                           (SIUL2_BASE_ADDR + 0x00000028)
+#define SIUL2_IFEER0                           (SIUL2_BASE_ADDR + 0x00000030)
+#define SIUL2_IFER0                            (SIUL2_BASE_ADDR + 0x00000038)
+
+#define SIUL2_IFMCR_BASE                       (SIUL2_BASE_ADDR + 0x00000040)
+#define SIUL2_IFMCRn(i)                                (SIUL2_IFMCR_BASE + 4 * (i))
+
+#define SIUL2_IFCPR                            (SIUL2_BASE_ADDR + 0x000000C0)
+
+/* SIUL2_MSCR specifications as stated in Reference Manual:
+ * 0 - 359 Output Multiplexed Signal Configuration Registers
+ * 512- 1023 Input Multiplexed Signal Configuration Registers */
+#define SIUL2_MSCR_BASE                                (SIUL2_BASE_ADDR + 0x00000240)
+#define SIUL2_MSCRn(i)                         (SIUL2_MSCR_BASE + 4 * (i))
+
+#define SIUL2_IMCR_BASE                                (SIUL2_BASE_ADDR + 0x00000A40)
+#define SIUL2_IMCRn(i)                         (SIUL2_IMCR_BASE +  4 * (i))
+
+#define SIUL2_GPDO_BASE                                (SIUL2_BASE_ADDR + 0x00001300)
+#define SIUL2_GPDOn(i)                         (SIUL2_GPDO_BASE + 4 * (i))
+
+#define SIUL2_GPDI_BASE                                (SIUL2_BASE_ADDR + 0x00001500)
+#define SIUL2_GPDIn(i)                         (SIUL2_GPDI_BASE + 4 * (i))
+
+#define SIUL2_PGPDO_BASE                       (SIUL2_BASE_ADDR + 0x00001700)
+#define SIUL2_PGPDOn(i)                                (SIUL2_PGPDO_BASE +  2 * (i))
+
+#define SIUL2_PGPDI_BASE                       (SIUL2_BASE_ADDR + 0x00001740)
+#define SIUL2_PGPDIn(i)                                (SIUL2_PGPDI_BASE + 2 * (i))
+
+#define SIUL2_MPGPDO_BASE                      (SIUL2_BASE_ADDR + 0x00001780)
+#define SIUL2_MPGPDOn(i)                       (SIUL2_MPGPDO_BASE + 4 * (i))
+
+/* SIUL2_MSCR masks */
+#define SIUL2_MSCR_DDR_DO_TRIM(v)      ((v) & 0xC0000000)
+#define SIUL2_MSCR_DDR_DO_TRIM_MIN     (0 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_50PS    (1 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_100PS   (2 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_150PS   (3 << 30)
+
+#define SIUL2_MSCR_DDR_INPUT(v)                ((v) & 0x20000000)
+#define SIUL2_MSCR_DDR_INPUT_CMOS      (0 << 29)
+#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR  (1 << 29)
+
+#define SIUL2_MSCR_DDR_SEL(v)          ((v) & 0x18000000)
+#define SIUL2_MSCR_DDR_SEL_DDR3                (0 << 27)
+#define SIUL2_MSCR_DDR_SEL_LPDDR2      (2 << 27)
+
+#define SIUL2_MSCR_DDR_ODT(v)          ((v) & 0x07000000)
+#define SIUL2_MSCR_DDR_ODT_120ohm      (1 << 24)
+#define SIUL2_MSCR_DDR_ODT_60ohm       (2 << 24)
+#define SIUL2_MSCR_DDR_ODT_40ohm       (3 << 24)
+#define SIUL2_MSCR_DDR_ODT_30ohm       (4 << 24)
+#define SIUL2_MSCR_DDR_ODT_24ohm       (5 << 24)
+#define SIUL2_MSCR_DDR_ODT_20ohm       (6 << 24)
+#define SIUL2_MSCR_DDR_ODT_17ohm       (7 << 24)
+
+#define SIUL2_MSCR_DCYCLE_TRIM(v)      ((v) & 0x00C00000)
+#define SIUL2_MSCR_DCYCLE_TRIM_NONE    (0 << 22)
+#define SIUL2_MSCR_DCYCLE_TRIM_LEFT    (1 << 22)
+#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT   (2 << 22)
+
+#define SIUL2_MSCR_OBE(v)              ((v) & 0x00200000)
+#define SIUL2_MSCR_OBE_EN              (1 << 21)
+
+#define SIUL2_MSCR_ODE(v)              ((v) & 0x00100000)
+#define SIUL2_MSCR_ODE_EN              (1 << 20)
+
+#define SIUL2_MSCR_IBE(v)              ((v) & 0x00010000)
+#define SIUL2_MSCR_IBE_EN              (1 << 19)
+
+#define SIUL2_MSCR_HYS(v)              ((v) & 0x00400000)
+#define SIUL2_MSCR_HYS_EN              (1 << 18)
+
+#define SIUL2_MSCR_INV(v)              ((v) & 0x00020000)
+#define SIUL2_MSCR_INV_EN              (1 << 17)
+
+#define SIUL2_MSCR_PKE(v)              ((v) & 0x00010000)
+#define SIUL2_MSCR_PKE_EN              (1 << 16)
+
+#define SIUL2_MSCR_SRE(v)              ((v) & 0x0000C000)
+#define SIUL2_MSCR_SRE_SPEED_LOW_50    (0 << 14)
+#define SIUL2_MSCR_SRE_SPEED_LOW_100   (1 << 14)
+#define SIUL2_MSCR_SRE_SPEED_HIGH_100  (2 << 14)
+#define SIUL2_MSCR_SRE_SPEED_HIGH_200  (3 << 14)
+
+#define SIUL2_MSCR_PUE(v)              ((v) & 0x00002000)
+#define SIUL2_MSCR_PUE_EN              (1 << 13)
+
+#define SIUL2_MSCR_PUS(v)              ((v) & 0x00001800)
+#define SIUL2_MSCR_PUS_100K_DOWN       (0 << 11)
+#define SIUL2_MSCR_PUS_50K_DOWN                (1 << 11)
+#define SIUL2_MSCR_PUS_100K_UP         (2 << 11)
+#define SIUL2_MSCR_PUS_33K_UP          (3 << 11)
+
+#define SIUL2_MSCR_DSE(v)              ((v) & 0x00000700)
+#define SIUL2_MSCR_DSE_240ohm          (1 << 8)
+#define SIUL2_MSCR_DSE_120ohm          (2 << 8)
+#define SIUL2_MSCR_DSE_80ohm           (3 << 8)
+#define SIUL2_MSCR_DSE_60ohm           (4 << 8)
+#define SIUL2_MSCR_DSE_48ohm           (5 << 8)
+#define SIUL2_MSCR_DSE_40ohm           (6 << 8)
+#define SIUL2_MSCR_DSE_34ohm           (7 << 8)
+
+#define SIUL2_MSCR_CRPOINT_TRIM(v)     ((v) & 0x000000C0)
+#define SIUL2_MSCR_CRPOINT_TRIM_1      (1 << 6)
+
+#define SIUL2_MSCR_SMC(v)              ((v) & 0x00000020)
+#define SIUL2_MSCR_MUX_MODE(v)         ((v) & 0x0000000f)
+#define SIUL2_MSCR_MUX_MODE_ALT1       (0x1)
+#define SIUL2_MSCR_MUX_MODE_ALT2       (0x2)
+#define SIUL2_MSCR_MUX_MODE_ALT3       (0x3)
+
+/* UART settings */
+#define SIUL2_UART0_TXD_PAD    12
+#define SIUL2_UART_TXD         (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm |    \
+                               SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
+
+#define SIUL2_UART0_MSCR_RXD_PAD       11
+#define SIUL2_UART0_IMCR_RXD_PAD       200
+
+#define SIUL2_UART_MSCR_RXD    (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
+#define SIUL2_UART_IMCR_RXD    (SIUL2_MSCR_MUX_MODE_ALT2)
+
+/* uSDHC settings */
+#define SIUL2_USDHC_PAD_CTRL_BASE      (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN |    \
+                                               SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN |          \
+                                               SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
+#define SIUL2_USDHC_PAD_CTRL_CMD       (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
+#define SIUL2_USDHC_PAD_CTRL_CLK       (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
+#define SIUL2_USDHC_PAD_CTRL_DAT0_3    (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
+#define SIUL2_USDHC_PAD_CTRL_DAT4_7    (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
+
+#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index f2990db9289f5e06cf19396847c5486f6a054a4d..c2e72f5a86b2595609d856d75a2ce18a1a87021a 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -222,7 +222,12 @@ struct sunxi_ccm_reg {
 #define CCM_PLL11_CTRL_UPD             (0x1 << 30)
 #define CCM_PLL11_CTRL_EN              (0x1 << 31)
 
+#if defined(CONFIG_MACH_SUN50I)
+/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
+#define AHB1_ABP1_DIV_DEFAULT          0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
+#else
 #define AHB1_ABP1_DIV_DEFAULT          0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#endif
 
 #define AXI_GATE_OFFSET_DRAM           0
 

diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 386c2dc42b9f300ba9a4aac4bc2987e59ca7394e..32f95b33c228fcde617f85366b4f16350c893534 100644 (file)
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -24,7 +24,15 @@
 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
 #define is_soc_type(soc) (get_soc_type() == soc)
 
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 73a9c74512a21a8fcfc261faefd81c9e366e42ed..6180699fed9593e279ee03546c1d46cce26e86bd 100644 (file)
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -23,6 +23,14 @@ config TARGET_SNAPPER9260
        select DM_SERIAL
        select DM_GPIO
 
+config TARGET_GURNARD
+       bool "Support gurnard"
+       select CPU_ARM926EJS
+       select DM
+       select DM_SERIAL
+       select DM_GPIO
+       select DM_ETH
+
 config TARGET_AT91SAM9261EK
        bool "Atmel at91sam9261 reference board"
        select CPU_ARM926EJS
@@ -149,6 +157,7 @@ source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
 source "board/atmel/sama5d4_xplained/Kconfig"
 source "board/atmel/sama5d4ek/Kconfig"
+source "board/bluewater/gurnard/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
 source "board/denx/ma5d4evk/Kconfig"

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d2abf310a59989c51362585fff3d83a6bc007d4e..a908004b0a4a9c1f031619af3e54d4d40e2f3e7f 100644 (file)
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,8 +10,8 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
-obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
+obj-$(CONFIG_SAMA5D3) += bootparams_atmel.o mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
 endif
 

diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
index 0d83426ead11708b6f9c9516a00ae3f4957cf727..eddfdb0853662b3392432ccf0ce68cc4f074f08c 100644 (file)
--- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
@@ -165,3 +166,20 @@ void at91_mci_hw_init(void)
        at91_periph_clk_enable(ATMEL_ID_MCI0);
 }
 #endif
+
+/* Platform data for the GPIOs */
+static const struct at91_port_platdata at91sam9260_plat[] = {
+       { ATMEL_BASE_PIOA, "PA" },
+       { ATMEL_BASE_PIOB, "PB" },
+       { ATMEL_BASE_PIOC, "PC" },
+       { ATMEL_BASE_PIOD, "PD" },
+       { ATMEL_BASE_PIOE, "PE" },
+};
+
+U_BOOT_DEVICES(at91sam9260_gpios) = {
+       { "gpio_at91", &at91sam9260_plat[0] },
+       { "gpio_at91", &at91sam9260_plat[1] },
+       { "gpio_at91", &at91sam9260_plat[2] },
+       { "gpio_at91", &at91sam9260_plat[3] },
+       { "gpio_at91", &at91sam9260_plat[4] },
+};

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 7684f09afcbb8fa649031077c702204855e5c61f..680ceb03145d6f8f0217d4ee52997f3dfd65b66c 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -67,18 +67,18 @@ typedef struct at91_pmc {
 #define AT91_PMC_MOR_MOSCEN            0x01
 #define AT91_PMC_MOR_OSCBYPASS         0x02
 #define AT91_PMC_MOR_MOSCRCEN          0x08
-#define AT91_PMC_MOR_OSCOUNT(x)                ((x & 0xff) << 8)
-#define AT91_PMC_MOR_KEY(x)            ((x & 0xff) << 16)
+#define AT91_PMC_MOR_OSCOUNT(x)                (((x) & 0xff) << 8)
+#define AT91_PMC_MOR_KEY(x)            (((x) & 0xff) << 16)
 #define AT91_PMC_MOR_MOSCSEL           (1 << 24)
 
-#define AT91_PMC_PLLXR_DIV(x)          (x & 0xFF)
-#define AT91_PMC_PLLXR_PLLCOUNT(x)     ((x & 0x3F) << 8)
-#define AT91_PMC_PLLXR_OUT(x)          ((x & 0x03) << 14)
+#define AT91_PMC_PLLXR_DIV(x)          ((x) & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x)     (((x) & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x)          (((x) & 0x03) << 14)
 #if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
        defined(CONFIG_SAMA5D4)
-#define AT91_PMC_PLLXR_MUL(x)          ((x & 0x7F) << 18)
+#define AT91_PMC_PLLXR_MUL(x)          (((x) & 0x7F) << 18)
 #else
-#define AT91_PMC_PLLXR_MUL(x)          ((x & 0x7FF) << 16)
+#define AT91_PMC_PLLXR_MUL(x)          (((x) & 0x7FF) << 16)
 #endif
 #define AT91_PMC_PLLAR_29              0x20000000
 #define AT91_PMC_PLLBR_USBDIV_1                0x00000000
@@ -158,7 +158,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_PCR_CMD_WRITE         (0x1 << 12)
 #define AT91_PMC_PCR_DIV               (0x3 << 16)
 #define AT91_PMC_PCR_GCKDIV            (0xff << 20)
-#define                AT91_PMC_PCR_GCKDIV_(x)         ((x & 0xff) << 20)
+#define                AT91_PMC_PCR_GCKDIV_(x)         (((x) & 0xff) << 20)
 #define                AT91_PMC_PCR_GCKDIV_OFFSET      20
 #define AT91_PMC_PCR_EN                        (0x1 << 28)
 #define AT91_PMC_PCR_GCKEN             (0x1 << 29)

diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
new file mode 100644 (file)
index 0000000..73070e3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Real Time Clock (RTC) - System peripheral registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef AT91_RTC_H
+#define AT91_RTC_H
+
+/* Control Register */
+#define AT91_RTC_CR            (ATMEL_BASE_RTC + 0x00)
+#define AT91_RTC_UPDTIM                (1 <<  0)       /* Update Request Time */
+#define AT91_RTC_UPDCAL                (1 <<  1)       /* Update Request Calendar */
+#define AT91_RTC_TIMEVSEL      (3 <<  8)       /* Time Event Selection */
+#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
+#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
+#define AT91_RTC_TIMEVSEL_DAY24        (2 << 8)
+#define AT91_RTC_TIMEVSEL_DAY12        (3 << 8)
+#define AT91_RTC_CALEVSEL      (3 << 16)       /* Calendar Event Selection */
+#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
+#define AT91_RTC_CALEVSEL_MONTH        (1 << 16)
+#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
+
+#define AT91_RTC_MR            (ATMEL_BASE_RTC + 0x04) /* Mode Register */
+#define AT91_RTC_HRMOD         (1 <<  0)               /* 12/24 Hour Mode */
+
+#define AT91_RTC_TIMR          (ATMEL_BASE_RTC + 0x08) /* Time Register */
+#define AT91_RTC_SEC           (0x7f <<  0)            /* Current Second */
+#define AT91_RTC_MIN           (0x7f <<  8)            /* Current Minute */
+#define AT91_RTC_HOUR          (0x3f << 16)            /* Current Hour */
+#define AT91_RTC_AMPM          (1    << 22)            /* AM/PM */
+
+#define AT91_RTC_CALR          (ATMEL_BASE_RTC + 0x0c) /* Calendar Register */
+#define AT91_RTC_CENT          (0x7f <<  0)            /* Current Century */
+#define AT91_RTC_YEAR          (0xff <<  8)            /* Current Year */
+#define AT91_RTC_MONTH         (0x1f << 16)            /* Current Month */
+#define AT91_RTC_DAY           (7    << 21)            /* Current Day */
+#define AT91_RTC_DATE          (0x3f << 24)            /* Current Date */
+
+#define AT91_RTC_TIMALR                (ATMEL_BASE_RTC + 0x10) /* Time Alarm */
+#define AT91_RTC_SECEN         (1 <<  7)               /* Second Alarm Enab */
+#define AT91_RTC_MINEN         (1 << 15)               /* Minute Alarm Enab */
+#define AT91_RTC_HOUREN                (1 << 23)               /* Hour Alarm Enable */
+
+#define AT91_RTC_CALALR                (ATMEL_BASE_RTC + 0x14) /* Calendar Alarm */
+#define AT91_RTC_MTHEN         (1 << 23)               /* Month Alarm Enable */
+#define AT91_RTC_DATEEN                (1 << 31)               /* Date Alarm Enable */
+
+#define AT91_RTC_SR            (ATMEL_BASE_RTC + 0x18) /* Status Register */
+#define AT91_RTC_ACKUPD                (1 <<  0)               /* Ack for Update */
+#define AT91_RTC_ALARM         (1 <<  1)               /* Alarm Flag */
+#define AT91_RTC_SECEV         (1 <<  2)               /* Second Event */
+#define AT91_RTC_TIMEV         (1 <<  3)               /* Time Event */
+#define AT91_RTC_CALEV         (1 <<  4)               /* Calendar Event */
+
+#define AT91_RTC_SCCR          (ATMEL_BASE_RTC + 0x1c) /* Status Clear Cmd */
+#define AT91_RTC_IER           (ATMEL_BASE_RTC + 0x20) /* Interrupt Enable */
+#define AT91_RTC_IDR           (ATMEL_BASE_RTC + 0x24) /* Interrupt Disable */
+#define AT91_RTC_IMR           (ATMEL_BASE_RTC + 0x28) /* Interrupt Mask */
+
+#define AT91_RTC_VER           (ATMEL_BASE_RTC + 0x2c) /* Valid Entry */
+#define AT91_RTC_NVTIM         (1 <<  0)               /* Non-valid Time */
+#define AT91_RTC_NVCAL         (1 <<  1)               /* Non-valid Calendar */
+#define AT91_RTC_NVTIMALR      (1 <<  2)               /* .. Time Alarm */
+#define AT91_RTC_NVCALALR      (1 <<  3)               /* .. Calendar Alarm */
+
+#endif

diff --git a/arch/arm/mach-at91/include/mach/at91_sck.h b/arch/arm/mach-at91/include/mach/at91_sck.h
new file mode 100644 (file)
index 0000000..ce8e577
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_sck.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef AT91_SCK_H
+#define AT91_SCK_H
+
+/*
+ * SCKCR flags
+ */
+#define AT91SAM9G45_SCKCR_RCEN     (1 << 0)    /* RC Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32EN   (1 << 1)   /* 32kHz Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32BYP  (1 << 2)   /* 32kHz Oscillator Bypass */
+#define AT91SAM9G45_SCKCR_OSCSEL    (1 << 3)   /* Slow Clock Selector */
+#define                AT91SAM9G45_SCKCR_OSCSEL_RC     (0 << 3)
+#define                AT91SAM9G45_SCKCR_OSCSEL_32     (1 << 3)
+
+#endif

diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index cf1c73f3d986219e3aa3fb3a212299fc0928a750..5c32e24ed0f24559f2cf66124752053b25fc1351 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -109,6 +109,7 @@
 #define ATMEL_BASE_RTT         0xfffffd20
 #define ATMEL_BASE_PIT         0xfffffd30
 #define ATMEL_BASE_WDT         0xfffffd40
+#define ATMEL_BASE_SCKCR       0xfffffd50
 #define ATMEL_BASE_GPBR                0xfffffd60
 #define ATMEL_BASE_RTC         0xfffffdb0
 /* Reserved:   0xfffffdc0 - 0xffffffff */

diff --git a/arch/arm/mach-at91/include/mach/sama5_boot.h b/arch/arm/mach-at91/include/mach/sama5_boot.h
new file mode 100644 (file)
index 0000000..8911a44
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5_boot.h
@@ -0,0 +1,25 @@
+/*
+ * Boot mode definitions for the SAMA5Dx SoC
+ *
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __SAMA5_BOOT_H
+#define __SAMA5_BOOT_H
+
+/* Boot modes stored by BootROM in r4 */
+#define ATMEL_SAMA5_BOOT_FROM_OFF      0
+#define ATMEL_SAMA5_BOOT_FROM_MASK     0xf
+#define ATMEL_SAMA5_BOOT_FROM_SPI      (0 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_MCI      (1 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_SMC      (2 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_TWI      (3 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_QSPI     (4 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_SAMBA    (7 << 0)
+
+#define ATMEL_SAMA5_BOOT_DEV_ID_OFF    4
+#define ATMEL_SAMA5_BOOT_DEV_ID_MASK   0xf
+
+#endif /* __SAMA5_BOOT_H */

diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index ee841da971a527d90915783db969a7b3ee49e2ef..25c85411e5a1e3c7ce3ee9dc6def14d3b1358f9e 100644 (file)
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -230,18 +230,6 @@
 /* No PMECC Galois table in ROM */
 #define NO_GALOIS_TABLE_IN_ROM
 
-/* Boot modes stored by BootROM in r4 */
-#define ATMEL_SAMA5D2_BOOT_FROM_OFF    0
-#define ATMEL_SAMA5D2_BOOT_FROM_MASK   0xf
-#define ATMEL_SAMA5D2_BOOT_FROM_SPI    (0 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_MCI    (1 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_SMC    (2 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_TWI    (3 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_QSPI   (4 << 0)
-
-#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF  4
-#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK 0xf
-
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
 unsigned int get_extension_chip_id(void);

diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index c4ed224d03dffa9ef0f19172cba33ca6fea9e496..f255b59195e6da69e704192d65308143fd637b2b 100644 (file)
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -23,20 +23,22 @@ void at91_disable_wdt(void)
 }
 #endif
 
-#if defined(CONFIG_SAMA5D2)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+    defined(CONFIG_SAMA5D4)
+#include <asm/arch/sama5_boot.h>
 struct {
        u32     r4;
 } bootrom_stash __attribute__((section(".data")));
 
 u32 spl_boot_device(void)
 {
-       u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) &
-                 ATMEL_SAMA5D2_BOOT_FROM_MASK;
-       u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) &
-                 ATMEL_SAMA5D2_BOOT_DEV_ID_MASK;
+       u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5_BOOT_FROM_OFF) &
+                 ATMEL_SAMA5_BOOT_FROM_MASK;
+       u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5_BOOT_DEV_ID_OFF) &
+                 ATMEL_SAMA5_BOOT_DEV_ID_MASK;
 
 #if defined(CONFIG_SYS_USE_MMC)
-       if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) {
+       if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) {
                if (off == 0)
                        return BOOT_DEVICE_MMC1;
                if (off == 1)
@@ -47,10 +49,13 @@ u32 spl_boot_device(void)
 #endif
 
 #if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
-       if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI)
+       if (dev == ATMEL_SAMA5_BOOT_FROM_SPI)
                return BOOT_DEVICE_SPI;
 #endif
 
+       if (dev == ATMEL_SAMA5_BOOT_FROM_SAMBA)
+               return BOOT_DEVICE_USB;
+
        printf("ERROR: SMC/TWI/QSPI boot device not supported!\n"
               "       Boot device %i, controller number %i\n", dev, off);
 

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5c30ae981dfdd871817316637862da326ef38fbc..21066f0fda69c1649cf981b52e2ae53c13a982d1 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -253,7 +253,7 @@ config SYS_DCACHE_SIZE
          The total size of the L1 Dcache, if known at compile time.
 
 config SYS_DCACHE_LINE_SIZE
-       hex
+       int
        default 0
        help
          The size of L1 Dcache lines, if known at compile time.

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 5f520c069f6205ea977ea96c383933455ea0dc89..db81953f86c5486bd1730fed99ac72a5b52f7401 100644 (file)
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        if (start_addr == stop)
                return;
 
-       cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+       cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 }

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index e522ff3b7f651cb8f8dcbc7d02983b255674dad3..269043dedc13c976fd77f2fb9e6ee0cbbe9f1687 100644 (file)
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -24,6 +24,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <syscon.h>
 #include <asm/control_regs.h>
 #include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
@@ -751,6 +752,10 @@ int cpu_init_r(void)
        uclass_first_device(UCLASS_PCH, &dev);
        uclass_first_device(UCLASS_LPC, &dev);
 
+       /* Set up pin control if available */
+       ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+       debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
        return 0;
 }
 

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4a50d8665e59cce41509450fd38a7b6660ef18be..c8907ce44bcdcf7296db77ac7eb021441bf8997d 100644 (file)
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,6 +65,26 @@
                };
        };
 
+       pch_pinctrl {
+               compatible = "intel,x86-pinctrl";
+               reg = <0 0>;
+
+               /*
+                * As of today, the latest version FSP (gold4) for BayTrail
+                * misses the PAD configuration of the SD controller's Card
+                * Detect signal. The default PAD value for the CD pin sets
+                * the pin to work in GPIO mode, which causes card detect
+                * status cannot be reflected by the Present State register
+                * in the SD controller (bit 16 & bit 18 are always zero).
+                *
+                * Configure this pin to function 1 (SD controller).
+                */
+               sdmmc3_cd@0 {
+                       pad-offset = <0x3a0>;
+                       mode-func = <1>;
+               };
+       };
+
        pci {
                compatible = "pci-x86";
                #address-cells = <3>;
@@ -213,7 +233,7 @@
                fsp,mrc-init-mmio-size = <0x800>;
                fsp,mrc-init-spd-addr1 = <0xa0>;
                fsp,mrc-init-spd-addr2 = <0xa2>;
-               fsp,emmc-boot-mode = <2>;
+               fsp,emmc-boot-mode = <1>;
                fsp,enable-sdio;
                fsp,enable-sdcard;
                fsp,enable-hsuart1;

diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 1a4ecaad0e917d2ac3ec038f227a6cf282128e4a..fba089d6668a98eabdb02565b498860168850a12 100644 (file)
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -30,6 +30,22 @@
 
        pch_pinctrl {
                compatible = "intel,x86-pinctrl";
+               reg = <0 0>;
+
+               /*
+                * As of today, the latest version FSP (gold4) for BayTrail
+                * misses the PAD configuration of the SD controller's Card
+                * Detect signal. The default PAD value for the CD pin sets
+                * the pin to work in GPIO mode, which causes card detect
+                * status cannot be reflected by the Present State register
+                * in the SD controller (bit 16 & bit 18 are always zero).
+                *
+                * Configure this pin to function 1 (SD controller).
+                */
+               sdmmc3_cd@0 {
+                       pad-offset = <0x3a0>;
+                       mode-func = <1>;
+               };
        };
 
        chosen {
@@ -217,7 +233,7 @@
                fsp,mrc-init-mmio-size = <0x800>;
                fsp,mrc-init-spd-addr1 = <0xa0>;
                fsp,mrc-init-spd-addr2 = <0xa2>;
-               fsp,emmc-boot-mode = <2>;
+               fsp,emmc-boot-mode = <1>;
                fsp,enable-sdio;
                fsp,enable-sdcard;
                fsp,enable-hsuart1;

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 936455b5e55ada3aff85dfd0b61dbf6ebd4fe3b9..1a8a8cc7f1bb6c355922530fb81ddf88d6ea10b3 100644 (file)
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -29,6 +29,7 @@
 
        pch_pinctrl {
                compatible = "intel,x86-pinctrl";
+               reg = <0 0>;
 
                /* GPIO E0 */
                soc_gpio_s5_0@0 {
@@ -72,6 +73,21 @@
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;
                };
+
+               /*
+                * As of today, the latest version FSP (gold4) for BayTrail
+                * misses the PAD configuration of the SD controller's Card
+                * Detect signal. The default PAD value for the CD pin sets
+                * the pin to work in GPIO mode, which causes card detect
+                * status cannot be reflected by the Present State register
+                * in the SD controller (bit 16 & bit 18 are always zero).
+                *
+                * Configure this pin to function 1 (SD controller).
+                */
+               sdmmc3_cd@0 {
+                       pad-offset = <0x3a0>;
+                       mode-func = <1>;
+               };
        };
 
        chosen {
@@ -246,7 +262,7 @@
                fsp,mrc-init-mmio-size = <0x800>;
                fsp,mrc-init-spd-addr1 = <0xa0>;
                fsp,mrc-init-spd-addr2 = <0xa2>;
-               fsp,emmc-boot-mode = <2>;
+               fsp,emmc-boot-mode = <1>;
                fsp,enable-sdio;
                fsp,enable-sdcard;
                fsp,enable-hsuart1;

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index ffb4678e510b38e9249db3209bf0dd8666155613..bb71286dba88a80325e3d5a06fff540a36a3d7c9 100644 (file)
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -183,20 +183,20 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
 int acpi_create_madt_lapics(u32 current)
 {
        struct udevice *dev;
-       int length = 0;
+       int total_length = 0;
 
        for (uclass_find_first_device(UCLASS_CPU, &dev);
             dev;
             uclass_find_next_device(&dev)) {
                struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
-               length += acpi_create_madt_lapic(
-                       (struct acpi_madt_lapic *)current,
-                       plat->cpu_id, plat->cpu_id);
+               int length = acpi_create_madt_lapic(
+                               (struct acpi_madt_lapic *)current,
+                               plat->cpu_id, plat->cpu_id);
                current += length;
+               total_length += length;
        }
 
-       return length;
+       return total_length;
 }
 
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,

diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig
new file mode 100644 (file)
index 0000000..e2cd9f0
--- /dev/null
+++ b/board/bluewater/gurnard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GURNARD
+
+config SYS_BOARD
+       default "gurnard"
+
+config SYS_VENDOR
+       default "bluewater"
+
+config SYS_CONFIG_NAME
+       default "snapper9g45"
+
+endif

diff --git a/board/bluewater/gurnard/MAINTAINERS b/board/bluewater/gurnard/MAINTAINERS
new file mode 100644 (file)
index 0000000..5e546d4
--- /dev/null
+++ b/board/bluewater/gurnard/MAINTAINERS
@@ -0,0 +1,6 @@
+GURNARD BOARD
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     board/bluewater/gurnard/
+F:     include/configs/snapper9g45.h
+F:     configs/gurnard_defconfig

diff --git a/board/bluewater/gurnard/Makefile b/board/bluewater/gurnard/Makefile
new file mode 100644 (file)
index 0000000..f646d35
--- /dev/null
+++ b/board/bluewater/gurnard/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += gurnard.o

diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
new file mode 100644 (file)
index 0000000..2a36d29
--- /dev/null
+++ b/board/bluewater/gurnard/gurnard.c
@@ -0,0 +1,449 @@
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#include <dm.h>
+#include <lcd.h>
+#include <net.h>
+#ifndef CONFIG_DM_ETH
+#include <netdev.h>
+#endif
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_emac.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_rtc.h>
+#include <asm/arch/at91_sck.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <dm/uclass-internal.h>
+
+#ifdef CONFIG_GURNARD_SPLASH
+#include "splash_logo.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET       (0 << 1)
+#define IO_EXP_ETH_POWER       (1 << 1)
+
+#ifdef CONFIG_MACB
+static void gurnard_macb_hw_init(void)
+{
+       struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+       at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+       /*
+        * Enable pull-up on:
+        *      RXDV (PA12) => MODE0 - PHY also has pull-up
+        *      ERX0 (PA13) => MODE1 - PHY also has pull-up
+        *      ERX1 (PA15) => MODE2 - PHY also has pull-up
+        */
+       writel(pin_to_mask(AT91_PIN_PA15) |
+              pin_to_mask(AT91_PIN_PA12) |
+              pin_to_mask(AT91_PIN_PA13),
+              &pioa->puer);
+
+       at91_phy_reset();
+
+       at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static int gurnard_nand_hw_init(void)
+{
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       ulong flags;
+       int ret;
+
+       /* Enable CS3 as NAND/SmartMedia */
+       setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+       /* Configure SMC CS3 for NAND/SmartMedia */
+       writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+              AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+              &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+              AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+              &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+              &smc->cs[3].cycle);
+#ifdef CONFIG_SYS_NAND_DBW_16
+       flags = AT91_SMC_MODE_DBW_16;
+#else
+       flags = AT91_SMC_MODE_DBW_8;
+#endif
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+              AT91_SMC_MODE_EXNW_DISABLE |
+              flags |
+              AT91_SMC_MODE_TDF_CYCLE(3),
+              &smc->cs[3].mode);
+
+       ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+       if (ret)
+               return ret;
+       gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+       /* Enable NandFlash */
+       ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+       if (ret)
+               return ret;
+       gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_GURNARD_SPLASH
+static void lcd_splash(int width, int height)
+{
+       u16 colour;
+       int x, y;
+       u16 *base_addr = (u16 *)gd->video_bottom;
+
+       memset(base_addr, 0xff, width * height * 2);
+       /*
+        * Blit the logo to the center of the screen
+        */
+       for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
+               for (x = 0; x < BMP_LOGO_WIDTH; x++) {
+                       int posx, posy;
+                       colour = bmp_logo_palette[bmp_logo_bitmap[
+                           y * BMP_LOGO_WIDTH + x]];
+                       posx = x + (width - BMP_LOGO_WIDTH) / 2;
+                       posy = y;
+                       base_addr[posy * width + posx] = colour;
+               }
+       }
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static void at91sam9g45_lcd_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
+       at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
+       at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
+       at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
+       at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
+
+       at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
+       at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
+       at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
+       at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
+       at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
+       at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
+       at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
+       at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
+       at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
+       at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
+       at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
+       at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
+       at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
+       at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
+       at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
+       at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
+       at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
+       at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
+       at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
+       at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
+       at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
+       at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
+       at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
+       at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
+
+       at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+/**
+ * Initialise the memory bus settings so that we can talk to the
+ * memory mapped FPGA
+ */
+static int fpga_hw_init(void)
+{
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       int i;
+
+       setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
+
+       at91_set_a_periph(2, 4, 0); /* EBIA21 */
+       at91_set_a_periph(2, 5, 0); /* EBIA22 */
+       at91_set_a_periph(2, 6, 0); /* EBIA23 */
+       at91_set_a_periph(2, 7, 0); /* EBIA24 */
+       at91_set_a_periph(2, 12, 0); /* EBIA25 */
+       for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
+               at91_set_a_periph(2, i, 0);
+
+       /* configure SMC cs0 for FPGA access timing */
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
+              AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
+              &smc->cs[0].setup);
+       writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
+              AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
+              &smc->cs[0].pulse);
+       writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+              &smc->cs[0].cycle);
+       writel(AT91_SMC_MODE_BAT |
+              AT91_SMC_MODE_EXNW_DISABLE |
+              AT91_SMC_MODE_DBW_32 |
+              AT91_SMC_MODE_TDF |
+              AT91_SMC_MODE_TDF_CYCLE(2),
+              &smc->cs[0].mode);
+
+       /* Do a write to within EBI_CS1 to enable the SDCK */
+       writel(0, ATMEL_BASE_CS1);
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+
+#define USB0_ENABLE_PIN                AT91_PIN_PB22
+#define USB1_ENABLE_PIN                AT91_PIN_PB23
+
+void gurnard_usb_init(void)
+{
+       at91_set_gpio_output(USB0_ENABLE_PIN, 1);
+       at91_set_gpio_value(USB0_ENABLE_PIN, 0);
+       at91_set_gpio_output(USB1_ENABLE_PIN, 1);
+       at91_set_gpio_value(USB1_ENABLE_PIN, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int cpu_mmc_init(bd_t *bis)
+{
+       return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+static void gurnard_enable_console(int enable)
+{
+       at91_set_gpio_output(AT91_PIN_PB14, 1);
+       at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
+}
+
+void at91sam9g45_slowclock_init(void)
+{
+       /*
+        * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
+        * internal impreciseRC oscillator or an external 32kHz oscillator.
+        * Switch to the latter.
+        */
+       unsigned i, tmp;
+       ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
+
+       tmp = readl(reg);
+       if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
+               timer_init();
+               tmp |= AT91SAM9G45_SCKCR_OSC32EN;
+               writel(tmp, reg);
+               for (i = 0; i < 1200; i++)
+                       udelay(1000);
+               tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
+               writel(tmp, reg);
+               udelay(200);
+               tmp &= ~AT91SAM9G45_SCKCR_RCEN;
+               writel(tmp, reg);
+       }
+}
+
+int board_early_init_f(void)
+{
+       at91_seriald_hw_init();
+       gurnard_enable_console(1);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       const char *rev_str;
+#ifdef CONFIG_CMD_NAND
+       int ret;
+#endif
+
+       at91_periph_clk_enable(ATMEL_ID_PIOA);
+       at91_periph_clk_enable(ATMEL_ID_PIOB);
+       at91_periph_clk_enable(ATMEL_ID_PIOC);
+       at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+       at91sam9g45_slowclock_init();
+
+       /*
+        * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
+        * boots with spurious IRQs.
+        */
+       writel(0xffffffff, AT91_RTC_IDR);
+
+       /* Make sure that the reset signal is attached properly */
+       setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
+
+       gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+       /* Address of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+       ret = gurnard_nand_hw_init();
+       if (ret)
+               return ret;
+#endif
+#ifdef CONFIG_ATMEL_SPI
+       at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+       gurnard_macb_hw_init();
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+       fpga_hw_init();
+#endif
+
+#ifdef CONFIG_CMD_USB
+       gurnard_usb_init();
+#endif
+
+#ifdef CONFIG_CMD_MMC
+       at91_set_A_periph(AT91_PIN_PA12, 0);
+       at91_set_gpio_output(AT91_PIN_PA8, 1);
+       at91_set_gpio_value(AT91_PIN_PA8, 0);
+       at91_mci_hw_init();
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+       at91sam9g45_lcd_hw_init();
+       at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
+
+       /* Select the second timing index for board rev 2 */
+       rev_str = getenv("board_rev");
+       if (rev_str && !strncmp(rev_str, "2", 1)) {
+               struct udevice *dev;
+
+               uclass_find_first_device(UCLASS_VIDEO, &dev);
+               if (dev) {
+                       struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+
+                       plat->timing_index = 1;
+               }
+       }
+#endif
+
+       return 0;
+}
+
+int board_late_init(void)
+{
+       u_int8_t env_enetaddr[8];
+       char *env_str;
+       char *end;
+       int i;
+
+       /*
+        * Set MAC address so we do not need to init Ethernet before Linux
+        * boot
+        */
+       env_str = getenv("ethaddr");
+       if (env_str) {
+               struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
+               /* Parse MAC address */
+               for (i = 0; i < 6; i++) {
+                       env_enetaddr[i] = env_str ?
+                               simple_strtoul(env_str, &end, 16) : 0;
+                       if (env_str)
+                               env_str = (*end) ? end+1 : end;
+               }
+
+               /* Set hardware address */
+               writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
+                      env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
+                      &emac->sa2l);
+               writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
+
+               printf("MAC:   %s\n", getenv("ethaddr"));
+       } else {
+               /* Not set in environment */
+               printf("MAC:   not set\n");
+       }
+#ifdef CONFIG_GURNARD_SPLASH
+       lcd_splash(480, 272);
+#endif
+
+       return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(bd_t *bis)
+{
+       return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
+}
+#endif
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
+       return 0;
+}
+
+void reset_phy(void)
+{
+}
+
+/* This breaks the Ethernet MAC at present */
+void enable_caches(void)
+{
+       dcache_enable();
+}
+
+/* SPI chip select control - only used for FPGA programming */
+#ifdef CONFIG_ATMEL_SPI
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       /* We don't use chipselects for FPGA programming */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       /* We don't use chipselects for FPGA programming */
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+       .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+       .name   = "serial_atmel",
+       .platdata = &at91sam9260_serial_plat,
+};

diff --git a/board/bluewater/gurnard/splash_logo.h b/board/bluewater/gurnard/splash_logo.h
new file mode 100644 (file)
index 0000000..fb87dea
--- /dev/null
+++ b/board/bluewater/gurnard/splash_logo.h
@@ -0,0 +1,2619 @@
+/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/
+#ifndef __BMP_LOGO_H__
+#define __BMP_LOGO_H__
+#define BMP_LOGO_WIDTH 187
+#define BMP_LOGO_HEIGHT 139
+#define BMP_LOGO_COLORS 255
+#define BMP_LOGO_OFFSET 50
+
+unsigned short bmp_logo_palette[] = {
+       0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e,
+       0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7,
+       0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf,
+       0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d,
+       0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410,
+       0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe,
+       0xffff, 0xef3c, };
+
+unsigned char bmp_logo_bitmap[] = {
+       0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
+       0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0006, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0001, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+       0x0008, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0009, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0009, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0009, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
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+       0x0026, 0x0026, 0x0026, 0x0025, 0x002d, 0x0022, 0x0024, 0x0023, 0x0027, 0x0029,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0027, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0006, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0004, 0x0025, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0027, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0006, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0004, 0x0025, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0027, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0006, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0004, 0x0025,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026, 0x0026,
+       0x0026, 0x0026, 0x0026, 0x0026, 0x0027, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+       0x0003, 0x0003, 0x0006, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+       0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0004, 0x0023, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+       0x002d, 0x0022, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x001f,
+       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
+       0x000e, 0x000e, 0x0009, };
+#endif

diff --git a/board/broadcom/bcm23550_w1d/Kconfig b/board/broadcom/bcm23550_w1d/Kconfig
new file mode 100644 (file)
index 0000000..007a127
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCM23550_W1D
+
+config SYS_BOARD
+       default "bcm23550_w1d"
+
+config SYS_VENDOR
+       default "broadcom"
+
+config SYS_SOC
+       default "bcm235xx"
+
+config SYS_CONFIG_NAME
+       default "bcm23550_w1d"
+
+endif

diff --git a/board/broadcom/bcm23550_w1d/MAINTAINERS b/board/broadcom/bcm23550_w1d/MAINTAINERS
new file mode 100644 (file)
index 0000000..fdaa539
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM23550_W1D BOARD
+M:     Steve Rae <srae@broadcom.com>
+S:     Maintained
+F:     board/broadcom/bcm23550_w1d/
+F:     include/configs/bcm23550_w1d.h
+F:     configs/bcm23550_w1d_defconfig

diff --git a/board/broadcom/bcm23550_w1d/Makefile b/board/broadcom/bcm23550_w1d/Makefile
new file mode 100644 (file)
index 0000000..76bd032
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += bcm23550_w1d.o

diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
new file mode 100644 (file)
index 0000000..0cb059f
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <g_dnl.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET      0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT    27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT        26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT  20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT    0
+
+#ifndef CONFIG_USB_SERIALNO
+#define CONFIG_USB_SERIALNO "1234567890"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+       printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+       clk_init();
+
+       return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+       return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
+       return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+       int ret = 0;
+
+       /* Register eMMC - SDIO2 */
+       ret = kona_sdhci_init(1, 400000, 0);
+       if (ret)
+               return ret;
+
+       /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+       ret = kona_sdhci_init(3, 400000, 0);
+       return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+static struct dwc2_plat_otg_data bcm_otg_data = {
+       .regs_otg       = HSOTG_BASE_ADDR
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+       debug("%s: performing dwc2_udc_probe\n", __func__);
+       return dwc2_udc_probe(&bcm_otg_data);
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+       debug("%s\n", __func__);
+       if (!getenv("serial#"))
+               g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
+       return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+       debug("%s\n", __func__);
+       return 1;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+       debug("%s\n", __func__);
+       return 0;
+}
+#endif

diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 33ad7dcf3e08d179832ba3cb200d469e037a5186..95ff68b3649f188f0749498596935ba44ea98941 100644 (file)
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -20,6 +20,7 @@
 
 #include "ls2080aqds_qixis.h"
 
+#define MC_BOOT_ENV_VAR "mcinitcmd"
 
 #ifdef CONFIG_FSL_MC_ENET
  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
@@ -714,6 +715,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 int board_eth_init(bd_t *bis)
 {
        int error;
+       char *mc_boot_env_var;
 #ifdef CONFIG_FSL_MC_ENET
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
        int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -781,6 +783,9 @@ int board_eth_init(bd_t *bis)
                }
        }
 
+       mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+       if (mc_boot_env_var)
+               run_command_list(mc_boot_env_var, -1, 0);
        error = cpu_eth_init(bis);
 
        if (hwconfig_f("xqsgmii", env_hwconfig)) {

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 897793d85b7db6dac3348e2e87245e6323010629..477f55646f93bd1e646a418ce3e9f4a260ad0e73 100644 (file)
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC       0x00
 #define PIN_MUX_SEL_DSPI       0x0a
+#define SCFG_QSPICLKCTRL_DIV_20        (5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -80,6 +81,8 @@ int checkboard(void)
                puts("PromJet\n");
        else if (sw == 0x9)
                puts("NAND\n");
+       else if (sw == 0xf)
+               puts("QSPI\n");
        else if (sw == 0x15)
                printf("IFCCard\n");
        else
@@ -207,6 +210,15 @@ int board_init(void)
        else
                config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+       val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+       if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+               QIXIS_WRITE(brdcfg[9],
+                           (QIXIS_READ(brdcfg[9]) & 0xf8) |
+                            FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
        gd->env_addr = (ulong)&default_environment[0];
 #endif
@@ -218,7 +230,14 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+       i2c_early_init_f();
+#endif
        fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+       /* input clk: 1/2 platform clk, output: input/20 */
+       out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
        return 0;
 }
 

diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 58ea7465477c86e959ce2603247698c1d4aa9e15..799799c251c2f21ed9eb8fe57ee00b4bc7df7bb4 100644 (file)
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -20,9 +20,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MC_BOOT_ENV_VAR "mcinitcmd"
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
+       char *mc_boot_env_var;
        int i, interface;
        struct memac_mdio_info mdio_info;
        struct mii_dev *dev;
@@ -89,6 +91,9 @@ int board_eth_init(bd_t *bis)
                }
        }
 
+       mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+       if (mc_boot_env_var)
+               run_command_list(mc_boot_env_var, -1, 0);
        cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
 

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c2e9c5739bf1629994ef4831754c8b64fdc6b461..d63a979be5899d45c910fb24058e0e2ea95b827f 100644 (file)
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -321,39 +321,6 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
-       unsigned short val;
-
-       /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-       val &= 0xffe3;
-       val |= 0x18;
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-       /* introduce tx clock delay */
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-       val |= 0x0100;
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-       return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-       mx6_rgmii_rework(phydev);
-
-       if (phydev->drv->config)
-               phydev->drv->config(phydev);
-
-       return 0;
-}
-
 static void setup_fec(void)
 {
        if (is_mx6dqp()) {
@@ -625,9 +592,9 @@ int board_late_init(void)
 
        if (is_mx6dqp())
                setenv("board_rev", "MX6QP");
-       else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+       else if (is_mx6dq())
                setenv("board_rev", "MX6Q");
-       else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+       else if (is_mx6sdl())
                setenv("board_rev", "MX6DL");
 #endif
 

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2319354fa33850b49f1f54239e85941023f1e788..54ba36b535910fdc3a9d446658182d0d10ecc041 100644 (file)
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -649,9 +649,9 @@ int board_late_init(void)
 
        if (is_mx6dqp())
                setenv("board_rev", "MX6QP");
-       else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+       else if (is_mx6dq())
                setenv("board_rev", "MX6Q");
-       else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+       else if (is_mx6sdl())
                setenv("board_rev", "MX6DL");
 #endif
 

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index f1915a8200680b6658a6b31d6179c5c0c6bbc76d..256d6029b4e6556ed13ad8f50312ccd7f445f1fa 100644 (file)
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -230,14 +230,14 @@ int board_mmc_init(bd_t *bis)
                        printf("Warning: you configured more USDHC controllers"
                                "(%d) than supported by the board\n", i + 1);
                        return -EINVAL;
-                       }
-
-                       ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-                       if (ret) {
-                               printf("Warning: failed to initialize "
-                                       "mmc dev %d\n", i);
-                               return ret;
-                       }
+               }
+
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               if (ret) {
+                       printf("Warning: failed to initialize "
+                               "mmc dev %d\n", i);
+                       return ret;
+               }
        }
 
        return 0;

diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig
new file mode 100644 (file)
index 0000000..e71dfc4
--- /dev/null
+++ b/board/freescale/s32v234evb/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_S32V234EVB
+
+config SYS_CPU
+       string
+       default "armv8"
+
+config SYS_BOARD
+       string
+       default "s32v234evb"
+
+config SYS_VENDOR
+       string
+       default "freescale"
+
+config SYS_SOC
+       string
+       default "s32v234"
+
+config SYS_CONFIG_NAME
+       string
+       default "s32v234evb"
+
+endif

diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS
new file mode 100644 (file)
index 0000000..62b2e1b
--- /dev/null
+++ b/board/freescale/s32v234evb/MAINTAINERS
@@ -0,0 +1,8 @@
+S32V234 Evaluation BOARD
+M:     Eddy Petrișor <eddy.petrisor@gmail.com>
+S:     Maintained
+F:     arch/arm/cpu/armv8/s32v234/
+F:     arch/arm/include/asm/arch-s32v234/
+F:     board/freescale/s32v234evb/
+F:     include/configs/s32v234evb.h
+F:     configs/s32v234evb_defconfig

diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile
new file mode 100644 (file)
index 0000000..69e6d3e
--- /dev/null
+++ b/board/freescale/s32v234evb/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y   := clock.o
+obj-y   += lpddr2.o
+obj-y   += s32v234evb.o
+
+#########################################################################

diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c
new file mode 100644 (file)
index 0000000..d218c21
--- /dev/null
+++ b/board/freescale/s32v234evb/clock.c
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mc_cgm_regs.h>
+#include <asm/arch/mc_me_regs.h>
+#include <asm/arch/clock.h>
+
+/*
+ * Select the clock reference for required pll.
+ * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
+ * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
+ */
+static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)
+{
+       u32 clk_src;
+       u32 pll_idx;
+       volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR;
+
+       /* select the pll clock source */
+       switch (refclk_freq) {
+       case FIRC_CLK_FREQ:
+               clk_src = SRC_GPR1_FIRC_CLK_SOURCE;
+               break;
+       case XOSC_CLK_FREQ:
+               clk_src = SRC_GPR1_XOSC_CLK_SOURCE;
+               break;
+       default:
+               /* The clock frequency for the source clock is unknown */
+               return -1;
+       }
+       /*
+        * The hardware definition is not uniform, it has to calculate again
+        * the recurrence formula.
+        */
+       switch (pll) {
+       case PERIPH_PLL:
+               pll_idx = 3;
+               break;
+       case ENET_PLL:
+               pll_idx = 1;
+               break;
+       case DDR_PLL:
+               pll_idx = 2;;
+               break;
+       default:
+               pll_idx = pll;
+       }
+
+       writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src),
+              &src->gpr1);
+
+       return 0;
+}
+
+static void entry_to_target_mode(u32 mode)
+{
+       writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL);
+       writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL);
+       while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ;
+}
+
+/*
+ * Program the pll according to the input parameters.
+ * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
+ * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
+ * freq - expected output frequency for PHY0
+ * freq1 - expected output frequency for PHY1
+ * dfs_nr - number of DFS modules for current PLL
+ * dfs - array with the activation dfs field, mfn and mfi
+ * plldv_prediv - divider of clkfreq_ref
+ * plldv_mfd - loop multiplication factor divider
+ * pllfd_mfn - numerator loop multiplication factor divider
+ * Please consult the PLLDIG chapter of platform manual
+ * before to use this function.
+ *)
+ */
+static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1,
+                      u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv,
+                      u32 plldv_mfd, u32 pllfd_mfn)
+{
+       u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco;
+
+       /*
+        * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter.
+        */
+       fvco =
+           (refclk_freq / plldv_prediv) * (plldv_mfd +
+                                           pllfd_mfn / (float)20480);
+
+       /*
+        * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult
+        * the platform DataSheet in order to determine the allowed values.
+        */
+
+       if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) {
+               return -1;
+       }
+
+       if (select_pll_source_clk(pll, refclk_freq) < 0) {
+               return -1;
+       }
+
+       rfdphi = fvco / freq0;
+
+       rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1;
+
+       writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) |
+              PLLDIG_PLLDV_RFDPHI_SET(rfdphi) |
+              PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) |
+              PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll));
+
+       writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) |
+              PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll));
+
+       /* switch on the pll in current mode */
+       writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll),
+              MC_ME_RUNn_MC(0));
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+       /* Only ARM_PLL, ENET_PLL and DDR_PLL */
+       if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) {
+               /* DFS clk enable programming */
+               writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll));
+
+               writel(DFS_DLLPRG1_CPICTRL_SET(0x5) |
+                      DFS_DLLPRG1_VSETTLCTRL_SET(0x1) |
+                      DFS_DLLPRG1_CALBYPEN_SET(0x0) |
+                      DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) |
+                      DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll));
+
+               for (i = 0; i < dfs_nr; i++) {
+                       if (dfs[i][0]) {
+                               writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) |
+                                      DFS_DVPORTn_MFN_SET(dfs[i][1]),
+                                      DFS_DVPORTn(pll, i));
+                               dfs_on |= (dfs[i][0] << i);
+                       }
+               }
+
+               writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET,
+                      DFS_CTRL(pll));
+               writel(readl(DFS_PORTRESET(pll)) &
+                      ~DFS_PORTRESET_PORTRESET_SET(dfs_on),
+                      DFS_PORTRESET(pll));
+               while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ;
+       }
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+       return 0;
+
+}
+
+static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source)
+{
+       /* select the clock source */
+       writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac));
+}
+
+static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider)
+{
+       /* set the divider */
+       writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider),
+              CGM_ACn_DCm(cgm_addr, ac, dc));
+}
+
+static void setup_sys_clocks(void)
+{
+
+       /* set ARM PLL DFS 1 as SYSCLK */
+       writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) |
+              MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0));
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+       /* select sysclks  ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */
+       writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK
+              (0x2,
+               MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) |
+              MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
+                                            MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET)
+              | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
+                                              MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET),
+              MC_ME_RUNn_SEC_CC_I(0));
+
+       /* setup the sys clock divider for CORE_CLK (1000MHz) */
+       writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
+              CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0));
+
+       /* setup the sys clock divider for CORE2_CLK (500MHz) */
+       writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
+              CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1));
+       /* setup the sys clock divider for SYS3_CLK (266 MHz) */
+       writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
+              CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0));
+
+       /* setup the sys clock divider for SYS6_CLK (133 Mhz) */
+       writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
+              CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1));
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+}
+
+static void setup_aux_clocks(void)
+{
+       /*
+        * setup the aux clock divider for PERI_CLK
+        * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)
+        */
+       aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX);
+       aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4);
+
+       /* setup the aux clock divider for LIN_CLK (40MHz) */
+       aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX);
+       aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1);
+
+       /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */
+       aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL);
+       aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9);
+
+       /* setup the aux clock divider for ENET_CLK (50MHz) */
+       aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL);
+       aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9);
+
+       /* setup the aux clock divider for SDHC_CLK (50 MHz). */
+       aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL);
+       aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9);
+
+       /* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */
+       aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL);
+       aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0);
+       /* setup the aux clock divider for DDR4_CLK (133,25MHz) */
+       aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3);
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+}
+
+static void enable_modules_clock(void)
+{
+       /* PIT0 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58);
+       /* PIT1 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170);
+       /* LINFLEX0 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83);
+       /* LINFLEX1 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188);
+       /* ENET */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50);
+       /* SDHC */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93);
+       /* IIC0 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81);
+       /* IIC1 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184);
+       /* IIC2 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186);
+       /* MMDC0 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54);
+       /* MMDC1 */
+       writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162);
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+}
+
+void clock_init(void)
+{
+       unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
+               {ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN,
+                ARM_PLL_PHI1_DFS1_MFI},
+               {ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN,
+                ARM_PLL_PHI1_DFS2_MFI},
+               {ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN,
+                ARM_PLL_PHI1_DFS3_MFI}
+       };
+
+       unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
+               {ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN,
+                ENET_PLL_PHI1_DFS1_MFI},
+               {ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN,
+                ENET_PLL_PHI1_DFS2_MFI},
+               {ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN,
+                ENET_PLL_PHI1_DFS3_MFI},
+               {ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN,
+                ENET_PLL_PHI1_DFS4_MFI}
+       };
+
+       unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
+               {DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN,
+                DDR_PLL_PHI1_DFS1_MFI},
+               {DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN,
+                DDR_PLL_PHI1_DFS2_MFI},
+               {DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN,
+                DDR_PLL_PHI1_DFS3_MFI}
+       };
+
+       writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 |
+              MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0));
+
+       /* turn on FXOSC */
+       writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON |
+              MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1),
+              MC_ME_RUNn_MC(0));
+
+       entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+       program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ,
+                   ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs,
+                   ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN);
+
+       setup_sys_clocks();
+
+       program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ,
+                   PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL,
+                   PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD,
+                   PERIPH_PLL_PLLDV_MFN);
+
+       program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ,
+                   ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs,
+                   ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD,
+                   ENET_PLL_PLLDV_MFN);
+
+       program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ,
+                   DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs,
+                   DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN);
+
+       program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ,
+                   VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL,
+                   VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD,
+                   VIDEO_PLL_PLLDV_MFN);
+
+       setup_aux_clocks();
+
+       enable_modules_clock();
+
+}

diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c
new file mode 100644 (file)
index 0000000..ecc0842
--- /dev/null
+++ b/board/freescale/s32v234evb/lpddr2.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/siul.h>
+#include <asm/arch/lpddr2.h>
+#include <asm/arch/mmdc.h>
+
+volatile int mscr_offset_ck0;
+
+void lpddr2_config_iomux(uint8_t module)
+{
+       int i;
+
+       switch (module) {
+       case DDR0:
+               mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
+               writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
+
+               writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
+               writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
+
+               writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
+               writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
+
+               for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
+                       writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
+
+               for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
+                       writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
+
+               for (i = _DDR0_A0; i <= _DDR0_A9; i++)
+                       writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
+
+               for (i = _DDR0_D0; i <= _DDR0_D31; i++)
+                       writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
+               break;
+       case DDR1:
+               writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
+
+               writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
+               writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
+
+               writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
+               writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
+
+               for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
+                       writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
+
+               for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
+                       writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
+
+               for (i = _DDR1_A0; i <= _DDR1_A9; i++)
+                       writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
+
+               for (i = _DDR1_D0; i <= _DDR1_D31; i++)
+                       writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
+               break;
+       }
+}
+
+void config_mmdc(uint8_t module)
+{
+       unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
+
+       writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
+
+       writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
+       writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
+       writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
+       writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
+       writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
+       writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
+       writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
+       writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
+
+       writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
+
+       while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
+       }
+
+       writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
+
+       /* Perform ZQ calibration */
+       writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
+       writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
+       while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
+       }
+
+       /* Enable MMDC with CS0 */
+       writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
+
+       /* Complete the initialization sequence as defined by JEDEC */
+       writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
+       writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
+       writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
+       writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
+
+       /* Set the amount of DRAM */
+       /* Set DQS settings based on board type */
+
+       switch (module) {
+       case MMDC0:
+               writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
+               writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
+                      mmdc_addr + MMDC_MPRDDLCTL);
+               writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
+                      mmdc_addr + MMDC_MPWRDLCTL);
+               writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
+                      mmdc_addr + MMDC_MPDGCTRL0);
+               writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
+                      mmdc_addr + MMDC_MPDGCTRL1);
+               break;
+       case MMDC1:
+               writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
+               writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
+                      mmdc_addr + MMDC_MPRDDLCTL);
+               writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
+                      mmdc_addr + MMDC_MPWRDLCTL);
+               writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
+                      mmdc_addr + MMDC_MPDGCTRL0);
+               writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
+                      mmdc_addr + MMDC_MPDGCTRL1);
+               break;
+       }
+
+       writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
+       writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
+       writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
+       writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
+       writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
+
+}

diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c
new file mode 100644 (file)
index 0000000..3100f09
--- /dev/null
+++ b/board/freescale/s32v234evb/s32v234evb.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/siul.h>
+#include <asm/arch/lpddr2.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void setup_iomux_ddr(void)
+{
+       lpddr2_config_iomux(DDR0);
+       lpddr2_config_iomux(DDR1);
+
+}
+
+void ddr_phy_init(void)
+{
+}
+
+void ddr_ctrl_init(void)
+{
+       config_mmdc(0);
+       config_mmdc(1);
+}
+
+int dram_init(void)
+{
+       setup_iomux_ddr();
+
+       ddr_ctrl_init();
+
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+       return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+       /* Muxing for linflex */
+       /* Replace the magic values after bringup */
+
+       /* set TXD - MSCR[12] PA12 */
+       writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
+
+       /* set RXD - MSCR[11] - PA11 */
+       writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
+
+       /* set RXD - IMCR[200] - 200 */
+       writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
+}
+
+static void setup_iomux_enet(void)
+{
+}
+
+static void setup_iomux_i2c(void)
+{
+}
+
+#ifdef CONFIG_SYS_USE_NAND
+void setup_iomux_nfc(void)
+{
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+       {USDHC_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       /* eSDHC1 is always present */
+       return 1;
+}
+
+int board_mmc_init(bd_t * bis)
+{
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
+
+       /* Set iomux PADS for USDHC */
+
+       /* PK6 pad: uSDHC clk */
+       writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
+       writel(0x3, SIUL2_MSCRn(902));
+
+       /* PK7 pad: uSDHC CMD */
+       writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
+       writel(0x3, SIUL2_MSCRn(901));
+
+       /* PK8 pad: uSDHC DAT0 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
+       writel(0x3, SIUL2_MSCRn(903));
+
+       /* PK9 pad: uSDHC DAT1 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
+       writel(0x3, SIUL2_MSCRn(904));
+
+       /* PK10 pad: uSDHC DAT2 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
+       writel(0x3, SIUL2_MSCRn(905));
+
+       /* PK11 pad: uSDHC DAT3 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
+       writel(0x3, SIUL2_MSCRn(906));
+
+       /* PK15 pad: uSDHC DAT4 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
+       writel(0x3, SIUL2_MSCRn(907));
+
+       /* PL0 pad: uSDHC DAT5 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
+       writel(0x3, SIUL2_MSCRn(908));
+
+       /* PL1 pad: uSDHC DAT6 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
+       writel(0x3, SIUL2_MSCRn(909));
+
+       /* PL2 pad: uSDHC DAT7 */
+       writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
+       writel(0x3, SIUL2_MSCRn(910));
+
+       return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void mscm_init(void)
+{
+       struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
+       int i;
+
+       for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+               writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       clock_init();
+       mscm_init();
+
+       setup_iomux_uart();
+       setup_iomux_enet();
+       setup_iomux_i2c();
+#ifdef CONFIG_SYS_USE_NAND
+       setup_iomux_nfc();
+#endif
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: s32v234evb\n");
+
+       return 0;
+}

diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg
new file mode 100644 (file)
index 0000000..6017a40
--- /dev/null
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION  2
+BOOT_FROM sd
+
+
+/*
+ * Boot Device : one of qspi, sd:
+ * qspi:   flash_offset: 0x1000
+ * sd/mmc: flash_offset: 0x1000
+ */
+
+
+#ifdef CONFIG_SECURE_BOOT
+SECURE_BOOT
+#endif

diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
index 94189076970914a689c204fce6d055008f3434b5..f3f8998aae613787946465887bf3877577df6df4 100644 (file)
--- a/board/gateworks/gw_ventana/README
+++ b/board/gateworks/gw_ventana/README
@@ -173,13 +173,8 @@ OS load time which defeats the purpose of Falcon mode in the first place.
 The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
 based on the return value of the spl_start_uboot() function. While often
 this can simply be the state of a GPIO based pushbutton or DIP switch, for
-Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if
-set to '1' will choose to boot the OS rather than U-Boot. While the choice
-of adding env support to the SPL adds a little bit of time to the boot
-process as well as (significant really) SPL code space this was deemed most
-flexible as within the large variety of Gateworks Ventana boards not all of
-them have a user pushbutton and that pushbutton may be configured as a hard
-reset per user configuration.
+Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
+set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
 
 To use Falcon mode it is required that you first 'prepare' the 'args' data
 that is stored on your boot medium along with the kernel (which can be any
@@ -235,8 +230,8 @@ using rootfs (ubi), kernel (uImage), and dtb from the network:
  # flash args (at 17MB)
  Ventana > nand erase.part args && nand write 18000000 args 100000
 
- # set boot_os env var to enable booting to Linux
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
 
 Be sure to adjust 'bootargs' above to your OS needs (this will be different
 for various distros such as OpenWrt, Yocto, Android, etc). You can use the
@@ -309,8 +304,8 @@ out in U-Boot and use the following to enable Falcon mode:
  # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
  Ventana > mmc write 18000000 0x800 0x800
 
- # set boot_os to enable falcon mode
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
 
 Be sure to adjust 'bootargs' above to your OS needs (this will be different
 for various distros such as OpenWrt, Yocto, Android, etc). You can use the

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index a20190eef080fb93148faa3cf0e298727f51e229..929dde9880a8dd4658543e456e4d058d156a0557 100644 (file)
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -132,10 +132,10 @@ void setup_ventana_i2c(void)
 
 /* common to add baseboards */
 static iomux_v3_cfg_t const gw_gpio_pads[] = {
-       /* MSATA_EN */
-       IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
        /* RS232_EN# */
        IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+       /* SD3_VSELECT */
+       IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 };
 
 /* prototype */
@@ -183,6 +183,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+       /* MSATA_EN */
+       IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
        /* PANLEDG# */
        IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
        /* PANLEDR# */
@@ -212,6 +214,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+       /* MSATA_EN */
+       IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
        /* CAN_STBY */
        IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
        /* USB_HUBRST# */
@@ -241,6 +245,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+       /* MSATA_EN */
+       IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
        /* CAN_STBY */
        IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
        /* PANLEDG# */
@@ -283,6 +289,8 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+       /* MSATA_EN */
+       IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
        /* USBOTG_SEL */
        IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
        /* USB_HUBRST# */
@@ -310,6 +318,20 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
        IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 };
 
+static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
+       /* PANLEDG# */
+       IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
+       /* PANLEDR# */
+       IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
+
+       /* VID_PWR */
+       IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+       /* PCI_RST# */
+       IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+       /* PCIESKT_WDIS# */
+       IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
 
 /*
  * Board Specific GPIO
@@ -445,6 +467,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
                .vidin_en = IMX_GPIO_NR(3, 31),
                .usb_sel = IMX_GPIO_NR(1, 2),
                .wdis = IMX_GPIO_NR(7, 12),
+               .msata_en = GP_MSATA_SEL,
        },
 
        /* GW53xx */
@@ -489,6 +512,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
                .gps_shdn = IMX_GPIO_NR(1, 27),
                .vidin_en = IMX_GPIO_NR(3, 31),
                .wdis = IMX_GPIO_NR(7, 12),
+               .msata_en = GP_MSATA_SEL,
        },
 
        /* GW54xx */
@@ -535,6 +559,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
                .dioi2c_en = IMX_GPIO_NR(4,  5),
                .pcie_sson = IMX_GPIO_NR(1, 20),
                .wdis = IMX_GPIO_NR(5, 17),
+               .msata_en = GP_MSATA_SEL,
        },
 
        /* GW551x */
@@ -602,6 +627,47 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
                .pcie_rst = IMX_GPIO_NR(1, 29),
                .usb_sel = IMX_GPIO_NR(1, 7),
                .wdis = IMX_GPIO_NR(7, 12),
+               .msata_en = GP_MSATA_SEL,
+       },
+
+       /* GW553x */
+       {
+               .gpio_pads = gw553x_gpio_pads,
+               .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
+               .dio_cfg = {
+                       {
+                               { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+                               IMX_GPIO_NR(1, 16),
+                               { 0, 0 },
+                               0
+                       },
+                       {
+                               { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+                               IMX_GPIO_NR(1, 19),
+                               { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+                               2
+                       },
+                       {
+                               { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+                               IMX_GPIO_NR(1, 17),
+                               { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+                               3
+                       },
+                       {
+                               { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+                               IMX_GPIO_NR(1, 18),
+                               { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+                               4
+                       },
+               },
+               .num_gpios = 4,
+               .leds = {
+                       IMX_GPIO_NR(4, 10),
+                       IMX_GPIO_NR(4, 11),
+               },
+               .pcie_rst = IMX_GPIO_NR(1, 0),
+               .vidin_en = IMX_GPIO_NR(5, 20),
+               .wdis = IMX_GPIO_NR(7, 12),
        },
 };
 
@@ -616,10 +682,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
        gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
        gpio_direction_output(GP_USB_OTG_PWR, 0);
 
-       /* MSATA Enable - default to PCI */
-       gpio_request(GP_MSATA_SEL, "msata_en");
-       gpio_direction_output(GP_MSATA_SEL, 0);
-
        /* RS232_EN# */
        gpio_request(GP_RS232_EN, "rs232_en");
        gpio_direction_output(GP_RS232_EN, 0);
@@ -649,6 +711,12 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
                }
        }
 
+       /* MSATA Enable - default to PCI */
+       if (gpio_cfg[board].msata_en) {
+               gpio_request(gpio_cfg[board].msata_en, "msata_en");
+               gpio_direction_output(gpio_cfg[board].msata_en, 0);
+       }
+
        /* Expansion Mezzanine IO */
        if (gpio_cfg[board].mezz_pwren) {
                gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
@@ -700,6 +768,11 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
                gpio_request(gpio_cfg[board].wdis, "wlan_dis");
                gpio_direction_output(gpio_cfg[board].wdis, 1);
        }
+
+       /* sense vselect pin to see if we support uhs-i */
+       gpio_request(GP_SD3_VSELECT, "sd3_vselect");
+       gpio_direction_input(GP_SD3_VSELECT);
+       gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
 }
 
 /* setup GPIO pinmux and default configuration per baseboard and env */
@@ -718,10 +791,9 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
        gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 
        /* MSATA Enable */
-       if (is_cpu_type(MXC_CPU_MX6Q) &&
-           test_bit(EECONFIG_SATA, info->config)) {
+       if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
                gpio_direction_output(GP_MSATA_SEL,
-                                     (hwconfig("msata")) ?  1 : 0);
+                                     (hwconfig("msata")) ? 1 : 0);
        }
 
        /* USBOTG Select (PCISKT or FrontPanel) */
@@ -760,8 +832,13 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
                                               ctrl);
                        gpio_requestf(cfg->gpio_param, "dio%d", i);
                        gpio_direction_input(cfg->gpio_param);
-               } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+               } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
                           cfg->pwm_padmux) {
+                       if (!cfg->pwm_param) {
+                               printf("DIO%d:  Error: pwm config invalid\n",
+                                       i);
+                               continue;
+                       }
                        if (!quiet)
                                printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
                        imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
@@ -770,8 +847,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
        }
 
        if (!quiet) {
-               if (is_cpu_type(MXC_CPU_MX6Q) &&
-                   (test_bit(EECONFIG_SATA, info->config))) {
+               if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
                        printf("MSATA: %s\n", (hwconfig("msata") ?
                               "enabled" : "disabled"));
                }

diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 28f58160de516189fd980d4c70fab82bff31f07b..d037767ecc8f81408d2a5f96d45e1d04fa1d1154 100644 (file)
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -17,6 +17,7 @@
 #define GP_SD3_CD      IMX_GPIO_NR(7, 0)
 #define GP_RS232_EN    IMX_GPIO_NR(2, 11)
 #define GP_MSATA_SEL   IMX_GPIO_NR(2, 8)
+#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14)
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
@@ -76,6 +77,8 @@ struct ventana {
        int pcie_sson;
        int usb_sel;
        int wdis;
+       int msata_en;
+       bool usd_vsel;
 };
 
 extern struct ventana gpio_cfg[GW_UNKNOWN];

diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index ba159696b43cf51e85bdd71414eb1faa61fc2753..1382e5debea12b1fbfc2dc5d395ff27dd4f94244 100644 (file)
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -87,6 +87,9 @@ read_eeprom(int bus, struct ventana_board_info *info)
                } else if (info->model[4] == '2') {
                        type = GW552x;
                        break;
+               } else if (info->model[4] == '3') {
+                       type = GW553x;
+                       break;
                }
                /* fall through */
        default:
@@ -100,43 +103,12 @@ read_eeprom(int bus, struct ventana_board_info *info)
 /* list of config bits that the bootloader will remove from dtb if not set */
 struct ventana_eeprom_config econfig[] = {
        { "eth0", "ethernet0", EECONFIG_ETH0 },
-       { "eth1", "ethernet1", EECONFIG_ETH1 },
-       { "sata", "ahci0", EECONFIG_SATA },
-       { "pcie", NULL, EECONFIG_PCIE},
-       { "lvds0", NULL, EECONFIG_LVDS0 },
-       { "lvds1", NULL, EECONFIG_LVDS1 },
        { "usb0", NULL, EECONFIG_USB0 },
        { "usb1", NULL, EECONFIG_USB1 },
        { "mmc0", NULL, EECONFIG_SD0 },
        { "mmc1", NULL, EECONFIG_SD1 },
        { "mmc2", NULL, EECONFIG_SD2 },
        { "mmc3", NULL, EECONFIG_SD3 },
-       { "uart0", NULL, EECONFIG_UART0 },
-       { "uart1", NULL, EECONFIG_UART1 },
-       { "uart2", NULL, EECONFIG_UART2 },
-       { "uart3", NULL, EECONFIG_UART3 },
-       { "uart4", NULL, EECONFIG_UART4 },
-       { "ipu0", NULL, EECONFIG_IPU0 },
-       { "ipu1", NULL, EECONFIG_IPU1 },
-       { "can0", NULL, EECONFIG_FLEXCAN },
-       { "i2c0", NULL, EECONFIG_I2C0 },
-       { "i2c1", NULL, EECONFIG_I2C1 },
-       { "i2c2", NULL, EECONFIG_I2C2 },
-       { "vpu", NULL, EECONFIG_VPU },
-       { "csi0", NULL, EECONFIG_CSI0 },
-       { "csi1", NULL, EECONFIG_CSI1 },
-       { "spi0", NULL, EECONFIG_ESPCI0 },
-       { "spi1", NULL, EECONFIG_ESPCI1 },
-       { "spi2", NULL, EECONFIG_ESPCI2 },
-       { "spi3", NULL, EECONFIG_ESPCI3 },
-       { "spi4", NULL, EECONFIG_ESPCI4 },
-       { "spi5", NULL, EECONFIG_ESPCI5 },
-       { "gps", "pps", EECONFIG_GPS },
-       { "hdmi_in", NULL, EECONFIG_HDMI_IN },
-       { "hdmi_out", NULL, EECONFIG_HDMI_OUT },
-       { "cvbs_in", NULL, EECONFIG_VID_IN },
-       { "cvbs_out", NULL, EECONFIG_VID_OUT },
-       { "nand", NULL, EECONFIG_NAND },
        { /* Sentinel */ }
 };
 

diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 3febd1276ebc081edc741c5cb787c52d75cf6b74..2ca6d5c7659a33738303a269f10b9b93b6e5448c 100644 (file)
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -11,6 +11,7 @@
 #include <i2c.h>
 #include <linux/ctype.h>
 
+#include "ventana_eeprom.h"
 #include "gsc.h"
 
 /*
@@ -70,6 +71,8 @@ static void read_hwmon(const char *name, uint reg, uint size)
                puts("fRD\n");
        } else {
                ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+               if (reg == GSC_HWMON_TEMP && ui > 0x8000)
+                       ui -= 0xffff;
                if (ui == 0xffffff)
                        puts("invalid\n");
                else
@@ -79,7 +82,6 @@ static void read_hwmon(const char *name, uint reg, uint size)
 
 int gsc_info(int verbose)
 {
-       const char *model = getenv("model");
        unsigned char buf[16];
 
        i2c_set_bus_num(0);
@@ -96,6 +98,12 @@ int gsc_info(int verbose)
                gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
                              &buf[GSC_SC_STATUS], 1);
        }
+       if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
+               int ui = buf[0] | buf[1]<<8;
+               if (ui > 0x8000)
+                       ui -= 0xffff;
+               printf(" board temp at %dC", ui / 10);
+       }
        puts("\n");
        if (!verbose)
                return CMD_RET_SUCCESS;
@@ -109,10 +117,11 @@ int gsc_info(int verbose)
        read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
        read_hwmon("VDD_DDR",  GSC_HWMON_VDD_DDR, 3);
        read_hwmon("VDD_5P0",  GSC_HWMON_VDD_5P0, 3);
-       read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
+       if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
+               read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
        read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3);
        read_hwmon("VDD_IO2",  GSC_HWMON_VDD_IO2, 3);
-       switch (model[3]) {
+       switch (ventana_info.model[3]) {
        case '1': /* GW51xx */
                read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
                break;
@@ -160,6 +169,48 @@ int gsc_boot_wd_disable(void)
 }
 
 #ifdef CONFIG_CMD_GSC
+static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
+                       char * const argv[])
+{
+       unsigned char reg;
+       unsigned long secs = 0;
+
+       if (argc < 2)
+               return CMD_RET_USAGE;
+
+       secs = simple_strtoul(argv[1], NULL, 10);
+       printf("GSC Sleeping for %ld seconds\n", secs);
+
+       i2c_set_bus_num(0);
+       reg = (secs >> 24) & 0xff;
+       if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, &reg, 1))
+               goto error;
+       reg = (secs >> 16) & 0xff;
+       if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, &reg, 1))
+               goto error;
+       reg = (secs >> 8) & 0xff;
+       if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, &reg, 1))
+               goto error;
+       reg = secs & 0xff;
+       if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, &reg, 1))
+               goto error;
+       if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+               goto error;
+       reg |= (1 << 2);
+       if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+               goto error;
+       reg &= ~(1 << 2);
+       reg |= 0x3;
+       if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+               goto error;
+
+       return CMD_RET_SUCCESS;
+
+error:
+       printf("i2c error\n");
+       return CMD_RET_FAILURE;
+}
+
 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        unsigned char reg;
@@ -206,13 +257,15 @@ static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        if (strcasecmp(argv[1], "wd") == 0)
                return do_gsc_wd(cmdtp, flag, --argc, ++argv);
+       else if (strcasecmp(argv[1], "sleep") == 0)
+               return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
 
        return CMD_RET_USAGE;
 }
 
 U_BOOT_CMD(
        gsc, 4, 1, do_gsc, "GSC configuration",
-       "[wd enable [30|60]]|[wd disable]\n"
+       "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
        );
 
 #endif /* CONFIG_CMD_GSC */

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index e2eeef37936610534f476096e97a704b29c0e9db..70395ac91db69ec5659f4fad93138e6f4ec84bec 100644 (file)
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -21,6 +21,7 @@
 #include <asm/io.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
+#include <hwconfig.h>
 #include <i2c.h>
 #include <fdt_support.h>
 #include <fsl_esdhc.h>
@@ -59,8 +60,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
        IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
        IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
        IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       /* CD */
-       IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 };
 
 /* ENET */
@@ -266,7 +266,9 @@ int board_phy_config(struct phy_device *phydev)
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FEC_MXC
-       if (board_type != GW551x && board_type != GW552x) {
+       struct ventana_board_info *info = &ventana_info;
+
+       if (test_bit(EECONFIG_ETH0, info->config)) {
                setup_iomux_enet(GP_PHY_RST);
                cpu_eth_init(bis);
        }
@@ -317,6 +319,8 @@ static void enable_lvds(struct display_info_t const *dev)
        writel(reg, &iomux->gpr[2]);
 
        /* Enable Backlight */
+       gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+       gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
        gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
        SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
        gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
@@ -456,8 +460,7 @@ static void setup_display(void)
               <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
        writel(reg, &iomux->gpr[3]);
 
-       /* Backlight CABEN on LVDS connector */
-       gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+       /* LVDS Backlight GPIO on LVDS connector - output low */
        SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
        gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 }
@@ -697,7 +700,9 @@ int misc_init_r(void)
                        setenv("model_base", str);
                        sprintf(fdt, "%s-%s.dtb", cputype, str);
                        setenv("fdt_file1", fdt);
-                       if (board_type != GW551x && board_type != GW552x)
+                       if (board_type != GW551x &&
+                           board_type != GW552x &&
+                           board_type != GW553x)
                                str[4] = 'x';
                        str[5] = 'x';
                        str[6] = 0;
@@ -776,6 +781,27 @@ static int ft_sethdmiinfmt(void *blob, char *mode)
        return 0;
 }
 
+/* enable a property of a node if the node is found */
+static inline void ft_enable_path(void *blob, const char *path)
+{
+       int i = fdt_path_offset(blob, path);
+       if (i >= 0) {
+               debug("enabling %s\n", path);
+               fdt_status_okay(blob, i);
+       }
+}
+
+/* remove a property of a node if the node is found */
+static inline void ft_delprop_path(void *blob, const char *path,
+                                  const char *name)
+{
+       int i = fdt_path_offset(blob, path);
+       if (i) {
+               debug("removing %s/%s\n", path, name);
+               fdt_delprop(blob, i, name);
+       }
+}
+
 /*
  * called prior to booting kernel or by 'fdt boardsetup' command
  *
@@ -879,6 +905,11 @@ int ft_board_setup(void *blob, bd_t *bd)
                                range[1] = cpu_to_fdt32(23);
                        }
                }
+
+               /* these have broken usd_vsel */
+               if (strstr((const char *)info->model, "SP318-B") ||
+                   strstr((const char *)info->model, "SP331-B"))
+                       gpio_cfg[board_type].usd_vsel = 0;
        }
 
        /*
@@ -919,6 +950,32 @@ int ft_board_setup(void *blob, bd_t *bd)
                ft_sethdmiinfmt(blob, "yuv422bt656");
        }
 
+       /* Configure DIO */
+       for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
+               struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
+               char arg[10];
+
+               sprintf(arg, "dio%d", i);
+               if (!hwconfig(arg))
+                       continue;
+               if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
+               {
+                       char path[48];
+                       sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
+                               0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
+                       printf("   Enabling pwm%d for DIO%d\n",
+                              cfg->pwm_param, i);
+                       ft_enable_path(blob, path);
+               }
+       }
+
+       /* remove no-1-8-v if UHS-I support is present */
+       if (gpio_cfg[board_type].usd_vsel) {
+               debug("Enabling UHS-I support\n");
+               ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
+                               "no-1-8-v");
+       }
+
        /*
         * Peripheral Config:
         *  remove nodes by alias path if EEPROM config tells us the

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 0a6ad47c7df37f4500c6fd126aac2c695833401f..e7f699a2b5bd3ea7f17b11aae46ea1c46e4d7838 100644 (file)
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -15,6 +15,7 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <environment.h>
+#include <i2c.h>
 #include <spl.h>
 
 #include "gsc.h"
@@ -189,6 +190,20 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
        .trasmin = 3500,
 };
 
+/* MT41K512M16HA-125 (8Gb density) */
+static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
+       .mem_speed = 1600,
+       .density = 8,
+       .width = 16,
+       .banks = 8,
+       .rowaddr = 16,
+       .coladdr = 10,
+       .pagesz = 2,
+       .trcd = 1375,
+       .trcmin = 4875,
+       .trasmin = 3500,
+};
+
 /*
  * calibration - these are the various CPU/DDR3 combinations we support
  */
@@ -340,6 +355,19 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
        .p1_mpwrdlctl = 0X40304239,
 };
 
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x002A0025,
+       .p0_mpwldectrl1 = 0x003A002A,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x43430356,
+       .p0_mpdgctrl1 = 0x033C0335,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x4B373F42,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x303E3C36,
+};
+
 static void spl_dram_init(int width, int size_mb, int board_model)
 {
        struct mx6_ddr3_cfg *mem = NULL;
@@ -419,6 +447,11 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                else
                        calib = &mx6sdl_256x32_mmdc_calib;
                debug("4gB density\n");
+       } else if (width == 32 && size_mb == 2048) {
+               mem = &mt41k512m16ha_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       calib = &mx6dq_512x32_mmdc_calib;
+               debug("8gB density\n");
        } else if (width == 64 && size_mb == 512) {
                mem = &mt41k64m16jt_125;
                debug("1gB density\n");
@@ -526,9 +559,6 @@ void board_init_f(ulong dummy)
 
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
-
-       /* disable boot watchdog */
-       gsc_boot_wd_disable();
 }
 
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
@@ -560,7 +590,7 @@ void spl_board_init(void)
 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 int spl_start_uboot(void)
 {
-       int ret = 1;
+       unsigned char ret = 1;
 
        debug("%s\n", __func__);
 #ifdef CONFIG_SPL_ENV_SUPPORT
@@ -569,7 +599,14 @@ int spl_start_uboot(void)
        debug("boot_os=%s\n", getenv("boot_os"));
        if (getenv_yesno("boot_os") == 1)
                ret = 0;
+#else
+       /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+       i2c_set_bus_num(0);
+       gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 #endif
+       if (!ret)
+               gsc_boot_wd_disable();
+
        debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
        return ret;
 }

diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index daff375e40b0a70fa0513fd3ad36023511a3b3ad..9ffad58e03e906cf0ec311a87481057ab7548f8d 100644 (file)
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -111,6 +111,7 @@ enum {
        GW54xx,
        GW551x,
        GW552x,
+       GW553x,
        GW_UNKNOWN,
        GW_BADCRC,
 };

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index ff8f4d7b972e842c6990afce8aa6fd95a4056953..d45ed44c68435ecb93ad33a1c5fb846889ead7ce 100644 (file)
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -601,6 +601,8 @@ int board_late_init(void)
 #ifdef CONFIG_CMD_BMODE
        add_board_boot_modes(board_boot_modes);
 #endif
+
+#ifdef CONFIG_VIDEO_IPUV3
        /* We need at least 200ms between power on and backlight on
         * as per specifications from CHI MEI */
        mdelay(250);
@@ -615,6 +617,7 @@ int board_late_init(void)
        gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 
        pwm_enable(0);
+#endif
 
        return 0;
 }

diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 84ee2bf43de911d1ee4441443ff7f650f18585c8..a5e774b2cf7b26e8d12b801e3e545b6e94666991 100644 (file)
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -54,7 +54,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
        writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
 
        /* Make sure other cores see written value in memory */
-       flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+       flush_dcache_all();
 }
 
 void smp_kick_all_cpus(void)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index bde5ac7c992aebafee04f64ce5737d26c0c68b9e..f005762edadea944ce1840bc7430086912131c76 100644 (file)
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -850,7 +850,7 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-       if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+       if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
                return 0;
        else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
                return 0;

diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig
index 87654f9799565ebd4aaf11901f7642441bbab95f..cead0f4f042e2233c2cae6d2ef7ccfb17ac7b452 100644 (file)
--- a/board/ti/am57xx/Kconfig
+++ b/board/ti/am57xx/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_BEAGLE_X15
+if TARGET_AM57XX_EVM
 
 config SYS_BOARD
        default "am57xx"

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index ccf97b2b13bb4ab11002a6490d9210c125b0011d..08cf14d5e73f629bf4a47d880aca7888d432d928 100644 (file)
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -736,3 +736,17 @@ int ft_board_setup(void *blob, bd_t *bd)
        return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+       if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
+               return 0;
+       else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
+               return 0;
+       else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
+               return 0;
+       else
+               return -1;
+}
+#endif

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 3fbbc9b23b0433bfc55e0384d8cc31be94c2522f..0394e4ee57adc2e79ccc377b4b3af059500f27c0 100644 (file)
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -305,6 +305,82 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
        }
 }
 
+struct vcores_data dra752_volts = {
+       .mpu.value      = VDD_MPU_DRA7,
+       .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
+       .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
+       .mpu.pmic       = &tps659038,
+       .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+       .eve.value      = VDD_EVE_DRA7,
+       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
+       .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .eve.addr       = TPS659038_REG_ADDR_SMPS45,
+       .eve.pmic       = &tps659038,
+       .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+       .gpu.value      = VDD_GPU_DRA7,
+       .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
+       .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
+       .gpu.pmic       = &tps659038,
+       .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+       .core.value     = VDD_CORE_DRA7,
+       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .core.addr      = TPS659038_REG_ADDR_SMPS7,
+       .core.pmic      = &tps659038,
+
+       .iva.value      = VDD_IVA_DRA7,
+       .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
+       .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .iva.addr       = TPS659038_REG_ADDR_SMPS8,
+       .iva.pmic       = &tps659038,
+       .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra722_volts = {
+       .mpu.value      = VDD_MPU_DRA7,
+       .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
+       .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
+       .mpu.pmic       = &tps659038,
+       .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+       .core.value     = VDD_CORE_DRA7,
+       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .core.addr      = TPS65917_REG_ADDR_SMPS2,
+       .core.pmic      = &tps659038,
+
+       /*
+        * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+        * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+        */
+       .gpu.value      = VDD_GPU_DRA7,
+       .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
+       .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
+       .gpu.pmic       = &tps659038,
+       .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+       .eve.value      = VDD_EVE_DRA7,
+       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
+       .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .eve.addr       = TPS65917_REG_ADDR_SMPS3,
+       .eve.pmic       = &tps659038,
+       .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+       .iva.value      = VDD_IVA_DRA7,
+       .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
+       .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .iva.addr       = TPS65917_REG_ADDR_SMPS3,
+       .iva.pmic       = &tps659038,
+       .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
 /**
  * @brief board_init
  *
@@ -390,6 +466,21 @@ void do_board_detect(void)
 }
 #endif /* CONFIG_SPL_BUILD */
 
+void vcores_init(void)
+{
+       if (board_is_dra74x_evm()) {
+               *omap_vcores = &dra752_volts;
+       } else if (board_is_dra72x_evm()) {
+               *omap_vcores = &dra722_volts;
+       } else {
+               /* If EEPROM is not populated */
+               if (is_dra72x())
+                       *omap_vcores = &dra722_volts;
+               else
+                       *omap_vcores = &dra752_volts;
+       }
+}
+
 void set_muxconf_regs(void)
 {
        do_set_mux32((*ctrl)->control_padconf_core_base,

diff --git a/cmd/gpt.c b/cmd/gpt.c
index 8ffaef30f568bd807669b93090eb8b3a802aa891..3d9706b679c5c2ff8f6a2b2ce2fd0546c08b6470 100644 (file)
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -181,6 +181,7 @@ static int set_gpt_info(struct blk_desc *dev_desc,
        disk_partition_t *parts;
        int errno = 0;
        uint64_t size_ll, start_ll;
+       lbaint_t offset = 0;
 
        debug("%s:  lba num: 0x%x %d\n", __func__,
              (unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba);
@@ -296,8 +297,14 @@ static int set_gpt_info(struct blk_desc *dev_desc,
                }
                if (extract_env(val, &p))
                        p = val;
-               size_ll = ustrtoull(p, &p, 0);
-               parts[i].size = lldiv(size_ll, dev_desc->blksz);
+               if ((strcmp(p, "-") == 0)) {
+                       /* remove first usable lba and last block */
+                       parts[i].size = dev_desc->lba - 34  - 1 - offset;
+               } else {
+                       size_ll = ustrtoull(p, &p, 0);
+                       parts[i].size = lldiv(size_ll, dev_desc->blksz);
+               }
+
                free(val);
 
                /* start address */
@@ -310,6 +317,8 @@ static int set_gpt_info(struct blk_desc *dev_desc,
                        free(val);
                }
 
+               offset += parts[i].size + parts[i].start;
+
                /* bootable */
                if (found_key(tok, "bootable"))
                        parts[i].bootable = 1;

diff --git a/common/Makefile b/common/Makefile
index 1557a044de5710b69c8e03768ec5e29899653ca5..97c59fe499a26beb8f51ec40435de385023597c1 100644 (file)
--- a/common/Makefile
+++ b/common/Makefile
@@ -93,6 +93,7 @@ obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
 endif # !CONFIG_SPL_BUILD
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o

diff --git a/common/bootm.c b/common/bootm.c
index 49414142dcd207902b96a7e93a64923c121e71ba..2431019b3f407d8eff683fa1cd8c5ce46a468cc4 100644 (file)
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -445,7 +445,7 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
                bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
                return err;
        }
-       flush_cache(load, *load_end - load);
+       flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
 
        debug("   kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
        bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);

diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index b3f825e33f28ae581ac08f3a7c8a37b303db35a1..2ac2596dce36acbfe6dfb5c59bbda171c9727ca5 100644 (file)
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=120
+CONFIG_INITIAL_USB_SCAN_DELAY=2000
 CONFIG_USB1_VBUS_PIN="PC27"
 CONFIG_USB2_VBUS_PIN=""
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"

diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index fc43cc5fb1ebbc09641ee6f60a0e5ecad5a8023b..17ed9685970c2848cf690210f0517d3e3fd76427 100644 (file)
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -11,3 +11,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_AXP_ALDO4_VOLT=3300

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index b63ff89da2097a4aad09ea1c26f20257f194828f..85265262afb80e26fa59f6fe465b4f919a608ad3 100644 (file)
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
@@ -36,3 +36,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"

diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 1cf82d293ed36434e779fab2f87d2cf412bc6a21..4c5a0de36917624a9f77c32f2ca6166f1a32080c 100644 (file)
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y

diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index aa459a1bedac8c184093c304405ec648d29d3416..ce377cbe714ff1cd5ba086c09666af8b80de4b22 100644 (file)
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000

diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 96a3de63c862831ac1f591c26bdabde3cac83a1c..c8474de3c462226a34ad386d6760cd358b38b94b 100644 (file)
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARC=y
 CONFIG_ISA_ARCV2=y
 CONFIG_DM_SERIAL=y
-CONFIG_SYS_CLK_FREQ=50000000
+CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="axs10x"
 CONFIG_BOOTDELAY=3

diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
new file mode 100644 (file)
index 0000000..3328e51
--- /dev/null
+++ b/configs/bcm23550_w1d_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCM23550_W1D=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_OF_LIBFDT=y

diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 2fa11fd442cc9fa30d06a6c427fab7144fbb1e2e..b18d80dea6008fe43151391a973ebb0b54c952a3 100644 (file)
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -24,6 +24,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y

diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index ffa04408a53a92f31ba9653548c269c9d83325b9..0ef418df22dd30e831e61665f2182052c58bb6ca 100644 (file)
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -8,18 +8,18 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n

diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index b039c248d586cab2128b67c5dd8c7324f15ca5f9..2af4b119c49f5781c430524df7a5de8410dea210 100644 (file)
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -8,18 +8,18 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n

diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index d9c8acd651663532361e9d9e330da0413639d084..9e0c5eb6a4f71f4a259fc3c1434948e9df09f311 100644 (file)
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -8,18 +8,18 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n

diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
new file mode 100644 (file)
index 0000000..80f0013
--- /dev/null
+++ b/configs/gurnard_defconfig
@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_GURNARD=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_BOOTDELAY=3
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set

diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 8c5b69d77fac2ada26c7dd0c31e8e0232ed203d3..dc1649299add17c3bd4c698fa6e6953e150ba8f6 100644 (file)
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -8,6 +8,14 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
@@ -19,6 +27,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y

diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
new file mode 100644 (file)
index 0000000..0850a68
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 45bb3ec0e9e9f3656fbf28070caed21983abf118..a03cff8e3fa9535c554b3ccad59f11991e3e0a9b 100644 (file)
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y

diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
new file mode 100644 (file)
index 0000000..847de63
--- /dev/null
+++ b/configs/s32v234evb_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_S32V234EVB=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_LIBFDT=y

diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index 22d3becb25a5541d2fe417d2a949b7052453873f..8c3a84caf8d8ee7ba8bf60af141af8693038d748 100644 (file)
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -9,7 +9,7 @@ The PINCTRL master node requires the following properties:
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
 - pad-offset   - (required) offset in the IOBASE for the pin to configure
-- gpio-offset  - (required) 2 cells
+- gpio-offset  - (required only when 'mode-gpio' is set) 2 cells
                        - offset in the GPIOBASE for the pin to configure
                        - the bit shift in this register (4 = bit 4)
 - mode-gpio    - (optional) standalone property to force the pin into GPIO mode
@@ -18,16 +18,16 @@ contain the following properties:
 in case of 'mode-gpio' property set:
 - output-value - (optional) this set the default output value of the GPIO
 - direction    - (optional) this set the direction of the gpio
-- pull-str     - (optional) this set the pull strength of the pin
+- pull-strength        - (optional) this set the pull strength of the pin
 - pull-assign  - (optional) this set the pull assignement (up/down) of the pin
-- invert            - (optional) this input pin is inverted
+- invert       - (optional) this input pin is inverted
 
 Example:
 
 pin_usb_host_en0@0 {
-    gpio-offset = <0x80 8>;
-    pad-offset = <0x260>;
-    mode-gpio;
-    output-value = <1>;
-    direction = <PIN_OUTPUT>;
+       gpio-offset = <0x80 8>;
+       pad-offset = <0x260>;
+       mode-gpio;
+       output-value = <1>;
+       direction = <PIN_OUTPUT>;
 };

diff --git a/drivers/Makefile b/drivers/Makefile
index f6295d285ece6a41cf4ae16a8945ade1d51a57a0..db5317c9c7cb07141f7ee750fdcb62b3ec52aa45 100644 (file)
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM)      += ram/
 
 ifdef CONFIG_SPL_BUILD
 
+obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 6ec52a9114b468ced0fffc0f70b7aea2bf29f9b5..6056fe5dfd027385601d746d7adca5926d7515e0 100644 (file)
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -563,7 +563,7 @@ int init_sata(int dev)
        struct ahci_probe_ent *probe_ent = NULL;
 
 #if defined(CONFIG_MX6)
-       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+       if (!is_mx6dq() && !is_mx6dqp())
                return 1;
 #endif
        if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {

diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
index dc6c064b4e3f030fb91fe3a684582664a066a2b5..3817fb3e47bf84664e399d6788490d69c902efab 100644 (file)
--- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
+++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
@@ -32,6 +32,7 @@ U_BOOT_DRIVER(mod_exp_sw) = {
        .name   = "mod_exp_sw",
        .id     = UCLASS_MOD_EXP,
        .ops    = &mod_exp_ops_sw,
+       .flags  = DM_FLAG_PRE_RELOC,
 };
 
 U_BOOT_DEVICE(mod_exp_sw) = {

diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 75a32ee8156f105f0454e24aec5ffe987e292935..8e52e3dad0af181e0df608466134ea3ba0660bef 100644 (file)
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -59,6 +59,11 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
 {
        struct at91_port *at91_port = at91_pio_get_port(port);
 
+#if defined(CPU_HAS_PIO3)
+       if (use_pullup)
+               at91_set_pio_pulldown(port, pin, 0);
+#endif
+
        if (at91_port && (pin < GPIO_PER_BANK))
                at91_set_port_pullup(at91_port, pin, use_pullup);
 
@@ -305,10 +310,10 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
 
        if (at91_port && (pin < GPIO_PER_BANK)) {
                mask = 1 << pin;
-               writel(mask, &at91_port->pudr);
-               if (is_on)
+               if (is_on) {
+                       at91_set_pio_pullup(port, pin, 0);
                        writel(mask, &at91_port->ppder);
-               else
+               } else
                        writel(mask, &at91_port->ppddr);
        }
 

diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 81ce446e1a162d1e2c624e657623b1fc96714963..8b50900f9fc262b56cde4fd3c9843964c3abe256 100644 (file)
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -9,7 +9,6 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev)
        struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
        struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
        struct broadwell_bank_priv *priv = dev_get_priv(dev);
-       struct udevice *pinctrl;
-       int ret;
-
-       /* Set up pin control if available */
-       ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
-       debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
        uc_priv->gpio_count = GPIO_PER_BANK;
        uc_priv->bank_name = plat->bank_name;

diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b7e379ab97984cbcffd1c4e9bb87350510f69151..fd6181fa5a733f4bc76856b621bd6d1ce1e897d7 100644 (file)
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,7 +32,6 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -113,10 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev)
        struct ich6_bank_platdata *plat = dev_get_platdata(dev);
        struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
        struct ich6_bank_priv *bank = dev_get_priv(dev);
-       struct udevice *pinctrl;
-
-       /* Set up pin control if available */
-       syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
 
        uc_priv->gpio_count = GPIO_PER_BANK;
        uc_priv->bank_name = plat->bank_name;

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8fa43b270de0253fe74036f013efd9125d..16b1aba32aaca5437cba1a25084dfefe3d4423d1 100644 (file)
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa2108248e0ea32f64e0ee34c9ef2fdf15104..f3402089a8ab7367f53e54c04587513bce013913 100644 (file)
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT       2
 #define VF610_I2C_REGSHIFT     0
+
+#define I2C_EARLY_INIT_INDEX           0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE      CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE      0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -659,6 +667,25 @@ void bus_i2c_init(int index, int speed, int unused,
        bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
 }
 
+/*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+       ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+       bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+                                       & I2C_QUIRK_FLAG ? true : false;
+       int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+       /* Set I2C divider value */
+       writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+       /* Reset module */
+       writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+       writeb(0, base + (I2SR << reg_shift));
+       /* Enable I2C */
+       writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
 /*
  * Init I2C Bus
  */

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 65ff8158e59b137d6592a48adcbed7dd5598aef7..38344e8090ed6f084c0d06e497ab84ef0782f295 100644 (file)
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -95,9 +95,9 @@ u32 fuse_bank_physical(int index)
 {
        u32 phy_index;
 
-       if (is_cpu_type(MXC_CPU_MX6SL)) {
+       if (is_mx6sl()) {
                phy_index = index;
-       } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+       } else if (is_mx6ul()) {
                if (index >= 6)
                        phy_index = fuse_bank_physical(5) + (index - 6) + 3;
                else

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 57ad9754f56a1af12f63576f190bf8a153ac88c3..b7b4f14145ea2f06139a677aae79f277c095a4d1 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -208,7 +208,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        int timeout;
        struct fsl_esdhc_priv *priv = mmc->priv;
        struct fsl_esdhc *regs = priv->esdhc_regs;
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
        dma_addr_t addr;
 #endif
        uint wml_value;
@@ -221,7 +221,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
                addr = virt_to_phys((void *)(data->dest));
                if (upper_32_bits(addr))
                        printf("Error found for upper 32 bits\n");
@@ -247,7 +247,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
                                        wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
                addr = virt_to_phys((void *)(data->src));
                if (upper_32_bits(addr))
                        printf("Error found for upper 32 bits\n");
@@ -312,7 +312,7 @@ static void check_and_invalidate_dcache_range
        unsigned end = 0;
        unsigned size = roundup(ARCH_DMA_MINALIGN,
                                data->blocks*data->blocksize);
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
        dma_addr_t addr;
 
        addr = virt_to_phys((void *)(data->dest));

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 75e830724c727bf11b3069d7ab2363e46db823e8..ad5ded3a5618d7fafb222eb219edf9a0cdd8e13f 100644 (file)
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -24,9 +24,9 @@
 
 /* Register access macros */
 #define ecc_readl(add, reg)                            \
-       readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+       readl(add + ATMEL_ECC_##reg)
 #define ecc_writel(add, reg, value)                    \
-       writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+       writel((value), add + ATMEL_ECC_##reg)
 
 #include "atmel_nand_ecc.h"    /* Hardware ECC registers */
 
@@ -1156,6 +1156,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
        nand->ecc.hwctl = atmel_nand_hwctl;
        nand->ecc.read_page = atmel_nand_read_page;
        nand->ecc.bytes = 4;
+       nand->ecc.strength = 4;
 
        if (nand->ecc.mode == NAND_ECC_HW) {
                /* ECC is calculated for the whole page (1 step) */

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7be1f86bc2b3d3bc795b92bcb6ac54c9475cef17..c90a3a7bd2cb596f5bd5d7ea75a5454faa12418c 100644 (file)
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
        int max_ecc_strength_supported;
 
        /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
+       if (is_mx6sx() || is_mx7())
                max_ecc_strength_supported = 62;
        else
                max_ecc_strength_supported = 40;

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3340dd256f6ed1db06f876305092eb9447a6cf1b..360f8e44d1017d9538a25496975727a645b8f6cc 100644 (file)
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -566,7 +566,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 
 
        /* Do not access reserved register for i.MX6UL */
-       if (!is_cpu_type(MXC_CPU_MX6UL)) {
+       if (!is_mx6ul()) {
                /* clear MIB RAM */
                for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
                        writel(0, i);

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 4bf8fa45d7a5e70b53e789f2133d39f3ebcd0b24..0835fdc306088e097e6b2509f8b0ddb83b1f76ff 100644 (file)
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
 
 /*
  * The u-boot networking stack is a little weird.  It seems like the
@@ -28,7 +29,9 @@
  */
 
 #include <net.h>
+#ifndef CONFIG_DM_ETH
 #include <netdev.h>
+#endif
 #include <malloc.h>
 #include <miiphy.h>
 
@@ -84,6 +87,8 @@ struct macb_device {
        unsigned int            rx_tail;
        unsigned int            tx_head;
        unsigned int            tx_tail;
+       unsigned int            next_rx_tail;
+       bool                    wrapped;
 
        void                    *rx_buffer;
        void                    *tx_buffer;
@@ -98,11 +103,15 @@ struct macb_device {
        unsigned long           dummy_desc_dma;
 
        const struct device     *dev;
+#ifndef CONFIG_DM_ETH
        struct eth_device       netdev;
+#endif
        unsigned short          phy_addr;
        struct mii_dev          *bus;
 };
+#ifndef CONFIG_DM_ETH
 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
+#endif
 
 static int macb_is_gem(struct macb_device *macb)
 {
@@ -192,8 +201,13 @@ void __weak arch_get_mdio_control(const char *name)
 
 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
 {
+#ifdef CONFIG_DM_ETH
+       struct udevice *dev = eth_get_dev_by_name(devname);
+       struct macb_device *macb = dev_get_priv(dev);
+#else
        struct eth_device *dev = eth_get_dev_by_name(devname);
        struct macb_device *macb = to_macb(dev);
+#endif
 
        if (macb->phy_addr != phy_adr)
                return -1;
@@ -206,8 +220,13 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
 
 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
 {
+#ifdef CONFIG_DM_ETH
+       struct udevice *dev = eth_get_dev_by_name(devname);
+       struct macb_device *macb = dev_get_priv(dev);
+#else
        struct eth_device *dev = eth_get_dev_by_name(devname);
        struct macb_device *macb = to_macb(dev);
+#endif
 
        if (macb->phy_addr != phy_adr)
                return -1;
@@ -255,9 +274,9 @@ static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
 
 #if defined(CONFIG_CMD_NET)
 
-static int macb_send(struct eth_device *netdev, void *packet, int length)
+static int _macb_send(struct macb_device *macb, const char *name, void *packet,
+                     int length)
 {
-       struct macb_device *macb = to_macb(netdev);
        unsigned long paddr, ctrl;
        unsigned int tx_head = macb->tx_head;
        int i;
@@ -278,7 +297,7 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
        barrier();
        macb_flush_ring_desc(macb, TX);
        /* Do we need check paddr and length is dcache line aligned? */
-       flush_dcache_range(paddr, paddr + length);
+       flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
        macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
 
        /*
@@ -298,12 +317,11 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
 
        if (i <= MACB_TX_TIMEOUT) {
                if (ctrl & TXBUF_UNDERRUN)
-                       printf("%s: TX underrun\n", netdev->name);
+                       printf("%s: TX underrun\n", name);
                if (ctrl & TXBUF_EXHAUSTED)
-                       printf("%s: TX buffers exhausted in mid frame\n",
-                              netdev->name);
+                       printf("%s: TX buffers exhausted in mid frame\n", name);
        } else {
-               printf("%s: TX timeout\n", netdev->name);
+               printf("%s: TX timeout\n", name);
        }
 
        /* No one cares anyway */
@@ -335,26 +353,25 @@ static void reclaim_rx_buffers(struct macb_device *macb,
        macb->rx_tail = new_tail;
 }
 
-static int macb_recv(struct eth_device *netdev)
+static int _macb_recv(struct macb_device *macb, uchar **packetp)
 {
-       struct macb_device *macb = to_macb(netdev);
-       unsigned int rx_tail = macb->rx_tail;
+       unsigned int next_rx_tail = macb->next_rx_tail;
        void *buffer;
        int length;
-       int wrapped = 0;
        u32 status;
 
+       macb->wrapped = false;
        for (;;) {
                macb_invalidate_ring_desc(macb, RX);
 
-               if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
-                       return -1;
+               if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+                       return -EAGAIN;
 
-               status = macb->rx_ring[rx_tail].ctrl;
+               status = macb->rx_ring[next_rx_tail].ctrl;
                if (status & RXBUF_FRAME_START) {
-                       if (rx_tail != macb->rx_tail)
-                               reclaim_rx_buffers(macb, rx_tail);
-                       wrapped = 0;
+                       if (next_rx_tail != macb->rx_tail)
+                               reclaim_rx_buffers(macb, next_rx_tail);
+                       macb->wrapped = false;
                }
 
                if (status & RXBUF_FRAME_END) {
@@ -362,7 +379,7 @@ static int macb_recv(struct eth_device *netdev)
                        length = status & RXBUF_FRMLEN_MASK;
 
                        macb_invalidate_rx_buffer(macb);
-                       if (wrapped) {
+                       if (macb->wrapped) {
                                unsigned int headlen, taillen;
 
                                headlen = 128 * (MACB_RX_RING_SIZE
@@ -372,34 +389,33 @@ static int macb_recv(struct eth_device *netdev)
                                       buffer, headlen);
                                memcpy((void *)net_rx_packets[0] + headlen,
                                       macb->rx_buffer, taillen);
-                               buffer = (void *)net_rx_packets[0];
+                               *packetp = (void *)net_rx_packets[0];
+                       } else {
+                               *packetp = buffer;
                        }
 
-                       net_process_received_packet(buffer, length);
-                       if (++rx_tail >= MACB_RX_RING_SIZE)
-                               rx_tail = 0;
-                       reclaim_rx_buffers(macb, rx_tail);
+                       if (++next_rx_tail >= MACB_RX_RING_SIZE)
+                               next_rx_tail = 0;
+                       macb->next_rx_tail = next_rx_tail;
+                       return length;
                } else {
-                       if (++rx_tail >= MACB_RX_RING_SIZE) {
-                               wrapped = 1;
-                               rx_tail = 0;
+                       if (++next_rx_tail >= MACB_RX_RING_SIZE) {
+                               macb->wrapped = true;
+                               next_rx_tail = 0;
                        }
                }
                barrier();
        }
-
-       return 0;
 }
 
-static void macb_phy_reset(struct macb_device *macb)
+static void macb_phy_reset(struct macb_device *macb, const char *name)
 {
-       struct eth_device *netdev = &macb->netdev;
        int i;
        u16 status, adv;
 
        adv = ADVERTISE_CSMA | ADVERTISE_ALL;
        macb_mdio_write(macb, MII_ADVERTISE, adv);
-       printf("%s: Starting autonegotiation...\n", netdev->name);
+       printf("%s: Starting autonegotiation...\n", name);
        macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
                                         | BMCR_ANRESTART));
 
@@ -411,10 +427,10 @@ static void macb_phy_reset(struct macb_device *macb)
        }
 
        if (status & BMSR_ANEGCOMPLETE)
-               printf("%s: Autonegotiation complete\n", netdev->name);
+               printf("%s: Autonegotiation complete\n", name);
        else
                printf("%s: Autonegotiation timed out (status=0x%04x)\n",
-                      netdev->name, status);
+                      name, status);
 }
 
 #ifdef CONFIG_MACB_SEARCH_PHY
@@ -441,9 +457,8 @@ static int macb_phy_find(struct macb_device *macb)
 #endif /* CONFIG_MACB_SEARCH_PHY */
 
 
-static int macb_phy_init(struct macb_device *macb)
+static int macb_phy_init(struct macb_device *macb, const char *name)
 {
-       struct eth_device *netdev = &macb->netdev;
 #ifdef CONFIG_PHYLIB
        struct phy_device *phydev;
 #endif
@@ -452,7 +467,7 @@ static int macb_phy_init(struct macb_device *macb)
        int media, speed, duplex;
        int i;
 
-       arch_get_mdio_control(netdev->name);
+       arch_get_mdio_control(name);
 #ifdef CONFIG_MACB_SEARCH_PHY
        /* Auto-detect phy_addr */
        if (!macb_phy_find(macb))
@@ -462,13 +477,13 @@ static int macb_phy_init(struct macb_device *macb)
        /* Check if the PHY is up to snuff... */
        phy_id = macb_mdio_read(macb, MII_PHYSID1);
        if (phy_id == 0xffff) {
-               printf("%s: No PHY present\n", netdev->name);
+               printf("%s: No PHY present\n", name);
                return 0;
        }
 
 #ifdef CONFIG_PHYLIB
        /* need to consider other phy interface mode */
-       phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
+       phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
                             PHY_INTERFACE_MODE_RGMII);
        if (!phydev) {
                printf("phy_connect failed\n");
@@ -481,7 +496,7 @@ static int macb_phy_init(struct macb_device *macb)
        status = macb_mdio_read(macb, MII_BMSR);
        if (!(status & BMSR_LSTATUS)) {
                /* Try to re-negotiate if we don't have link already. */
-               macb_phy_reset(macb);
+               macb_phy_reset(macb, name);
 
                for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
                        status = macb_mdio_read(macb, MII_BMSR);
@@ -493,7 +508,7 @@ static int macb_phy_init(struct macb_device *macb)
 
        if (!(status & BMSR_LSTATUS)) {
                printf("%s: link down (status: 0x%04x)\n",
-                      netdev->name, status);
+                      name, status);
                return 0;
        }
 
@@ -505,7 +520,7 @@ static int macb_phy_init(struct macb_device *macb)
                        duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
 
                        printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
-                              netdev->name,
+                              name,
                               duplex ? "full" : "half",
                               lpa);
 
@@ -530,7 +545,7 @@ static int macb_phy_init(struct macb_device *macb)
                 ? 1 : 0);
        duplex = (media & ADVERTISE_FULL) ? 1 : 0;
        printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
-              netdev->name,
+              name,
               speed ? "100" : "10",
               duplex ? "full" : "half",
               lpa);
@@ -570,9 +585,8 @@ static int gmac_init_multi_queues(struct macb_device *macb)
        return 0;
 }
 
-static int macb_init(struct eth_device *netdev, bd_t *bd)
+static int _macb_init(struct macb_device *macb, const char *name)
 {
-       struct macb_device *macb = to_macb(netdev);
        unsigned long paddr;
        int i;
 
@@ -605,6 +619,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
        macb->rx_tail = 0;
        macb->tx_head = 0;
        macb->tx_tail = 0;
+       macb->next_rx_tail = 0;
 
        macb_writel(macb, RBQP, macb->rx_ring_dma);
        macb_writel(macb, TBQP, macb->tx_ring_dma);
@@ -641,7 +656,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 #endif /* CONFIG_RMII */
        }
 
-       if (!macb_phy_init(macb))
+       if (!macb_phy_init(macb, name))
                return -1;
 
        /* Enable TX and RX */
@@ -650,9 +665,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
        return 0;
 }
 
-static void macb_halt(struct eth_device *netdev)
+static void _macb_halt(struct macb_device *macb)
 {
-       struct macb_device *macb = to_macb(netdev);
        u32 ncr, tsr;
 
        /* Halt the controller and wait for any ongoing transmission to end. */
@@ -668,17 +682,16 @@ static void macb_halt(struct eth_device *netdev)
        macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
 }
 
-static int macb_write_hwaddr(struct eth_device *dev)
+static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
 {
-       struct macb_device *macb = to_macb(dev);
        u32 hwaddr_bottom;
        u16 hwaddr_top;
 
        /* set hardware address */
-       hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
-                       dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
+       hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
+                       enetaddr[2] << 16 | enetaddr[3] << 24;
        macb_writel(macb, SA1B, hwaddr_bottom);
-       hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
+       hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
        macb_writel(macb, SA1T, hwaddr_top);
        return 0;
 }
@@ -739,11 +752,87 @@ static u32 macb_dbw(struct macb_device *macb)
        }
 }
 
+static void _macb_eth_initialize(struct macb_device *macb)
+{
+       int id = 0;     /* This is not used by functions we call */
+       u32 ncfgr;
+
+       /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
+       macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
+                                            &macb->rx_buffer_dma);
+       macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
+                                          &macb->rx_ring_dma);
+       macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
+                                          &macb->tx_ring_dma);
+       macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
+                                          &macb->dummy_desc_dma);
+
+       /*
+        * Do some basic initialization so that we at least can talk
+        * to the PHY
+        */
+       if (macb_is_gem(macb)) {
+               ncfgr = gem_mdc_clk_div(id, macb);
+               ncfgr |= macb_dbw(macb);
+       } else {
+               ncfgr = macb_mdc_clk_div(id, macb);
+       }
+
+       macb_writel(macb, NCFGR, ncfgr);
+}
+
+#ifndef CONFIG_DM_ETH
+static int macb_send(struct eth_device *netdev, void *packet, int length)
+{
+       struct macb_device *macb = to_macb(netdev);
+
+       return _macb_send(macb, netdev->name, packet, length);
+}
+
+static int macb_recv(struct eth_device *netdev)
+{
+       struct macb_device *macb = to_macb(netdev);
+       uchar *packet;
+       int length;
+
+       macb->wrapped = false;
+       for (;;) {
+               macb->next_rx_tail = macb->rx_tail;
+               length = _macb_recv(macb, &packet);
+               if (length >= 0) {
+                       net_process_received_packet(packet, length);
+                       reclaim_rx_buffers(macb, macb->next_rx_tail);
+               } else if (length < 0) {
+                       return length;
+               }
+       }
+}
+
+static int macb_init(struct eth_device *netdev, bd_t *bd)
+{
+       struct macb_device *macb = to_macb(netdev);
+
+       return _macb_init(macb, netdev->name);
+}
+
+static void macb_halt(struct eth_device *netdev)
+{
+       struct macb_device *macb = to_macb(netdev);
+
+       return _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct eth_device *netdev)
+{
+       struct macb_device *macb = to_macb(netdev);
+
+       return _macb_write_hwaddr(macb, netdev->enetaddr);
+}
+
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 {
        struct macb_device *macb;
        struct eth_device *netdev;
-       u32 ncfgr;
 
        macb = malloc(sizeof(struct macb_device));
        if (!macb) {
@@ -754,17 +843,6 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 
        netdev = &macb->netdev;
 
-       macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
-                                            &macb->rx_buffer_dma);
-       macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
-                                          &macb->rx_ring_dma);
-       macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
-                                          &macb->tx_ring_dma);
-       macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
-                                          &macb->dummy_desc_dma);
-
-       /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
-
        macb->regs = regs;
        macb->phy_addr = phy_addr;
 
@@ -779,18 +857,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
        netdev->recv = macb_recv;
        netdev->write_hwaddr = macb_write_hwaddr;
 
-       /*
-        * Do some basic initialization so that we at least can talk
-        * to the PHY
-        */
-       if (macb_is_gem(macb)) {
-               ncfgr = gem_mdc_clk_div(id, macb);
-               ncfgr |= macb_dbw(macb);
-       } else {
-               ncfgr = macb_mdc_clk_div(id, macb);
-       }
-
-       macb_writel(macb, NCFGR, ncfgr);
+       _macb_eth_initialize(macb);
 
        eth_register(netdev);
 
@@ -800,5 +867,106 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 #endif
        return 0;
 }
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_DM_ETH
+
+static int macb_start(struct udevice *dev)
+{
+       struct macb_device *macb = dev_get_priv(dev);
+
+       return _macb_init(macb, dev->name);
+}
+
+static int macb_send(struct udevice *dev, void *packet, int length)
+{
+       struct macb_device *macb = dev_get_priv(dev);
+
+       return _macb_send(macb, dev->name, packet, length);
+}
+
+static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+       struct macb_device *macb = dev_get_priv(dev);
+
+       macb->next_rx_tail = macb->rx_tail;
+       macb->wrapped = false;
+
+       return _macb_recv(macb, packetp);
+}
+
+static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+       struct macb_device *macb = dev_get_priv(dev);
+
+       reclaim_rx_buffers(macb, macb->next_rx_tail);
+
+       return 0;
+}
+
+static void macb_stop(struct udevice *dev)
+{
+       struct macb_device *macb = dev_get_priv(dev);
+
+       _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct udevice *dev)
+{
+       struct eth_pdata *plat = dev_get_platdata(dev);
+       struct macb_device *macb = dev_get_priv(dev);
+
+       return _macb_write_hwaddr(macb, plat->enetaddr);
+}
+
+static const struct eth_ops macb_eth_ops = {
+       .start  = macb_start,
+       .send   = macb_send,
+       .recv   = macb_recv,
+       .stop   = macb_stop,
+       .free_pkt       = macb_free_pkt,
+       .write_hwaddr   = macb_write_hwaddr,
+};
+
+static int macb_eth_probe(struct udevice *dev)
+{
+       struct eth_pdata *pdata = dev_get_platdata(dev);
+       struct macb_device *macb = dev_get_priv(dev);
+
+       macb->regs = (void *)pdata->iobase;
+
+       _macb_eth_initialize(macb);
+#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
+       miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write);
+       macb->bus = miiphy_get_dev_by_name(dev->name);
+#endif
+
+       return 0;
+}
+
+static int macb_eth_ofdata_to_platdata(struct udevice *dev)
+{
+       struct eth_pdata *pdata = dev_get_platdata(dev);
+
+       pdata->iobase = dev_get_addr(dev);
+       return 0;
+}
+
+static const struct udevice_id macb_eth_ids[] = {
+       { .compatible = "cdns,macb" },
+       { }
+};
+
+U_BOOT_DRIVER(eth_macb) = {
+       .name   = "eth_macb",
+       .id     = UCLASS_ETH,
+       .of_match = macb_eth_ids,
+       .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
+       .probe  = macb_eth_probe,
+       .ops    = &macb_eth_ops,
+       .priv_auto_alloc_size = sizeof(struct macb_device),
+       .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif
 
 #endif

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e1e28ded30aa905dea995c799e9a8faa22739257..92cbea59135abeabee0e7133f1bba417a9aae8cc 100644 (file)
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
+obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 4fe992bf2bf38dc9d53359dac9212efdf1246e0d..e450135c75745e7231fd83bf5f35bd4d98bb7591 100644 (file)
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -191,16 +191,35 @@ static int atmel_serial_probe(struct udevice *dev)
 {
        struct atmel_serial_platdata *plat = dev->platdata;
        struct atmel_serial_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+       fdt_addr_t addr_base;
 
+       addr_base = dev_get_addr(dev);
+       if (addr_base == FDT_ADDR_T_NONE)
+               return -ENODEV;
+
+       plat->base_addr = (uint32_t)addr_base;
+#endif
        priv->usart = (atmel_usart3_t *)plat->base_addr;
        atmel_serial_init_internal(priv->usart);
 
        return 0;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id atmel_serial_ids[] = {
+       { .compatible = "atmel,at91sam9260-usart" },
+       { }
+};
+#endif
+
 U_BOOT_DRIVER(serial_atmel) = {
        .name   = "serial_atmel",
        .id     = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+       .of_match = atmel_serial_ids,
+       .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
+#endif
        .probe = atmel_serial_probe,
        .ops    = &atmel_serial_ops,
        .flags = DM_FLAG_PRE_RELOC,

diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c
new file mode 100644 (file)
index 0000000..fbb3959
--- /dev/null
+++ b/drivers/serial/serial_linflexuart.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define US1_TDRE            (1 << 7)
+#define US1_RDRF            (1 << 5)
+#define UC2_TE              (1 << 3)
+#define LINCR1_INIT         (1 << 0)
+#define LINCR1_MME          (1 << 4)
+#define LINCR1_BF           (1 << 7)
+#define LINSR_LINS_INITMODE (0x00001000)
+#define LINSR_LINS_MASK     (0x0000F000)
+#define UARTCR_UART         (1 << 0)
+#define UARTCR_WL0          (1 << 1)
+#define UARTCR_PCE          (1 << 2)
+#define UARTCR_PC0          (1 << 3)
+#define UARTCR_TXEN         (1 << 4)
+#define UARTCR_RXEN         (1 << 5)
+#define UARTCR_PC1          (1 << 6)
+#define UARTSR_DTF          (1 << 1)
+#define UARTSR_DRF          (1 << 2)
+#define UARTSR_RMB          (1 << 9)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_SERIAL
+#error "The linflex serial driver does not have non-DM support."
+#endif
+
+static void _linflex_serial_setbrg(struct linflex_fsl *base, int baudrate)
+{
+       u32 clk = mxc_get_clock(MXC_UART_CLK);
+       u32 ibr, fbr;
+
+       if (!baudrate)
+               baudrate = CONFIG_BAUDRATE;
+
+       ibr = (u32) (clk / (16 * gd->baudrate));
+       fbr = (u32) (clk % (16 * gd->baudrate)) * 16;
+
+       __raw_writel(ibr, &base->linibrr);
+       __raw_writel(fbr, &base->linfbrr);
+}
+
+static int _linflex_serial_getc(struct linflex_fsl *base)
+{
+       char c;
+
+       if (!(__raw_readb(&base->uartsr) & UARTSR_DRF))
+               return -EAGAIN;
+
+       if (!(__raw_readl(&base->uartsr) & UARTSR_RMB))
+               return -EAGAIN;
+
+       c = __raw_readl(&base->bdrm);
+       __raw_writeb((__raw_readb(&base->uartsr) | (UARTSR_DRF | UARTSR_RMB)),
+                    &base->uartsr);
+       return c;
+}
+
+static int _linflex_serial_putc(struct linflex_fsl *base, const char c)
+{
+       __raw_writeb(c, &base->bdrl);
+
+
+       if (!(__raw_readb(&base->uartsr) & UARTSR_DTF))
+               return -EAGAIN;
+
+       __raw_writeb((__raw_readb(&base->uartsr) | UARTSR_DTF), &base->uartsr);
+
+       return 0;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int _linflex_serial_init(struct linflex_fsl *base)
+{
+       volatile u32 ctrl;
+
+       /* set the Linflex in master mode amd activate by-pass filter */
+       ctrl = LINCR1_BF | LINCR1_MME;
+       __raw_writel(ctrl, &base->lincr1);
+
+       /* init mode */
+       ctrl |= LINCR1_INIT;
+       __raw_writel(ctrl, &base->lincr1);
+
+       /* waiting for init mode entry - TODO: add a timeout */
+       while ((__raw_readl(&base->linsr) & LINSR_LINS_MASK) !=
+              LINSR_LINS_INITMODE);
+
+       /* set UART bit to allow writing other bits */
+       __raw_writel(UARTCR_UART, &base->uartcr);
+
+       /* provide data bits, parity, stop bit, etc */
+       serial_setbrg();
+
+       /* 8 bit data, no parity, Tx and Rx enabled, UART mode */
+       __raw_writel(UARTCR_PC1 | UARTCR_RXEN | UARTCR_TXEN | UARTCR_PC0
+                    | UARTCR_WL0 | UARTCR_UART, &base->uartcr);
+
+       ctrl = __raw_readl(&base->lincr1);
+       ctrl &= ~LINCR1_INIT;
+       __raw_writel(ctrl, &base->lincr1);      /* end init mode */
+
+       return 0;
+}
+
+struct linflex_serial_platdata {
+       struct linflex_fsl *base_addr;
+       u8 port_id; /* do we need this? */
+};
+
+struct linflex_serial_priv {
+       struct linflex_fsl *lfuart;
+};
+
+int linflex_serial_setbrg(struct udevice *dev, int baudrate)
+{
+       struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+       _linflex_serial_setbrg(priv->lfuart, baudrate);
+
+       return 0;
+}
+
+static int linflex_serial_getc(struct udevice *dev)
+{
+       struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+       return _linflex_serial_getc(priv->lfuart);
+}
+
+static int linflex_serial_putc(struct udevice *dev, const char ch)
+{
+
+       struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+       return _linflex_serial_putc(priv->lfuart, ch);
+}
+
+static int linflex_serial_pending(struct udevice *dev, bool input)
+{
+       struct linflex_serial_priv *priv = dev_get_priv(dev);
+       uint32_t uartsr = __raw_readl(&priv->lfuart->uartsr);
+
+       if (input)
+               return ((uartsr & UARTSR_DRF) && (uartsr & UARTSR_RMB)) ? 1 : 0;
+       else
+               return uartsr & UARTSR_DTF ? 0 : 1;
+}
+
+static void linflex_serial_init_internal(struct linflex_fsl *lfuart)
+{
+       _linflex_serial_init(lfuart);
+       _linflex_serial_setbrg(lfuart, CONFIG_BAUDRATE);
+       return;
+}
+
+static int linflex_serial_probe(struct udevice *dev)
+{
+       struct linflex_serial_platdata *plat = dev->platdata;
+       struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+       priv->lfuart = (struct linflex_fsl *)plat->base_addr;
+       linflex_serial_init_internal(priv->lfuart);
+
+       return 0;
+}
+
+static const struct dm_serial_ops linflex_serial_ops = {
+       .putc = linflex_serial_putc,
+       .pending = linflex_serial_pending,
+       .getc = linflex_serial_getc,
+       .setbrg = linflex_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_linflex) = {
+       .name   = "serial_linflex",
+       .id     = UCLASS_SERIAL,
+       .probe = linflex_serial_probe,
+       .ops    = &linflex_serial_ops,
+       .flags = DM_FLAG_PRE_RELOC,
+       .priv_auto_alloc_size   = sizeof(struct linflex_serial_priv),
+};
+
+#ifdef CONFIG_DEBUG_UART_LINFLEXUART
+
+#include <debug_uart.h>
+
+
+static inline void _debug_uart_init(void)
+{
+       struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+
+       linflex_serial_init_internal(base);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+       struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+
+       /* XXX: Is this OK? Should this use the non-DM version? */
+       _linflex_serial_putc(base, ch);
+}
+
+DEBUG_UART_FUNCS
+
+#endif /* CONFIG_DEBUG_UART_LINFLEXUART */

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b7fd8e53a2f62d6cd1f7aefa91f82e89c7fe5aea..aca385d5e59f69367fb62e5fca00e708a436b6bc 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -75,6 +75,14 @@ config ICH_SPI
          access the SPI NOR flash on platforms embedding this Intel
          ICH IP core.
 
+config PIC32_SPI
+       bool "Microchip PIC32 SPI driver"
+       depends on MACH_PIC32
+       help
+         Enable the Microchip PIC32 SPI driver. This driver can be used
+         to access the SPI NOR flash, MMC-over-SPI on platforms based on
+         Microchip PIC32 family devices.
+
 config ROCKCHIP_SPI
        bool "Rockchip SPI driver"
        help

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7fb2926e78135129939dbad3e789a8d8a0d67ed9..b1d9e2075eb2d1937a464db3b0137642c444a010 100644 (file)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o

diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c
new file mode 100644 (file)
index 0000000..25ca1f3
--- /dev/null
+++ b/drivers/spi/pic32_spi.c
@@ -0,0 +1,448 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Copyright (c) 2015, Microchip Technology Inc.
+ *      Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include <mach/pic32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 SPI controller registers */
+struct pic32_reg_spi {
+       struct pic32_reg_atomic ctrl;
+       struct pic32_reg_atomic status;
+       struct pic32_reg_atomic buf;
+       struct pic32_reg_atomic baud;
+       struct pic32_reg_atomic ctrl2;
+};
+
+/* Bit fields in SPI Control Register */
+#define PIC32_SPI_CTRL_MSTEN   BIT(5) /* Enable SPI Master */
+#define PIC32_SPI_CTRL_CKP     BIT(6) /* active low */
+#define PIC32_SPI_CTRL_CKE     BIT(8) /* Tx on falling edge */
+#define PIC32_SPI_CTRL_SMP     BIT(9) /* Rx at middle or end of tx */
+#define PIC32_SPI_CTRL_BPW_MASK        0x03   /* Bits per word */
+#define  PIC32_SPI_CTRL_BPW_8          0x0
+#define  PIC32_SPI_CTRL_BPW_16         0x1
+#define  PIC32_SPI_CTRL_BPW_32         0x2
+#define PIC32_SPI_CTRL_BPW_SHIFT       10
+#define PIC32_SPI_CTRL_ON      BIT(15) /* Macro enable */
+#define PIC32_SPI_CTRL_ENHBUF  BIT(16) /* Enable enhanced buffering */
+#define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
+#define PIC32_SPI_CTRL_MSSEN   BIT(28) /* SPI macro will drive SS */
+#define PIC32_SPI_CTRL_FRMEN   BIT(31) /* Enable framing mode */
+
+/* Bit fields in SPI Status Register */
+#define PIC32_SPI_STAT_RX_OV           BIT(6) /* err, s/w needs to clear */
+#define PIC32_SPI_STAT_TF_LVL_MASK     0x1f
+#define PIC32_SPI_STAT_TF_LVL_SHIFT    16
+#define PIC32_SPI_STAT_RF_LVL_MASK     0x1f
+#define PIC32_SPI_STAT_RF_LVL_SHIFT    24
+
+/* Bit fields in SPI Baud Register */
+#define PIC32_SPI_BAUD_MASK    0x1ff
+
+struct pic32_spi_priv {
+       struct pic32_reg_spi    *regs;
+       u32                     fifo_depth; /* FIFO depth in bytes */
+       u32                     fifo_n_word; /* FIFO depth in words */
+       struct gpio_desc        cs_gpio;
+
+       /* Current SPI slave specific */
+       ulong                   clk_rate;
+       u32                     speed_hz; /* spi-clk rate */
+       int                     mode;
+
+       /* Current message/transfer state */
+       const void              *tx;
+       const void              *tx_end;
+       const void              *rx;
+       const void              *rx_end;
+       u32                     len;
+
+       /* SPI FiFo accessor */
+       void (*rx_fifo)(struct pic32_spi_priv *);
+       void (*tx_fifo)(struct pic32_spi_priv *);
+};
+
+static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
+{
+       writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
+}
+
+static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
+{
+       writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
+}
+
+static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
+{
+       u32 sr = readl(&priv->regs->status.raw);
+
+       return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
+}
+
+static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
+{
+       u32 sr = readl(&priv->regs->status.raw);
+
+       return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
+}
+
+/* Return the max entries we can fill into tx fifo */
+static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+       u32 tx_left, tx_room, rxtx_gap;
+
+       tx_left = (priv->tx_end - priv->tx) / n_bytes;
+       tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
+
+       rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
+       rxtx_gap /= n_bytes;
+       return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
+}
+
+/* Return the max entries we should read out of rx fifo */
+static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+       u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
+
+       return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
+}
+
+#define BUILD_SPI_FIFO_RW(__name, __type, __bwl)               \
+static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
+{                                                              \
+       __type val;                                             \
+       u32 mx = pic32_rx_max(priv, sizeof(__type));            \
+                                                               \
+       for (; mx; mx--) {                                      \
+               val = read##__bwl(&priv->regs->buf.raw);        \
+               if (priv->rx_end - priv->len)                   \
+                       *(__type *)(priv->rx) = val;            \
+               priv->rx += sizeof(__type);                     \
+       }                                                       \
+}                                                              \
+                                                               \
+static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
+{                                                              \
+       __type val;                                             \
+       u32 mx = pic32_tx_max(priv, sizeof(__type));            \
+                                                               \
+       for (; mx ; mx--) {                                     \
+               val = (__type) ~0U;                             \
+               if (priv->tx_end - priv->len)                   \
+                       val =  *(__type *)(priv->tx);           \
+               write##__bwl(val, &priv->regs->buf.raw);        \
+               priv->tx += sizeof(__type);                     \
+       }                                                       \
+}
+BUILD_SPI_FIFO_RW(byte, u8, b);
+BUILD_SPI_FIFO_RW(word, u16, w);
+BUILD_SPI_FIFO_RW(dword, u32, l);
+
+static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
+                                  unsigned int wordlen)
+{
+       u32 bits_per_word;
+       u32 val;
+
+       switch (wordlen) {
+       case 8:
+               priv->rx_fifo = pic32_spi_rx_byte;
+               priv->tx_fifo = pic32_spi_tx_byte;
+               bits_per_word = PIC32_SPI_CTRL_BPW_8;
+               break;
+       case 16:
+               priv->rx_fifo = pic32_spi_rx_word;
+               priv->tx_fifo = pic32_spi_tx_word;
+               bits_per_word = PIC32_SPI_CTRL_BPW_16;
+               break;
+       case 32:
+               priv->rx_fifo = pic32_spi_rx_dword;
+               priv->tx_fifo = pic32_spi_tx_dword;
+               bits_per_word = PIC32_SPI_CTRL_BPW_32;
+               break;
+       default:
+               printf("pic32-spi: unsupported wordlen\n");
+               return -EINVAL;
+       }
+
+       /* set bits-per-word */
+       val = readl(&priv->regs->ctrl.raw);
+       val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
+       val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
+       writel(val, &priv->regs->ctrl.raw);
+
+       /* calculate maximum number of words fifo can hold */
+       priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
+
+       return 0;
+}
+
+static int pic32_spi_claim_bus(struct udevice *slave)
+{
+       struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+       /* enable chip */
+       pic32_spi_enable(priv);
+
+       return 0;
+}
+
+static int pic32_spi_release_bus(struct udevice *slave)
+{
+       struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+       /* disable chip */
+       pic32_spi_disable(priv);
+
+       return 0;
+}
+
+static void spi_cs_activate(struct pic32_spi_priv *priv)
+{
+       if (!dm_gpio_is_valid(&priv->cs_gpio))
+               return;
+
+       dm_gpio_set_value(&priv->cs_gpio, 1);
+}
+
+static void spi_cs_deactivate(struct pic32_spi_priv *priv)
+{
+       if (!dm_gpio_is_valid(&priv->cs_gpio))
+               return;
+
+       dm_gpio_set_value(&priv->cs_gpio, 0);
+}
+
+static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
+                         const void *tx_buf, void *rx_buf,
+                         unsigned long flags)
+{
+       struct dm_spi_slave_platdata *slave_plat;
+       struct udevice *bus = slave->parent;
+       struct pic32_spi_priv *priv;
+       int len = bitlen / 8;
+       int ret = 0;
+       ulong tbase;
+
+       priv = dev_get_priv(bus);
+       slave_plat = dev_get_parent_platdata(slave);
+
+       debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
+             bus->seq, slave_plat->cs, flags);
+       debug("msg tx %p, rx %p submitted of %d byte(s)\n",
+             tx_buf, rx_buf, len);
+
+       /* assert cs */
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(priv);
+
+       /* set current transfer information */
+       priv->tx = tx_buf;
+       priv->rx = rx_buf;
+       priv->tx_end = priv->tx + len;
+       priv->rx_end = priv->rx + len;
+       priv->len = len;
+
+       /* transact by polling */
+       tbase = get_timer(0);
+       for (;;) {
+               priv->tx_fifo(priv);
+               priv->rx_fifo(priv);
+
+               /* received sufficient data */
+               if (priv->rx >= priv->rx_end) {
+                       ret = 0;
+                       break;
+               }
+
+               if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
+                       printf("pic32_spi: error, xfer timedout.\n");
+                       flags |= SPI_XFER_END;
+                       ret = -ETIMEDOUT;
+                       break;
+               }
+       }
+
+       /* deassert cs */
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(priv);
+
+       return ret;
+}
+
+static int pic32_spi_set_speed(struct udevice *bus, uint speed)
+{
+       struct pic32_spi_priv *priv = dev_get_priv(bus);
+       u32 div;
+
+       debug("%s: %s, speed %u\n", __func__, bus->name, speed);
+
+       /* div = [clk_in / (2 * spi_clk)] - 1 */
+       div = (priv->clk_rate / 2 / speed) - 1;
+       div &= PIC32_SPI_BAUD_MASK;
+       writel(div, &priv->regs->baud.raw);
+
+       priv->speed_hz = speed;
+
+       return 0;
+}
+
+static int pic32_spi_set_mode(struct udevice *bus, uint mode)
+{
+       struct pic32_spi_priv *priv = dev_get_priv(bus);
+       u32 val;
+
+       debug("%s: %s, mode %d\n", __func__, bus->name, mode);
+
+       /* set spi-clk mode */
+       val = readl(&priv->regs->ctrl.raw);
+       /* HIGH when idle */
+       if (mode & SPI_CPOL)
+               val |= PIC32_SPI_CTRL_CKP;
+       else
+               val &= ~PIC32_SPI_CTRL_CKP;
+
+       /* TX at idle-to-active clk transition */
+       if (mode & SPI_CPHA)
+               val &= ~PIC32_SPI_CTRL_CKE;
+       else
+               val |= PIC32_SPI_CTRL_CKE;
+
+       /* RX at end of tx */
+       val |= PIC32_SPI_CTRL_SMP;
+       writel(val, &priv->regs->ctrl.raw);
+
+       priv->mode = mode;
+
+       return 0;
+}
+
+static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
+{
+       struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+       return pic32_spi_set_word_size(priv, wordlen);
+}
+
+static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
+{
+       u32 val;
+
+       /* disable module */
+       pic32_spi_disable(priv);
+
+       val = readl(&priv->regs->ctrl);
+
+       /* enable enhanced fifo of 128bit deep */
+       val |= PIC32_SPI_CTRL_ENHBUF;
+       priv->fifo_depth = 16;
+
+       /* disable framing mode */
+       val &= ~PIC32_SPI_CTRL_FRMEN;
+
+       /* enable master mode */
+       val |= PIC32_SPI_CTRL_MSTEN;
+
+       /* select clk source */
+       val &= ~PIC32_SPI_CTRL_MCLKSEL;
+
+       /* set manual /CS mode */
+       val &= ~PIC32_SPI_CTRL_MSSEN;
+
+       writel(val, &priv->regs->ctrl);
+
+       /* clear rx overflow indicator */
+       writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
+}
+
+static int pic32_spi_probe(struct udevice *bus)
+{
+       struct pic32_spi_priv *priv = dev_get_priv(bus);
+       struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
+       struct udevice *clkdev;
+       fdt_addr_t addr;
+       fdt_size_t size;
+       int ret;
+
+       debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
+       addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->regs = ioremap(addr, size);
+       if (!priv->regs)
+               return -EINVAL;
+
+       dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+                                       "spi-max-frequency", 250000000);
+       /* get clock rate */
+       ret = clk_get_by_index(bus, 0, &clkdev);
+       if (ret < 0) {
+               printf("pic32-spi: error, clk not found\n");
+               return ret;
+       }
+       priv->clk_rate = clk_get_periph_rate(clkdev, ret);
+
+       /* initialize HW */
+       pic32_spi_hw_init(priv);
+
+       /* set word len */
+       pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
+
+       /* PIC32 SPI controller can automatically drive /CS during transfer
+        * depending on fifo fill-level. /CS will stay asserted as long as
+        * TX fifo is non-empty, else will be deasserted confirming completion
+        * of the ongoing transfer. To avoid this sort of error we will drive
+        * /CS manually by toggling cs-gpio pins.
+        */
+       ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
+                                        "cs-gpios", 0,
+                                        &priv->cs_gpio, GPIOD_IS_OUT);
+       if (ret) {
+               printf("pic32-spi: error, cs-gpios not found\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+static const struct dm_spi_ops pic32_spi_ops = {
+       .claim_bus      = pic32_spi_claim_bus,
+       .release_bus    = pic32_spi_release_bus,
+       .xfer           = pic32_spi_xfer,
+       .set_speed      = pic32_spi_set_speed,
+       .set_mode       = pic32_spi_set_mode,
+       .set_wordlen    = pic32_spi_set_wordlen,
+};
+
+static const struct udevice_id pic32_spi_ids[] = {
+       { .compatible = "microchip,pic32mzda-spi" },
+       { }
+};
+
+U_BOOT_DRIVER(pic32_spi) = {
+       .name           = "pic32_spi",
+       .id             = UCLASS_SPI,
+       .of_match       = pic32_spi_ids,
+       .ops            = &pic32_spi_ops,
+       .priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
+       .probe          = pic32_spi_probe,
+};

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 3081afca0e28befb2ccb50ee41dfc238de18a8ab..c016a0bb544dd82a86a6a6dfe780d58c5bcc426f 100644 (file)
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev)
 int musb_usb_remove(struct udevice *dev)
 {
        struct musb_host_data *host = dev_get_priv(dev);
+       struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
        musb_stop(host->host);
 
+       sunxi_usb_phy_exit(0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+       clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+       clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+
        return 0;
 }
 

diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index d43d8a59d3b78606ea242b0334dac690d511e0b4..39cd7caff16dbf25c3ff9e1f89bb95b032a71bf8 100644 (file)
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -7,6 +7,10 @@
  */
 
 #include <common.h>
+#include <atmel_lcd.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <video.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -14,6 +18,21 @@
 #include <bmp_layout.h>
 #include <atmel_lcdc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_VIDEO
+enum {
+       /* Maximum LCD size we support */
+       LCD_MAX_WIDTH           = 1366,
+       LCD_MAX_HEIGHT          = 768,
+       LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
+};
+#endif
+
+struct atmel_fb_priv {
+       struct display_timing timing;
+};
+
 /* configurable parameters */
 #define ATMEL_LCDC_CVAL_DEFAULT                0xc8
 #define ATMEL_LCDC_DMA_BURST_LEN       8
@@ -30,6 +49,7 @@
 #define lcdc_readl(mmio, reg)          __raw_readl((mmio)+(reg))
 #define lcdc_writel(mmio, reg, val)    __raw_writel((val), (mmio)+(reg))
 
+#ifndef CONFIG_DM_VIDEO
 ushort *configuration_get_cmap(void)
 {
        return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
@@ -90,40 +110,43 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
                lcd_setcolreg(i, cte.red, cte.green, cte.blue);
        }
 }
+#endif
 
-void lcd_ctrl_init(void *lcdbase)
+static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
+                         bool tft, bool cont_pol_low, ulong lcdbase)
 {
        unsigned long value;
+       void *reg = (void *)addr;
 
        /* Turn off the LCD controller and the DMA controller */
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+       lcdc_writel(reg, ATMEL_LCDC_PWRCON,
                    ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 
        /* Wait for the LCDC core to become idle */
-       while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+       while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
                udelay(10);
 
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
+       lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 
        /* Reset LCDC DMA */
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
+       lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 
        /* ...set frame size and burst length = 8 words (?) */
-       value = (panel_info.vl_col * panel_info.vl_row *
-                NBITS(panel_info.vl_bpix)) / 32;
+       value = (timing->hactive.typ * timing->vactive.typ *
+                (1 << bpix)) / 32;
        value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
+       lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 
        /* Set pixel clock */
-       value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
-       if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
+       value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
+       if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
                value++;
        value = (value / 2) - 1;
 
        if (!value) {
-               lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+               lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
        } else
-               lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
+               lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
                            value << ATMEL_LCDC_CLKVAL_OFFSET);
 
        /* Initialize control register 2 */
@@ -132,58 +155,160 @@ void lcd_ctrl_init(void *lcdbase)
 #else
        value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 #endif
-       if (panel_info.vl_tft)
+       if (tft)
                value |= ATMEL_LCDC_DISTYPE_TFT;
 
-       value |= panel_info.vl_sync;
-       value |= (panel_info.vl_bpix << 5);
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
+       if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
+               value |= ATMEL_LCDC_INVLINE_INVERTED;
+       if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
+               value |= ATMEL_LCDC_INVFRAME_INVERTED;
+       value |= bpix << 5;
+       lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 
        /* Vertical timing */
-       value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
-       value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
-       value |= panel_info.vl_lower_margin;
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
+       value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
+       value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
+       value |= timing->vfront_porch.typ;
+       /* Magic! (Datasheet says "Bit 31 must be written to 1") */
+       value |= 1U << 31;
+       lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 
        /* Horizontal timing */
-       value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
-       value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
-       value |= (panel_info.vl_left_margin - 1);
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
+       value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
+       value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
+       value |= (timing->hback_porch.typ - 1);
+       lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 
        /* Display size */
-       value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
-       value |= panel_info.vl_row - 1;
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
+       value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+       value |= timing->vactive.typ - 1;
+       lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 
        /* FIFO Threshold: Use formula from data sheet */
        value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
+       lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 
        /* Toggle LCD_MODE every frame */
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
+       lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 
        /* Disable all interrupts */
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
+       lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 
        /* Set contrast */
        value = ATMEL_LCDC_PS_DIV8 |
                ATMEL_LCDC_ENA_PWMENABLE;
-       if (!panel_info.vl_cont_pol_low)
+       if (!cont_pol_low)
                value |= ATMEL_LCDC_POL_POSITIVE;
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+       lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
+       lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 
        /* Set framebuffer DMA base address and pixel offset */
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
+       lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+       lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
+       lcdc_writel(reg, ATMEL_LCDC_PWRCON,
                    (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 }
 
+#ifndef CONFIG_DM_VIDEO
+void lcd_ctrl_init(void *lcdbase)
+{
+       struct display_timing timing;
+
+       timing.flags = 0;
+       if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
+               timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+       if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
+               timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
+       timing.pixelclock.typ = panel_info.vl_clk;
+
+       timing.hactive.typ = panel_info.vl_col;
+       timing.hfront_porch.typ = panel_info.vl_right_margin;
+       timing.hback_porch.typ = panel_info.vl_left_margin;
+       timing.hsync_len.typ = panel_info.vl_hsync_len;
+
+       timing.vactive.typ = panel_info.vl_row;
+       timing.vfront_porch.typ = panel_info.vl_clk;
+       timing.vback_porch.typ = panel_info.vl_clk;
+       timing.vsync_len.typ = panel_info.vl_clk;
+
+       atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
+                     panel_info.vl_tft, panel_info.vl_cont_pol_low,
+                     (ulong)lcdbase);
+}
+
 ulong calc_fbsize(void)
 {
        return ((panel_info.vl_col * panel_info.vl_row *
                NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 }
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static int atmel_fb_lcd_probe(struct udevice *dev)
+{
+       struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+       struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+       struct atmel_fb_priv *priv = dev_get_priv(dev);
+       struct display_timing *timing = &priv->timing;
+
+       /*
+        * For now some values are hard-coded. We could use the device tree
+        * bindings in simple-framebuffer.txt to specify the format/bpp and
+        * some Atmel-specific binding for tft and cont_pol_low.
+        */
+       atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
+                     uc_plat->base);
+       uc_priv->xsize = timing->hactive.typ;
+       uc_priv->ysize = timing->vactive.typ;
+       uc_priv->bpix = VIDEO_BPP16;
+       video_set_flush_dcache(dev, true);
+       debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
+             uc_plat->size, uc_priv->xsize, uc_priv->ysize);
+
+       return 0;
+}
+
+static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
+{
+       struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+       struct atmel_fb_priv *priv = dev_get_priv(dev);
+       struct display_timing *timing = &priv->timing;
+       const void *blob = gd->fdt_blob;
+
+       if (fdtdec_decode_display_timing(blob, dev->of_offset,
+                                        plat->timing_index, timing)) {
+               debug("%s: Failed to decode display timing\n", __func__);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int atmel_fb_lcd_bind(struct udevice *dev)
+{
+       struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+
+       uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+                       (1 << VIDEO_BPP16) / 8;
+       debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+       return 0;
+}
+
+static const struct udevice_id atmel_fb_lcd_ids[] = {
+       { .compatible = "atmel,at91sam9g45-lcdc" },
+       { }
+};
+
+U_BOOT_DRIVER(atmel_fb) = {
+       .name   = "atmel_fb",
+       .id     = UCLASS_VIDEO,
+       .of_match = atmel_fb_lcd_ids,
+       .bind   = atmel_fb_lcd_bind,
+       .ofdata_to_platdata     = atmel_fb_ofdata_to_platdata,
+       .probe  = atmel_fb_lcd_probe,
+       .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
+       .priv_auto_alloc_size   = sizeof(struct atmel_fb_priv),
+};
+#endif

diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h
index 6993128b1b4c37df8d6c544cb2e06e0f220269c0..8a2f46f6c7bca9abdf9fdb76538496d06ca2a90d 100644 (file)
--- a/include/atmel_lcd.h
+++ b/include/atmel_lcd.h
@@ -10,6 +10,15 @@
 #ifndef _ATMEL_LCD_H_
 #define _ATMEL_LCD_H_
 
+/**
+ * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ *
+ * @timing_index:      Index of LCD timing to use in device tree node
+ */
+struct atmel_lcd_platdata {
+       int timing_index;
+};
+
 typedef struct vidinfo {
        ushort vl_col;          /* Number of columns (i.e. 640) */
        ushort vl_row;          /* Number of rows (i.e. 480) */

diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
new file mode 100644 (file)
index 0000000..bd3c711
--- /dev/null
+++ b/include/configs/bcm23550_w1d.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __BCM23550_W1D_H
+#define __BCM23550_W1D_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* CPU, chip, mach, etc */
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_KONA_RESET_S
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE           0x9f000000
+
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+#define CONFIG_SYS_SDRAM_SIZE          0x20000000
+#define CONFIG_NR_DRAM_BANKS           1
+
+#define CONFIG_SYS_MALLOC_LEN          SZ_4M   /* see armv7/start.S. */
+#define CONFIG_STACKSIZE               SZ_256K
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_KONA_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM 3       /* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS 4
+#define CONFIG_SYS_I2C_BASE0   BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1   BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2   BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3   PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE          32000
+#define CONFIG_SYS_TIMER_COUNTER       (TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+#define CONFIG_MISC_INIT_R     /* board's misc_init_r function */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR                CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
+#define CONFIG_SYS_NS16550_CLK         13000000
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_SYS_NS16550_COM1                0x3e000000
+
+#define CONFIG_BAUDRATE                        115200
+
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_OFFSET              (0x00011a00 * 512)
+#define CONFIG_ENV_SIZE                        (8 * 512)
+
+#define CONFIG_SYS_NO_FLASH    /* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE              1024    /* Console buffer size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                       sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND             ""
+
+/* Commands */
+#define CONFIG_FAT_WRITE
+
+/* Fastboot and USB OTG */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV  0
+#define CONFIG_SYS_CACHELINE_SIZE      64
+#define CONFIG_FASTBOOT_BUF_SIZE       0x1d000000
+#define CONFIG_FASTBOOT_BUF_ADDR       CONFIG_SYS_SDRAM_BASE
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#define CONFIG_USB_GADGET_VBUS_DRAW    0
+#define CONFIG_USB_GADGET_DWC2_PHY_8_BIT
+#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
+#define CONFIG_USBID_ADDR              0x34052c46
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_L2CACHE_OFF
+
+#endif /* __BCM23550_W1D_H */

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 13076072e46e79fd30d6e254c6ca9eced48135a1..502ddad96b82813ea35bf75f14bcb78841634509 100644 (file)
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -97,11 +97,6 @@
 /*
  * Env Settings
  */
-#ifndef CONFIG_BOOTDELAY
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# else
-# endif
-#endif
 #ifndef CONFIG_BOOTCOMMAND
 # define CONFIG_BOOTCOMMAND    "run ramboot"
 #endif

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 42771b51d4441e118a9961418afc13d3e868364a..4de2460bc0ee641bf9ddb38d8aa78bed85bda984 100644 (file)
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -59,13 +59,14 @@
 #define CONFIG_MXC_OCOTP
 
 /* SATA Configs */
-#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
 #define CONFIG_DWC_AHSATA
 #define CONFIG_SYS_SATA_MAX_DEVICE     1
 #define CONFIG_DWC_AHSATA_PORT_ID      0
 #define CONFIG_DWC_AHSATA_BASE_ADDR    SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
 #define CONFIG_LIBATA
+#endif
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
@@ -77,6 +78,7 @@
 #define CONFIG_DOS_PARTITION
 
 /* USB Configs */
+#ifdef CONFIG_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -98,8 +100,10 @@
 #define CONFIG_G_DNL_VENDOR_NUM   0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM  0xa4a5
 #define CONFIG_G_DNL_MANUFACTURER "Advantech"
+#endif
 
 /* Networking Configs */
+#ifdef CONFIG_NET
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
@@ -108,6 +112,7 @@
 #define CONFIG_FEC_MXC_PHYADDR         4
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
+#endif
 
 /* Serial Flash */
 #ifdef CONFIG_CMD_SF
@@ -220,29 +225,37 @@
                        "bootm; " \
                "fi;\0" \
 
-#define CONFIG_BOOTCOMMAND \
-       "usb start; " \
-       "setenv dev usb; " \
-       "setenv devnum 0; " \
-       "setenv rootdev sda1; " \
-       "run tryboot; " \
-       \
+#define CONFIG_MMCBOOTCOMMAND \
        "setenv dev mmc; " \
-       "setenv rootdev mmcblk0p1; " \
+       "setenv rootdev mmcblk0p${partnum}; " \
        \
        "setenv devnum ${sddev}; " \
        "if mmc dev ${devnum}; then " \
                "run tryboot; " \
-               "setenv rootdev mmcblk1p1; " \
+               "setenv rootdev mmcblk1p${partnum}; " \
        "fi; " \
        \
        "setenv devnum ${emmcdev}; " \
        "if mmc dev ${devnum}; then " \
                "run tryboot; " \
        "fi; " \
+
+#define CONFIG_USBBOOTCOMMAND \
+       "usb start; " \
+       "setenv dev usb; " \
+       "setenv devnum 0; " \
+       "setenv rootdev sda${partnum}; " \
+       "run tryboot; " \
        \
+       CONFIG_MMCBOOTCOMMAND \
        "bmode usb; " \
 
+#ifdef CONFIG_CMD_USB
+#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
+#else
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#endif
+
 #define CONFIG_ARP_TIMEOUT     200UL
 
 /* Miscellaneous configurable options */
@@ -292,13 +305,14 @@
 
 #define CONFIG_SYS_FSL_USDHC_NUM       3
 
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+
 /* Framebuffer */
-#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
@@ -308,6 +322,7 @@
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
+#endif
 
 #define CONFIG_PWM_IMX
 #define CONFIG_IMX6_PWM_PER_CLK        66000000

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index e11629cc5545651d4aac4acd64cfc30e4d9b880b..982ddba39cf9bab0d23686a6a095e42cd9e877c4 100644 (file)
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -18,7 +18,6 @@
 /* Falcon Mode */
 #define CONFIG_CMD_SPL
 #define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
 #define CONFIG_CMD_SPL_WRITE_SIZE      (128 * SZ_1K)
 
@@ -33,6 +32,7 @@
 
 #include "imx6_spl.h"                  /* common IMX6 SPL configuration */
 #include "mx6_common.h"
+#undef CONFIG_SPL_EXT_SUPPORT
 
 #define CONFIG_MACH_TYPE       4520   /* Gateworks Ventana Platform */
 
@@ -52,9 +52,6 @@
 #define CONFIG_DM_THERMAL
 #endif
 
-/* GPIO */
-#define CONFIG_MXC_GPIO
-
 /* Thermal */
 #define CONFIG_IMX_THERMAL
 
@@ -204,6 +201,7 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_HWCONFIG
+#define CONFIG_PREBOOT
 
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -284,37 +282,45 @@
        \
        "mtdparts=" MTDPARTS_DEFAULT "\0" \
        "mtdids=" MTDIDS_DEFAULT "\0" \
+       "disk=0\0" \
+       "part=1\0" \
        \
        "fdt_high=0xffffffff\0" \
        "fdt_addr=0x18000000\0" \
        "initrd_high=0xffffffff\0" \
+       "fixfdt=" \
+               "fdt addr ${fdt_addr}\0" \
        "bootdir=boot\0" \
        "loadfdt=" \
                "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
                        "echo Loaded DTB from ${bootdir}/${fdt_file}; " \
+                       "run fixfdt; " \
                "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
                        "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
+                       "run fixfdt; " \
                "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
                        "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
+                       "run fixfdt; " \
                "fi\0" \
        \
+       "fs=ext4\0" \
        "script=6x_bootscript-ventana\0" \
        "loadscript=" \
                "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
-                       "source; " \
+                       "source ${loadaddr}; " \
                "fi\0" \
        \
        "uimage=uImage\0" \
-       "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+       "mmc_root=/dev/mmcblk0p1 rootfstype=${fs} rootwait rw\0" \
        "mmc_boot=" \
-               "setenv fsload 'ext2load mmc 0:1'; " \
-               "mmc dev 0 && mmc rescan && " \
+               "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
+               "mmc dev ${disk} && mmc rescan && " \
                "setenv dtype mmc; run loadscript; " \
                "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
                        "setenv bootargs console=${console},${baudrate} " \
-                               "root=/dev/mmcblk0p1 rootfstype=ext4 " \
+                               "root=/dev/mmcblk0p1 rootfstype=${fs} " \
                                "rootwait rw ${video} ${extra}; " \
-                       "if run loadfdt && fdt addr ${fdt_addr}; then " \
+                       "if run loadfdt; then " \
                                "bootm ${loadaddr} - ${fdt_addr}; " \
                        "else " \
                                "bootm; " \
@@ -322,26 +328,28 @@
                "fi\0" \
        \
        "sata_boot=" \
-               "setenv fsload 'ext2load sata 0:1'; sata init && " \
+               "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \
+               "sata init && " \
                "setenv dtype sata; run loadscript; " \
                "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
                        "setenv bootargs console=${console},${baudrate} " \
-                               "root=/dev/sda1 rootfstype=ext4 " \
+                               "root=/dev/sda1 rootfstype=${fs} " \
                                "rootwait rw ${video} ${extra}; " \
-                       "if run loadfdt && fdt addr ${fdt_addr}; then " \
+                       "if run loadfdt; then " \
                                "bootm ${loadaddr} - ${fdt_addr}; " \
                        "else " \
                                "bootm; " \
                        "fi; " \
                "fi\0" \
        "usb_boot=" \
-               "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+               "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \
+               "usb start && usb dev ${disk} && " \
                "setenv dtype usb; run loadscript; " \
                "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
                        "setenv bootargs console=${console},${baudrate} " \
-                               "root=/dev/sda1 rootfstype=ext4 " \
+                               "root=/dev/sda1 rootfstype=${fs} " \
                                "rootwait rw ${video} ${extra}; " \
-                       "if run loadfdt && fdt addr ${fdt_addr}; then " \
+                       "if run loadfdt; then " \
                                "bootm ${loadaddr} - ${fdt_addr}; " \
                        "else " \
                                "bootm; " \
@@ -404,7 +412,7 @@
                "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
                        "setenv bootargs console=${console},${baudrate} " \
                                "root=${root} ${video} ${extra}; " \
-                       "if run loadfdt && fdt addr ${fdt_addr}; then " \
+                       "if run loadfdt; then " \
                                "ubifsumount; " \
                                "bootm ${loadaddr} - ${fdt_addr}; " \
                        "else " \

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2bf524f69af0467c3b5bcc09dd2f5f8d7a234aa9..ebe14154213c1b413968f07403b6be2a059545f4 100644 (file)
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE           0x80400000
 #else
 #define CONFIG_SYS_TEXT_BASE           0x30100000
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
@@ -138,13 +140,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS            0xC0000000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY      0x8000000
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
@@ -289,7 +284,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
 #define CONFIG_SYS_SPL_MALLOC_START    0x80200000
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN         (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 

diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aafbc62c3844a597af44265b6623fcd97c39..7f245b5fad7526c548b287167a465fec043984ee 100644 (file)
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT       (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index b44066c4073de376640cf3a5056828e91ae700d8..df1455bef34297585968095cc2317d1af3bd764b 100644 (file)
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV                0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR       0x66
 #define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ            get_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL         (CONFIG_SYS_CLK_FREQ/4)
@@ -162,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK           0x00
 #define QIXIS_LBMAP_ALTBANK            0x04
 #define QIXIS_LBMAP_NAND               0x09
+#define QIXIS_LBMAP_QSPI               0x0f
 #define QIXIS_RST_CTL_RESET            0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND             0x107
+#define QIXIS_RCW_SRC_QSPI             0x62
 #define        QIXIS_RST_FORCE_MEM             0x01
 
 #define CONFIG_SYS_CSPR3_EXT   (0x0)
@@ -227,7 +239,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE    (512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR_EARLY
@@ -257,11 +269,19 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE           0x20010000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define CONFIG_ENV_SIZE                        0x2000
 #endif
+#endif
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
@@ -279,8 +299,27 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT      0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE            (1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM             4
+#endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI         0x1
+
 #endif
 
 /*

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 27f38f497e4c1f8858100c2cb2374fc2e2b86b24..fb49322f3be35664c68367219a3fbe2321e23400 100644 (file)
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -59,9 +59,6 @@
 #endif
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-#ifndef CONFIG_BOOTDELAY
-#endif
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX       1

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 5e5656d480662d5550dd5d1941f06ddd3aefcc0f..fbc6de62837038d16a2c335b486771286afc5457 100644 (file)
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -34,9 +34,6 @@
 #define CONFIG_LOADADDR                 0x80800000
 #define CONFIG_SYS_TEXT_BASE            0x87800000
 
-#ifndef CONFIG_BOOTDELAY
-#endif
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX               1

diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 96c3c4b958d2c247d350d6a4cd9cf8f6c61e2744..82e0d5000ca93bd7d5c5cde61cd877699979de90 100644 (file)
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -73,8 +73,6 @@
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
-/* override default CONFIG_BOOTDELAY */
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "machid=ffffffff\0" \
        "fdt_high=0x87000000\0" \

diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
new file mode 100644 (file)
index 0000000..9723bab
--- /dev/null
+++ b/include/configs/s32v234evb.h
@@ -0,0 +1,260 @@
+/*
+ * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ * Configuration settings for the Freescale S32V234 EVB board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_S32V234
+#define CONFIG_DM
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Config GIC */
+#define CONFIG_GICV2
+#define GICD_BASE 0x7D001000
+#define GICC_BASE 0x7D002000
+
+#define CONFIG_REMAKE_ELF
+#undef CONFIG_RUN_FROM_IRAM_ONLY
+
+#define CONFIG_RUN_FROM_DDR1
+#undef CONFIG_RUN_FROM_DDR0
+
+/* Run by default from DDR1  */
+#ifdef CONFIG_RUN_FROM_DDR0
+#define DDR_BASE_ADDR          0x80000000
+#else
+#define DDR_BASE_ADDR          0xC0000000
+#endif
+
+#define CONFIG_MACH_TYPE               4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Config CACHE */
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_FULL_VA
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY               (1000000000)   /* 1000MHz */
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+
+/* Size of malloc() pool */
+#ifdef CONFIG_RUN_FROM_IRAM_ONLY
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 1 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#endif
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_DM_SERIAL
+#define CONFIG_FSL_LINFLEXUART
+#define LINFLEXUART_BASE               LINFLEXD0_BASE_ADDR
+
+#define CONFIG_DEBUG_UART_LINFLEXUART
+#define CONFIG_DEBUG_UART_BASE         LINFLEXUART_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT           (1)
+#define CONFIG_BAUDRATE                                115200
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_NUM       1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+/* #define CONFIG_CMD_EXT2 EXT2 Support */
+#define CONFIG_CMD_FAT         /* FAT support */
+#define CONFIG_DOS_PARTITION
+
+#if 0
+
+/* Ethernet config */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE            ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE     RMII
+#define CONFIG_FEC_MXC_PHYADDR  0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#endif
+
+#if 0                          /* Disable until the I2C driver will be updated */
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE            I2C0_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED           100000
+#endif
+
+#if 0                          /* Disable until the FLASH will be implemented */
+#define CONFIG_SYS_USE_NAND
+#endif
+
+#ifdef CONFIG_SYS_USE_NAND
+/* Nand Flash Configs */
+#define        CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define MTD_NAND_FSL_NFC_SWECC 1
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE           0x400E0000
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define NAND_MAX_CHIPS                 CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define CONFIG_SYS_64BIT_VSPRINTF      /* needed for nand_util.c */
+#endif
+
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_LOADADDR                        0xC307FFC0
+#define CONFIG_BOOTARGS                        "console=ttyLF0 root=/dev/ram rw"
+
+#define CONFIG_CMD_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "boot_scripts=boot.scr.uimg boot.scr\0" \
+       "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+       "console=ttyLF0,115200\0" \
+       "fdt_file=s32v234-evb.dtb\0" \
+       "fdt_high=0xffffffff\0" \
+       "initrd_high=0xffffffff\0" \
+       "fdt_addr_r=0xC2000000\0" \
+       "kernel_addr_r=0xC307FFC0\0" \
+       "ramdisk_addr_r=0xC4000000\0" \
+       "ramdisk=rootfs.uimg\0"\
+       "ip_dyn=yes\0" \
+       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+       "update_sd_firmware_filename=u-boot.imx\0" \
+       "update_sd_firmware=" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "if mmc dev ${mmcdev}; then "   \
+                       "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+                               "setexpr fw_sz ${filesize} / 0x200; " \
+                               "setexpr fw_sz ${fw_sz} + 1; "  \
+                               "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+                       "fi; "  \
+               "fi\0" \
+       "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
+       "jtagboot=echo Booting using jtag...; " \
+               "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+       "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
+               "run loaduimage; run loadramdisk; run loadfdt;"\
+               "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+       "boot_net_usb_start=true\0" \
+       BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 1) \
+       func(MMC, mmc, 0) \
+       func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+       "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP    /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "=> "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE              \
+                       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16      /* max number of command args */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       (DDR_BASE_ADDR)
+#define CONFIG_SYS_MEMTEST_END         (DDR_BASE_ADDR + 0x7C00000)
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+#define CONFIG_SYS_HZ                          1000
+
+#define CONFIG_SYS_TEXT_BASE           0x3E800000      /* SDRAM */
+
+#ifdef CONFIG_RUN_FROM_IRAM_ONLY
+#define CONFIG_SYS_MALLOC_BASE         (DDR_BASE_ADDR)
+#endif
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE               (128 * 1024)    /* regular stack */
+
+#if 0
+/* Configure PXE */
+#define CONFIG_CMD_PXE
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH    0x100
+#endif
+
+/* Physical memory map */
+/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     (DDR_BASE_ADDR)
+#define PHYS_SDRAM_SIZE                        (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET              (12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV         0
+
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#endif

diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
new file mode 100644 (file)
index 0000000..ddfbcec
--- /dev/null
+++ b/include/configs/snapper9g45.h
@@ -0,0 +1,155 @@
+/*
+ * Bluewater Systems Snapper 9G45 module
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_TEXT_BASE           0x73f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK     32768
+
+/* CPU */
+#define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE          (128 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR                (ATMEL_BASE_SRAM + 0x1000 - \
+                                        GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_SYS_NAND_ECC_BASE       ATMEL_BASE_ECC
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE       (1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE       (1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN     AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN      AT91_PIN_PC8
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT         20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#define CONFIG_PARTITION_UUIDS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+
+/* LCD */
+#define CONFIG_ATMEL_LCD
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_GURNARD_SPLASH
+
+#define CONFIG_ATMEL_SPI
+
+/* GPIOs and IO expander */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP                1
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_BAUDRATE                        115200
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR           0x23000000
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Environment settings */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              (512 << 10)
+#define CONFIG_ENV_SIZE                        (256 << 10)
+#define CONFIG_ENV_OVERWRITE
+
+#define        CONFIG_EXTRA_ENV_SETTINGS       \
+       "ethaddr=00:00:00:00:00:00\0" \
+       "serial=0\0" \
+       "stdout=serial_atmel\0" \
+       "stderr=serial_atmel\0" \
+       "stdin=serial_atmel\0" \
+       "bootlimit=3\0" \
+       "loadaddr=0x71000000\0" \
+       "board_rev=2\0" \
+       "bootfile=/tftpboot/uImage\0" \
+       "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
+       "nfsroot=/export/root\0" \
+       "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
+       "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
+       "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
+       "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+       "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+       "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
+       "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
+
+/* Console settings */
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE +            \
+                                        sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN          (1 << 20)
+
+/* Command line configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PART
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 8bbe580ebf36979ff691072b52b5f5a3cca5a87f..f05c1aacaf99ea892896f5cc7c87f1931eb42d82 100644 (file)
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -82,8 +82,6 @@
        "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
        "bootm 0x08044000 - 0x08042000\0"
 
-#define CONFIG_AUTOBOOT
-
 /*
  * Command line configuration.
  */

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b33cfb86f82e0831f5d19b1e473205f65efb5a96..94275a7183ffc35547893dedcc933bb6b8d61c7a 100644 (file)
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -100,7 +100,7 @@
  * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x10000
-#define CONFIG_SYS_INIT_RAM_SIZE       0x08000 /* FIXME: 40 KiB ? */
+#define CONFIG_SYS_INIT_RAM_SIZE       0xA000  /* 40 KiB */
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR       0x0
 #define CONFIG_SYS_INIT_RAM_SIZE       0x8000  /* 32 KiB */
@@ -213,8 +213,7 @@
 #define CONFIG_SPL_PAD_TO              32768           /* decimal for 'dd' */
 
 #if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
-/* FIXME: 40 KiB instead of 32 KiB ? */
-#define LOW_LEVEL_SRAM_STACK           0x00018000
+#define LOW_LEVEL_SRAM_STACK           0x0001A000
 #define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 #else
 /* end of 32 KiB in sram */

diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 707106ffab8d3c8afb33793b1fb0964b2353381e..2ee26c40367077d67d88d717ea6b232358c48f9a 100644 (file)
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -245,7 +245,6 @@
        "tftp_root=/\0"                                                 \
        "nfs_root=/export\0"                                            \
        "mem_lpae=1\0"                                                  \
-       "mem_reserve=512M\0"                                            \
        "addr_ubi=0x82000000\0"                                         \
        "addr_secdb_key=0xc000000\0"                                    \
        "name_kern=zImage\0"                                            \

diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 5c5a12d493c3597590b84eef2e44fef4dc28effa..2e4c8e9646787eff88539a8f4873b524b6568caa 100644 (file)
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -104,6 +104,8 @@
                        "setenv fdtfile dra72-evm.dtb; fi;" \
                "if test $board_name = beagle_x15; then " \
                        "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+               "if test $board_name = am572x_idk; then " \
+                       "setenv fdtfile am572x-idk.dtb; fi;" \
                "if test $board_name = am57xx_evm; then " \
                        "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
                "if test $fdtfile = undefined; then " \

diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 8b4726f19c360a0e06a2e574f6fe36cdd8e6109c..252b3fc70656daa5dcc634e3425439923e9f74b4 100644 (file)
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -62,6 +62,8 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      MMC_SDHC1_BASE_ADDR
 
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
 #define CONFIG_MMC
 
 #define CONFIG_GENERIC_MMC
@@ -95,19 +97,28 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "script=boot.scr\0" \
-       "image=uImage\0" \
+       "image=zImage\0" \
+       "fdt_file=imx51-ts4800.dtb\0" \
+       "fdt_addr=0x90fe0000\0" \
        "mmcdev=0\0" \
-       "mmcpart=1\0" \
-       "mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
+       "mmcpart=2\0" \
+       "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+       "mmcargs=setenv bootargs root=${mmcroot}\0" \
        "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
        "loadbootscript=" \
                "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
        "bootscript=echo Running bootscript from mmc ...; " \
                "source\0" \
        "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
        "mmcboot=echo Booting from mmc ...; " \
                "run mmcargs addtty; " \
-                "bootm; "
+               "if run loadfdt; then " \
+                       "bootz ${loadaddr} - ${fdt_addr}; " \
+               "else " \
+                       "echo ERR: cannot load FDT; " \
+               "fi; "
+
 
 #define CONFIG_BOOTCOMMAND \
        "mmc dev ${mmcdev}; if mmc rescan; then " \

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
new file mode 100644 (file)
index 0000000..ab3ee24
--- /dev/null
+++ b/include/dt-bindings/clock/at91.h
@@ -0,0 +1,23 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS         0               /* MOSCS Flag */
+#define AT91_PMC_LOCKA         1               /* PLLA Lock */
+#define AT91_PMC_LOCKB         2               /* PLLB Lock */
+#define AT91_PMC_MCKRDY                3               /* Master Clock */
+#define AT91_PMC_LOCKU         6               /* UPLL Lock */
+#define AT91_PMC_PCKRDY(id)    (8 + (id))      /* Programmable Clock */
+#define AT91_PMC_MOSCSELS      16              /* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS       17              /* Main On-Chip RC */
+#define AT91_PMC_CFDEV         18              /* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY                24              /* Generated Clocks */
+
+#endif

diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
new file mode 100644 (file)
index 0000000..ab6cbba
--- /dev/null
+++ b/include/dt-bindings/dma/at91.h
@@ -0,0 +1,52 @@
+/*
+ * This header provides macros for at91 dma bindings.
+ *
+ * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_DMA_H__
+#define __DT_BINDINGS_AT91_DMA_H__
+
+/* ---------- HDMAC ---------- */
+
+/*
+ * Source and/or destination peripheral ID
+ */
+#define AT91_DMA_CFG_PER_ID_MASK       (0xff)
+#define AT91_DMA_CFG_PER_ID(id)                (id & AT91_DMA_CFG_PER_ID_MASK)
+
+/*
+ * FIFO configuration: it defines when a request is serviced.
+ */
+#define AT91_DMA_CFG_FIFOCFG_OFFSET    (8)
+#define AT91_DMA_CFG_FIFOCFG_MASK      (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
+#define AT91_DMA_CFG_FIFOCFG_HALF      (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET)    /* half FIFO (default behavior) */
+#define AT91_DMA_CFG_FIFOCFG_ALAP      (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET)    /* largest defined AHB burst */
+#define AT91_DMA_CFG_FIFOCFG_ASAP      (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET)    /* single AHB access */
+
+
+/* ---------- XDMAC ---------- */
+#define AT91_XDMAC_DT_MEM_IF_MASK      (0x1)
+#define AT91_XDMAC_DT_MEM_IF_OFFSET    (13)
+#define AT91_XDMAC_DT_MEM_IF(mem_if)   (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
+                                       << AT91_XDMAC_DT_MEM_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_MEM_IF(cfg)  (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
+                                       & AT91_XDMAC_DT_MEM_IF_MASK)
+
+#define AT91_XDMAC_DT_PER_IF_MASK      (0x1)
+#define AT91_XDMAC_DT_PER_IF_OFFSET    (14)
+#define AT91_XDMAC_DT_PER_IF(per_if)   (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
+                                       << AT91_XDMAC_DT_PER_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_PER_IF(cfg)  (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
+                                       & AT91_XDMAC_DT_PER_IF_MASK)
+
+#define AT91_XDMAC_DT_PERID_MASK       (0x7f)
+#define AT91_XDMAC_DT_PERID_OFFSET     (24)
+#define AT91_XDMAC_DT_PERID(perid)     (((perid) & AT91_XDMAC_DT_PERID_MASK) \
+                                       << AT91_XDMAC_DT_PERID_OFFSET)
+#define AT91_XDMAC_DT_GET_PERID(cfg)   (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
+                                       & AT91_XDMAC_DT_PERID_MASK)
+
+#endif /* __DT_BINDINGS_AT91_DMA_H__ */

diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
new file mode 100644 (file)
index 0000000..bbca3d0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for most at91 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
+#define __DT_BINDINGS_AT91_PINCTRL_H__
+
+#define AT91_PINCTRL_NONE              (0 << 0)
+#define AT91_PINCTRL_PULL_UP           (1 << 0)
+#define AT91_PINCTRL_MULTI_DRIVE       (1 << 1)
+#define AT91_PINCTRL_DEGLITCH          (1 << 2)
+#define AT91_PINCTRL_PULL_DOWN         (1 << 3)
+#define AT91_PINCTRL_DIS_SCHMIT                (1 << 4)
+#define AT91_PINCTRL_DEBOUNCE          (1 << 16)
+#define AT91_PINCTRL_DEBOUNCE_VAL(x)   (x << 17)
+
+#define AT91_PINCTRL_PULL_UP_DEGLITCH  (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT            (0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW                        (0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED                        (0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI                 (0x3 << 5)
+
+#define AT91_PIOA      0
+#define AT91_PIOB      1
+#define AT91_PIOC      2
+#define AT91_PIOD      3
+#define AT91_PIOE      4
+
+#define AT91_PERIPH_GPIO       0
+#define AT91_PERIPH_A          1
+#define AT91_PERIPH_B          2
+#define AT91_PERIPH_C          3
+#define AT91_PERIPH_D          4
+
+#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */

diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae4538a70e00ce846ee9fa3262a11aaaebc15..d500445aaf193b517f7df3ec457105d85ef9fa71 100644 (file)
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT

diff --git a/include/linux/compat.h b/include/linux/compat.h
index e561ee311a09cd546794524bd91896eb47688084..7236b8d0c302b7c42bb4128d3ea75de27ae822fe 100644 (file)
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -25,6 +25,8 @@ extern struct p_current *current;
        printf(fmt, ##args)
 #define dev_err(dev, fmt, args...)             \
        printf(fmt, ##args)
+#define dev_warn(dev, fmt, args...)            \
+       printf(fmt, ##args)
 #define printk printf
 #define printk_once    printf
 

diff --git a/lib/Makefile b/lib/Makefile
index f77befe03c24fe35e6509cb9b17636a8c7b3cd2f..f48d90103d2134f841912ff9c82450d6b8707087 100644 (file)
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -9,7 +9,6 @@ ifndef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_EFI) += efi/
 obj-$(CONFIG_EFI_LOADER) += efi_loader/
-obj-$(CONFIG_RSA) += rsa/
 obj-$(CONFIG_LZMA) += lzma/
 obj-$(CONFIG_LZO) += lzo/
 obj-$(CONFIG_ZLIB) += zlib/
@@ -25,8 +24,6 @@ obj-y += crc8.o
 obj-y += crc16.o
 obj-$(CONFIG_ERRNO_STR) += errno_str.o
 obj-$(CONFIG_FIT) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
 obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
 obj-$(CONFIG_GZIP) += gunzip.o
 obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
@@ -39,15 +36,17 @@ obj-y += net_utils.o
 obj-$(CONFIG_PHYSMEM) += physmem.o
 obj-y += qsort.o
 obj-y += rc4.o
-obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
-obj-$(CONFIG_SHA256) += sha256.o
 obj-$(CONFIG_TPM) += tpm.o
 obj-$(CONFIG_RBTREE)   += rbtree.o
 obj-$(CONFIG_BITREVERSE) += bitrev.o
 obj-y += list_sort.o
 endif
 
+obj-$(CONFIG_$(SPL_)RSA) += rsa/
+obj-$(CONFIG_$(SPL_)SHA1) += sha1.o
+obj-$(CONFIG_$(SPL_)SHA256) += sha256.o
+
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
 ifdef CONFIG_SPL_OF_CONTROL
 obj-$(CONFIG_OF_LIBFDT) += libfdt/

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index ab002e9fa3e5ceb33edcca7a08fcfb2f1d42e595..686b89da38549883c8cdaa5511c8a15d1921706d 100644 (file)
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1170,7 +1170,7 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
        if (fdtdec_get_bool(blob, node, "doubleclk"))
                dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
 
-       return 0;
+       return ret;
 }
 
 int fdtdec_setup(void)

diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 86df0a0dd83b8c60f4995f801d186d58318cc3e9..09ec3582423bc0fc30c37531ade495e06f65fa01 100644 (file)
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -13,6 +13,10 @@ config RSA
          option. The software based modular exponentiation is built into
          mkimage irrespective of this option.
 
+config SPL_RSA
+       bool "Use RSA Library within SPL"
+       depends on RSA
+
 if RSA
 config RSA_SOFTWARE_EXP
        bool "Enable driver for RSA Modular Exponentiation in software"

diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index 6867e5054c098c20a64b18cecb128cae9b548079..4b2c1bae79bcc543ad1f27a3eaa2d702a77dfeca 100644 (file)
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -7,5 +7,5 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
 obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o

diff --git a/net/bootp.c b/net/bootp.c
index aa6cdf0a47a5c17a36a711c62e72043890ce2465..42e14eda417436b0b6ef133055185e2ecb895029 100644 (file)
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -673,6 +673,15 @@ static int bootp_extended(u8 *e)
 
        *e++ = 255;             /* End of the list */
 
+       /*
+        * If nothing in list, remove it altogether. Some DHCP servers get
+        * upset by this minor faux pas and do not respond at all.
+        */
+       if (e == start + 3) {
+               printf("*** Warning: no DHCP options requested\n");
+               e -= 3;
+       }
+
        return e - start;
 }
 #endif

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 68631b7faed8267e786da0c7c687369f22f189ea..5e5ca06d8f9542537abcfffd352e971605963ae3 100755 (executable)
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -17,72 +17,57 @@ This tool intends to help this tremendous work.
 Usage
 -----
 
-This tool takes one input file.  (let's say 'recipe' file here.)
-The recipe describes the list of config options you want to move.
-Each line takes the form:
-<config_name> <type> <default>
-(the fields must be separated with whitespaces.)
-
-<config_name> is the name of config option.
-
-<type> is the type of the option.  It must be one of bool, tristate,
-string, int, and hex.
-
-<default> is the default value of the option.  It must be appropriate
-value corresponding to the option type.  It must be either y or n for
-the bool type.  Tristate options can also take m (although U-Boot has
-not supported the module feature).
-
-You can add two or more lines in the recipe file, so you can move
-multiple options at once.
-
-Let's say, for example, you want to move CONFIG_CMD_USB and
-CONFIG_SYS_TEXT_BASE.
-
-The type should be bool, hex, respectively.  So, the recipe file
-should look like this:
-
-  $ cat recipe
-  CONFIG_CMD_USB bool n
-  CONFIG_SYS_TEXT_BASE hex 0x00000000
-
-Next you must edit the Kconfig to add the menu entries for the configs
+First, you must edit the Kconfig to add the menu entries for the configs
 you are moving.
 
-And then run this tool giving the file name of the recipe
+And then run this tool giving CONFIG names you want to move.
+For example, if you want to move CONFIG_CMD_USB and CONFIG_SYS_TEXT_BASE,
+simply type as follows:
 
-  $ tools/moveconfig.py recipe
+  $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_SYS_TEXT_BASE
 
-The tool walks through all the defconfig files to move the config
-options specified by the recipe file.
+The tool walks through all the defconfig files and move the given CONFIGs.
 
 The log is also displayed on the terminal.
 
-Each line is printed in the format
-<defconfig_name>   :  <action>
+The log is printed for each defconfig as follows:
 
-<defconfig_name> is the name of the defconfig
-(without the suffix _defconfig).
+<defconfig_name>
+    <action1>
+    <action2>
+    <action3>
+    ...
 
-<action> shows what the tool did for that defconfig.
+<defconfig_name> is the name of the defconfig.
+
+<action*> shows what the tool did for that defconfig.
 It looks like one of the followings:
 
  - Move 'CONFIG_... '
    This config option was moved to the defconfig
 
- - Default value 'CONFIG_...'.  Do nothing.
-   The value of this option is the same as default.
-   We do not have to add it to the defconfig.
+ - CONFIG_... is not defined in Kconfig.  Do nothing.
+   The entry for this CONFIG was not found in Kconfig.
+   There are two common cases:
+     - You forgot to create an entry for the CONFIG before running
+       this tool, or made a typo in a CONFIG passed to this tool.
+     - The entry was hidden due to unmet 'depends on'.
+       This is correct behavior.
 
- - 'CONFIG_...' already exists in Kconfig.  Do nothing.
-   This config option is already defined in Kconfig.
-   We do not need/want to touch it.
+ - 'CONFIG_...' is the same as the define in Kconfig.  Do nothing.
+   The define in the config header matched the one in Kconfig.
+   We do not need to touch it.
 
  - Undefined.  Do nothing.
    This config option was not found in the config header.
    Nothing to do.
 
- - Failed to process.  Skip.
+ - Compiler is missing.  Do nothing.
+   The compiler specified for this architecture was not found
+   in your PATH environment.
+   (If -e option is passed, the tool exits immediately.)
+
+ - Failed to process.
    An error occurred during processing this defconfig.  Skipped.
    (If -e option is passed, the tool exits immediately on error.)
 
@@ -94,19 +79,19 @@ It just uses the regex method, so you should not rely on it.
 Just in case, please do 'git diff' to see what happened.
 
 
-How does it works?
-------------------
+How does it work?
+-----------------
 
 This tool runs configuration and builds include/autoconf.mk for every
 defconfig.  The config options defined in Kconfig appear in the .config
 file (unless they are hidden because of unmet dependency.)
 On the other hand, the config options defined by board headers are seen
 in include/autoconf.mk.  The tool looks for the specified options in both
-of them to decide the appropriate action for the options.  If the option
-is found in the .config or the value is the same as the specified default,
-the option does not need to be touched.  If the option is found in
-include/autoconf.mk, but not in the .config, and the value is different
-from the default, the tools adds the option to the defconfig.
+of them to decide the appropriate action for the options.  If the given
+config option is found in the .config, but its value does not match the
+one from the board header, the config option in the .config is replaced
+with the define in the board header.  Then, the .config is synced by
+"make savedefconfig" and the defconfig is updated with it.
 
 For faster processing, this tool handles multi-threading.  It creates
 separate build directories where the out-of-tree build is run.  The
@@ -139,13 +124,18 @@ Available options
   Specify a file containing a list of defconfigs to move
 
  -n, --dry-run
-   Peform a trial run that does not make any changes.  It is useful to
+   Perform a trial run that does not make any changes.  It is useful to
    see what is going to happen before one actually runs it.
 
  -e, --exit-on-error
    Exit immediately if Make exits with a non-zero status while processing
    a defconfig file.
 
+ -s, --force-sync
+   Do "make savedefconfig" forcibly for all the defconfig files.
+   If not specified, "make savedefconfig" only occurs for cases
+   where at least one CONFIG was moved.
+
  -H, --headers-only
    Only cleanup the headers; skip the defconfig processing
 
@@ -153,6 +143,14 @@ Available options
    Specify the number of threads to run simultaneously.  If not specified,
    the number of threads is the same as the number of CPU cores.
 
+ -r, --git-ref
+   Specify the git ref to clone for building the autoconf.mk. If unspecified
+   use the CWD. This is useful for when changes to the Kconfig affect the
+   default values and you want to capture the state of the defconfig from
+   before that change was in effect. If in doubt, specify a ref pre-Kconfig
+   changes (use HEAD if Kconfig changes are not committed). Worst case it will
+   take a bit longer to run, but will always do the right thing.
+
  -v, --verbose
    Show any build errors as boards are built
 
@@ -162,6 +160,7 @@ To see the complete list of supported options, run
 
 """
 
+import filecmp
 import fnmatch
 import multiprocessing
 import optparse
@@ -211,9 +210,8 @@ STATE_AUTOCONF = 2
 STATE_SAVEDEFCONFIG = 3
 
 ACTION_MOVE = 0
-ACTION_DEFAULT_VALUE = 1
-ACTION_ALREADY_EXIST = 2
-ACTION_UNDEFINED = 3
+ACTION_NO_ENTRY = 1
+ACTION_NO_CHANGE = 2
 
 COLOR_BLACK        = '0;30'
 COLOR_RED          = '0;31'
@@ -247,6 +245,12 @@ def check_top_directory():
         if not os.path.exists(f):
             sys.exit('Please run at the top of source directory.')
 
+def check_clean_directory():
+    """Exit if the source tree is not clean."""
+    for f in ('.config', 'include/config'):
+        if os.path.exists(f):
+            sys.exit("source tree is not clean, please run 'make mrproper'")
+
 def get_make_cmd():
     """Get the command name of GNU Make.
 
@@ -263,16 +267,14 @@ def get_make_cmd():
 def color_text(color_enabled, color, string):
     """Return colored string."""
     if color_enabled:
-        return '\033[' + color + 'm' + string + '\033[0m'
+        # LF should not be surrounded by the escape sequence.
+        # Otherwise, additional whitespace or line-feed might be printed.
+        return '\n'.join([ '\033[' + color + 'm' + s + '\033[0m' if s else ''
+                           for s in string.split('\n') ])
     else:
         return string
 
-def log_msg(color_enabled, color, defconfig, msg):
-    """Return the formated line for the log."""
-    return defconfig[:-len('_defconfig')].ljust(37) + ': ' + \
-        color_text(color_enabled, color, msg) + '\n'
-
-def update_cross_compile():
+def update_cross_compile(color_enabled):
     """Update per-arch CROSS_COMPILE via environment variables
 
     The default CROSS_COMPILE values are available
@@ -286,6 +288,9 @@ def update_cross_compile():
 
     export CROSS_COMPILE_ARM=...
     export CROSS_COMPILE_POWERPC=...
+
+    Then, this function checks if specified compilers really exist in your
+    PATH environment.
     """
     archs = []
 
@@ -299,8 +304,20 @@ def update_cross_compile():
     for arch in archs:
         env = 'CROSS_COMPILE_' + arch.upper()
         cross_compile = os.environ.get(env)
-        if cross_compile:
-            CROSS_COMPILE[arch] = cross_compile
+        if not cross_compile:
+            cross_compile = CROSS_COMPILE.get(arch, '')
+
+        for path in os.environ["PATH"].split(os.pathsep):
+            gcc_path = os.path.join(path, cross_compile + 'gcc')
+            if os.path.isfile(gcc_path) and os.access(gcc_path, os.X_OK):
+                break
+        else:
+            print >> sys.stderr, color_text(color_enabled, COLOR_YELLOW,
+                 'warning: %sgcc: not found in PATH.  %s architecture boards will be skipped'
+                                            % (cross_compile, arch))
+            cross_compile = None
+
+        CROSS_COMPILE[arch] = cross_compile
 
 def cleanup_one_header(header_path, patterns, dry_run):
     """Clean regex-matched lines away from a file.
@@ -331,12 +348,11 @@ def cleanup_one_header(header_path, patterns, dry_run):
             if not i in matched:
                 f.write(line)
 
-def cleanup_headers(config_attrs, dry_run):
+def cleanup_headers(configs, dry_run):
     """Delete config defines from board headers.
 
     Arguments:
-      config_attrs: A list of dictionaris, each of them includes the name,
-                    the type, and the default value of the target config.
+      configs: A list of CONFIGs to remove.
       dry_run: make no changes, but still display log.
     """
     while True:
@@ -349,8 +365,7 @@ def cleanup_headers(config_attrs, dry_run):
         return
 
     patterns = []
-    for config_attr in config_attrs:
-        config = config_attr['config']
+    for config in configs:
         patterns.append(re.compile(r'#\s*define\s+%s\W' % config))
         patterns.append(re.compile(r'#\s*undef\s+%s\W' % config))
 
@@ -362,6 +377,29 @@ def cleanup_headers(config_attrs, dry_run):
                                        patterns, dry_run)
 
 ### classes ###
+class Progress:
+
+    """Progress Indicator"""
+
+    def __init__(self, total):
+        """Create a new progress indicator.
+
+        Arguments:
+          total: A number of defconfig files to process.
+        """
+        self.current = 0
+        self.total = total
+
+    def inc(self):
+        """Increment the number of processed defconfig files."""
+
+        self.current += 1
+
+    def show(self):
+        """Display the progress."""
+        print ' %d defconfigs out of %d\r' % (self.current, self.total),
+        sys.stdout.flush()
+
 class KconfigParser:
 
     """A parser of .config and include/autoconf.mk."""
@@ -369,29 +407,35 @@ class KconfigParser:
     re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
     re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
 
-    def __init__(self, config_attrs, options, build_dir):
+    def __init__(self, configs, options, build_dir):
         """Create a new parser.
 
         Arguments:
-          config_attrs: A list of dictionaris, each of them includes the name,
-                        the type, and the default value of the target config.
+          configs: A list of CONFIGs to move.
           options: option flags.
           build_dir: Build directory.
         """
-        self.config_attrs = config_attrs
+        self.configs = configs
         self.options = options
-        self.build_dir = build_dir
+        self.dotconfig = os.path.join(build_dir, '.config')
+        self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
+        self.config_autoconf = os.path.join(build_dir, 'include', 'config',
+                                            'auto.conf')
+        self.defconfig = os.path.join(build_dir, 'defconfig')
 
     def get_cross_compile(self):
         """Parse .config file and return CROSS_COMPILE.
 
         Returns:
           A string storing the compiler prefix for the architecture.
+          Return a NULL string for architectures that do not require
+          compiler prefix (Sandbox and native build is the case).
+          Return None if the specified compiler is missing in your PATH.
+          Caller should distinguish '' and None.
         """
         arch = ''
         cpu = ''
-        dotconfig = os.path.join(self.build_dir, '.config')
-        for line in open(dotconfig):
+        for line in open(self.dotconfig):
             m = self.re_arch.match(line)
             if m:
                 arch = m.group(1)
@@ -400,15 +444,16 @@ class KconfigParser:
             if m:
                 cpu = m.group(1)
 
-        assert arch, 'Error: arch is not defined in %s' % defconfig
+        if not arch:
+            return None
 
         # fix-up for aarch64
         if arch == 'arm' and cpu == 'armv8':
             arch = 'aarch64'
 
-        return CROSS_COMPILE.get(arch, '')
+        return CROSS_COMPILE.get(arch, None)
 
-    def parse_one_config(self, config_attr, defconfig_lines, autoconf_lines):
+    def parse_one_config(self, config, dotconfig_lines, autoconf_lines):
         """Parse .config, defconfig, include/autoconf.mk for one config.
 
         This function looks for the config options in the lines from
@@ -416,74 +461,72 @@ class KconfigParser:
         which action should be taken for this defconfig.
 
         Arguments:
-          config_attr: A dictionary including the name, the type,
-                       and the default value of the target config.
-          defconfig_lines: lines from the original defconfig file.
+          config: CONFIG name to parse.
+          dotconfig_lines: lines from the .config file.
           autoconf_lines: lines from the include/autoconf.mk file.
 
         Returns:
           A tupple of the action for this defconfig and the line
           matched for the config.
         """
-        config = config_attr['config']
         not_set = '# %s is not set' % config
 
-        if config_attr['type'] in ('bool', 'tristate') and \
-           config_attr['default'] == 'n':
-            default = not_set
-        else:
-            default = config + '=' + config_attr['default']
-
-        for line in defconfig_lines:
+        for line in dotconfig_lines:
             line = line.rstrip()
             if line.startswith(config + '=') or line == not_set:
-                return (ACTION_ALREADY_EXIST, line)
-
-        if config_attr['type'] in ('bool', 'tristate'):
-            value = not_set
+                old_val = line
+                break
         else:
-            value = '(undefined)'
+            return (ACTION_NO_ENTRY, config)
 
         for line in autoconf_lines:
             line = line.rstrip()
             if line.startswith(config + '='):
-                value = line
+                new_val = line
                 break
-
-        if value == default:
-            action = ACTION_DEFAULT_VALUE
-        elif value == '(undefined)':
-            action = ACTION_UNDEFINED
         else:
-            action = ACTION_MOVE
+            new_val = not_set
 
-        return (action, value)
+        if old_val == new_val:
+            return (ACTION_NO_CHANGE, new_val)
 
-    def update_defconfig(self, defconfig):
-        """Parse files for the config options and update the defconfig.
+        # If this CONFIG is neither bool nor trisate
+        if old_val[-2:] != '=y' and old_val[-2:] != '=m' and old_val != not_set:
+            # tools/scripts/define2mk.sed changes '1' to 'y'.
+            # This is a problem if the CONFIG is int type.
+            # Check the type in Kconfig and handle it correctly.
+            if new_val[-2:] == '=y':
+                new_val = new_val[:-1] + '1'
 
-        This function parses the given defconfig, the generated .config
-        and include/autoconf.mk searching the target options.
-        Move the config option(s) to the defconfig or do nothing if unneeded.
-        Also, display the log to show what happened to this defconfig.
+        return (ACTION_MOVE, new_val)
+
+    def update_dotconfig(self):
+        """Parse files for the config options and update the .config.
+
+        This function parses the generated .config and include/autoconf.mk
+        searching the target options.
+        Move the config option(s) to the .config as needed.
 
         Arguments:
           defconfig: defconfig name.
+
+        Returns:
+          Return a tuple of (updated flag, log string).
+          The "updated flag" is True if the .config was updated, False
+          otherwise.  The "log string" shows what happend to the .config.
         """
 
-        defconfig_path = os.path.join('configs', defconfig)
-        dotconfig_path = os.path.join(self.build_dir, '.config')
-        autoconf_path = os.path.join(self.build_dir, 'include', 'autoconf.mk')
         results = []
+        updated = False
 
-        with open(defconfig_path) as f:
-            defconfig_lines = f.readlines()
+        with open(self.dotconfig) as f:
+            dotconfig_lines = f.readlines()
 
-        with open(autoconf_path) as f:
+        with open(self.autoconf) as f:
             autoconf_lines = f.readlines()
 
-        for config_attr in self.config_attrs:
-            result = self.parse_one_config(config_attr, defconfig_lines,
+        for config in self.configs:
+            result = self.parse_one_config(config, dotconfig_lines,
                                            autoconf_lines)
             results.append(result)
 
@@ -493,32 +536,52 @@ class KconfigParser:
             if action == ACTION_MOVE:
                 actlog = "Move '%s'" % value
                 log_color = COLOR_LIGHT_GREEN
-            elif action == ACTION_DEFAULT_VALUE:
-                actlog = "Default value '%s'.  Do nothing." % value
+            elif action == ACTION_NO_ENTRY:
+                actlog = "%s is not defined in Kconfig.  Do nothing." % value
                 log_color = COLOR_LIGHT_BLUE
-            elif action == ACTION_ALREADY_EXIST:
-                actlog = "'%s' already defined in Kconfig.  Do nothing." % value
+            elif action == ACTION_NO_CHANGE:
+                actlog = "'%s' is the same as the define in Kconfig.  Do nothing." \
+                         % value
                 log_color = COLOR_LIGHT_PURPLE
-            elif action == ACTION_UNDEFINED:
-                actlog = "Undefined.  Do nothing."
-                log_color = COLOR_DARK_GRAY
             else:
                 sys.exit("Internal Error. This should not happen.")
 
-            log += log_msg(self.options.color, log_color, defconfig, actlog)
+            log += color_text(self.options.color, log_color, actlog) + '\n'
 
-        # Some threads are running in parallel.
-        # Print log in one shot to not mix up logs from different threads.
-        print log,
+        with open(self.dotconfig, 'a') as f:
+            for (action, value) in results:
+                if action == ACTION_MOVE:
+                    f.write(value + '\n')
+                    updated = True
+
+        self.results = results
+        os.remove(self.config_autoconf)
+        os.remove(self.autoconf)
+
+        return (updated, log)
+
+    def check_defconfig(self):
+        """Check the defconfig after savedefconfig
+
+        Returns:
+          Return additional log if moved CONFIGs were removed again by
+          'make savedefconfig'.
+        """
+
+        log = ''
+
+        with open(self.defconfig) as f:
+            defconfig_lines = f.readlines()
 
-        if not self.options.dry_run:
-            with open(dotconfig_path, 'a') as f:
-                for (action, value) in results:
-                    if action == ACTION_MOVE:
-                        f.write(value + '\n')
+        for (action, value) in self.results:
+            if action != ACTION_MOVE:
+                continue
+            if not value + '\n' in defconfig_lines:
+                log += color_text(self.options.color, COLOR_YELLOW,
+                                  "'%s' was removed by savedefconfig.\n" %
+                                  value)
 
-        os.remove(os.path.join(self.build_dir, 'include', 'config', 'auto.conf'))
-        os.remove(autoconf_path)
+        return log
 
 class Slot:
 
@@ -529,21 +592,25 @@ class Slot:
     for faster processing.
     """
 
-    def __init__(self, config_attrs, options, devnull, make_cmd):
+    def __init__(self, configs, options, progress, devnull, make_cmd, reference_src_dir):
         """Create a new process slot.
 
         Arguments:
-          config_attrs: A list of dictionaris, each of them includes the name,
-                        the type, and the default value of the target config.
+          configs: A list of CONFIGs to move.
           options: option flags.
+          progress: A progress indicator.
           devnull: A file object of '/dev/null'.
           make_cmd: command name of GNU Make.
+          reference_src_dir: Determine the true starting config state from this
+                             source tree.
         """
         self.options = options
+        self.progress = progress
         self.build_dir = tempfile.mkdtemp()
         self.devnull = devnull
         self.make_cmd = (make_cmd, 'O=' + self.build_dir)
-        self.parser = KconfigParser(config_attrs, options, self.build_dir)
+        self.reference_src_dir = reference_src_dir
+        self.parser = KconfigParser(configs, options, self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = []
 
@@ -552,7 +619,7 @@ class Slot:
 
         This function makes sure the temporary directory is cleaned away
         even if Python suddenly dies due to error.  It should be done in here
-        because it is guranteed the destructor is always invoked when the
+        because it is guaranteed the destructor is always invoked when the
         instance of the class gets unreferenced.
 
         If the subprocess is still running, wait until it finishes.
@@ -562,7 +629,7 @@ class Slot:
                 pass
         shutil.rmtree(self.build_dir)
 
-    def add(self, defconfig, num, total):
+    def add(self, defconfig):
         """Assign a new subprocess for defconfig and add it to the slot.
 
         If the slot is vacant, create a new subprocess for processing the
@@ -577,14 +644,11 @@ class Slot:
         """
         if self.state != STATE_IDLE:
             return False
-        cmd = list(self.make_cmd)
-        cmd.append(defconfig)
-        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   stderr=subprocess.PIPE)
+
         self.defconfig = defconfig
-        self.state = STATE_DEFCONFIG
-        self.num = num
-        self.total = total
+        self.log = ''
+        self.use_git_ref = True if self.options.git_ref else False
+        self.do_defconfig()
         return True
 
     def poll(self):
@@ -594,8 +658,11 @@ class Slot:
         If the configuration is successfully finished, assign a new
         subprocess to build include/autoconf.mk.
         If include/autoconf.mk is generated, invoke the parser to
-        parse the .config and the include/autoconf.mk, and then set the
-        slot back to the idle state.
+        parse the .config and the include/autoconf.mk, moving
+        config options to the .config as needed.
+        If the .config was updated, run "make savedefconfig" to sync
+        it, update the original defconfig, and then set the slot back
+        to the idle state.
 
         Returns:
           Return True if the subprocess is terminated, False otherwise
@@ -607,65 +674,131 @@ class Slot:
             return False
 
         if self.ps.poll() != 0:
-            errmsg = 'Failed to process.'
-            errout = self.ps.stderr.read()
-            if errout.find('gcc: command not found') != -1:
-                errmsg = 'Compiler not found ('
-                errmsg += color_text(self.options.color, COLOR_YELLOW,
-                                     self.cross_compile)
-                errmsg += color_text(self.options.color, COLOR_LIGHT_RED,
-                                     ')')
-            print >> sys.stderr, log_msg(self.options.color,
-                                         COLOR_LIGHT_RED,
-                                         self.defconfig,
-                                         errmsg),
-            if self.options.verbose:
-                print >> sys.stderr, color_text(self.options.color,
-                                                COLOR_LIGHT_CYAN, errout)
-            if self.options.exit_on_error:
-                sys.exit("Exit on error.")
+            self.handle_error()
+        elif self.state == STATE_DEFCONFIG:
+            if self.options.git_ref and not self.use_git_ref:
+                self.do_savedefconfig()
             else:
-                # If --exit-on-error flag is not set,
-                # skip this board and continue.
-                # Record the failed board.
-                self.failed_boards.append(self.defconfig)
-                self.state = STATE_IDLE
-                return True
+                self.do_autoconf()
+        elif self.state == STATE_AUTOCONF:
+            if self.use_git_ref:
+                self.use_git_ref = False
+                self.do_defconfig()
+            else:
+                self.do_savedefconfig()
+        elif self.state == STATE_SAVEDEFCONFIG:
+            self.update_defconfig()
+        else:
+            sys.exit("Internal Error. This should not happen.")
 
-        if self.state == STATE_AUTOCONF:
-            self.parser.update_defconfig(self.defconfig)
+        return True if self.state == STATE_IDLE else False
 
-            print ' %d defconfigs out of %d\r' % (self.num + 1, self.total),
-            sys.stdout.flush()
+    def handle_error(self):
+        """Handle error cases."""
 
-            """Save off the defconfig in a consistent way"""
-            cmd = list(self.make_cmd)
-            cmd.append('savedefconfig')
-            self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                       stderr=subprocess.PIPE)
-            self.state = STATE_SAVEDEFCONFIG
-            return False
+        self.log += color_text(self.options.color, COLOR_LIGHT_RED,
+                               "Failed to process.\n")
+        if self.options.verbose:
+            self.log += color_text(self.options.color, COLOR_LIGHT_CYAN,
+                                   self.ps.stderr.read())
+        self.finish(False)
 
-        if self.state == STATE_SAVEDEFCONFIG:
-            defconfig_path = os.path.join(self.build_dir, 'defconfig')
-            shutil.move(defconfig_path,
-                        os.path.join('configs', self.defconfig))
-            self.state = STATE_IDLE
-            return True
+    def do_defconfig(self):
+        """Run 'make <board>_defconfig' to create the .config file."""
+
+        cmd = list(self.make_cmd)
+        cmd.append(self.defconfig)
+        if self.use_git_ref:
+            cmd.append('-C')
+            cmd.append(self.reference_src_dir)
+        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+                                   stderr=subprocess.PIPE)
+        self.state = STATE_DEFCONFIG
+
+    def do_autoconf(self):
+        """Run 'make include/config/auto.conf'."""
 
         self.cross_compile = self.parser.get_cross_compile()
+        if self.cross_compile is None:
+            self.log += color_text(self.options.color, COLOR_YELLOW,
+                                   "Compiler is missing.  Do nothing.\n")
+            self.finish(False)
+            return
+
         cmd = list(self.make_cmd)
         if self.cross_compile:
             cmd.append('CROSS_COMPILE=%s' % self.cross_compile)
         cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
         cmd.append('include/config/auto.conf')
-        """This will be screen-scraped, so be sure the expected text will be
-        returned consistently on every machine by setting LANG=C"""
+        if self.use_git_ref:
+            cmd.append('-C')
+            cmd.append(self.reference_src_dir)
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   env=dict(os.environ, LANG='C'),
                                    stderr=subprocess.PIPE)
         self.state = STATE_AUTOCONF
-        return False
+
+    def do_savedefconfig(self):
+        """Update the .config and run 'make savedefconfig'."""
+
+        (updated, log) = self.parser.update_dotconfig()
+        self.log += log
+
+        if not self.options.force_sync and not updated:
+            self.finish(True)
+            return
+        if updated:
+            self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+                                   "Syncing by savedefconfig...\n")
+        else:
+            self.log += "Syncing by savedefconfig (forced by option)...\n"
+
+        cmd = list(self.make_cmd)
+        cmd.append('savedefconfig')
+        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+                                   stderr=subprocess.PIPE)
+        self.state = STATE_SAVEDEFCONFIG
+
+    def update_defconfig(self):
+        """Update the input defconfig and go back to the idle state."""
+
+        self.log += self.parser.check_defconfig()
+        orig_defconfig = os.path.join('configs', self.defconfig)
+        new_defconfig = os.path.join(self.build_dir, 'defconfig')
+        updated = not filecmp.cmp(orig_defconfig, new_defconfig)
+
+        if updated:
+            self.log += color_text(self.options.color, COLOR_LIGHT_BLUE,
+                                   "defconfig was updated.\n")
+
+        if not self.options.dry_run and updated:
+            shutil.move(new_defconfig, orig_defconfig)
+        self.finish(True)
+
+    def finish(self, success):
+        """Display log along with progress and go to the idle state.
+
+        Arguments:
+          success: Should be True when the defconfig was processed
+                   successfully, or False when it fails.
+        """
+        # output at least 30 characters to hide the "* defconfigs out of *".
+        log = self.defconfig.ljust(30) + '\n'
+
+        log += '\n'.join([ '    ' + s for s in self.log.split('\n') ])
+        # Some threads are running in parallel.
+        # Print log atomically to not mix up logs from different threads.
+        print >> (sys.stdout if success else sys.stderr), log
+
+        if not success:
+            if self.options.exit_on_error:
+                sys.exit("Exit on error.")
+            # If --exit-on-error flag is not set, skip this board and continue.
+            # Record the failed board.
+            self.failed_boards.append(self.defconfig)
+
+        self.progress.inc()
+        self.progress.show()
+        self.state = STATE_IDLE
 
     def get_failed_boards(self):
         """Returns a list of failed boards (defconfigs) in this slot.
@@ -676,22 +809,25 @@ class Slots:
 
     """Controller of the array of subprocess slots."""
 
-    def __init__(self, config_attrs, options):
+    def __init__(self, configs, options, progress, reference_src_dir):
         """Create a new slots controller.
 
         Arguments:
-          config_attrs: A list of dictionaris containing the name, the type,
-                        and the default value of the target CONFIG.
+          configs: A list of CONFIGs to move.
           options: option flags.
+          progress: A progress indicator.
+          reference_src_dir: Determine the true starting config state from this
+                             source tree.
         """
         self.options = options
         self.slots = []
         devnull = get_devnull()
         make_cmd = get_make_cmd()
         for i in range(options.jobs):
-            self.slots.append(Slot(config_attrs, options, devnull, make_cmd))
+            self.slots.append(Slot(configs, options, progress, devnull,
+                                   make_cmd, reference_src_dir))
 
-    def add(self, defconfig, num, total):
+    def add(self, defconfig):
         """Add a new subprocess if a vacant slot is found.
 
         Arguments:
@@ -701,7 +837,7 @@ class Slots:
           Return True on success or False on failure
         """
         for slot in self.slots:
-            if slot.add(defconfig, num, total):
+            if slot.add(defconfig):
                 return True
         return False
 
@@ -746,23 +882,54 @@ class Slots:
                 for board in failed_boards:
                     f.write(board + '\n')
 
-def move_config(config_attrs, options):
+class WorkDir:
+    def __init__(self):
+        """Create a new working directory."""
+        self.work_dir = tempfile.mkdtemp()
+
+    def __del__(self):
+        """Delete the working directory
+
+        This function makes sure the temporary directory is cleaned away
+        even if Python suddenly dies due to error.  It should be done in here
+        because it is guaranteed the destructor is always invoked when the
+        instance of the class gets unreferenced.
+        """
+        shutil.rmtree(self.work_dir)
+
+    def get(self):
+        return self.work_dir
+
+def move_config(configs, options):
     """Move config options to defconfig files.
 
     Arguments:
-      config_attrs: A list of dictionaris, each of them includes the name,
-                    the type, and the default value of the target config.
+      configs: A list of CONFIGs to move.
       options: option flags
     """
-    if len(config_attrs) == 0:
-        print 'Nothing to do. exit.'
-        sys.exit(0)
-
-    print 'Move the following CONFIG options (jobs: %d)' % options.jobs
-    for config_attr in config_attrs:
-        print '  %s (type: %s, default: %s)' % (config_attr['config'],
-                                                config_attr['type'],
-                                                config_attr['default'])
+    if len(configs) == 0:
+        if options.force_sync:
+            print 'No CONFIG is specified. You are probably syncing defconfigs.',
+        else:
+            print 'Neither CONFIG nor --force-sync is specified. Nothing will happen.',
+    else:
+        print 'Move ' + ', '.join(configs),
+    print '(jobs: %d)\n' % options.jobs
+
+    reference_src_dir = ''
+
+    if options.git_ref:
+        work_dir = WorkDir()
+        reference_src_dir = work_dir.get()
+        print "Cloning git repo to a separate work directory..."
+        subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
+                                cwd=reference_src_dir)
+        print "Checkout '%s' to build the original autoconf.mk." % \
+            subprocess.check_output(['git', 'rev-parse', '--short',
+                                    options.git_ref]).strip()
+        subprocess.check_output(['git', 'checkout', options.git_ref],
+                                stderr=subprocess.STDOUT,
+                                cwd=reference_src_dir)
 
     if options.defconfigs:
         defconfigs = [line.strip() for line in open(options.defconfigs)]
@@ -780,13 +947,14 @@ def move_config(config_attrs, options):
             for filename in fnmatch.filter(filenames, '*_defconfig'):
                 defconfigs.append(os.path.join(dirpath, filename))
 
-    slots = Slots(config_attrs, options)
+    progress = Progress(len(defconfigs))
+    slots = Slots(configs, options, progress, reference_src_dir)
 
     # Main loop to process defconfig files:
     #  Add a new subprocess into a vacant slot.
     #  Sleep if there is no available slot.
-    for i, defconfig in enumerate(defconfigs):
-        while not slots.add(defconfig, i, len(defconfigs)):
+    for defconfig in defconfigs:
+        while not slots.add(defconfig):
             while not slots.available():
                 # No available slot: sleep for a while
                 time.sleep(SLEEP_TIME)
@@ -798,76 +966,6 @@ def move_config(config_attrs, options):
     print ''
     slots.show_failed_boards()
 
-def bad_recipe(filename, linenum, msg):
-    """Print error message with the file name and the line number and exit."""
-    sys.exit("%s: line %d: error : " % (filename, linenum) + msg)
-
-def parse_recipe(filename):
-    """Parse the recipe file and retrieve the config attributes.
-
-    This function parses the given recipe file and gets the name,
-    the type, and the default value of the target config options.
-
-    Arguments:
-      filename: path to file to be parsed.
-    Returns:
-      A list of dictionaris, each of them includes the name,
-      the type, and the default value of the target config.
-    """
-    config_attrs = []
-    linenum = 1
-
-    for line in open(filename):
-        tokens = line.split()
-        if len(tokens) != 3:
-            bad_recipe(filename, linenum,
-                       "%d fields in this line.  Each line must contain 3 fields"
-                       % len(tokens))
-
-        (config, type, default) = tokens
-
-        # prefix the option name with CONFIG_ if missing
-        if not config.startswith('CONFIG_'):
-            config = 'CONFIG_' + config
-
-        # sanity check of default values
-        if type == 'bool':
-            if not default in ('y', 'n'):
-                bad_recipe(filename, linenum,
-                           "default for bool type must be either y or n")
-        elif type == 'tristate':
-            if not default in ('y', 'm', 'n'):
-                bad_recipe(filename, linenum,
-                           "default for tristate type must be y, m, or n")
-        elif type == 'string':
-            if default[0] != '"' or default[-1] != '"':
-                bad_recipe(filename, linenum,
-                           "default for string type must be surrounded by double-quotations")
-        elif type == 'int':
-            try:
-                int(default)
-            except:
-                bad_recipe(filename, linenum,
-                           "type is int, but default value is not decimal")
-        elif type == 'hex':
-            if len(default) < 2 or default[:2] != '0x':
-                bad_recipe(filename, linenum,
-                           "default for hex type must be prefixed with 0x")
-            try:
-                int(default, 16)
-            except:
-                bad_recipe(filename, linenum,
-                           "type is hex, but default value is not hexadecimal")
-        else:
-            bad_recipe(filename, linenum,
-                       "unsupported type '%s'. type must be one of bool, tristate, string, int, hex"
-                       % type)
-
-        config_attrs.append({'config': config, 'type': type, 'default': default})
-        linenum += 1
-
-    return config_attrs
-
 def main():
     try:
         cpu_count = multiprocessing.cpu_count()
@@ -885,37 +983,40 @@ def main():
     parser.add_option('-e', '--exit-on-error', action='store_true',
                       default=False,
                       help='exit immediately on any error')
+    parser.add_option('-s', '--force-sync', action='store_true', default=False,
+                      help='force sync by savedefconfig')
     parser.add_option('-H', '--headers-only', dest='cleanup_headers_only',
                       action='store_true', default=False,
                       help='only cleanup the headers')
     parser.add_option('-j', '--jobs', type='int', default=cpu_count,
                       help='the number of jobs to run simultaneously')
+    parser.add_option('-r', '--git-ref', type='string',
+                      help='the git ref to clone for building the autoconf.mk')
     parser.add_option('-v', '--verbose', action='store_true', default=False,
                       help='show any build errors as boards are built')
-    parser.usage += ' recipe_file\n\n' + \
-                    'The recipe_file should describe config options you want to move.\n' + \
-                    'Each line should contain config_name, type, default_value\n\n' + \
-                    'Example:\n' + \
-                    'CONFIG_FOO bool n\n' + \
-                    'CONFIG_BAR int 100\n' + \
-                    'CONFIG_BAZ string "hello"\n'
+    parser.usage += ' CONFIG ...'
 
-    (options, args) = parser.parse_args()
+    (options, configs) = parser.parse_args()
 
-    if len(args) != 1:
+    if len(configs) == 0 and not options.force_sync:
         parser.print_usage()
         sys.exit(1)
 
-    config_attrs = parse_recipe(args[0])
-
-    update_cross_compile()
+    # prefix the option name with CONFIG_ if missing
+    configs = [ config if config.startswith('CONFIG_') else 'CONFIG_' + config
+                for config in configs ]
 
     check_top_directory()
 
+    check_clean_directory()
+
+    update_cross_compile(options.color)
+
     if not options.cleanup_headers_only:
-        move_config(config_attrs, options)
+        move_config(configs, options)
 
-    cleanup_headers(config_attrs, options.dry_run)
+    if configs:
+        cleanup_headers(configs, options.dry_run)
 
 if __name__ == '__main__':
     main()

diff --git a/tools/scripts/define2mk.sed b/tools/scripts/define2mk.sed
index c641edfb0194ba81195e930b668c6250c90072d8..0f00285f367e4c1d429aee1f8e8b069a054c2280 100644 (file)
--- a/tools/scripts/define2mk.sed
+++ b/tools/scripts/define2mk.sed
@@ -22,6 +22,8 @@
        s/=\(..*\)/="\1"/;
        # but remove again from decimal numbers
        s/="\([0-9][0-9]*\)"/=\1/;
+       # ... and from negative decimal numbers
+       s/="\(-[1-9][0-9]*\)"/=\1/;
        # ... and from hex numbers
        s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
        # ... and from configs defined from other configs