]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
Convert CONFIG_EMIF4 et al to Kconfig
authorAdam Ford <aford173@gmail.com>
Tue, 12 Sep 2017 20:27:33 +0000 (15:27 -0500)
committerTom Rini <trini@konsulko.com>
Wed, 13 Sep 2017 13:24:27 +0000 (09:24 -0400)
This converts the following to Kconfig:
   CONFIG_EMIF4
   CONFIG_SDRC

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefano Babic <sbabic@denx.de>
20 files changed:
arch/arm/mach-omap2/omap3/Kconfig
configs/am3517_crane_defconfig
configs/am3517_evm_defconfig
configs/cm_t3517_defconfig
configs/eco5pk_defconfig
configs/mcx_defconfig
configs/mt_ventoux_defconfig
configs/twister_defconfig
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/cm_t35.h
include/configs/cm_t3517.h
include/configs/mcx.h
include/configs/nokia_rx51.h
include/configs/sniper.h
include/configs/tam3517-common.h
include/configs/tao3530.h
include/configs/ti_omap3_common.h
include/configs/tricorder.h
scripts/config_whitelist.txt

index cc2c4cd1242b5fe5e3598d4b8b7f509f81f862c0..11f5f058b9e0c4772da7fd90c06570d16ba070f5 100644 (file)
@@ -150,6 +150,21 @@ config TARGET_SNIPER
 
 endchoice
 
+choice
+       prompt "Memory Controller"
+       default SDRC
+
+config SDRC
+       bool "SDRC controller"
+       help
+         The default memory controller on most OMAP3 boards is SDRC.
+
+config EMIF4
+       bool "EMIF4 controller"
+       help
+         Enable this on boards like AM3517 which use EMIF4 controller
+endchoice
+
 config SPL_OMAP3_ID_NAND
        bool "Support OMAP3-specific ID and MFR function"
        help
index 42260b1db2a3c88fd6f38484b84ab2fb53ef24ce..516ac2de3f04b764e1d6f0a5932811d1087244c3 100644 (file)
@@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80100000
 # CONFIG_SPL_GPIO_SUPPORT is not set
 CONFIG_TARGET_AM3517_CRANE=y
+CONFIG_EMIF4=y
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 # CONFIG_SPL_EXT_SUPPORT is not set
index b3e89eb016efc5ca11e3f15862345828869ea96a..920c61c39174185812b121b38cbf9ac40d3b24fd 100644 (file)
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x80100000
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 # CONFIG_SPL_GPIO_SUPPORT is not set
 CONFIG_TARGET_AM3517_EVM=y
+CONFIG_EMIF4=y
 CONFIG_BOOTDELAY=10
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
index ba7d813d7e823ebd6a0094de555e838ae0d78f28..4df40d6dfdb28b0db7c771ee1e7ab50e1b979379 100644 (file)
@@ -3,6 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80008000
 CONFIG_TARGET_CM_T3517=y
+CONFIG_EMIF4=y
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
index ed329307b1f11ccfb201ab567abf2e98bdc2116e..2bf48e0199215a228678b6869890e45fc3cdd5b1 100644 (file)
@@ -3,6 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80008000
 CONFIG_TARGET_ECO5PK=y
+CONFIG_EMIF4=y
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 # CONFIG_SPL_EXT_SUPPORT is not set
index c36cef8fd4b908d63cfd4f0fc399a0c832729d22..972cb637f591fae455f5981622f721cc65cf95ab 100644 (file)
@@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80008000
 # CONFIG_SPL_GPIO_SUPPORT is not set
 CONFIG_TARGET_MCX=y
+CONFIG_EMIF4=y
 CONFIG_VIDEO=y
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
index 09580e7b32b9f980905d754f65b13f2370233624..316e4f0b8432334ccc493ca44236569d5a9ea79d 100644 (file)
@@ -3,6 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80008000
 CONFIG_TARGET_MT_VENTOUX=y
+CONFIG_EMIF4=y
 CONFIG_VIDEO=y
 CONFIG_BOOTDELAY=10
 # CONFIG_CONSOLE_MUX is not set
index 7bbf78188dba5e1b286652c3cf425298e2854515..53edadb6481153aabdbae7a237b712ec8bd4633e 100644 (file)
@@ -3,6 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80008000
 CONFIG_TARGET_TWISTER=y
+CONFIG_EMIF4=y
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 # CONFIG_SPL_EXT_SUPPORT is not set
index c5fe3dcba63ac129dbd64d5289d6039bf042d3b4..db75fe547a34dfb48335d202fba1857c7ecd02be 100644 (file)
@@ -16,7 +16,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
index b13381dc722a58884d00e49bdebaf3dd5209f050..708a98f8270948e9edbe772528c1520e1e1061ef 100644 (file)
@@ -14,7 +14,6 @@
 #define __CONFIG_H
 
 #define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
-#define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 /*
  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
index 30e20b865997b9626689e12c95ce81a4b378412e..6e7dcc66de711817f292baabea6f04dd3c021506 100644 (file)
@@ -24,8 +24,6 @@
  */
 #define CONFIG_CM_T3X  /* working with CM-T35 and CM-T3730 */
 
-#define CONFIG_SDRC    /* The chip has SDRC controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 
index c166bf7c625675eddd4c36a3ca1f4a13f3eeaf1a..b44777fc9829ac0e3ef1fba6cf0a24fa7ba3d78f 100644 (file)
@@ -23,8 +23,6 @@
  * to be on the safe side once the default is changed.
  */
 
-#define CONFIG_EMIF4   /* The chip has EMIF4 controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 
index fb35f97ab30c7940b16ad7937e363560232a3a52..2a77430e7cea8d01c2576045fafe522576f8695d 100644 (file)
@@ -15,8 +15,6 @@
 
 #define CONFIG_MACH_TYPE       MACH_TYPE_MCX
 
-#define CONFIG_EMIF4   /* The chip has EMIF4 controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 
index 8e1effad34f53a867c0588ee251fa371618cda90..20b8c345f06620210d4852f547b1e64c54e48904 100644 (file)
@@ -33,8 +33,6 @@
  */
 #define CONFIG_SYS_TEXT_BASE   0x80008000
 
-#define CONFIG_SDRC                    /* The chip has SDRC controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 #include <asm/arch/mem.h>
index 5997902961c5f2cb1e891c6c2018cb5fcb3b4895..580994280b113ed388f72aa934eff5a77b591841 100644 (file)
@@ -39,7 +39,6 @@
  * DRAM
  */
 
-#define CONFIG_SDRC
 #define CONFIG_NR_DRAM_BANKS   2
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
index 2363912de1169408510097ec6df08444082a13ac..ba8483f0bf9ae6a710bdc6cb0001a851941d3ba5 100644 (file)
@@ -16,8 +16,6 @@
 
 #define CONFIG_SYS_TEXT_BASE 0x80008000
 
-#define CONFIG_EMIF4   /* The chip has EMIF4 controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 
index 7f4acbae34ccf37e4d094e16fbc44c2201c02003..b4311d94cc2a90c41dd281ec77e7234f6e004580 100644 (file)
@@ -17,8 +17,6 @@
  * High Level Configuration Options
  */
 
-#define CONFIG_SDRC                    /* Has an SDRC controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 
index 938136c94629fa6fc34bfc8709f7d489b0d6241b..531bffca8c3974131286973895f079b8b80a2e20 100644 (file)
@@ -21,9 +21,6 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/omap.h>
 
-/* The chip has SDRC controller */
-#define CONFIG_SDRC
-
 /* Clock Defines */
 #define V_OSCK                 26000000        /* Clock output from T2 */
 #define V_SCLK                 (V_OSCK >> 1)
index 46bb6f445ee94f0fc1541c7727c18eff657590ef..33071ef507b9d99715098dc1348b89f5b4be9cc3 100644 (file)
@@ -25,8 +25,6 @@
  */
 #define CONFIG_SYS_TEXT_BASE           0x80100000
 
-#define CONFIG_SDRC                    /* The chip has SDRC controller */
-
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
 
index 0368f2c3b892626d810e6555ef021efcfdc6ddc7..56bb639091f388e97991c21504b6e0d0780f443d 100644 (file)
@@ -562,7 +562,6 @@ CONFIG_EHCI_MMIO_BIG_ENDIAN
 CONFIG_EHCI_MXS_PORT0
 CONFIG_EHCI_MXS_PORT1
 CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-CONFIG_EMIF4
 CONFIG_EMMC_BOOT
 CONFIG_EMU
 CONFIG_ENABLE_36BIT_PHYS
@@ -1973,7 +1972,6 @@ CONFIG_SCSI_DEV_LIST
 CONFIG_SC_TIMER_CLK
 CONFIG_SDCARD
 CONFIG_SDRAM_OFFSET_FOR_RT
-CONFIG_SDRC
 CONFIG_SD_BOOT_QSPI
 CONFIG_SECBOOT
 CONFIG_SECURE_BL1_ONLY