LIBS += post/libpost.a post/drivers/libpostdrivers.a
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
+LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
+ "post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
#########################################################################
#########################################################################
- ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
+ ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
all: $(ALL)
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
+ $(obj)u-boot.sha1: $(obj)u-boot.bin
+ ./tools/ubsha1 $(obj)u-boot.bin
+
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
luan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
+lwmon5_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
+
METROBOX_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
$(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
$(obj)examples/test_burst
rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
- $(obj)tools/gen_eth_addr
+ $(obj)tools/gen_eth_addr $(obj)tools/ubsha1
rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h
rm -fr $(obj)*.*~
rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
- rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
+ rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c $(obj)tools/sha1.c
rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
[ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
#include <common.h>
#include <ppc4xx.h>
+ #include <malloc.h>
+ #include <command.h>
+ #include <crc.h>
#include <asm/processor.h>
#include <spd_sdram.h>
+ #include <status_led.h>
+ #include <sha1.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
- static void set_leds(int val)
+ unsigned char sha1_checksum[SHA1_SUM_LEN];
+
+ /* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
+ unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+ 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
+
+ static void set_leds (int val)
+ {
+ out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
+ }
+
+ #define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
+
+ void __led_init (led_id_t mask, int state)
+ {
+ int val = GET_LEDS;
+
+ if (state == STATUS_LED_ON)
+ val |= mask;
+ else
+ val &= ~mask;
+ set_leds (val);
+ }
+
+ void __led_set (led_id_t mask, int state)
+ {
+ int val = GET_LEDS;
+
+ if (state == STATUS_LED_ON)
+ val |= mask;
+ else if (state == STATUS_LED_OFF)
+ val &= ~mask;
+ set_leds (val);
+ }
+
+ void __led_toggle (led_id_t mask)
{
- unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
- 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
- out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
+ int val = GET_LEDS;
+
+ val ^= mask;
+ set_leds (val);
}
+ static void status_led_blink (void)
+ {
+ int i;
+ int val = GET_LEDS;
+
+ /* set all LED which are on, to state BLINKING */
+ for (i = 0; i < 4; i++) {
+ if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING);
+ val = val << 1;
+ }
+ }
+
+ #if defined(CONFIG_SHOW_BOOT_PROGRESS)
+ void show_boot_progress (int val)
+ {
+ /* find all valid Codes for val in README */
+ if (val == -30) return;
+ if (val < 0) {
+ /* smthing goes wrong */
+ status_led_blink ();
+ return;
+ }
+ switch (val) {
+ case 1:
+ /* validating Image */
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ case 15:
+ /* booting */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_ON);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ case 64:
+ /* starting Ethernet configuration */
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_OFF);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ case 80:
+ /* loading Image */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_OFF);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ }
+ }
+ #endif
+
int board_early_init_f(void)
{
register uint reg;
return 0;
}
+ #define EEPROM_LEN 256
+ void load_sernum_ethaddr (void)
+ {
+ int ret;
+ char buf[EEPROM_LEN];
+ char mac[32];
+ char *use_eeprom;
+ u16 checksumcrc16 = 0;
+
+ /* read the MACs from EEprom */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_ON);
+ ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
+ if (ret == 0) {
+ checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2);
+ /* check, if the EEprom is programmed:
+ * - The Prefix(Byte 0,1,2) is equal to "ATR"
+ * - The checksum, stored in the last 2 Bytes, is correct
+ */
+ if ((strncmp (buf,"ATR",3) != 0) ||
+ ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
+ ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1]))
+ {
+ /* EEprom is not programmed */
+ printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
+ } else {
+ /* get the MACs */
+ sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
+ buf[3],
+ buf[4],
+ buf[5],
+ buf[6],
+ buf[7],
+ buf[8]);
+ setenv ("ethaddr", (char *) mac);
+ sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
+ buf[9],
+ buf[10],
+ buf[11],
+ buf[12],
+ buf[13],
+ buf[14]);
+ setenv ("eth1addr", (char *) mac);
+ return;
+ }
+ }
+
+ /* some error reading the EEprom */
+ if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
+ /* dont use bootcmd */
+ setenv("bootdelay", "-1");
+ return;
+ }
+ /* == default ? use standard */
+ if (strncmp (use_eeprom, "default", 7) == 0) {
+ return;
+ }
+ /* Env doesnt exist -> hang */
+ status_led_blink ();
+ hang ();
+ return;
+ }
+
+ #ifdef CONFIG_PREBOOT
+
+ static uchar kbd_magic_prefix[] = "key_magic";
+ static uchar kbd_command_prefix[] = "key_cmd";
+
+ struct kbd_data_t {
+ char s1;
+ char s2;
+ };
+
+ struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+ {
+ char *val;
+ unsigned long tmp;
+
+ /* use the DIPs for some bootoptions */
+ val = getenv (ENV_NAME_DIP);
+ tmp = simple_strtoul (val, NULL, 16);
+
+ kbd_data->s2 = (tmp & 0x0f);
+ kbd_data->s1 = (tmp & 0xf0) >> 4;
+ return kbd_data;
+ }
+
+ static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+ {
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1) return -1;
+
+ s1 = str[1];
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s2) return -1;
+ return 0;
+ }
+
+ static char *key_match (const struct kbd_data_t *kbd_data)
+ {
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ if (compare_magic (kbd_data, getenv (magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv (cmd_name);
+
+ return (cmd);
+ }
+ }
+ return (NULL);
+ }
+
+ #endif /* CONFIG_PREBOOT */
+
+ static int pcs440ep_readinputs (void)
+ {
+ int i;
+ char value[20];
+
+ /* read the inputs and set the Envvars */
+ /* Revision Level Bit 26 - 29 */
+ i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
+ i = swapbits[i];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_REVLEV, value);
+ /* Solder Switch Bit 30 - 33 */
+ i = (in32 (GPIO0_IR) & 0x00000003) << 2;
+ i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
+ i = swapbits[i];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_SOLDER, value);
+ /* DIP Switch Bit 49 - 56 */
+ i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
+ i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_DIP, value);
+ return 0;
+ }
+
+
+ #if defined(CONFIG_SHA1_CHECK_UB_IMG)
+ /*************************************************************************
+ * calculate a SHA1 sum for the U-Boot image in Flash.
+ *
+ ************************************************************************/
+ static int pcs440ep_sha1 (int docheck)
+ {
+ unsigned char *data;
+ unsigned char *ptroff;
+ unsigned char output[20];
+ unsigned char org[20];
+ int i, len = CONFIG_SHA1_LEN;
+
+ memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
+ data = (unsigned char *)CFG_LOAD_ADDR;
+ ptroff = &data[len + SHA1_SUM_POS];
+
+ for (i = 0; i < SHA1_SUM_LEN; i++) {
+ org[i] = ptroff[i];
+ ptroff[i] = 0;
+ }
+
+ sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
+
+ if (docheck == 2) {
+ for (i = 0; i < 20 ; i++) {
+ printf("%02X ", output[i]);
+ }
+ printf("\n");
+ }
+ if (docheck == 1) {
+ for (i = 0; i < 20 ; i++) {
+ if (org[i] != output[i]) return 1;
+ }
+ }
+ return 0;
+ }
+
+ /*************************************************************************
+ * do some checks after the SHA1 checksum from the U-Boot Image was
+ * calculated.
+ *
+ ************************************************************************/
+ static void pcs440ep_checksha1 (void)
+ {
+ int ret;
+ char *cs_test;
+
+ ret = pcs440ep_sha1 (1);
+ if (ret == 0) return;
+
+ if ((cs_test = getenv ("cs_test")) == NULL) {
+ /* Env doesnt exist -> hang */
+ status_led_blink ();
+ hang ();
+ }
+
+ if (strncmp (cs_test, "off", 3) == 0) {
+ printf ("SHA1 U-Boot sum NOT ok!\n");
+ setenv ("bootdelay", "-1");
+ }
+ }
+ #else
+ static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
+ #endif
+
int misc_init_r (void)
{
uint pbcr;
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[1]);
+ pcs440ep_readinputs ();
+ pcs440ep_checksha1 ();
+ #ifdef CONFIG_PREBOOT
+ {
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup (key_match (get_keys (&kbd_data)));
+ /* Set or delete definition */
+ setenv ("preboot", str);
+ free (str);
+ }
+ #endif /* CONFIG_PREBOOT */
return 0;
}
return (0);
}
+ void spd_ddr_init_hang (void)
+ {
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ /* we cannot use hang() because we are still running from
+ Flash, and so the status_led driver is not initialized */
+ puts ("### ERROR ### Please RESET the board ###\n");
+ for (;;) {
+ __led_toggle (4);
+ udelay (100000);
+ }
+ }
+
long int initdram (int board_type)
{
long dram_size = 0;
- set_leds(1); /* display boot info counter */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_OFF);
dram_size = spd_sdram();
- set_leds(2); /* display boot info counter */
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ if (dram_size == 0) {
+ hang();
+ }
return dram_size;
}
* certain pre-initialization actions.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
return 1;
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
}
#endif
+
+ /*************************************************************************
+ * "led" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ {
+ int rcode = 0;
+ ulong pattern = 0;
+
+ pattern = simple_strtoul (argv[1], NULL, 10);
+ if (pattern > 200) {
+ status_led_blink ();
+ hang ();
+ return rcode;
+ }
+ if (pattern > 100) {
+ status_led_blink ();
+ return rcode;
+ }
+ pattern &= 0x0f;
+ set_leds (pattern);
+ return rcode;
+ }
+
+ U_BOOT_CMD(
+ led, 2, 1, do_led,
+ "led - set the led\n",
+ NULL
+ );
+
+ #if defined(CONFIG_SHA1_CHECK_UB_IMG)
+ /*************************************************************************
+ * "sha1" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ {
+ int rcode = -1;
+
+ if (argc < 2) {
+ usage:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (argc >= 3) {
+ unsigned char *data;
+ unsigned char output[20];
+ int len;
+ int i;
+
+ data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
+ len = simple_strtoul (argv[2], NULL, 16);
+ sha1_csum (data, len, (unsigned char *)output);
+ printf ("U-Boot sum:\n");
+ for (i = 0; i < 20 ; i++) {
+ printf ("%02X ", output[i]);
+ }
+ printf ("\n");
+ if (argc == 4) {
+ data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
+ memcpy (data, output, 20);
+ }
+ return 0;
+ }
+ if (argc == 2) {
+ char *ptr = argv[1];
+ if (*ptr != '-') goto usage;
+ ptr++;
+ if ((*ptr == 'c') || (*ptr == 'C')) {
+ rcode = pcs440ep_sha1 (1);
+ printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
+ } else if ((*ptr == 'p') || (*ptr == 'P')) {
+ rcode = pcs440ep_sha1 (2);
+ } else {
+ rcode = pcs440ep_sha1 (0);
+ }
+ return rcode;
+ }
+ return rcode;
+ }
+
+ U_BOOT_CMD(
+ sha1, 4, 1, do_sha1,
+ "sha1 - calculate the SHA1 Sum\n",
+ "address len [addr] calculate the SHA1 sum [save at addr]\n"
+ " -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
+ " -c check the U-Boot image in flash\n"
+ );
+ #endif
+
+ #ifdef CONFIG_IDE_PREINIT
+ int ide_preinit (void)
+ {
+ /* Set True IDE Mode */
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+ out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
+ udelay (100000);
+ return 0;
+ }
+ #endif
+
+ #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+ void ide_set_reset (int idereset)
+ {
+ debug ("ide_reset(%d)\n", idereset);
+ if (idereset == 0) {
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+ } else {
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
+ }
+ udelay (10000);
+ }
+ #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
#define ONE_BILLION 1000000000
+ /*
+ * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
+ */
+ void __spd_ddr_init_hang (void)
+ {
+ hang ();
+ }
+ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+
/*-----------------------------------------------------------------------------
| Memory Controller Options 0
+-----------------------------------------------------------------------------*/
#ifdef CFG_SIMULATE_SPD_EEPROM
extern unsigned char cfg_simulate_spd_eeprom[128];
#endif
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static unsigned char spd_read(uchar chip, uint addr);
static void get_spd_info(unsigned long *dimm_populated,
#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
/* and program tlb entries for this size (dynamic) */
- program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
+ program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
#endif
/*
if (dimm_found == FALSE) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
}
dimm_num);
printf("Only DDR SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
}
}
if (voltage_type != 0x04) {
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
dimm_num);
- hang();
+ spd_ddr_init_hang ();
} else {
debug("DIMM %lu voltage level supported.\n", dimm_num);
}
printf("WARNING: DIMM with datawidth of %lu bits.\n",
data_width);
printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
- hang();
+ spd_ddr_init_hang ();
}
break;
}
if ((tcyc_reg & 0x0F) >= 10) {
printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
dimm_num);
- hang();
+ spd_ddr_init_hang ();
}
cycle_time_ns_x_10[cas_index] =
printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range.\n");
- hang();
+ spd_ddr_init_hang ();
}
/*
*/
for (i = 0; i < NUMMEMTESTS; i++) {
for (j = 0; j < NUMMEMWORDS; j++) {
+ //printf("bank enabled base:%x\n", &membase[j]);
membase[j] = test[i][j];
ppcDcbf((unsigned long)&(membase[j]));
}
*/
if (window_found == FALSE) {
printf("ERROR: Cannot determine a common read delay.\n");
- hang();
+ spd_ddr_init_hang ();
}
/*
printf("ERROR: Unsupported value for the banksize: %d.\n",
bank_size_id);
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
switch (num_col_addr) {
printf("ERROR: Unsupported value for number of "
"column addresses: %d.\n", num_col_addr);
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
/*
*/
cr |= SDRAM_BXCR_SDBE;
- for (i = 0; i < num_banks; i++) {
+ for (i = 0; i < num_banks; i++) {
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
dimm_num, i, ctrl_bank_num[dimm_num]+i,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
- }
+ }
}
}
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
-#define MAXDIMMS 2
-#define MAXRANKS 4
+#define MAXDIMMS 2
+#define MAXRANKS 4
#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
+ /*
+ * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
+ */
+ void __spd_ddr_init_hang (void)
+ {
+ hang ();
+ }
+ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+
+
/* Private Structure Definitions */
/* enum only to ease code for cas latency setting */
* Prototypes
*-----------------------------------------------------------------------------*/
static unsigned long sdram_memsize(void);
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static void get_spd_info(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
dram_size = sdram_memsize();
/* and program tlb entries for this size (dynamic) */
- program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
+ program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
/*------------------------------------------------------------------
* DQS calibration.
if (dimm_found == FALSE) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
}
"slot %d.\n", (unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
case 2:
printf("ERROR: EDO DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
case 3:
printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
case 4:
printf("ERROR: SDRAM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
case 5:
printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
case 6:
printf("ERROR: SGRAM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
case 7:
debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
(unsigned int)dimm_num);
printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
}
}
&& (dimm_populated[dimm_num] != SDRAM_NONE)
&& (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
- hang();
+ spd_ddr_init_hang ();
}
}
}
(unsigned int)(calc_cycle_time*10));
printf("Replace the DIMM, or change DDR frequency via "
"strapping bits.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
}
}
"slot %d is not supported.\n", dimm_rank, dimm_num);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
} else
total_rank += dimm_rank;
}
"for all slots.\n", (unsigned int)total_rank);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Remove one of the DIMM modules.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
}
}
printf("This DIMM is 5.0 Volt/TTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
- hang();
+ spd_ddr_init_hang ();
break;
case 0x01:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is LVTTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
- hang();
+ spd_ddr_init_hang ();
break;
case 0x02:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is 1.5 Volt.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
- hang();
+ spd_ddr_init_hang ();
break;
case 0x03:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is 3.3 Volt/TTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
- hang();
+ spd_ddr_init_hang ();
break;
case 0x04:
/* 2.5 Voltage only for DDR1 */
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
- hang();
+ spd_ddr_init_hang ();
break;
}
}
if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
if (buf0 != buf1) {
printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
- hang();
+ spd_ddr_init_hang ();
}
}
if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
- hang();
+ spd_ddr_init_hang ();
}
else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
} else {
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
if (ecc_enabled == TRUE)
break;
default:
printf("ERROR: ucode error on selected_cas value %d", selected_cas);
- hang();
+ spd_ddr_init_hang ();
break;
}
break;
default:
printf("ERROR: write recovery not support (%d)", write_recovery);
- hang();
+ spd_ddr_init_hang ();
break;
}
#else
ods = ODS_REDUCED;
} else {
printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
- hang();
+ spd_ddr_init_hang ();
}
mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
} else {
printf("ERROR: ucode error as unknown DDR type in program_initplr");
- hang();
+ spd_ddr_init_hang ();
}
}
} else {
printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
"in slot %d\n", (unsigned int)dimm_num);
- hang();
+ spd_ddr_init_hang ();
}
} else {
/* Convert from hex to decimal */
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
} else { /* DDR2 */
debug("cas_3_0_available=%d\n", cas_3_0_available);
cas_3_0_available, cas_4_0_available, cas_5_0_available);
printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
- hang();
+ spd_ddr_init_hang ();
}
}
printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
(unsigned int)dimm_num);
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
break;
}
printf("ERROR: Unsupported value for number of "
"column addresses: %d.\n", (unsigned int)num_col_addr);
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
}
printf("ERROR: Unsupported value for the banksize: %d.\n",
(unsigned int)rank_size_id);
printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
+ spd_ddr_init_hang ();
}
if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
printf("\nERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
- hang();
+ spd_ddr_init_hang ();
}
blank_string(strlen(str));
if (window_found == FALSE) {
printf("ERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
- hang();
+ spd_ddr_init_hang ();
}
/*------------------------------------------------------------------
*----------------------------------------------------------------------*/
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
- #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+ #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+ #define CONFIG_ENV_OVERWRITE 1
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
+ #define ENV_NAME_REVLEV "revision_level"
+ #define ENV_NAME_SOLDER "solder_switch"
+ #define ENV_NAME_DIP "dip"
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define SPD_EEPROM_ADDRESS {0x50}
+ #define CONFIG_PROG_SDRAM_TLB 1
/*-----------------------------------------------------------------------
* I2C
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pcs440ep\0" \
+ "use_eeprom_ethaddr=default\0" \
+ "cs_test=off\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
+ #define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+ /* check U-Boot image with SHA1 sum */
+ #define CONFIG_SHA1_CHECK_UB_IMG 1
+ #define CONFIG_SHA1_START CFG_MONITOR_BASE
+ #define CONFIG_SHA1_LEN CFG_MONITOR_LEN
+
+ /*-----------------------------------------------------------------------
+ * Definitions for status LED
+ */
+ #define CONFIG_STATUS_LED 1 /* Status LED enabled */
+ #define CONFIG_BOARD_SPECIFIC_LED 1
+
+ #define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */
+ #define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+ #define STATUS_LED_STATE STATUS_LED_OFF
+ #define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */
+ #define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+ #define STATUS_LED_STATE1 STATUS_LED_ON
+ #define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */
+ #define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+ #define STATUS_LED_STATE2 STATUS_LED_OFF
+ #define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */
+ #define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+ #define STATUS_LED_STATE3 STATUS_LED_OFF
+
+ #define CONFIG_SHOW_BOOT_PROGRESS 1
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
+ CFG_CMD_EXT2 | \
+ CFG_CMD_FAT | \
CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
+ CFG_CMD_REISER | \
CFG_CMD_SDRAM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
CFG_CMD_USB )
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
+{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+ /*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+ #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+ #undef CONFIG_IDE_LED /* LED for ide not supported */
+
+ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+ #define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
+
+ #define CONFIG_IDE_PREINIT 1
+ #define CONFIG_IDE_RESET 1
+
+ #define CFG_ATA_IDE0_OFFSET 0x0000
+
+ #define CFG_ATA_BASE_ADDR CFG_CF1
+
+ /* Offset for data I/O */
+ #define CFG_ATA_DATA_OFFSET 0
+
+ /* Offset for normal register accesses */
+ #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+ /* Offset for alternate registers */
+ #define CFG_ATA_ALT_OFFSET (0x0000)
+
+ /* This addresses need to be shifted one place to the left
+ * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
+ * This values are shifted
+ */
+ #define CFG_ATA_PORT_ADDR(port) ((port) << 1)
+
#endif /* __CONFIG_H */
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+ #if defined(CONFIG_SHOW_BOOT_PROGRESS)
+ # include <status_led.h>
+ extern void show_ethcfg_progress (int arg);
+ # define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg)
+ #else
+ # define SHOW_BOOT_PROGRESS(arg)
+ #endif
+
#ifdef CFG_GT_6426x
extern int gt6426x_eth_initialize(bd_t *bis);
#endif
eth_devices = NULL;
eth_current = NULL;
+ SHOW_BOOT_PROGRESS(64);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_init();
#endif
#if defined(CONFIG_SK98)
skge_initialize(bis);
#endif
-#if defined(CONFIG_MPC85XX_TSEC1)
- tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME);
-#elif defined(CONFIG_MPC83XX_TSEC1)
- tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME);
+#if defined(CONFIG_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
#endif
-#if defined(CONFIG_MPC85XX_TSEC2)
- tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME);
-#elif defined(CONFIG_MPC83XX_TSEC2)
- tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME);
+#if defined(CONFIG_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
#endif
#if defined(CONFIG_MPC85XX_FEC)
tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
#else
-# if defined(CONFIG_MPC85XX_TSEC3)
- tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME);
-# elif defined(CONFIG_MPC83XX_TSEC3)
- tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME);
+# if defined(CONFIG_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
# endif
-# if defined(CONFIG_MPC85XX_TSEC4)
- tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME);
-# elif defined(CONFIG_MPC83XX_TSEC4)
- tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
+# if defined(CONFIG_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
# endif
#endif
#if defined(CONFIG_UEC_ETH1)
#if defined(CONFIG_UEC_ETH2)
uec_initialize(1);
#endif
-#if defined(CONFIG_MPC86XX_TSEC1)
- tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME);
-#endif
-
-#if defined(CONFIG_MPC86XX_TSEC2)
- tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME);
-#endif
-
-#if defined(CONFIG_MPC86XX_TSEC3)
- tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME);
-#endif
-
-#if defined(CONFIG_MPC86XX_TSEC4)
- tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME);
-#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
if (!eth_devices) {
puts ("No ethernet found.\n");
+ SHOW_BOOT_PROGRESS(-64);
} else {
struct eth_device *dev = eth_devices;
char *ethprime = getenv ("ethprime");
+ SHOW_BOOT_PROGRESS(65);
do {
if (eth_number)
puts (", ");
# MA 02111-1307 USA
#
- BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
+ BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) ubsha1$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
- OBJ_LINKS = environment.o crc32.o
- OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o
+ OBJ_LINKS = environment.o crc32.o sha1.o
+ OBJ_FILES = img2srec.o mkimage.o envcrc.o ubsha1.o gen_eth_addr.o bmp_logo.o
ifeq ($(ARCH),mips)
BIN_FILES += inca-swap-bytes$(SFX)
ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
HOST_CFLAGS = -traditional-cpp -Wall
HOST_LDFLAGS =-multiply_defined suppress
-HOST_ENVIRO_CFLAGS = -traditional-cpp
+HOST_ENVIRO_CFLAGS =
else
ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc)
all: $(obj).depend $(BINS) $(LOGO_H) subdirs
- $(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o
+ $(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o $(obj)sha1.o
+ $(CC) $(CFLAGS) -o $@ $^
+
+ $(obj)ubsha1$(SFX): $(obj)ubsha1.o $(obj)sha1.o
$(CC) $(CFLAGS) -o $@ $^
$(obj)img2srec$(SFX): $(obj)img2srec.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
- $(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o
+ $(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o $(obj)sha1.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
$(obj)envcrc.o: $(src)envcrc.c
$(CC) -g $(CFLAGS) -c -o $@ $<
+ $(obj)ubsha1.o: $(src)ubsha1.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
+
$(obj)crc32.o: $(obj)crc32.c
$(CC) -g $(CFLAGS) -c -o $@ $<
+ $(obj)sha1.o: $(obj)sha1.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
+
$(obj)mkimage.o: $(src)mkimage.c
$(CC) -g $(CFLAGS) -c -o $@ $<
@rm -f $(obj)crc32.c
ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
+ $(obj)sha1.c:
+ @rm -f $(obj)sha1.c
+ ln -s $(src)../lib_generic/sha1.c $(obj)sha1.c
+
$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
$(obj)./bmp_logo $(LOGO_BMP) >$@
projects / people / ms / u-boot.git / commitdiff
