select CMD_FS_GENERIC
select CMD_MII
select CMD_PING
+ select CMD_PART
select HUSH_PARSER
help
Select this to enable various options and commands which are suitable
source "cmd/Kconfig"
+source "disk/Kconfig"
+
source "dts/Kconfig"
source "net/Kconfig"
F: arch/arm/mach-omap2/omap5/sec-fxns.c
F: arch/arm/mach-omap2/sec-common.c
F: arch/arm/mach-omap2/config_secure.mk
+F: configs/am335x_hs_evm_defconfig
F: configs/am43xx_hs_evm_defconfig
F: configs/am57xx_hs_evm_defconfig
F: configs/dra7xx_hs_evm_defconfig
#
VERSION = 2017
-PATCHLEVEL = 01
+PATCHLEVEL = 03
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
- -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
+ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ $(if $(KEYDIR),-k $(KEYDIR))
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
CONFIG_SH_MMCIF_CLK
Define the clock frequency for MMCIF
- CONFIG_GENERIC_MMC
- Enable the generic MMC driver
-
CONFIG_SUPPORT_EMMC_BOOT
Enable some additional features of the eMMC boot partitions.
select OF_CONTROL
select SYS_CACHE_SHIFT_7
+config ARCH_ASPEED
+ bool "Support Aspeed SoCs"
+ select OF_CONTROL
+ select DM
+
endchoice
+source "arch/arm/mach-aspeed/Kconfig"
+
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcm283x/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
-source "arch/arm/mach-litesom/Kconfig"
-
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/freescale/vf610twr/Kconfig"
+source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
-machine-$(CONFIG_LITESOM) += litesom
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
select ROM_UNIFIED_SECTIONS
bool
+config MX6UL_LITESOM
+ bool
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config MX6ULL
bool
select MX6UL
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_MCCMON6
+ bool "mccmon6"
+ select SUPPORT_SPL
+
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select BOARD_LATE_INIT
config TARGET_LITEBOARD
bool "Grinn liteBoard (i.MX6UL)"
select BOARD_LATE_INIT
- select LITESOM
+ select MX6UL_LITESOM
config TARGET_PLATINUM_PICON
bool "platinum-picon"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/mccmon6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
To use this feature, you must do:
- Specify enable-method = "spin-table" in each CPU node in the
Device Tree you are using to boot the kernel
- - Let secondary CPUs in U-Boot (in a board specific manner)
- before the master CPU jumps to the kernel
+ - Bring secondary CPUs into U-Boot proper in a board specific
+ manner. This must be done *after* relocation. Otherwise, the
+ secondary CPUs will spin in unprotected memory area because the
+ master CPU protects the relocated spin code.
U-Boot automatically does:
- Set "cpu-release-addr" property of each CPU node
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb
+
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
imx6dl-icore-rqs.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
+ imx6sx-sabreauto.dtb \
imx6ul-geam-kit.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
bcm2836-rpi-2-b.dtb \
bcm2837-rpi-3-b.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
--- /dev/null
+#include "skeleton.dtsi"
+
+/ {
+ nvic: interrupt-controller@e000e100 {
+ compatible = "arm,armv7m-nvic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe000e100 0xc00>;
+ };
+
+ systick: timer@e000e010 {
+ compatible = "arm,armv7m-systick";
+ reg = <0xe000e010 0x10>;
+ status = "disabled";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&nvic>;
+ ranges;
+ };
+};
+
--- /dev/null
+/dts-v1/;
+
+#include "ast2500-u-boot.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ };
+};
+
+&uart5 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdrammc {
+ clock-frequency = <400000000>;
+};
--- /dev/null
+#include <dt-bindings/clock/ast2500-scu.h>
+
+#include "ast2500.dtsi"
+
+/ {
+ scu: clock-controller@1e6e2000 {
+ compatible = "aspeed,ast2500-scu";
+ reg = <0x1e6e2000 0x1000>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sdrammc: sdrammc@1e6e0000 {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2500-sdrammc";
+ reg = <0x1e6e0000 0x174
+ 0x1e6e0200 0x1d4 >;
+ clocks = <&scu PLL_MPLL>;
+ };
+
+ ahb {
+ u-boot,dm-pre-reloc;
+
+ apb {
+ u-boot,dm-pre-reloc;
+
+ timer: timer@1e782000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ uart1: serial@1e783000 {
+ clocks = <&scu PCLK_UART1>;
+ };
+
+ uart2: serial@1e78d000 {
+ clocks = <&scu PCLK_UART2>;
+ };
+
+ uart3: serial@1e78e000 {
+ clocks = <&scu PCLK_UART3>;
+ };
+
+ uart4: serial@1e78f000 {
+ clocks = <&scu PCLK_UART4>;
+ };
+
+ uart5: serial@1e784000 {
+ clocks = <&scu PCLK_UART5>;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * This device tree is copied from
+ * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
+ */
+#include "skeleton.dtsi"
+
+/ {
+ model = "Aspeed BMC";
+ compatible = "aspeed,ast2500";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&vic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm1176jzf-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vic: interrupt-controller@1e6c0080 {
+ compatible = "aspeed,ast2400-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ valid-sources = <0xfefff7ff 0x0807ffff>;
+ reg = <0x1e6c0080 0x80>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clk_clkin: clk_clkin@1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-clkin-clock";
+ reg = <0x1e6e2070 0x04>;
+ };
+
+ clk_hpll: clk_hpll@1e6e2024 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-hpll-clock";
+ reg = <0x1e6e2024 0x4>;
+ clocks = <&clk_clkin>;
+ };
+
+ clk_ahb: clk_ahb@1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-ahb-clock";
+ reg = <0x1e6e2070 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+ clk_apb: clk_apb@1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-apb-clock";
+ reg = <0x1e6e2008 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+ clk_uart: clk_uart@1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,uart-clock";
+ reg = <0x1e6e202c 0x4>;
+ };
+
+ sram@1e720000 {
+ compatible = "mmio-sram";
+ reg = <0x1e720000 0x9000>; // 36K
+ };
+
+ timer: timer@1e782000 {
+ compatible = "aspeed,ast2400-timer";
+ reg = <0x1e782000 0x90>;
+ // The moxart_timer driver registers only one
+ // interrupt and assumes it's for timer 1
+ //interrupts = <16 17 18 35 36 37 38 39>;
+ interrupts = <16>;
+ clocks = <&clk_apb>;
+ };
+
+ wdt1: wdt@1e785000 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785000 0x1c>;
+ interrupts = <27>;
+ };
+
+ wdt2: wdt@1e785020 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785020 0x1c>;
+ interrupts = <27>;
+ status = "disabled";
+ };
+
+ wdt3: wdt@1e785040 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785074 0x1c>;
+ status = "disabled";
+ };
+
+ uart1: serial@1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart2: serial@1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <32>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart3: serial@1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <33>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart4: serial@1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <34>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart5: serial@1e784000 {
+ compatible = "ns16550a";
+ reg = <0x1e784000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clocks = <&clk_uart>;
+ current-speed = <38400>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart6: serial@1e787000 {
+ compatible = "ns16550a";
+ reg = <0x1e787000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+ };
+ };
+};
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SX_PINFUNC_H
+#define __DTS_IMX6SX_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
+#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
+#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0
+#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1
+#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
+#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0
+#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0
+#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0
+#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1
+#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
+#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0
+#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0
+#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0
+#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1
+#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
+#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0
+#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0
+#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0
+#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1
+#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
+#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0
+#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0
+#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0
+#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
+#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
+#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
+#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
+#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0
+#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
+#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
+#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
+#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
+#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0
+#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
+#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
+#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
+#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
+#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0
+#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
+#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
+#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
+#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
+#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
+#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
+#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
+#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
+#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
+#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
+#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
+#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0
+#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
+#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
+#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
+#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
+#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
+#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
+#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
+#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
+#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0
+#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
+#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1
+#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1
+#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
+#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
+#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1
+#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
+#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
+#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1
+#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
+#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
+/*
+ * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is
+ * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a
+ * PHY in RMII mode. This configuration is valid if:
+ * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set
+ * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset
+ * It seems to be a silicon bug that in this configuration ENET1_TX reference
+ * clock isn't provided automatically. According to i.MX6SX reference manual
+ * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it
+ * should be the case.
+ * So this might have unwanted side effects for other hardware units that are
+ * also connected to that pin and using respective function as input (e.g.
+ * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
+ */
+#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
+#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
+#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
+#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
+#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
+#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
+#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
+#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
+#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
+#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
+#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
+#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
+#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
+#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
+#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
+#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
+#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
+#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
+#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
+#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
+#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1
+#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0
+#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
+#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
+#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
+#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
+#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
+#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
+#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
+#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
+#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
+#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
+#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
+#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0
+#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
+#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
+#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
+#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1
+#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
+#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
+#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
+#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
+#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0
+#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
+#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
+#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
+#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
+#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
+#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
+#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
+#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3
+#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
+#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0
+#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0
+#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
+#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0
+#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0
+#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
+#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0
+#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0
+#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0
+#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
+#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0
+#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0
+#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
+#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0
+#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0
+#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1
+#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
+#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0
+#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0
+#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0
+#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0
+#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0
+#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0
+#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0
+#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0
+#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0
+#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0
+#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0
+#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0
+#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0
+#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0
+#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0
+#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0
+#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0
+#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0
+#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0
+#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0
+#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
+#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
+#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
+#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
+#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
+#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
+#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
+#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0
+#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0
+#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0
+#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0
+#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0
+#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0
+#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0
+#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0
+#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
+#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
+#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
+#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
+#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
+#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1
+#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
+#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
+#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
+#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1
+#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
+#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
+#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1
+#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
+#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
+#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1
+#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1
+#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
+#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
+#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
+#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
+#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
+#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1
+#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
+#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
+#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
+#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
+#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
+#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
+#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
+#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
+#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1
+#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1
+#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1
+#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
+#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1
+#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
+#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1
+#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1
+#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
+#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
+#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
+#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
+#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
+#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
+#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
+#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
+#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
+#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
+#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
+#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1
+#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
+#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
+#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
+#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1
+#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
+#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
+#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
+#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0
+#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
+#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
+#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
+#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
+#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0
+#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
+#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
+#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
+#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
+#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1
+#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
+#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
+#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
+#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
+#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1
+#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
+#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
+#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
+#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
+#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
+#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0
+#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
+#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
+#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
+#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
+#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0
+#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0
+#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0
+#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0
+#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
+#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
+#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
+#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
+#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
+#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
+#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
+#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
+#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
+#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
+#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
+#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
+#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
+#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
+#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0
+#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
+#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0
+#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
+#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0
+#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
+#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0
+#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
+#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0
+#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
+#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0
+#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
+#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
+#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
+#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
+#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0
+#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
+#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
+#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0
+#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
+#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0
+#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0
+#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0
+#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0
+#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0
+#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
+#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1
+#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0
+#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0
+#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0
+#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0
+#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
+#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1
+#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
+#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6SX_PINFUNC_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+ model = "Freescale i.MX6 SoloX Sabre Auto Board";
+ compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vcc_sd3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_sd3>;
+ regulator-name = "VCC_SD3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <&vcc_sd3>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_2>;
+ status = "okay";
+
+ max7310_a: gpio@30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio@32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&iomuxc {
+ imx6x-sabreauto {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_2: i2c3grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
+ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
+ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
+ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
+ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
+ >;
+ };
+
+ pinctrl_vcc_sd3: vccsd3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
+ >;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx6sx-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx6sx-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ mmc3 = &usdhc4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ spi4 = &ecspi5;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 996000 1250000
+ 792000 1175000
+ 396000 1075000
+ 198000 975000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC uV */
+ 996000 1175000
+ 792000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks IMX6SX_CLK_ARM>,
+ <&clks IMX6SX_CLK_PLL2_PFD2>,
+ <&clks IMX6SX_CLK_STEP>,
+ <&clks IMX6SX_CLK_PLL1_SW>,
+ <&clks IMX6SX_CLK_PLL1_SYS>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ ipp_di0: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
+
+ ipp_di1: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ocram: sram@00900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
+ clocks = <&clks IMX6SX_CLK_OCRAM>;
+ };
+
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
+ };
+
+ gpu: gpu@01800000 {
+ compatible = "vivante,gc";
+ reg = <0x01800000 0x4000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_GPU>,
+ <&clks IMX6SX_CLK_GPU>,
+ <&clks IMX6SX_CLK_GPU>;
+ clock-names = "bus", "core", "shader";
+ };
+
+ dma_apbh: dma-apbh@01804000 {
+ compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x01804000 0x2000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX6SX_CLK_APBH_DMA>;
+ };
+
+ gpmi: gpmi-nand@01806000{
+ compatible = "fsl,imx6sx-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX6SX_CLK_GPMI_IO>,
+ <&clks IMX6SX_CLK_GPMI_APB>,
+ <&clks IMX6SX_CLK_GPMI_BCH>,
+ <&clks IMX6SX_CLK_GPMI_BCH_APB>,
+ <&clks IMX6SX_CLK_PER1_BCH>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ aips1: aips-bus@02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ spdif: spdif@02004000 {
+ compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
+ <&clks IMX6SX_CLK_OSC>,
+ <&clks IMX6SX_CLK_SPDIF>,
+ <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_IPG>,
+ <&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ status = "disabled";
+ };
+
+ ecspi1: ecspi@02008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ECSPI1>,
+ <&clks IMX6SX_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi@0200c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ECSPI2>,
+ <&clks IMX6SX_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi@02010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ECSPI3>,
+ <&clks IMX6SX_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi@02014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ECSPI4>,
+ <&clks IMX6SX_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>,
+ <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ esai: esai@02024000 {
+ reg = <0x02024000 0x4000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
+ <&clks IMX6SX_CLK_ESAI_MEM>,
+ <&clks IMX6SX_CLK_ESAI_EXTAL>,
+ <&clks IMX6SX_CLK_ESAI_IPG>,
+ <&clks IMX6SX_CLK_SPBA>;
+ clock-names = "core", "mem", "extal",
+ "fsys", "spba";
+ status = "disabled";
+ };
+
+ ssi1: ssi@02028000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
+ reg = <0x02028000 0x4000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
+ <&clks IMX6SX_CLK_SSI1>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@0202c000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
+ <&clks IMX6SX_CLK_SSI2>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@02030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
+ reg = <0x02030000 0x4000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
+ <&clks IMX6SX_CLK_SSI3>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ asrc: asrc@02034000 {
+ reg = <0x02034000 0x4000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
+ <&clks IMX6SX_CLK_ASRC_IPG>,
+ <&clks IMX6SX_CLK_SPDIF>,
+ <&clks IMX6SX_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck", "spba";
+ dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
+ <&sdma 19 20 1>, <&sdma 20 20 1>,
+ <&sdma 21 20 1>, <&sdma 22 20 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ status = "okay";
+ };
+ };
+
+ pwm1: pwm@02080000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM1>,
+ <&clks IMX6SX_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm2: pwm@02084000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM2>,
+ <&clks IMX6SX_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@02088000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM3>,
+ <&clks IMX6SX_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm4: pwm@0208c000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM4>,
+ <&clks IMX6SX_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ flexcan1: can@02090000 {
+ compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
+ <&clks IMX6SX_CLK_CAN1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ flexcan2: can@02094000 {
+ compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
+ <&clks IMX6SX_CLK_CAN2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt: gpt@02098000 {
+ compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_GPT_BUS>,
+ <&clks IMX6SX_CLK_GPT_3M>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 5 26>;
+ };
+
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 31 20>;
+ };
+
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 51 29>;
+ };
+
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 80 32>;
+ };
+
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 112 24>;
+ };
+
+ gpio6: gpio@020b0000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x020b0000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
+ };
+
+ gpio7: gpio@020b4000 {
+ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
+ reg = <0x020b4000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
+ };
+
+ kpp: kpp@020b8000 {
+ compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_DUMMY>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6sx-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ regulator-1p1 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd1p1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1375000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x110>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <4>;
+ anatop-min-voltage = <800000>;
+ anatop-max-voltage = <1375000>;
+ };
+
+ regulator-3p0 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ };
+
+ regulator-2p5 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd2p5";
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2875000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x130>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2100000>;
+ anatop-max-voltage = <2875000>;
+ };
+
+ reg_arm: regulator-vddcore {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddarm";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <0>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_pcie: regulator-vddpcie {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddpcie";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <26>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_soc: regulator-vddsoc {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddsoc";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <18>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <28>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ fsl,tempmon-data = <&ocotp>;
+ clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ };
+
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBPHY1>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBPHY2>;
+ fsl,anatop = <&anatop>;
+ };
+
+ snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x60>;
+ status = "disabled";
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ epit1: epit@020d0000 {
+ reg = <0x020d0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 {
+ reg = <0x020d4000 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6sx-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6sx-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@020e4000 {
+ compatible = "fsl,imx6sx-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_SDMA>,
+ <&clks IMX6SX_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ /* imx6sx reuses imx6q sdma firmware */
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+ };
+
+ aips2: aips-bus@02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
+ <&clks IMX6SX_CLK_CAAM_ACLK>,
+ <&clks IMX6SX_CLK_CAAM_IPG>,
+ <&clks IMX6SX_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ usbotg1: usb@02184000 {
+ compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,anatop = <&anatop>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@02184200 {
+ compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbh: usb@02184400 {
+ compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
+ reg = <0x02184400 0x200>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBOH3>;
+ fsl,usbmisc = <&usbmisc 2>;
+ phy_type = "hsic";
+ fsl,anatop = <&anatop>;
+ dr_mode = "host";
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ clocks = <&clks IMX6SX_CLK_USBOH3>;
+ };
+
+ fec1: ethernet@02188000 {
+ compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ENET>,
+ <&clks IMX6SX_CLK_ENET_AHB>,
+ <&clks IMX6SX_CLK_ENET_PTP>,
+ <&clks IMX6SX_CLK_ENET_REF>,
+ <&clks IMX6SX_CLK_ENET_PTP>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ status = "disabled";
+ };
+
+ mlb: mlb@0218c000 {
+ reg = <0x0218c000 0x4000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_MLB>;
+ status = "disabled";
+ };
+
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USDHC1>,
+ <&clks IMX6SX_CLK_USDHC1>,
+ <&clks IMX6SX_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USDHC2>,
+ <&clks IMX6SX_CLK_USDHC2>,
+ <&clks IMX6SX_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USDHC3>,
+ <&clks IMX6SX_CLK_USDHC3>,
+ <&clks IMX6SX_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc4: usdhc@0219c000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x0219c000 0x4000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USDHC4>,
+ <&clks IMX6SX_CLK_USDHC4>,
+ <&clks IMX6SX_CLK_USDHC4>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ mmdc: mmdc@021b0000 {
+ compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ fec2: ethernet@021b4000 {
+ compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
+ reg = <0x021b4000 0x4000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ENET>,
+ <&clks IMX6SX_CLK_ENET_AHB>,
+ <&clks IMX6SX_CLK_ENET_PTP>,
+ <&clks IMX6SX_CLK_ENET2_REF_125M>,
+ <&clks IMX6SX_CLK_ENET_PTP>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ status = "disabled";
+ };
+
+ weim: weim@021b8000 {
+ compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
+ };
+
+ ocotp: ocotp@021bc000 {
+ compatible = "fsl,imx6sx-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6SX_CLK_OCOTP>;
+ };
+
+ sai1: sai@021d4000 {
+ compatible = "fsl,imx6sx-sai";
+ reg = <0x021d4000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
+ <&clks IMX6SX_CLK_SAI1>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
+ status = "disabled";
+ };
+
+ audmux: audmux@021d8000 {
+ compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
+ reg = <0x021d8000 0x4000>;
+ status = "disabled";
+ };
+
+ sai2: sai@021dc000 {
+ compatible = "fsl,imx6sx-sai";
+ reg = <0x021dc000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
+ <&clks IMX6SX_CLK_SAI2>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
+ status = "disabled";
+ };
+
+ qspi1: qspi@021e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-qspi";
+ reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_QSPI1>,
+ <&clks IMX6SX_CLK_QSPI1>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
+ qspi2: qspi@021e4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-qspi";
+ reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_QSPI2>,
+ <&clks IMX6SX_CLK_QSPI2>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>,
+ <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@021ec000 {
+ compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ reg = <0x021ec000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>,
+ <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@021f0000 {
+ compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ reg = <0x021f0000 0x4000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>,
+ <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@021f4000 {
+ compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>,
+ <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_I2C4>;
+ status = "disabled";
+ };
+ };
+
+ aips3: aips-bus@02200000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02200000 0x100000>;
+ ranges;
+
+ spba-bus@02200000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02240000 0x40000>;
+ ranges;
+
+ csi1: csi@02214000 {
+ reg = <0x02214000 0x4000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
+ <&clks IMX6SX_CLK_CSI>,
+ <&clks IMX6SX_CLK_DCIC1>;
+ clock-names = "disp-axi", "csi_mclk", "dcic";
+ status = "disabled";
+ };
+
+ pxp: pxp@02218000 {
+ reg = <0x02218000 0x4000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PXP_AXI>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pxp-axi", "disp-axi";
+ status = "disabled";
+ };
+
+ csi2: csi@0221c000 {
+ reg = <0x0221c000 0x4000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
+ <&clks IMX6SX_CLK_CSI>,
+ <&clks IMX6SX_CLK_DCIC2>;
+ clock-names = "disp-axi", "csi_mclk", "dcic";
+ status = "disabled";
+ };
+
+ lcdif1: lcdif@02220000 {
+ compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
+ reg = <0x02220000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
+ <&clks IMX6SX_CLK_LCDIF_APB>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ lcdif2: lcdif@02224000 {
+ compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
+ reg = <0x02224000 0x4000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
+ <&clks IMX6SX_CLK_LCDIF_APB>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ vadc: vadc@02228000 {
+ reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
+ reg-names = "vadc-vafe", "vadc-vdec";
+ clocks = <&clks IMX6SX_CLK_VADC>,
+ <&clks IMX6SX_CLK_CSI>;
+ clock-names = "vadc", "csi";
+ status = "disabled";
+ };
+ };
+
+ adc1: adc@02280000 {
+ compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
+ reg = <0x02280000 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
+ clock-names = "adc";
+ fsl,adck-max-frequency = <30000000>, <40000000>,
+ <20000000>;
+ status = "disabled";
+ };
+
+ adc2: adc@02284000 {
+ compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
+ reg = <0x02284000 0x4000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
+ clock-names = "adc";
+ fsl,adck-max-frequency = <30000000>, <40000000>,
+ <20000000>;
+ status = "disabled";
+ };
+
+ wdog3: wdog@02288000 {
+ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
+ reg = <0x02288000 0x4000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ ecspi5: ecspi@0228c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0228c000 0x4000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_ECSPI5>,
+ <&clks IMX6SX_CLK_ECSPI5>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart6: serial@022a0000 {
+ compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ reg = <0x022a0000 0x4000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>,
+ <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ pwm5: pwm@022a4000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x022a4000 0x4000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM5>,
+ <&clks IMX6SX_CLK_PWM5>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm6: pwm@022a8000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x022a8000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM6>,
+ <&clks IMX6SX_CLK_PWM6>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm7: pwm@022ac000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x022ac000 0x4000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM7>,
+ <&clks IMX6SX_CLK_PWM7>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm8: pwm@0022b0000 {
+ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
+ reg = <0x0022b0000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PWM8>,
+ <&clks IMX6SX_CLK_PWM8>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+ };
+
+ pcie: pcie@0x08000000 {
+ compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
+ reg = <0x08ffc000 0x4000>; /* DBI */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ /* configuration space */
+ ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
+ /* downstream I/O */
+ 0x81000000 0 0 0x08f80000 0 0x00010000
+ /* non-prefetchable memory */
+ 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
+ <&clks IMX6SX_CLK_PCIE_AXI>,
+ <&clks IMX6SX_CLK_LVDS1_OUT>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pcie_ref_125m", "pcie_axi",
+ "lvds_gate", "display_axi";
+ status = "disabled";
+ };
+ };
+
+ gpu-subsystem {
+ compatible = "fsl,imx-gpu-subsystem";
+ cores = <&gpu>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
+ *
+ * Based on:
+ * stm32f469-disco.dts from Linux
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32F746-DISCO board";
+ compatible = "st,stm32f746-disco", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/ram rdinit=/linuxrc";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x800000>;
+ };
+
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&mac {
+ status = "okay";
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ qflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a13", "spi-flash";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ memory-map = <0x90000000 0x1000000>;
+ reg = <0>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
+ *
+ * Based on:
+ * stm32f429.dtsi from Linux
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+
+/ {
+ soc {
+ mac: ethernet@40028000 {
+ compatible = "st,stm32-dwmac";
+ reg = <0x40028000 0x8000>;
+ reg-names = "stmmaceth";
+ interrupts = <61>, <62>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ snps,pbl = <8>;
+ snps,mixed-burst;
+ dma-ranges;
+ status = "disabled";
+ };
+
+ qspi: quadspi@A0001000 {
+ compatible = "st,stm32-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <92>;
+ spi-max-frequency = <108000000>;
+ status = "disabled";
+ };
+ };
+};
+
+&systick {
+ status = "okay";
+};
* Check for BMODE if serial downloader is enabled
* BOOT_MODE - see IMX6DQRM Table 8-1
*/
- if ((((bmode >> 24) & 0x03) == 0x01) || /* Serial Downloader */
- (gpr10_boot && (reg == 1)))
+ if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
return BOOT_DEVICE_UART;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x000000FF) >> 4) {
else
return BOOT_DEVICE_NOR;
break;
+ /* Reserved: Used to force Serial Downloader */
+ case 0x1:
+ return BOOT_DEVICE_UART;
/* SATA: See 8.5.4, Table 8-20 */
case 0x2:
return BOOT_DEVICE_SATA;
--- /dev/null
+/*
+ * Copyright (C) 2017 Grinn
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
+#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void chilisom_enable_pin_mux(void);
+void chilisom_spl_board_init(void);
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SCU_AST2500_H
+#define _ASM_ARCH_SCU_AST2500_H
+
+#define SCU_UNLOCK_VALUE 0x1688a8a8
+
+#define SCU_HWSTRAP_VGAMEM_MASK 3
+#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_DDR4 (1 << 24)
+#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
+
+#define SCU_MPLL_DENUM_SHIFT 0
+#define SCU_MPLL_DENUM_MASK 0x1f
+#define SCU_MPLL_NUM_SHIFT 5
+#define SCU_MPLL_NUM_MASK 0xff
+#define SCU_MPLL_POST_SHIFT 13
+#define SCU_MPLL_POST_MASK 0x3f
+
+#define SCU_HPLL_DENUM_SHIFT 0
+#define SCU_HPLL_DENUM_MASK 0x1f
+#define SCU_HPLL_NUM_SHIFT 5
+#define SCU_HPLL_NUM_MASK 0xff
+#define SCU_HPLL_POST_SHIFT 13
+#define SCU_HPLL_POST_MASK 0x3f
+
+#define SCU_MISC2_UARTCLK_SHIFT 24
+
+#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+
+#ifndef __ASSEMBLY__
+
+struct ast2500_clk_priv {
+ struct ast2500_scu *scu;
+};
+
+struct ast2500_scu {
+ u32 protection_key;
+ u32 sysreset_ctrl1;
+ u32 clk_sel1;
+ u32 clk_stop_ctrl1;
+ u32 freq_counter_ctrl;
+ u32 freq_counter_cmp;
+ u32 intr_ctrl;
+ u32 d2_pll_param;
+ u32 m_pll_param;
+ u32 h_pll_param;
+ u32 d_pll_param;
+ u32 misc_ctrl1;
+ u32 pci_config[3];
+ u32 sysreset_status;
+ u32 vga_handshake[2];
+ u32 mac_clk_delay;
+ u32 misc_ctrl2;
+ u32 vga_scratch[8];
+ u32 hwstrap;
+ u32 rng_ctrl;
+ u32 rng_data;
+ u32 rev_id;
+ u32 pinmux_ctrl[6];
+ u32 reserved0;
+ u32 extrst_sel;
+ u32 pinmux_ctrl1[4];
+ u32 reserved1[2];
+ u32 mac_clk_delay_100M;
+ u32 mac_clk_delay_10M;
+ u32 wakeup_enable;
+ u32 wakeup_control;
+ u32 reserved2[3];
+ u32 sysreset_ctrl2;
+ u32 clk_sel2;
+ u32 clk_stop_ctrl2;
+ u32 freerun_counter;
+ u32 freerun_counter_ext;
+ u32 clk_duty_meas_ctrl;
+ u32 clk_duty_meas_res;
+ u32 reserved3[4];
+ /* The next registers are not key-protected */
+ struct ast2500_cpu2 {
+ u32 ctrl;
+ u32 base_addr[9];
+ u32 cache_ctrl;
+ } cpu2;
+ u32 reserved4;
+ u32 d_pll_ext_param[3];
+ u32 d2_pll_ext_param[3];
+ u32 mh_pll_ext_param;
+ u32 reserved5;
+ u32 chip_id[2];
+ u32 reserved6[2];
+ u32 uart_clk_ctrl;
+ u32 reserved7[7];
+ u32 pcie_config;
+ u32 mmio_decode;
+ u32 reloc_ctrl_decode[2];
+ u32 mailbox_addr;
+ u32 shared_sram_decode[2];
+ u32 bmc_rev_id;
+ u32 reserved8;
+ u32 bmc_device_id;
+ u32 reserved9[13];
+ u32 clk_duty_sel;
+};
+
+/**
+ * ast_get_clk() - get a pointer to Clock Driver
+ *
+ * @devp, OUT - pointer to Clock Driver
+ * @return zero on success, error code (< 0) otherwise.
+ */
+int ast_get_clk(struct udevice **devp);
+
+/**
+ * ast_get_scu() - get a pointer to SCU registers
+ *
+ * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
+ */
+void *ast_get_scu(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_SCU_AST2500_H */
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SDRAM_AST2500_H
+#define _ASM_ARCH_SDRAM_AST2500_H
+
+#define SDRAM_UNLOCK_KEY 0xfc600309
+#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f
+
+#define SDRAM_PCR_CKE_EN (1 << 0)
+#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1)
+#define SDRAM_PCR_CKE_DELAY_SHIFT 4
+#define SDRAM_PCR_CKE_DELAY_MASK 7
+#define SDRAM_PCR_RESETN_DIS (1 << 7)
+#define SDRAM_PCR_ODT_EN (1 << 8)
+#define SDRAM_PCR_ODT_AUTO_ON (1 << 10)
+#define SDRAM_PCR_ODT_EXT_EN (1 << 11)
+#define SDRAM_PCR_TCKE_PW_SHIFT 12
+#define SDRAM_PCR_TCKE_PW_MASK 7
+#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15)
+#define SDRAM_PCR_MREQI_DIS (1 << 17)
+
+/* Fixed priority DRAM Requests mask */
+#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0)
+#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1)
+#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2)
+#define SDRAM_REQ_VGA_CRT (1 << 3)
+#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4)
+#define SDRAM_REQ_SOC_DC_OCD (1 << 5)
+#define SDRAM_REQ_SOC_DC_CRT (1 << 6)
+#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7)
+#define SDRAM_REQ_USB20_EHCI1 (1 << 8)
+#define SDRAM_REQ_USB20_EHCI2 (1 << 9)
+#define SDRAM_REQ_CPU (1 << 10)
+#define SDRAM_REQ_AHB2 (1 << 11)
+#define SDRAM_REQ_AHB (1 << 12)
+#define SDRAM_REQ_MAC0 (1 << 13)
+#define SDRAM_REQ_MAC1 (1 << 14)
+#define SDRAM_REQ_PCIE (1 << 16)
+#define SDRAM_REQ_XDMA (1 << 17)
+#define SDRAM_REQ_ENCRYPTION (1 << 18)
+#define SDRAM_REQ_VIDEO_FLAG (1 << 21)
+#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28)
+#define SDRAM_REQ_2D_RW (1 << 29)
+#define SDRAM_REQ_MEMCHECK (1 << 30)
+
+#define SDRAM_ICR_RESET_ALL (1 << 31)
+
+#define SDRAM_CONF_CAP_SHIFT 0
+#define SDRAM_CONF_CAP_MASK 3
+#define SDRAM_CONF_DDR4 (1 << 4)
+#define SDRAM_CONF_SCRAMBLE (1 << 8)
+#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9)
+#define SDRAM_CONF_CACHE_EN (1 << 10)
+#define SDRAM_CONF_CACHE_INIT_EN (1 << 12)
+#define SDRAM_CONF_DUALX8 (1 << 13)
+#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19)
+
+#define SDRAM_CONF_CAP_128M 0
+#define SDRAM_CONF_CAP_256M 1
+#define SDRAM_CONF_CAP_512M 2
+#define SDRAM_CONF_CAP_1024M 3
+
+#define SDRAM_MISC_DDR4_TREFRESH (1 << 3)
+
+#define SDRAM_PHYCTRL0_INIT (1 << 0)
+#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1)
+#define SDRAM_PHYCTRL0_NRST (1 << 2)
+
+#define SDRAM_REFRESH_CYCLES_SHIFT 0
+#define SDRAM_REFRESH_CYCLES_MASK 0xf
+#define SDRAM_REFRESH_ZQCS_EN (1 << 7)
+#define SDRAM_REFRESH_PERIOD_SHIFT 8
+#define SDRAM_REFRESH_PERIOD_MASK 0xf
+
+#define SDRAM_TEST_LEN_SHIFT 4
+#define SDRAM_TEST_LEN_MASK 0xfffff
+#define SDRAM_TEST_START_ADDR_SHIFT 24
+#define SDRAM_TEST_START_ADDR_MASK 0x3f
+
+#define SDRAM_TEST_EN (1 << 0)
+#define SDRAM_TEST_MODE_SHIFT 1
+#define SDRAM_TEST_MODE_MASK 3
+#define SDRAM_TEST_MODE_WO 0
+#define SDRAM_TEST_MODE_RB 1
+#define SDRAM_TEST_MODE_RW 2
+#define SDRAM_TEST_GEN_MODE_SHIFT 3
+#define SDRAM_TEST_GEN_MODE_MASK 7
+#define SDRAM_TEST_TWO_MODES (1 << 6)
+#define SDRAM_TEST_ERRSTOP (1 << 7)
+#define SDRAM_TEST_DONE (1 << 12)
+#define SDRAM_TEST_FAIL (1 << 13)
+
+#define SDRAM_AC_TRFC_SHIFT 0
+#define SDRAM_AC_TRFC_MASK 0xff
+
+#ifndef __ASSEMBLY__
+
+struct ast2500_sdrammc_regs {
+ u32 protection_key;
+ u32 config;
+ u32 gm_protection_key;
+ u32 refresh_timing;
+ u32 ac_timing[3];
+ u32 misc_control;
+ u32 mr46_mode_setting;
+ u32 mr5_mode_setting;
+ u32 mode_setting_control;
+ u32 mr02_mode_setting;
+ u32 mr13_mode_setting;
+ u32 power_control;
+ u32 req_limit_mask;
+ u32 pri_group_setting;
+ u32 max_grant_len[4];
+ u32 intr_ctrl;
+ u32 ecc_range_ctrl;
+ u32 first_ecc_err_addr;
+ u32 last_ecc_err_addr;
+ u32 phy_ctrl[4];
+ u32 ecc_test_ctrl;
+ u32 test_addr;
+ u32 test_fail_dq_bit;
+ u32 test_init_val;
+ u32 phy_debug_ctrl;
+ u32 phy_debug_data;
+ u32 reserved1[30];
+ u32 scu_passwd;
+ u32 reserved2[7];
+ u32 scu_mpll;
+ u32 reserved3[19];
+ u32 scu_hwstrap;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_SDRAM_AST2500_H */
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+/* Each timer has 4 control bits in ctrl1 register.
+ * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
+ * such that timer X uses bits (4 * X - 4):(4 * X - 1)
+ * If the timer does not support PWM, bit 4 is reserved.
+ */
+#define AST_TMC_EN (1 << 0)
+#define AST_TMC_1MHZ (1 << 1)
+#define AST_TMC_OVFINTR (1 << 2)
+#define AST_TMC_PWM (1 << 3)
+
+/* Timers are counted from 1 in the datasheet. */
+#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
+
+#define AST_TMC_RATE (1000*1000)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All timers share control registers, which makes it harder to make them
+ * separate devices. Since only one timer is needed at the moment, making
+ * it this just one device.
+ */
+
+struct ast_timer_counter {
+ u32 status;
+ u32 reload_val;
+ u32 match1;
+ u32 match2;
+};
+
+struct ast_timer {
+ struct ast_timer_counter timers1[3];
+ u32 ctrl1;
+ u32 ctrl2;
+#ifdef CONFIG_ASPEED_AST2500
+ u32 ctrl3;
+ u32 ctrl1_clr;
+#else
+ u32 reserved[2];
+#endif
+ struct ast_timer_counter timers2[5];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_TIMER_H */
--- /dev/null
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_WDT_H
+#define _ASM_ARCH_WDT_H
+
+#define WDT_BASE 0x1e785000
+
+/*
+ * Special value that needs to be written to counter_restart register to
+ * (re)start the timer
+ */
+#define WDT_COUNTER_RESTART_VAL 0x4755
+
+/* Control register */
+#define WDT_CTRL_RESET_MODE_SHIFT 5
+#define WDT_CTRL_RESET_MODE_MASK 3
+
+#define WDT_CTRL_EN (1 << 0)
+#define WDT_CTRL_RESET (1 << 1)
+#define WDT_CTRL_CLK1MHZ (1 << 4)
+#define WDT_CTRL_2ND_BOOT (1 << 7)
+
+/* Values for Reset Mode */
+#define WDT_CTRL_RESET_SOC 0
+#define WDT_CTRL_RESET_CHIP 1
+#define WDT_CTRL_RESET_CPU 2
+#define WDT_CTRL_RESET_MASK 3
+
+/* Reset Mask register */
+#define WDT_RESET_ARM (1 << 0)
+#define WDT_RESET_COPROC (1 << 1)
+#define WDT_RESET_SDRAM (1 << 2)
+#define WDT_RESET_AHB (1 << 3)
+#define WDT_RESET_I2C (1 << 4)
+#define WDT_RESET_MAC1 (1 << 5)
+#define WDT_RESET_MAC2 (1 << 6)
+#define WDT_RESET_GCRT (1 << 7)
+#define WDT_RESET_USB20 (1 << 8)
+#define WDT_RESET_USB11_HOST (1 << 9)
+#define WDT_RESET_USB11_EHCI2 (1 << 10)
+#define WDT_RESET_VIDEO (1 << 11)
+#define WDT_RESET_HAC (1 << 12)
+#define WDT_RESET_LPC (1 << 13)
+#define WDT_RESET_SDSDIO (1 << 14)
+#define WDT_RESET_MIC (1 << 15)
+#define WDT_RESET_CRT2C (1 << 16)
+#define WDT_RESET_PWM (1 << 17)
+#define WDT_RESET_PECI (1 << 18)
+#define WDT_RESET_JTAG (1 << 19)
+#define WDT_RESET_ADC (1 << 20)
+#define WDT_RESET_GPIO (1 << 21)
+#define WDT_RESET_MCTP (1 << 22)
+#define WDT_RESET_XDMA (1 << 23)
+#define WDT_RESET_SPI (1 << 24)
+#define WDT_RESET_MISC (1 << 25)
+
+#ifndef __ASSEMBLY__
+struct ast_wdt {
+ u32 counter_status;
+ u32 counter_reload_val;
+ u32 counter_restart;
+ u32 ctrl;
+ u32 timeout_status;
+ u32 clr_timeout_status;
+ u32 reset_width;
+#ifdef CONFIG_ASPEED_AST2500
+ u32 reset_mask;
+#else
+ u32 reserved0;
+#endif
+};
+
+void wdt_stop(struct ast_wdt *wdt);
+void wdt_start(struct ast_wdt *wdt, u32 timeout);
+
+/**
+ * Reset peripherals specified by mask
+ *
+ * Note, that this is only supported by ast2500 SoC
+ *
+ * @wdt: watchdog to use for this reset
+ * @mask: reset mask.
+ */
+int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
+
+/**
+ * ast_get_wdt() - get a pointer to watchdog registers
+ *
+ * @wdt_number: 0-based WDT peripheral number
+ * @return pointer to registers or -ve error on error
+ */
+struct ast_wdt *ast_get_wdt(u8 wdt_number);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_WDT_H */
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_DOS_PARTITION
-
#ifdef CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __ARCH_ARM_MACH_LITESOM_SOM_H__
-#define __ARCH_ARM_MACH_LITESOM_SOM_H__
+#ifndef __ARCH_ARM_MX6UL_LITESOM_H__
+#define __ARCH_ARM_MX6UL_LITESOM_H__
int litesom_mmc_init(bd_t *bis);
#define AM3517 0x1c00
#define OMAP3730 0x0c00
+#define OMAP3725 0x4c00
+#define AM3715 0x1c00
+#define AM3703 0x5c00
+
+#define OMAP3730_1GHZ 0x0e00
+#define OMAP3725_1GHZ 0x4e00
+#define AM3715_1GHZ 0x1e00
+#define AM3703_1GHZ 0x5e00
/*
* ROM code API related flags
/*
* FMC registers base
*/
-#define STM32_SDRAM_FMC_BASE 0xA0000140
-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
+#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
/* Control register SDCR */
#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
#define FMC_SDCMR_MODE_SELFREFRESH 5
#define FMC_SDCMR_MODE_POWERDOWN 6
-#define FMC_SDCMR_BANK_1 (1 << 4)
-#define FMC_SDCMR_BANK_2 (1 << 3)
+#define FMC_SDCMR_BANK_1 BIT(4)
+#define FMC_SDCMR_BANK_2 BIT(3)
#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-#define FMC_SDSR_BUSY (1 << 5)
+#define FMC_SDSR_BUSY BIT(5)
#define FMC_BUSY_WAIT() do { \
__asm__ __volatile__ ("dsb" : : : "memory"); \
(struct gpt_regs *)TIM2_BASE;
/* Timer control1 register */
-#define GPT_CR1_CEN 0x0001
-#define GPT_MODE_AUTO_RELOAD (1 << 7)
+#define GPT_CR1_CEN BIT(0)
+#define GPT_MODE_AUTO_RELOAD BIT(7)
/* Auto reload register for free running config */
#define GPT_FREE_RUNNING 0xFFFFFFFF
#define CONFIG_STM32_HZ 1000
/* Timer Event Generation registers */
-#define TIM_EGR_UG (1 << 0)
+#define TIM_EGR_UG BIT(0)
#endif
#ifndef _STM32_RCC_H
#define _STM32_RCC_H
-#define RCC_CR 0x00 /* clock control */
-#define RCC_PLLCFGR 0x04 /* PLL configuration */
-#define RCC_CFGR 0x08 /* clock configuration */
-#define RCC_CIR 0x0C /* clock interrupt */
-#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */
-#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */
-#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */
-#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */
-#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */
-#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */
-#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */
-#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */
-#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */
-#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */
-#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */
-#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */
-#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */
-#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */
-#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */
-#define RCC_BDCR 0x70 /* Backup domain control */
-#define RCC_CSR 0x74 /* clock control & status */
-#define RCC_SSCGR 0x80 /* spread spectrum clock generation */
-#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */
-#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */
-#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */
-#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */
+/*
+ * RCC AHB1ENR specific definitions
+ */
+#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
+#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
+#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
+#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
+#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
+#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
+#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
+#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
+#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
+#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
+#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
+#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
+#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
+#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
+#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
-#define RCC_APB1ENR_TIM2EN (1 << 0)
-#define RCC_APB1ENR_PWREN (1 << 28)
+/*
+ * RCC AHB3ENR specific definitions
+ */
+#define RCC_AHB3ENR_FMC_EN BIT(0)
+#define RCC_AHB3ENR_QSPI_EN BIT(1)
/*
- * RCC USART specific definitions
+ * RCC APB1ENR specific definitions
*/
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
+#define RCC_APB1ENR_TIM2EN BIT(0)
+#define RCC_APB1ENR_USART2EN BIT(17)
+#define RCC_APB1ENR_USART3EN BIT(18)
+#define RCC_APB1ENR_PWREN BIT(28)
/*
- * RCC GPIO specific definitions
+ * RCC APB2ENR specific definitions
*/
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
+#define RCC_APB2ENR_USART1EN BIT(4)
+#define RCC_APB2ENR_USART6EN BIT(5)
+#define RCC_APB2ENR_SYSCFGEN BIT(14)
#endif
#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
+#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
-#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140)
+#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
CLOCK_APB1,
CLOCK_APB2
};
-#define STM32_BUS_MASK 0xFFFF0000
+#define STM32_BUS_MASK GENMASK(31, 16)
struct stm32_rcc_regs {
u32 cr; /* RCC clock control */
u32 rsv6[2];
u32 sscgr; /* RCC spread spectrum clock generation */
u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr;
- u32 dckcfgr;
+ u32 pllsaicfgr; /* PLLSAI configuration */
+ u32 dckcfgr; /* dedicated clocks configuration register */
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
+struct stm32_rcc_ext_f7_regs {
+ u32 dckcfgr2; /* dedicated clocks configuration register */
+};
+#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs)))
+
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
*
*/
enum periph_id {
- UART1_GPIOA_9_10 = 0,
- UART2_GPIOD_5_6,
+ PERIPH_ID_USART1 = 37,
+
+ PERIPH_ID_QUADSPI = 92,
};
enum periph_clock {
GPIO_I_CLOCK_CFG,
GPIO_J_CLOCK_CFG,
GPIO_K_CLOCK_CFG,
+ SYSCFG_CLOCK_CFG,
+ TIMER2_CLOCK_CFG,
+ FMC_CLOCK_CFG,
+ STMMAC_CLOCK_CFG,
+ QSPI_CLOCK_CFG,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */
--- /dev/null
+/*
+ * (C) Copyright 2016
+ * Michael Kurz, michi.kurz@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STM32_SYSCFG_H
+#define _STM32_SYSCFG_H
+
+struct stm32_syscfg_regs {
+ u32 memrmp;
+ u32 pmc;
+ u32 exticr1;
+ u32 exticr2;
+ u32 exticr3;
+ u32 exticr4;
+ u32 cmpcr;
+};
+
+/*
+ * SYSCFG registers base
+ */
+#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
+
+/* SYSCFG memory remap register */
+#define SYSCFG_MEMRMP_MEM_BOOT BIT(0)
+#define SYSCFG_MEMRMP_SWP_FMC BIT(10)
+
+/* SYSCFG peripheral mode configuration register */
+#define SYSCFG_PMC_ADCXDC2 BIT(16)
+#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
+
+/* Compensation cell control register */
+#define SYSCFG_CMPCR_CMP_PD BIT(0)
+#define SYSCFG_CMPCR_READY BIT(8)
+
+#endif
/* see arch/arm/kernel/arch.c for a description of these */
#define MACH_TYPE_EBSA110 0
#define MACH_TYPE_RISCPC 1
+#define MACH_TYPE_NEXUSPCI 3
#define MACH_TYPE_EBSA285 4
#define MACH_TYPE_NETWINDER 5
#define MACH_TYPE_CATS 6
+#define MACH_TYPE_TBOX 7
+#define MACH_TYPE_CO285 8
+#define MACH_TYPE_CLPS7110 9
+#define MACH_TYPE_ARCHIMEDES 10
+#define MACH_TYPE_A5K 11
+#define MACH_TYPE_ETOILE 12
+#define MACH_TYPE_LACIE_NAS 13
+#define MACH_TYPE_CLPS7500 14
#define MACH_TYPE_SHARK 15
#define MACH_TYPE_BRUTUS 16
#define MACH_TYPE_PERSONAL_SERVER 17
+#define MACH_TYPE_ITSY 18
#define MACH_TYPE_L7200 19
#define MACH_TYPE_PLEB 20
#define MACH_TYPE_INTEGRATOR 21
#define MACH_TYPE_H3600 22
+#define MACH_TYPE_IXP1200 23
#define MACH_TYPE_P720T 24
#define MACH_TYPE_ASSABET 25
+#define MACH_TYPE_VICTOR 26
#define MACH_TYPE_LART 27
+#define MACH_TYPE_RANGER 28
#define MACH_TYPE_GRAPHICSCLIENT 29
#define MACH_TYPE_XP860 30
#define MACH_TYPE_CERF 31
#define MACH_TYPE_NANOENGINE 32
+#define MACH_TYPE_FPIC 33
+#define MACH_TYPE_EXTENEX1 34
+#define MACH_TYPE_SHERMAN 35
+#define MACH_TYPE_ACCELENT_SA 36
+#define MACH_TYPE_ACCELENT_L7200 37
+#define MACH_TYPE_NETPORT 38
+#define MACH_TYPE_PANGOLIN 39
+#define MACH_TYPE_YOPY 40
+#define MACH_TYPE_COOLIDGE 41
+#define MACH_TYPE_HUW_WEBPANEL 42
+#define MACH_TYPE_SPOTME 43
+#define MACH_TYPE_FREEBIRD 44
+#define MACH_TYPE_TI925 45
+#define MACH_TYPE_RISCSTATION 46
+#define MACH_TYPE_CAVY 47
#define MACH_TYPE_JORNADA720 48
+#define MACH_TYPE_OMNIMETER 49
#define MACH_TYPE_EDB7211 50
+#define MACH_TYPE_CITYGO 51
#define MACH_TYPE_PFS168 52
+#define MACH_TYPE_SPOT 53
#define MACH_TYPE_FLEXANET 54
+#define MACH_TYPE_WEBPAL 55
+#define MACH_TYPE_LINPDA 56
+#define MACH_TYPE_ANAKIN 57
+#define MACH_TYPE_MVI 58
+#define MACH_TYPE_JUPITER 59
+#define MACH_TYPE_PSIONW 60
+#define MACH_TYPE_ALN 61
+#define MACH_TYPE_CAMELOT 62
+#define MACH_TYPE_GDS2200 63
+#define MACH_TYPE_PSION_SERIES7 64
+#define MACH_TYPE_XFILE 65
+#define MACH_TYPE_ACCELENT_EP9312 66
+#define MACH_TYPE_IC200 67
+#define MACH_TYPE_CREDITLART 68
+#define MACH_TYPE_HTM 69
+#define MACH_TYPE_IQ80310 70
+#define MACH_TYPE_FREEBOT 71
+#define MACH_TYPE_ENTEL 72
+#define MACH_TYPE_ENP3510 73
+#define MACH_TYPE_TRIZEPS 74
+#define MACH_TYPE_NESA 75
+#define MACH_TYPE_VENUS 76
+#define MACH_TYPE_TARDIS 77
+#define MACH_TYPE_MERCURY 78
+#define MACH_TYPE_EMPEG 79
+#define MACH_TYPE_I80200FCC 80
+#define MACH_TYPE_ITT_CPB 81
+#define MACH_TYPE_SVC 82
+#define MACH_TYPE_ALPHA2 84
+#define MACH_TYPE_ALPHA1 85
+#define MACH_TYPE_NETARM 86
#define MACH_TYPE_SIMPAD 87
+#define MACH_TYPE_PDA1 88
#define MACH_TYPE_LUBBOCK 89
+#define MACH_TYPE_ANIKO 90
#define MACH_TYPE_CLEP7212 91
+#define MACH_TYPE_CS89712 92
+#define MACH_TYPE_WEARARM 93
+#define MACH_TYPE_POSSIO_PX 94
+#define MACH_TYPE_SIDEARM 95
+#define MACH_TYPE_STORK 96
#define MACH_TYPE_SHANNON 97
+#define MACH_TYPE_ACE 98
+#define MACH_TYPE_BALLYARM 99
+#define MACH_TYPE_SIMPUTER 100
+#define MACH_TYPE_NEXTERM 101
+#define MACH_TYPE_SA1100_ELF 102
+#define MACH_TYPE_GATOR 103
+#define MACH_TYPE_GRANITE 104
#define MACH_TYPE_CONSUS 105
#define MACH_TYPE_AAED2000 106
#define MACH_TYPE_CDB89712 107
#define MACH_TYPE_GRAPHICSMASTER 108
#define MACH_TYPE_ADSBITSY 109
#define MACH_TYPE_PXA_IDP 110
+#define MACH_TYPE_PLCE 111
#define MACH_TYPE_PT_SYSTEM3 112
+#define MACH_TYPE_MEDALB 113
+#define MACH_TYPE_EAGLE 114
+#define MACH_TYPE_DSC21 115
+#define MACH_TYPE_DSC24 116
+#define MACH_TYPE_TI5472 117
#define MACH_TYPE_AUTCPU12 118
+#define MACH_TYPE_UENGINE 119
+#define MACH_TYPE_BLUESTEM 120
+#define MACH_TYPE_XINGU8 121
+#define MACH_TYPE_BUSHSTB 122
+#define MACH_TYPE_EPSILON1 123
+#define MACH_TYPE_BALLOON 124
+#define MACH_TYPE_PUPPY 125
+#define MACH_TYPE_ELROY 126
+#define MACH_TYPE_GMS720 127
+#define MACH_TYPE_S24X 128
+#define MACH_TYPE_JTEL_CLEP7312 129
+#define MACH_TYPE_CX821XX 130
+#define MACH_TYPE_EDB7312 131
+#define MACH_TYPE_BSA1110 132
+#define MACH_TYPE_POWERPIN 133
+#define MACH_TYPE_OPENARM 134
+#define MACH_TYPE_WHITECHAPEL 135
#define MACH_TYPE_H3100 136
+#define MACH_TYPE_H3800 137
+#define MACH_TYPE_BLUE_V1 138
+#define MACH_TYPE_PXA_CERF 139
+#define MACH_TYPE_ARM7TEVB 140
+#define MACH_TYPE_D7400 141
+#define MACH_TYPE_PIRANHA 142
+#define MACH_TYPE_SBCAMELOT 143
+#define MACH_TYPE_KINGS 144
+#define MACH_TYPE_SMDK2400 145
#define MACH_TYPE_COLLIE 146
+#define MACH_TYPE_IDR 147
#define MACH_TYPE_BADGE4 148
+#define MACH_TYPE_WEBNET 149
+#define MACH_TYPE_D7300 150
+#define MACH_TYPE_CEP 151
#define MACH_TYPE_FORTUNET 152
+#define MACH_TYPE_VC547X 153
+#define MACH_TYPE_FILEWALKER 154
+#define MACH_TYPE_NETGATEWAY 155
+#define MACH_TYPE_SYMBOL2800 156
+#define MACH_TYPE_SUNS 157
+#define MACH_TYPE_FRODO 158
+#define MACH_TYPE_MACH_TYTE_MS301 159
#define MACH_TYPE_MX1ADS 160
#define MACH_TYPE_H7201 161
#define MACH_TYPE_H7202 162
+#define MACH_TYPE_AMICO 163
+#define MACH_TYPE_IAM 164
+#define MACH_TYPE_TT530 165
+#define MACH_TYPE_SAM2400 166
+#define MACH_TYPE_JORNADA56X 167
+#define MACH_TYPE_ACTIVE 168
#define MACH_TYPE_IQ80321 169
+#define MACH_TYPE_WID 170
+#define MACH_TYPE_SABINAL 171
+#define MACH_TYPE_IXP425_MATACUMBE 172
+#define MACH_TYPE_MINIPRINT 173
+#define MACH_TYPE_ADM510X 174
+#define MACH_TYPE_SVS200 175
+#define MACH_TYPE_ATG_TCU 176
+#define MACH_TYPE_JORNADA820 177
+#define MACH_TYPE_S3C44B0 178
+#define MACH_TYPE_MARGIS2 179
#define MACH_TYPE_KS8695 180
+#define MACH_TYPE_BRH 181
+#define MACH_TYPE_S3C2410 182
+#define MACH_TYPE_POSSIO_PX30 183
+#define MACH_TYPE_S3C2800 184
+#define MACH_TYPE_FLEETWOOD 185
+#define MACH_TYPE_OMAHA 186
+#define MACH_TYPE_TA7 187
+#define MACH_TYPE_NOVA 188
+#define MACH_TYPE_HMK 189
+#define MACH_TYPE_KARO 190
+#define MACH_TYPE_FESTER 191
+#define MACH_TYPE_GPI 192
#define MACH_TYPE_SMDK2410 193
+#define MACH_TYPE_I519 194
+#define MACH_TYPE_NEXIO 195
+#define MACH_TYPE_BITBOX 196
+#define MACH_TYPE_G200 197
+#define MACH_TYPE_GILL 198
+#define MACH_TYPE_PXA_MERCURY 199
#define MACH_TYPE_CEIVA 200
+#define MACH_TYPE_FRET 201
+#define MACH_TYPE_EMAILPHONE 202
+#define MACH_TYPE_H3900 203
+#define MACH_TYPE_PXA1 204
+#define MACH_TYPE_KOAN369 205
+#define MACH_TYPE_COGENT 206
+#define MACH_TYPE_ESL_SIMPUTER 207
+#define MACH_TYPE_ESL_SIMPUTER_CLR 208
+#define MACH_TYPE_ESL_SIMPUTER_BW 209
+#define MACH_TYPE_HHP_CRADLE 210
+#define MACH_TYPE_HE500 211
+#define MACH_TYPE_INHANDELF2 212
+#define MACH_TYPE_INHANDFTIP 213
+#define MACH_TYPE_DNP1110 214
+#define MACH_TYPE_PNP1110 215
+#define MACH_TYPE_CSB226 216
+#define MACH_TYPE_ARNOLD 217
#define MACH_TYPE_VOICEBLUE 218
+#define MACH_TYPE_JZ8028 219
#define MACH_TYPE_H5400 220
+#define MACH_TYPE_FORTE 221
+#define MACH_TYPE_ACAM 222
+#define MACH_TYPE_ABOX 223
+#define MACH_TYPE_ATMEL 224
+#define MACH_TYPE_SITSANG 225
+#define MACH_TYPE_CPU1110LCDNET 226
+#define MACH_TYPE_MPL_VCMA9 227
+#define MACH_TYPE_OPUS_A1 228
+#define MACH_TYPE_DAYTONA 229
+#define MACH_TYPE_KILLBEAR 230
+#define MACH_TYPE_YOHO 231
+#define MACH_TYPE_JASPER 232
+#define MACH_TYPE_DSC25 233
#define MACH_TYPE_OMAP_INNOVATOR 234
+#define MACH_TYPE_RAMSES 235
+#define MACH_TYPE_S28X 236
+#define MACH_TYPE_MPORT3 237
+#define MACH_TYPE_PXA_EAGLE250 238
+#define MACH_TYPE_PDB 239
+#define MACH_TYPE_BLUE_2G 240
+#define MACH_TYPE_BLUEARCH 241
#define MACH_TYPE_IXDP2400 242
#define MACH_TYPE_IXDP2800 243
+#define MACH_TYPE_EXPLORER 244
#define MACH_TYPE_IXDP425 245
+#define MACH_TYPE_CHIMP 246
+#define MACH_TYPE_STORK_NEST 247
+#define MACH_TYPE_STORK_EGG 248
+#define MACH_TYPE_WISMO 249
+#define MACH_TYPE_EZLINX 250
+#define MACH_TYPE_AT91RM9200 251
+#define MACH_TYPE_ADTECH_ORION 252
+#define MACH_TYPE_NEPTUNE 253
#define MACH_TYPE_HACKKIT 254
+#define MACH_TYPE_PXA_WINS30 255
+#define MACH_TYPE_LAVINNA 256
+#define MACH_TYPE_PXA_UENGINE 257
+#define MACH_TYPE_INNOKOM 258
+#define MACH_TYPE_BMS 259
#define MACH_TYPE_IXCDP1100 260
+#define MACH_TYPE_PRPMC1100 261
#define MACH_TYPE_AT91RM9200DK 262
+#define MACH_TYPE_ARMSTICK 263
+#define MACH_TYPE_ARMONIE 264
+#define MACH_TYPE_MPORT1 265
+#define MACH_TYPE_S3C5410 266
+#define MACH_TYPE_ZCP320A 267
+#define MACH_TYPE_I_BOX 268
+#define MACH_TYPE_STLC1502 269
+#define MACH_TYPE_SIREN 270
+#define MACH_TYPE_GREENLAKE 271
+#define MACH_TYPE_ARGUS 272
+#define MACH_TYPE_COMBADGE 273
+#define MACH_TYPE_ROKEPXA 274
#define MACH_TYPE_CINTEGRATOR 275
+#define MACH_TYPE_GUIDEA07 276
+#define MACH_TYPE_TAT257 277
+#define MACH_TYPE_IGP2425 278
+#define MACH_TYPE_BLUEGRAMMA 279
+#define MACH_TYPE_IPOD 280
+#define MACH_TYPE_ADSBITSYX 281
+#define MACH_TYPE_TRIZEPS2 282
#define MACH_TYPE_VIPER 283
+#define MACH_TYPE_ADSBITSYPLUS 284
+#define MACH_TYPE_ADSAGC 285
+#define MACH_TYPE_STP7312 286
+#define MACH_TYPE_NX_PHNX 287
+#define MACH_TYPE_WEP_EP250 288
+#define MACH_TYPE_INHANDELF3 289
#define MACH_TYPE_ADI_COYOTE 290
+#define MACH_TYPE_IYONIX 291
+#define MACH_TYPE_DAMICAM_SA1110 292
+#define MACH_TYPE_MEG03 293
+#define MACH_TYPE_PXA_WHITECHAPEL 294
+#define MACH_TYPE_NWSC 295
+#define MACH_TYPE_NWLARM 296
+#define MACH_TYPE_IXP425_MGUARD 297
+#define MACH_TYPE_PXA_NETDCU4 298
#define MACH_TYPE_IXDP2401 299
#define MACH_TYPE_IXDP2801 300
+#define MACH_TYPE_ZODIAC 301
+#define MACH_TYPE_ARMMODUL 302
+#define MACH_TYPE_KETOP 303
+#define MACH_TYPE_AV7200 304
+#define MACH_TYPE_ARCH_TI925 305
+#define MACH_TYPE_ACQ200 306
+#define MACH_TYPE_PT_DAFIT 307
+#define MACH_TYPE_IHBA 308
+#define MACH_TYPE_QUINQUE 309
+#define MACH_TYPE_NIMBRAONE 310
+#define MACH_TYPE_NIMBRA29X 311
+#define MACH_TYPE_NIMBRA210 312
+#define MACH_TYPE_HHP_D95XX 313
+#define MACH_TYPE_LABARM 314
+#define MACH_TYPE_M825XX 315
+#define MACH_TYPE_M7100 316
+#define MACH_TYPE_NIPC2 317
+#define MACH_TYPE_FU7202 318
+#define MACH_TYPE_ADSAGX 319
+#define MACH_TYPE_PXA_POOH 320
+#define MACH_TYPE_BANDON 321
+#define MACH_TYPE_PCM7210 322
+#define MACH_TYPE_NMS9200 323
+#define MACH_TYPE_LOGODL 324
+#define MACH_TYPE_M7140 325
+#define MACH_TYPE_KOREBOT 326
#define MACH_TYPE_IQ31244 327
+#define MACH_TYPE_KOAN393 328
+#define MACH_TYPE_INHANDFTIP3 329
+#define MACH_TYPE_GONZO 330
#define MACH_TYPE_BAST 331
+#define MACH_TYPE_SCANPASS 332
+#define MACH_TYPE_EP7312_POOH 333
+#define MACH_TYPE_TA7S 334
+#define MACH_TYPE_TA7V 335
+#define MACH_TYPE_ICARUS 336
+#define MACH_TYPE_H1900 337
+#define MACH_TYPE_GEMINI 338
+#define MACH_TYPE_AXIM 339
+#define MACH_TYPE_AUDIOTRON 340
+#define MACH_TYPE_H2200 341
+#define MACH_TYPE_LOOX600 342
+#define MACH_TYPE_NIOP 343
+#define MACH_TYPE_DM310 344
+#define MACH_TYPE_SEEDPXA_C2 345
+#define MACH_TYPE_IXP4XX_MGUARD_PCI 346
#define MACH_TYPE_H1940 347
+#define MACH_TYPE_SCORPIO 348
+#define MACH_TYPE_VIVA 349
+#define MACH_TYPE_PXA_XCARD 350
+#define MACH_TYPE_CSB335 351
+#define MACH_TYPE_IXRD425 352
+#define MACH_TYPE_IQ80315 353
+#define MACH_TYPE_NMP7312 354
+#define MACH_TYPE_CX861XX 355
#define MACH_TYPE_ENP2611 356
+#define MACH_TYPE_XDA 357
+#define MACH_TYPE_CSIR_IMS 358
+#define MACH_TYPE_IXP421_DNAEETH 359
+#define MACH_TYPE_POCKETSERV9200 360
+#define MACH_TYPE_TOTO 361
#define MACH_TYPE_S3C2440 362
+#define MACH_TYPE_KS8695P 363
+#define MACH_TYPE_SE4000 364
+#define MACH_TYPE_QUADRICEPS 365
+#define MACH_TYPE_BRONCO 366
+#define MACH_TYPE_ESL_WIRELESS_TAB 367
+#define MACH_TYPE_ESL_SOFCOMP 368
+#define MACH_TYPE_S5C7375 369
+#define MACH_TYPE_SPEARHEAD 370
+#define MACH_TYPE_PANTERA 371
+#define MACH_TYPE_PRAYOGLITE 372
#define MACH_TYPE_GUMSTIX 373
+#define MACH_TYPE_RCUBE 374
+#define MACH_TYPE_REA_OLV 375
+#define MACH_TYPE_PXA_IPHONE 376
+#define MACH_TYPE_S3C3410 377
+#define MACH_TYPE_ESPD_4510B 378
+#define MACH_TYPE_MP1X 379
+#define MACH_TYPE_AT91RM9200TB 380
+#define MACH_TYPE_ADSVGX 381
#define MACH_TYPE_OMAP_H2 382
+#define MACH_TYPE_PELEE 383
#define MACH_TYPE_E740 384
#define MACH_TYPE_IQ80331 385
#define MACH_TYPE_VERSATILE_PB 387
#define MACH_TYPE_KEV7A400 388
#define MACH_TYPE_LPD7A400 389
#define MACH_TYPE_LPD7A404 390
+#define MACH_TYPE_FUJITSU_CAMELOT 391
+#define MACH_TYPE_JANUS2M 392
+#define MACH_TYPE_EMBTF 393
+#define MACH_TYPE_HPM 394
+#define MACH_TYPE_SMDK2410TK 395
+#define MACH_TYPE_SMDK2410AJ 396
+#define MACH_TYPE_STREETRACER 397
+#define MACH_TYPE_EFRAME 398
#define MACH_TYPE_CSB337 399
+#define MACH_TYPE_PXA_LARK 400
+#define MACH_TYPE_PNP2110 401
+#define MACH_TYPE_TCC72X 402
+#define MACH_TYPE_ALTAIR 403
+#define MACH_TYPE_KC3 404
+#define MACH_TYPE_SINTEFTD 405
#define MACH_TYPE_MAINSTONE 406
+#define MACH_TYPE_ADAY4X 407
#define MACH_TYPE_LITE300 408
+#define MACH_TYPE_S5C7376 409
+#define MACH_TYPE_MT02 410
+#define MACH_TYPE_MPORT3S 411
+#define MACH_TYPE_RA_ALPHA 412
#define MACH_TYPE_XCEP 413
#define MACH_TYPE_ARCOM_VULCAN 414
+#define MACH_TYPE_STARGATE 415
+#define MACH_TYPE_ARMADILLOJ 416
+#define MACH_TYPE_ELROY_JACK 417
+#define MACH_TYPE_BACKEND 418
+#define MACH_TYPE_S5LINBOX 419
#define MACH_TYPE_NOMADIK 420
+#define MACH_TYPE_IA_CPU_9200 421
+#define MACH_TYPE_AT91_BJA1 422
#define MACH_TYPE_CORGI 423
#define MACH_TYPE_POODLE 424
+#define MACH_TYPE_TEN 425
+#define MACH_TYPE_ROVERP5P 426
+#define MACH_TYPE_SC2700 427
+#define MACH_TYPE_EX_EAGLE 428
+#define MACH_TYPE_NX_PXA12 429
+#define MACH_TYPE_NX_PXA5 430
+#define MACH_TYPE_BLACKBOARD2 431
+#define MACH_TYPE_I819 432
+#define MACH_TYPE_IXMB995E 433
+#define MACH_TYPE_SKYRIDER 434
+#define MACH_TYPE_SKYHAWK 435
+#define MACH_TYPE_ENTERPRISE 436
+#define MACH_TYPE_DEP2410 437
#define MACH_TYPE_ARMCORE 438
+#define MACH_TYPE_HOBBIT 439
+#define MACH_TYPE_H7210 440
+#define MACH_TYPE_PXA_NETDCU5 441
+#define MACH_TYPE_ACC 442
+#define MACH_TYPE_ESL_SARVA 443
+#define MACH_TYPE_XM250 444
+#define MACH_TYPE_T6TC1XB 445
+#define MACH_TYPE_ESS710 446
#define MACH_TYPE_MX31ADS 447
#define MACH_TYPE_HIMALAYA 448
+#define MACH_TYPE_BOLFENK 449
+#define MACH_TYPE_AT91RM9200KR 450
#define MACH_TYPE_EDB9312 451
#define MACH_TYPE_OMAP_GENERIC 452
+#define MACH_TYPE_AXIMX3 453
+#define MACH_TYPE_EB67XDIP 454
+#define MACH_TYPE_WEBTXS 455
+#define MACH_TYPE_HAWK 456
+#define MACH_TYPE_CCAT91SBC001 457
+#define MACH_TYPE_EXPRESSO 458
+#define MACH_TYPE_H4000 459
+#define MACH_TYPE_DINO 460
+#define MACH_TYPE_ML675K 461
#define MACH_TYPE_EDB9301 462
#define MACH_TYPE_EDB9315 463
+#define MACH_TYPE_RECIVA_TT 464
+#define MACH_TYPE_CSTCB01 465
+#define MACH_TYPE_CSTCB1 466
+#define MACH_TYPE_SHADWELL 467
+#define MACH_TYPE_GOEPEL263 468
+#define MACH_TYPE_ACQ100 469
+#define MACH_TYPE_MX1FS2 470
+#define MACH_TYPE_HIPTOP_G1 471
+#define MACH_TYPE_SPARKY 472
+#define MACH_TYPE_NS9750 473
+#define MACH_TYPE_PHOENIX 474
#define MACH_TYPE_VR1000 475
+#define MACH_TYPE_DEISTERPXA 476
+#define MACH_TYPE_BCM1160 477
+#define MACH_TYPE_PCM022 478
+#define MACH_TYPE_ADSGCX 479
+#define MACH_TYPE_DREADNAUGHT 480
+#define MACH_TYPE_DM320 481
+#define MACH_TYPE_MARKOV 482
+#define MACH_TYPE_COS7A400 483
+#define MACH_TYPE_MILANO 484
+#define MACH_TYPE_UE9328 485
+#define MACH_TYPE_UEX255 486
+#define MACH_TYPE_UE2410 487
+#define MACH_TYPE_A620 488
+#define MACH_TYPE_OCELOT 489
+#define MACH_TYPE_CHEETAH 490
#define MACH_TYPE_OMAP_PERSEUS2 491
+#define MACH_TYPE_ZVUE 492
+#define MACH_TYPE_ROVERP1 493
+#define MACH_TYPE_ASIDIAL2 494
+#define MACH_TYPE_S3C24A0 495
#define MACH_TYPE_E800 496
#define MACH_TYPE_E750 497
+#define MACH_TYPE_S3C5500 498
+#define MACH_TYPE_SMDK5500 499
+#define MACH_TYPE_SIGNALSYNC 500
+#define MACH_TYPE_NBC 501
+#define MACH_TYPE_KODIAK 502
+#define MACH_TYPE_NETBOOKPRO 503
+#define MACH_TYPE_HW90200 504
+#define MACH_TYPE_CONDOR 505
+#define MACH_TYPE_CUP 506
+#define MACH_TYPE_KITE 507
#define MACH_TYPE_SCB9328 508
#define MACH_TYPE_OMAP_H3 509
#define MACH_TYPE_OMAP_H4 510
+#define MACH_TYPE_N10 511
+#define MACH_TYPE_MONTAJADE 512
+#define MACH_TYPE_SG560 513
+#define MACH_TYPE_DP1000 514
#define MACH_TYPE_OMAP_OSK 515
+#define MACH_TYPE_RG100V3 516
+#define MACH_TYPE_MX2ADS 517
+#define MACH_TYPE_PXA_KILO 518
+#define MACH_TYPE_IXP4XX_EAGLE 519
#define MACH_TYPE_TOSA 520
+#define MACH_TYPE_MB2520F 521
+#define MACH_TYPE_EMC1000 522
+#define MACH_TYPE_TIDSC25 523
+#define MACH_TYPE_AKCPMXL 524
+#define MACH_TYPE_AV3XX 525
#define MACH_TYPE_AVILA 526
+#define MACH_TYPE_PXA_MPM10 527
+#define MACH_TYPE_PXA_KYANITE 528
+#define MACH_TYPE_SGOLD 529
+#define MACH_TYPE_OSCAR 530
+#define MACH_TYPE_EPXA4USB2 531
+#define MACH_TYPE_XSENGINE 532
+#define MACH_TYPE_IP600 533
+#define MACH_TYPE_MCAN2 534
+#define MACH_TYPE_DDI_BLUERIDGE 535
+#define MACH_TYPE_SKYMINDER 536
+#define MACH_TYPE_LPD79520 537
#define MACH_TYPE_EDB9302 538
+#define MACH_TYPE_HW90340 539
+#define MACH_TYPE_CIP_BOX 540
+#define MACH_TYPE_IVPN 541
+#define MACH_TYPE_RSOC2 542
#define MACH_TYPE_HUSKY 543
+#define MACH_TYPE_BOXER 544
#define MACH_TYPE_SHEPHERD 545
+#define MACH_TYPE_AML42800AA 546
+#define MACH_TYPE_LPC2294 548
+#define MACH_TYPE_SWITCHGRASS 549
+#define MACH_TYPE_ENS_CMU 550
+#define MACH_TYPE_MM6_SDB 551
+#define MACH_TYPE_SATURN 552
+#define MACH_TYPE_I30030EVB 553
+#define MACH_TYPE_MXC27530EVB 554
+#define MACH_TYPE_SMDK2800 555
+#define MACH_TYPE_MTWILSON 556
+#define MACH_TYPE_ZITI 557
+#define MACH_TYPE_GRANDFATHER 558
+#define MACH_TYPE_TENGINE 559
+#define MACH_TYPE_S3C2460 560
+#define MACH_TYPE_PDM 561
#define MACH_TYPE_H4700 562
+#define MACH_TYPE_H6300 563
+#define MACH_TYPE_RZ1700 564
+#define MACH_TYPE_A716 565
+#define MACH_TYPE_ESTK2440A 566
+#define MACH_TYPE_ATWIXP425 567
+#define MACH_TYPE_CSB336 568
+#define MACH_TYPE_RIRM2 569
+#define MACH_TYPE_CX23518 570
+#define MACH_TYPE_CX2351X 571
+#define MACH_TYPE_COMPUTIME 572
+#define MACH_TYPE_IZARUS 573
+#define MACH_TYPE_RTS 574
+#define MACH_TYPE_SE5100 575
+#define MACH_TYPE_S3C2510 576
+#define MACH_TYPE_CSB437TL 577
+#define MACH_TYPE_SLAUSON 578
+#define MACH_TYPE_PEARLRIVER 579
+#define MACH_TYPE_TDC_P210 580
+#define MACH_TYPE_SG580 581
+#define MACH_TYPE_WRSBCARM7 582
+#define MACH_TYPE_IPD 583
+#define MACH_TYPE_PXA_DNP2110 584
+#define MACH_TYPE_XAENIAX 585
+#define MACH_TYPE_SOMN4250 586
+#define MACH_TYPE_PLEB2 587
+#define MACH_TYPE_CORNWALLIS 588
+#define MACH_TYPE_GURNEY_DRV 589
+#define MACH_TYPE_CHAFFEE 590
+#define MACH_TYPE_RMS101 591
#define MACH_TYPE_RX3715 592
+#define MACH_TYPE_SWIFT 593
+#define MACH_TYPE_ROVERP7 594
+#define MACH_TYPE_PR818S 595
+#define MACH_TYPE_TRXPRO 596
#define MACH_TYPE_NSLU2 597
#define MACH_TYPE_E400 598
+#define MACH_TYPE_TRAB 599
+#define MACH_TYPE_CMC_PU2 600
+#define MACH_TYPE_FULCRUM 601
+#define MACH_TYPE_NETGATE42X 602
+#define MACH_TYPE_STR710 603
#define MACH_TYPE_IXDPG425 604
+#define MACH_TYPE_TOMTOMGO 605
#define MACH_TYPE_VERSATILE_AB 606
#define MACH_TYPE_EDB9307 607
+#define MACH_TYPE_SG565 608
+#define MACH_TYPE_LPD79524 609
+#define MACH_TYPE_LPD79525 610
+#define MACH_TYPE_RMS100 611
#define MACH_TYPE_KB9200 612
#define MACH_TYPE_SX1 613
+#define MACH_TYPE_HMS39C7092 614
+#define MACH_TYPE_ARMADILLO 615
+#define MACH_TYPE_IPCU 616
+#define MACH_TYPE_LOOX720 617
#define MACH_TYPE_IXDP465 618
#define MACH_TYPE_IXDP2351 619
+#define MACH_TYPE_ADSVIX 620
+#define MACH_TYPE_DM270 621
+#define MACH_TYPE_SOCLTPLUS 622
+#define MACH_TYPE_ECIA 623
#define MACH_TYPE_CM4008 624
+#define MACH_TYPE_P2001 625
+#define MACH_TYPE_TWISTER 626
+#define MACH_TYPE_MUDSHARK 627
+#define MACH_TYPE_HB2 628
#define MACH_TYPE_IQ80332 629
+#define MACH_TYPE_SENDT 630
+#define MACH_TYPE_MX2JAZZ 631
+#define MACH_TYPE_MULTIIO 632
+#define MACH_TYPE_HRDISPLAY 633
+#define MACH_TYPE_MXC27530ADS 634
+#define MACH_TYPE_TRIZEPS3 635
+#define MACH_TYPE_ZEFEERDZA 636
+#define MACH_TYPE_ZEFEERDZB 637
+#define MACH_TYPE_ZEFEERDZG 638
+#define MACH_TYPE_ZEFEERDZN 639
+#define MACH_TYPE_ZEFEERDZQ 640
#define MACH_TYPE_GTWX5715 641
+#define MACH_TYPE_ASTRO_JACK 643
+#define MACH_TYPE_TIP03 644
+#define MACH_TYPE_A9200EC 645
+#define MACH_TYPE_PNX0105 646
+#define MACH_TYPE_ADCPOECPU 647
#define MACH_TYPE_CSB637 648
+#define MACH_TYPE_MB9200 650
+#define MACH_TYPE_KULUN 651
+#define MACH_TYPE_SNAPPER 652
+#define MACH_TYPE_OPTIMA 653
+#define MACH_TYPE_DLHSBC 654
+#define MACH_TYPE_X30 655
#define MACH_TYPE_N30 656
+#define MACH_TYPE_MANGA_KS8695 657
+#define MACH_TYPE_AJAX 658
#define MACH_TYPE_NEC_MP900 659
+#define MACH_TYPE_VVTK1000 661
#define MACH_TYPE_KAFA 662
+#define MACH_TYPE_VVTK3000 663
+#define MACH_TYPE_PIMX1 664
+#define MACH_TYPE_OLLIE 665
+#define MACH_TYPE_SKYMAX 666
+#define MACH_TYPE_JAZZ 667
+#define MACH_TYPE_TEL_T3 668
+#define MACH_TYPE_AISINO_FCR255 669
+#define MACH_TYPE_BTWEB 670
+#define MACH_TYPE_DBG_LH79520 671
#define MACH_TYPE_CM41XX 672
#define MACH_TYPE_TS72XX 673
+#define MACH_TYPE_NGGPXA 674
+#define MACH_TYPE_CSB535 675
+#define MACH_TYPE_CSB536 676
+#define MACH_TYPE_PXA_TRAKPOD 677
+#define MACH_TYPE_PRAXIS 678
+#define MACH_TYPE_LH75411 679
#define MACH_TYPE_OTOM 680
#define MACH_TYPE_NEXCODER_2440 681
+#define MACH_TYPE_LOOX410 682
+#define MACH_TYPE_WESTLAKE 683
+#define MACH_TYPE_NSB 684
+#define MACH_TYPE_ESL_SARVA_STN 685
+#define MACH_TYPE_ESL_SARVA_TFT 686
+#define MACH_TYPE_ESL_SARVA_IAD 687
+#define MACH_TYPE_ESL_SARVA_ACC 688
+#define MACH_TYPE_TYPHOON 689
+#define MACH_TYPE_CNAV 690
+#define MACH_TYPE_A730 691
+#define MACH_TYPE_NETSTAR 692
+#define MACH_TYPE_PHASEFALE_SUPERCON 693
+#define MACH_TYPE_SHIVA1100 694
+#define MACH_TYPE_ETEXSC 695
+#define MACH_TYPE_IXDPG465 696
+#define MACH_TYPE_A9M2410 697
+#define MACH_TYPE_A9M2440 698
+#define MACH_TYPE_A9M9750 699
+#define MACH_TYPE_A9M9360 700
+#define MACH_TYPE_UNC90 701
#define MACH_TYPE_ECO920 702
+#define MACH_TYPE_SATVIEW 703
#define MACH_TYPE_ROADRUNNER 704
#define MACH_TYPE_AT91RM9200EK 705
+#define MACH_TYPE_GP32 706
+#define MACH_TYPE_GEM 707
+#define MACH_TYPE_I858 708
+#define MACH_TYPE_HX2750 709
+#define MACH_TYPE_MXC91131EVB 710
+#define MACH_TYPE_P700 711
+#define MACH_TYPE_CPE 712
#define MACH_TYPE_SPITZ 713
+#define MACH_TYPE_NIMBRA340 714
+#define MACH_TYPE_LPC22XX 715
+#define MACH_TYPE_COMET3 716
+#define MACH_TYPE_COMET4 717
+#define MACH_TYPE_CSB625 718
+#define MACH_TYPE_FORTUNET2 719
+#define MACH_TYPE_S5H2200 720
+#define MACH_TYPE_OPTORM920 721
+#define MACH_TYPE_ADSBITSYXB 722
#define MACH_TYPE_ADSSPHERE 723
+#define MACH_TYPE_ADSPORTAL 724
+#define MACH_TYPE_LN2410SBC 725
+#define MACH_TYPE_CB3RUFC 726
+#define MACH_TYPE_MP2USB 727
+#define MACH_TYPE_NTNP425C 728
#define MACH_TYPE_COLIBRI 729
+#define MACH_TYPE_PCM7220 730
#define MACH_TYPE_GATEWAY7001 731
#define MACH_TYPE_PCM027 732
+#define MACH_TYPE_CMPXA 733
#define MACH_TYPE_ANUBIS 734
+#define MACH_TYPE_ITE8152 735
+#define MACH_TYPE_LPC3XXX 736
+#define MACH_TYPE_PUPPETEER 737
+#define MACH_TYPE_E570 739
+#define MACH_TYPE_X50 740
+#define MACH_TYPE_RECON 741
#define MACH_TYPE_XBOARDGP8 742
+#define MACH_TYPE_FPIC2 743
#define MACH_TYPE_AKITA 744
+#define MACH_TYPE_A81 745
+#define MACH_TYPE_SVM_SC25X 746
+#define MACH_TYPE_VADATECH020 747
+#define MACH_TYPE_TLI 748
+#define MACH_TYPE_EDB9315LC 749
+#define MACH_TYPE_PASSEC 750
+#define MACH_TYPE_DS_TIGER 751
+#define MACH_TYPE_E310 752
#define MACH_TYPE_E330 753
+#define MACH_TYPE_RT3000 754
#define MACH_TYPE_NOKIA770 755
+#define MACH_TYPE_PNX0106 756
+#define MACH_TYPE_HX21XX 757
+#define MACH_TYPE_FARADAY 758
+#define MACH_TYPE_SBC9312 759
+#define MACH_TYPE_BATMAN 760
+#define MACH_TYPE_JPD201 761
+#define MACH_TYPE_MIPSA 762
+#define MACH_TYPE_KACOM 763
+#define MACH_TYPE_SWARCOCPU 764
+#define MACH_TYPE_SWARCODSL 765
+#define MACH_TYPE_BLUEANGEL 766
+#define MACH_TYPE_HAIRYGRAMA 767
+#define MACH_TYPE_BANFF 768
#define MACH_TYPE_CARMEVA 769
+#define MACH_TYPE_SAM255 770
+#define MACH_TYPE_PPM10 771
#define MACH_TYPE_EDB9315A 772
+#define MACH_TYPE_SUNSET 773
#define MACH_TYPE_STARGATE2 774
#define MACH_TYPE_INTELMOTE2 775
#define MACH_TYPE_TRIZEPS4 776
+#define MACH_TYPE_MAINSTONE2 777
+#define MACH_TYPE_EZ_IXP42X 778
+#define MACH_TYPE_TAPWAVE_ZODIAC 779
+#define MACH_TYPE_UNIVERSALMETER 780
+#define MACH_TYPE_HICOARM9 781
#define MACH_TYPE_PNX4008 782
+#define MACH_TYPE_KWS6000 783
+#define MACH_TYPE_PORTUX920T 784
+#define MACH_TYPE_EZ_X5 785
+#define MACH_TYPE_OMAP_RUDOLPH 786
#define MACH_TYPE_CPUAT91 787
+#define MACH_TYPE_REA9200 788
+#define MACH_TYPE_ACTS_PUNE_SA1110 789
+#define MACH_TYPE_IXP425 790
+#define MACH_TYPE_I30030ADS 791
+#define MACH_TYPE_PERCH 792
+#define MACH_TYPE_EIS05R1 793
+#define MACH_TYPE_PEPPERPAD 794
+#define MACH_TYPE_SB3010 795
+#define MACH_TYPE_RM9200 796
+#define MACH_TYPE_DMA03 797
+#define MACH_TYPE_ROAD_S101 798
#define MACH_TYPE_IQ81340SC 799
+#define MACH_TYPE_IQ_NEXTGEN_B 800
#define MACH_TYPE_IQ81340MC 801
+#define MACH_TYPE_IQ_NEXTGEN_D 802
+#define MACH_TYPE_IQ_NEXTGEN_E 803
+#define MACH_TYPE_MALLOW_AT91 804
+#define MACH_TYPE_CYBERTRACKER_I 805
+#define MACH_TYPE_GESBC931X 806
+#define MACH_TYPE_CENTIPAD 807
+#define MACH_TYPE_ARMSOC 808
#define MACH_TYPE_SE4200 809
+#define MACH_TYPE_EMS197A 810
#define MACH_TYPE_MICRO9 811
#define MACH_TYPE_MICRO9L 812
+#define MACH_TYPE_UC5471DSP 813
+#define MACH_TYPE_SJ5471ENG 814
+#define MACH_TYPE_CMPXA26X 815
+#define MACH_TYPE_NC 816
#define MACH_TYPE_OMAP_PALMTE 817
+#define MACH_TYPE_AJAX52X 818
+#define MACH_TYPE_SIRIUSTAR 819
+#define MACH_TYPE_IODATA_HDLG 820
+#define MACH_TYPE_AT91RM9200UTL 821
+#define MACH_TYPE_BIOSAFE 822
+#define MACH_TYPE_MP1000 823
+#define MACH_TYPE_PARSY 824
+#define MACH_TYPE_CCXP 825
+#define MACH_TYPE_OMAP_GSAMPLE 826
#define MACH_TYPE_REALVIEW_EB 827
+#define MACH_TYPE_SAMOA 828
+#define MACH_TYPE_PALMT3 829
+#define MACH_TYPE_I878 830
#define MACH_TYPE_BORZOI 831
+#define MACH_TYPE_GECKO 832
+#define MACH_TYPE_DS101 833
+#define MACH_TYPE_OMAP_PALMTT2 834
#define MACH_TYPE_PALMLD 835
+#define MACH_TYPE_CC9C 836
+#define MACH_TYPE_SBC1670 837
#define MACH_TYPE_IXDP28X5 838
#define MACH_TYPE_OMAP_PALMTT 839
+#define MACH_TYPE_ML696K 840
#define MACH_TYPE_ARCOM_ZEUS 841
#define MACH_TYPE_OSIRIS 842
+#define MACH_TYPE_MAESTRO 843
#define MACH_TYPE_PALMTE2 844
+#define MACH_TYPE_IXBBM 845
#define MACH_TYPE_MX27ADS 846
+#define MACH_TYPE_AX8004 847
#define MACH_TYPE_AT91SAM9261EK 848
#define MACH_TYPE_LOFT 849
+#define MACH_TYPE_MAGPIE 850
#define MACH_TYPE_MX21ADS 851
+#define MACH_TYPE_MB87M3400 852
+#define MACH_TYPE_MGUARD_DELTA 853
+#define MACH_TYPE_DAVINCI_DVDP 854
+#define MACH_TYPE_HTCUNIVERSAL 855
+#define MACH_TYPE_TPAD 856
+#define MACH_TYPE_ROVERP3 857
+#define MACH_TYPE_JORNADA928 858
+#define MACH_TYPE_MV88FXX81 859
+#define MACH_TYPE_STMP36XX 860
+#define MACH_TYPE_SXNI79524 861
#define MACH_TYPE_AMS_DELTA 862
+#define MACH_TYPE_URANIUM 863
+#define MACH_TYPE_UCON 864
#define MACH_TYPE_NAS100D 865
+#define MACH_TYPE_L083_1000 866
+#define MACH_TYPE_EZX 867
+#define MACH_TYPE_PNX5220 868
+#define MACH_TYPE_BUTTE 869
+#define MACH_TYPE_SRM2 870
+#define MACH_TYPE_DSBR 871
+#define MACH_TYPE_CRYSTALBALL 872
+#define MACH_TYPE_TINYPXA27X 873
+#define MACH_TYPE_HERBIE 874
#define MACH_TYPE_MAGICIAN 875
#define MACH_TYPE_CM4002 876
+#define MACH_TYPE_B4 877
+#define MACH_TYPE_MAUI 878
+#define MACH_TYPE_CYBERTRACKER_G 879
#define MACH_TYPE_NXDKN 880
+#define MACH_TYPE_MIO8390 881
+#define MACH_TYPE_OMI_BOARD 882
+#define MACH_TYPE_MX21CIV 883
+#define MACH_TYPE_MAHI_CDAC 884
#define MACH_TYPE_PALMTX 885
#define MACH_TYPE_S3C2413 887
+#define MACH_TYPE_SAMSYS_EP0 888
+#define MACH_TYPE_WG302V1 889
#define MACH_TYPE_WG302V2 890
+#define MACH_TYPE_EB42X 891
+#define MACH_TYPE_IQ331ES 892
+#define MACH_TYPE_COSYDSP 893
+#define MACH_TYPE_UPLAT7D 894
+#define MACH_TYPE_PTDAVINCI 895
+#define MACH_TYPE_MBUS 896
+#define MACH_TYPE_NADIA2VB 897
+#define MACH_TYPE_R1000 898
+#define MACH_TYPE_HW90250 899
#define MACH_TYPE_OMAP_2430SDP 900
#define MACH_TYPE_DAVINCI_EVM 901
+#define MACH_TYPE_OMAP_TORNADO 902
+#define MACH_TYPE_OLOCREEK 903
#define MACH_TYPE_PALMZ72 904
#define MACH_TYPE_NXDB500 905
#define MACH_TYPE_APF9328 906
+#define MACH_TYPE_OMAP_WIPOQ 907
+#define MACH_TYPE_OMAP_TWIP 908
+#define MACH_TYPE_TREO650 909
+#define MACH_TYPE_ACUMEN 910
+#define MACH_TYPE_XP100 911
+#define MACH_TYPE_FS2410 912
+#define MACH_TYPE_PXA270_CERF 913
+#define MACH_TYPE_SQ2FTLPALM 914
+#define MACH_TYPE_BSEMSERVER 915
+#define MACH_TYPE_NETCLIENT 916
#define MACH_TYPE_PALMT5 917
#define MACH_TYPE_PALMTC 918
#define MACH_TYPE_OMAP_APOLLON 919
+#define MACH_TYPE_MXC30030EVB 920
+#define MACH_TYPE_REA_2D 921
+#define MACH_TYPE_TI3E524 922
#define MACH_TYPE_ATEB9200 923
+#define MACH_TYPE_AUCKLAND 924
+#define MACH_TYPE_AK3320M 925
+#define MACH_TYPE_DURAMAX 926
#define MACH_TYPE_N35 927
+#define MACH_TYPE_PRONGHORN 928
+#define MACH_TYPE_FUNDY 929
#define MACH_TYPE_LOGICPD_PXA270 930
+#define MACH_TYPE_CPU777 931
+#define MACH_TYPE_SIMICON9201 932
+#define MACH_TYPE_LEAP2_HPM 933
+#define MACH_TYPE_CM922TXA10 934
+#define MACH_TYPE_PXA 935
+#define MACH_TYPE_SANDGATE2 936
+#define MACH_TYPE_SANDGATE2G 937
+#define MACH_TYPE_SANDGATE2P 938
+#define MACH_TYPE_FRED_JACK 939
+#define MACH_TYPE_TTG_COLOR1 940
#define MACH_TYPE_NXEB500HMI 941
+#define MACH_TYPE_NETDCU8 942
+#define MACH_TYPE_NG_FVX538 944
+#define MACH_TYPE_NG_FVS338 945
+#define MACH_TYPE_PNX4103 946
+#define MACH_TYPE_HESDB 947
+#define MACH_TYPE_XSILO 948
#define MACH_TYPE_ESPRESSO 949
+#define MACH_TYPE_EMLC 950
+#define MACH_TYPE_SISTERON 951
#define MACH_TYPE_RX1950 952
+#define MACH_TYPE_TSC_VENUS 953
+#define MACH_TYPE_DS101J 954
+#define MACH_TYPE_MXC30030ADS 955
+#define MACH_TYPE_FUJITSU_WIMAXSOC 956
+#define MACH_TYPE_DUALPCMODEM 957
#define MACH_TYPE_GESBC9312 958
+#define MACH_TYPE_HTCAPACHE 959
+#define MACH_TYPE_IXDP435 960
+#define MACH_TYPE_CATPROVT100 961
+#define MACH_TYPE_PICOTUX1XX 962
#define MACH_TYPE_PICOTUX2XX 963
#define MACH_TYPE_DSMG600 964
+#define MACH_TYPE_EMPC2 965
+#define MACH_TYPE_VENTURA 966
+#define MACH_TYPE_PHIDGET_SBC 967
+#define MACH_TYPE_IJ3K 968
+#define MACH_TYPE_PISGAH 969
#define MACH_TYPE_OMAP_FSAMPLE 970
+#define MACH_TYPE_SG720 971
+#define MACH_TYPE_REDFOX 972
+#define MACH_TYPE_MYSH_EP9315_1 973
+#define MACH_TYPE_TPF106 974
+#define MACH_TYPE_AT91RM9200KG 975
+#define MACH_TYPE_SLEDB 976
+#define MACH_TYPE_ONTRACK 977
+#define MACH_TYPE_PM1200 978
+#define MACH_TYPE_ESS24XXX 979
+#define MACH_TYPE_COREMP7 980
+#define MACH_TYPE_NEXCODER_6446 981
+#define MACH_TYPE_STVC8380 982
+#define MACH_TYPE_TEKLYNX 983
+#define MACH_TYPE_CARBONADO 984
+#define MACH_TYPE_SYSMOS_MP730 985
#define MACH_TYPE_SNAPPER_CL15 986
+#define MACH_TYPE_PGIGIM 987
+#define MACH_TYPE_PTX9160P2 988
+#define MACH_TYPE_DCORE1 989
+#define MACH_TYPE_VICTORPXA 990
+#define MACH_TYPE_MX2DTB 991
+#define MACH_TYPE_PXA_IREX_ER0100 992
#define MACH_TYPE_OMAP_PALMZ71 993
+#define MACH_TYPE_BARTEC_DEG 994
+#define MACH_TYPE_HW50251 995
+#define MACH_TYPE_IBOX 996
+#define MACH_TYPE_ATLASLH7A404 997
+#define MACH_TYPE_PT2026 998
+#define MACH_TYPE_HTCALPINE 999
+#define MACH_TYPE_BARTEC_VTU 1000
+#define MACH_TYPE_VCOREII 1001
+#define MACH_TYPE_PDNB3 1002
+#define MACH_TYPE_HTCBEETLES 1003
+#define MACH_TYPE_S3C6400 1004
+#define MACH_TYPE_S3C2443 1005
+#define MACH_TYPE_OMAP_LDK 1006
+#define MACH_TYPE_SMDK2460 1007
+#define MACH_TYPE_SMDK2440 1008
#define MACH_TYPE_SMDK2412 1009
+#define MACH_TYPE_WEBBOX 1010
+#define MACH_TYPE_CWWNDP 1011
+#define MACH_TYPE_DRAGON 1012
+#define MACH_TYPE_OPENDO_CPU_BOARD 1013
+#define MACH_TYPE_CCM2200 1014
+#define MACH_TYPE_ETWARM 1015
+#define MACH_TYPE_M93030 1016
+#define MACH_TYPE_CC7U 1017
+#define MACH_TYPE_MTT_RANGER 1018
+#define MACH_TYPE_NEXUS 1019
+#define MACH_TYPE_DESMAN 1020
+#define MACH_TYPE_BKDE303 1021
#define MACH_TYPE_SMDK2413 1022
+#define MACH_TYPE_AML_M7200 1023
#define MACH_TYPE_AML_M5900 1024
+#define MACH_TYPE_SG640 1025
+#define MACH_TYPE_EDG79524 1026
+#define MACH_TYPE_AI2410 1027
+#define MACH_TYPE_IXP465 1028
#define MACH_TYPE_BALLOON3 1029
+#define MACH_TYPE_HEINS 1030
+#define MACH_TYPE_MPLUSEVA 1031
+#define MACH_TYPE_RT042 1032
+#define MACH_TYPE_CWIEM 1033
+#define MACH_TYPE_CM_X270 1034
+#define MACH_TYPE_CM_X255 1035
+#define MACH_TYPE_ESH_AT91 1036
+#define MACH_TYPE_SANDGATE3 1037
+#define MACH_TYPE_PRIMO 1038
+#define MACH_TYPE_GEMSTONE 1039
+#define MACH_TYPE_PRONGHORNMETRO 1040
+#define MACH_TYPE_SIDEWINDER 1041
+#define MACH_TYPE_PICOMOD1 1042
+#define MACH_TYPE_SG590 1043
+#define MACH_TYPE_AKAI9307 1044
+#define MACH_TYPE_FONTAINE 1045
+#define MACH_TYPE_WOMBAT 1046
+#define MACH_TYPE_ACQ300 1047
+#define MACH_TYPE_MOD_270 1048
+#define MACH_TYPE_VC0820 1049
+#define MACH_TYPE_ANI_AIM 1050
+#define MACH_TYPE_JELLYFISH 1051
+#define MACH_TYPE_AMANITA 1052
+#define MACH_TYPE_VLINK 1053
+#define MACH_TYPE_DEXFLEX 1054
+#define MACH_TYPE_EIGEN_TTQ 1055
+#define MACH_TYPE_ARCOM_TITAN 1056
+#define MACH_TYPE_TABLA 1057
+#define MACH_TYPE_MDIRAC3 1058
+#define MACH_TYPE_MRHFBP2 1059
+#define MACH_TYPE_AT91RM9200RB 1060
+#define MACH_TYPE_ANI_APM 1061
+#define MACH_TYPE_ELLA1 1062
+#define MACH_TYPE_INHAND_PXA27X 1063
+#define MACH_TYPE_INHAND_PXA25X 1064
+#define MACH_TYPE_EMPOS_XM 1065
+#define MACH_TYPE_EMPOS 1066
+#define MACH_TYPE_EMPOS_TINY 1067
+#define MACH_TYPE_EMPOS_SM 1068
+#define MACH_TYPE_EGRET 1069
+#define MACH_TYPE_OSTRICH 1070
+#define MACH_TYPE_N50 1071
#define MACH_TYPE_ECBAT91 1072
+#define MACH_TYPE_STAREAST 1073
+#define MACH_TYPE_DSPG_DW 1074
#define MACH_TYPE_ONEARM 1075
+#define MACH_TYPE_MRG110_6 1076
+#define MACH_TYPE_WRT300NV2 1077
+#define MACH_TYPE_XM_BULVERDE 1078
+#define MACH_TYPE_MSM6100 1079
+#define MACH_TYPE_ETI_B1 1080
+#define MACH_TYPE_ZILOG_ZA9L 1081
+#define MACH_TYPE_BIT2440 1082
+#define MACH_TYPE_NBI 1083
#define MACH_TYPE_SMDK2443 1084
+#define MACH_TYPE_VDAVINCI 1085
+#define MACH_TYPE_ATC6 1086
+#define MACH_TYPE_MULTMDW 1087
+#define MACH_TYPE_MBA2440 1088
+#define MACH_TYPE_ECSD 1089
+#define MACH_TYPE_PALMZ31 1090
#define MACH_TYPE_FSG 1091
+#define MACH_TYPE_RAZOR101 1092
+#define MACH_TYPE_OPERA_TDM 1093
+#define MACH_TYPE_COMCERTO 1094
+#define MACH_TYPE_TB0319 1095
+#define MACH_TYPE_KWS8000 1096
+#define MACH_TYPE_B2 1097
+#define MACH_TYPE_LCL54 1098
#define MACH_TYPE_AT91SAM9260EK 1099
#define MACH_TYPE_GLANTANK 1100
#define MACH_TYPE_N2100 1101
+#define MACH_TYPE_N4100 1102
+#define MACH_TYPE_VERTICAL_RSC4 1103
+#define MACH_TYPE_SG8100 1104
#define MACH_TYPE_IM42XX 1105
+#define MACH_TYPE_FTXX 1106
+#define MACH_TYPE_LWFUSION 1107
#define MACH_TYPE_QT2410 1108
#define MACH_TYPE_KIXRP435 1109
+#define MACH_TYPE_CCW9C 1110
+#define MACH_TYPE_DABHS 1111
+#define MACH_TYPE_GZMX 1112
+#define MACH_TYPE_IPNW100AP 1113
#define MACH_TYPE_CC9P9360DEV 1114
+#define MACH_TYPE_CC9P9750DEV 1115
+#define MACH_TYPE_CC9P9360VAL 1116
+#define MACH_TYPE_CC9P9750VAL 1117
+#define MACH_TYPE_NX70V 1118
+#define MACH_TYPE_AT91RM9200DF 1119
+#define MACH_TYPE_SE_PILOT2 1120
+#define MACH_TYPE_MTCN_T800 1121
+#define MACH_TYPE_VCMX212 1122
+#define MACH_TYPE_LYNX 1123
+#define MACH_TYPE_AT91SAM9260ID 1124
+#define MACH_TYPE_HW86052 1125
+#define MACH_TYPE_PILZ_PMI3 1126
#define MACH_TYPE_EDB9302A 1127
#define MACH_TYPE_EDB9307A 1128
+#define MACH_TYPE_CT_DFS 1129
+#define MACH_TYPE_PILZ_PMI4 1130
+#define MACH_TYPE_XCEEDNP_IXP 1131
+#define MACH_TYPE_SMDK2442B 1132
+#define MACH_TYPE_XNODE 1133
+#define MACH_TYPE_AIDX270 1134
+#define MACH_TYPE_REMA 1135
+#define MACH_TYPE_BPS1000 1136
+#define MACH_TYPE_HW90350 1137
#define MACH_TYPE_OMAP_3430SDP 1138
+#define MACH_TYPE_BLUETOUCH 1139
#define MACH_TYPE_VSTMS 1140
+#define MACH_TYPE_XSBASE270 1141
+#define MACH_TYPE_AT91SAM9260EK_CN 1142
+#define MACH_TYPE_ADSTURBOXB 1143
+#define MACH_TYPE_OTI4110 1144
+#define MACH_TYPE_HME_PXA 1145
+#define MACH_TYPE_DEISTERDCA 1146
+#define MACH_TYPE_CES_SSEM2 1147
+#define MACH_TYPE_CES_MTR 1148
+#define MACH_TYPE_TDS_AVNG_SBC 1149
+#define MACH_TYPE_EVEREST 1150
+#define MACH_TYPE_PNX4010 1151
+#define MACH_TYPE_OXNAS 1152
+#define MACH_TYPE_FIORI 1153
+#define MACH_TYPE_ML1200 1154
+#define MACH_TYPE_PECOS 1155
+#define MACH_TYPE_NB2XXX 1156
+#define MACH_TYPE_HW6900 1157
+#define MACH_TYPE_CDCS_QUOLL 1158
+#define MACH_TYPE_QUICKSILVER 1159
+#define MACH_TYPE_UPLAT926 1160
+#define MACH_TYPE_DEP2410_THOMAS 1161
+#define MACH_TYPE_DTK2410 1162
+#define MACH_TYPE_CHILI 1163
+#define MACH_TYPE_DEMETER 1164
+#define MACH_TYPE_DIONYSUS 1165
+#define MACH_TYPE_AS352X 1166
+#define MACH_TYPE_SERVICE 1167
+#define MACH_TYPE_CS_E9301 1168
#define MACH_TYPE_MICRO9M 1169
+#define MACH_TYPE_IA_MOSPCK 1170
+#define MACH_TYPE_QL201B 1171
+#define MACH_TYPE_BBM 1174
+#define MACH_TYPE_EXXX 1175
+#define MACH_TYPE_WMA11B 1176
+#define MACH_TYPE_PELCO_ATLAS 1177
+#define MACH_TYPE_G500 1178
#define MACH_TYPE_BUG 1179
+#define MACH_TYPE_MX33ADS 1180
+#define MACH_TYPE_CHUB 1181
+#define MACH_TYPE_NEO1973_GTA01 1182
+#define MACH_TYPE_W90N740 1183
+#define MACH_TYPE_MEDALLION_SA2410 1184
+#define MACH_TYPE_IA_CPU_9200_2 1185
+#define MACH_TYPE_DIMMRM9200 1186
+#define MACH_TYPE_PM9261 1187
+#define MACH_TYPE_ML7304 1189
+#define MACH_TYPE_UCP250 1190
+#define MACH_TYPE_INTBOARD 1191
+#define MACH_TYPE_GULFSTREAM 1192
+#define MACH_TYPE_LABQUEST 1193
+#define MACH_TYPE_VCMX313 1194
+#define MACH_TYPE_URG200 1195
+#define MACH_TYPE_CPUX255LCDNET 1196
+#define MACH_TYPE_NETDCU9 1197
+#define MACH_TYPE_NETDCU10 1198
+#define MACH_TYPE_DSPG_DGA 1199
+#define MACH_TYPE_DSPG_DVW 1200
+#define MACH_TYPE_SOLOS 1201
#define MACH_TYPE_AT91SAM9263EK 1202
+#define MACH_TYPE_OSSTBOX 1203
+#define MACH_TYPE_KBAT9261 1204
+#define MACH_TYPE_CT1100 1205
+#define MACH_TYPE_AKCPPXA 1206
+#define MACH_TYPE_OCHAYA1020 1207
+#define MACH_TYPE_HITRACK 1208
+#define MACH_TYPE_SYME1 1209
+#define MACH_TYPE_SYHL1 1210
+#define MACH_TYPE_EMPCA400 1211
#define MACH_TYPE_EM7210 1212
+#define MACH_TYPE_HTCHERMES 1213
+#define MACH_TYPE_ETI_C1 1214
+#define MACH_TYPE_AC100 1216
+#define MACH_TYPE_SNEETCH 1217
+#define MACH_TYPE_STUDENTMATE 1218
+#define MACH_TYPE_ZIR2410 1219
+#define MACH_TYPE_ZIR2413 1220
+#define MACH_TYPE_DLONIP3 1221
+#define MACH_TYPE_INSTREAM 1222
+#define MACH_TYPE_AMBARELLA 1223
+#define MACH_TYPE_NEVIS 1224
+#define MACH_TYPE_HTC_TRINITY 1225
+#define MACH_TYPE_QL202B 1226
#define MACH_TYPE_VPAC270 1227
+#define MACH_TYPE_RD129 1228
+#define MACH_TYPE_HTCWIZARD 1229
#define MACH_TYPE_TREO680 1230
+#define MACH_TYPE_TECON_TMEZON 1231
#define MACH_TYPE_ZYLONITE 1233
+#define MACH_TYPE_GENE1270 1234
+#define MACH_TYPE_ZIR2412 1235
#define MACH_TYPE_MX31LITE 1236
+#define MACH_TYPE_T700WX 1237
+#define MACH_TYPE_VF100 1238
+#define MACH_TYPE_NSB2 1239
+#define MACH_TYPE_NXHMI_BB 1240
+#define MACH_TYPE_NXHMI_RE 1241
+#define MACH_TYPE_N4100PRO 1242
+#define MACH_TYPE_SAM9260 1243
+#define MACH_TYPE_OMAP_TREO600 1244
+#define MACH_TYPE_INDY2410 1245
+#define MACH_TYPE_NELT_A 1246
+#define MACH_TYPE_N311 1248
+#define MACH_TYPE_AT91SAM9260VGK 1249
+#define MACH_TYPE_AT91LEPPE 1250
+#define MACH_TYPE_AT91LEPCCN 1251
+#define MACH_TYPE_APC7100 1252
+#define MACH_TYPE_STARGAZER 1253
+#define MACH_TYPE_SONATA 1254
+#define MACH_TYPE_SCHMOOGIE 1255
+#define MACH_TYPE_AZTOOL 1256
#define MACH_TYPE_MIOA701 1257
+#define MACH_TYPE_SXNI9260 1258
+#define MACH_TYPE_MXC27520EVB 1259
#define MACH_TYPE_ARMADILLO5X0 1260
+#define MACH_TYPE_MB9260 1261
+#define MACH_TYPE_MB9263 1262
+#define MACH_TYPE_IPAC9302 1263
#define MACH_TYPE_CC9P9360JS 1264
+#define MACH_TYPE_GALLIUM 1265
+#define MACH_TYPE_MSC2410 1266
+#define MACH_TYPE_GHI270 1267
+#define MACH_TYPE_DAVINCI_LEONARDO 1268
+#define MACH_TYPE_OIAB 1269
#define MACH_TYPE_SMDK6400 1270
#define MACH_TYPE_NOKIA_N800 1271
+#define MACH_TYPE_GREENPHONE 1272
+#define MACH_TYPE_COMPEXWP18 1273
+#define MACH_TYPE_XMATE 1274
+#define MACH_TYPE_ENERGIZER 1275
+#define MACH_TYPE_IME1 1276
+#define MACH_TYPE_SWEDATMS 1277
+#define MACH_TYPE_NTNP435C 1278
+#define MACH_TYPE_SPECTRO2 1279
+#define MACH_TYPE_H6039 1280
#define MACH_TYPE_EP80219 1281
+#define MACH_TYPE_SAMOA_II 1282
+#define MACH_TYPE_CWMXL 1283
+#define MACH_TYPE_AS9200 1284
+#define MACH_TYPE_SFX1149 1285
+#define MACH_TYPE_NAVI010 1286
+#define MACH_TYPE_MULTMDP 1287
+#define MACH_TYPE_SCB9520 1288
+#define MACH_TYPE_HTCATHENA 1289
+#define MACH_TYPE_XP179 1290
+#define MACH_TYPE_H4300 1291
#define MACH_TYPE_GORAMO_MLR 1292
+#define MACH_TYPE_MXC30020EVB 1293
+#define MACH_TYPE_ADSBITSYG5 1294
+#define MACH_TYPE_ADSPORTALPLUS 1295
+#define MACH_TYPE_MMSP2PLUS 1296
#define MACH_TYPE_EM_X270 1297
+#define MACH_TYPE_TPP302 1298
+#define MACH_TYPE_TPM104 1299
+#define MACH_TYPE_TPM102 1300
+#define MACH_TYPE_TPM109 1301
+#define MACH_TYPE_FBXO1 1302
+#define MACH_TYPE_HXD8 1303
#define MACH_TYPE_NEO1973_GTA02 1304
+#define MACH_TYPE_EMTEST 1305
+#define MACH_TYPE_AD6900 1306
+#define MACH_TYPE_EUROPA 1307
+#define MACH_TYPE_METROCONNECT 1308
+#define MACH_TYPE_EZ_S2410 1309
+#define MACH_TYPE_EZ_S2440 1310
+#define MACH_TYPE_EZ_EP9312 1311
+#define MACH_TYPE_EZ_EP9315 1312
+#define MACH_TYPE_EZ_X7 1313
+#define MACH_TYPE_GODOTDB 1314
+#define MACH_TYPE_MISTRAL 1315
+#define MACH_TYPE_MSM 1316
+#define MACH_TYPE_CT5910 1317
+#define MACH_TYPE_CT5912 1318
+#define MACH_TYPE_HYNET_INE 1319
+#define MACH_TYPE_HYNET_APP 1320
+#define MACH_TYPE_MSM7200 1321
+#define MACH_TYPE_MSM7600 1322
+#define MACH_TYPE_CEB255 1323
+#define MACH_TYPE_CIEL 1324
+#define MACH_TYPE_SLM5650 1325
#define MACH_TYPE_AT91SAM9RLEK 1326
+#define MACH_TYPE_COMTECH_ROUTER 1327
+#define MACH_TYPE_SBC2410X 1328
+#define MACH_TYPE_AT4X0BD 1329
+#define MACH_TYPE_CBIFR 1330
+#define MACH_TYPE_ARCOM_QUANTUM 1331
+#define MACH_TYPE_MATRIX520 1332
+#define MACH_TYPE_MATRIX510 1333
+#define MACH_TYPE_MATRIX500 1334
+#define MACH_TYPE_M501 1335
+#define MACH_TYPE_AAEON1270 1336
+#define MACH_TYPE_MATRIX500EV 1337
+#define MACH_TYPE_PAC500 1338
+#define MACH_TYPE_PNX8181 1339
#define MACH_TYPE_COLIBRI320 1340
+#define MACH_TYPE_AZTOOLBB 1341
+#define MACH_TYPE_AZTOOLG2 1342
+#define MACH_TYPE_DVLHOST 1343
+#define MACH_TYPE_ZIR9200 1344
+#define MACH_TYPE_ZIR9260 1345
+#define MACH_TYPE_COCOPAH 1346
+#define MACH_TYPE_NDS 1347
+#define MACH_TYPE_ROSENCRANTZ 1348
+#define MACH_TYPE_FTTX_ODSC 1349
+#define MACH_TYPE_CLASSE_R6904 1350
#define MACH_TYPE_CAM60 1351
+#define MACH_TYPE_MXC30031ADS 1352
+#define MACH_TYPE_DATACALL 1353
#define MACH_TYPE_AT91EB01 1354
+#define MACH_TYPE_RTY 1355
+#define MACH_TYPE_DWL2100 1356
+#define MACH_TYPE_VINSI 1357
#define MACH_TYPE_DB88F5281 1358
#define MACH_TYPE_CSB726 1359
+#define MACH_TYPE_TIK27 1360
+#define MACH_TYPE_MX_UC7420 1361
+#define MACH_TYPE_RIRM3 1362
+#define MACH_TYPE_PELCO_ODYSSEY 1363
+#define MACH_TYPE_ADX_ABOX 1365
+#define MACH_TYPE_ADX_TPID 1366
+#define MACH_TYPE_MINICHECK 1367
+#define MACH_TYPE_IDAM 1368
+#define MACH_TYPE_MARIO_MX 1369
+#define MACH_TYPE_VI1888 1370
+#define MACH_TYPE_ZR4230 1371
+#define MACH_TYPE_T1_IX_BLUE 1372
+#define MACH_TYPE_SYHQ2 1373
+#define MACH_TYPE_COMPUTIME_R3 1374
+#define MACH_TYPE_ORATIS 1375
+#define MACH_TYPE_MIKKO 1376
+#define MACH_TYPE_HOLON 1377
+#define MACH_TYPE_OLIP8 1378
+#define MACH_TYPE_GHI270HG 1379
#define MACH_TYPE_DAVINCI_DM6467_EVM 1380
#define MACH_TYPE_DAVINCI_DM355_EVM 1381
+#define MACH_TYPE_BLACKRIVER 1383
+#define MACH_TYPE_SANDGATEWP 1384
+#define MACH_TYPE_CDOTBWSG 1385
+#define MACH_TYPE_QUARK963 1386
+#define MACH_TYPE_CSB735 1387
#define MACH_TYPE_LITTLETON 1388
+#define MACH_TYPE_MIO_P550 1389
+#define MACH_TYPE_MOTION2440 1390
+#define MACH_TYPE_IMM500 1391
+#define MACH_TYPE_HOMEMATIC 1392
+#define MACH_TYPE_ERMINE 1393
+#define MACH_TYPE_KB9202B 1394
+#define MACH_TYPE_HS1XX 1395
+#define MACH_TYPE_STUDENTMATE2440 1396
+#define MACH_TYPE_ARVOO_L1_Z1 1397
+#define MACH_TYPE_DEP2410K 1398
+#define MACH_TYPE_XXSVIDEO 1399
#define MACH_TYPE_IM4004 1400
+#define MACH_TYPE_OCHAYA1050 1401
+#define MACH_TYPE_LEP9261 1402
+#define MACH_TYPE_SVENMEB 1403
+#define MACH_TYPE_FORTUNET2NE 1404
+#define MACH_TYPE_NXHX 1406
#define MACH_TYPE_REALVIEW_PB11MP 1407
+#define MACH_TYPE_IDS500 1408
+#define MACH_TYPE_ORS_N725 1409
+#define MACH_TYPE_HSDARM 1410
+#define MACH_TYPE_SHA_PON003 1411
+#define MACH_TYPE_SHA_PON004 1412
+#define MACH_TYPE_SHA_PON007 1413
+#define MACH_TYPE_SHA_PON011 1414
+#define MACH_TYPE_H6042 1415
+#define MACH_TYPE_H6043 1416
+#define MACH_TYPE_LOOXC550 1417
+#define MACH_TYPE_CNTY_TITAN 1418
+#define MACH_TYPE_APP3XX 1419
+#define MACH_TYPE_SIDEOATSGRAMA 1420
+#define MACH_TYPE_TREO700P 1421
+#define MACH_TYPE_TREO700W 1422
+#define MACH_TYPE_TREO750 1423
+#define MACH_TYPE_TREO755P 1424
+#define MACH_TYPE_EZREGANUT9200 1425
+#define MACH_TYPE_SARGE 1426
+#define MACH_TYPE_A696 1427
+#define MACH_TYPE_TURTLE 1428
#define MACH_TYPE_MX27_3DS 1430
+#define MACH_TYPE_BISHOP 1431
+#define MACH_TYPE_PXX 1432
+#define MACH_TYPE_REDWOOD 1433
+#define MACH_TYPE_OMAP_2430DLP 1436
+#define MACH_TYPE_OMAP_2430OSK 1437
+#define MACH_TYPE_SARDINE 1438
#define MACH_TYPE_HALIBUT 1439
#define MACH_TYPE_TROUT 1440
+#define MACH_TYPE_GOLDFISH 1441
+#define MACH_TYPE_GESBC2440 1442
+#define MACH_TYPE_NOMAD 1443
+#define MACH_TYPE_ROSALIND 1444
+#define MACH_TYPE_CC9P9215 1445
+#define MACH_TYPE_CC9P9210 1446
+#define MACH_TYPE_CC9P9215JS 1447
+#define MACH_TYPE_CC9P9210JS 1448
+#define MACH_TYPE_NASFFE 1449
+#define MACH_TYPE_TN2X0BD 1450
+#define MACH_TYPE_GWMPXA 1451
+#define MACH_TYPE_EXYPLUS 1452
+#define MACH_TYPE_JADOO21 1453
+#define MACH_TYPE_LOOXN560 1454
+#define MACH_TYPE_BONSAI 1455
+#define MACH_TYPE_ADSMILGATO 1456
+#define MACH_TYPE_GBA 1457
+#define MACH_TYPE_H6044 1458
+#define MACH_TYPE_APP 1459
#define MACH_TYPE_TCT_HAMMER 1460
#define MACH_TYPE_HERALD 1461
+#define MACH_TYPE_ARTEMIS 1462
+#define MACH_TYPE_HTCTITAN 1463
+#define MACH_TYPE_QRANIUM 1464
+#define MACH_TYPE_ADX_WSC2 1465
+#define MACH_TYPE_ADX_MEDCOM 1466
+#define MACH_TYPE_BBOARD 1467
+#define MACH_TYPE_CAMBRIA 1468
+#define MACH_TYPE_MT7XXX 1469
+#define MACH_TYPE_MATRIX512 1470
+#define MACH_TYPE_MATRIX522 1471
+#define MACH_TYPE_IPAC5010 1472
+#define MACH_TYPE_SAKURA 1473
+#define MACH_TYPE_GROCX 1474
+#define MACH_TYPE_PM9263 1475
#define MACH_TYPE_SIM_ONE 1476
+#define MACH_TYPE_ACQ132 1477
+#define MACH_TYPE_DATR 1478
+#define MACH_TYPE_ACTUX1 1479
+#define MACH_TYPE_ACTUX2 1480
+#define MACH_TYPE_ACTUX3 1481
+#define MACH_TYPE_FLEXIT 1482
+#define MACH_TYPE_BH2X0BD 1483
+#define MACH_TYPE_ATB2002 1484
+#define MACH_TYPE_XENON 1485
+#define MACH_TYPE_FM607 1486
+#define MACH_TYPE_MATRIX514 1487
+#define MACH_TYPE_MATRIX524 1488
+#define MACH_TYPE_INPOD 1489
#define MACH_TYPE_JIVE 1490
+#define MACH_TYPE_TLL_MX21 1491
+#define MACH_TYPE_SBC2800 1492
+#define MACH_TYPE_CC7UCAMRY 1493
+#define MACH_TYPE_UBISYS_P9_SC15 1494
+#define MACH_TYPE_UBISYS_P9_SSC2D10 1495
+#define MACH_TYPE_UBISYS_P9_RCU3 1496
+#define MACH_TYPE_AML_M8000 1497
+#define MACH_TYPE_SNAPPER_270 1498
+#define MACH_TYPE_OMAP_BBX 1499
+#define MACH_TYPE_UCN2410 1500
#define MACH_TYPE_SAM9_L9260 1501
+#define MACH_TYPE_ETI_C2 1502
+#define MACH_TYPE_AVALANCHE 1503
#define MACH_TYPE_REALVIEW_PB1176 1504
+#define MACH_TYPE_DP1500 1505
+#define MACH_TYPE_APPLE_IPHONE 1506
#define MACH_TYPE_YL9200 1507
#define MACH_TYPE_RD88F5182 1508
#define MACH_TYPE_KUROBOX_PRO 1509
+#define MACH_TYPE_SE_POET 1510
#define MACH_TYPE_MX31_3DS 1511
+#define MACH_TYPE_R270 1512
+#define MACH_TYPE_ARMOUR21 1513
+#define MACH_TYPE_DT2 1514
+#define MACH_TYPE_VT4 1515
+#define MACH_TYPE_TYCO320 1516
+#define MACH_TYPE_ADMA 1517
+#define MACH_TYPE_WP188 1518
+#define MACH_TYPE_CORSICA 1519
+#define MACH_TYPE_BIGEYE 1520
+#define MACH_TYPE_TLL5000 1522
+#define MACH_TYPE_BEBOT 1523
#define MACH_TYPE_QONG 1524
+#define MACH_TYPE_TCOMPACT 1525
+#define MACH_TYPE_PUMA5 1526
+#define MACH_TYPE_ELARA 1527
+#define MACH_TYPE_ELLINGTON 1528
+#define MACH_TYPE_XDA_ATOM 1529
+#define MACH_TYPE_ENERGIZER2 1530
+#define MACH_TYPE_ODIN 1531
+#define MACH_TYPE_ACTUX4 1532
+#define MACH_TYPE_ESL_OMAP 1533
#define MACH_TYPE_OMAP2EVM 1534
#define MACH_TYPE_OMAP3EVM 1535
+#define MACH_TYPE_ADX_PCU57 1536
+#define MACH_TYPE_MONACO 1537
+#define MACH_TYPE_LEVANTE 1538
+#define MACH_TYPE_TMXIPX425 1539
+#define MACH_TYPE_LEEP 1540
+#define MACH_TYPE_RAAD 1541
#define MACH_TYPE_DNS323 1542
+#define MACH_TYPE_AP1000 1543
+#define MACH_TYPE_A9SAM6432 1544
+#define MACH_TYPE_SHINY 1545
#define MACH_TYPE_OMAP3_BEAGLE 1546
+#define MACH_TYPE_CSR_BDB2 1547
#define MACH_TYPE_NOKIA_N810 1548
+#define MACH_TYPE_C270 1549
+#define MACH_TYPE_SENTRY 1550
#define MACH_TYPE_PCM038 1551
+#define MACH_TYPE_ANC300 1552
+#define MACH_TYPE_HTCKAISER 1553
+#define MACH_TYPE_SBAT100 1554
+#define MACH_TYPE_MODUNORM 1555
+#define MACH_TYPE_PELOS_TWARM 1556
+#define MACH_TYPE_FLANK 1557
+#define MACH_TYPE_SIRLOIN 1558
+#define MACH_TYPE_BRISKET 1559
+#define MACH_TYPE_CHUCK 1560
+#define MACH_TYPE_OTTER 1561
+#define MACH_TYPE_DAVINCI_LDK 1562
+#define MACH_TYPE_PHREEDOM 1563
#define MACH_TYPE_SG310 1564
#define MACH_TYPE_TS209 1565
#define MACH_TYPE_AT91CAP9ADK 1566
+#define MACH_TYPE_TION9315 1567
+#define MACH_TYPE_MAST 1568
+#define MACH_TYPE_PFW 1569
+#define MACH_TYPE_YL_P2440 1570
+#define MACH_TYPE_ZSBC32 1571
+#define MACH_TYPE_OMAP_PACE2 1572
+#define MACH_TYPE_IMX_PACE2 1573
#define MACH_TYPE_MX31MOBOARD 1574
+#define MACH_TYPE_MX37_3DS 1575
+#define MACH_TYPE_RCC 1576
+#define MACH_TYPE_ARM9 1577
#define MACH_TYPE_VISION_EP9307 1578
+#define MACH_TYPE_SCLY1000 1579
+#define MACH_TYPE_FONTEL_EP 1580
+#define MACH_TYPE_VOICEBLUE3G 1581
+#define MACH_TYPE_TT9200 1582
+#define MACH_TYPE_DIGI2410 1583
#define MACH_TYPE_TERASTATION_PRO2 1584
#define MACH_TYPE_LINKSTATION_PRO 1585
+#define MACH_TYPE_MOTOROLA_A780 1587
+#define MACH_TYPE_MOTOROLA_E6 1588
+#define MACH_TYPE_MOTOROLA_E2 1589
+#define MACH_TYPE_MOTOROLA_E680 1590
+#define MACH_TYPE_UR2410 1591
+#define MACH_TYPE_TAS9261 1592
+#define MACH_TYPE_HERMES_HD 1593
+#define MACH_TYPE_PERSEO_HD 1594
+#define MACH_TYPE_STARGAZER2 1595
#define MACH_TYPE_E350 1596
+#define MACH_TYPE_WPCM450 1597
+#define MACH_TYPE_CARTESIO 1598
+#define MACH_TYPE_TOYBOX 1599
+#define MACH_TYPE_TX27 1600
#define MACH_TYPE_TS409 1601
+#define MACH_TYPE_P300 1602
+#define MACH_TYPE_XDACOMET 1603
+#define MACH_TYPE_DEXFLEX2 1604
+#define MACH_TYPE_OW 1605
+#define MACH_TYPE_ARMEBS3 1606
+#define MACH_TYPE_U3 1607
+#define MACH_TYPE_SMDK2450 1608
#define MACH_TYPE_RSI_EWS 1609
+#define MACH_TYPE_TNB 1610
+#define MACH_TYPE_TOEPATH 1611
+#define MACH_TYPE_KB9263 1612
+#define MACH_TYPE_MT7108 1613
+#define MACH_TYPE_SMTR2440 1614
+#define MACH_TYPE_MANAO 1615
#define MACH_TYPE_CM_X300 1616
+#define MACH_TYPE_GULFSTREAM_KP 1617
+#define MACH_TYPE_LANREADYFN522 1618
+#define MACH_TYPE_ARMA37 1619
+#define MACH_TYPE_MENDEL 1620
+#define MACH_TYPE_PELCO_ILIAD 1621
+#define MACH_TYPE_UNIT2P 1622
+#define MACH_TYPE_INC20OTTER 1623
#define MACH_TYPE_AT91SAM9G20EK 1624
+#define MACH_TYPE_STORCENTER 1625
#define MACH_TYPE_SMDK6410 1626
#define MACH_TYPE_U300 1627
+#define MACH_TYPE_U500 1628
+#define MACH_TYPE_DS9260 1629
+#define MACH_TYPE_RIVERROCK 1630
+#define MACH_TYPE_SCIBATH 1631
+#define MACH_TYPE_AT91SAM7SE512EK 1632
#define MACH_TYPE_WRT350N_V2 1633
+#define MACH_TYPE_MULTIMEDIA 1634
+#define MACH_TYPE_MARVIN 1635
+#define MACH_TYPE_X500 1636
+#define MACH_TYPE_AWLUG4LCU 1637
+#define MACH_TYPE_PALERMOC 1638
#define MACH_TYPE_OMAP_LDP 1639
+#define MACH_TYPE_IP500 1640
+#define MACH_TYPE_ASE2 1642
+#define MACH_TYPE_MX35EVB 1643
+#define MACH_TYPE_AML_M8050 1644
#define MACH_TYPE_MX35_3DS 1645
+#define MACH_TYPE_MARS 1646
#define MACH_TYPE_NEUROS_OSD2 1647
+#define MACH_TYPE_BADGER 1648
#define MACH_TYPE_TRIZEPS4WL 1649
+#define MACH_TYPE_TRIZEPS5 1650
+#define MACH_TYPE_MARLIN 1651
#define MACH_TYPE_TS78XX 1652
+#define MACH_TYPE_HPIPAQ214 1653
+#define MACH_TYPE_AT572D940DCM 1654
+#define MACH_TYPE_NE1BOARD 1655
+#define MACH_TYPE_ZANTE 1656
#define MACH_TYPE_SFFSDR 1657
+#define MACH_TYPE_TW2662 1658
+#define MACH_TYPE_VF10XX 1659
+#define MACH_TYPE_ZORAN43XX 1660
+#define MACH_TYPE_SONIX926 1661
+#define MACH_TYPE_CELESTIALSEMI 1662
+#define MACH_TYPE_CC9M2443JS 1663
+#define MACH_TYPE_TW5334 1664
+#define MACH_TYPE_HTCARTEMIS 1665
+#define MACH_TYPE_NAL_HLITE 1666
+#define MACH_TYPE_HTCVOGUE 1667
+#define MACH_TYPE_SMARTWEB 1668
+#define MACH_TYPE_MV86XX 1669
+#define MACH_TYPE_MV87XX 1670
+#define MACH_TYPE_SONGYOUNGHO 1671
+#define MACH_TYPE_YOUNGHOTEMA 1672
#define MACH_TYPE_PCM037 1673
+#define MACH_TYPE_MMVP 1674
+#define MACH_TYPE_MMAP 1675
+#define MACH_TYPE_PTID2410 1676
+#define MACH_TYPE_JAMES_926 1677
+#define MACH_TYPE_FM6000 1678
#define MACH_TYPE_DB88F6281_BP 1680
#define MACH_TYPE_RD88F6192_NAS 1681
#define MACH_TYPE_RD88F6281 1682
#define MACH_TYPE_DB78X00_BP 1683
#define MACH_TYPE_SMDK2416 1685
+#define MACH_TYPE_OCE_SPIDER_SI 1686
+#define MACH_TYPE_OCE_SPIDER_SK 1687
+#define MACH_TYPE_ROVERN6 1688
+#define MACH_TYPE_PELCO_EVOLUTION 1689
#define MACH_TYPE_WBD111 1690
+#define MACH_TYPE_ELARACPE 1691
+#define MACH_TYPE_MABV3 1692
#define MACH_TYPE_MV2120 1693
+#define MACH_TYPE_CSB737 1695
#define MACH_TYPE_MX51_3DS 1696
+#define MACH_TYPE_G900 1697
+#define MACH_TYPE_APF27 1698
+#define MACH_TYPE_GGUS2000 1699
+#define MACH_TYPE_OMAP_2430_MIMIC 1700
#define MACH_TYPE_IMX27LITE 1701
+#define MACH_TYPE_ALMEX 1702
+#define MACH_TYPE_CONTROL 1703
+#define MACH_TYPE_MBA2410 1704
+#define MACH_TYPE_VOLCANO 1705
+#define MACH_TYPE_ZENITH 1706
+#define MACH_TYPE_MUCHIP 1707
+#define MACH_TYPE_MAGELLAN 1708
#define MACH_TYPE_USB_A9260 1709
#define MACH_TYPE_USB_A9263 1710
#define MACH_TYPE_QIL_A9260 1711
+#define MACH_TYPE_CME9210 1712
+#define MACH_TYPE_HCZH4 1713
+#define MACH_TYPE_SPEARBASIC 1714
+#define MACH_TYPE_DEP2440 1715
+#define MACH_TYPE_HDL_GXR 1716
+#define MACH_TYPE_HDL_GT 1717
+#define MACH_TYPE_HDL_4G 1718
+#define MACH_TYPE_S3C6000 1719
+#define MACH_TYPE_MMSP2_MDK 1720
+#define MACH_TYPE_MPX220 1721
#define MACH_TYPE_KZM_ARM11_01 1722
+#define MACH_TYPE_HTC_POLARIS 1723
+#define MACH_TYPE_HTC_KAISER 1724
+#define MACH_TYPE_LG_KS20 1725
+#define MACH_TYPE_HHGPS 1726
#define MACH_TYPE_NOKIA_N810_WIMAX 1727
+#define MACH_TYPE_INSIGHT 1728
#define MACH_TYPE_SAPPHIRE 1729
+#define MACH_TYPE_CSB637XO 1730
+#define MACH_TYPE_EVISIONG 1731
#define MACH_TYPE_STMP37XX 1732
#define MACH_TYPE_STMP378X 1733
+#define MACH_TYPE_TNT 1734
+#define MACH_TYPE_TBXT 1735
+#define MACH_TYPE_PLAYMATE 1736
+#define MACH_TYPE_PNS10 1737
+#define MACH_TYPE_EZNAVI 1738
+#define MACH_TYPE_PS4000 1739
#define MACH_TYPE_EZX_A780 1740
#define MACH_TYPE_EZX_E680 1741
#define MACH_TYPE_EZX_A1200 1742
#define MACH_TYPE_EZX_E6 1743
#define MACH_TYPE_EZX_E2 1744
#define MACH_TYPE_EZX_A910 1745
+#define MACH_TYPE_CWMX31 1746
+#define MACH_TYPE_SL2312 1747
+#define MACH_TYPE_BLENNY 1748
+#define MACH_TYPE_DS107 1749
+#define MACH_TYPE_DSX07 1750
+#define MACH_TYPE_PICOCOM1 1751
+#define MACH_TYPE_LYNX_WOLVERINE 1752
+#define MACH_TYPE_UBISYS_P9_SC19 1753
+#define MACH_TYPE_KRATOS_LOW 1754
+#define MACH_TYPE_M700 1755
#define MACH_TYPE_EDMINI_V2 1756
#define MACH_TYPE_ZIPIT2 1757
+#define MACH_TYPE_HSLFEMTOCELL 1758
+#define MACH_TYPE_DAINTREE_AT91 1759
+#define MACH_TYPE_SG560USB 1760
#define MACH_TYPE_OMAP3_PANDORA 1761
+#define MACH_TYPE_USR8200 1762
+#define MACH_TYPE_S1S65K 1763
+#define MACH_TYPE_S2S65A 1764
+#define MACH_TYPE_ICORE 1765
#define MACH_TYPE_MSS2 1766
+#define MACH_TYPE_BELMONT 1767
+#define MACH_TYPE_ASUSP525 1768
#define MACH_TYPE_LB88RC8480 1769
+#define MACH_TYPE_HIPXA 1770
#define MACH_TYPE_MX25_3DS 1771
+#define MACH_TYPE_M800 1772
#define MACH_TYPE_OMAP3530_LV_SOM 1773
+#define MACH_TYPE_PRIMA_EVB 1774
+#define MACH_TYPE_MX31BT1 1775
+#define MACH_TYPE_ATLAS4_EVB 1776
+#define MACH_TYPE_MX31CICADA 1777
+#define MACH_TYPE_MI424WR 1778
+#define MACH_TYPE_AXS_ULTRAX 1779
+#define MACH_TYPE_AT572D940DEB 1780
#define MACH_TYPE_DAVINCI_DA830_EVM 1781
+#define MACH_TYPE_EP9302 1782
+#define MACH_TYPE_AT572D940HFEB 1783
+#define MACH_TYPE_CYBOOK3 1784
+#define MACH_TYPE_WDG002 1785
+#define MACH_TYPE_SG560ADSL 1786
+#define MACH_TYPE_NEXTIO_N2800_ICA 1787
#define MACH_TYPE_DOVE_DB 1788
+#define MACH_TYPE_VANDIHUD 1790
+#define MACH_TYPE_MAGX_E8 1791
+#define MACH_TYPE_MAGX_Z6 1792
+#define MACH_TYPE_MAGX_V8 1793
+#define MACH_TYPE_MAGX_U9 1794
+#define MACH_TYPE_TOUGHCF08 1795
+#define MACH_TYPE_ZW4400 1796
+#define MACH_TYPE_MARAT91 1797
#define MACH_TYPE_OVERO 1798
#define MACH_TYPE_AT2440EVB 1799
#define MACH_TYPE_NEOCORE926 1800
#define MACH_TYPE_WNR854T 1801
+#define MACH_TYPE_IMX27 1802
+#define MACH_TYPE_MOOSE_DB 1803
+#define MACH_TYPE_FAB4 1804
+#define MACH_TYPE_HTCDIAMOND 1805
+#define MACH_TYPE_FIONA 1806
+#define MACH_TYPE_MXC30030_X 1807
+#define MACH_TYPE_BMP1000 1808
+#define MACH_TYPE_LOGI9200 1809
+#define MACH_TYPE_TQMA31 1810
+#define MACH_TYPE_CCW9P9215JS 1811
#define MACH_TYPE_RD88F5181L_GE 1812
+#define MACH_TYPE_SIFMAIN 1813
+#define MACH_TYPE_SAM9_L9261 1814
+#define MACH_TYPE_CC9M2443 1815
+#define MACH_TYPE_XARIA300 1816
+#define MACH_TYPE_IT9200 1817
#define MACH_TYPE_RD88F5181L_FXO 1818
+#define MACH_TYPE_KRISS_SENSOR 1819
+#define MACH_TYPE_PILZ_PMI5 1820
+#define MACH_TYPE_JADE 1821
+#define MACH_TYPE_KS8695_SOFTPLC 1822
+#define MACH_TYPE_GPRISC3 1823
#define MACH_TYPE_STAMP9G20 1824
+#define MACH_TYPE_SMDK6430 1825
#define MACH_TYPE_SMDKC100 1826
#define MACH_TYPE_TAVOREVB 1827
#define MACH_TYPE_SAAR 1828
+#define MACH_TYPE_DEISTER_EYECAM 1829
#define MACH_TYPE_AT91SAM9M10G45EK 1830
+#define MACH_TYPE_LINKSTATION_PRODUO 1831
+#define MACH_TYPE_HIT_B0 1832
+#define MACH_TYPE_ADX_RMU 1833
+#define MACH_TYPE_XG_CPE_MAIN 1834
+#define MACH_TYPE_EDB9407A 1835
+#define MACH_TYPE_DTB9608 1836
+#define MACH_TYPE_EM104V1 1837
+#define MACH_TYPE_DEMO 1838
+#define MACH_TYPE_LOGI9260 1839
+#define MACH_TYPE_MX31_EXM32 1840
#define MACH_TYPE_USB_A9G20 1841
+#define MACH_TYPE_PICPROJE2008 1842
+#define MACH_TYPE_CS_E9315 1843
+#define MACH_TYPE_QIL_A9G20 1844
+#define MACH_TYPE_SHA_PON020 1845
+#define MACH_TYPE_NAD 1846
+#define MACH_TYPE_SBC35_A9260 1847
+#define MACH_TYPE_SBC35_A9G20 1848
+#define MACH_TYPE_DAVINCI_BEGINNING 1849
+#define MACH_TYPE_UWC 1850
#define MACH_TYPE_MXLADS 1851
+#define MACH_TYPE_HTCNIKE 1852
+#define MACH_TYPE_DEISTER_PXA270 1853
+#define MACH_TYPE_CME9210JS 1854
+#define MACH_TYPE_CC9P9360 1855
+#define MACH_TYPE_MOCHA 1856
+#define MACH_TYPE_WAPD170AG 1857
#define MACH_TYPE_LINKSTATION_MINI 1858
#define MACH_TYPE_AFEB9260 1859
+#define MACH_TYPE_W90X900 1860
+#define MACH_TYPE_W90X700 1861
+#define MACH_TYPE_KT300IP 1862
+#define MACH_TYPE_KT300IP_G20 1863
+#define MACH_TYPE_SRCM 1864
+#define MACH_TYPE_WLNX_9260 1865
+#define MACH_TYPE_OPENMOKO_GTA03 1866
+#define MACH_TYPE_OSPREY2 1867
+#define MACH_TYPE_KBIO9260 1868
+#define MACH_TYPE_GINZA 1869
+#define MACH_TYPE_A636N 1870
#define MACH_TYPE_IMX27IPCAM 1871
+#define MACH_TYPE_NEMOC 1872
+#define MACH_TYPE_GENEVA 1873
+#define MACH_TYPE_HTCPHAROS 1874
+#define MACH_TYPE_NEONC 1875
+#define MACH_TYPE_NAS7100 1876
+#define MACH_TYPE_TEUPHONE 1877
+#define MACH_TYPE_ANNAX_ETH2 1878
+#define MACH_TYPE_CSB733 1879
+#define MACH_TYPE_BK3 1880
+#define MACH_TYPE_OMAP_EM32 1881
+#define MACH_TYPE_ET9261CP 1882
+#define MACH_TYPE_JASPERC 1883
+#define MACH_TYPE_ISSI_ARM9 1884
+#define MACH_TYPE_UED 1885
+#define MACH_TYPE_ESIBLADE 1886
+#define MACH_TYPE_EYE02 1887
+#define MACH_TYPE_IMX27KBD 1888
+#define MACH_TYPE_KIXVP435 1890
+#define MACH_TYPE_KIXNP435 1891
+#define MACH_TYPE_AFRICA 1892
+#define MACH_TYPE_NH233 1893
#define MACH_TYPE_RD88F6183AP_GE 1894
+#define MACH_TYPE_BCM4760 1895
+#define MACH_TYPE_EDDY_V2 1896
#define MACH_TYPE_REALVIEW_PBA8 1897
+#define MACH_TYPE_HID_A7 1898
+#define MACH_TYPE_HERO 1899
+#define MACH_TYPE_OMAP_POSEIDON 1900
#define MACH_TYPE_REALVIEW_PBX 1901
#define MACH_TYPE_MICRO9S 1902
+#define MACH_TYPE_MAKO 1903
+#define MACH_TYPE_XDAFLAME 1904
+#define MACH_TYPE_PHIDGET_SBC2 1905
+#define MACH_TYPE_LIMESTONE 1906
+#define MACH_TYPE_IPROBE_C32 1907
#define MACH_TYPE_RUT100 1908
+#define MACH_TYPE_ASUSP535 1909
+#define MACH_TYPE_HTCRAPHAEL 1910
+#define MACH_TYPE_SYGDG1 1911
+#define MACH_TYPE_SYGDG2 1912
+#define MACH_TYPE_SEOUL 1913
+#define MACH_TYPE_SALERNO 1914
+#define MACH_TYPE_UCN_S3C64XX 1915
+#define MACH_TYPE_MSM7201A 1916
+#define MACH_TYPE_LPR1 1917
+#define MACH_TYPE_ARMADILLO500FX 1918
#define MACH_TYPE_G3EVM 1919
+#define MACH_TYPE_Z3_DM355 1920
#define MACH_TYPE_W90P910EVB 1921
+#define MACH_TYPE_W90P920EVB 1922
#define MACH_TYPE_W90P950EVB 1923
#define MACH_TYPE_W90N960EVB 1924
+#define MACH_TYPE_CAMHD 1925
+#define MACH_TYPE_MVC100 1926
+#define MACH_TYPE_ELECTRUM_200 1927
+#define MACH_TYPE_HTCJADE 1928
+#define MACH_TYPE_MEMPHIS 1929
+#define MACH_TYPE_IMX27SBC 1930
+#define MACH_TYPE_LEXTAR 1931
#define MACH_TYPE_MV88F6281GTW_GE 1932
#define MACH_TYPE_NCP 1933
+#define MACH_TYPE_Z32AN 1934
+#define MACH_TYPE_TMQ_CAPD 1935
+#define MACH_TYPE_OMAP3_WL 1936
+#define MACH_TYPE_CHUMBY 1937
+#define MACH_TYPE_ATSARM9 1938
#define MACH_TYPE_DAVINCI_DM365_EVM 1939
+#define MACH_TYPE_BAHAMAS 1940
+#define MACH_TYPE_DAS 1941
+#define MACH_TYPE_MINIDAS 1942
+#define MACH_TYPE_VK1000 1943
#define MACH_TYPE_CENTRO 1944
+#define MACH_TYPE_CTERA_2BAY 1945
+#define MACH_TYPE_EDGECONNECT 1946
+#define MACH_TYPE_ND27000 1947
+#define MACH_TYPE_GEMALTO_COBRA 1948
+#define MACH_TYPE_INGELABS_COMET 1949
+#define MACH_TYPE_POLLUX_WIZ 1950
+#define MACH_TYPE_BLACKSTONE 1951
+#define MACH_TYPE_TOPAZ 1952
+#define MACH_TYPE_AIXLE 1953
+#define MACH_TYPE_MW998 1954
#define MACH_TYPE_NOKIA_RX51 1955
+#define MACH_TYPE_VSC5605EV 1956
+#define MACH_TYPE_NT98700DK 1957
+#define MACH_TYPE_ICONTACT 1958
+#define MACH_TYPE_SWARCO_FRCPU 1959
+#define MACH_TYPE_SWARCO_SCPU 1960
+#define MACH_TYPE_BBOX_P16 1961
+#define MACH_TYPE_BSTD 1962
+#define MACH_TYPE_SBC2440II 1963
+#define MACH_TYPE_PCM034 1964
+#define MACH_TYPE_NESO 1965
+#define MACH_TYPE_WLNX_9G20 1966
#define MACH_TYPE_OMAP_ZOOM2 1967
+#define MACH_TYPE_TOTEMNOVA 1968
+#define MACH_TYPE_C5000 1969
+#define MACH_TYPE_UNIPO_AT91SAM9263 1970
+#define MACH_TYPE_ETHERNUT5 1971
+#define MACH_TYPE_ARM11 1972
#define MACH_TYPE_CPUAT9260 1973
+#define MACH_TYPE_CPUPXA255 1974
#define MACH_TYPE_EUKREA_CPUIMX27 1975
+#define MACH_TYPE_CHEFLUX 1976
+#define MACH_TYPE_EB_CPUX9K2 1977
+#define MACH_TYPE_OPCOTEC 1978
+#define MACH_TYPE_YT 1979
+#define MACH_TYPE_MOTOQ 1980
+#define MACH_TYPE_BSB1 1981
#define MACH_TYPE_ACS5K 1982
+#define MACH_TYPE_MILAN 1983
+#define MACH_TYPE_QUARTZV2 1984
+#define MACH_TYPE_RSVP 1985
+#define MACH_TYPE_RMP200 1986
#define MACH_TYPE_SNAPPER_9260 1987
#define MACH_TYPE_DSM320 1988
+#define MACH_TYPE_ADSGCM 1989
+#define MACH_TYPE_ASE2_400 1990
+#define MACH_TYPE_PIZZA 1991
+#define MACH_TYPE_SPOT_NGPL 1992
+#define MACH_TYPE_ARMATA 1993
#define MACH_TYPE_EXEDA 1994
+#define MACH_TYPE_MX31SF005 1995
+#define MACH_TYPE_F5D8231_4_V2 1996
+#define MACH_TYPE_Q2440 1997
+#define MACH_TYPE_QQ2440 1998
#define MACH_TYPE_MINI2440 1999
#define MACH_TYPE_COLIBRI300 2000
+#define MACH_TYPE_JADES 2001
+#define MACH_TYPE_SPARK 2002
+#define MACH_TYPE_BENZINA 2003
+#define MACH_TYPE_BLAZE 2004
#define MACH_TYPE_LINKSTATION_LS_HGL 2005
+#define MACH_TYPE_HTCKOVSKY 2006
+#define MACH_TYPE_SONY_PRS505 2007
+#define MACH_TYPE_HANLIN_V3 2008
+#define MACH_TYPE_SAPPHIRA 2009
+#define MACH_TYPE_DACK_SDA_01 2010
+#define MACH_TYPE_ARMBOX 2011
+#define MACH_TYPE_HARRIS_RVP 2012
+#define MACH_TYPE_RIBALDO 2013
+#define MACH_TYPE_AGORA 2014
+#define MACH_TYPE_OMAP3_MINI 2015
+#define MACH_TYPE_A9SAM6432_B 2016
+#define MACH_TYPE_USG2410 2017
+#define MACH_TYPE_PC72052_I10_REVB 2018
+#define MACH_TYPE_MX35_EXM32 2019
+#define MACH_TYPE_TOPAS910 2020
+#define MACH_TYPE_HYENA 2021
+#define MACH_TYPE_POSPAX 2022
+#define MACH_TYPE_HDL_GX 2023
+#define MACH_TYPE_CTERA_4BAY 2024
+#define MACH_TYPE_CTERA_PLUG_C 2025
+#define MACH_TYPE_CRWEA_PLUG_I 2026
+#define MACH_TYPE_EGAUGE2 2027
+#define MACH_TYPE_DIDJ 2028
+#define MACH_TYPE_MEISTER 2029
+#define MACH_TYPE_HTCBLACKSTONE 2030
#define MACH_TYPE_CPUAT9G20 2031
#define MACH_TYPE_SMDK6440 2032
+#define MACH_TYPE_OMAP_35XX_MVP 2033
+#define MACH_TYPE_CTERA_PLUG_I 2034
+#define MACH_TYPE_PVG610 2035
+#define MACH_TYPE_HPRW6815 2036
+#define MACH_TYPE_OMAP3_OSWALD 2037
#define MACH_TYPE_NAS4220B 2038
+#define MACH_TYPE_HTCRAPHAEL_CDMA 2039
+#define MACH_TYPE_HTCDIAMOND_CDMA 2040
+#define MACH_TYPE_SCALER 2041
#define MACH_TYPE_ZYLONITE2 2042
#define MACH_TYPE_ASPENITE 2043
+#define MACH_TYPE_TETON 2044
#define MACH_TYPE_TTC_DKB 2045
+#define MACH_TYPE_BISHOP2 2046
+#define MACH_TYPE_IPPV5 2047
+#define MACH_TYPE_FARM926 2048
+#define MACH_TYPE_MMCCPU 2049
+#define MACH_TYPE_SGMSFL 2050
+#define MACH_TYPE_TT8000 2051
+#define MACH_TYPE_ZRN4300LP 2052
+#define MACH_TYPE_MPTC 2053
+#define MACH_TYPE_H6051 2054
+#define MACH_TYPE_PVG610_101 2055
+#define MACH_TYPE_STAMP9261_PC_EVB 2056
+#define MACH_TYPE_PELCO_ODYSSEUS 2057
+#define MACH_TYPE_TNY_A9260 2058
+#define MACH_TYPE_TNY_A9G20 2059
+#define MACH_TYPE_AESOP_MP2530F 2060
+#define MACH_TYPE_DX900 2061
+#define MACH_TYPE_CPODC2 2062
+#define MACH_TYPE_TILT_8925 2063
+#define MACH_TYPE_DAVINCI_DM357_EVM 2064
+#define MACH_TYPE_SWORDFISH 2065
+#define MACH_TYPE_CORVUS 2066
+#define MACH_TYPE_TAURUS 2067
+#define MACH_TYPE_AXM 2068
+#define MACH_TYPE_AXC 2069
+#define MACH_TYPE_BABY 2070
+#define MACH_TYPE_MP200 2071
#define MACH_TYPE_PCM043 2072
+#define MACH_TYPE_HANLIN_V3C 2073
+#define MACH_TYPE_KBK9G20 2074
+#define MACH_TYPE_ADSTURBOG5 2075
+#define MACH_TYPE_AVENGER_LITE1 2076
+#define MACH_TYPE_SUC 2077
+#define MACH_TYPE_AT91SAM7S256 2078
+#define MACH_TYPE_MENDOZA 2079
+#define MACH_TYPE_KIRA 2080
+#define MACH_TYPE_MX1HBM 2081
+#define MACH_TYPE_QUATRO43XX 2082
+#define MACH_TYPE_QUATRO4230 2083
+#define MACH_TYPE_NSB400 2084
+#define MACH_TYPE_DRP255 2085
+#define MACH_TYPE_THOTH 2086
+#define MACH_TYPE_FIRESTONE 2087
+#define MACH_TYPE_ASUSP750 2088
+#define MACH_TYPE_CTERA_DL 2089
+#define MACH_TYPE_SOCR 2090
+#define MACH_TYPE_HTCOXYGEN 2091
+#define MACH_TYPE_HEROC 2092
+#define MACH_TYPE_ZENO6800 2093
+#define MACH_TYPE_SC2MCS 2094
+#define MACH_TYPE_GENE100 2095
+#define MACH_TYPE_AS353X 2096
#define MACH_TYPE_SHEEVAPLUG 2097
+#define MACH_TYPE_AT91SAM9G20 2098
+#define MACH_TYPE_MV88F6192GTW_FE 2099
+#define MACH_TYPE_CC9200 2100
+#define MACH_TYPE_SM9200 2101
+#define MACH_TYPE_TP9200 2102
+#define MACH_TYPE_SNAPPERDV 2103
#define MACH_TYPE_AVENGERS_LITE 2104
+#define MACH_TYPE_AVENGERS_LITE1 2105
+#define MACH_TYPE_OMAP3AXON 2106
+#define MACH_TYPE_MA8XX 2107
+#define MACH_TYPE_MP201EK 2108
+#define MACH_TYPE_DAVINCI_TUX 2109
+#define MACH_TYPE_MPA1600 2110
+#define MACH_TYPE_PELCO_TROY 2111
+#define MACH_TYPE_NSB667 2112
+#define MACH_TYPE_ROVERS5_4MPIX 2113
+#define MACH_TYPE_TWOCOM 2114
+#define MACH_TYPE_UBISYS_P9_RCU3R2 2115
+#define MACH_TYPE_HERO_ESPRESSO 2116
+#define MACH_TYPE_AFEUSB 2117
+#define MACH_TYPE_T830 2118
+#define MACH_TYPE_SPD8020_CC 2119
+#define MACH_TYPE_OM_3D7K 2120
+#define MACH_TYPE_PICOCOM2 2121
+#define MACH_TYPE_UWG4MX27 2122
+#define MACH_TYPE_UWG4MX31 2123
+#define MACH_TYPE_CHERRY 2124
#define MACH_TYPE_MX51_BABBAGE 2125
+#define MACH_TYPE_S3C2440TURKIYE 2126
+#define MACH_TYPE_TX37 2127
+#define MACH_TYPE_SBC2800_9G20 2128
+#define MACH_TYPE_BENZGLB 2129
+#define MACH_TYPE_BENZTD 2130
+#define MACH_TYPE_CARTESIO_PLUS 2131
+#define MACH_TYPE_SOLRAD_G20 2132
+#define MACH_TYPE_MX27WALLACE 2133
+#define MACH_TYPE_FMZWEBMODUL 2134
#define MACH_TYPE_RD78X00_MASA 2135
+#define MACH_TYPE_SMALLOGGER 2136
+#define MACH_TYPE_CCW9P9215 2137
#define MACH_TYPE_DM355_LEOPARD 2138
#define MACH_TYPE_TS219 2139
+#define MACH_TYPE_TNY_A9263 2140
+#define MACH_TYPE_APOLLO 2141
+#define MACH_TYPE_AT91CAP9STK 2142
+#define MACH_TYPE_SPC300 2143
+#define MACH_TYPE_EKO 2144
+#define MACH_TYPE_CCW9M2443 2145
+#define MACH_TYPE_CCW9M2443JS 2146
+#define MACH_TYPE_M2M_ROUTER_DEVICE 2147
+#define MACH_TYPE_STAR9104NAS 2148
#define MACH_TYPE_PCA100 2149
+#define MACH_TYPE_Z3_DM365_MOD_01 2150
+#define MACH_TYPE_HIPOX 2151
+#define MACH_TYPE_OMAP3_PITEDS 2152
+#define MACH_TYPE_BM150R 2153
+#define MACH_TYPE_TBONE 2154
+#define MACH_TYPE_MERLIN 2155
+#define MACH_TYPE_FALCON 2156
#define MACH_TYPE_DAVINCI_DA850_EVM 2157
+#define MACH_TYPE_S5P6440 2158
#define MACH_TYPE_AT91SAM9G10EK 2159
#define MACH_TYPE_OMAP_4430SDP 2160
+#define MACH_TYPE_LPC313X 2161
#define MACH_TYPE_MAGX_ZN5 2162
+#define MACH_TYPE_MAGX_EM30 2163
+#define MACH_TYPE_MAGX_VE66 2164
+#define MACH_TYPE_MEESC 2165
+#define MACH_TYPE_OTC570 2166
+#define MACH_TYPE_BCU2412 2167
+#define MACH_TYPE_BEACON 2168
+#define MACH_TYPE_ACTIA_TGW 2169
+#define MACH_TYPE_E4430 2170
+#define MACH_TYPE_QL300 2171
+#define MACH_TYPE_BTMAVB101 2172
+#define MACH_TYPE_BTMAWB101 2173
+#define MACH_TYPE_SQ201 2174
+#define MACH_TYPE_QUATRO45XX 2175
+#define MACH_TYPE_OPENPAD 2176
+#define MACH_TYPE_TX25 2177
#define MACH_TYPE_OMAP3_TORPEDO 2178
+#define MACH_TYPE_HTCRAPHAEL_K 2179
+#define MACH_TYPE_LAL43 2181
+#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182
#define MACH_TYPE_ANW6410 2183
+#define MACH_TYPE_HTCPROPHET 2185
+#define MACH_TYPE_CFA_10022 2186
#define MACH_TYPE_IMX27_VISSTRIM_M10 2187
+#define MACH_TYPE_PX2IMX27 2188
+#define MACH_TYPE_STM3210E_EVAL 2189
+#define MACH_TYPE_DVS10 2190
#define MACH_TYPE_PORTUXG20 2191
+#define MACH_TYPE_ARM_SPV 2192
#define MACH_TYPE_SMDKC110 2193
#define MACH_TYPE_CABESPRESSO 2194
+#define MACH_TYPE_HMC800 2195
+#define MACH_TYPE_SHOLES 2196
+#define MACH_TYPE_BTMXC31 2197
+#define MACH_TYPE_DT501 2198
+#define MACH_TYPE_KTX 2199
#define MACH_TYPE_OMAP3517EVM 2200
#define MACH_TYPE_NETSPACE_V2 2201
#define MACH_TYPE_NETSPACE_MAX_V2 2202
#define MACH_TYPE_D2NET_V2 2203
#define MACH_TYPE_NET2BIG_V2 2204
+#define MACH_TYPE_NET4BIG_V2 2205
#define MACH_TYPE_NET5BIG_V2 2206
+#define MACH_TYPE_ENDB2443 2207
#define MACH_TYPE_INETSPACE_V2 2208
+#define MACH_TYPE_TROS 2209
+#define MACH_TYPE_PELCO_HOMER 2210
+#define MACH_TYPE_OFSP8 2211
#define MACH_TYPE_AT91SAM9G45EKES 2212
+#define MACH_TYPE_GUF_CUPID 2213
+#define MACH_TYPE_EAB1R 2214
+#define MACH_TYPE_DESIREC 2215
+#define MACH_TYPE_CORDOBA 2216
+#define MACH_TYPE_IRVINE 2217
+#define MACH_TYPE_SFF772 2218
+#define MACH_TYPE_PELCO_MILANO 2219
+#define MACH_TYPE_PC7302 2220
+#define MACH_TYPE_BIP6000 2221
+#define MACH_TYPE_SILVERMOON 2222
+#define MACH_TYPE_VC0830 2223
+#define MACH_TYPE_DT430 2224
+#define MACH_TYPE_JI42PF 2225
+#define MACH_TYPE_GNET_KSM 2226
+#define MACH_TYPE_GNET_SGM 2227
+#define MACH_TYPE_GNET_SGR 2228
+#define MACH_TYPE_OMAP3_ICETEKEVM 2229
+#define MACH_TYPE_PNP 2230
+#define MACH_TYPE_CTERA_2BAY_K 2231
+#define MACH_TYPE_CTERA_2BAY_U 2232
+#define MACH_TYPE_SAS_C 2233
+#define MACH_TYPE_VMA2315 2234
+#define MACH_TYPE_VCS 2235
#define MACH_TYPE_SPEAR600 2236
#define MACH_TYPE_SPEAR300 2237
+#define MACH_TYPE_SPEAR1300 2238
#define MACH_TYPE_LILLY1131 2239
+#define MACH_TYPE_ARVOO_AX301 2240
+#define MACH_TYPE_MAPPHONE 2241
+#define MACH_TYPE_LEGEND 2242
+#define MACH_TYPE_SALSA 2243
+#define MACH_TYPE_LOUNGE 2244
+#define MACH_TYPE_VISION 2245
+#define MACH_TYPE_VMB20 2246
+#define MACH_TYPE_HY2410 2247
+#define MACH_TYPE_HY9315 2248
+#define MACH_TYPE_BULLWINKLE 2249
+#define MACH_TYPE_ARM_ULTIMATOR2 2250
+#define MACH_TYPE_VS_V210 2252
+#define MACH_TYPE_VS_V212 2253
#define MACH_TYPE_HMT 2254
+#define MACH_TYPE_KM_KIRKWOOD 2255
+#define MACH_TYPE_VESPER 2256
+#define MACH_TYPE_STR9 2257
+#define MACH_TYPE_OMAP3_WL_FF 2258
+#define MACH_TYPE_SIMCOM 2259
+#define MACH_TYPE_MCWEBIO 2260
+#define MACH_TYPE_OMAP3_PHRAZER 2261
+#define MACH_TYPE_DARWIN 2262
+#define MACH_TYPE_ORATISCOMU 2263
+#define MACH_TYPE_RTSBC20 2264
+#define MACH_TYPE_I780 2265
+#define MACH_TYPE_GEMINI324 2266
+#define MACH_TYPE_ORATISLAN 2267
+#define MACH_TYPE_ORATISALOG 2268
+#define MACH_TYPE_ORATISMADI 2269
+#define MACH_TYPE_ORATISOT16 2270
+#define MACH_TYPE_ORATISDESK 2271
#define MACH_TYPE_VEXPRESS 2272
+#define MACH_TYPE_SINTEXO 2273
+#define MACH_TYPE_CM3389 2274
+#define MACH_TYPE_OMAP3_CIO 2275
+#define MACH_TYPE_SGH_I900 2276
+#define MACH_TYPE_BST100 2277
+#define MACH_TYPE_PASSION 2278
+#define MACH_TYPE_INDESIGN_AT91SAM 2279
+#define MACH_TYPE_C4_BADGER 2280
+#define MACH_TYPE_C4_VIPER 2281
#define MACH_TYPE_D2NET 2282
#define MACH_TYPE_BIGDISK 2283
+#define MACH_TYPE_NOTALVISION 2284
+#define MACH_TYPE_OMAP3_KBOC 2285
+#define MACH_TYPE_CYCLONE 2286
+#define MACH_TYPE_NINJA 2287
#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288
#define MACH_TYPE_BCMRING 2289
+#define MACH_TYPE_RESOL_DL2 2290
+#define MACH_TYPE_IFOSW 2291
+#define MACH_TYPE_HTCRHODIUM 2292
+#define MACH_TYPE_HTCTOPAZ 2293
+#define MACH_TYPE_MATRIX504 2294
+#define MACH_TYPE_MRFSA 2295
+#define MACH_TYPE_SC_P270 2296
+#define MACH_TYPE_ATLAS5_EVB 2297
+#define MACH_TYPE_PELCO_LOBOX 2298
+#define MACH_TYPE_DILAX_PCU200 2299
+#define MACH_TYPE_LEONARDO 2300
+#define MACH_TYPE_ZORAN_APPROACH7 2301
+#define MACH_TYPE_DP6XX 2302
+#define MACH_TYPE_BCM2153_VESPER 2303
#define MACH_TYPE_MAHIMAHI 2304
+#define MACH_TYPE_CLICKC 2305
+#define MACH_TYPE_ZB_GATEWAY 2306
+#define MACH_TYPE_TAZCARD 2307
+#define MACH_TYPE_TAZDEV 2308
+#define MACH_TYPE_ANNAX_CB_ARM 2309
+#define MACH_TYPE_ANNAX_DM3 2310
#define MACH_TYPE_CEREBRIC 2311
+#define MACH_TYPE_ORCA 2312
+#define MACH_TYPE_PC9260 2313
+#define MACH_TYPE_EMS285A 2314
+#define MACH_TYPE_GEC2410 2315
+#define MACH_TYPE_GEC2440 2316
+#define MACH_TYPE_ARCH_MW903 2317
+#define MACH_TYPE_MW2440 2318
+#define MACH_TYPE_ECAC2378 2319
+#define MACH_TYPE_TAZKIOSK 2320
+#define MACH_TYPE_WHITERABBIT_MCH 2321
+#define MACH_TYPE_SBOX9263 2322
#define MACH_TYPE_SMDK6442 2324
#define MACH_TYPE_OPENRD_BASE 2325
+#define MACH_TYPE_INCREDIBLE 2326
+#define MACH_TYPE_INCREDIBLEC 2327
+#define MACH_TYPE_HEROCT 2328
+#define MACH_TYPE_MMNET1000 2329
#define MACH_TYPE_DEVKIT8000 2330
+#define MACH_TYPE_DEVKIT9000 2331
+#define MACH_TYPE_MX31TXTR 2332
+#define MACH_TYPE_U380 2333
+#define MACH_TYPE_HUALU_BOARD 2334
+#define MACH_TYPE_NPCMX50 2335
#define MACH_TYPE_MX51_EFIKAMX 2336
+#define MACH_TYPE_MX51_LANGE52 2337
+#define MACH_TYPE_RIOM 2338
+#define MACH_TYPE_COMCAS 2339
+#define MACH_TYPE_WSI_MX27 2340
#define MACH_TYPE_CM_T35 2341
#define MACH_TYPE_NET2BIG 2342
+#define MACH_TYPE_MOTOROLA_A1600 2343
#define MACH_TYPE_IGEP0020 2344
+#define MACH_TYPE_IGEP0010 2345
+#define MACH_TYPE_MV6281GTWGE2 2346
+#define MACH_TYPE_SCAT100 2347
+#define MACH_TYPE_SANMINA 2348
+#define MACH_TYPE_MOMENTO 2349
+#define MACH_TYPE_NUC9XX 2350
+#define MACH_TYPE_NUC910EVB 2351
+#define MACH_TYPE_NUC920EVB 2352
+#define MACH_TYPE_NUC950EVB 2353
+#define MACH_TYPE_NUC945EVB 2354
+#define MACH_TYPE_NUC960EVB 2355
#define MACH_TYPE_NUC932EVB 2356
+#define MACH_TYPE_NUC900 2357
+#define MACH_TYPE_SD1SOC 2358
+#define MACH_TYPE_LN2440BC 2359
+#define MACH_TYPE_RSBC 2360
#define MACH_TYPE_OPENRD_CLIENT 2361
+#define MACH_TYPE_HPIPAQ11X 2362
+#define MACH_TYPE_WAYLAND 2363
+#define MACH_TYPE_ACNBSX102 2364
+#define MACH_TYPE_HWAT91 2365
+#define MACH_TYPE_AT91SAM9263CS 2366
+#define MACH_TYPE_CSB732 2367
#define MACH_TYPE_U8500 2368
+#define MACH_TYPE_HUQIU 2369
#define MACH_TYPE_MX51_EFIKASB 2370
+#define MACH_TYPE_PMT1G 2371
+#define MACH_TYPE_HTCELF 2372
+#define MACH_TYPE_ARMADILLO420 2373
+#define MACH_TYPE_ARMADILLO440 2374
+#define MACH_TYPE_U_CHIP_DUAL_ARM 2375
+#define MACH_TYPE_CSR_BDB3 2376
+#define MACH_TYPE_DOLBY_CAT1018 2377
+#define MACH_TYPE_HY9307 2378
+#define MACH_TYPE_A_ES 2379
+#define MACH_TYPE_DAVINCI_IRIF 2380
+#define MACH_TYPE_AGAMA9263 2381
#define MACH_TYPE_MARVELL_JASPER 2382
#define MACH_TYPE_FLINT 2383
#define MACH_TYPE_TAVOREVB3 2384
+#define MACH_TYPE_SCH_M490 2386
+#define MACH_TYPE_RBL01 2387
+#define MACH_TYPE_OMNIFI 2388
+#define MACH_TYPE_OTAVALO 2389
+#define MACH_TYPE_HTC_EXCALIBUR_S620 2391
+#define MACH_TYPE_HTC_OPAL 2392
#define MACH_TYPE_TOUCHBOOK 2393
+#define MACH_TYPE_LATTE 2394
+#define MACH_TYPE_XA200 2395
+#define MACH_TYPE_NIMROD 2396
+#define MACH_TYPE_CC9P9215_3G 2397
+#define MACH_TYPE_CC9P9215_3GJS 2398
+#define MACH_TYPE_TK71 2399
+#define MACH_TYPE_COMHAM3525 2400
+#define MACH_TYPE_MX31EREBUS 2401
+#define MACH_TYPE_MCARDMX27 2402
+#define MACH_TYPE_PARADISE 2403
+#define MACH_TYPE_TIDE 2404
+#define MACH_TYPE_WZL2440 2405
+#define MACH_TYPE_SDRDEMO 2406
+#define MACH_TYPE_ETHERCAN2 2407
+#define MACH_TYPE_ECMIMG20 2408
+#define MACH_TYPE_OMAP_DRAGON 2409
+#define MACH_TYPE_HALO 2410
+#define MACH_TYPE_HUANGSHAN 2411
+#define MACH_TYPE_VL_MA2SC 2412
#define MACH_TYPE_RAUMFELD_RC 2413
#define MACH_TYPE_RAUMFELD_CONNECTOR 2414
#define MACH_TYPE_RAUMFELD_SPEAKER 2415
+#define MACH_TYPE_MULTIBUS_MASTER 2416
+#define MACH_TYPE_MULTIBUS_PBK 2417
#define MACH_TYPE_TNETV107X 2418
+#define MACH_TYPE_SNAKE 2419
+#define MACH_TYPE_CWMX27 2420
+#define MACH_TYPE_SCH_M480 2421
+#define MACH_TYPE_PLATYPUS 2422
+#define MACH_TYPE_PSS2 2423
+#define MACH_TYPE_DAVINCI_APM150 2424
+#define MACH_TYPE_STR9100 2425
+#define MACH_TYPE_NET5BIG 2426
+#define MACH_TYPE_SEABED9263 2427
+#define MACH_TYPE_MX51_M2ID 2428
+#define MACH_TYPE_OCTVOCPLUS_EB 2429
+#define MACH_TYPE_KLK_FIREFOX 2430
+#define MACH_TYPE_KLK_WIRMA_MODULE 2431
+#define MACH_TYPE_KLK_WIRMA_MMI 2432
+#define MACH_TYPE_SUPERSONIC 2433
+#define MACH_TYPE_LIBERTY 2434
+#define MACH_TYPE_MH355 2435
+#define MACH_TYPE_PC7802 2436
+#define MACH_TYPE_GNET_SGC 2437
+#define MACH_TYPE_EINSTEIN15 2438
+#define MACH_TYPE_CMPD 2439
+#define MACH_TYPE_DAVINCI_HASE1 2440
+#define MACH_TYPE_LGEINCITEPHONE 2441
+#define MACH_TYPE_EA313X 2442
+#define MACH_TYPE_FWBD_39064 2443
+#define MACH_TYPE_FWBD_390128 2444
+#define MACH_TYPE_PELCO_MOE 2445
+#define MACH_TYPE_MINIMIX27 2446
+#define MACH_TYPE_OMAP3_THUNDER 2447
+#define MACH_TYPE_PASSIONC 2448
+#define MACH_TYPE_MX27AMATA 2449
+#define MACH_TYPE_BGAT1 2450
+#define MACH_TYPE_BUZZ 2451
+#define MACH_TYPE_MB9G20 2452
+#define MACH_TYPE_YUSHAN 2453
+#define MACH_TYPE_LIZARD 2454
+#define MACH_TYPE_OMAP3POLYCOM 2455
#define MACH_TYPE_SMDKV210 2456
+#define MACH_TYPE_BRAVO 2457
+#define MACH_TYPE_SIOGENTOO1 2458
+#define MACH_TYPE_SIOGENTOO2 2459
+#define MACH_TYPE_SM3K 2460
+#define MACH_TYPE_ACER_TEMPO_F900 2461
+#define MACH_TYPE_GLITTERTIND 2463
#define MACH_TYPE_OMAP_ZOOM3 2464
#define MACH_TYPE_OMAP_3630SDP 2465
#define MACH_TYPE_CYBOOK2440 2466
+#define MACH_TYPE_TORINO_S 2467
+#define MACH_TYPE_HAVANA 2468
+#define MACH_TYPE_BEAUMONT_11 2469
+#define MACH_TYPE_VANGUARD 2470
+#define MACH_TYPE_S5PC110_DRACO 2471
+#define MACH_TYPE_CARTESIO_TWO 2472
+#define MACH_TYPE_ASTER 2473
+#define MACH_TYPE_VOGUESV210 2474
+#define MACH_TYPE_ACM500X 2475
+#define MACH_TYPE_KM9260 2476
+#define MACH_TYPE_NIDEFLEXG1 2477
+#define MACH_TYPE_CTERA_PLUG_IO 2478
#define MACH_TYPE_SMARTQ7 2479
+#define MACH_TYPE_AT91SAM9G10EK2 2480
+#define MACH_TYPE_ASUSP527 2481
+#define MACH_TYPE_AT91SAM9G20MPM2 2482
+#define MACH_TYPE_TOPASA900 2483
+#define MACH_TYPE_ELECTRUM_100 2484
+#define MACH_TYPE_MX51GRB 2485
+#define MACH_TYPE_XEA300 2486
+#define MACH_TYPE_HTCSTARTREK 2487
+#define MACH_TYPE_LIMA 2488
+#define MACH_TYPE_CSB740 2489
+#define MACH_TYPE_USB_S8815 2490
#define MACH_TYPE_WATSON_EFM_PLUGIN 2491
+#define MACH_TYPE_MILKYWAY 2492
#define MACH_TYPE_G4EVM 2493
+#define MACH_TYPE_PICOMOD6 2494
#define MACH_TYPE_OMAPL138_HAWKBOARD 2495
+#define MACH_TYPE_IP6000 2496
+#define MACH_TYPE_IP6010 2497
+#define MACH_TYPE_UTM400 2498
+#define MACH_TYPE_OMAP3_ZYBEX 2499
+#define MACH_TYPE_WIRELESS_SPACE 2500
+#define MACH_TYPE_SX560 2501
#define MACH_TYPE_TS41X 2502
+#define MACH_TYPE_ELPHEL10373 2503
+#define MACH_TYPE_RHOBOT 2504
+#define MACH_TYPE_MX51_REFRESH 2505
+#define MACH_TYPE_LS9260 2506
+#define MACH_TYPE_SHANK 2507
+#define MACH_TYPE_QSD8X50_ST1 2508
+#define MACH_TYPE_AT91SAM9M10EKES 2509
+#define MACH_TYPE_HIRAM 2510
#define MACH_TYPE_PHY3250 2511
+#define MACH_TYPE_EA3250 2512
+#define MACH_TYPE_FDI3250 2513
+#define MACH_TYPE_AT91SAM9263NIT 2515
+#define MACH_TYPE_CCMX51 2516
+#define MACH_TYPE_CCMX51JS 2517
+#define MACH_TYPE_CCWMX51 2518
+#define MACH_TYPE_CCWMX51JS 2519
#define MACH_TYPE_MINI6410 2520
+#define MACH_TYPE_TINY6410 2521
+#define MACH_TYPE_NANO6410 2522
+#define MACH_TYPE_AT572D940HFNLDB 2523
+#define MACH_TYPE_HTCLEO 2524
+#define MACH_TYPE_AVP13 2525
+#define MACH_TYPE_XXSVIDEOD 2526
+#define MACH_TYPE_VPNEXT 2527
+#define MACH_TYPE_SWARCO_ITC3 2528
+#define MACH_TYPE_TX51 2529
+#define MACH_TYPE_DOLBY_CAT1021 2530
#define MACH_TYPE_MX28EVK 2531
+#define MACH_TYPE_PHOENIX260 2532
+#define MACH_TYPE_UVACA_STORK 2533
#define MACH_TYPE_SMARTQ5 2534
+#define MACH_TYPE_ALL3078 2535
+#define MACH_TYPE_CTERA_2BAY_DS 2536
+#define MACH_TYPE_SIOGENTOO3 2537
+#define MACH_TYPE_EPB5000 2538
+#define MACH_TYPE_HY9263 2539
+#define MACH_TYPE_ACER_TEMPO_M900 2540
+#define MACH_TYPE_ACER_TEMPO_DX900 2541
+#define MACH_TYPE_ACER_TEMPO_X960 2542
+#define MACH_TYPE_ACER_ETEN_V900 2543
+#define MACH_TYPE_ACER_ETEN_X900 2544
+#define MACH_TYPE_BONNELL 2545
+#define MACH_TYPE_OHT_MX27 2546
+#define MACH_TYPE_HTCQUARTZ 2547
#define MACH_TYPE_DAVINCI_DM6467TEVM 2548
+#define MACH_TYPE_C3AX03 2549
#define MACH_TYPE_MXT_TD60 2550
+#define MACH_TYPE_ESYX 2551
+#define MACH_TYPE_DOVE_DB2 2552
+#define MACH_TYPE_BULLDOG 2553
+#define MACH_TYPE_DERELL_ME2000 2554
+#define MACH_TYPE_BCMRING_BASE 2555
+#define MACH_TYPE_BCMRING_EVM 2556
+#define MACH_TYPE_BCMRING_EVM_JAZZ 2557
+#define MACH_TYPE_BCMRING_SP 2558
+#define MACH_TYPE_BCMRING_SV 2559
+#define MACH_TYPE_BCMRING_SV_JAZZ 2560
+#define MACH_TYPE_BCMRING_TABLET 2561
+#define MACH_TYPE_BCMRING_VP 2562
+#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563
+#define MACH_TYPE_BCMRING_SP_WQVGA 2564
+#define MACH_TYPE_BCMRING_CUSTOM 2565
+#define MACH_TYPE_ACER_S200 2566
+#define MACH_TYPE_BT270 2567
+#define MACH_TYPE_ISEO 2568
+#define MACH_TYPE_CEZANNE 2569
+#define MACH_TYPE_LUCCA 2570
+#define MACH_TYPE_SUPERSMART 2571
+#define MACH_TYPE_CS_MISANO 2572
+#define MACH_TYPE_MAGNOLIA2 2573
+#define MACH_TYPE_EMXX 2574
+#define MACH_TYPE_OUTLAW 2575
+#define MACH_TYPE_RIOT_BEI2 2576
+#define MACH_TYPE_RIOT_VOX 2577
+#define MACH_TYPE_RIOT_X37 2578
+#define MACH_TYPE_MEGA25MX 2579
+#define MACH_TYPE_BENZINA2 2580
+#define MACH_TYPE_IGNITE 2581
+#define MACH_TYPE_FOGGIA 2582
+#define MACH_TYPE_AREZZO 2583
+#define MACH_TYPE_LEICA_SKYWALKER 2584
+#define MACH_TYPE_JACINTO2_JAMR 2585
+#define MACH_TYPE_GTS_NOVA 2586
+#define MACH_TYPE_P3600 2587
+#define MACH_TYPE_DLT2 2588
+#define MACH_TYPE_DF3120 2589
+#define MACH_TYPE_ECUCORE_9G20 2590
+#define MACH_TYPE_NAUTEL_LPC3240 2591
+#define MACH_TYPE_GLACIER 2592
+#define MACH_TYPE_PHRAZER_BULLDOG 2593
+#define MACH_TYPE_OMAP3_BULLDOG 2594
+#define MACH_TYPE_PCA101 2595
+#define MACH_TYPE_BUZZC 2596
+#define MACH_TYPE_SASIE2 2597
+#define MACH_TYPE_SMARTMETER_DL 2599
+#define MACH_TYPE_WZL6410 2600
+#define MACH_TYPE_WZL6410M 2601
+#define MACH_TYPE_WZL6410F 2602
+#define MACH_TYPE_WZL6410I 2603
+#define MACH_TYPE_SPACECOM1 2604
+#define MACH_TYPE_PINGU920 2605
+#define MACH_TYPE_BRAVOC 2606
+#define MACH_TYPE_VDSSW 2608
+#define MACH_TYPE_ROMULUS 2609
+#define MACH_TYPE_OMAP_MAGIC 2610
+#define MACH_TYPE_ELTD100 2611
#define MACH_TYPE_CAPC7117 2612
+#define MACH_TYPE_SWAN 2613
+#define MACH_TYPE_VEU 2614
+#define MACH_TYPE_RM2 2615
+#define MACH_TYPE_TT2100 2616
+#define MACH_TYPE_VENICE 2617
+#define MACH_TYPE_PC7323 2618
+#define MACH_TYPE_MASP 2619
+#define MACH_TYPE_FUJITSU_TVSTBSOC 2620
+#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621
+#define MACH_TYPE_LEXIKON 2622
+#define MACH_TYPE_MINI2440V2 2623
#define MACH_TYPE_ICONTROL 2624
#define MACH_TYPE_GPLUGD 2625
+#define MACH_TYPE_QSD8X50A_ST1_1 2626
#define MACH_TYPE_QSD8X50A_ST1_5 2627
+#define MACH_TYPE_BEE 2628
#define MACH_TYPE_MX23EVK 2629
#define MACH_TYPE_AP4EVB 2630
+#define MACH_TYPE_STOCKHOLM 2631
+#define MACH_TYPE_LPC_H3131 2632
+#define MACH_TYPE_STINGRAY 2633
+#define MACH_TYPE_KRAKEN 2634
+#define MACH_TYPE_GW2388 2635
+#define MACH_TYPE_JADECPU 2636
+#define MACH_TYPE_CARLISLE 2637
+#define MACH_TYPE_LUX_SF9 2638
+#define MACH_TYPE_NEMID_TB 2639
+#define MACH_TYPE_TERRIER 2640
+#define MACH_TYPE_TURBOT 2641
+#define MACH_TYPE_SANDDAB 2642
+#define MACH_TYPE_MX35_CICADA 2643
+#define MACH_TYPE_GHI2703D 2644
+#define MACH_TYPE_LUX_SFX9 2645
+#define MACH_TYPE_LUX_SF9G 2646
+#define MACH_TYPE_LUX_EDK9 2647
+#define MACH_TYPE_HW90240 2648
+#define MACH_TYPE_DM365_LEOPARD 2649
#define MACH_TYPE_MITYOMAPL138 2650
+#define MACH_TYPE_SCAT110 2651
+#define MACH_TYPE_ACER_A1 2652
+#define MACH_TYPE_CMCONTROL 2653
+#define MACH_TYPE_PELCO_LAMAR 2654
+#define MACH_TYPE_RFP43 2655
+#define MACH_TYPE_SK86R0301 2656
+#define MACH_TYPE_CTPXA 2657
+#define MACH_TYPE_EPB_ARM9_A 2658
#define MACH_TYPE_GURUPLUG 2659
#define MACH_TYPE_SPEAR310 2660
#define MACH_TYPE_SPEAR320 2661
+#define MACH_TYPE_ROBOTX 2662
+#define MACH_TYPE_LSXHL 2663
+#define MACH_TYPE_SMARTLITE 2664
+#define MACH_TYPE_CWS2 2665
+#define MACH_TYPE_M619 2666
+#define MACH_TYPE_SMARTVIEW 2667
+#define MACH_TYPE_LSA_SALSA 2668
+#define MACH_TYPE_KIZBOX 2669
+#define MACH_TYPE_HTCCHARMER 2670
+#define MACH_TYPE_GUF_NESO_LT 2671
+#define MACH_TYPE_PM9G45 2672
+#define MACH_TYPE_HTCPANTHER 2673
+#define MACH_TYPE_HTCPANTHER_CDMA 2674
+#define MACH_TYPE_REB01 2675
#define MACH_TYPE_AQUILA 2676
+#define MACH_TYPE_SPARK_SLS_HW2 2677
#define MACH_TYPE_ESATA_SHEEVAPLUG 2678
#define MACH_TYPE_MSM7X30_SURF 2679
+#define MACH_TYPE_MICRO2440 2680
+#define MACH_TYPE_AM2440 2681
+#define MACH_TYPE_TQ2440 2682
+#define MACH_TYPE_EA2478DEVKIT 2683
+#define MACH_TYPE_AK880X 2684
+#define MACH_TYPE_COBRA3530 2685
+#define MACH_TYPE_PMPPB 2686
+#define MACH_TYPE_U6715 2687
+#define MACH_TYPE_AXAR1500_SENDER 2688
+#define MACH_TYPE_G30_DVB 2689
+#define MACH_TYPE_VC088X 2690
+#define MACH_TYPE_MIOA702 2691
+#define MACH_TYPE_HPMIN 2692
+#define MACH_TYPE_AK880XAK 2693
+#define MACH_TYPE_ARM926TOMAP850 2694
+#define MACH_TYPE_LKEVM 2695
+#define MACH_TYPE_MW6410 2696
#define MACH_TYPE_TERASTATION_WXL 2697
+#define MACH_TYPE_CPU8000E 2698
+#define MACH_TYPE_TOKYO 2700
+#define MACH_TYPE_MSM7201A_SURF 2701
+#define MACH_TYPE_MSM7201A_FFA 2702
#define MACH_TYPE_MSM7X25_SURF 2703
#define MACH_TYPE_MSM7X25_FFA 2704
#define MACH_TYPE_MSM7X27_SURF 2705
#define MACH_TYPE_MSM7X27_FFA 2706
#define MACH_TYPE_MSM7X30_FFA 2707
#define MACH_TYPE_QSD8X50_SURF 2708
+#define MACH_TYPE_QSD8X50_COMET 2709
+#define MACH_TYPE_QSD8X50_FFA 2710
+#define MACH_TYPE_QSD8X50A_SURF 2711
+#define MACH_TYPE_QSD8X50A_FFA 2712
+#define MACH_TYPE_ADX_XGCP10 2713
+#define MACH_TYPE_MCGWUMTS2A 2714
+#define MACH_TYPE_MOBIKT 2715
#define MACH_TYPE_MX53_EVK 2716
#define MACH_TYPE_IGEP0030 2717
+#define MACH_TYPE_AXELL_H40_H50_CTRL 2718
+#define MACH_TYPE_DTCOMMOD 2719
+#define MACH_TYPE_GOULD 2720
+#define MACH_TYPE_SIBERIA 2721
#define MACH_TYPE_SBC3530 2722
+#define MACH_TYPE_QARM 2723
+#define MACH_TYPE_MIPS 2724
+#define MACH_TYPE_MX27GRB 2725
+#define MACH_TYPE_SBC8100 2726
#define MACH_TYPE_SAARB 2727
+#define MACH_TYPE_OMAP3MINI 2728
+#define MACH_TYPE_CNMBOOK7SE 2729
+#define MACH_TYPE_CATAN 2730
#define MACH_TYPE_HARMONY 2731
+#define MACH_TYPE_TONGA 2732
#define MACH_TYPE_CYBOOK_ORIZON 2733
+#define MACH_TYPE_HTCRHODIUMCDMA 2734
+#define MACH_TYPE_EPC_G45 2735
+#define MACH_TYPE_EPC_LPC3250 2736
+#define MACH_TYPE_MXC91341EVB 2737
+#define MACH_TYPE_RTW1000 2738
+#define MACH_TYPE_BOBCAT 2739
+#define MACH_TYPE_TRIZEPS6 2740
#define MACH_TYPE_MSM7X30_FLUID 2741
+#define MACH_TYPE_NEDAP9263 2742
+#define MACH_TYPE_NETGEAR_MS2110 2743
+#define MACH_TYPE_BMX 2744
+#define MACH_TYPE_NETSTREAM 2745
+#define MACH_TYPE_VPNEXT_RCU 2746
+#define MACH_TYPE_VPNEXT_MPU 2747
+#define MACH_TYPE_BCMRING_TABLET_V1 2748
+#define MACH_TYPE_SGARM10 2749
#define MACH_TYPE_CM_T3517 2750
+#define MACH_TYPE_OMAP3_CPS 2751
+#define MACH_TYPE_AXAR1500_RECEIVER 2752
#define MACH_TYPE_WBD222 2753
+#define MACH_TYPE_MT65XX 2754
#define MACH_TYPE_MSM8X60_SURF 2755
#define MACH_TYPE_MSM8X60_SIM 2756
#define MACH_TYPE_TCC8000_SDK 2758
+#define MACH_TYPE_NANOS 2759
+#define MACH_TYPE_STAMP9G10 2760
+#define MACH_TYPE_STAMP9G45 2761
+#define MACH_TYPE_H6053 2762
+#define MACH_TYPE_SMINT01 2763
+#define MACH_TYPE_PRTLVT2 2764
+#define MACH_TYPE_AP420 2765
+#define MACH_TYPE_DAVINCI_DM365_FC 2767
+#define MACH_TYPE_MSM8X55_SURF 2768
+#define MACH_TYPE_MSM8X55_FFA 2769
+#define MACH_TYPE_ESL_VAMANA 2770
+#define MACH_TYPE_SBC35 2771
+#define MACH_TYPE_MPX6446 2772
+#define MACH_TYPE_OREO_CONTROLLER 2773
+#define MACH_TYPE_KOPIN_MODELS 2774
+#define MACH_TYPE_TTC_VISION2 2775
#define MACH_TYPE_CNS3420VB 2776
+#define MACH_TYPE_LPC2 2777
+#define MACH_TYPE_OLYMPUS 2778
+#define MACH_TYPE_VORTEX 2779
+#define MACH_TYPE_S5PC200 2780
+#define MACH_TYPE_ECUCORE_9263 2781
+#define MACH_TYPE_SMDKC200 2782
+#define MACH_TYPE_EMSISO_SX27 2783
+#define MACH_TYPE_APX_SOM9G45_EK 2784
+#define MACH_TYPE_SONGSHAN 2785
+#define MACH_TYPE_TIANSHAN 2786
+#define MACH_TYPE_VPX500 2787
+#define MACH_TYPE_AM3517SAM 2788
+#define MACH_TYPE_SKAT91_SIM508 2789
+#define MACH_TYPE_SKAT91_S3E 2790
#define MACH_TYPE_OMAP4_PANDA 2791
+#define MACH_TYPE_DF7220 2792
+#define MACH_TYPE_NEMINI 2793
+#define MACH_TYPE_T8200 2794
+#define MACH_TYPE_APF51 2795
+#define MACH_TYPE_DR_RC_UNIT 2796
+#define MACH_TYPE_BORDEAUX 2797
+#define MACH_TYPE_CATANIA_B 2798
+#define MACH_TYPE_MX51_OCEAN 2799
#define MACH_TYPE_TI8168EVM 2800
+#define MACH_TYPE_NEOCOREOMAP 2801
+#define MACH_TYPE_WITHINGS_WBP 2802
+#define MACH_TYPE_DBPS 2803
+#define MACH_TYPE_PCBFP0001 2805
+#define MACH_TYPE_SPEEDY 2806
+#define MACH_TYPE_CHRYSAOR 2807
+#define MACH_TYPE_TANGO 2808
+#define MACH_TYPE_SYNOLOGY_DSX11 2809
+#define MACH_TYPE_HANLIN_V3EXT 2810
+#define MACH_TYPE_HANLIN_V5 2811
+#define MACH_TYPE_HANLIN_V3PLUS 2812
+#define MACH_TYPE_IRIVER_STORY 2813
+#define MACH_TYPE_IREX_ILIAD 2814
+#define MACH_TYPE_IREX_DR1000 2815
#define MACH_TYPE_TETON_BGA 2816
+#define MACH_TYPE_SNAPPER9G45 2817
+#define MACH_TYPE_TAM3517 2818
+#define MACH_TYPE_PDC100 2819
#define MACH_TYPE_EUKREA_CPUIMX25SD 2820
#define MACH_TYPE_EUKREA_CPUIMX35SD 2821
#define MACH_TYPE_EUKREA_CPUIMX51SD 2822
#define MACH_TYPE_EUKREA_CPUIMX51 2823
+#define MACH_TYPE_P565 2824
+#define MACH_TYPE_ACER_A4 2825
+#define MACH_TYPE_DAVINCI_DM368_BIP 2826
+#define MACH_TYPE_ESHARE 2827
+#define MACH_TYPE_WLBARGN 2829
+#define MACH_TYPE_BM170 2830
+#define MACH_TYPE_NETSPACE_MINI_V2 2831
+#define MACH_TYPE_NETSPACE_PLUG_V2 2832
+#define MACH_TYPE_SIEMENS_L1 2833
+#define MACH_TYPE_ELV_LCU1 2834
+#define MACH_TYPE_MCU1 2835
+#define MACH_TYPE_OMAP3_TAO3530 2836
+#define MACH_TYPE_OMAP3_PCUTOUCH 2837
#define MACH_TYPE_SMDKC210 2838
+#define MACH_TYPE_OMAP3_BRAILLO 2839
+#define MACH_TYPE_SPYPLUG 2840
+#define MACH_TYPE_GINGER 2841
+#define MACH_TYPE_TNY_T3530 2842
+#define MACH_TYPE_PCAAL1 2843
+#define MACH_TYPE_SPADE 2844
+#define MACH_TYPE_MXC25_TOPAZ 2845
#define MACH_TYPE_T5325 2846
+#define MACH_TYPE_GW2361 2847
+#define MACH_TYPE_ELOG 2848
#define MACH_TYPE_INCOME 2849
+#define MACH_TYPE_BCM589X 2850
+#define MACH_TYPE_ETNA 2851
+#define MACH_TYPE_HAWKS 2852
+#define MACH_TYPE_MESON 2853
+#define MACH_TYPE_XSBASE255 2854
+#define MACH_TYPE_PVM2030 2855
+#define MACH_TYPE_MIOA502 2856
+#define MACH_TYPE_VVBOX_SDORIG2 2857
+#define MACH_TYPE_VVBOX_SDLITE2 2858
+#define MACH_TYPE_VVBOX_SDPRO4 2859
+#define MACH_TYPE_HTC_SPV_M700 2860
+#define MACH_TYPE_MX257SX 2861
#define MACH_TYPE_GONI 2862
+#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863
+#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864
+#define MACH_TYPE_QUICKSTEP 2865
+#define MACH_TYPE_DMW96 2866
+#define MACH_TYPE_HAMMERHEAD 2867
+#define MACH_TYPE_TRIDENT 2868
+#define MACH_TYPE_LIGHTNING 2869
+#define MACH_TYPE_ICONNECT 2870
+#define MACH_TYPE_AUTOBOT 2871
+#define MACH_TYPE_COCONUT 2872
+#define MACH_TYPE_DURIAN 2873
+#define MACH_TYPE_CAYENNE 2874
+#define MACH_TYPE_FUJI 2875
+#define MACH_TYPE_SYNOLOGY_6282 2876
+#define MACH_TYPE_EM1SY 2877
+#define MACH_TYPE_M502 2878
+#define MACH_TYPE_MATRIX518 2879
+#define MACH_TYPE_TINY_GURNARD 2880
+#define MACH_TYPE_SPEAR1310 2881
#define MACH_TYPE_BV07 2882
+#define MACH_TYPE_MXT_TD61 2883
#define MACH_TYPE_OPENRD_ULTIMATE 2884
#define MACH_TYPE_DEVIXP 2885
#define MACH_TYPE_MICCPT 2886
#define MACH_TYPE_MIC256 2887
+#define MACH_TYPE_AS1167 2888
+#define MACH_TYPE_OMAP3_IBIZA 2889
#define MACH_TYPE_U5500 2890
+#define MACH_TYPE_DAVINCI_PICTO 2891
+#define MACH_TYPE_MECHA 2892
+#define MACH_TYPE_BUBBA3 2893
+#define MACH_TYPE_PUPITRE 2894
+#define MACH_TYPE_TEGRA_VOGUE 2896
+#define MACH_TYPE_TEGRA_E1165 2897
+#define MACH_TYPE_SIMPLENET 2898
+#define MACH_TYPE_EC4350TBM 2899
+#define MACH_TYPE_PEC_TC 2900
+#define MACH_TYPE_PEC_HC2 2901
+#define MACH_TYPE_ESL_MOBILIS_A 2902
+#define MACH_TYPE_ESL_MOBILIS_B 2903
+#define MACH_TYPE_ESL_WAVE_A 2904
+#define MACH_TYPE_ESL_WAVE_B 2905
+#define MACH_TYPE_UNISENSE_MMM 2906
+#define MACH_TYPE_BLUESHARK 2907
+#define MACH_TYPE_E10 2908
+#define MACH_TYPE_APP3K_ROBIN 2909
+#define MACH_TYPE_POV15HD 2910
+#define MACH_TYPE_STELLA 2911
#define MACH_TYPE_LINKSTATION_LSCHL 2913
+#define MACH_TYPE_NETWALKER 2914
+#define MACH_TYPE_ACSX106 2915
+#define MACH_TYPE_ATLAS5_C1 2916
+#define MACH_TYPE_NSB3AST 2917
+#define MACH_TYPE_GNET_SLC 2918
+#define MACH_TYPE_AF4000 2919
+#define MACH_TYPE_ARK9431 2920
+#define MACH_TYPE_FS_S5PC100 2921
+#define MACH_TYPE_OMAP3505NOVA8 2922
+#define MACH_TYPE_OMAP3621_EDP1 2923
+#define MACH_TYPE_ORATISAES 2924
#define MACH_TYPE_SMDKV310 2925
+#define MACH_TYPE_SIEMENS_L0 2926
+#define MACH_TYPE_VENTANA 2927
#define MACH_TYPE_WM8505_7IN_NETBOOK 2928
+#define MACH_TYPE_EC4350SDB 2929
+#define MACH_TYPE_MIMAS 2930
+#define MACH_TYPE_TITAN 2931
#define MACH_TYPE_CRANEBOARD 2932
+#define MACH_TYPE_ES2440 2933
+#define MACH_TYPE_NAJAY_A9263 2934
+#define MACH_TYPE_HTCTORNADO 2935
+#define MACH_TYPE_DIMM_MX257 2936
+#define MACH_TYPE_JIGEN 2937
#define MACH_TYPE_SMDK6450 2938
+#define MACH_TYPE_MENO_QNG 2939
+#define MACH_TYPE_NS2416 2940
+#define MACH_TYPE_RPC353 2941
+#define MACH_TYPE_TQ6410 2942
+#define MACH_TYPE_SKY6410 2943
+#define MACH_TYPE_DYNASTY 2944
+#define MACH_TYPE_VIVO 2945
+#define MACH_TYPE_BURY_BL7582 2946
+#define MACH_TYPE_BURY_BPS5270 2947
+#define MACH_TYPE_BASI 2948
+#define MACH_TYPE_TN200 2949
+#define MACH_TYPE_C2MMI 2950
+#define MACH_TYPE_MESON_6236M 2951
+#define MACH_TYPE_MESON_8626M 2952
+#define MACH_TYPE_TUBE 2953
+#define MACH_TYPE_MESSINA 2954
+#define MACH_TYPE_MX50_ARM2 2955
+#define MACH_TYPE_CETUS9263 2956
#define MACH_TYPE_BROWNSTONE 2957
+#define MACH_TYPE_VMX25 2958
+#define MACH_TYPE_VMX51 2959
+#define MACH_TYPE_ABACUS 2960
+#define MACH_TYPE_CM4745 2961
+#define MACH_TYPE_ORATISLINK 2962
+#define MACH_TYPE_DAVINCI_DM365_DVR 2963
+#define MACH_TYPE_NETVIZ 2964
#define MACH_TYPE_FLEXIBITY 2965
+#define MACH_TYPE_WLAN_COMPUTER 2966
+#define MACH_TYPE_LPC24XX 2967
+#define MACH_TYPE_SPICA 2968
+#define MACH_TYPE_GPSDISPLAY 2969
+#define MACH_TYPE_BIPNET 2970
+#define MACH_TYPE_OVERO_CTU_INERTIAL 2971
+#define MACH_TYPE_DAVINCI_DM355_MMM 2972
+#define MACH_TYPE_PC9260_V2 2973
+#define MACH_TYPE_PTX7545 2974
+#define MACH_TYPE_TM_EFDC 2975
+#define MACH_TYPE_OMAP3_WALDO1 2977
+#define MACH_TYPE_FLYER 2978
+#define MACH_TYPE_TORNADO3240 2979
+#define MACH_TYPE_SOLI_01 2980
+#define MACH_TYPE_OMAPL138_EUROPALC 2981
+#define MACH_TYPE_HELIOS_V1 2982
+#define MACH_TYPE_NETSPACE_LITE_V2 2983
+#define MACH_TYPE_SSC 2984
+#define MACH_TYPE_PREMIERWAVE_EN 2985
+#define MACH_TYPE_WASABI 2986
#define MACH_TYPE_MX50_RDP 2988
#define MACH_TYPE_UNIVERSAL_C210 2989
#define MACH_TYPE_REAL6410 2990
+#define MACH_TYPE_SPX_SAKURA 2991
+#define MACH_TYPE_IJ3K_2440 2992
+#define MACH_TYPE_OMAP3_BC10 2993
+#define MACH_TYPE_THEBE 2994
+#define MACH_TYPE_RV082 2995
+#define MACH_TYPE_ARMLGUEST 2996
+#define MACH_TYPE_TJINC1000 2997
#define MACH_TYPE_DOCKSTAR 2998
+#define MACH_TYPE_AX8008 2999
+#define MACH_TYPE_GNET_SGCE 3000
+#define MACH_TYPE_PXWNAS_500_1000 3001
+#define MACH_TYPE_EA20 3002
+#define MACH_TYPE_AWM2 3003
#define MACH_TYPE_TI8148EVM 3004
#define MACH_TYPE_SEABOARD 3005
+#define MACH_TYPE_LINKSTATION_CHLV2 3006
+#define MACH_TYPE_TERA_PRO2_RACK 3007
+#define MACH_TYPE_RUBYS 3008
+#define MACH_TYPE_AQUARIUS 3009
#define MACH_TYPE_MX53_ARD 3010
#define MACH_TYPE_MX53_SMD 3011
+#define MACH_TYPE_LSWXL 3012
+#define MACH_TYPE_DOVE_AVNG_V3 3013
+#define MACH_TYPE_SDI_ESS_9263 3014
+#define MACH_TYPE_JOCPU550 3015
#define MACH_TYPE_MSM8X60_RUMI3 3016
#define MACH_TYPE_MSM8X60_FFA 3017
+#define MACH_TYPE_YANOMAMI 3018
+#define MACH_TYPE_GTA04 3019
#define MACH_TYPE_CM_A510 3020
+#define MACH_TYPE_OMAP3_RFS200 3021
+#define MACH_TYPE_KX33XX 3022
+#define MACH_TYPE_PTX7510 3023
+#define MACH_TYPE_TOP9000 3024
+#define MACH_TYPE_TEENOTE 3025
+#define MACH_TYPE_TS3 3026
+#define MACH_TYPE_A0 3027
+#define MACH_TYPE_FSM9XXX_SURF 3028
+#define MACH_TYPE_FSM9XXX_FFA 3029
+#define MACH_TYPE_FRRHWCDMA60W 3030
+#define MACH_TYPE_REMUS 3031
+#define MACH_TYPE_AT91CAP7XDK 3032
+#define MACH_TYPE_AT91CAP7STK 3033
+#define MACH_TYPE_KT_SBC_SAM9_1 3034
+#define MACH_TYPE_ARMADA_XP_DB 3036
+#define MACH_TYPE_SPDM 3037
+#define MACH_TYPE_GTIB 3038
+#define MACH_TYPE_DGM3240 3039
+#define MACH_TYPE_ATLAS_I_LPE 3040
+#define MACH_TYPE_HTCMEGA 3041
+#define MACH_TYPE_TRICORDER 3042
#define MACH_TYPE_TX28 3043
+#define MACH_TYPE_BSTBRD 3044
+#define MACH_TYPE_PWB3090 3045
+#define MACH_TYPE_IDEA6410 3046
+#define MACH_TYPE_QBC9263 3047
+#define MACH_TYPE_BORABORA 3048
+#define MACH_TYPE_VALDEZ 3049
+#define MACH_TYPE_LS9G20 3050
+#define MACH_TYPE_MIOS_V1 3051
+#define MACH_TYPE_S5PC110_CRESPO 3052
+#define MACH_TYPE_CONTROLTEK9G20 3053
+#define MACH_TYPE_TIN307 3054
+#define MACH_TYPE_TIN510 3055
+#define MACH_TYPE_EP3517 3056
+#define MACH_TYPE_BLUECHEESE 3057
+#define MACH_TYPE_TEM3X30 3058
+#define MACH_TYPE_HARVEST_DESOTO 3059
+#define MACH_TYPE_MSM8X60_QRDC 3060
+#define MACH_TYPE_SPEAR900 3061
#define MACH_TYPE_PCONTROL_G20 3062
+#define MACH_TYPE_RDSTOR 3063
+#define MACH_TYPE_USDLOADER 3064
+#define MACH_TYPE_TSOPLOADER 3065
+#define MACH_TYPE_KRONOS 3066
+#define MACH_TYPE_FFCORE 3067
+#define MACH_TYPE_MONE 3068
+#define MACH_TYPE_UNIT2S 3069
+#define MACH_TYPE_ACER_A5 3070
+#define MACH_TYPE_ETHERPRO_ISP 3071
+#define MACH_TYPE_STRETCHS7000 3072
+#define MACH_TYPE_P87_SMARTSIM 3073
+#define MACH_TYPE_TULIP 3074
+#define MACH_TYPE_SUNFLOWER 3075
+#define MACH_TYPE_RIB 3076
+#define MACH_TYPE_CLOD 3077
+#define MACH_TYPE_RUMP 3078
+#define MACH_TYPE_TENDERLOIN 3079
+#define MACH_TYPE_SHORTLOIN 3080
+#define MACH_TYPE_ANTARES 3082
+#define MACH_TYPE_WB40N 3083
+#define MACH_TYPE_HERRING 3084
+#define MACH_TYPE_NAXY400 3085
+#define MACH_TYPE_NAXY1200 3086
#define MACH_TYPE_VPR200 3087
+#define MACH_TYPE_BUG20 3088
+#define MACH_TYPE_GOFLEXNET 3089
#define MACH_TYPE_TORBRECK 3090
+#define MACH_TYPE_SAARB_MG1 3091
+#define MACH_TYPE_CALLISTO 3092
+#define MACH_TYPE_MULTHSU 3093
+#define MACH_TYPE_SALUDA 3094
+#define MACH_TYPE_PEMP_OMAP3_APOLLO 3095
+#define MACH_TYPE_VC0718 3096
+#define MACH_TYPE_MVBLX 3097
+#define MACH_TYPE_INHAND_APEIRON 3098
+#define MACH_TYPE_INHAND_FURY 3099
+#define MACH_TYPE_INHAND_SIREN 3100
+#define MACH_TYPE_HDNVP 3101
+#define MACH_TYPE_SOFTWINNER 3102
#define MACH_TYPE_PRIMA2_EVB 3103
+#define MACH_TYPE_NAS6210 3104
+#define MACH_TYPE_UNISDEV 3105
+#define MACH_TYPE_SBCA11 3106
+#define MACH_TYPE_SAGA 3107
+#define MACH_TYPE_NS_K330 3108
+#define MACH_TYPE_TANNA 3109
+#define MACH_TYPE_IMATE8502 3110
+#define MACH_TYPE_ASPEN 3111
+#define MACH_TYPE_DAINTREE_CWAC 3112
+#define MACH_TYPE_ZMX25 3113
+#define MACH_TYPE_MAPLE1 3114
+#define MACH_TYPE_QSD8X72_SURF 3115
+#define MACH_TYPE_QSD8X72_FFA 3116
+#define MACH_TYPE_ABILENE 3117
+#define MACH_TYPE_EIGEN_TTR 3118
+#define MACH_TYPE_IOMEGA_IX2_200 3119
+#define MACH_TYPE_CORETEC_VCX7400 3120
+#define MACH_TYPE_SANTIAGO 3121
+#define MACH_TYPE_MX257SOL 3122
+#define MACH_TYPE_STRASBOURG 3123
+#define MACH_TYPE_MSM8X60_FLUID 3124
+#define MACH_TYPE_SMARTQV5 3125
+#define MACH_TYPE_SMARTQV3 3126
+#define MACH_TYPE_SMARTQV7 3127
#define MACH_TYPE_PAZ00 3128
#define MACH_TYPE_ACMENETUSFOXG20 3129
+#define MACH_TYPE_FWBD_0404 3131
+#define MACH_TYPE_HDGU 3132
+#define MACH_TYPE_PYRAMID 3133
+#define MACH_TYPE_EPIPHAN 3134
+#define MACH_TYPE_OMAP_BENDER 3135
+#define MACH_TYPE_GURNARD 3136
+#define MACH_TYPE_GTL_IT5100 3137
+#define MACH_TYPE_BCM2708 3138
+#define MACH_TYPE_MX51_GGC 3139
+#define MACH_TYPE_SHARESPACE 3140
+#define MACH_TYPE_HABA_KNX_EXPLORER 3141
+#define MACH_TYPE_SIMTEC_KIRKMOD 3142
+#define MACH_TYPE_CRUX 3143
+#define MACH_TYPE_MX51_BRAVO 3144
+#define MACH_TYPE_CHARON 3145
+#define MACH_TYPE_PICOCOM3 3146
+#define MACH_TYPE_PICOCOM4 3147
+#define MACH_TYPE_SERRANO 3148
+#define MACH_TYPE_DOUBLESHOT 3149
+#define MACH_TYPE_EVSY 3150
+#define MACH_TYPE_HUASHAN 3151
+#define MACH_TYPE_LAUSANNE 3152
+#define MACH_TYPE_EMERALD 3153
+#define MACH_TYPE_TQMA35 3154
+#define MACH_TYPE_MARVEL 3155
+#define MACH_TYPE_MANUAE 3156
+#define MACH_TYPE_CHACHA 3157
+#define MACH_TYPE_LEMON 3158
+#define MACH_TYPE_CSC 3159
+#define MACH_TYPE_GIRA_KNXIP_ROUTER 3160
+#define MACH_TYPE_T20 3161
+#define MACH_TYPE_HDMINI 3162
+#define MACH_TYPE_SCIPHONE_G2 3163
+#define MACH_TYPE_EXPRESS 3164
+#define MACH_TYPE_EXPRESS_KT 3165
+#define MACH_TYPE_MAXIMASP 3166
+#define MACH_TYPE_NITROGEN_IMX51 3167
+#define MACH_TYPE_NITROGEN_IMX53 3168
+#define MACH_TYPE_SUNFIRE 3169
+#define MACH_TYPE_AROWANA 3170
+#define MACH_TYPE_TEGRA_DAYTONA 3171
+#define MACH_TYPE_TEGRA_SWORDFISH 3172
+#define MACH_TYPE_EDISON 3173
+#define MACH_TYPE_SVP8500V1 3174
+#define MACH_TYPE_SVP8500V2 3175
+#define MACH_TYPE_SVP5500 3176
+#define MACH_TYPE_B5500 3177
+#define MACH_TYPE_S5500 3178
+#define MACH_TYPE_ICON 3179
+#define MACH_TYPE_ELEPHANT 3180
+#define MACH_TYPE_SHOOTER 3182
+#define MACH_TYPE_SPADE_LTE 3183
+#define MACH_TYPE_PHILHWANI 3184
+#define MACH_TYPE_GSNCOMM 3185
+#define MACH_TYPE_STRASBOURG_A2 3186
+#define MACH_TYPE_MMM 3187
+#define MACH_TYPE_DAVINCI_DM365_BV 3188
#define MACH_TYPE_AG5EVM 3189
+#define MACH_TYPE_SC575PLC 3190
+#define MACH_TYPE_SC575IPC 3191
+#define MACH_TYPE_OMAP3_TDM3730 3192
+#define MACH_TYPE_TOP9000_EVAL 3194
+#define MACH_TYPE_TOP9000_SU 3195
+#define MACH_TYPE_UTM300 3196
+#define MACH_TYPE_TSUNAGI 3197
+#define MACH_TYPE_TS75XX 3198
+#define MACH_TYPE_TS47XX 3200
+#define MACH_TYPE_DA850_K5 3201
+#define MACH_TYPE_AX502 3202
+#define MACH_TYPE_IGEP0032 3203
+#define MACH_TYPE_ANTERO 3204
+#define MACH_TYPE_SYNERGY 3205
#define MACH_TYPE_ICS_IF_VOIP 3206
#define MACH_TYPE_WLF_CRAGG_6410 3207
+#define MACH_TYPE_PUNICA 3208
#define MACH_TYPE_TRIMSLICE 3209
+#define MACH_TYPE_MX27_WMULTRA 3210
+#define MACH_TYPE_MACKEREL 3211
+#define MACH_TYPE_FA9X27 3213
+#define MACH_TYPE_NS2816TB 3214
+#define MACH_TYPE_NS2816_NTPAD 3215
+#define MACH_TYPE_NS2816_NTNB 3216
#define MACH_TYPE_KAEN 3217
+#define MACH_TYPE_NV1000 3218
+#define MACH_TYPE_NUC950TS 3219
#define MACH_TYPE_NOKIA_RM680 3220
+#define MACH_TYPE_AST2200 3221
+#define MACH_TYPE_LEAD 3222
+#define MACH_TYPE_UNINO1 3223
+#define MACH_TYPE_GREECO 3224
+#define MACH_TYPE_VERDI 3225
+#define MACH_TYPE_DM6446_ADBOX 3226
+#define MACH_TYPE_QUAD_SALSA 3227
+#define MACH_TYPE_ABB_GMA_1_1 3228
+#define MACH_TYPE_SVCID 3229
#define MACH_TYPE_MSM8960_SIM 3230
#define MACH_TYPE_MSM8960_RUMI3 3231
+#define MACH_TYPE_ICON_G 3232
+#define MACH_TYPE_MB3 3233
#define MACH_TYPE_GSIA18S 3234
+#define MACH_TYPE_PIVICC 3235
+#define MACH_TYPE_PCM048 3236
+#define MACH_TYPE_DDS 3237
+#define MACH_TYPE_CHALTEN_XA1 3238
+#define MACH_TYPE_TS48XX 3239
+#define MACH_TYPE_TONGA2_TFTTIMER 3240
+#define MACH_TYPE_WHISTLER 3241
+#define MACH_TYPE_ASL_PHOENIX 3242
+#define MACH_TYPE_AT91SAM9263OTLITE 3243
+#define MACH_TYPE_DDPLUG 3244
+#define MACH_TYPE_D2PLUG 3245
+#define MACH_TYPE_KZM9D 3246
+#define MACH_TYPE_VERDI_LTE 3247
+#define MACH_TYPE_NANOZOOM 3248
+#define MACH_TYPE_DM3730_SOM_LV 3249
+#define MACH_TYPE_DM3730_TORPEDO 3250
+#define MACH_TYPE_ANCHOVY 3251
+#define MACH_TYPE_RE2REV20 3253
+#define MACH_TYPE_RE2REV21 3254
+#define MACH_TYPE_CNS21XX 3255
+#define MACH_TYPE_RIDER 3257
+#define MACH_TYPE_NSK330 3258
+#define MACH_TYPE_CNS2133EVB 3259
+#define MACH_TYPE_Z3_816X_MOD 3260
+#define MACH_TYPE_Z3_814X_MOD 3261
+#define MACH_TYPE_BEECT 3262
+#define MACH_TYPE_DMA_THUNDERBUG 3263
+#define MACH_TYPE_OMN_AT91SAM9G20 3264
+#define MACH_TYPE_MX25_E2S_UC 3265
+#define MACH_TYPE_MIONE 3266
+#define MACH_TYPE_TOP9000_TCU 3267
+#define MACH_TYPE_TOP9000_BSL 3268
+#define MACH_TYPE_KINGDOM 3269
+#define MACH_TYPE_ARMADILLO460 3270
+#define MACH_TYPE_LQ2 3271
+#define MACH_TYPE_SWEDA_TMS2 3272
#define MACH_TYPE_MX53_LOCO 3273
+#define MACH_TYPE_ACER_A8 3275
+#define MACH_TYPE_ACER_GAUGUIN 3276
+#define MACH_TYPE_GUPPY 3277
+#define MACH_TYPE_MX61_ARD 3278
+#define MACH_TYPE_TX53 3279
+#define MACH_TYPE_OMAPL138_CASE_A3 3280
+#define MACH_TYPE_UEMD 3281
+#define MACH_TYPE_CCWMX51MUT 3282
+#define MACH_TYPE_ROCKHOPPER 3283
+#define MACH_TYPE_ENCORE 3284
+#define MACH_TYPE_HKDKC100 3285
+#define MACH_TYPE_TS42XX 3286
+#define MACH_TYPE_AEBL 3287
#define MACH_TYPE_WARIO 3288
+#define MACH_TYPE_GFS_SPM 3289
#define MACH_TYPE_CM_T3730 3290
+#define MACH_TYPE_ISC3 3291
+#define MACH_TYPE_RASCAL 3292
#define MACH_TYPE_HREFV60 3293
+#define MACH_TYPE_TPT_2_0 3294
+#define MACH_TYPE_PYRAMID_TD 3295
+#define MACH_TYPE_SPLENDOR 3296
+#define MACH_TYPE_GUF_PLANET 3297
+#define MACH_TYPE_MSM8X60_QT 3298
+#define MACH_TYPE_HTC_HD_MINI 3299
+#define MACH_TYPE_ATHENE 3300
+#define MACH_TYPE_DEEP_R_EK_1 3301
+#define MACH_TYPE_VIVOW_CT 3302
+#define MACH_TYPE_NERY_1000 3303
+#define MACH_TYPE_RFL109145_SSRV 3304
+#define MACH_TYPE_NMH 3305
+#define MACH_TYPE_WN802T 3306
+#define MACH_TYPE_DRAGONET 3307
+#define MACH_TYPE_GENEVA_B 3308
+#define MACH_TYPE_AT91SAM9263DESK16L 3309
+#define MACH_TYPE_BCMHANA_SV 3310
+#define MACH_TYPE_BCMHANA_TABLET 3311
+#define MACH_TYPE_KOI 3312
+#define MACH_TYPE_TS4800 3313
+#define MACH_TYPE_TQMA9263 3314
+#define MACH_TYPE_HOLIDAY 3315
+#define MACH_TYPE_DMA6410 3316
+#define MACH_TYPE_PCATS_OVERLAY 3317
+#define MACH_TYPE_HWGW6410 3318
+#define MACH_TYPE_SHENZHOU 3319
+#define MACH_TYPE_CWME9210 3320
+#define MACH_TYPE_CWME9210JS 3321
+#define MACH_TYPE_PGS_SITARA 3322
+#define MACH_TYPE_COLIBRI_TEGRA2 3323
+#define MACH_TYPE_W21 3324
+#define MACH_TYPE_POLYSAT1 3325
+#define MACH_TYPE_DATAWAY 3326
+#define MACH_TYPE_COBRAL138 3327
+#define MACH_TYPE_ROVERPCS8 3328
+#define MACH_TYPE_MARVELC 3329
+#define MACH_TYPE_NAVEFIHID 3330
+#define MACH_TYPE_DM365_CV100 3331
+#define MACH_TYPE_ABLE 3332
+#define MACH_TYPE_LEGACY 3333
+#define MACH_TYPE_ICONG 3334
+#define MACH_TYPE_ROVER_G8 3335
+#define MACH_TYPE_T5388P 3336
+#define MACH_TYPE_DINGO 3337
+#define MACH_TYPE_GOFLEXHOME 3338
+#define MACH_TYPE_LANREADYFN511 3340
+#define MACH_TYPE_OMAP3_BAIA 3341
+#define MACH_TYPE_OMAP3SMARTDISPLAY 3342
+#define MACH_TYPE_XILINX 3343
+#define MACH_TYPE_A2F 3344
+#define MACH_TYPE_SKY25 3345
+#define MACH_TYPE_CCMX53 3346
+#define MACH_TYPE_CCMX53JS 3347
+#define MACH_TYPE_CCWMX53 3348
+#define MACH_TYPE_CCWMX53JS 3349
+#define MACH_TYPE_FRISMS 3350
+#define MACH_TYPE_MSM7X27A_FFA 3351
+#define MACH_TYPE_MSM7X27A_SURF 3352
+#define MACH_TYPE_MSM7X27A_RUMI3 3353
+#define MACH_TYPE_DIMMSAM9G20 3354
+#define MACH_TYPE_DIMM_IMX28 3355
+#define MACH_TYPE_AMK_A4 3356
+#define MACH_TYPE_GNET_SGME 3357
+#define MACH_TYPE_SHOOTER_U 3358
+#define MACH_TYPE_VMX53 3359
+#define MACH_TYPE_RHINO 3360
#define MACH_TYPE_ARMLEX4210 3361
+#define MACH_TYPE_SWARCOEXTMODEM 3362
#define MACH_TYPE_SNOWBALL 3363
+#define MACH_TYPE_PCM049 3364
+#define MACH_TYPE_VIGOR 3365
+#define MACH_TYPE_OSLO_AMUNDSEN 3366
+#define MACH_TYPE_GSL_DIAMOND 3367
+#define MACH_TYPE_CV2201 3368
+#define MACH_TYPE_CV2202 3369
+#define MACH_TYPE_CV2203 3370
+#define MACH_TYPE_VIT_IBOX 3371
+#define MACH_TYPE_DM6441_ESP 3372
+#define MACH_TYPE_AT91SAM9X5EK 3373
+#define MACH_TYPE_LIBRA 3374
+#define MACH_TYPE_EASYCRRH 3375
+#define MACH_TYPE_TRIPEL 3376
+#define MACH_TYPE_ENDIAN_MINI 3377
#define MACH_TYPE_XILINX_EP107 3378
#define MACH_TYPE_NURI 3379
+#define MACH_TYPE_JANUS 3380
+#define MACH_TYPE_DDNAS 3381
+#define MACH_TYPE_TAG 3382
+#define MACH_TYPE_TAGW 3383
+#define MACH_TYPE_NITROGEN_VM_IMX51 3384
+#define MACH_TYPE_VIPRINET 3385
+#define MACH_TYPE_BOCKW 3386
+#define MACH_TYPE_EVA2000 3387
+#define MACH_TYPE_STEELYARD 3388
+#define MACH_TYPE_LPC2468OEM 3389
+#define MACH_TYPE_MACH_SDH001 3390
+#define MACH_TYPE_LPC2478MICROBLOX 3391
+#define MACH_TYPE_NSSLSBOARD 3392
+#define MACH_TYPE_GENEVA_B5 3393
+#define MACH_TYPE_SPEAR1340 3394
+#define MACH_TYPE_REXMAS 3395
+#define MACH_TYPE_MSM8960_CDP 3396
+#define MACH_TYPE_MSM8960_MDP 3397
+#define MACH_TYPE_MSM8960_FLUID 3398
+#define MACH_TYPE_MSM8960_APQ 3399
+#define MACH_TYPE_HELIOS_V2 3400
+#define MACH_TYPE_MIF10P 3401
+#define MACH_TYPE_IAM28 3402
+#define MACH_TYPE_PICASSO 3403
+#define MACH_TYPE_MR301A 3404
+#define MACH_TYPE_NOTLE 3405
+#define MACH_TYPE_EELX2 3406
+#define MACH_TYPE_MOON 3407
+#define MACH_TYPE_RUBY 3408
+#define MACH_TYPE_GOLDENGATE 3409
+#define MACH_TYPE_CTBU_GEN2 3410
+#define MACH_TYPE_KMP_AM17_01 3411
+#define MACH_TYPE_WTPLUG 3412
+#define MACH_TYPE_MX27SU2 3413
+#define MACH_TYPE_NB31 3414
+#define MACH_TYPE_HJSDU 3415
+#define MACH_TYPE_TD3_REV1 3416
+#define MACH_TYPE_EAG_CI4000 3417
+#define MACH_TYPE_NET5BIG_NAND_V2 3418
+#define MACH_TYPE_CPX2 3419
+#define MACH_TYPE_NET2BIG_NAND_V2 3420
+#define MACH_TYPE_ECUV5 3421
+#define MACH_TYPE_HSGX6D 3422
+#define MACH_TYPE_DAWAD7 3423
+#define MACH_TYPE_SAM9REPEATER 3424
+#define MACH_TYPE_GT_I5700 3425
+#define MACH_TYPE_CTERA_PLUG_C2 3426
+#define MACH_TYPE_MARVELCT 3427
+#define MACH_TYPE_AG11005 3428
+#define MACH_TYPE_OMAP_BLAZE 3429
+#define MACH_TYPE_VANGOGH 3430
+#define MACH_TYPE_MATRIX505 3431
+#define MACH_TYPE_OCE_NIGMA 3432
+#define MACH_TYPE_T55 3433
+#define MACH_TYPE_BIO3K 3434
+#define MACH_TYPE_EXPRESSCT 3435
+#define MACH_TYPE_CARDHU 3436
+#define MACH_TYPE_ARUBA 3437
+#define MACH_TYPE_BONAIRE 3438
+#define MACH_TYPE_NUC700EVB 3439
+#define MACH_TYPE_NUC710EVB 3440
+#define MACH_TYPE_NUC740EVB 3441
+#define MACH_TYPE_NUC745EVB 3442
+#define MACH_TYPE_TRANSCEDE 3443
+#define MACH_TYPE_MORA 3444
+#define MACH_TYPE_NDA_EVM 3445
+#define MACH_TYPE_TIMU 3446
+#define MACH_TYPE_EXPRESSH 3447
+#define MACH_TYPE_VERIDIS_A300 3448
+#define MACH_TYPE_DM368_LEOPARD 3449
+#define MACH_TYPE_OMAP_MCOP 3450
+#define MACH_TYPE_TRITIP 3451
+#define MACH_TYPE_SM1K 3452
+#define MACH_TYPE_MONCH 3453
+#define MACH_TYPE_CURACAO 3454
#define MACH_TYPE_ORIGEN 3455
+#define MACH_TYPE_EPC10 3456
+#define MACH_TYPE_SGH_I740 3457
+#define MACH_TYPE_TUNA 3458
+#define MACH_TYPE_MX51_TULIP 3459
+#define MACH_TYPE_MX51_ASTER7 3460
+#define MACH_TYPE_ACRO37XBRD 3461
+#define MACH_TYPE_ELKE 3462
+#define MACH_TYPE_SBC6000X 3463
+#define MACH_TYPE_R1801E 3464
+#define MACH_TYPE_H1600 3465
+#define MACH_TYPE_MINI210 3466
+#define MACH_TYPE_MINI8168 3467
+#define MACH_TYPE_PC7308 3468
+#define MACH_TYPE_GE863 3469
+#define MACH_TYPE_KMM2M01 3470
+#define MACH_TYPE_MX51EREBUS 3471
+#define MACH_TYPE_WM8650REFBOARD 3472
+#define MACH_TYPE_TUXRAIL 3473
+#define MACH_TYPE_ARTHUR 3474
+#define MACH_TYPE_DOORBOY 3475
+#define MACH_TYPE_XARINA 3476
+#define MACH_TYPE_ROVERX7 3477
+#define MACH_TYPE_SDVR 3478
+#define MACH_TYPE_ACER_MAYA 3479
+#define MACH_TYPE_PICO 3480
+#define MACH_TYPE_CWMX233 3481
+#define MACH_TYPE_CWAM1808 3482
+#define MACH_TYPE_CWDM365 3483
+#define MACH_TYPE_MX51_MORAY 3484
+#define MACH_TYPE_THALES_CBC 3485
+#define MACH_TYPE_BLUEPOINT 3486
+#define MACH_TYPE_DIR665 3487
+#define MACH_TYPE_ACMEROVER1 3488
+#define MACH_TYPE_SHOOTER_CT 3489
+#define MACH_TYPE_BLISS 3490
+#define MACH_TYPE_BLISSC 3491
+#define MACH_TYPE_THALES_ADC 3492
+#define MACH_TYPE_UBISYS_P9D_EVP 3493
+#define MACH_TYPE_ATDGP318 3494
+#define MACH_TYPE_DMA210U 3495
+#define MACH_TYPE_EM_T3 3496
+#define MACH_TYPE_HTX3250 3497
+#define MACH_TYPE_G50 3498
+#define MACH_TYPE_ECO5 3499
+#define MACH_TYPE_WINTERGRASP 3500
+#define MACH_TYPE_PURO 3501
+#define MACH_TYPE_SHOOTER_K 3502
#define MACH_TYPE_NSPIRE 3503
+#define MACH_TYPE_MICKXX 3504
+#define MACH_TYPE_LXMB 3505
+#define MACH_TYPE_TMDXSCBP6616X 3506
+#define MACH_TYPE_ADAM 3507
+#define MACH_TYPE_B1004 3508
+#define MACH_TYPE_OBOEA 3509
+#define MACH_TYPE_A1015 3510
+#define MACH_TYPE_ROBIN_VBDT30 3511
+#define MACH_TYPE_TEGRA_ENTERPRISE 3512
+#define MACH_TYPE_RFL108200_MK10 3513
+#define MACH_TYPE_RFL108300_MK16 3514
+#define MACH_TYPE_ROVER_V7 3515
+#define MACH_TYPE_MIPHONE 3516
+#define MACH_TYPE_FEMTOBTS 3517
+#define MACH_TYPE_MONOPOLI 3518
+#define MACH_TYPE_BOSS 3519
+#define MACH_TYPE_DAVINCI_DM368_VTAM 3520
+#define MACH_TYPE_CLCON 3521
#define MACH_TYPE_NOKIA_RM696 3522
+#define MACH_TYPE_TAHITI 3523
+#define MACH_TYPE_FIGHTER 3524
+#define MACH_TYPE_SGH_I710 3525
+#define MACH_TYPE_INTEGREPROSCB 3526
+#define MACH_TYPE_MONZA 3527
+#define MACH_TYPE_CALIMAIN 3528
+#define MACH_TYPE_MX6Q_SABREAUTO 3529
+#define MACH_TYPE_GMA01X 3530
+#define MACH_TYPE_SBC51 3531
+#define MACH_TYPE_FIT 3532
+#define MACH_TYPE_STEELHEAD 3533
+#define MACH_TYPE_PANTHER 3534
+#define MACH_TYPE_MSM8960_LIQUID 3535
+#define MACH_TYPE_LEXIKONCT 3536
+#define MACH_TYPE_NS2816_STB 3537
+#define MACH_TYPE_SEI_MM2_LPC3250 3538
+#define MACH_TYPE_CMIMX53 3539
+#define MACH_TYPE_SANDWICH 3540
+#define MACH_TYPE_CHIEF 3541
+#define MACH_TYPE_POGO_E02 3542
#define MACH_TYPE_MIKRAP_X168 3543
+#define MACH_TYPE_HTCMOZART 3544
+#define MACH_TYPE_HTCGOLD 3545
+#define MACH_TYPE_MT72XX 3546
+#define MACH_TYPE_MX51_IVY 3547
+#define MACH_TYPE_MX51_LVD 3548
+#define MACH_TYPE_OMAP3_WISER2 3549
+#define MACH_TYPE_DREAMPLUG 3550
+#define MACH_TYPE_COBAS_C_111 3551
+#define MACH_TYPE_COBAS_U_411 3552
+#define MACH_TYPE_HSSD 3553
+#define MACH_TYPE_IOM35X 3554
+#define MACH_TYPE_PSOM_OMAP 3555
+#define MACH_TYPE_IPHONE_2G 3556
+#define MACH_TYPE_IPHONE_3G 3557
+#define MACH_TYPE_IPOD_TOUCH_1G 3558
+#define MACH_TYPE_PHAROS_TPC 3559
+#define MACH_TYPE_MX53_HYDRA 3560
+#define MACH_TYPE_NS2816_DEV_BOARD 3561
+#define MACH_TYPE_IPHONE_3GS 3562
+#define MACH_TYPE_IPHONE_4 3563
+#define MACH_TYPE_IPOD_TOUCH_4G 3564
+#define MACH_TYPE_DRAGON_E1100 3565
+#define MACH_TYPE_TOPSIDE 3566
+#define MACH_TYPE_IRISIII 3567
#define MACH_TYPE_DETO_MACARM9 3568
+#define MACH_TYPE_ETI_D1 3569
+#define MACH_TYPE_SOM3530SDK 3570
+#define MACH_TYPE_OC_ENGINE 3571
+#define MACH_TYPE_APQ8064_SIM 3572
+#define MACH_TYPE_ALPS 3575
+#define MACH_TYPE_TNY_T3730 3576
+#define MACH_TYPE_GERYON_NFE 3577
+#define MACH_TYPE_NS2816_REF_BOARD 3578
+#define MACH_TYPE_SILVERSTONE 3579
+#define MACH_TYPE_MTT2440 3580
+#define MACH_TYPE_YNICDB 3581
+#define MACH_TYPE_BCT 3582
+#define MACH_TYPE_TUSCAN 3583
+#define MACH_TYPE_XBT_SAM9G45 3584
+#define MACH_TYPE_ENBW_CMC 3585
+#define MACH_TYPE_APQ8060_DRAGON 3586
+#define MACH_TYPE_CH104MX257 3587
+#define MACH_TYPE_OPENPRI 3588
+#define MACH_TYPE_AM335XEVM 3589
+#define MACH_TYPE_PICODMB 3590
+#define MACH_TYPE_WALUIGI 3591
+#define MACH_TYPE_PUNICAG7 3592
+#define MACH_TYPE_IPAD_1G 3593
+#define MACH_TYPE_APPLETV_2G 3594
+#define MACH_TYPE_MACH_ECOG45 3595
+#define MACH_TYPE_AIT_CAM_ENC_4XX 3596
+#define MACH_TYPE_RUNNYMEDE 3597
+#define MACH_TYPE_PLAY 3598
+#define MACH_TYPE_HW90260 3599
+#define MACH_TYPE_TAGH 3600
+#define MACH_TYPE_FILBERT 3601
+#define MACH_TYPE_GETINGE_NETCOMV3 3602
+#define MACH_TYPE_CW20 3603
+#define MACH_TYPE_CINEMA 3604
+#define MACH_TYPE_CINEMA_TEA 3605
+#define MACH_TYPE_CINEMA_COFFEE 3606
+#define MACH_TYPE_CINEMA_JUICE 3607
+#define MACH_TYPE_THEPAD 3608
+#define MACH_TYPE_MX53_MIRAGE2 3609
+#define MACH_TYPE_MX53_EFIKASB 3610
+#define MACH_TYPE_STM_B2000 3612
#define MACH_TYPE_M28EVK 3613
+#define MACH_TYPE_PDA 3614
+#define MACH_TYPE_MERAKI_MR58 3615
#define MACH_TYPE_KOTA2 3616
+#define MACH_TYPE_LETCOOL 3617
+#define MACH_TYPE_MX27IAT 3618
+#define MACH_TYPE_APOLLO_TD 3619
+#define MACH_TYPE_ARENA 3620
+#define MACH_TYPE_GSNGATEWAY 3621
+#define MACH_TYPE_LF2000 3622
#define MACH_TYPE_BONITO 3623
+#define MACH_TYPE_ASYMPTOTE 3624
+#define MACH_TYPE_BST2BRD 3625
+#define MACH_TYPE_TX335S 3626
+#define MACH_TYPE_PELCO_TESLA 3627
+#define MACH_TYPE_RRHTESTPLAT 3628
+#define MACH_TYPE_VIDTONIC_PRO 3629
+#define MACH_TYPE_PL_APOLLO 3630
+#define MACH_TYPE_PL_PHOENIX 3631
+#define MACH_TYPE_M28CU3 3632
+#define MACH_TYPE_VVBOX_HD 3633
+#define MACH_TYPE_COREWARE_SAM9260_ 3634
+#define MACH_TYPE_MARMADUKE 3635
+#define MACH_TYPE_AMG_XLCORE_CAMERA 3636
#define MACH_TYPE_OMAP3_EGF 3637
#define MACH_TYPE_SMDK4212 3638
+#define MACH_TYPE_DNP9200 3639
+#define MACH_TYPE_TF101 3640
+#define MACH_TYPE_OMAP3SILVIO 3641
+#define MACH_TYPE_PICASSO2 3642
+#define MACH_TYPE_VANGOGH2 3643
+#define MACH_TYPE_OLPC_XO_1_75 3644
+#define MACH_TYPE_GX400 3645
+#define MACH_TYPE_GS300 3646
+#define MACH_TYPE_ACER_A9 3647
+#define MACH_TYPE_VIVOW_EVM 3648
+#define MACH_TYPE_VELOCE_CXQ 3649
+#define MACH_TYPE_VELOCE_CXM 3650
+#define MACH_TYPE_P1852 3651
+#define MACH_TYPE_NAXY100 3652
+#define MACH_TYPE_TAISHAN 3653
+#define MACH_TYPE_TOUCHLINK 3654
+#define MACH_TYPE_STM32F103ZE 3655
+#define MACH_TYPE_MCX 3656
+#define MACH_TYPE_STM_NMHDK_FLI7610 3657
+#define MACH_TYPE_TOP28X 3658
+#define MACH_TYPE_OKL4VP_MICROVISOR 3659
+#define MACH_TYPE_POP 3660
+#define MACH_TYPE_LAYER 3661
+#define MACH_TYPE_TRONDHEIM 3662
+#define MACH_TYPE_EVA 3663
+#define MACH_TYPE_TRUST_TAURUS 3664
+#define MACH_TYPE_NS2816_HUASHAN 3665
+#define MACH_TYPE_NS2816_YANGCHENG 3666
+#define MACH_TYPE_P852 3667
+#define MACH_TYPE_FLEA3 3668
+#define MACH_TYPE_BOWFIN 3669
+#define MACH_TYPE_MV88DE3100 3670
+#define MACH_TYPE_PIA_AM35X 3671
+#define MACH_TYPE_CEDAR 3672
+#define MACH_TYPE_PICASSO_E 3673
+#define MACH_TYPE_SAMSUNG_E60 3674
+#define MACH_TYPE_MDM9615 3675
+#define MACH_TYPE_SDVR_MINI 3676
+#define MACH_TYPE_OMAP3_IJ3K 3677
+#define MACH_TYPE_MODASMC1 3678
+#define MACH_TYPE_APQ8064_RUMI3 3679
+#define MACH_TYPE_MATRIX506 3680
+#define MACH_TYPE_MSM9615_MTP 3681
+#define MACH_TYPE_DM36X_SPAWNDC 3682
+#define MACH_TYPE_SFF792 3683
+#define MACH_TYPE_AM335XIAEVM 3684
+#define MACH_TYPE_G3C2440 3685
+#define MACH_TYPE_TION270 3686
+#define MACH_TYPE_W22Q7ARM02 3687
+#define MACH_TYPE_OMAP_CAT 3688
+#define MACH_TYPE_AT91SAM9N12EK 3689
+#define MACH_TYPE_MORRISON 3690
+#define MACH_TYPE_SVDU 3691
+#define MACH_TYPE_LPP01 3692
+#define MACH_TYPE_UBC283 3693
+#define MACH_TYPE_ZEPPELIN 3694
+#define MACH_TYPE_MOTUS 3695
+#define MACH_TYPE_NEOMAINBOARD 3696
+#define MACH_TYPE_DEVKIT3250 3697
+#define MACH_TYPE_DEVKIT7000 3698
+#define MACH_TYPE_FMC_UIC 3699
+#define MACH_TYPE_FMC_DCM 3700
+#define MACH_TYPE_BATWM 3701
+#define MACH_TYPE_ATLAS6CB 3702
+#define MACH_TYPE_QUATTROF 3703
+#define MACH_TYPE_QUATTROU 3704
+#define MACH_TYPE_BLUE 3705
+#define MACH_TYPE_COLORADO 3706
+#define MACH_TYPE_POPC 3707
+#define MACH_TYPE_PROMWAD_JADE 3708
+#define MACH_TYPE_AMP 3709
+#define MACH_TYPE_GNET_AMP 3710
+#define MACH_TYPE_TOQUES 3711
#define MACH_TYPE_APX4DEVKIT 3712
+#define MACH_TYPE_DCT_STORM 3713
+#define MACH_TYPE_Z3 3714
+#define MACH_TYPE_OWL 3715
+#define MACH_TYPE_COGENT_CSB1741 3716
+#define MACH_TYPE_OMAP3 3717
+#define MACH_TYPE_ADILLUSTRA610 3718
+#define MACH_TYPE_ECAFE_NA04 3719
+#define MACH_TYPE_POPCT 3720
+#define MACH_TYPE_OMAP3_HELENA 3721
+#define MACH_TYPE_ACH 3722
+#define MACH_TYPE_MODULE_DTB 3723
+#define MACH_TYPE_RACKBOX 3724
+#define MACH_TYPE_OSLO_ELISABETH 3725
+#define MACH_TYPE_TT01 3726
+#define MACH_TYPE_MSM8930_CDP 3727
+#define MACH_TYPE_MSM8930_MTP 3728
+#define MACH_TYPE_MSM8930_FLUID 3729
+#define MACH_TYPE_LTU11 3730
+#define MACH_TYPE_AM1808_SPAWNCO 3731
+#define MACH_TYPE_FLX6410 3732
+#define MACH_TYPE_MX6Q_QSB 3733
+#define MACH_TYPE_MX53_PLT424 3734
+#define MACH_TYPE_JASMINE 3735
+#define MACH_TYPE_L138_OWLBOARD_PLUS 3736
+#define MACH_TYPE_WR21 3737
+#define MACH_TYPE_PEABOY 3739
+#define MACH_TYPE_MX28_PLATO 3740
+#define MACH_TYPE_KACOM2 3741
+#define MACH_TYPE_SLCO 3742
+#define MACH_TYPE_IMX51PICO 3743
+#define MACH_TYPE_GLINK1 3744
+#define MACH_TYPE_DIAMOND 3745
+#define MACH_TYPE_D9000 3746
+#define MACH_TYPE_W5300E01 3747
+#define MACH_TYPE_IM6000 3748
+#define MACH_TYPE_MX51_FRED51 3749
+#define MACH_TYPE_STM32F2 3750
+#define MACH_TYPE_VILLE 3751
+#define MACH_TYPE_PTIP_MURNAU 3752
+#define MACH_TYPE_PTIP_CLASSIC 3753
+#define MACH_TYPE_MX53GRB 3754
+#define MACH_TYPE_GAGARIN 3755
+#define MACH_TYPE_MSM7X27A_QRD1 3756
+#define MACH_TYPE_NAS2BIG 3757
+#define MACH_TYPE_SUPERFEMTO 3758
+#define MACH_TYPE_TEUFEL 3759
+#define MACH_TYPE_DINARA 3760
+#define MACH_TYPE_VANQUISH 3761
+#define MACH_TYPE_ZIPABOX1 3762
+#define MACH_TYPE_U9540 3763
+#define MACH_TYPE_JET 3764
#define MACH_TYPE_SMDK4412 3765
+#define MACH_TYPE_ELITE 3766
+#define MACH_TYPE_SPEAR320_HMI 3767
+#define MACH_TYPE_ONTARIO 3768
+#define MACH_TYPE_MX6Q_SABRELITE 3769
+#define MACH_TYPE_VC200 3770
+#define MACH_TYPE_MSM7625A_FFA 3771
+#define MACH_TYPE_MSM7625A_SURF 3772
+#define MACH_TYPE_BENTHOSSBP 3773
+#define MACH_TYPE_SMDK5210 3774
+#define MACH_TYPE_EMPQ2300 3775
+#define MACH_TYPE_MINIPOS 3776
+#define MACH_TYPE_OMAP5_SEVM 3777
+#define MACH_TYPE_SHELTER 3778
+#define MACH_TYPE_OMAP3_DEVKIT8500 3779
+#define MACH_TYPE_EDGETD 3780
+#define MACH_TYPE_COPPERYARD 3781
+#define MACH_TYPE_EDGE 3782
+#define MACH_TYPE_EDGE_U 3783
+#define MACH_TYPE_EDGE_TD 3784
+#define MACH_TYPE_WDSS 3785
+#define MACH_TYPE_DL_PB25 3786
+#define MACH_TYPE_DSS11 3787
+#define MACH_TYPE_CPA 3788
+#define MACH_TYPE_APTP2000 3789
#define MACH_TYPE_MARZEN 3790
+#define MACH_TYPE_ST_TURBINE 3791
+#define MACH_TYPE_GTL_IT3300 3792
+#define MACH_TYPE_MX6_MULE 3793
+#define MACH_TYPE_V7PXA_DT 3794
+#define MACH_TYPE_V7MMP_DT 3795
+#define MACH_TYPE_DRAGON7 3796
#define MACH_TYPE_KROME 3797
+#define MACH_TYPE_ORATISDANTE 3798
+#define MACH_TYPE_FATHOM 3799
+#define MACH_TYPE_DNS325 3800
+#define MACH_TYPE_SARNEN 3801
+#define MACH_TYPE_UBISYS_G1 3802
+#define MACH_TYPE_MX53_PF1 3803
+#define MACH_TYPE_ASANTI 3804
+#define MACH_TYPE_VOLTA 3805
+#define MACH_TYPE_S5P6450 3806
+#define MACH_TYPE_KNIGHT 3807
+#define MACH_TYPE_BEAGLEBONE 3808
+#define MACH_TYPE_BECKER 3809
+#define MACH_TYPE_FC360 3810
+#define MACH_TYPE_PMI2_XLS 3811
+#define MACH_TYPE_TARANTO 3812
+#define MACH_TYPE_PLUTUX 3813
+#define MACH_TYPE_IPMP_MEDCOM 3814
+#define MACH_TYPE_ABSOLUT 3815
+#define MACH_TYPE_AWPB3 3816
+#define MACH_TYPE_NFP32XX_DT 3817
+#define MACH_TYPE_DL_PB53 3818
+#define MACH_TYPE_ACU_II 3819
+#define MACH_TYPE_AVALON 3820
+#define MACH_TYPE_SPHINX 3821
+#define MACH_TYPE_TITAN_T 3822
+#define MACH_TYPE_HARVEST_BORIS 3823
+#define MACH_TYPE_MACH_MSM7X30_M3S 3824
+#define MACH_TYPE_SMDK5250 3825
+#define MACH_TYPE_IMXT_LITE 3826
+#define MACH_TYPE_IMXT_STD 3827
+#define MACH_TYPE_IMXT_LOG 3828
+#define MACH_TYPE_IMXT_NAV 3829
+#define MACH_TYPE_IMXT_FULL 3830
+#define MACH_TYPE_AG09015 3831
+#define MACH_TYPE_AM3517_MT_VENTOUX 3832
+#define MACH_TYPE_DP1ARM9 3833
+#define MACH_TYPE_PICASSO_M 3834
+#define MACH_TYPE_VIDEO_GADGET 3835
+#define MACH_TYPE_MTT_OM3X 3836
+#define MACH_TYPE_MX6Q_ARM2 3837
+#define MACH_TYPE_PICOSAM9G45 3838
+#define MACH_TYPE_VPM_DM365 3839
+#define MACH_TYPE_BONFIRE 3840
+#define MACH_TYPE_MT2P2D 3841
+#define MACH_TYPE_SIGPDA01 3842
+#define MACH_TYPE_CN27 3843
+#define MACH_TYPE_MX25_CWTAP 3844
+#define MACH_TYPE_APF28 3845
+#define MACH_TYPE_PELCO_MAXWELL 3846
+#define MACH_TYPE_GE_PHOENIX 3847
+#define MACH_TYPE_EMPC_A500 3848
+#define MACH_TYPE_IMS_ARM9 3849
+#define MACH_TYPE_MINI2416 3850
+#define MACH_TYPE_MINI2450 3851
+#define MACH_TYPE_MINI310 3852
+#define MACH_TYPE_SPEAR_HURRICANE 3853
+#define MACH_TYPE_MT7208 3854
+#define MACH_TYPE_LPC178X 3855
+#define MACH_TYPE_FARLEYS 3856
+#define MACH_TYPE_EFM32GG_DK3750 3857
+#define MACH_TYPE_ZEUS_BOARD 3858
+#define MACH_TYPE_CC51 3859
+#define MACH_TYPE_FXI_C210 3860
+#define MACH_TYPE_MSM8627_CDP 3861
+#define MACH_TYPE_MSM8627_MTP 3862
#define MACH_TYPE_ARMADILLO800EVA 3863
+#define MACH_TYPE_PRIMOU 3864
+#define MACH_TYPE_PRIMOC 3865
+#define MACH_TYPE_PRIMOCT 3866
+#define MACH_TYPE_A9500 3867
+#define MACH_TYPE_PULSE_TD 3868
+#define MACH_TYPE_PLUTO 3869
+#define MACH_TYPE_ACFX100 3870
+#define MACH_TYPE_MSM8625_RUMI3 3871
+#define MACH_TYPE_VALENTE 3872
+#define MACH_TYPE_CRFS_RFEYE 3873
+#define MACH_TYPE_RFEYE 3874
+#define MACH_TYPE_PHIDGET_SBC3 3875
+#define MACH_TYPE_TCW_MIKA 3876
+#define MACH_TYPE_IMX28_EGF 3877
+#define MACH_TYPE_VALENTE_WX 3878
+#define MACH_TYPE_HUANGSHANS 3879
+#define MACH_TYPE_BOSPHORUS1 3880
+#define MACH_TYPE_PRIMA 3881
+#define MACH_TYPE_M3_SKT 3882
+#define MACH_TYPE_M3_REF 3883
+#define MACH_TYPE_EVITA_ULK 3884
+#define MACH_TYPE_MERISC600 3885
+#define MACH_TYPE_DOLAK 3886
+#define MACH_TYPE_SBC53 3887
+#define MACH_TYPE_ELITE_ULK 3888
+#define MACH_TYPE_POV2 3889
+#define MACH_TYPE_IPOD_TOUCH_2G 3890
+#define MACH_TYPE_DA850_PQAB 3891
+#define MACH_TYPE_FERMI 3892
+#define MACH_TYPE_CCARDWMX28 3893
+#define MACH_TYPE_CCARDMX28 3894
+#define MACH_TYPE_FS20_FCM2050 3895
+#define MACH_TYPE_KINETIS 3896
+#define MACH_TYPE_KAI 3897
+#define MACH_TYPE_BCTHB2 3898
+#define MACH_TYPE_INELS3_CU 3899
+#define MACH_TYPE_JUNIPER 3900
+#define MACH_TYPE_DA850_APOLLO 3901
+#define MACH_TYPE_TRACNAS 3902
+#define MACH_TYPE_MITYARM335X 3903
+#define MACH_TYPE_XCGZ7X 3904
+#define MACH_TYPE_CUBOX 3905
+#define MACH_TYPE_TERMINATOR 3906
+#define MACH_TYPE_EYE03 3907
+#define MACH_TYPE_KOTA3 3908
+#define MACH_TYPE_MX5 3909
+#define MACH_TYPE_PSCPE 3910
+#define MACH_TYPE_AKT1100 3911
+#define MACH_TYPE_PCAAXL2 3912
+#define MACH_TYPE_PRIMODD_CT 3913
+#define MACH_TYPE_NSBC 3914
+#define MACH_TYPE_MESON2_SKT 3915
+#define MACH_TYPE_MESON2_REF 3916
+#define MACH_TYPE_CCARDWMX28JS 3917
+#define MACH_TYPE_CCARDMX28JS 3918
+#define MACH_TYPE_INDICO 3919
+#define MACH_TYPE_MSM8960DT 3920
+#define MACH_TYPE_PRIMODS 3921
+#define MACH_TYPE_BELUGA_M1388 3922
+#define MACH_TYPE_PRIMOTD 3923
+#define MACH_TYPE_VARAN_MASTER 3924
+#define MACH_TYPE_PRIMODD 3925
+#define MACH_TYPE_JETDUO 3926
#define MACH_TYPE_MX53_UMOBO 3927
+#define MACH_TYPE_TRATS 3928
+#define MACH_TYPE_STARCRAFT 3929
+#define MACH_TYPE_QSEVEN_TEGRA2 3930
+#define MACH_TYPE_LICHEE_SUN4I_DEVBD 3931
+#define MACH_TYPE_MOVENOW 3932
+#define MACH_TYPE_GOLF_U 3933
+#define MACH_TYPE_MSM7627A_EVB 3934
+#define MACH_TYPE_RAMBO 3935
+#define MACH_TYPE_GOLFU 3936
+#define MACH_TYPE_MANGO310 3937
+#define MACH_TYPE_DNS343 3938
+#define MACH_TYPE_VAR_SOM_OM44 3939
+#define MACH_TYPE_NAON 3940
+#define MACH_TYPE_VP4000 3941
+#define MACH_TYPE_IMPCARD 3942
+#define MACH_TYPE_SMOOVCAM 3943
+#define MACH_TYPE_COBHAM3725 3944
+#define MACH_TYPE_COBHAM3730 3945
+#define MACH_TYPE_COBHAM3703 3946
+#define MACH_TYPE_QUETZAL 3947
+#define MACH_TYPE_APQ8064_CDP 3948
+#define MACH_TYPE_APQ8064_MTP 3949
+#define MACH_TYPE_APQ8064_FLUID 3950
+#define MACH_TYPE_APQ8064_LIQUID 3951
+#define MACH_TYPE_MANGO210 3952
+#define MACH_TYPE_MANGO100 3953
+#define MACH_TYPE_MANGO24 3954
+#define MACH_TYPE_MANGO64 3955
+#define MACH_TYPE_NSA320 3956
+#define MACH_TYPE_ELV_CCU2 3957
+#define MACH_TYPE_TRITON_X00 3958
+#define MACH_TYPE_TRITON_1500_2000 3959
+#define MACH_TYPE_POGOPLUGV4 3960
+#define MACH_TYPE_VENUS_CL 3961
+#define MACH_TYPE_VULCANO_G20 3962
+#define MACH_TYPE_SGS_I9100 3963
+#define MACH_TYPE_STSV2 3964
+#define MACH_TYPE_CSB1724 3965
+#define MACH_TYPE_OMAPL138_LCDK 3966
+#define MACH_TYPE_JEWEL_DD 3967
+#define MACH_TYPE_PVD_MX25 3968
+#define MACH_TYPE_MESON6_SKT 3969
+#define MACH_TYPE_MESON6_REF 3970
+#define MACH_TYPE_PXM 3971
+#define MACH_TYPE_S3 3972
+#define MACH_TYPE_POGOPLUGV3 3973
+#define MACH_TYPE_MLP89626 3974
+#define MACH_TYPE_IOMEGAHMNDCE 3975
+#define MACH_TYPE_POGOPLUGV3PCI 3976
+#define MACH_TYPE_BNTV250 3977
+#define MACH_TYPE_MX53_QSEVEN 3978
+#define MACH_TYPE_GTL_IT1100 3979
+#define MACH_TYPE_MX6Q_SABRESD 3980
#define MACH_TYPE_MT4 3981
+#define MACH_TYPE_JUMBO_D 3982
+#define MACH_TYPE_JUMBO_I 3983
+#define MACH_TYPE_FS20_DMP 3984
+#define MACH_TYPE_DNS320 3985
+#define MACH_TYPE_MX28BACOS 3986
+#define MACH_TYPE_TL80 3987
+#define MACH_TYPE_POLATIS_NIC_1001 3988
+#define MACH_TYPE_TELY 3989
#define MACH_TYPE_U8520 3990
+#define MACH_TYPE_MANTA 3991
+#define MACH_TYPE_SPEAR_EM_S900 3992
+#define MACH_TYPE_MPQ8064_CDP 3993
+#define MACH_TYPE_MPQ8064_STB 3994
+#define MACH_TYPE_MPQ8064_DTV 3995
+#define MACH_TYPE_DM368SOM 3996
+#define MACH_TYPE_GPRISB2 3997
+#define MACH_TYPE_CHAMMID 3998
+#define MACH_TYPE_SEOUL2 3999
+#define MACH_TYPE_OMAP4_NOOKTABLET 4000
+#define MACH_TYPE_AALTO 4001
+#define MACH_TYPE_METRO 4002
+#define MACH_TYPE_CYDM3730 4003
+#define MACH_TYPE_TQMA53 4004
+#define MACH_TYPE_MSM7627A_QRD3 4005
+#define MACH_TYPE_MX28_CANBY 4006
+#define MACH_TYPE_TIGER 4007
+#define MACH_TYPE_PCATS_9307_TYPE_A 4008
+#define MACH_TYPE_PCATS_9307_TYPE_O 4009
+#define MACH_TYPE_PCATS_9307_TYPE_R 4010
+#define MACH_TYPE_STREAMPLUG 4011
+#define MACH_TYPE_ICECHICKEN_DEV 4012
+#define MACH_TYPE_HEDGEHOG 4013
+#define MACH_TYPE_YUSEND_OBC 4014
+#define MACH_TYPE_IMXNINJA 4015
+#define MACH_TYPE_OMAP4_JAROD 4016
+#define MACH_TYPE_ECO5_PK 4017
+#define MACH_TYPE_QJ2440 4018
+#define MACH_TYPE_MX6Q_MERCURY 4019
+#define MACH_TYPE_CM6810 4020
+#define MACH_TYPE_OMAP4_TORPEDO 4021
+#define MACH_TYPE_NSA310 4022
+#define MACH_TYPE_TMX536 4023
+#define MACH_TYPE_KTT20 4024
+#define MACH_TYPE_DRAGONIX 4025
+#define MACH_TYPE_LUNGCHING 4026
+#define MACH_TYPE_BULOGICS 4027
+#define MACH_TYPE_MX535_SX 4028
+#define MACH_TYPE_NGUI3250 4029
+#define MACH_TYPE_SALUTEC_DAC 4030
+#define MACH_TYPE_LOCO 4031
+#define MACH_TYPE_CTERA_PLUG_USI 4032
+#define MACH_TYPE_SCEPTER 4033
+#define MACH_TYPE_SGA 4034
+#define MACH_TYPE_P_81_J5 4035
+#define MACH_TYPE_P_81_O4 4036
+#define MACH_TYPE_MSM8625_SURF 4037
+#define MACH_TYPE_CARALLON_SHARK 4038
+#define MACH_TYPE_LSGCICAM 4039
+#define MACH_TYPE_ORDOG 4040
+#define MACH_TYPE_PUENTE_IO 4041
+#define MACH_TYPE_MSM8625_EVB 4042
+#define MACH_TYPE_EV_AM1707 4043
+#define MACH_TYPE_EV_AM1707E2 4044
+#define MACH_TYPE_EV_AM3517E2 4045
+#define MACH_TYPE_CALABRIA 4046
+#define MACH_TYPE_EV_IMX287 4047
+#define MACH_TYPE_ERAU 4048
+#define MACH_TYPE_SICHUAN 4049
+#define MACH_TYPE_WIRMA3 4050
+#define MACH_TYPE_DAVINCI_DA850 4051
+#define MACH_TYPE_OMAP138_TRUNARC 4052
+#define MACH_TYPE_BCM4761 4053
+#define MACH_TYPE_PICASSO_E2 4054
+#define MACH_TYPE_PICASSO_MF 4055
+#define MACH_TYPE_MIRO 4056
+#define MACH_TYPE_AT91SAM9G20EWON3 4057
+#define MACH_TYPE_YOYO 4058
+#define MACH_TYPE_WINDJKL 4059
+#define MACH_TYPE_MONARUDO 4060
+#define MACH_TYPE_BATAN 4061
+#define MACH_TYPE_TADAO 4062
+#define MACH_TYPE_BASO 4063
+#define MACH_TYPE_MAHON 4064
+#define MACH_TYPE_VILLEC2 4065
+#define MACH_TYPE_ASI1230 4066
+#define MACH_TYPE_ALASKA 4067
+#define MACH_TYPE_SWARCO_SHDSL2 4068
+#define MACH_TYPE_OXRTU 4069
+#define MACH_TYPE_OMAP5_PANDA 4070
+#define MACH_TYPE_MX28XDI 4071
+#define MACH_TYPE_C8000 4072
+#define MACH_TYPE_BJE_DISPLAY3_5 4073
+#define MACH_TYPE_PICOMOD7 4074
+#define MACH_TYPE_PICOCOM5 4075
+#define MACH_TYPE_QBLISSA8 4076
+#define MACH_TYPE_ARMSTONEA8 4077
+#define MACH_TYPE_NETDCU14 4078
+#define MACH_TYPE_AT91SAM9X5_EPIPHAN 4079
+#define MACH_TYPE_P2U 4080
+#define MACH_TYPE_DORIS 4081
+#define MACH_TYPE_J49 4082
+#define MACH_TYPE_VDSS2E 4083
+#define MACH_TYPE_VC300 4084
+#define MACH_TYPE_NS115_PAD_TEST 4085
+#define MACH_TYPE_NS115_PAD_REF 4086
+#define MACH_TYPE_NS115_PHONE_TEST 4087
+#define MACH_TYPE_NS115_PHONE_REF 4088
+#define MACH_TYPE_GOLFC 4089
+#define MACH_TYPE_XEROX_OLYMPUS 4090
+#define MACH_TYPE_MX6SL_ARM2 4091
+#define MACH_TYPE_CSB1701_CSB1726 4092
+#define MACH_TYPE_AT91SAM9XEEK 4093
+#define MACH_TYPE_EBV210 4094
+#define MACH_TYPE_MSM7627A_QRD7 4095
+#define MACH_TYPE_SVTHIN 4096
+#define MACH_TYPE_DUOVERO 4097
#define MACH_TYPE_CHUPACABRA 4098
#define MACH_TYPE_SCORPION 4099
#define MACH_TYPE_DAVINCI_HE_HMI10 4100
#define MACH_TYPE_GROUPER 4117
#define MACH_TYPE_MPCSA21_9G20 4118
#define MACH_TYPE_M6U_CPU 4119
+#define MACH_TYPE_DAVINCI_DP10 4120
#define MACH_TYPE_GINKGO 4121
#define MACH_TYPE_CGT_QMX6 4122
#define MACH_TYPE_PROFPGA 4123
#define MACH_TYPE_TN_MUNINN 4157
#define MACH_TYPE_RAMPAGE 4158
#define MACH_TYPE_VISSTRIM_MV10 4159
+#define MACH_TYPE_MONACO_TDU 4160
+#define MACH_TYPE_MONACO_UL 4161
+#define MACH_TYPE_ENRC2_U 4162
+#define MACH_TYPE_EVITA_UL 4163
#define MACH_TYPE_MX28_WILMA 4164
+#define MACH_TYPE_MONACO_U 4165
#define MACH_TYPE_MSM8625_FFA 4166
#define MACH_TYPE_VPU101 4167
+#define MACH_TYPE_OPERA_UL 4168
#define MACH_TYPE_BAILEYS 4169
#define MACH_TYPE_FAMILYBOX 4170
#define MACH_TYPE_ENSEMBLE_MX35 4171
#define MACH_TYPE_MINITV 4210
#define MACH_TYPE_U8540 4211
#define MACH_TYPE_IV_ATLAS_I_Z7E 4212
+#define MACH_TYPE_COGENT_CSB1733 4213
#define MACH_TYPE_MACH_TYPE_SKY 4214
#define MACH_TYPE_BLUESKY 4215
#define MACH_TYPE_NGROUTER 4216
#define MACH_TYPE_LINKSTATION_LSQL 4238
#define MACH_TYPE_AM3703GATEWAY 4239
#define MACH_TYPE_ACCIPITER 4240
+#define MACH_TYPE_P1853 4241
#define MACH_TYPE_MAGNIDUG 4242
#define MACH_TYPE_HYDRA 4243
#define MACH_TYPE_SUN3I 4244
#define MACH_TYPE_BCTRM3 4332
#define MACH_TYPE_DOCTORWS 4333
#define MACH_TYPE_M2601 4334
+#define MACH_TYPE_GRIDCO_TRINITY 4335
+#define MACH_TYPE_PC3032 4336
#define MACH_TYPE_VGG1111 4337
#define MACH_TYPE_COUNTACH 4338
#define MACH_TYPE_VISSTRIM_SM20 4339
#define MACH_TYPE_NAD435 4385
#define MACH_TYPE_NS115_PROTO_TYPE 4386
#define MACH_TYPE_FS20_VCC 4387
+#define MACH_TYPE_MESON6TV 4388
#define MACH_TYPE_MESON6TV_SKT 4389
#define MACH_TYPE_KEYSTONE 4390
#define MACH_TYPE_PCM052 4391
+#define MACH_TYPE_TYPE 4392
#define MACH_TYPE_QRD_SKUD_PRIME 4393
+#define MACH_TYPE_RAINBOWG15 4394
#define MACH_TYPE_GUF_SANTARO 4395
#define MACH_TYPE_SHEEPSHEAD 4396
#define MACH_TYPE_MX6_IWG15M_MXM 4397
#define MACH_TYPE_MX6_IWG15M_Q7 4398
#define MACH_TYPE_AT91SAM9263IF8MIC 4399
+#define MACH_TYPE_EXCEL 4400
#define MACH_TYPE_MARCOPOLO 4401
#define MACH_TYPE_MX535_SDCR 4402
#define MACH_TYPE_MX53_CSB2733 4403
#define MACH_TYPE_CEC4 4427
#define MACH_TYPE_APE6EVM 4428
#define MACH_TYPE_TX6 4429
+#define MACH_TYPE_OWENSOM 4430
#define MACH_TYPE_CFA10037 4431
+#define MACH_TYPE_NATEKS_VOIP 4432
#define MACH_TYPE_EZP1000 4433
#define MACH_TYPE_WGR826V 4434
#define MACH_TYPE_EXUMA 4435
#define MACH_TYPE_SMARTRTU 4464
#define MACH_TYPE_RCM101 4465
#define MACH_TYPE_AMX_IMX53_MXX 4466
+#define MACH_TYPE_CP3DCG 4467
+#define MACH_TYPE_CP3DTG 4468
+#define MACH_TYPE_CP3DUG 4469
#define MACH_TYPE_ACER_A12 4470
#define MACH_TYPE_SBC6X 4471
#define MACH_TYPE_U2 4472
#define MACH_TYPE_PRISCILLAC 4475
#define MACH_TYPE_PRISCILLA 4476
#define MACH_TYPE_INNOVA_SHPU_V2 4477
+#define MACH_TYPE_M7CDTU 4478
#define MACH_TYPE_MACH_TYPE_DEP2410 4479
#define MACH_TYPE_BCTRE3 4480
#define MACH_TYPE_OMAP_M100 4481
#define MACH_TYPE_STM_B2105 4484
#define MACH_TYPE_OMAP4_BSC_BAP_V3 4485
#define MACH_TYPE_SS1PAM 4486
+#define MACH_TYPE_DLXP_WL 4487
#define MACH_TYPE_PRIMOMINIU 4488
#define MACH_TYPE_MRT_35HD_DUALNAS_E 4489
#define MACH_TYPE_KIWI 4490
#define MACH_TYPE_COLIBRI_T30 4493
#define MACH_TYPE_CWV1 4494
#define MACH_TYPE_NSA325 4495
+#define MACH_TYPE_DLXP_UL 4496
#define MACH_TYPE_DPXMTC 4497
#define MACH_TYPE_TT_STUTTGART 4498
#define MACH_TYPE_MIRANDA_APCII 4499
#define MACH_TYPE_MUDSKIPPER 4501
#define MACH_TYPE_URANIA 4502
#define MACH_TYPE_STM_B2112 4503
+#define MACH_TYPE_GTOU 4504
#define MACH_TYPE_MX6Q_ATS_PHOENIX 4505
#define MACH_TYPE_STM_B2116 4506
#define MACH_TYPE_MYTHOLOGY 4507
#define MACH_TYPE_MPQ8064_DMA 4511
#define MACH_TYPE_WEMS_ASD01 4512
#define MACH_TYPE_APALIS_T30 4513
+#define MACH_TYPE_MX6Q_QSBC35_C398 4514
#define MACH_TYPE_ARMSTONEA9 4515
#define MACH_TYPE_OMAP_BLAZETABLET 4516
#define MACH_TYPE_AR6MXQ 4517
#define MACH_TYPE_AR6MXS 4518
+#define MACH_TYPE_DETO_APOS_MX6 4519
#define MACH_TYPE_GWVENTANA 4520
#define MACH_TYPE_IGEP0033 4521
+#define MACH_TYPE_RACA 4522
+#define MACH_TYPE_APPLESODA 4523
#define MACH_TYPE_H52C1_CONCERTO 4524
#define MACH_TYPE_FCMBRD 4525
#define MACH_TYPE_PCAAXS1 4526
#define MACH_TYPE_EUKREA_CPUIMX28SD 4573
#define MACH_TYPE_DOMOTAB 4574
#define MACH_TYPE_PFLA03 4575
-
+#define MACH_TYPE_ET_CPU_301_16 4576
+#define MACH_TYPE_SKYWALKER 4577
+#define MACH_TYPE_SCORPIUS 4578
+#define MACH_TYPE_CAPRICORNUS 4579
+#define MACH_TYPE_LYRA 4580
+#define MACH_TYPE_GATERO 4581
+#define MACH_TYPE_GATERO01 4582
+#define MACH_TYPE_Z4DTG 4583
+#define MACH_TYPE_LUPUS 4584
+#define MACH_TYPE_LEAP101 4585
+#define MACH_TYPE_CM_T335 4586
+#define MACH_TYPE_PNA 4587
+#define MACH_TYPE_ECOFOREST_CPU2013 4588
+#define MACH_TYPE_APQ8064_DMA 4589
+#define MACH_TYPE_MX53_ARMOUR 4590
+#define MACH_TYPE_EUROFUNK_AEPL3 4591
+#define MACH_TYPE_EUROFUNK_MHLS3 4592
+#define MACH_TYPE_EUROFUNK_E1IF 4593
+#define MACH_TYPE_LEPUS 4594
+#define MACH_TYPE_BORA 4595
+#define MACH_TYPE_ADS4011 4596
+#define MACH_TYPE_BEAVER 4597
+#define MACH_TYPE_IMX233_IUNGO 4598
+#define MACH_TYPE_CEPHEUS 4599
+#define MACH_TYPE_CETUS 4600
+#define MACH_TYPE_CHAMAELEON 4601
+#define MACH_TYPE_ARDBEG 4602
+#define MACH_TYPE_IXORA 4603
+#define MACH_TYPE_JUGLANS 4604
+#define MACH_TYPE_CANISMAJOR 4605
+#define MACH_TYPE_AT91SAM9263MIB 4606
+#define MACH_TYPE_COSINO_9G35 4607
+#define MACH_TYPE_TINY4412 4608
+#define MACH_TYPE_BALLOON4 4609
+#define MACH_TYPE_PGG 4610
+#define MACH_TYPE_XXSQ701 4611
+#define MACH_TYPE_MX6_NAVICO_RDR 4612
+#define MACH_TYPE_PHANTOM 4613
+#define MACH_TYPE_CANISMINORH 4614
+#define MACH_TYPE_CARINA 4615
+#define MACH_TYPE_E1859 4616
+#define MACH_TYPE_ARMSTONEA5 4617
+#define MACH_TYPE_PICOCOMA5 4618
+#define MACH_TYPE_NETDCUA5 4619
+#define MACH_TYPE_MOLLY 4620
+#define MACH_TYPE_MASERATI 4621
+#define MACH_TYPE_MX53_IDEBX 4622
+#define MACH_TYPE_MX53_C2CB 4623
+#define MACH_TYPE_MIPSEE 4624
+#define MACH_TYPE_SEEKLOP 4625
+#define MACH_TYPE_AUDISEE 4626
+#define MACH_TYPE_TX48 4627
+#define MACH_TYPE_TL7689_PAD_REF 4628
+#define MACH_TYPE_TL7689_PAD_TEST 4629
+#define MACH_TYPE_TL7689_PHONE_REF 4630
+#define MACH_TYPE_TL7689_PHONE_TEST 4631
+#define MACH_TYPE_SWARCO_SCC_WKS 4632
+#define MACH_TYPE_ACCORDO2 4633
+#define MACH_TYPE_TRIZEPS7 4634
+#define MACH_TYPE_F100 4635
+#define MACH_TYPE_ARMADILLO410 4636
+#define MACH_TYPE_TINY2416 4637
+#define MACH_TYPE_TINY2451 4638
+#define MACH_TYPE_MINI2451 4639
+#define MACH_TYPE_TINY5250 4640
+#define MACH_TYPE_TINY3358 4641
+#define MACH_TYPE_T6_UL 4642
+#define MACH_TYPE_T6_U 4643
+#define MACH_TYPE_T6_ULA 4644
+#define MACH_TYPE_T6_WL 4645
+#define MACH_TYPE_T6_WHL 4646
+#define MACH_TYPE_CIRCINUS 4647
+#define MACH_TYPE_SOCPK255 4648
+#define MACH_TYPE_SOCPRV270 4649
+#define MACH_TYPE_SOCPRC270 4650
+#define MACH_TYPE_MACH_CP5DTU 4651
+#define MACH_TYPE_CP5DTU 4652
+#define MACH_TYPE_CP5DUG 4653
+#define MACH_TYPE_CP5DWG 4654
+#define MACH_TYPE_AM335X_EGF 4655
+#define MACH_TYPE_AZM9G45 4656
+#define MACH_TYPE_AZM335X 4657
+#define MACH_TYPE_LYNBRD 4658
+#define MACH_TYPE_AM35X_EGF 4659
+#define MACH_TYPE_SEVULCAN 4660
+#define MACH_TYPE_AX8008M 4661
+#define MACH_TYPE_AX8008MR 4662
+#define MACH_TYPE_XYNIX 4663
+#define MACH_TYPE_OMAP3621_ODYV4 4664
+#define MACH_TYPE_MX6_CAMERONET 4665
+#define MACH_TYPE_OMAP4_DART 4666
+#define MACH_TYPE_MX6Q_ENZO 4667
+#define MACH_TYPE_EV_IMX287MICRO 4668
+#define MACH_TYPE_EV_IMX287MINI 4669
+#define MACH_TYPE_MX53_CEC2 4670
+#define MACH_TYPE_HELIOS_V8 4671
+#define MACH_TYPE_HELIOS_V9 4672
+#define MACH_TYPE_COGNAC 4673
+#define MACH_TYPE_ZEST 4674
+#define MACH_TYPE_GC3 4675
+#define MACH_TYPE_DAD_MEDIA 4676
+#define MACH_TYPE_HTOUCH 4677
+#define MACH_TYPE_SPT7500BASEBOARD 4678
+#define MACH_TYPE_OMAP4_DART_EVM 4679
+#define MACH_TYPE_MX53_TLV 4680
+#define MACH_TYPE_PDAK2H 4681
+#define MACH_TYPE_MATRIX513 4682
+#define MACH_TYPE_LIVEBOX01 4683
+#define MACH_TYPE_CEVRZA1L 4684
+#define MACH_TYPE_B1010 4685
+#define MACH_TYPE_FWTMK1 4686
+#define MACH_TYPE_GRENADA 4687
+#define MACH_TYPE_HASSEL 4688
+#define MACH_TYPE_ODROIDXU 4689
+#define MACH_TYPE_ODROIDU2 4690
+#define MACH_TYPE_NAIAD 4691
+#define MACH_TYPE_HARRIER 4692
+#define MACH_TYPE_PCL052 4693
+#define MACH_TYPE_LIBRA2404 4694
+#define MACH_TYPE_MX6_LEMONBOARD 4695
+#define MACH_TYPE_MX6_ATLAS 4696
+#define MACH_TYPE_ELECSYS_Z2 4697
+#define MACH_TYPE_ELECSYS_Z4 4698
+#define MACH_TYPE_IPQ806X_DB149 4699
+#define MACH_TYPE_PULSAR 4700
+#define MACH_TYPE_SCALANCEM 4701
+#define MACH_TYPE_NA11 4702
+#define MACH_TYPE_IPQ806X_DB147 4703
+#define MACH_TYPE_IPQ806X_AP148 4704
+#define MACH_TYPE_AMLTD_IMX6 4705
+#define MACH_TYPE_PIA_AM335X 4706
+#define MACH_TYPE_BLADE 4707
+#define MACH_TYPE_MATISSE 4708
+#define MACH_TYPE_IKEBANA 4709
+#define MACH_TYPE_LF3000 4710
+#define MACH_TYPE_CARALLON_STINGRAY 4711
+#define MACH_TYPE_MENSA 4712
+#define MACH_TYPE_CES_COREBOARD 4713
+#define MACH_TYPE_VYBRID_IWG16M_UMXM 4714
+#define MACH_TYPE_LOKI 4715
+#define MACH_TYPE_PCM053 4716
+#define MACH_TYPE_SMM200 4717
+#define MACH_TYPE_M507 4718
+#define MACH_TYPE_ORSOC_ARMSOC_8695 4719
+#define MACH_TYPE_AM335X_ZY 4720
+#define MACH_TYPE_ARRAKIS 4721
+#define MACH_TYPE_SXLT 4722
+#define MACH_TYPE_YLCM 4723
+#define MACH_TYPE_EAGLE6D 4724
+#define MACH_TYPE_LCU1 4725
+#define MACH_TYPE_MX6DL_IWG15M_Q7 4726
+#define MACH_TYPE_SBCPHYFLEXAM335 4727
+#define MACH_TYPE_SBCPHYCARDAM335 4728
+#define MACH_TYPE_SBCPHYFLEXIMX6 4729
+#define MACH_TYPE_HOMESERVERSTICK 4730
+#define MACH_TYPE_ECXEC 4731
+#define MACH_TYPE_HH300 4732
+#define MACH_TYPE_CPUCA8 4733
+#define MACH_TYPE_A0057_LSEMBEDDEDPC 4734
+#define MACH_TYPE_IPROC 4735
+#define MACH_TYPE_NEMESIS_NFE 4736
+#define MACH_TYPE_MABV3X25 4737
+#define MACH_TYPE_OCTANT 4738
+#define MACH_TYPE_MSM7X27_THUNDER 4739
+#define MACH_TYPE_MAXIM 4740
+#define MACH_TYPE_TELEMATICCTRLUNIT 4741
+#define MACH_TYPE_MX6Q_JCDBOX 4742
+#define MACH_TYPE_CKB_1808 4743
+#define MACH_TYPE_CKB_3352 4744
+#define MACH_TYPE_HIKIRK 4745
+#define MACH_TYPE_DNS320L 4746
+#define MACH_TYPE_STM_B2120 4747
+#define MACH_TYPE_STM_B2089 4748
+#define MACH_TYPE_COLIBRI_VF50 4749
+#define MACH_TYPE_COLIBRI_VF61 4750
+#define MACH_TYPE_SYNERGY2 4751
+#define MACH_TYPE_PCM051_HMI 4752
+#define MACH_TYPE_TEK2 4753
+#define MACH_TYPE_DUCKBILL 4754
+#define MACH_TYPE_MX50_SEISMIC 4755
+#define MACH_TYPE_TWOFACE 4756
+#define MACH_TYPE_T10 4757
+#define MACH_TYPE_LIB1313 4758
+#define MACH_TYPE_HIMX 4759
+#define MACH_TYPE_VCM30_T30 4760
+#define MACH_TYPE_CORNERVIEW 4761
+#define MACH_TYPE_P01600 4762
+#define MACH_TYPE_AXEL 4763
+#define MACH_TYPE_IMX6_ANDY 4764
+#define MACH_TYPE_NSA220 4765
+#define MACH_TYPE_TI8168HSC1 4766
+#define MACH_TYPE_DORY 4767
+#define MACH_TYPE_ECV4 4768
+#define MACH_TYPE_WEBBG3FLIGHT 4769
+#define MACH_TYPE_SBC_PHYCORE_AM335X 4770
+#define MACH_TYPE_TSC 4771
+#define MACH_TYPE_IMX6_CLOUS 4772
+#define MACH_TYPE_C1 4773
+#define MACH_TYPE_VCM30T30 4774
+#define MACH_TYPE_IMX6_EMSYM_BLURR 4775
+#define MACH_TYPE_PDIS_M 4776
+#define MACH_TYPE_MX6Q_REX 4777
+#define MACH_TYPE_SWARCO_FR_ANYBUS 4778
+#define MACH_TYPE_SHMAC 4779
+#define MACH_TYPE_CKB_RZA1H 4780
+#define MACH_TYPE_AZETI_SP_NG01 4781
+#define MACH_TYPE_E6210 4782
+#define MACH_TYPE_MH9001 4783
+#define MACH_TYPE_STM_B2147 4784
+#define MACH_TYPE_OMAP5_VARSOM 4785
+#define MACH_TYPE_CUBEA5 4786
+#define MACH_TYPE_CP5 4787
+#define MACH_TYPE_FORNAX 4788
+#define MACH_TYPE_ICU 4789
+#define MACH_TYPE_COMUS3 4790
+#define MACH_TYPE_LIBRA4344 4791
+#define MACH_TYPE_LIBRA4644 4792
+#define MACH_TYPE_PAVO 4793
+#define MACH_TYPE_XL824 4794
+#define MACH_TYPE_XL850 4795
+#define MACH_TYPE_MX6_PICO_ITX 4796
+#define MACH_TYPE_AMICO_S 4797
+#define MACH_TYPE_AMICO_P 4798
+#define MACH_TYPE_MINNOW 4799
+#define MACH_TYPE_DAVINCI_DM365_ZY 4800
+#define MACH_TYPE_PAVO_2 4801
+#define MACH_TYPE_IAVS 4802
+#define MACH_TYPE_RANA 4803
+#define MACH_TYPE_MERAKI_MS26 4804
+#define MACH_TYPE_VP2_REFRESH 4805
+#define MACH_TYPE_MCB1800 4806
+#define MACH_TYPE_MX6Q_DEVONIT_TC3 4807
+#define MACH_TYPE_UC81XX 4808
+#define MACH_TYPE_UC84XX 4809
+#define MACH_TYPE_IPQ806X_AP145 4810
+#define MACH_TYPE_IPQ806X_DB149_MMC 4811
+#define MACH_TYPE_IPQ806X_AP145_MMC 4812
+#define MACH_TYPE_E3QT 4813
+#define MACH_TYPE_U222 4814
+#define MACH_TYPE_UFO878 4815
+#define MACH_TYPE_GEKKO 4816
+#define MACH_TYPE_MINI2440ARM 4817
+#define MACH_TYPE_MPCSB2_9G20 4818
+#define MACH_TYPE_TL7689_PAD_706 4819
+#define MACH_TYPE_TDA7 4820
+#define MACH_TYPE_CUBOXI 4821
+#define MACH_TYPE_TIBIDABO 4822
+#define MACH_TYPE_T216MINI 4823
+#define MACH_TYPE_HERA_IMX6 4824
+#define MACH_TYPE_GRIDPOINT_EC1K 4825
+#define MACH_TYPE_LIBRA4404 4826
+#define MACH_TYPE_MI_MOCHA 4827
+#define MACH_TYPE_BCM2835 4828
+#define MACH_TYPE_NFP6XXX 4829
+#define MACH_TYPE_TETRA 4830
+#define MACH_TYPE_NECO 4831
+#define MACH_TYPE_PROTONEX_VPM402 4832
+#define MACH_TYPE_MX6Q_SAVAGE 4833
+#define MACH_TYPE_MX6Q_SOMB 4834
+#define MACH_TYPE_FILI_DL 4835
+#define MACH_TYPE_ADAPT_SDRDC 4836
+#define MACH_TYPE_DS_QUARTZ 4837
+#define MACH_TYPE_ULTRAFLEX 4838
+#define MACH_TYPE_APQ8064_ADP_2 4839
+#define MACH_TYPE_BEAN 4840
+#define MACH_TYPE_BALDR 4841
+#define MACH_TYPE_CCIMX6ADPT 4842
+#define MACH_TYPE_TS4900 4843
+#define MACH_TYPE_ZEPLUG 4844
+#define MACH_TYPE_MSM8X60_DUPLICITY 4845
+#define MACH_TYPE_CTERA_2BAY_A 4846
+#define MACH_TYPE_AM335X_BAP_V3_1 4847
+#define MACH_TYPE_XPECT01 4848
+#define MACH_TYPE_ESI23 4849
+#define MACH_TYPE_MX6DL_SBC35_C398 4850
+#define MACH_TYPE_MX6SOLO_SBC35_C398 4851
+#define MACH_TYPE_KSP5012 4852
+#define MACH_TYPE_MX6Q_ZEUS 4853
+#define MACH_TYPE_INNOVA_MATRIX 4854
+#define MACH_TYPE_RF6XXR 4855
+#define MACH_TYPE_PECORINO 4856
+#define MACH_TYPE_MHPLAY_W 4857
+#define MACH_TYPE_PELCO_DRAGONFLY 4858
+#define MACH_TYPE_VSM_CHAMHIGH 4859
+#define MACH_TYPE_HACHIKO 4860
+#define MACH_TYPE_TL7689_PHONE_IN260 4861
+#define MACH_TYPE_CWMX6 4862
+#define MACH_TYPE_HD3 4863
+#define MACH_TYPE_UHD4 4864
+#define MACH_TYPE_BULPRINT_BOARD 4865
+#define MACH_TYPE_PELCO_SPECTRAHD2 4866
+#define MACH_TYPE_VISTEONV2X 4867
+#define MACH_TYPE_PHIDGET_VINTSBC 4868
+#define MACH_TYPE_LMU7030 4869
+#define MACH_TYPE_ECC2 4870
+#define MACH_TYPE_CDS_CTS 4871
+#define MACH_TYPE_AXELLITE 4872
+#define MACH_TYPE_ARNIE 4873
+#define MACH_TYPE_AGATEWAY 4874
+#define MACH_TYPE_PICOMODA9 4875
+#define MACH_TYPE_P_137_I6 4876
+#define MACH_TYPE_VVDN_MCAM 4877
+#define MACH_TYPE_MX6_INSIGHT 4878
+#define MACH_TYPE_VIPRINET_200 4879
+#define MACH_TYPE_ELLYPTO 4880
+#define MACH_TYPE_G7P 4881
+#define MACH_TYPE_YSE5250 4882
+#define MACH_TYPE_NG500 4883
+#define MACH_TYPE_DTSC02 4884
+#define MACH_TYPE_MX6DL_SBB 4885
+#define MACH_TYPE_APALIS_IMX6Q 4886
+#define MACH_TYPE_WOMBAT6 4887
+#define MACH_TYPE_BALTO 4888
+#define MACH_TYPE_TNGSBL 4889
+#define MACH_TYPE_H6061 4890
+#define MACH_TYPE_XA300 4891
+#define MACH_TYPE_PELCO_WOOFF 4892
+#define MACH_TYPE_PELCO_EVM 4893
+#define MACH_TYPE_MX6Q_IMXB 4894
+#define MACH_TYPE_SMARTTAB_V55 4895
+#define MACH_TYPE_SMARTTAB_V11A 4896
+#define MACH_TYPE_SMARTTAB_V71A 4897
+#define MACH_TYPE_NOVASOM5 4898
+#define MACH_TYPE_CCIMX6SBC 4899
+#define MACH_TYPE_INTOUCH 4900
+#define MACH_TYPE_MX6S_HAWTHORNE 4901
+#define MACH_TYPE_SEAH 4902
+#define MACH_TYPE_AM335X_EC3 4903
+#define MACH_TYPE_EMBEST_MARS 4904
+#define MACH_TYPE_MX6DL_VIKITOUCH 4905
+#define MACH_TYPE_IX2_NG 4906
+#define MACH_TYPE_PEKQSD 4907
+#define MACH_TYPE_PTEKN 4908
+#define MACH_TYPE_APQ8064_ADP2_ES2 4909
+#define MACH_TYPE_GHIIMX6 4910
+#define MACH_TYPE_M3000 4911
+#define MACH_TYPE_TCW101 4912
+#define MACH_TYPE_IPQ806X_AP148_1XX 4913
+#define MACH_TYPE_HNS_ACADIA 4914
+#define MACH_TYPE_MX6S_VIKITOUCH 4915
+#define MACH_TYPE_CM_QS600 4916
+#define MACH_TYPE_IPQ806X_DB149_2XX 4917
+#define MACH_TYPE_EAG_UGW400 4918
+#define MACH_TYPE_SK_GRANT_OEM 4919
+#define MACH_TYPE_KNOBLOCH_TXT 4920
+#define MACH_TYPE_MX6SL_SHD 4921
+#define MACH_TYPE_HIMX0294 4922
+#define MACH_TYPE_MX6Q_TTJ500 4923
+#define MACH_TYPE_CONTI_SGM358 4924
+#define MACH_TYPE_DENSOJ6REF 4925
+#define MACH_TYPE_KEVIN 4926
+#define MACH_TYPE_VVDN_TOII 4927
+#define MACH_TYPE_PENGWYN 4928
+#define MACH_TYPE_XARINA_ENTRY 4929
+#define MACH_TYPE_CONTI_MRNEVO 4930
+#define MACH_TYPE_NSA310S 4931
+#define MACH_TYPE_POWERECU 4932
+#define MACH_TYPE_Q7M120 4933
+#define MACH_TYPE_H6829 4934
+#define MACH_TYPE_AG13008 4935
+#define MACH_TYPE_IPQ806X_STORM 4936
+#define MACH_TYPE_DM3725_GSOM 4937
+#define MACH_TYPE_HP_PRIME 4938
+#define MACH_TYPE_FIRESTORM 4939
+#define MACH_TYPE_WINGZ 4940
+#define MACH_TYPE_ANDROMED 4941
+#define MACH_TYPE_SCM120 4942
+#define MACH_TYPE_CM_3G 4943
+#define MACH_TYPE_IPA400 4944
+#define MACH_TYPE_HYDRA_MKII 4945
+#define MACH_TYPE_AXM2 4946
+#define MACH_TYPE_CALOPUS 4947
+#define MACH_TYPE_BCTRM3S 4948
+#define MACH_TYPE_DM385LB 4949
+#define MACH_TYPE_SURMA_MKII 4950
+#define MACH_TYPE_OMAP4_SKHU_HCAM 4951
+#define MACH_TYPE_SCMCON 4952
+#define MACH_TYPE_KLK_IMX6S_G 4953
+#define MACH_TYPE_AM335XMX 4954
+#define MACH_TYPE_DMVA2_BTFU_WCAM 4955
+#define MACH_TYPE_UXC 4956
+#define MACH_TYPE_ELARM_A 4957
+#define MACH_TYPE_EMPC_AIMX6 4958
+#define MACH_TYPE_BCTRE2G2 4959
+#define MACH_TYPE_DMD 4960
+#define MACH_TYPE_DISCOVERY 4961
+#define MACH_TYPE_RELIAGATE_10_20 4962
+#define MACH_TYPE_MX6Q_DSA2LS 4963
+#define MACH_TYPE_MX6SL_ECT5 4964
+#define MACH_TYPE_COBHAM_MDC3 4965
+#define MACH_TYPE_TS_WAV 4966
+#define MACH_TYPE_XIN_GIGE_CAM 4967
+#define MACH_TYPE_ASAIIOTG 4968
+#define MACH_TYPE_DAU 4969
+#define MACH_TYPE_SOCFPGA_ARRIA5 4970
+#define MACH_TYPE_IPQ806X_AP160 4971
+#define MACH_TYPE_IPQ806X_AP161 4972
+#define MACH_TYPE_GEMX6 4973
+#define MACH_TYPE_EFUSA9 4974
+#define MACH_TYPE_DYNACOR_10_20 4975
+#define MACH_TYPE_BLUELIGHTNING 4976
+#define MACH_TYPE_SILVERBULLET 4977
+#define MACH_TYPE_MX6_MAEXLE 4978
+#define MACH_TYPE_PAYTEC_EPT 4979
+#define MACH_TYPE_ATLASCOPCO_ITMK2 4980
+#define MACH_TYPE_ATLASCOPCO_FLEXDRV 4981
+#define MACH_TYPE_ATLASCOPCO_FLEXIT 4982
+#define MACH_TYPE_PCDON 4983
+#define MACH_TYPE_DM8168_IWG12M_Q7 4984
+#define MACH_TYPE_RTM9431 4985
+#define MACH_TYPE_ARM11_CAR 4986
+#define MACH_TYPE_VIDEOPHONE 4987
+#define MACH_TYPE_MPFA 4988
+#define MACH_TYPE_PS10 4989
+#define MACH_TYPE_HGATEWAY 4990
+#define MACH_TYPE_IPQ806X_AP160_2 4991
+#define MACH_TYPE_ECP5COM 4992
+#define MACH_TYPE_H6064 4993
+#define MACH_TYPE_MX6X_MX 4994
+#define MACH_TYPE_MAJIC5422 4995
+#define MACH_TYPE_EMINDS 4996
+#define MACH_TYPE_TI8168TOII 4997
+#define MACH_TYPE_VXR10 4998
+#define MACH_TYPE_DS5 4999
+#define MACH_TYPE_DS3 5000
+#define MACH_TYPE_NOKIAN97 5001
+#define MACH_TYPE_TECNINT_ODBC 5002
+#define MACH_TYPE_C111 5003
+#define MACH_TYPE_ML300DU 5004
+#define MACH_TYPE_YAK 5005
+#define MACH_TYPE_NSA221 5006
+#define MACH_TYPE_GINKGOP 5007
+#define MACH_TYPE_MANGO 5008
+#define MACH_TYPE_AMBS2E 5009
+#define MACH_TYPE_AMBS3L 5010
+#define MACH_TYPE_DRA7XX_EVM 5011
+#define MACH_TYPE_DENSODRA74XMID 5012
+#define MACH_TYPE_MILD 5013
+#define MACH_TYPE_YLCM_MK2 5014
+#define MACH_TYPE_DS_CB 5015
+#define MACH_TYPE_EMPEROR 5016
+#define MACH_TYPE_ARTPEC 5017
+#define MACH_TYPE_DCIM 5018
+#define MACH_TYPE_WS1XX 5019
+#define MACH_TYPE_IPQ806X_AK01_1XX 5020
+#define MACH_TYPE_MGWACE_DEC 5021
+#define MACH_TYPE_W6000 5022
+#define MACH_TYPE_WATSON_FIB_PLUGIN 5023
+#define MACH_TYPE_MX6Q_TINYREX 5024
+#define MACH_TYPE_MX6S_TINYREX 5025
+#define MACH_TYPE_MX6Q_MODEROS 5026
+#define MACH_TYPE_AFI 5027
+#define MACH_TYPE_RCPRO 5028
+#define MACH_TYPE_ONBOX 5029
+#define MACH_TYPE_EXYNOS4412 5030
+#define MACH_TYPE_EXYNOS4413 5031
+#define MACH_TYPE_PELCO_DF20_EVT 5032
+#define MACH_TYPE_LION_DUG 5033
+#define MACH_TYPE_LIONP_DUG 5034
+#define MACH_TYPE_ESSE 5035
+#define MACH_TYPE_ILLINOIS 5036
+#define MACH_TYPE_TI8168KSIPOLARIS 5037
+#define MACH_TYPE_YSE_BOARD 5038
+#define MACH_TYPE_PELCO_HWE0_EVT 5039
+#define MACH_TYPE_PELCO_S2E_EVM 5040
+#define MACH_TYPE_PELCO_DRAGONFLY20 5041
+#define MACH_TYPE_PELCO_HAWKEYE 5042
+#define MACH_TYPE_ARM 5043
+#define MACH_TYPE_TCAM 5044
+#define MACH_TYPE_MX6Q_HOBBY 5045
+#define MACH_TYPE_H6067 5046
+#define MACH_TYPE_DENSODRA72XLOW 5047
+#define MACH_TYPE_MX6_UNETBIT 5048
+#define MACH_TYPE_BT_OAK 5049
+#define MACH_TYPE_BT500 5050
+#define MACH_TYPE_FARWATER_GEO 5051
+#define MACH_TYPE_YT2 5052
+#define MACH_TYPE_EH9000 5053
+#define MACH_TYPE_GVPU 5054
+#define MACH_TYPE_CEDEX 5055
+#define MACH_TYPE_NT450R5G 5056
+#define MACH_TYPE_MSA23XX 5057
+#define MACH_TYPE_OMAP3_MOSS 5058
+#define MACH_TYPE_KYEONGHAWOO 5059
+#define MACH_TYPE_GIRA_IM03 5060
+#define MACH_TYPE_EUROFUNK_AIIF 5061
+#define MACH_TYPE_BCU1 5062
+#define MACH_TYPE_DIYEFIS6410 5063
+#define MACH_TYPE_MX53_TURING 5064
+#define MACH_TYPE_MX6X_TURING 5065
+#define MACH_TYPE_MX6DL_TURING 5066
+#define MACH_TYPE_MX53_INDASH 5067
+#define MACH_TYPE_MX6Q_INDASH 5068
+#define MACH_TYPE_MX6DL_INDASH 5069
+#define MACH_TYPE_RTS_G6 5070
+#define MACH_TYPE_KA_TITAN 5071
+#define MACH_TYPE_CL_SOM_IMX7 5072
+#define MACH_TYPE_VVDN_MGSI_VSIS 5073
+#define MACH_TYPE_MX6Q_NANO 5074
+#define MACH_TYPE_PDU001 5075
+#define MACH_TYPE_CAB_PROYK 5076
+#define MACH_TYPE_KLIN 5077
+#define MACH_TYPE_ENMAN_STEUERBOX 5078
+#define MACH_TYPE_LS_STINGRAY 5079
+#define MACH_TYPE_IPDU 5080
+#define MACH_TYPE_LINDA 5081
+#define MACH_TYPE_MX6Q_OPENREX 5082
+#define MACH_TYPE_ON100 5083
+#define MACH_TYPE_EMINDS_RTU12 5084
+#define MACH_TYPE_EMINDS_AVL10 5085
+#define MACH_TYPE_MAIN_PLC_LME 5086
+#define MACH_TYPE_MSPX 5087
+#define MACH_TYPE_CGW_300 5088
+#define MACH_TYPE_MX7D_CICADA 5089
+#define MACH_TYPE_VIRT2REAL_DM365 5090
+#define MACH_TYPE_DM365_VIRT2REAL 5091
+#define MACH_TYPE_H6073 5092
+#define MACH_TYPE_GTGATEWAY 5093
+#define MACH_TYPE_XARINA_STANDARD 5094
+#define MACH_TYPE_NOVASOMS 5095
+#define MACH_TYPE_NOVASOMP 5096
+#define MACH_TYPE_NOVASOMU 5097
+#define MACH_TYPE_MX6Q_MPBD 5098
+#define MACH_TYPE_NCR_1930 5099
+#define MACH_TYPE_UAP301 5100
+#define MACH_TYPE_URT02 5101
+#define MACH_TYPE_ATC8 5102
+#define MACH_TYPE_IOT_GATEWAY 5103
+#define MACH_TYPE_HSM_PHOENIX 5104
+#define MACH_TYPE_MISSOURI 5105
+#define MACH_TYPE_REMARKABLE 5106
+#define MACH_TYPE_FA0113 5107
+#define MACH_TYPE_INNOVA_STATNETTAWM 5108
+#define MACH_TYPE_TEGRA3 5109
+#define MACH_TYPE_MALI400 5110
+#define MACH_TYPE_MALI450 5111
+#define MACH_TYPE_NASM25 5112
+#define MACH_TYPE_TOMATO 5113
+#define MACH_TYPE_OMAP3_MRC3D 5114
#endif
--- /dev/null
+if ARCH_ASPEED
+
+config SYS_ARCH
+ default "arm"
+
+config SYS_SOC
+ default "aspeed"
+
+config SYS_TEXT_BASE
+ default 0x00000000
+
+config ASPEED_AST2500
+ bool "Support Aspeed AST2500 SoC"
+ select CPU_ARM1176
+ help
+ The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
+ It is used as Board Management Controller on many server boards,
+ which is enabled by support of LPC and eSPI peripherals.
+
+config WDT_NUM
+ int "Number of Watchdog Timers"
+ default 3 if ASPEED_AST2500
+ help
+ The number of Watchdot Timers on a SoC.
+ AST2500 has three WDTsk earlier versions have two or fewer.
+
+source "arch/arm/mach-aspeed/ast2500/Kconfig"
+
+endif
--- /dev/null
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
+obj-$(CONFIG_ASPEED_AST2500) += ast2500/ ast2500-board.o
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+#include <dm/uclass.h>
+
+/*
+ * Second Watchdog Timer by default is configured
+ * to trigger secondary boot source.
+ */
+#define AST_2ND_BOOT_WDT 1
+
+/*
+ * Third Watchdog Timer by default is configured
+ * to toggle Flash address mode switch before reset.
+ */
+#define AST_FLASH_ADDR_DETECT_WDT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void lowlevel_init(void)
+{
+ /*
+ * These two watchdogs need to be stopped as soon as possible,
+ * otherwise the board might hang. By default they are set to
+ * a very short timeout and even simple debug write to serial
+ * console early in the init process might cause them to fire.
+ */
+ struct ast_wdt *flash_addr_wdt =
+ (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) *
+ AST_FLASH_ADDR_DETECT_WDT);
+
+ clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
+
+#ifndef CONFIG_FIRMWARE_2ND_BOOT
+ struct ast_wdt *sec_boot_wdt =
+ (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) *
+ AST_2ND_BOOT_WDT);
+
+ clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
+#endif
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct udevice *dev;
+ struct ram_info ram;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM FAIL1\r\n");
+ return ret;
+ }
+
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("DRAM FAIL2\r\n");
+ return ret;
+ }
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
--- /dev/null
+if ASPEED_AST2500
+
+config SYS_CPU
+ default "arm1176"
+
+config TARGET_EVB_AST2500
+ bool "Evb-AST2500"
+ help
+ Evb-AST2500 is Aspeed evaluation board for AST2500 chip.
+ It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
+ 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot,
+ 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs.
+
+source "board/aspeed/evb_ast2500/Kconfig"
+
+endif
--- /dev/null
+obj-y += clk_ast2500.o sdram_ast2500.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/scu_ast2500.h>
+
+int ast_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(aspeed_ast2500_scu), devp);
+}
+
+void *ast_get_scu(void)
+{
+ struct ast2500_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = ast_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->scu;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ *
+ * Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <ram.h>
+#include <regmap.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+#include <asm/arch/sdram_ast2500.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <dt-bindings/clock/ast2500-scu.h>
+
+/* These configuration parameters are taken from Aspeed SDK */
+#define DDR4_MR46_MODE 0x08000000
+#define DDR4_MR5_MODE 0x400
+#define DDR4_MR13_MODE 0x101
+#define DDR4_MR02_MODE 0x410
+#define DDR4_TRFC 0x45457188
+
+#define PHY_CFG_SIZE 15
+
+static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
+static const struct {
+ u32 index[PHY_CFG_SIZE];
+ u32 value[PHY_CFG_SIZE];
+} ddr4_phy_config = {
+ .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
+ .value = {
+ 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
+ 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
+ 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
+ },
+};
+
+#define SDRAM_MAX_SIZE (1024 * 1024 * 1024)
+#define SDRAM_MIN_SIZE (128 * 1024 * 1024)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Bandwidth configuration parameters for different SDRAM requests.
+ * These are hardcoded settings taken from Aspeed SDK.
+ */
+static const u32 ddr_max_grant_params[4] = {
+ 0x88448844, 0x24422288, 0x22222222, 0x22222222
+};
+
+/*
+ * These registers are not documented by Aspeed at all.
+ * All writes and reads are taken pretty much as is from SDK.
+ */
+struct ast2500_ddr_phy {
+ u32 phy[117];
+};
+
+struct dram_info {
+ struct ram_info info;
+ struct clk ddr_clk;
+ struct ast2500_sdrammc_regs *regs;
+ struct ast2500_scu *scu;
+ struct ast2500_ddr_phy *phy;
+ ulong clock_rate;
+};
+
+static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
+{
+ writel(0, &phy->phy[2]);
+ writel(0, &phy->phy[6]);
+ writel(0, &phy->phy[8]);
+ writel(0, &phy->phy[10]);
+ writel(0, &phy->phy[12]);
+ writel(0, &phy->phy[42]);
+ writel(0, &phy->phy[44]);
+
+ writel(0x86000000, &phy->phy[16]);
+ writel(0x00008600, &phy->phy[17]);
+ writel(0x80000000, &phy->phy[18]);
+ writel(0x80808080, &phy->phy[19]);
+
+ return 0;
+}
+
+static void ast2500_ddr_phy_init_process(struct dram_info *info)
+{
+ struct ast2500_sdrammc_regs *regs = info->regs;
+
+ writel(0, ®s->phy_ctrl[0]);
+ writel(0x4040, &info->phy->phy[51]);
+
+ writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]);
+ while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
+ ;
+ writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
+ ®s->phy_ctrl[0]);
+}
+
+static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
+{
+ writel(0, &info->regs->phy_ctrl[0]);
+ writel((vref << 8) | 0x6, &info->phy->phy[48]);
+ ast2500_ddr_phy_init_process(info);
+}
+
+static int ast2500_ddr_cbr_test(struct dram_info *info)
+{
+ struct ast2500_sdrammc_regs *regs = info->regs;
+ int i;
+ const u32 test_params = SDRAM_TEST_EN
+ | SDRAM_TEST_ERRSTOP
+ | SDRAM_TEST_TWO_MODES;
+ int ret = 0;
+
+ writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
+ (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing);
+ writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr);
+ writel(0xff00ff00, ®s->test_init_val);
+ writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
+ SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl);
+
+ while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
+ ;
+
+ if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
+ ret = -EIO;
+ } else {
+ for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
+ writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
+ ®s->ecc_test_ctrl);
+ while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
+ ;
+ if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
+ ret = -EIO;
+ break;
+ }
+ }
+ }
+
+ writel(0, ®s->refresh_timing);
+ writel(0, ®s->ecc_test_ctrl);
+
+ return ret;
+}
+
+static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
+{
+ int i;
+ int vref_min = 0xff;
+ int vref_max = 0;
+ int range_size = 0;
+
+ for (i = 1; i < 0x40; ++i) {
+ int res;
+
+ ast2500_sdrammc_set_vref(info, i);
+ res = ast2500_ddr_cbr_test(info);
+ if (res < 0) {
+ if (range_size > 0)
+ break;
+ } else {
+ ++range_size;
+ vref_min = min(vref_min, i);
+ vref_max = max(vref_max, i);
+ }
+ }
+
+ /* Pick average setting */
+ ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
+
+ return 0;
+}
+
+static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
+{
+ size_t vga_mem_size_base = 8 * 1024 * 1024;
+ u32 vga_hwconf = (readl(&info->scu->hwstrap)
+ >> SCU_HWSTRAP_VGAMEM_SHIFT)
+ & SCU_HWSTRAP_VGAMEM_MASK;
+
+ return vga_mem_size_base << vga_hwconf;
+}
+
+/*
+ * Find out RAM size and save it in dram_info
+ *
+ * The procedure is taken from Aspeed SDK
+ */
+static void ast2500_sdrammc_calc_size(struct dram_info *info)
+{
+ /* The controller supports 128/256/512/1024 MB ram */
+ size_t ram_size = SDRAM_MIN_SIZE;
+ const int write_test_offset = 0x100000;
+ u32 test_pattern = 0xdeadbeef;
+ u32 cap_param = SDRAM_CONF_CAP_1024M;
+ u32 refresh_timing_param = DDR4_TRFC;
+ const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+
+ for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
+ ram_size >>= 1) {
+ writel(test_pattern, write_addr_base + (ram_size >> 1));
+ test_pattern = (test_pattern >> 4) | (test_pattern << 28);
+ }
+
+ /* One last write to overwrite all wrapped values */
+ writel(test_pattern, write_addr_base);
+
+ /* Reset the pattern and see which value was really written */
+ test_pattern = 0xdeadbeef;
+ for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
+ ram_size >>= 1) {
+ if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
+ break;
+
+ --cap_param;
+ refresh_timing_param >>= 8;
+ test_pattern = (test_pattern >> 4) | (test_pattern << 28);
+ }
+
+ clrsetbits_le32(&info->regs->ac_timing[1],
+ (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
+ ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
+ << SDRAM_AC_TRFC_SHIFT));
+
+ info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
+ clrsetbits_le32(&info->regs->config,
+ (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
+ ((cap_param & SDRAM_CONF_CAP_MASK)
+ << SDRAM_CONF_CAP_SHIFT));
+}
+
+static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
+{
+ int i;
+ const u32 power_control = SDRAM_PCR_CKE_EN
+ | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
+ | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
+ | SDRAM_PCR_RESETN_DIS
+ | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
+ const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
+#ifdef CONFIG_DUALX8_RAM
+ | SDRAM_CONF_DUALX8
+#endif
+ | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
+ int ret;
+
+ writel(conf, &info->regs->config);
+ for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
+ writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
+
+ writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
+ writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
+ writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
+ writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
+
+ for (i = 0; i < PHY_CFG_SIZE; ++i) {
+ writel(ddr4_phy_config.value[i],
+ &info->phy->phy[ddr4_phy_config.index[i]]);
+ }
+
+ writel(power_control, &info->regs->power_control);
+
+ ast2500_ddr_phy_init_process(info);
+
+ ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
+ if (ret < 0) {
+ debug("Vref calibration failed!\n");
+ return ret;
+ }
+
+ writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
+ | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
+ &info->regs->refresh_timing);
+
+ setbits_le32(&info->regs->power_control,
+ SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
+
+ ast2500_sdrammc_calc_size(info);
+
+ setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
+ while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
+ ;
+ setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
+
+ writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
+
+ /* Enable all requests except video & display */
+ writel(SDRAM_REQ_USB20_EHCI1
+ | SDRAM_REQ_USB20_EHCI2
+ | SDRAM_REQ_CPU
+ | SDRAM_REQ_AHB2
+ | SDRAM_REQ_AHB
+ | SDRAM_REQ_MAC0
+ | SDRAM_REQ_MAC1
+ | SDRAM_REQ_PCIE
+ | SDRAM_REQ_XDMA
+ | SDRAM_REQ_ENCRYPTION
+ | SDRAM_REQ_VIDEO_FLAG
+ | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
+ | SDRAM_REQ_2D_RW
+ | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
+
+ return 0;
+}
+
+static void ast2500_sdrammc_unlock(struct dram_info *info)
+{
+ writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
+ while (!readl(&info->regs->protection_key))
+ ;
+}
+
+static void ast2500_sdrammc_lock(struct dram_info *info)
+{
+ writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
+ while (readl(&info->regs->protection_key))
+ ;
+}
+
+static int ast2500_sdrammc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
+ struct ast2500_sdrammc_regs *regs = priv->regs;
+ int i;
+ int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
+
+ if (ret) {
+ debug("DDR:No CLK\n");
+ return ret;
+ }
+
+ priv->scu = ast_get_scu();
+ if (IS_ERR(priv->scu)) {
+ debug("%s(): can't get SCU\n", __func__);
+ return PTR_ERR(priv->scu);
+ }
+
+ clk_set_rate(&priv->ddr_clk, priv->clock_rate);
+ ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
+ if (ret) {
+ debug("%s(): SDRAM reset failed\n", __func__);
+ return ret;
+ }
+
+ ast2500_sdrammc_unlock(priv);
+
+ writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
+ ®s->power_control);
+ writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key);
+
+ /* Mask all requests except CPU and AHB during PHY init */
+ writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask);
+
+ for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
+ writel(ddr_max_grant_params[i], ®s->max_grant_len[i]);
+
+ setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
+
+ ast2500_sdrammc_init_phy(priv->phy);
+ if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
+ ast2500_sdrammc_init_ddr4(priv);
+ } else {
+ debug("Unsupported DRAM3\n");
+ return -EINVAL;
+ }
+
+ clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
+ ast2500_sdrammc_lock(priv);
+
+ return 0;
+}
+
+static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct regmap *map;
+ int ret;
+
+ ret = regmap_init_mem(dev, &map);
+ if (ret)
+ return ret;
+
+ priv->regs = regmap_get_range(map, 0);
+ priv->phy = regmap_get_range(map, 1);
+
+ priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 0);
+
+ if (!priv->clock_rate) {
+ debug("DDR Clock Rate not defined\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops ast2500_sdrammc_ops = {
+ .get_info = ast2500_sdrammc_get_info,
+};
+
+static const struct udevice_id ast2500_sdrammc_ids[] = {
+ { .compatible = "aspeed,ast2500-sdrammc" },
+ { }
+};
+
+U_BOOT_DRIVER(sdrammc_ast2500) = {
+ .name = "aspeed_ast2500_sdrammc",
+ .id = UCLASS_RAM,
+ .of_match = ast2500_sdrammc_ids,
+ .ops = &ast2500_sdrammc_ops,
+ .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
+ .probe = ast2500_sdrammc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+};
--- /dev/null
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+
+void wdt_stop(struct ast_wdt *wdt)
+{
+ clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
+}
+
+void wdt_start(struct ast_wdt *wdt, u32 timeout)
+{
+ writel(timeout, &wdt->counter_reload_val);
+ writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
+ /*
+ * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
+ * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
+ * read-only
+ */
+ setbits_le32(&wdt->ctrl,
+ WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
+}
+
+struct ast_wdt *ast_get_wdt(u8 wdt_number)
+{
+ if (wdt_number > CONFIG_WDT_NUM - 1)
+ return ERR_PTR(-EINVAL);
+
+ return (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) * wdt_number);
+}
+
+int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
+{
+#ifdef CONFIG_ASPEED_AST2500
+ if (!mask)
+ return -EINVAL;
+
+ writel(mask, &wdt->reset_mask);
+ clrbits_le32(&wdt->ctrl,
+ WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT);
+ wdt_start(wdt, 1);
+
+ /* Wait for WDT to reset */
+ while (readl(&wdt->ctrl) & WDT_CTRL_EN)
+ ;
+ wdt_stop(wdt);
+
+ return 0;
+#else
+ return -EINVAL;
+#endif
+}
+++ /dev/null
-config LITESOM
- bool
- select MX6UL
- select DM
- select DM_THERMAL
- select SUPPORT_SPL
+++ /dev/null
-# (C) Copyright 2016 Grinn
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := litesom.o
if ARCH_MVEBU
+config HAVE_MVEBU_EFUSE
+ bool
+ default n
+
config ARMADA_32BIT
bool
select CPU_V7
config ARMADA_38X
bool
select ARMADA_32BIT
+ select HAVE_MVEBU_EFUSE
config ARMADA_XP
bool
config SYS_SOC
default "mvebu"
+config MVEBU_EFUSE
+ bool "Enable eFuse support"
+ default n
+ depends on HAVE_MVEBU_EFUSE
+ help
+ Enable support for reading and writing eFuses on mvebu SoCs.
+
+config MVEBU_EFUSE_FAKE
+ bool "Fake eFuse access (dry run)"
+ default n
+ depends on MVEBU_EFUSE
+ help
+ This enables a "dry run" mode where eFuses are not really programmed.
+ Instead the eFuse accesses are emulated by writing to and reading
+ from a memory block.
+ This is can be used for testing prog scripts.
+
+config SECURED_MODE_IMAGE
+ bool "Build image for trusted boot"
+ default false
+ depends on 88F6820
+ help
+ Build an image that employs the ARMADA SoC's trusted boot framework
+ for securely booting images.
+
+config SECURED_MODE_CSK_INDEX
+ int "Index of active CSK"
+ default 0
+ depends on SECURED_MODE_IMAGE
+
endif
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
+obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
endif # CONFIG_SPL_BUILD
obj-y += gpio.o
obj-y += mbus.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Reinhard Pfau <reinhard.pfau@gdsys.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/efuse.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#if defined(CONFIG_MVEBU_EFUSE_FAKE)
+#define DRY_RUN
+#else
+#undef DRY_RUN
+#endif
+
+#define MBUS_EFUSE_BASE 0xF6000000
+#define MBUS_EFUSE_SIZE BIT(20)
+
+#define MVEBU_EFUSE_CONTROL (MVEBU_REGISTER(0xE4008))
+
+enum {
+ MVEBU_EFUSE_CTRL_PROGRAM_ENABLE = (1 << 31),
+};
+
+struct mvebu_hd_efuse {
+ u32 bits_31_0;
+ u32 bits_63_32;
+ u32 bit64;
+ u32 reserved0;
+};
+
+#ifndef DRY_RUN
+static struct mvebu_hd_efuse *efuses =
+ (struct mvebu_hd_efuse *)(MBUS_EFUSE_BASE + 0xF9000);
+#else
+static struct mvebu_hd_efuse efuses[EFUSE_LINE_MAX + 1];
+#endif
+
+static int efuse_initialised;
+
+static struct mvebu_hd_efuse *get_efuse_line(int nr)
+{
+ if (nr < 0 || nr > 63 || !efuse_initialised)
+ return NULL;
+
+ return efuses + nr;
+}
+
+static void enable_efuse_program(void)
+{
+#ifndef DRY_RUN
+ setbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_CTRL_PROGRAM_ENABLE);
+#endif
+}
+
+static void disable_efuse_program(void)
+{
+#ifndef DRY_RUN
+ clrbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_CTRL_PROGRAM_ENABLE);
+#endif
+}
+
+static int do_prog_efuse(struct mvebu_hd_efuse *efuse,
+ struct efuse_val *new_val, u32 mask0, u32 mask1)
+{
+ struct efuse_val val;
+
+ val.dwords.d[0] = readl(&efuse->bits_31_0);
+ val.dwords.d[1] = readl(&efuse->bits_63_32);
+ val.lock = readl(&efuse->bit64);
+
+ if (val.lock & 1)
+ return -EPERM;
+
+ val.dwords.d[0] |= (new_val->dwords.d[0] & mask0);
+ val.dwords.d[1] |= (new_val->dwords.d[1] & mask1);
+ val.lock |= new_val->lock;
+
+ writel(val.dwords.d[0], &efuse->bits_31_0);
+ mdelay(1);
+ writel(val.dwords.d[1], &efuse->bits_63_32);
+ mdelay(1);
+ writel(val.lock, &efuse->bit64);
+ mdelay(5);
+
+ return 0;
+}
+
+static int prog_efuse(int nr, struct efuse_val *new_val, u32 mask0, u32 mask1)
+{
+ struct mvebu_hd_efuse *efuse;
+ int res = 0;
+
+ res = mvebu_efuse_init_hw();
+ if (res)
+ return res;
+
+ efuse = get_efuse_line(nr);
+ if (!efuse)
+ return -ENODEV;
+
+ if (!new_val)
+ return -EINVAL;
+
+ /* only write a fuse line with lock bit */
+ if (!new_val->lock)
+ return -EINVAL;
+
+ /* according to specs ECC protection bits must be 0 on write */
+ if (new_val->bytes.d[7] & 0xFE)
+ return -EINVAL;
+
+ if (!new_val->dwords.d[0] && !new_val->dwords.d[1] && (mask0 | mask1))
+ return 0;
+
+ enable_efuse_program();
+
+ res = do_prog_efuse(efuse, new_val, mask0, mask1);
+
+ disable_efuse_program();
+
+ return res;
+}
+
+int mvebu_efuse_init_hw(void)
+{
+ int ret;
+
+ if (efuse_initialised)
+ return 0;
+
+ ret = mvebu_mbus_add_window_by_id(
+ CPU_TARGET_SATA23_DFX, 0xA, MBUS_EFUSE_BASE, MBUS_EFUSE_SIZE);
+
+ if (ret)
+ return ret;
+
+ efuse_initialised = 1;
+
+ return 0;
+}
+
+int mvebu_read_efuse(int nr, struct efuse_val *val)
+{
+ struct mvebu_hd_efuse *efuse;
+ int res;
+
+ res = mvebu_efuse_init_hw();
+ if (res)
+ return res;
+
+ efuse = get_efuse_line(nr);
+ if (!efuse)
+ return -ENODEV;
+
+ if (!val)
+ return -EINVAL;
+
+ val->dwords.d[0] = readl(&efuse->bits_31_0);
+ val->dwords.d[1] = readl(&efuse->bits_63_32);
+ val->lock = readl(&efuse->bit64);
+ return 0;
+}
+
+int mvebu_write_efuse(int nr, struct efuse_val *val)
+{
+ return prog_efuse(nr, val, ~0, ~0);
+}
+
+int mvebu_lock_efuse(int nr)
+{
+ struct efuse_val val = {
+ .lock = 1,
+ };
+
+ return prog_efuse(nr, &val, 0, 0);
+}
+
+/*
+ * wrapper funcs providing the fuse API
+ *
+ * we use the following mapping:
+ * "bank" -> eFuse line
+ * "word" -> 0: bits 0-31
+ * 1: bits 32-63
+ * 2: bit 64 (lock)
+ */
+
+static struct efuse_val prog_val;
+static int valid_prog_words;
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ struct efuse_val fuse_line;
+ int res;
+
+ if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2)
+ return -EINVAL;
+
+ res = mvebu_read_efuse(bank, &fuse_line);
+ if (res)
+ return res;
+
+ if (word < 2)
+ *val = fuse_line.dwords.d[word];
+ else
+ *val = fuse_line.lock;
+
+ return res;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ /* not supported */
+ return -ENOSYS;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ int res = 0;
+
+ /*
+ * NOTE: Fuse line should be written as whole.
+ * So how can we do that with this API?
+ * For now: remember values for word == 0 and word == 1 and write the
+ * whole line when word == 2.
+ * This implies that we always require all 3 fuse prog cmds (one for
+ * for each word) to write a single fuse line.
+ * Exception is a single write to word 2 which will lock the fuse line.
+ *
+ * Hope that will be OK.
+ */
+
+ if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2)
+ return -EINVAL;
+
+ if (word < 2) {
+ prog_val.dwords.d[word] = val;
+ valid_prog_words |= (1 << word);
+ } else if ((valid_prog_words & 3) == 0 && val) {
+ res = mvebu_lock_efuse(bank);
+ valid_prog_words = 0;
+ } else if ((valid_prog_words & 3) != 3 || !val) {
+ res = -EINVAL;
+ } else {
+ prog_val.lock = val != 0;
+ res = mvebu_write_efuse(bank, &prog_val);
+ valid_prog_words = 0;
+ }
+
+ return res;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ /* not supported */
+ return -ENOSYS;
+}
CPU_TARGET_ETH01 = 0x7,
CPU_TARGET_PCIE13 = 0x8,
CPU_TARGET_SASRAM = 0x9,
+ CPU_TARGET_SATA01 = 0xa, /* A38X */
CPU_TARGET_NAND = 0xd,
+ CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
};
enum cpu_attrib {
--- /dev/null
+/*
+ * Copyright (C) 2015 Reinhard Pfau <reinhard.pfau@gdsys.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MVEBU_EFUSE_H
+#define _MVEBU_EFUSE_H
+
+#include <common.h>
+
+struct efuse_val {
+ union {
+ struct {
+ u8 d[8];
+ } bytes;
+ struct {
+ u16 d[4];
+ } words;
+ struct {
+ u32 d[2];
+ } dwords;
+ };
+ u32 lock;
+};
+
+#if defined(CONFIG_ARMADA_38X)
+
+enum efuse_line {
+ EFUSE_LINE_SECURE_BOOT = 24,
+ EFUSE_LINE_PUBKEY_DIGEST_0 = 26,
+ EFUSE_LINE_PUBKEY_DIGEST_1 = 27,
+ EFUSE_LINE_PUBKEY_DIGEST_2 = 28,
+ EFUSE_LINE_PUBKEY_DIGEST_3 = 29,
+ EFUSE_LINE_PUBKEY_DIGEST_4 = 30,
+ EFUSE_LINE_CSK_0_VALID = 31,
+ EFUSE_LINE_CSK_1_VALID = 32,
+ EFUSE_LINE_CSK_2_VALID = 33,
+ EFUSE_LINE_CSK_3_VALID = 34,
+ EFUSE_LINE_CSK_4_VALID = 35,
+ EFUSE_LINE_CSK_5_VALID = 36,
+ EFUSE_LINE_CSK_6_VALID = 37,
+ EFUSE_LINE_CSK_7_VALID = 38,
+ EFUSE_LINE_CSK_8_VALID = 39,
+ EFUSE_LINE_CSK_9_VALID = 40,
+ EFUSE_LINE_CSK_10_VALID = 41,
+ EFUSE_LINE_CSK_11_VALID = 42,
+ EFUSE_LINE_CSK_12_VALID = 43,
+ EFUSE_LINE_CSK_13_VALID = 44,
+ EFUSE_LINE_CSK_14_VALID = 45,
+ EFUSE_LINE_CSK_15_VALID = 46,
+ EFUSE_LINE_FLASH_ID = 47,
+ EFUSE_LINE_BOX_ID = 48,
+
+ EFUSE_LINE_MIN = 0,
+ EFUSE_LINE_MAX = 63,
+};
+
+#endif
+
+int mvebu_efuse_init_hw(void);
+
+int mvebu_read_efuse(int nr, struct efuse_val *val);
+
+int mvebu_write_efuse(int nr, struct efuse_val *val);
+
+int mvebu_lock_efuse(int nr);
+
+#endif
#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
#define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
+#define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000))
#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#include "ctrl_pex.h"
#include "sys_env_lib.h"
+__weak void board_pex_config(void)
+{
+ /* nothing in this weak default implementation */
+}
+
int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
{
u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
/* Support gen1/gen2 */
DEBUG_INIT_FULL_S("Support gen1/gen2\n");
+
+ board_pex_config();
+
next_busno = 0;
mdelay(150);
int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
+void board_pex_config(void);
+
#endif
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static u32 get_boot_device(void)
{
u32 val;
if AM33XX
+config AM33XX_CHILISOM
+ bool
+ select SUPPORT_SPL
+
choice
prompt "AM33xx board select"
optional
For more information, visit: http://birdland.com/oem
+config TARGET_CHILIBOARD
+ bool "Grinn chiliBoard"
+ select AM33XX_CHILISOM
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+
config TARGET_CM_T335
bool "Support cm_t335"
select DM
obj-y += mux.o
obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
+
+obj-$(CONFIG_AM33XX_CHILISOM) += chilisom.o
--- /dev/null
+/*
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include <spl.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void chilisom_enable_pin_mux(void)
+{
+ /* chilisom pin mux */
+ configure_module_pin_mux(nand_pin_mux);
+}
+
+static const struct ddr_data ddr3_chilisom_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_chilisom_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .ocp_config = 0x00141414,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+void chilisom_spl_board_init(void)
+{
+ int mpu_vdd;
+ int usb_cur_lim;
+
+ enable_i2c0_pin_mux();
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_POWER_PATH,
+ usb_cur_lim,
+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set LDO3 to 1.8V and LDO4 to 3.3V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr_chilisom = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr_chilisom;
+}
+
+const struct ctrl_ioregs ioregs_chilisom = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(400, &ioregs_chilisom,
+ &ddr3_chilisom_data,
+ &ddr3_chilisom_cmd_ctrl_data,
+ &ddr3_chilisom_emif_reg_data, 0);
+}
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
cpu_s = "35XX";
break;
}
- max_clk = "600 Mhz";
+ max_clk = "600 MHz";
break;
case CPU_OMAP36XX:
- cpu_family_s = "OMAP";
switch (get_cpu_type()) {
+ case AM3703:
+ cpu_family_s = "AM";
+ cpu_s = "3703";
+ max_clk = "800 MHz";
+ break;
+ case AM3703_1GHZ:
+ cpu_family_s = "AM";
+ cpu_s = "3703";
+ max_clk = "1 GHz";
+ break;
+ case AM3715:
+ cpu_family_s = "AM";
+ cpu_s = "3715";
+ max_clk = "800 MHz";
+ break;
+ case AM3715_1GHZ:
+ cpu_family_s = "AM";
+ cpu_s = "3715";
+ max_clk = "1 GHz";
+ break;
+ case OMAP3725:
+ cpu_family_s = "OMAP";
+ cpu_s = "3625/3725";
+ max_clk = "800 MHz";
+ break;
+ case OMAP3725_1GHZ:
+ cpu_family_s = "OMAP";
+ cpu_s = "3625/3725";
+ max_clk = "1 GHz";
+ break;
case OMAP3730:
+ cpu_family_s = "OMAP";
cpu_s = "3630/3730";
+ max_clk = "800 MHz";
+ break;
+ case OMAP3730_1GHZ:
+ cpu_family_s = "OMAP";
+ cpu_s = "3630/3730";
+ max_clk = "1 GHz";
break;
default:
+ cpu_family_s = "OMAP/AM";
cpu_s = "36XX/37XX";
+ max_clk = "1 GHz";
break;
}
- max_clk = "1 Ghz";
+
break;
default:
cpu_family_s = "OMAP";
cpu_s = "35XX";
- max_clk = "600 Mhz";
+ max_clk = "600 MHz";
}
switch (get_device_type()) {
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
-#define RCC_CR_HSION (1 << 0)
-#define RCC_CR_HSEON (1 << 16)
-#define RCC_CR_HSERDY (1 << 17)
-#define RCC_CR_HSEBYP (1 << 18)
-#define RCC_CR_CSSON (1 << 19)
-#define RCC_CR_PLLON (1 << 24)
-#define RCC_CR_PLLRDY (1 << 25)
+#define RCC_CR_HSION BIT(0)
+#define RCC_CR_HSEON BIT(16)
+#define RCC_CR_HSERDY BIT(17)
+#define RCC_CR_HSEBYP BIT(18)
+#define RCC_CR_CSSON BIT(19)
+#define RCC_CR_PLLON BIT(24)
+#define RCC_CR_PLLRDY BIT(25)
-#define RCC_PLLCFGR_PLLM_MASK 0x3F
-#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK 0x30000
-#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
-#define RCC_PLLCFGR_PLLSRC (1 << 22)
-#define RCC_PLLCFGR_PLLM_SHIFT 0
-#define RCC_PLLCFGR_PLLN_SHIFT 6
-#define RCC_PLLCFGR_PLLP_SHIFT 16
-#define RCC_PLLCFGR_PLLQ_SHIFT 24
+#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
+#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
+#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
+#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
+#define RCC_PLLCFGR_PLLSRC BIT(22)
+#define RCC_PLLCFGR_PLLM_SHIFT 0
+#define RCC_PLLCFGR_PLLN_SHIFT 6
+#define RCC_PLLCFGR_PLLP_SHIFT 16
+#define RCC_PLLCFGR_PLLQ_SHIFT 24
-#define RCC_CFGR_AHB_PSC_MASK 0xF0
-#define RCC_CFGR_APB1_PSC_MASK 0x1C00
-#define RCC_CFGR_APB2_PSC_MASK 0xE000
-#define RCC_CFGR_SW0 (1 << 0)
-#define RCC_CFGR_SW1 (1 << 1)
-#define RCC_CFGR_SW_MASK 0x3
-#define RCC_CFGR_SW_HSI 0
-#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
-#define RCC_CFGR_SWS0 (1 << 2)
-#define RCC_CFGR_SWS1 (1 << 3)
-#define RCC_CFGR_SWS_MASK 0xC
-#define RCC_CFGR_SWS_HSI 0
-#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT 4
-#define RCC_CFGR_PPRE1_SHIFT 10
-#define RCC_CFGR_PPRE2_SHIFT 13
-
-#define RCC_APB1ENR_PWREN (1 << 28)
-
-/*
- * RCC USART specific definitions
- */
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
+#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
+#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
+#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
+#define RCC_CFGR_SW0 BIT(0)
+#define RCC_CFGR_SW1 BIT(1)
+#define RCC_CFGR_SW_MASK GENMASK(1, 0)
+#define RCC_CFGR_SW_HSI 0
+#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
+#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
+#define RCC_CFGR_SWS0 BIT(2)
+#define RCC_CFGR_SWS1 BIT(3)
+#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
+#define RCC_CFGR_SWS_HSI 0
+#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT 4
+#define RCC_CFGR_PPRE1_SHIFT 10
+#define RCC_CFGR_PPRE2_SHIFT 13
/*
* Offsets of some PWR registers
*/
-#define PWR_CR1_ODEN (1 << 16)
-#define PWR_CR1_ODSWEN (1 << 17)
-#define PWR_CSR1_ODRDY (1 << 16)
-#define PWR_CSR1_ODSWRDY (1 << 17)
-
-
-/*
- * RCC GPIO specific definitions
- */
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
struct pll_psc {
u8 pll_m;
u8 apb2_psc;
};
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
+#define AHB_PSC_1 0
+#define AHB_PSC_2 0x8
+#define AHB_PSC_4 0x9
+#define AHB_PSC_8 0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_128 0xD
+#define AHB_PSC_256 0xE
+#define AHB_PSC_512 0xF
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
+#define APB_PSC_1 0
+#define APB_PSC_2 0x4
+#define APB_PSC_4 0x5
+#define APB_PSC_8 0x6
+#define APB_PSC_16 0x7
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
{
switch (peripheral) {
case USART1_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
+ setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
break;
case GPIO_A_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
break;
case GPIO_B_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
break;
case GPIO_C_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
break;
case GPIO_D_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
break;
case GPIO_E_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
break;
case GPIO_F_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
break;
case GPIO_G_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
break;
case GPIO_H_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
break;
case GPIO_I_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
break;
case GPIO_J_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
break;
case GPIO_K_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
+ break;
+ case SYSCFG_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
+ break;
+ case TIMER2_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
+ break;
+ case FMC_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
+ break;
+ case STMMAC_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
+ break;
+ case QSPI_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_QSPI_EN);
break;
default:
break;
#include <common.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
+#include <asm/arch/stm32_defs.h>
#include <asm/arch/gpt.h>
-#include <asm/arch/rcc.h>
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ)
int timer_init(void)
{
/* Timer2 clock configuration */
- setbits_le32(RCC_BASE + RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
+ clock_setup(TIMER2_CLOCK_CFG);
/* Stop the timer */
writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
ifdef CONFIG_SPL_BUILD
+obj-y += boards.o
obj-y += spl_board_init.o
obj-y += memconf.o
obj-y += bcu/
endif
-obj-y += boards.o
obj-y += soc-info.o
obj-y += boot-mode/
obj-y += clk/
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
+#include <linux/sizes.h>
-#include "../init.h"
+#include "../soc-info.h"
#include "ddrmphy-regs.h"
/* Select either decimal or hexadecimal */
/* field separator */
#define FS " "
-static void __iomem *get_phy_base(int ch)
-{
- return (void __iomem *)(0x5b830000 + ch * 0x00200000);
-}
-
-static int get_nr_ch(void)
-{
- const struct uniphier_board_data *bd = uniphier_get_board_param();
-
- return bd->dram_ch[2].size ? 3 : 2;
-}
-
-static int get_nr_datx8(int ch)
-{
- const struct uniphier_board_data *bd = uniphier_get_board_param();
-
- return bd->dram_ch[ch].width / 8;
-}
+#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
+
+#define UNIPHIER_MAX_NR_DDRMPHY 3
+
+struct uniphier_ddrmphy_param {
+ unsigned int soc_id;
+ unsigned int nr_phy;
+ struct {
+ resource_size_t base;
+ unsigned int nr_zq;
+ unsigned int nr_dx;
+ } phy[UNIPHIER_MAX_NR_DDRMPHY];
+};
+
+static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .nr_phy = 3,
+ .phy = {
+ { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .nr_phy = 3,
+ .phy = {
+ { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
+ },
+ },
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
static void print_bdl(void __iomem *reg, int n)
{
printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
}
-static void dump_loop(void (*callback)(void __iomem *))
+static void dump_loop(const struct uniphier_ddrmphy_param *param,
+ void (*callback)(void __iomem *))
{
- int ch, dx, nr_ch, nr_dx;
- void __iomem *dx_base;
-
- nr_ch = get_nr_ch();
+ void __iomem *phy_base, *dx_base;
+ int phy, dx;
- for (ch = 0; ch < nr_ch; ch++) {
- dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
- nr_dx = get_nr_datx8(ch);
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+ dx_base = phy_base + MPHY_DX_BASE;
- for (dx = 0; dx < nr_dx; dx++) {
- printf("CH%dDX%d:", ch, dx);
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
+ printf("PHY%dDX%d:", phy, dx);
(*callback)(dx_base);
- dx_base += DMPHY_DX_STRIDE;
+ dx_base += MPHY_DX_STRIDE;
printf("\n");
}
+
+ iounmap(phy_base);
}
}
-static void zq_dump(void)
+static void zq_dump(const struct uniphier_ddrmphy_param *param)
{
- int ch, zq, nr_ch, nr_zq, i;
- void __iomem *zq_base;
- u32 dr, pr;
+ void __iomem *phy_base, *zq_base;
+ u32 val;
+ int phy, zq, i;
printf("\n--- Impedance Data ---\n");
- printf(" ZPD ZPU OPD OPU ZDV ODV\n");
+ printf(" ZPD ZPU OPD OPU ZDV ODV\n");
- nr_ch = get_nr_ch();
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+ zq_base = phy_base + MPHY_ZQ_BASE;
- for (ch = 0; ch < nr_ch; ch++) {
- zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
- nr_zq = 3;
+ for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
+ printf("PHY%dZQ%d:", phy, zq);
- for (zq = 0; zq < nr_zq; zq++) {
- printf("CH%dZQ%d:", ch, zq);
-
- dr = readl(zq_base + DMPHY_ZQ_DR);
+ val = readl(zq_base + MPHY_ZQ_DR);
for (i = 0; i < 4; i++) {
- printf(FS PRINTF_FORMAT, dr & 0x7f);
- dr >>= 7;
+ printf(FS PRINTF_FORMAT, val & 0x7f);
+ val >>= 7;
}
- pr = readl(zq_base + DMPHY_ZQ_PR);
+ val = readl(zq_base + MPHY_ZQ_PR);
for (i = 0; i < 2; i++) {
- printf(FS PRINTF_FORMAT, pr & 0xf);
- pr >>= 4;
+ printf(FS PRINTF_FORMAT, val & 0xf);
+ val >>= 4;
}
- zq_base += DMPHY_ZQ_STRIDE;
+ zq_base += MPHY_ZQ_STRIDE;
printf("\n");
}
+
+ iounmap(phy_base);
}
}
static void __wbdl_dump(void __iomem *dx_base)
{
- print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
- print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
- print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
+ print_bdl(dx_base + MPHY_DX_BDLR0, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR1, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR2, 2);
printf(FS "(+" PRINTF_FORMAT ")",
- readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
+ readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
}
-static void wbdl_dump(void)
+static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
{
printf("\n--- Write Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
- dump_loop(&__wbdl_dump);
+ dump_loop(param, &__wbdl_dump);
}
static void __rbdl_dump(void __iomem *dx_base)
{
- print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
- print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
- print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
+ print_bdl(dx_base + MPHY_DX_BDLR3, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR4, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR5, 1);
printf(FS "(+" PRINTF_FORMAT ")",
- (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
+ (readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
printf(FS "(+" PRINTF_FORMAT ")",
- (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
+ (readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
}
-static void rbdl_dump(void)
+static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
{
printf("\n--- Read Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
- dump_loop(&__rbdl_dump);
+ dump_loop(param, &__rbdl_dump);
}
static void __wld_dump(void __iomem *dx_base)
{
int rank;
- u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
- u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+ u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + MPHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
}
}
-static void wld_dump(void)
+static void wld_dump(const struct uniphier_ddrmphy_param *param)
{
printf("\n--- Write Leveling Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(&__wld_dump);
+ dump_loop(param, &__wld_dump);
}
static void __dqsgd_dump(void __iomem *dx_base)
{
int rank;
- u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
- u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+ u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + MPHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
}
}
-static void dqsgd_dump(void)
+static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
{
printf("\n--- DQS Gating Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(&__dqsgd_dump);
+ dump_loop(param, &__dqsgd_dump);
}
static void __mdl_dump(void __iomem *dx_base)
{
int i;
- u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
+ u32 mdl = readl(dx_base + MPHY_DX_MDLR);
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-static void mdl_dump(void)
+static void mdl_dump(const struct uniphier_ddrmphy_param *param)
{
printf("\n--- Master Delay Line ---\n");
- printf(" IPRD TPRD MDLD\n");
+ printf(" IPRD TPRD MDLD\n");
- dump_loop(&__mdl_dump);
+ dump_loop(param, &__mdl_dump);
}
#define REG_DUMP(x) \
- { int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
printf("%3d: %-10s: %p : %08x\n", \
- ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
+ ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
#define DX_REG_DUMP(dx, x) \
- { int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
- DMPHY_DX_## x; \
+ { int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
+ MPHY_DX_## x; \
void __iomem *reg = phy_base + ofst; \
printf("%3d: DX%d%-7s: %p : %08x\n", \
- ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
+ ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
-static void reg_dump(void)
+static void reg_dump(const struct uniphier_ddrmphy_param *param)
{
- int ch, dx, nr_ch, nr_dx;
void __iomem *phy_base;
+ int phy, dx;
- printf("\n--- DDR PHY registers ---\n");
+ printf("\n--- DDR Multi PHY registers ---\n");
- nr_ch = get_nr_ch();
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
- for (ch = 0; ch < nr_ch; ch++) {
- phy_base = get_phy_base(ch);
- nr_dx = get_nr_datx8(ch);
-
- printf("== Ch%d ==\n", ch);
+ printf("== PHY%d (base: %08x) ==\n", phy,
+ ptr_to_uint(phy_base));
printf(" No: Name : Address : Data\n");
REG_DUMP(RIDR);
REG_DUMP(MR2);
REG_DUMP(MR3);
- for (dx = 0; dx < nr_dx; dx++) {
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
DX_REG_DUMP(dx, GCR0);
DX_REG_DUMP(dx, GCR1);
DX_REG_DUMP(dx, GCR2);
DX_REG_DUMP(dx, GCR3);
DX_REG_DUMP(dx, GTR);
}
+
+ iounmap(phy_base);
}
}
static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *cmd = argv[1];
+ const struct uniphier_ddrmphy_param *param;
+ char *cmd;
+
+ param = uniphier_get_ddrmphy_param();
+ if (!param) {
+ printf("unsupported SoC\n");
+ return CMD_RET_FAILURE;
+ }
if (argc == 1)
cmd = "all";
+ else
+ cmd = argv[1];
if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
- zq_dump();
+ zq_dump(param);
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump();
+ wbdl_dump(param);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump();
+ rbdl_dump(param);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump();
+ wld_dump(param);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump();
+ dqsgd_dump(param);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump();
+ mdl_dump(param);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump();
+ reg_dump(param);
- return 0;
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
ddrm, 2, 1, do_ddrm,
- "UniPhier DDR PHY parameters dumper",
+ "UniPhier DDR Multi PHY parameters dumper",
"- dump all of the following\n"
"ddrm zq - dump Impedance Data\n"
"ddrm wbdl - dump Write Bit Delay\n"
/*
* Copyright (C) 2014 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
+ * Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
-struct phy_param {
- resource_size_t base;
- unsigned int nr_dx;
-};
-
-static const struct phy_param uniphier_ld4_phy_param[] = {
- { .base = 0x5bc01000, .nr_dx = 2, },
- { .base = 0x5be01000, .nr_dx = 2, },
- { /* sentinel */ }
-};
+#define UNIPHIER_MAX_NR_DDRPHY 4
-static const struct phy_param uniphier_pro4_phy_param[] = {
- { .base = 0x5bc01000, .nr_dx = 2, },
- { .base = 0x5bc02000, .nr_dx = 2, },
- { .base = 0x5be01000, .nr_dx = 2, },
- { .base = 0x5be02000, .nr_dx = 2, },
- { /* sentinel */ }
+struct uniphier_ddrphy_param {
+ unsigned int soc_id;
+ unsigned int nr_phy;
+ struct {
+ resource_size_t base;
+ unsigned int nr_dx;
+ } phy[UNIPHIER_MAX_NR_DDRPHY];
};
-static const struct phy_param uniphier_sld8_phy_param[] = {
- { .base = 0x5bc01000, .nr_dx = 2, },
- { .base = 0x5be01000, .nr_dx = 2, },
- { /* sentinel */ }
-};
-
-static const struct phy_param uniphier_ld11_phy_param[] = {
- { .base = 0x5bc01000, .nr_dx = 4, },
- { /* sentinel */ }
+static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .nr_phy = 2,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .nr_phy = 4,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5bc02000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { .base = 0x5be02000, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .nr_phy = 2,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .nr_phy = 1,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 4, },
+ },
+ },
};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
static void print_bdl(void __iomem *reg, int n)
{
printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
}
-static void dump_loop(const struct phy_param *phy_param,
+static void dump_loop(const struct uniphier_ddrphy_param *param,
void (*callback)(void __iomem *))
{
void __iomem *phy_base, *dx_base;
- int p, dx;
+ int phy, dx;
- for (p = 0; phy_param->base; phy_param++, p++) {
- phy_base = ioremap(phy_param->base, SZ_4K);
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
dx_base = phy_base + PHY_DX_BASE;
- for (dx = 0; dx < phy_param->nr_dx; dx++) {
- printf("PHY%dDX%d:", p, dx);
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
+ printf("PHY%dDX%d:", phy, dx);
(*callback)(dx_base);
dx_base += PHY_DX_STRIDE;
printf("\n");
readl(dx_base + PHY_DX_LCDLR1) & 0xff);
}
-static void wbdl_dump(const struct phy_param *phy_param)
+static void wbdl_dump(const struct uniphier_ddrphy_param *param)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
- dump_loop(phy_param, &__wbdl_dump);
+ dump_loop(param, &__wbdl_dump);
}
static void __rbdl_dump(void __iomem *dx_base)
(readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
}
-static void rbdl_dump(const struct phy_param *phy_param)
+static void rbdl_dump(const struct uniphier_ddrphy_param *param)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
- dump_loop(phy_param, &__rbdl_dump);
+ dump_loop(param, &__rbdl_dump);
}
static void __wld_dump(void __iomem *dx_base)
}
}
-static void wld_dump(const struct phy_param *phy_param)
+static void wld_dump(const struct uniphier_ddrphy_param *param)
{
printf("\n--- Write Leveling Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(phy_param, &__wld_dump);
+ dump_loop(param, &__wld_dump);
}
static void __dqsgd_dump(void __iomem *dx_base)
}
}
-static void dqsgd_dump(const struct phy_param *phy_param)
+static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
{
printf("\n--- DQS Gating Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(phy_param, &__dqsgd_dump);
+ dump_loop(param, &__dqsgd_dump);
}
static void __mdl_dump(void __iomem *dx_base)
{
int i;
u32 mdl = readl(dx_base + PHY_DX_MDLR);
+
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-static void mdl_dump(const struct phy_param *phy_param)
+static void mdl_dump(const struct uniphier_ddrphy_param *param)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
- dump_loop(phy_param, &__mdl_dump);
+ dump_loop(param, &__mdl_dump);
}
#define REG_DUMP(x) \
ofst >> PHY_REG_SHIFT, (dx), #x, \
ptr_to_uint(reg), readl(reg)); }
-static void reg_dump(const struct phy_param *phy_param)
+static void reg_dump(const struct uniphier_ddrphy_param *param)
{
void __iomem *phy_base;
- int p, dx;
+ int phy, dx;
printf("\n--- DDR PHY registers ---\n");
- for (p = 0; phy_param->base; phy_param++, p++) {
- phy_base = ioremap(phy_param->base, SZ_4K);
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
- printf("== PHY%d (base: %08x) ==\n", p, ptr_to_uint(phy_base));
+ printf("== PHY%d (base: %08x) ==\n",
+ phy, ptr_to_uint(phy_base));
printf(" No: Name : Address : Data\n");
REG_DUMP(RIDR);
REG_DUMP(MR2);
REG_DUMP(MR3);
- for (dx = 0; dx < phy_param->nr_dx; dx++) {
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
DX_REG_DUMP(dx, GCR);
DX_REG_DUMP(dx, GTR);
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *cmd = argv[1];
- const struct phy_param *phy_param;
-
- switch (uniphier_get_soc_id()) {
- case UNIPHIER_LD4_ID:
- phy_param = uniphier_ld4_phy_param;
- break;
- case UNIPHIER_PRO4_ID:
- phy_param = uniphier_pro4_phy_param;
- break;
- case UNIPHIER_SLD8_ID:
- phy_param = uniphier_sld8_phy_param;
- break;
- case UNIPHIER_LD11_ID:
- phy_param = uniphier_ld11_phy_param;
- break;
- default:
+ const struct uniphier_ddrphy_param *param;
+ char *cmd;
+
+ param = uniphier_get_ddrphy_param();
+ if (!param) {
printf("unsupported SoC\n");
return CMD_RET_FAILURE;
}
if (argc == 1)
cmd = "all";
+ else
+ cmd = argv[1];
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump(phy_param);
+ wbdl_dump(param);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump(phy_param);
+ rbdl_dump(param);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump(phy_param);
+ wld_dump(param);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump(phy_param);
+ dqsgd_dump(param);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump(phy_param);
+ mdl_dump(param);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump(phy_param);
+ reg_dump(param);
return CMD_RET_SUCCESS;
}
/*
* UniPhier DDR MultiPHY registers
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef ARCH_DDRMPHY_REGS_H
-#define ARCH_DDRMPHY_REGS_H
+#ifndef UNIPHIER_DDRMPHY_REGS_H
+#define UNIPHIER_DDRMPHY_REGS_H
#include <linux/bitops.h>
-#define DMPHY_SHIFT 2
+#define MPHY_SHIFT 2
-#define DMPHY_RIDR (0x000 << DMPHY_SHIFT)
-#define DMPHY_PIR (0x001 << DMPHY_SHIFT)
-#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */
-#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
-#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
-#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */
-#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */
-#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
-#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
-#define DMPHY_PIR_WL BIT(9) /* Write Leveling */
-#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
-#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
-#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
-#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
-#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
-#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
-#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
-#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
-#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT)
-#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
-#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT)
-#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
-#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT)
-#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
-#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
-#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT)
-#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT)
-#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
-#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
-#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
-#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
-#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
-#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
-#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
-#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
-#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
-#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
-#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
-#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
-#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
-#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
-#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
-#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
-#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
-#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
-#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
-#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
-#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT)
-#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
-#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT)
-#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT)
-#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT)
-#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT)
-#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT)
-#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT)
-#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT)
-#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT)
-#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT)
-#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT)
-#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT)
-#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT)
-#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT)
-#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT)
-#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT)
-#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT)
-#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT)
-#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT)
-#define DMPHY_DCR (0x022 << DMPHY_SHIFT)
-#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT)
-#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT)
-#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT)
-#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT)
-#define DMPHY_MR0 (0x027 << DMPHY_SHIFT)
-#define DMPHY_MR1 (0x028 << DMPHY_SHIFT)
-#define DMPHY_MR2 (0x029 << DMPHY_SHIFT)
-#define DMPHY_MR3 (0x02A << DMPHY_SHIFT)
-#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT)
-#define DMPHY_DTCR (0x02C << DMPHY_SHIFT)
-#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
-#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT))
-#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT)
-#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT)
-#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT)
-#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT)
-#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT)
-#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT)
-#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT)
-#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT)
-#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT)
-#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
-#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
+#define MPHY_RIDR (0x000 << MPHY_SHIFT)
+#define MPHY_PIR (0x001 << MPHY_SHIFT)
+#define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define MPHY_PIR_WL BIT(9) /* Write Leveling */
+#define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define MPHY_PGCR0 (0x002 << MPHY_SHIFT)
+#define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
+#define MPHY_PGCR1 (0x003 << MPHY_SHIFT)
+#define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define MPHY_PGCR2 (0x004 << MPHY_SHIFT)
+#define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
+#define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
+#define MPHY_PGCR3 (0x005 << MPHY_SHIFT)
+#define MPHY_PGSR0 (0x006 << MPHY_SHIFT)
+#define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
+#define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define MPHY_PGSR1 (0x007 << MPHY_SHIFT)
+#define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
+#define MPHY_PLLCR (0x008 << MPHY_SHIFT)
+#define MPHY_PTR0 (0x009 << MPHY_SHIFT)
+#define MPHY_PTR1 (0x00A << MPHY_SHIFT)
+#define MPHY_PTR2 (0x00B << MPHY_SHIFT)
+#define MPHY_PTR3 (0x00C << MPHY_SHIFT)
+#define MPHY_PTR4 (0x00D << MPHY_SHIFT)
+#define MPHY_ACMDLR (0x00E << MPHY_SHIFT)
+#define MPHY_ACLCDLR (0x00F << MPHY_SHIFT)
+#define MPHY_ACBDLR0 (0x010 << MPHY_SHIFT)
+#define MPHY_ACBDLR1 (0x011 << MPHY_SHIFT)
+#define MPHY_ACBDLR2 (0x012 << MPHY_SHIFT)
+#define MPHY_ACBDLR3 (0x013 << MPHY_SHIFT)
+#define MPHY_ACBDLR4 (0x014 << MPHY_SHIFT)
+#define MPHY_ACBDLR5 (0x015 << MPHY_SHIFT)
+#define MPHY_ACBDLR6 (0x016 << MPHY_SHIFT)
+#define MPHY_ACBDLR7 (0x017 << MPHY_SHIFT)
+#define MPHY_ACBDLR8 (0x018 << MPHY_SHIFT)
+#define MPHY_ACBDLR9 (0x019 << MPHY_SHIFT)
+#define MPHY_ACIOCR0 (0x01A << MPHY_SHIFT)
+#define MPHY_ACIOCR1 (0x01B << MPHY_SHIFT)
+#define MPHY_ACIOCR2 (0x01C << MPHY_SHIFT)
+#define MPHY_ACIOCR3 (0x01D << MPHY_SHIFT)
+#define MPHY_ACIOCR4 (0x01E << MPHY_SHIFT)
+#define MPHY_ACIOCR5 (0x01F << MPHY_SHIFT)
+#define MPHY_DXCCR (0x020 << MPHY_SHIFT)
+#define MPHY_DSGCR (0x021 << MPHY_SHIFT)
+#define MPHY_DCR (0x022 << MPHY_SHIFT)
+#define MPHY_DTPR0 (0x023 << MPHY_SHIFT)
+#define MPHY_DTPR1 (0x024 << MPHY_SHIFT)
+#define MPHY_DTPR2 (0x025 << MPHY_SHIFT)
+#define MPHY_DTPR3 (0x026 << MPHY_SHIFT)
+#define MPHY_MR0 (0x027 << MPHY_SHIFT)
+#define MPHY_MR1 (0x028 << MPHY_SHIFT)
+#define MPHY_MR2 (0x029 << MPHY_SHIFT)
+#define MPHY_MR3 (0x02A << MPHY_SHIFT)
+#define MPHY_ODTCR (0x02B << MPHY_SHIFT)
+#define MPHY_DTCR (0x02C << MPHY_SHIFT)
+#define MPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define MPHY_DTCR_RANKEN_MASK (0xf << (MPHY_DTCR_RANKEN_SHIFT))
+#define MPHY_DTAR0 (0x02D << MPHY_SHIFT)
+#define MPHY_DTAR1 (0x02E << MPHY_SHIFT)
+#define MPHY_DTAR2 (0x02F << MPHY_SHIFT)
+#define MPHY_DTAR3 (0x030 << MPHY_SHIFT)
+#define MPHY_DTDR0 (0x031 << MPHY_SHIFT)
+#define MPHY_DTDR1 (0x032 << MPHY_SHIFT)
+#define MPHY_DTEDR0 (0x033 << MPHY_SHIFT)
+#define MPHY_DTEDR1 (0x034 << MPHY_SHIFT)
+#define MPHY_ZQCR (0x090 << MPHY_SHIFT)
+#define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
+#define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
/* ZQ */
-#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT)
-#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT)
-#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT)
-#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT)
-#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT)
+#define MPHY_ZQ_BASE (0x091 << MPHY_SHIFT)
+#define MPHY_ZQ_STRIDE (0x004 << MPHY_SHIFT)
+#define MPHY_ZQ_PR (0x000 << MPHY_SHIFT)
+#define MPHY_ZQ_DR (0x001 << MPHY_SHIFT)
+#define MPHY_ZQ_SR (0x002 << MPHY_SHIFT)
/* DATX8 */
-#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT)
-#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT)
-#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT)
-#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
-#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT))
-#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT)
-#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT)
-#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT)
-#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT)
-#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT)
-#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT)
-#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT)
-#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT)
-#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT)
-#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT)
-#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT)
-#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT)
+#define MPHY_DX_BASE (0x0A0 << MPHY_SHIFT)
+#define MPHY_DX_STRIDE (0x020 << MPHY_SHIFT)
+#define MPHY_DX_GCR0 (0x000 << MPHY_SHIFT)
+#define MPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define MPHY_DX_GCR0_WLRKEN_MASK (0xf << (MPHY_DX_GCR0_WLRKEN_SHIFT))
+#define MPHY_DX_GCR1 (0x001 << MPHY_SHIFT)
+#define MPHY_DX_GCR2 (0x002 << MPHY_SHIFT)
+#define MPHY_DX_GCR3 (0x003 << MPHY_SHIFT)
+#define MPHY_DX_GSR0 (0x004 << MPHY_SHIFT)
+#define MPHY_DX_GSR1 (0x005 << MPHY_SHIFT)
+#define MPHY_DX_GSR2 (0x006 << MPHY_SHIFT)
+#define MPHY_DX_BDLR0 (0x007 << MPHY_SHIFT)
+#define MPHY_DX_BDLR1 (0x008 << MPHY_SHIFT)
+#define MPHY_DX_BDLR2 (0x009 << MPHY_SHIFT)
+#define MPHY_DX_BDLR3 (0x00A << MPHY_SHIFT)
+#define MPHY_DX_BDLR4 (0x00B << MPHY_SHIFT)
+#define MPHY_DX_BDLR5 (0x00C << MPHY_SHIFT)
+#define MPHY_DX_BDLR6 (0x00D << MPHY_SHIFT)
+#define MPHY_DX_LCDLR0 (0x00E << MPHY_SHIFT)
+#define MPHY_DX_LCDLR1 (0x00F << MPHY_SHIFT)
+#define MPHY_DX_LCDLR2 (0x010 << MPHY_SHIFT)
+#define MPHY_DX_MDLR (0x011 << MPHY_SHIFT)
+#define MPHY_DX_GTR (0x012 << MPHY_SHIFT)
-#endif /* ARCH_DDRMPHY_REGS_H */
+#endif /* UNIPHIER_DDRMPHY_REGS_H */
/*
- * Copyright (C) 2016 Socionext Inc.
+ * Copyright (C) 2016-2017 Socionext Inc.
*
- * based on commit 1f6feb76e7f9753f51955444e422486521f9b3a3 of Diag
+ * based on commit e732175d0b0dbc2a3855cb8ac791c538666b6fd4 of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
0x00000140, 0x00000180, 0x00000140
};
-static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
- { /* LD20 reference */
- {
- 2, 1, 0, 1, 2, 1, 1, 1,
- 2, 1, 1, 2, 1, 1, 1, 1,
- 1, 2, 1, 1, 1, 2, 1, 1,
- 2, 2, 0, 1, 1, 2, 2, 1,
- },
- {
- 1, 1, 0, 1, 2, 2, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 0, 0, 1, 1, 0, 0,
- 0, 1, 1, 1, 2, 1, 2, 1,
- },
- {
- 2, 2, 0, 2, 1, 1, 2, 1,
- 1, 1, 0, 1, 1, -1, 1, 1,
- 2, 2, 2, 2, 1, 1, 1, 1,
- 1, 1, 1, 0, 2, 2, 1, 2,
- },
+static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = {
+ {
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
},
- { /* LD20 TV */
- {
- 2, 1, 0, 1, 2, 1, 1, 1,
- 2, 1, 1, 2, 1, 1, 1, 1,
- 1, 2, 1, 1, 1, 2, 1, 1,
- 2, 2, 0, 1, 1, 2, 2, 1,
- },
- {
- 1, 1, 0, 1, 2, 2, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 0, 0, 1, 1, 0, 0,
- 0, 1, 1, 1, 2, 1, 2, 1,
- },
- {
- 2, 2, 0, 2, 1, 1, 2, 1,
- 1, 1, 0, 1, 1, -1, 1, 1,
- 2, 2, 2, 2, 1, 1, 1, 1,
- 1, 1, 1, 0, 2, 2, 1, 2,
- },
+ {
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
},
- { /* LD20 TV C1 */
- {
- 2, 1, 0, 1, 2, 1, 1, 1,
- 2, 1, 1, 2, 1, 1, 1, 1,
- 1, 2, 1, 1, 1, 2, 1, 1,
- 2, 2, 0, 1, 1, 2, 2, 1,
- },
- {
- 1, 1, 0, 1, 2, 2, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 0, 0, 1, 1, 0, 0,
- 0, 1, 1, 1, 2, 1, 2, 1,
- },
- {
- 2, 2, 0, 2, 1, 1, 2, 1,
- 1, 1, 0, 1, 1, -1, 1, 1,
- 2, 2, 2, 2, 1, 1, 1, 1,
- 1, 1, 1, 0, 2, 2, 1, 2,
- },
+ {
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
},
- { /* LD21 reference */
- {
- 1, 1, 0, 1, 1, 1, 1, 1,
- 1, 0, 0, 0, 1, 1, 0, 2,
- 1, 1, 0, 0, 1, 1, 1, 1,
- 1, 0, 0, 0, 1, 0, 0, 1,
- },
- { 1, 0, 2, 1, 1, 1, 1, 0,
- 1, 0, 0, 1, 0, 1, 0, 0,
- 1, 0, 1, 0, 1, 1, 1, 0,
- 1, 1, 1, 1, 0, 1, 0, 0,
- },
- /* No CH2 */
+};
+
+static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = {
+ {
+ 1, 1, 0, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 1, 0, 2,
+ 1, 1, 0, 0, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 0, 0, 1,
},
- { /* LD21 TV */
- {
- 1, 1, 0, 1, 1, 1, 1, 1,
- 1, 0, 0, 0, 1, 1, 0, 2,
- 1, 1, 0, 0, 1, 1, 1, 1,
- 1, 0, 0, 0, 1, 0, 0, 1,
- },
- { 1, 0, 2, 1, 1, 1, 1, 0,
- 1, 0, 0, 1, 0, 1, 0, 0,
- 1, 0, 1, 0, 1, 1, 1, 0,
- 1, 1, 1, 1, 0, 1, 0, 0,
- },
- /* No CH2 */
+ { 1, 0, 2, 1, 1, 1, 1, 0,
+ 1, 0, 0, 1, 0, 1, 0, 0,
+ 1, 0, 1, 0, 1, 1, 1, 0,
+ 1, 1, 1, 1, 0, 1, 0, 0,
},
+ /* No CH2 */
+};
+
+static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = {
+ ddrphy_op_dq_shift_val_ld20, /* LD20 reference */
+ ddrphy_op_dq_shift_val_ld20, /* LD20 TV */
+ ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */
+ ddrphy_op_dq_shift_val_ld21, /* LD21 reference */
+ ddrphy_op_dq_shift_val_ld21, /* LD21 TV */
};
-static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
- { /* LD20 reference */
- {
- 3, 3, 3, 2, 3, 2, 0, 2,
- 2, 3, 3, 1, 2, 2, 2, 2,
- 2, 2, 2, 2, 0, 1, 1, 1,
- 2, 2, 2, 2, 3, 0, 2, 2,
- },
- {
- 2, 2, 1, 1, -1, 1, 1, 1,
- 2, 0, 2, 2, 2, 1, 0, 2,
- 2, 1, 2, 1, 0, 1, 1, 1,
- 2, 2, 2, 2, 2, 2, 2, 2,
- },
- {
- 2, 2, 3, 2, 1, 2, 2, 2,
- 2, 3, 4, 2, 3, 4, 3, 3,
- 2, 2, 1, 2, 1, 1, 1, 1,
- 2, 2, 2, 2, 1, 2, 2, 1,
- },
+static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = {
+ {
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
},
- { /* LD20 TV */
- {
- 3, 3, 3, 2, 3, 2, 0, 2,
- 2, 3, 3, 1, 2, 2, 2, 2,
- 2, 2, 2, 2, 0, 1, 1, 1,
- 2, 2, 2, 2, 3, 0, 2, 2,
- },
- {
- 2, 2, 1, 1, -1, 1, 1, 1,
- 2, 0, 2, 2, 2, 1, 0, 2,
- 2, 1, 2, 1, 0, 1, 1, 1,
- 2, 2, 2, 2, 2, 2, 2, 2,
- },
- {
- 2, 2, 3, 2, 1, 2, 2, 2,
- 2, 3, 4, 2, 3, 4, 3, 3,
- 2, 2, 1, 2, 1, 1, 1, 1,
- 2, 2, 2, 2, 1, 2, 2, 1,
- },
+ {
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
},
- { /* LD20 TV C1 */
- {
- 3, 3, 3, 2, 3, 2, 0, 2,
- 2, 3, 3, 1, 2, 2, 2, 2,
- 2, 2, 2, 2, 0, 1, 1, 1,
- 2, 2, 2, 2, 3, 0, 2, 2,
- },
- {
- 2, 2, 1, 1, -1, 1, 1, 1,
- 2, 0, 2, 2, 2, 1, 0, 2,
- 2, 1, 2, 1, 0, 1, 1, 1,
- 2, 2, 2, 2, 2, 2, 2, 2,
- },
- {
- 2, 2, 3, 2, 1, 2, 2, 2,
- 2, 3, 4, 2, 3, 4, 3, 3,
- 2, 2, 1, 2, 1, 1, 1, 1,
- 2, 2, 2, 2, 1, 2, 2, 1,
- },
+ {
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
},
- { /* LD21 reference */
- {
- 2, 2, 2, 2, 1, 2, 2, 2,
- 2, 3, 3, 2, 2, 2, 2, 2,
- 2, 1, 2, 2, 1, 1, 1, 1,
- 2, 2, 2, 3, 1, 2, 2, 2,
- },
- {
- 3, 4, 4, 1, 0, 1, 1, 1,
- 1, 2, 1, 2, 2, 3, 3, 2,
- 1, 0, 2, 1, 1, 0, 1, 0,
- 0, 1, 0, 0, 1, 1, 0, 1,
- },
- /* No CH2 */
+};
+
+static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = {
+ {
+ 2, 2, 2, 2, 1, 2, 2, 2,
+ 2, 3, 3, 2, 2, 2, 2, 2,
+ 2, 1, 2, 2, 1, 1, 1, 1,
+ 2, 2, 2, 3, 1, 2, 2, 2,
},
- { /* LD21 TV */
- {
- 2, 2, 2, 2, 1, 2, 2, 2,
- 2, 3, 3, 2, 2, 2, 2, 2,
- 2, 1, 2, 2, 1, 1, 1, 1,
- 2, 2, 2, 3, 1, 2, 2, 2,
- },
- {
- 3, 4, 4, 1, 0, 1, 1, 1,
- 1, 2, 1, 2, 2, 3, 3, 2,
- 1, 0, 2, 1, 1, 0, 1, 0,
- 0, 1, 0, 0, 1, 1, 0, 1,
- },
- /* No CH2 */
+ {
+ 3, 4, 4, 1, 0, 1, 1, 1,
+ 1, 2, 1, 2, 2, 3, 3, 2,
+ 1, 0, 2, 1, 1, 0, 1, 0,
+ 0, 1, 0, 0, 1, 1, 0, 1,
},
+ /* No CH2 */
+};
+
+static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = {
+ ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */
+ ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */
+ ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */
+ ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */
+ ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */
};
-/* DDR PHY */
static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
unsigned int bit)
{
}
static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
- u32 mask, u32 incr, int shift_val)
+ u32 mask, u32 incr, short shift_val)
{
u32 tmp;
int val;
static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
u32 mask, u32 incr, u32 override,
- const int *shift_val_array)
+ const short *shift_val_array)
{
u32 tmp;
int dx, bit;
DRAM_SZ_NR,
};
+/* PHY */
static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
/* dependent on package and board design */
static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
-/*
- * The ch2 is a different generation UMC core.
- * The register spec is different, unfortunately.
- */
-static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
-static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
-static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- {0x004A071D, 0x0078071D},
- {0x0055081E, 0x0089081E},
-};
-
-static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
-/* The ch2 is different for some reason only hardware guys know... */
-static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
-static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
-
/* DDR multiPHY */
static inline int ddrphy_get_rank(int dx)
{
{
u32 tmp;
- tmp = readl(phy_base + DMPHY_PGCR0);
- tmp &= ~DMPHY_PGCR0_PHYFRST;
- writel(tmp, phy_base + DMPHY_PGCR0);
+ tmp = readl(phy_base + MPHY_PGCR0);
+ tmp &= ~MPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + MPHY_PGCR0);
udelay(1);
- tmp |= DMPHY_PGCR0_PHYFRST;
- writel(tmp, phy_base + DMPHY_PGCR0);
+ tmp |= MPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + MPHY_PGCR0);
udelay(1);
}
{
u32 tmp;
- tmp = readl(phy_base + DMPHY_PGCR1);
+ tmp = readl(phy_base + MPHY_PGCR1);
if (enable)
- tmp &= ~DMPHY_PGCR1_INHVT;
+ tmp &= ~MPHY_PGCR1_INHVT;
else
- tmp |= DMPHY_PGCR1_INHVT;
+ tmp |= MPHY_PGCR1_INHVT;
- writel(tmp, phy_base + DMPHY_PGCR1);
+ writel(tmp, phy_base + MPHY_PGCR1);
if (!enable) {
- while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
+ while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP))
cpu_relax();
}
}
{
int dx;
u32 lcdlr1, rdqsd;
- void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+ void __iomem *dx_base = phy_base + MPHY_DX_BASE;
ddrphy_vt_ctrl(phy_base, 0);
for (dx = 0; dx < nr_dx; dx++) {
- lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
+ lcdlr1 = readl(dx_base + MPHY_DX_LCDLR1);
rdqsd = (lcdlr1 >> 8) & 0xff;
rdqsd = clamp(rdqsd + step, 0U, 0xffU);
lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
- writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
- readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
- dx_base += DMPHY_DX_STRIDE;
+ writel(lcdlr1, dx_base + MPHY_DX_LCDLR1);
+ readl(dx_base + MPHY_DX_LCDLR1); /* relax */
+ dx_base += MPHY_DX_STRIDE;
}
ddrphy_vt_ctrl(phy_base, 1);
static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
{
- void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+ void __iomem *dx_base = phy_base + MPHY_DX_BASE;
const int nr_dx = width / 8;
int dx, rank;
u32 gtr;
int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
for (dx = 0; dx < nr_dx; dx++) {
- gtr = readl(dx_base + DMPHY_DX_GTR);
+ gtr = readl(dx_base + MPHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
dgsl = gtr & 0x7;
/* if dgsl is zero, this rank was not trained. skip. */
}
gtr >>= 3;
}
- dx_base += DMPHY_DX_STRIDE;
+ dx_base += MPHY_DX_STRIDE;
}
if (dgsl_min != dgsl_max)
nr_dx = width / 8;
- writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
+ writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR);
/*
* Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
* to avoid read error issue.
*/
- writel(0x07d81e37, phy_base + DMPHY_PGCR0);
- writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
+ writel(0x07d81e37, phy_base + MPHY_PGCR0);
+ writel(0x0200c4e0, phy_base + MPHY_PGCR1);
tmp = ddrphy_pgcr2[freq];
if (width >= 32)
- tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
- writel(tmp, phy_base + DMPHY_PGCR2);
-
- writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
- writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
- writel(0x00083def, phy_base + DMPHY_PTR2);
- writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
- writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
-
- writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
-
- writel(0x55555555, phy_base + DMPHY_ACIOCR1);
- writel(0x00000000, phy_base + DMPHY_ACIOCR2);
- writel(0x55555555, phy_base + DMPHY_ACIOCR3);
- writel(0x00000000, phy_base + DMPHY_ACIOCR4);
- writel(0x00000055, phy_base + DMPHY_ACIOCR5);
- writel(0x00181aa4, phy_base + DMPHY_DXCCR);
-
- writel(0x0024641e, phy_base + DMPHY_DSGCR);
- writel(0x0000040b, phy_base + DMPHY_DCR);
- writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
- writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
- writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
- writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
- writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
- writel(0x00000006, phy_base + DMPHY_MR1);
- writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
- writel(0x00000000, phy_base + DMPHY_MR3);
+ tmp |= MPHY_PGCR2_DUALCHN | MPHY_PGCR2_ACPDDC;
+ writel(tmp, phy_base + MPHY_PGCR2);
+
+ writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0);
+ writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1);
+ writel(0x00083def, phy_base + MPHY_PTR2);
+ writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3);
+ writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4);
+
+ writel(ddrphy_acbdlr0[ch], phy_base + MPHY_ACBDLR0);
+
+ writel(0x55555555, phy_base + MPHY_ACIOCR1);
+ writel(0x00000000, phy_base + MPHY_ACIOCR2);
+ writel(0x55555555, phy_base + MPHY_ACIOCR3);
+ writel(0x00000000, phy_base + MPHY_ACIOCR4);
+ writel(0x00000055, phy_base + MPHY_ACIOCR5);
+ writel(0x00181aa4, phy_base + MPHY_DXCCR);
+
+ writel(0x0024641e, phy_base + MPHY_DSGCR);
+ writel(0x0000040b, phy_base + MPHY_DCR);
+ writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0);
+ writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1);
+ writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2);
+ writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3);
+ writel(ddrphy_mr0[freq], phy_base + MPHY_MR0);
+ writel(0x00000006, phy_base + MPHY_MR1);
+ writel(ddrphy_mr2[freq], phy_base + MPHY_MR2);
+ writel(0x00000000, phy_base + MPHY_MR3);
tmp = 0;
for (dx = 0; dx < nr_dx; dx++)
- tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
- writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
+ tmp |= BIT(MPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
+ writel(0x90003087 | tmp, phy_base + MPHY_DTCR);
- writel(0x00000000, phy_base + DMPHY_DTAR0);
- writel(0x00000008, phy_base + DMPHY_DTAR1);
- writel(0x00000010, phy_base + DMPHY_DTAR2);
- writel(0x00000018, phy_base + DMPHY_DTAR3);
- writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
- writel(0x7788bb44, phy_base + DMPHY_DTDR1);
+ writel(0x00000000, phy_base + MPHY_DTAR0);
+ writel(0x00000008, phy_base + MPHY_DTAR1);
+ writel(0x00000010, phy_base + MPHY_DTAR2);
+ writel(0x00000018, phy_base + MPHY_DTAR3);
+ writel(0xdd22ee11, phy_base + MPHY_DTDR0);
+ writel(0x7788bb44, phy_base + MPHY_DTDR1);
/* impedance control settings */
- writel(0x04048900, phy_base + DMPHY_ZQCR);
+ writel(0x04048900, phy_base + MPHY_ZQCR);
- zq_base = phy_base + DMPHY_ZQ_BASE;
+ zq_base = phy_base + MPHY_ZQ_BASE;
for (zq = 0; zq < 4; zq++) {
/*
* board-dependent
* PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
*/
- writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
- zq_base += DMPHY_ZQ_STRIDE;
+ writel(0x0007BB5D, zq_base + MPHY_ZQ_PR);
+ zq_base += MPHY_ZQ_STRIDE;
}
/* DATX8 settings */
- dx_base = phy_base + DMPHY_DX_BASE;
+ dx_base = phy_base + MPHY_DX_BASE;
for (dx = 0; dx < 4; dx++) {
- tmp = readl(dx_base + DMPHY_DX_GCR0);
- tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
- tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
- DMPHY_DX_GCR0_WLRKEN_MASK;
- writel(tmp, dx_base + DMPHY_DX_GCR0);
-
- writel(0x00000000, dx_base + DMPHY_DX_GCR1);
- writel(0x00000000, dx_base + DMPHY_DX_GCR2);
- writel(0x00000000, dx_base + DMPHY_DX_GCR3);
- dx_base += DMPHY_DX_STRIDE;
+ tmp = readl(dx_base + MPHY_DX_GCR0);
+ tmp &= ~MPHY_DX_GCR0_WLRKEN_MASK;
+ tmp |= BIT(MPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
+ MPHY_DX_GCR0_WLRKEN_MASK;
+ writel(tmp, dx_base + MPHY_DX_GCR0);
+
+ writel(0x00000000, dx_base + MPHY_DX_GCR1);
+ writel(0x00000000, dx_base + MPHY_DX_GCR2);
+ writel(0x00000000, dx_base + MPHY_DX_GCR3);
+ dx_base += MPHY_DX_STRIDE;
}
- while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
+ while (!(readl(phy_base + MPHY_PGSR0) & MPHY_PGSR0_IDONE))
cpu_relax();
ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
{
"Impedance Calibration",
- DMPHY_PIR_ZCAL,
- DMPHY_PGSR0_ZCDONE,
- DMPHY_PGSR0_ZCERR,
+ MPHY_PIR_ZCAL,
+ MPHY_PGSR0_ZCDONE,
+ MPHY_PGSR0_ZCERR,
},
{ /* sentinel */ }
};
static const struct ddrphy_init_sequence dram_init_sequence[] = {
{
"DRAM Initialization",
- DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
- DMPHY_PGSR0_DIDONE,
+ MPHY_PIR_DRAMRST | MPHY_PIR_DRAMINIT,
+ MPHY_PGSR0_DIDONE,
0,
},
{ /* sentinel */ }
static const struct ddrphy_init_sequence training_sequence[] = {
{
"Write Leveling",
- DMPHY_PIR_WL,
- DMPHY_PGSR0_WLDONE,
- DMPHY_PGSR0_WLERR,
+ MPHY_PIR_WL,
+ MPHY_PGSR0_WLDONE,
+ MPHY_PGSR0_WLERR,
},
{
"Read DQS Gate Training",
- DMPHY_PIR_QSGATE,
- DMPHY_PGSR0_QSGDONE,
- DMPHY_PGSR0_QSGERR,
+ MPHY_PIR_QSGATE,
+ MPHY_PGSR0_QSGDONE,
+ MPHY_PGSR0_QSGERR,
},
{
"Write Leveling Adjustment",
- DMPHY_PIR_WLADJ,
- DMPHY_PGSR0_WLADONE,
- DMPHY_PGSR0_WLAERR,
+ MPHY_PIR_WLADJ,
+ MPHY_PGSR0_WLADONE,
+ MPHY_PGSR0_WLAERR,
},
{
"Read Bit Deskew",
- DMPHY_PIR_RDDSKW,
- DMPHY_PGSR0_RDDONE,
- DMPHY_PGSR0_RDERR,
+ MPHY_PIR_RDDSKW,
+ MPHY_PGSR0_RDDONE,
+ MPHY_PGSR0_RDERR,
},
{
"Write Bit Deskew",
- DMPHY_PIR_WRDSKW,
- DMPHY_PGSR0_WDDONE,
- DMPHY_PGSR0_WDERR,
+ MPHY_PIR_WRDSKW,
+ MPHY_PGSR0_WDDONE,
+ MPHY_PGSR0_WDERR,
},
{
"Read Eye Training",
- DMPHY_PIR_RDEYE,
- DMPHY_PGSR0_REDONE,
- DMPHY_PGSR0_REERR,
+ MPHY_PIR_RDEYE,
+ MPHY_PGSR0_REDONE,
+ MPHY_PGSR0_REERR,
},
{
"Write Eye Training",
- DMPHY_PIR_WREYE,
- DMPHY_PGSR0_WEDONE,
- DMPHY_PGSR0_WEERR,
+ MPHY_PIR_WREYE,
+ MPHY_PGSR0_WEDONE,
+ MPHY_PGSR0_WEERR,
},
{ /* sentinel */ }
};
{
const struct ddrphy_init_sequence *s;
u32 pgsr0;
- u32 init_flag = DMPHY_PIR_INIT;
- u32 done_flag = DMPHY_PGSR0_IDONE;
+ u32 init_flag = MPHY_PIR_INIT;
+ u32 done_flag = MPHY_PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
ulong start = get_timer(0);
done_flag |= s->done_flag;
}
- writel(init_flag, phy_base + DMPHY_PIR);
+ writel(init_flag, phy_base + MPHY_PIR);
do {
if (--timeout < 0) {
return -ETIMEDOUT;
}
udelay(1);
- pgsr0 = readl(phy_base + DMPHY_PGSR0);
+ pgsr0 = readl(phy_base + MPHY_PGSR0);
} while ((pgsr0 & done_flag) != done_flag);
for (s = seq; s->description; s++) {
udelay(1);
/* reflect ZQ settings and enable average algorithm*/
- tmp = readl(phy_base + DMPHY_ZQCR);
- tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
- writel(tmp, phy_base + DMPHY_ZQCR);
- tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
- tmp |= DMPHY_ZQCR_AVGEN;
- writel(tmp, phy_base + DMPHY_ZQCR);
+ tmp = readl(phy_base + MPHY_ZQCR);
+ tmp |= MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ writel(tmp, phy_base + MPHY_ZQCR);
+ tmp &= ~MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ tmp |= MPHY_ZQCR_AVGEN;
+ writel(tmp, phy_base + MPHY_ZQCR);
return 0;
}
}
/* UMC */
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
+/*
+ * The ch2 is a different generation UMC core.
+ * The register spec is different, unfortunately.
+ */
+static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
+static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x004A071D, 0x0078071D},
+ {0x0055081E, 0x0089081E},
+};
+
+static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
+/* The ch2 is different for some reason only hardware guys know... */
+static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
+static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
+
static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
{
u32 val;
/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <libfdt.h>
#include <fdtdec.h>
#include <linux/errno.h>
+#include <linux/sizes.h>
#include "init.h"
+#include "sg-regs.h"
#include "soc-info.h"
DECLARE_GLOBAL_DATA_PTR;
-static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+struct uniphier_memif_data {
+ unsigned int soc_id;
+ unsigned long sparse_ch1_base;
+ int have_ch2;
+};
+
+static const struct uniphier_memif_data uniphier_memif_data[] = {
+ {
+ .soc_id = UNIPHIER_SLD3_ID,
+ .sparse_ch1_base = 0xc0000000,
+ /*
+ * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
+ * and ch2 overlap, and host cannot get access to them at the
+ * same time. Hide the ch2 from U-Boot.
+ */
+ },
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .sparse_ch1_base = 0xa0000000,
+ },
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_PRO5_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_LD20_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+ {
+ .soc_id = UNIPHIER_PXS3_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
+
+static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
{
- int offset;
+ const struct uniphier_memif_data *data;
+ unsigned long size;
+ u32 val;
- offset = fdt_path_offset(fdt, "/memory");
- if (offset < 0)
- return NULL;
+ data = uniphier_get_memif_data();
+ if (!data) {
+ pr_err("unsupported SoC\n");
+ return -EINVAL;
+ }
- return fdt_getprop(fdt, offset, "reg", lenp);
-}
+ val = readl(SG_MEMCONF);
-int dram_init(void)
-{
- const void *fdt = gd->fdt_blob;
- const fdt32_t *val;
- int ac, sc, len;
-
- ac = fdt_address_cells(fdt, 0);
- sc = fdt_size_cells(fdt, 0);
- if (ac < 0 || sc < 1 || sc > 2) {
- printf("invalid address/size cells\n");
+ /* set up ch0 */
+ dram_ch[0].base = CONFIG_SYS_SDRAM_BASE;
+
+ switch (val & SG_MEMCONF_CH0_SZ_MASK) {
+ case SG_MEMCONF_CH0_SZ_64M:
+ size = SZ_64M;
+ break;
+ case SG_MEMCONF_CH0_SZ_128M:
+ size = SZ_128M;
+ break;
+ case SG_MEMCONF_CH0_SZ_256M:
+ size = SZ_256M;
+ break;
+ case SG_MEMCONF_CH0_SZ_512M:
+ size = SZ_512M;
+ break;
+ case SG_MEMCONF_CH0_SZ_1G:
+ size = SZ_1G;
+ break;
+ default:
+ pr_err("error: invald value is set to MEMCONF ch0 size\n");
return -EINVAL;
}
- val = get_memory_reg_prop(fdt, &len);
- if (len / sizeof(*val) < ac + sc)
+ if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
+ size *= 2;
+
+ dram_ch[0].size = size;
+
+ /* set up ch1 */
+ dram_ch[1].base = dram_ch[0].base + size;
+
+ if (val & SG_MEMCONF_SPARSEMEM) {
+ if (dram_ch[1].base > data->sparse_ch1_base) {
+ pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
+ pr_warn("Only ch0 is available\n");
+ dram_ch[1].base = 0;
+ return 0;
+ }
+
+ dram_ch[1].base = data->sparse_ch1_base;
+ }
+
+ switch (val & SG_MEMCONF_CH1_SZ_MASK) {
+ case SG_MEMCONF_CH1_SZ_64M:
+ size = SZ_64M;
+ break;
+ case SG_MEMCONF_CH1_SZ_128M:
+ size = SZ_128M;
+ break;
+ case SG_MEMCONF_CH1_SZ_256M:
+ size = SZ_256M;
+ break;
+ case SG_MEMCONF_CH1_SZ_512M:
+ size = SZ_512M;
+ break;
+ case SG_MEMCONF_CH1_SZ_1G:
+ size = SZ_1G;
+ break;
+ default:
+ pr_err("error: invald value is set to MEMCONF ch1 size\n");
return -EINVAL;
+ }
- val += ac;
+ if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
+ size *= 2;
- gd->ram_size = fdtdec_get_number(val, sc);
+ dram_ch[1].size = size;
- debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
+ if (!data->have_ch2)
+ return 0;
+
+ /* set up ch2 */
+ dram_ch[2].base = dram_ch[1].base + size;
+
+ switch (val & SG_MEMCONF_CH2_SZ_MASK) {
+ case SG_MEMCONF_CH2_SZ_64M:
+ size = SZ_64M;
+ break;
+ case SG_MEMCONF_CH2_SZ_128M:
+ size = SZ_128M;
+ break;
+ case SG_MEMCONF_CH2_SZ_256M:
+ size = SZ_256M;
+ break;
+ case SG_MEMCONF_CH2_SZ_512M:
+ size = SZ_512M;
+ break;
+ case SG_MEMCONF_CH2_SZ_1G:
+ size = SZ_1G;
+ break;
+ default:
+ pr_err("error: invald value is set to MEMCONF ch2 size\n");
+ return -EINVAL;
+ }
+
+ if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
+ size *= 2;
+
+ dram_ch[2].size = size;
return 0;
}
-void dram_init_banksize(void)
+int dram_init(void)
{
- const void *fdt = gd->fdt_blob;
- const fdt32_t *val;
- int ac, sc, cells, len, i;
-
- val = get_memory_reg_prop(fdt, &len);
- if (len < 0)
- return;
-
- ac = fdt_address_cells(fdt, 0);
- sc = fdt_size_cells(fdt, 0);
- if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
- printf("invalid address/size cells\n");
- return;
+ struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
+ int ret, i;
+
+ gd->ram_size = 0;
+
+ ret = uniphier_memconf_decode(dram_ch);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
+
+ if (!dram_ch[i].size)
+ break;
+
+ /*
+ * U-Boot relocates itself to the tail of the memory region,
+ * but it does not expect sparse memory. We use the first
+ * contiguous chunk here.
+ */
+ if (i > 0 &&
+ dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base)
+ break;
+
+ gd->ram_size += dram_ch[i].size;
}
- cells = ac + sc;
+ return 0;
+}
- len /= sizeof(*val);
+void dram_init_banksize(void)
+{
+ struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
+ int i;
+
+ uniphier_memconf_decode(dram_ch);
- for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
- i++, len -= cells) {
- gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
- val += ac;
- gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
- val += sc;
+ for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
+ if (i >= ARRAY_SIZE(gd->bd->bi_dram))
+ break;
- debug("DRAM bank %d: start = %08lx, size = %08lx\n",
- i, (unsigned long)gd->bd->bi_dram[i].start,
- (unsigned long)gd->bd->bi_dram[i].size);
+ gd->bd->bi_dram[i].start = dram_ch[i].base;
+ gd->bd->bi_dram[i].size = dram_ch[i].size;
}
}
*/
int ft_board_setup(void *fdt, bd_t *bd)
{
- const struct uniphier_board_data *param;
unsigned long rsv_addr;
const unsigned long rsv_size = 64;
- int ch, ret;
+ int i, ret;
if (uniphier_get_soc_id() != UNIPHIER_LD20_ID)
return 0;
- param = uniphier_get_board_param();
- if (!param) {
- printf("failed to get board parameter\n");
- return -ENODEV;
- }
-
- for (ch = 0; ch < param->dram_nr_ch; ch++) {
- rsv_addr = param->dram_ch[ch].base + param->dram_ch[ch].size;
+ for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+ rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
rsv_addr -= rsv_size;
ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
void uniphier_smp_kick_all_cpus(void);
void cci500_init(int nr_slaves);
+#define pr_warn(fmt, args...) printf(fmt, ##args)
#define pr_err(fmt, args...) printf(fmt, ##args)
#endif /* __MACH_INIT_H */
default y
config SPL_MMC_SUPPORT
- default y if ZYNQ_SDHCI
+ default y if MMC_SDHCI_ZYNQ
config SPL_SERIAL_SUPPORT
default y
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
+ /* global data region was cleared in start.S */
/* system performance tweaking */
clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
*/
void cpu_init_f (volatile immap_t * im)
{
- int i;
-
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- /* Clear initial global data */
- for (i = 0; i < sizeof(gd_t); i++)
- ((char *)gd)[i] = 0;
+ /* global data region was cleared in start.S */
/* system performance tweaking */
#endif
/* set up the stack pointer in our newly created
- * cache-ram (r1) */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
+ * cache-ram; use r3 to keep the new SP for now to
+ * avoid overiding the SP it uselessly */
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
+ /* r4 = end of GD area */
+ addi r4, r3, GENERATED_GBL_DATA_SIZE
+
+ /* Zero GD area */
+ li r0, 0
+1:
+ subi r4, r4, 1
+ stb r0, 0(r4)
+ cmplw r3, r4
+ bne 1b
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+ /* r3 = new stack pointer / pre-reloc malloc area */
+ subi r3, r3, CONFIG_SYS_MALLOC_F_LEN
+
+ /* Set pointer to pre-reloc malloc area in GD */
+ stw r3, GD_MALLOC_BASE(r4)
+#endif
li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+ stwu r0, -4(r3) /* clear final stack frame so that */
+ stwu r0, -4(r3) /* stack backtraces terminate cleanly */
+ /* Finally, actually set SP */
+ mr r1, r3
/* let the C-code set up the rest */
/* */
mtlr r8
isync
mfspr r4,L1CSR1
- ori r4,r4,0x0001
- oris r4,r4,0x0001
+ ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
+ oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
mtspr L1CSR1,r4
isync
blr
mtlr r8
isync
mfspr r0,L1CSR0
- ori r0,r0,0x0001
- oris r0,r0,0x0001
+ ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
+ oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
msync
isync
mtspr L1CSR0,r0
extern void* __memcpy(void *, const void *, size_t);
char *s = (char *)src;
char *t = (char *)trg;
- void *dest = (void *)src;
+ void *dest = (void *)trg;
/*
* Check is source address is in flash:
(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
/* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
+ gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
/* Assert PHY_RST# */
int board_init(void)
{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
+
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* arch number of board
*/
- gd->bd->bi_arch_number = MACH_TYPE_NAS220;
+ gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
--- /dev/null
+if TARGET_EVB_AST2500
+
+config SYS_BOARD
+ default "evb_ast2500"
+
+config SYS_VENDOR
+ default "aspeed"
+
+config SYS_CONFIG_NAME
+ default "evb_ast2500"
+
+endif
--- /dev/null
+obj-y += evb_ast2500.o
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
/* adress of boot parameters */
gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
int board_init(void)
{
+ /* arch number of AT91SAM9X5EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
+
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
irq_init();
#endif
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
+
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
int board_init(void)
{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
-#include <mmc.h>
-#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
-
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-#define I2C_PMIC 1
-
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
-
-#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
-#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
- int ret;
-
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
- if (ret)
- return ret;
-
- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (value << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- return 0;
-}
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /* CD pin */
- MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
- /* RST_B, used for power reset cycle */
- MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /* CD pin */
- MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
return 0;
}
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C2 for PMIC */
-struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
- .gp = IMX_GPIO_NR(1, 2),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
- .gp = IMX_GPIO_NR(1, 3),
- },
-};
-
-/* I2C3 for IO Expander */
-struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
- .gp = IMX_GPIO_NR(2, 14),
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
- .gp = IMX_GPIO_NR(2, 19),
- },
-};
-
int power_init_board(void)
{
- struct pmic *p;
+ struct udevice *dev;
+ int ret;
+ u32 dev_id, rev_id, i;
+ u32 switch_num = 6;
+ u32 offset = PFUZE100_SW1CMODE;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV)
+ return 0;
+
+ if (ret != 0)
+ return ret;
+
+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
+
+ /* Init mode to APS_PFM */
+ pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+ for (i = 0; i < switch_num - 1; i++)
+ pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+ /* set SW1AB staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+ /* set SW1C staby volatage 1.10V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
return 0;
}
return 0;
}
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
-#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
-#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC3_BASE_ADDR:
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = !gpio_get_value(USDHC4_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 USDHC3
- * mmc1 USDHC4
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- gpio_direction_input(USDHC3_CD_GPIO);
-
- /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
- gpio_direction_output(USDHC3_RST_GPIO, 0);
- udelay(1000); /* need 1ms at least */
- gpio_direction_output(USDHC3_RST_GPIO, 1);
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- gpio_direction_input(USDHC4_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-}
-
#ifdef CONFIG_FSL_QSPI
#define QSPI_PAD_CTRL1 \
int board_init(void)
{
+ struct gpio_desc desc;
+ int ret;
+
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-#endif
+ ret = dm_gpio_lookup_name("gpio@30_4", &desc);
+ if (ret)
+ return ret;
+ ret = dm_gpio_request(&desc, "cpu_per_rst_b");
+ if (ret)
+ return ret;
/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
- port_exp_direction_output(CPU_PER_RST_B, 0);
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
udelay(500);
- port_exp_direction_output(CPU_PER_RST_B, 1);
+ dm_gpio_set_value(&desc, 1);
+
+ ret = dm_gpio_lookup_name("gpio@32_2", &desc);
+ if (ret)
+ return ret;
+ ret = dm_gpio_request(&desc, "steer_enet");
+ if (ret)
+ return ret;
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ udelay(500);
/* Set steering signal to L for selecting B0 */
- port_exp_direction_output(STEER_ENET, 0);
+ dm_gpio_set_value(&desc, 0);
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#define CCDM_AUTO_FIRST_STAGE
#endif
-/* enums from TCG specs */
-enum {
- /* capability areas */
- TPM_CAP_NV_INDEX = 0x00000011,
- TPM_CAP_HANDLE = 0x00000014,
- /* resource types */
- TPM_RT_KEY = 0x00000001,
-};
-
/* CCDM specific contants */
enum {
/* NV indices */
--- /dev/null
+if TARGET_CHILIBOARD
+
+config SYS_BOARD
+ default "chiliboard"
+
+config SYS_VENDOR
+ default "grinn"
+
+config SYS_CONFIG_NAME
+ default "chiliboard"
+
+config SYS_SOC
+ default "am33xx"
+
+endif
--- /dev/null
+CHILIBOARD
+M: Marcin Niestroj <m.niestroj@grinn-global.com>
+S: Maintained
+F: arch/arm/include/asm/arch-am33xx/chilisom.h
+F: arch/arm/mach-omap2/am33xx/chilisom.c
+F: board/grinn/chiliboard/
+F: include/configs/chiliboard.h
+F: configs/chiliboard_defconfig
--- /dev/null
+# (C) Copyright 2017 Grinn
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
--- /dev/null
+How to use U-Boot on Grinn's chiliBoard
+--------------------------------------
+
+- Build U-Boot for chiliBoard:
+
+$ make mrproper
+$ make chiliboard_defconfig
+$ make
+
+This will generate the SPL image called MLO and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=MLO of=/dev/mmcblk0 bs=128k; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=128k seek=3; sync
+
+- Jumper settings:
+
+S2: 1 1 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between chiliBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
--- /dev/null
+/*
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/chilisom.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/io.h>
+#include <cpsw.h>
+#include <environment.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <serial.h>
+#include <spl.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __maybe_unused struct ctrl_dev *cdev =
+ (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
+static void enable_board_pin_mux(void)
+{
+ chilisom_enable_pin_mux();
+
+ /* chiliboard pinmux */
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+ return &eserial1_device;
+}
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void set_uart_mux_conf(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+void am33xx_spl_board_init(void)
+{
+ chilisom_spl_board_init();
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+#endif
+
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \
+ !defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ }
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+
+ return n;
+}
+#endif
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/litesom.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <fsl_esdhc.h>
#include <linux/sizes.h>
#include <linux/fb.h>
-#include <mach/litesom.h>
#include <miiphy.h>
#include <mmc.h>
#include <netdev.h>
{
gpmc_init();
- gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
+ gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
--- /dev/null
+if TARGET_MCCMON6
+
+config SYS_BOARD
+ default "mccmon6"
+
+config SYS_VENDOR
+ default "liebherr"
+
+config SYS_CONFIG_NAME
+ default "mccmon6"
+
+endif
--- /dev/null
+MCCMON6 BOARD
+M: Lukasz Majewski <lukma@denx.de>
+S: Maintained
+F: board/liebherr/mccmon6/
+F: include/configs/mccmon6.h
+F: configs/mccmon6_nor_defconfig
+F: configs/mccmon6_sd_defconfig
--- /dev/null
+#
+# (C) Copyright 2016-2017
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mccmon6.o spl.o
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <phy.h>
+#include <input.h>
+#include <i2c.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define ETH_PHY_RESET IMX_GPIO_NR(1, 27)
+#define ECSPI3_CS0 IMX_GPIO_NR(4, 24)
+#define ECSPI3_FLWP IMX_GPIO_NR(4, 27)
+#define NOR_WP IMX_GPIO_NR(1, 1)
+#define DISPLAY_EN IMX_GPIO_NR(1, 2)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* Carrier MicroSD Card Detect */
+ IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
+ | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
+ | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
+ | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* KSZ9031 PHY Reset */
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+
+ /* Reset KSZ9031 PHY */
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ mdelay(10);
+ gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ /*
+ * eMMC don't have card detect pin - since it is soldered to the
+ * PCB board
+ */
+ ret = 1;
+ break;
+ }
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ /*
+ * MMC MAP
+ * (U-Boot device node) (Physical Port)
+ * mmc0 Soldered on board eMMC device
+ * mmc1 MicroSD card
+ */
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ break;
+ case 1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ gpio_direction_input(USDHC2_CD_GPIO);
+ break;
+ default:
+ printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+
+ /* NOR configuration */
+ writel(0x00620181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0b020000, &weim_regs->cs0rcr1);
+ writel(0x0000b000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000000, &weim_regs->cs0wcr2);
+
+ writel(0x00000120, &weim_regs->wcr);
+ writel(0x00000010, &weim_regs->wiar);
+ writel(0x00000000, &weim_regs->ear);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_eimnor(void)
+{
+ SETUP_IOMUX_PADS(eimnor_pads);
+ gpio_direction_output(NOR_WP, 1);
+
+ enable_eim_clk(1);
+ eimnor_cs_setup();
+}
+
+/* mccmon6 board has SPI Flash is connected to SPI3 */
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
+}
+
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+ /* SPI3 */
+ IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+void setup_spi(void)
+{
+ SETUP_IOMUX_PADS(ecspi3_pads);
+
+ enable_spi_clk(true, 2);
+
+ /* set cs0 to high */
+ gpio_direction_output(ECSPI3_CS0, 1);
+
+ /* set flwp to high */
+ gpio_direction_output(ECSPI3_FLWP, 1);
+}
+
+struct i2c_pads_info mx6q_i2c1_pad_info = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info mx6q_i2c2_pad_info = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ gpio_direction_output(DISPLAY_EN, 1);
+
+ setup_eimnor();
+ setup_spi();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("board_name", "mccmon6");
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MCCMON6\n");
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Default setting for GMII Clock Pad Skew Register 0x1EF:
+ * MMD Address 0x2h, Register 0x8h
+ *
+ * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
+ * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
+ *
+ * Adjustment -> write 0x3FF:
+ * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
+ * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
+ *
+ */
+ ksz9031_phy_extended_write(phydev, 0x2,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
+
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
+
+ ksz9031_phy_extended_write(phydev, 0x2,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x3333);
+
+ ksz9031_phy_extended_write(phydev, 0x2,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x2052);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ setup_eimnor();
+
+ gpio_direction_output(DISPLAY_EN, 1);
+}
+#endif /* CONFIG_SPL_BOARD_INIT */
+
+#ifdef CONFIG_SPL_BUILD
+void board_boot_order(u32 *spl_boot_list)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC1:
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+ break;
+
+ case BOOT_DEVICE_NOR:
+ spl_boot_list[0] = BOOT_DEVICE_NOR;
+ break;
+ }
+}
+#endif /* CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ char s[16];
+ int ret;
+ /*
+ * We use BOOT_DEVICE_MMC1, but SD card is connected
+ * to MMC2
+ *
+ * Correct "mapping" is delivered in board defined
+ * board_boot_order() function.
+ *
+ * SD card boot is regarded as a "development" one,
+ * hence we _always_ go through the u-boot.
+ *
+ */
+ if (spl_boot_device() == BOOT_DEVICE_MMC1)
+ return 1;
+
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ env_init();
+ ret = getenv_f("boot_os", s, sizeof(s));
+ if ((ret != -1) && (strcmp(s, "no") == 0))
+ return 1;
+
+ /*
+ * Check if SWUpdate recovery needs to be started
+ *
+ * recovery_status = NULL (not set - ret == -1) -> normal operation
+ *
+ * recovery_status = progress or
+ * recovery_status = failed or
+ * recovery_status = <any value> -> start SWUpdate
+ *
+ */
+ ret = getenv_f("recovery_status", s, sizeof(s));
+ if (ret != -1)
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM nor
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
--- /dev/null
+/*
+ * Copyright (C) 2014 Wandboard
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ * Richard Hu <hakahu@gmail.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* H5TQ2G63DFR-H9 */
+static struct mx6_ddr3_cfg h5tq2g63dfr = {
+ .mem_speed = 1333,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x4301030d,
+ .p0_mpdgctrl1 = 0x03020277,
+ .p1_mpdgctrl0 = 0x4300030a,
+ .p1_mpdgctrl1 = 0x02780248,
+ .p0_mprddlctl = 0x4536393b,
+ .p1_mprddlctl = 0x36353441,
+ .p0_mpwrdlctl = 0x41414743,
+ .p1_mpwrdlctl = 0x462f453f,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x420e020e,
+ .p0_mpdgctrl1 = 0x02000200,
+ .p1_mpdgctrl0 = 0x42020202,
+ .p1_mpdgctrl1 = 0x01720172,
+ .p0_mprddlctl = 0x494c4f4c,
+ .p1_mprddlctl = 0x4a4c4c49,
+ .p0_mpwrdlctl = 0x3f3f3133,
+ .p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0040003c,
+ .p0_mpwldectrl1 = 0x0032003e,
+ .p0_mpdgctrl0 = 0x42350231,
+ .p0_mpdgctrl1 = 0x021a0218,
+ .p0_mprddlctl = 0x4b4b4e49,
+ .p0_mpwrdlctl = 0x3f3f3035,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
+ } else if (is_cpu_type(MXC_CPU_MX6DL)) {
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
int board_init(void)
{
+ gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
+
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/rcc.h>
#include <asm/arch/fmc.h>
#include <dm/platdata.h>
#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_defs.h>
+#include <asm/arch/syscfg.h>
DECLARE_GLOBAL_DATA_PTR;
return rv;
}
-/*
- * STM32 RCC FMC specific definitions
- */
-#define RCC_ENR_FMC (1 << 0) /* FMC module clock */
-
static inline u32 _ns2clk(u32 ns, u32 freq)
{
u32 tmp = freq/1000000;
if (rv)
return rv;
- setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
+ clock_setup(FMC_CLOCK_CFG);
/*
* Get frequency for NS2CLK calculation.
.platdata = &serial_platdata,
};
+#ifdef CONFIG_ETH_DESIGNWARE
+const struct stm32_gpio_ctl gpio_ctl_eth = {
+ .mode = STM32_GPIO_MODE_AF,
+ .otype = STM32_GPIO_OTYPE_PP,
+ .speed = STM32_GPIO_SPEED_100M,
+ .pupd = STM32_GPIO_PUPD_NO,
+ .af = STM32_GPIO_AF11
+};
+
+static const struct stm32_gpio_dsc eth_gpio[] = {
+ {STM32_GPIO_PORT_A, STM32_GPIO_PIN_1}, /* ETH_RMII_REF_CLK */
+ {STM32_GPIO_PORT_A, STM32_GPIO_PIN_2}, /* ETH_MDIO */
+ {STM32_GPIO_PORT_A, STM32_GPIO_PIN_7}, /* ETH_RMII_CRS_DV */
+
+ {STM32_GPIO_PORT_C, STM32_GPIO_PIN_1}, /* ETH_MDC */
+ {STM32_GPIO_PORT_C, STM32_GPIO_PIN_4}, /* ETH_RMII_RXD0 */
+ {STM32_GPIO_PORT_C, STM32_GPIO_PIN_5}, /* ETH_RMII_RXD1 */
+
+ {STM32_GPIO_PORT_G, STM32_GPIO_PIN_11}, /* ETH_RMII_TX_EN */
+ {STM32_GPIO_PORT_G, STM32_GPIO_PIN_13}, /* ETH_RMII_TXD0 */
+ {STM32_GPIO_PORT_G, STM32_GPIO_PIN_14}, /* ETH_RMII_TXD1 */
+};
+
+static int stmmac_setup(void)
+{
+ int res = 0;
+ int i;
+
+ clock_setup(SYSCFG_CLOCK_CFG);
+
+ /* Set >RMII mode */
+ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
+
+ clock_setup(GPIO_A_CLOCK_CFG);
+ clock_setup(GPIO_C_CLOCK_CFG);
+ clock_setup(GPIO_G_CLOCK_CFG);
+
+ for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) {
+ res = stm32_gpio_config(ð_gpio[i], &gpio_ctl_eth);
+ if (res)
+ return res;
+ }
+
+ clock_setup(STMMAC_CLOCK_CFG);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32_QSPI
+const struct stm32_gpio_ctl gpio_ctl_qspi_9 = {
+ .mode = STM32_GPIO_MODE_AF,
+ .otype = STM32_GPIO_OTYPE_PP,
+ .speed = STM32_GPIO_SPEED_100M,
+ .pupd = STM32_GPIO_PUPD_NO,
+ .af = STM32_GPIO_AF9
+};
+
+const struct stm32_gpio_ctl gpio_ctl_qspi_10 = {
+ .mode = STM32_GPIO_MODE_AF,
+ .otype = STM32_GPIO_OTYPE_PP,
+ .speed = STM32_GPIO_SPEED_100M,
+ .pupd = STM32_GPIO_PUPD_NO,
+ .af = STM32_GPIO_AF10
+};
+
+static const struct stm32_gpio_dsc qspi_af9_gpio[] = {
+ {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */
+ {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */
+ {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */
+ {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */
+ {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */
+};
+
+static const struct stm32_gpio_dsc qspi_af10_gpio[] = {
+ {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */
+};
+
+static int qspi_setup(void)
+{
+ int res = 0;
+ int i;
+
+ clock_setup(GPIO_B_CLOCK_CFG);
+ clock_setup(GPIO_D_CLOCK_CFG);
+ clock_setup(GPIO_E_CLOCK_CFG);
+
+ for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) {
+ res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9);
+ if (res)
+ return res;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) {
+ res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10);
+ if (res)
+ return res;
+ }
+
+ return 0;
+}
+#endif
+
u32 get_board_rev(void)
{
return 0;
if (res)
return res;
+#ifdef CONFIG_ETH_DESIGNWARE
+ res = stmmac_setup();
+ if (res)
+ return res;
+#endif
+
+#ifdef CONFIG_STM32_QSPI
+ res = qspi_setup();
+ if (res)
+ return res;
+#endif
+
return 0;
}
int board_init(void)
{
gpmc_init();
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
erase - FLASH memory
protect - enable or disable FLASH write protection
+config CMD_GPT
+ bool "GPT (GUID Partition Table) command"
+ select PARTITION_UUIDS
+ select EFI_PARTITION
+ help
+ Enable the 'gpt' command to ready and write GPT style partition
+ tables.
+
config CMD_ARMFLASH
#depends on FLASH_CFI_DRIVER
bool "armflash"
help
NAND support.
+config CMD_PART
+ bool "part"
+ select PARTITION_UUIDS
+ help
+ Read and display information about the partition table on
+ various media.
+
config CMD_SF
bool "sf"
help
char devname[32] = { 0 }; /* dp->str is u16[32] long */
char *colon;
-#if defined(CONFIG_BLK) || defined(CONFIG_ISO_PARTITION)
+#if defined(CONFIG_BLK) || CONFIG_IS_ENABLED(ISO_PARTITION)
desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
#endif
colon = strchr(devname, ':');
-#ifdef CONFIG_ISO_PARTITION
+#if CONFIG_IS_ENABLED(ISO_PARTITION)
/* For ISOs we create partition block devices */
if (desc && (desc->type != DEV_TYPE_UNKNOWN) &&
(desc->part_type == PART_TYPE_ISO)) {
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
+ images.os.arch = IH_ARCH_ARM64;
ret = do_bootm_states(cmdtp, flag, argc, argv,
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
BOOTM_STATE_RAMDISK |
#include <div64.h>
#include <memalign.h>
-#ifndef CONFIG_PARTITION_UUIDS
-#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_GPT to be enabled
-#endif
-
/**
* extract_env(): Expand env name from string format '&{env_name}'
* and return pointer to the env (if the env is set)
#include <part.h>
#include <vsprintf.h>
-#ifndef CONFIG_PARTITION_UUIDS
-#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_PART to be enabled
-#endif
-
static int do_part_uuid(int argc, char * const argv[])
{
int part;
#include <reiserfs.h>
#include <part.h>
-#ifndef CONFIG_DOS_PARTITION
+#if !CONFIG_IS_ENABLED(DOS_PARTITION)
#error DOS partition support must be selected
#endif
#endif /* CONFIG_TPM_AUTH_SESSIONS */
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int type = 0;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (strcasecmp(argv[1], "key"))
+ type = TPM_RT_KEY;
+ else if (strcasecmp(argv[1], "auth"))
+ type = TPM_RT_AUTH;
+ else if (strcasecmp(argv[1], "hash"))
+ type = TPM_RT_HASH;
+ else if (strcasecmp(argv[1], "trans"))
+ type = TPM_RT_TRANS;
+ else if (strcasecmp(argv[1], "context"))
+ type = TPM_RT_CONTEXT;
+ else if (strcasecmp(argv[1], "counter"))
+ type = TPM_RT_COUNTER;
+ else if (strcasecmp(argv[1], "delegate"))
+ type = TPM_RT_DELEGATE;
+ else if (strcasecmp(argv[1], "daa_tpm"))
+ type = TPM_RT_DAA_TPM;
+ else if (strcasecmp(argv[1], "daa_v0"))
+ type = TPM_RT_DAA_V0;
+ else if (strcasecmp(argv[1], "daa_v1"))
+ type = TPM_RT_DAA_V1;
+
+ if (strcasecmp(argv[2], "all")) {
+ uint16_t res_count;
+ uint8_t buf[288];
+ uint8_t *ptr;
+ int err;
+ uint i;
+
+ /* fetch list of already loaded resources in the TPM */
+ err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
+ sizeof(buf));
+ if (err)
+ return -1;
+ res_count = get_unaligned_be16(buf);
+ ptr = buf + 2;
+ for (i = 0; i < res_count; ++i, ptr += 4)
+ tpm_flush_specific(get_unaligned_be32(ptr), type);
+ } else {
+ uint32_t handle = simple_strtoul(argv[2], NULL, 0);
+
+ if (!handle)
+ return -1;
+ tpm_flush_specific(cpu_to_be32(handle), type);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
+
#define MAKE_TPM_CMD_ENTRY(cmd) \
U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
U_BOOT_CMD_MKENT(get_pub_key_oiap, 0, 1,
do_tpm_get_pub_key_oiap, "", ""),
#endif /* CONFIG_TPM_AUTH_SESSIONS */
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+ U_BOOT_CMD_MKENT(flush, 0, 1,
+ do_tpm_flush, "", ""),
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
};
static int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
" get_capability cap_area sub_cap addr count\n"
" - Read <count> bytes of TPM capability indexed by <cap_area> and\n"
" <sub_cap> to memory address <addr>.\n"
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+"Resource management functions\n"
+" flush resource_type id\n"
+" - flushes a resource of type <resource_type> (may be one of key, auth,\n"
+" hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
+" and id <id> from the TPM. Use an <id> of \"all\" to flush all\n"
+" resources of that type.\n"
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
#ifdef CONFIG_TPM_AUTH_SESSIONS
"Storage functions\n"
" loadkey2_oiap parent_handle key_addr key_len usage_auth\n"
#include <usb.h>
#endif
-#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION)
+#if !CONFIG_IS_ENABLED(DOS_PARTITION) && !CONFIG_IS_ENABLED(EFI_PARTITION)
#error DOS or EFI partition support must be selected
#endif
return;
}
-#ifdef CONFIG_EFI_PARTITION
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
printf("%s: updating MBR, Primary and Backup GPT(s)\n",
__func__);
}
#endif
-#ifdef CONFIG_DOS_PARTITION
+#if CONFIG_IS_ENABLED(DOS_PARTITION)
if (strcmp(cmd, CONFIG_FASTBOOT_MBR_NAME) == 0) {
printf("%s: updating MBR\n", __func__);
if (is_valid_dos_buf(download_buffer)) {
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
new_ptr = addr + bytes - gd->malloc_base;
- if (new_ptr > gd->malloc_limit)
+ if (new_ptr > gd->malloc_limit) {
+ debug("space exhausted\n");
return NULL;
+ }
+
ptr = map_sysmem(addr, bytes);
gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
+ debug("%lx\n", (ulong)ptr);
return ptr;
}
depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
default 0x50 if ARCH_SUNXI
default 0x75 if ARCH_DAVINCI
- default 0x80 if ARCH_UNIPHIER
default 0x8a if ARCH_MX6
- default 0x100 if ARCH_ROCKCHIP
+ default 0x100 if ARCH_ROCKCHIP || ARCH_UNIPHIER
default 0x140 if ARCH_MVEBU
default 0x200 if ARCH_SOCFPGA || ARCH_AT91
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
(image_entry_noargs_t)spl_image->entry_point;
debug("image entry point: 0x%lX\n", spl_image->entry_point);
-#if defined(CONFIG_ARMV8_SPIN_TABLE) && defined(CONFIG_ARMV8_MULTIENTRY)
- /*
- * Release all slave cores from CPU_RELEASE_ADDR so they could
- * arrive to the spin-table code in start.S of the u-boot
- */
- *(ulong *)CPU_RELEASE_ADDR = (ulong)spl_image->entry_point;
-#endif
-
image_entry();
}
int ret;
debug("spl_init()\n");
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+/*
+ * with CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN we set malloc_base and
+ * malloc_limit in spl_relocate_stack_gd
+ */
+#if defined(CONFIG_SYS_MALLOC_F_LEN) && \
+ !defined(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN)
#ifdef CONFIG_MALLOC_F_ADDR
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO4_VOLT=2500
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DFU_RAM=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP809_POWER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_AXP_FLDO1_VOLT=1200
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_VIDEO_CT69000=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP809_POWER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_ELDO2_VOLT=1800
CONFIG_USB_MUSB_GADGET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MAC_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_ALDO2_VOLT=1800
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_SW_ON=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
# CONFIG_PCI is not set
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
CONFIG_LED_STATUS0=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
# CONFIG_PCI is not set
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_TI_SECURE_DEVICE=y
+# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+# CONFIG_SPL_YMODEM_SUPPORT is not set
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm"
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_RSA=y
+CONFIG_SPL_OF_LIBFDT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DM=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DM=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
CONFIG_DM=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_X86=y
-CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
CONFIG_TARGET_BAYLEYBAY=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_ARCH_EARLY_INIT_R is not set
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_ARCH_MISC_INIT=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_KONA=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_KONA=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_KONA=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_KONA=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_KONA=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_BLANCHE=y
-# CONFIG_MMC is not set
CONFIG_BOOTSTAGE_USER_COUNT=0x20
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
+CONFIG_GENERIC_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TARGET_CHILIBOARD=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_GPIO=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO2_VOLT=1800
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
+CONFIG_DOS_PARTITION=y
CONFIG_DM=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
+CONFIG_DOS_PARTITION=y
CONFIG_DM=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_X86=y
CONFIG_MAX_CPUS=2
-CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_TARGET_CROWNBAY=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MISC=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_ISO_PARTITION is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_ISO_PARTITION is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_ISO_PARTITION is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_ISO_PARTITION is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_X86=y
-CONFIG_MMC=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
CONFIG_TARGET_DFI_BT700=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
+CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_UBI=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_MSM_SDHCI=y
+CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PM8916=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LED_STATUS_RED=1
CONFIG_LED_STATUS_GREEN_ENABLE=y
CONFIG_LED_STATUS_GREEN=0
+# CONFIG_DOS_PARTITION is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM_PCI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_UBI=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ASPEED=y
+CONFIG_ASPEED_AST2500=y
+CONFIG_TARGET_EVB_AST2500=y
+CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DISPLAY_CPUINFO=n
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_CLK=y
+CONFIG_TIMER=y
+CONFIG_RAM=y
+CONFIG_REGMAP=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x1e720000
+CONFIG_PRE_CON_BUF_SZ=4096
+CONFIG_SYS_NO_FLASH=y
+CONFIG_CMD_IMLS=n
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_ROCKCHIP_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_PINCTRL=y
CONFIG_ROCKCHIP_RK3399_PINCTRL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_X86=y
-CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="galileo"
CONFIG_TARGET_GALILEO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SOURCE is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="k2e-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_TI_AEMIF=y
+# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_TI_AEMIF=y
+# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="k2l-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_TI_AEMIF=y
+# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_QSPI_AHB_INIT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
-CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=n
-CONFIG_BLK=n
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
-CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=n
-CONFIG_BLK=n
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_GPT=y
+CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_CMD_GPT=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_FSL_DDR3=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_NETDEVICES=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_SPI=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
+CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
+CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MCCMON6=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MCCMON6=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_X86=y
-CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_ARCH_MISC_INIT=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
CONFIG_MMC_DW=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DM=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_RARP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_PIC32_SDHCI=y
+CONFIG_MMC_SDHCI_PIC32=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_ETH=y
CONFIG_PIC32_ETH=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_NETDEVICES=y
CONFIG_RTL8139=y
CONFIG_PCI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_PCI=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_UBI=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_GPIO=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_MAX8998=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX8998=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX8998=y
-CONFIG_SYS_I2C_S3C24X0=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_DOS_PARTITION=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_DM_MMC=y
-CONFIG_ATMEL_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_DM_MMC=y
-CONFIG_ATMEL_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DEMO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_NETCONSOLE=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
CONFIG_I2C_EEPROM=y
-CONFIG_SANDBOX_MMC=y
+CONFIG_MMC_SANDBOX=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DEMO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_NETCONSOLE=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
# CONFIG_MMC is not set
+CONFIG_GENERIC_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DEMO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
-CONFIG_SANDBOX_MMC=y
+CONFIG_MMC_SANDBOX=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_TIMER=y
-CONFIG_OF_LIBFDT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
CONFIG_DM=y
CONFIG_PCI=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_X86=y
-CONFIG_MMC=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
CONFIG_TARGET_DFI_BT700=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
+CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_GPIO=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_UBI=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_DM_SPI_FLASH=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
CONFIG_MMC_DW=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
CONFIG_MMC_DW=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=16
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_DOS_PARTITION=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
# CONFIG_PCI is not set
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_ETH=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
--- /dev/null
+
+menu "Partition Types"
+
+config PARTITIONS
+ bool "Enable Partition Labels (disklabels) support"
+ default y
+ help
+ Partition Labels (disklabels) Supported:
+ Zero or more of the following:
+ - CONFIG_MAC_PARTITION Apple's MacOS partition table.
+ - CONFIG_DOS_PARTITION MS Dos partition table, traditional on the
+ Intel architecture, USB sticks, etc.
+ - CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc.
+ - CONFIG_EFI_PARTITION GPT partition table, common when EFI is the
+ bootloader. Note 2TB partition limit; see
+ disk/part_efi.c
+ - CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
+ If IDE or SCSI support is enabled (CONFIG_CMD_IDE or CONFIG_SCSI)
+ you must configure support for at least one non-MTD partition type
+ as well.
+
+config MAC_PARTITION
+ bool "Enable Apple's MacOS partition table"
+ depends on PARTITIONS
+ default y if SPARC
+ help
+ Say Y here if you would like to use device under U-Boot which
+ were partitioned on a Macintosh.
+
+config SPL_MAC_PARTITION
+ bool "Enable Apple's MacOS partition table for SPL"
+ depends on SPL && PARTITIONS
+ default y if MAC_PARTITION
+
+config DOS_PARTITION
+ bool "Enable MS Dos partition table"
+ depends on PARTITIONS
+ default y if DISTRO_DEFAULTS
+ default y if x86 || SPARC || CMD_FAT || USB_STORAGE
+ help
+ traditional on the Intel architecture, USB sticks, etc.
+
+config SPL_DOS_PARTITION
+ bool "Enable MS Dos partition table for SPL"
+ depends on SPL && PARTITIONS
+ default y if DOS_PARTITION
+
+config ISO_PARTITION
+ bool "Enable ISO partition table"
+ depends on PARTITIONS
+ default y if DISTRO_DEFAULTS
+ default y if SPARC || MIPS || TEGRA
+
+config SPL_ISO_PARTITION
+ bool "Enable ISO partition table for SPL"
+ depends on SPL && PARTITIONS
+ default y if ISO_PARTITION
+
+config AMIGA_PARTITION
+ bool "Enable AMIGA partition table"
+ depends on PARTITIONS
+ help
+ Say Y here if you would like to use device under U-Boot which
+ were partitioned under AmigaOS.
+
+config SPL_AMIGA_PARTITION
+ bool "Enable AMIGA partition table for SPL"
+ depends on SPL && PARTITIONS
+ default y if AMIGA_PARTITION
+
+config EFI_PARTITION
+ bool "Enable EFI GPT partition table"
+ depends on PARTITIONS
+ default y if DISTRO_DEFAULTS
+ default y if TEGRA
+ help
+ Say Y here if you would like to use device under U-Boot which
+ were partitioned using EFI GPT.
+ common when EFI is the bootloader. Note 2TB partition limit;
+ see disk/part_efi.c
+
+config SPL_EFI_PARTITION
+ bool "Enable EFI GPT partition table for SPL"
+ depends on SPL && PARTITIONS
+ default y if EFI_PARTITION
+
+config PARTITION_UUIDS
+ bool "Enable support of UUID for partition"
+ depends on PARTITIONS
+ default y if DISTRO_DEFAULTS
+ default y if EFI_PARTITION
+ help
+ Activate the configuration of UUID for partition
+
+config SPL_PARTITION_UUIDS
+ bool "Enable support of UUID for partition in SPL"
+ depends on SPL && PARTITIONS
+ default y if SPL_EFI_PARTITION
+
+config PARTITION_TYPE_GUID
+ bool "Enable support of GUID for partition type"
+ depends on PARTITIONS
+ depends on EFI_PARTITION
+ help
+ Activate the configuration of GUID type
+ for EFI partition
+
+endmenu
#ccflags-y += -DET_DEBUG -DDEBUG
obj-$(CONFIG_PARTITIONS) += part.o
-obj-$(CONFIG_MAC_PARTITION) += part_mac.o
-obj-$(CONFIG_DOS_PARTITION) += part_dos.o
-obj-$(CONFIG_ISO_PARTITION) += part_iso.o
-obj-$(CONFIG_AMIGA_PARTITION) += part_amiga.o
-obj-$(CONFIG_EFI_PARTITION) += part_efi.o
+obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o
+obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o
+obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o
+obj-$(CONFIG_$(SPL_)AMIGA_PARTITION) += part_amiga.o
+obj-$(CONFIG_$(SPL_)EFI_PARTITION) += part_efi.o
static void print_part_header(const char *type, struct blk_desc *dev_desc)
{
-#if defined(CONFIG_MAC_PARTITION) || \
- defined(CONFIG_DOS_PARTITION) || \
- defined(CONFIG_ISO_PARTITION) || \
- defined(CONFIG_AMIGA_PARTITION) || \
- defined(CONFIG_EFI_PARTITION)
+#if CONFIG_IS_ENABLED(MAC_PARTITION) || \
+ CONFIG_IS_ENABLED(DOS_PARTITION) || \
+ CONFIG_IS_ENABLED(ISO_PARTITION) || \
+ CONFIG_IS_ENABLED(AMIGA_PARTITION) || \
+ CONFIG_IS_ENABLED(EFI_PARTITION)
puts ("\nPartition Map for ");
switch (dev_desc->if_type) {
case IF_TYPE_IDE:
#ifdef HAVE_BLOCK_DEVICE
struct part_driver *drv;
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
/* The common case is no UUID support */
info->uuid[0] = 0;
#endif
info->bootable = 0;
strcpy((char *)info->type, BOOT_PART_TYPE);
strcpy((char *)info->name, "Sandbox host");
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
info->uuid[0] = 0;
#endif
#ifdef CONFIG_PARTITION_TYPE_GUID
memset(info, 0, sizeof(*info));
strcpy((char *)info->type, BOOT_PART_TYPE);
strcpy((char *)info->name, "UBI");
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
info->uuid[0] = 0;
#endif
return 0;
info->bootable = 0;
strcpy((char *)info->type, BOOT_PART_TYPE);
strcpy((char *)info->name, "Whole Disk");
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
info->uuid[0] = 0;
#endif
#ifdef CONFIG_PARTITION_TYPE_GUID
#define _DISK_PART_AMIGA_H
#include <common.h>
-#ifdef CONFIG_ISO_PARTITION
+#if CONFIG_IS_ENABLED(ISO_PARTITION)
/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS
have 2048 byte blocks */
#define DEFAULT_SECTOR_SIZE 2048
return -1;
}
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
if (!ext_part_sector)
disksig = le32_to_int(&buffer[DOS_PART_DISKSIG_OFFSET]);
#endif
/* sprintf(info->type, "%d, pt->sys_ind); */
strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(pt);
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
sprintf(info->uuid, "%08x-%02x", disksig, part_num);
#endif
return 0;
info->blksz = DOS_PART_DEFAULT_SECTOR;
info->bootable = 0;
strcpy((char *)info->type, "U-Boot");
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
info->uuid[0] = 0;
#endif
return 0;
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
}
-#ifdef CONFIG_EFI_PARTITION
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
/*
* Public Functions (include/part.h)
*/
print_efiname(&gpt_pte[part - 1]));
strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(&gpt_pte[part - 1]);
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
UUID_STR_FORMAT_GUID);
#endif
le64_to_cpu(gpt_h->last_usable_lba);
int i, k;
size_t efiname_len, dosname_len;
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
char *str_uuid;
unsigned char *bin_uuid;
#endif
&PARTITION_BASIC_DATA_GUID, 16);
#endif
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
str_uuid = partitions[i].uuid;
bin_uuid = gpt_e[i].unique_partition_guid.b;
__u32 boot_cksum; /* boot code checksum */
uchar processor[16]; /* Type of Processor */
__u16 part_pad[188]; /* reserved */
-#ifdef CONFIG_ISO_PARTITION
+#if CONFIG_IS_ENABLED(ISO_PARTITION)
uchar iso_dummy[2048];/* Reservere enough room for an ISO partition block to fit */
#endif
} mac_partition_t;
--- /dev/null
+The trusted boot framework on Marvell Armada 38x
+================================================
+
+Contents:
+
+1. Overview of the trusted boot
+2. Terminology
+3. Boot image layout
+4. The secured header
+5. The secured boot flow
+6. Usage example
+7. Work to be done
+8. Bibliography
+
+1. Overview of the trusted boot
+-------------------------------
+
+The Armada's trusted boot framework enables the SoC to cryptographically verify
+a specially prepared boot image. This can be used to establish a chain of trust
+from the boot firmware all the way to the OS.
+
+To achieve this, the Armada SoC requires a specially prepared boot image, which
+contains the relevant cryptographic data, as well as other information
+pertaining to the boot process. Furthermore, a eFuse structure (a
+one-time-writeable memory) need to be configured in the correct way.
+
+Roughly, the secure boot process works as follows:
+
+* Load the header block of the boot image, extract a special "root" public RSA
+ key from it, and verify its SHA-256 hash against a SHA-256 stored in a eFuse
+ field.
+* Load an array of code signing public RSA keys from the header block, and
+ verify its RSA signature (contained in the header block as well) using the
+ "root" RSA key.
+* Choose a code signing key, and use it to verify the header block (excluding
+ the key array).
+* Verify the binary image's signature (contained in the header block) using the
+ code signing key.
+* If all checks pass successfully, boot the image.
+
+The chain of trust is thus as follows:
+
+* The SHA-256 value in the eFuse field verifies the "root" public key.
+* The "root" public key verifies the code signing key array.
+* The selected code signing key verifies the header block and the binary image.
+
+In the special case of building a boot image containing U-Boot as the binary
+image, which employs this trusted boot framework, the following tasks need to
+be addressed:
+
+1. Creation of the needed cryptographic key material.
+2. Creation of a conforming boot image containing the U-Boot image as binary
+ image.
+3. Burning the necessary eFuse values.
+
+(1) will be addressed later, (2) will be taken care of by U-Boot's build
+system (some user configuration is required, though), and for (3) the necessary
+data (essentially a series of U-Boot commands to be entered at the U-Boot
+command prompt) will be created by the build system as well.
+
+The documentation of the trusted boot mode is contained in part 1, chapter
+7.2.5 in the functional specification [1], and in application note [2].
+
+2. Terminology
+--------------
+
+ CSK - Code Signing Key(s): An array of RSA key pairs, which
+ are used to sign and verify the secured header and the
+ boot loader image.
+ KAK - Key Authentication Key: A RSA key pair, which is used
+ to sign and verify the array of CSKs.
+ Header block - The first part of the boot image, which contains the
+ image's headers (also known as "headers block", "boot
+ header", and "image header")
+ eFuse - A one-time-writeable memory.
+ BootROM - The Armada's built-in boot firmware, which is
+ responsible for verifying and starting secure images.
+ Boot image - The complete image the SoC's boot firmware loads
+ (contains the header block and the binary image)
+ Main header - The header in the header block containing information
+ and data pertaining to the boot process (used for both
+ the regular and secured boot processes)
+ Binary image - The binary code payload of the boot image; in this
+ case the U-Boot's code (also known as "source image",
+ or just "image")
+ Secured header - The specialized header in the header block that
+ contains information and data pertaining to the
+ trusted boot (also known as "security header")
+ Secured boot mode - A special boot mode of the Armada SoC in which secured
+ images are verified (non-secure images won't boot);
+ the mode is activated by setting a eFuse field.
+ Trusted debug mode - A special mode for the trusted boot that allows
+ debugging of devices employing the trusted boot
+ framework in a secure manner (untested in the current
+ implementation).
+Trusted boot framework - The ARMADA SoC's implementation of a secure verified
+ boot process.
+
+3. Boot image layout
+--------------------
+
++-- Boot image --------------------------------------------+
+| |
+| +-- Header block --------------------------------------+ |
+| | Main header | |
+| +------------------------------------------------------+ |
+| | Secured header | |
+| +------------------------------------------------------+ |
+| | BIN header(s) | |
+| +------------------------------------------------------+ |
+| | REG header(s) | |
+| +------------------------------------------------------+ |
+| | Padding | |
+| +------------------------------------------------------+ |
+| |
+| +------------------------------------------------------+ |
+| | Binary image + checksum | |
+| +------------------------------------------------------+ |
++----------------------------------------------------------+
+
+4. The secured header
+---------------------
+
+For the trusted boot framework, a additional header is added to the boot image.
+The following data are relevant for the secure boot:
+
+ KAK: The KAK is contained in the secured header in the form
+ of a RSA-2048 public key in DER format with a length of
+ 524 bytes.
+Header block signature: The RSA signature of the header block (excluding the
+ CSK array), created using the selected CSK.
+Binary image signature: The RSA signature of the binary image, created using
+ the selected CSK.
+ CSK array: The array of the 16 CSKs as RSA-2048 public keys in DER
+ format with a length of 8384 = 16 * 524 bytes.
+ CSK block signature: The RSA signature of the CSK array, created using the
+ KAK.
+
+NOTE: The JTAG delay, Box ID, and Flash ID header fields do play a role in the
+trusted boot process to enable and configure secure debugging, but they were
+not tested in the current implementation of the trusted boot in U-Boot.
+
+5. The secured boot flow
+------------------------
+
+The steps in the boot flow that are relevant for the trusted boot framework
+proceed as follows:
+
+1) Check if trusted boot is enabled, and perform regular boot if it is not.
+2) Load the secured header, and verify its checksum.
+3) Select the lowest valid CSK from CSK0 to CSK15.
+4) Verify the SHA-256 hash of the KAK embedded in the secured header.
+5) Verify the RSA signature of the CSK block from the secured header with the
+ KAK.
+6) Verify the header block signature (which excludes the CSK block) from the
+ secured header with the selected CSK.
+7) Load the binary image to the main memory and verify its checksum.
+8) Verify the binary image's RSA signature from the secured header with the
+ selected CSK.
+9) Continue the boot process as in the case of the regular boot.
+
+NOTE: All RSA signatures are verified according to the PKCS #1 v2.1 standard
+described in [3].
+
+NOTE: The Box ID and Flash ID are checked after step 6, and the trusted debug
+mode may be entered there, but since this mode is untested in the current
+implementation, it is not described further.
+
+6. Usage example
+----------------
+
+### Create key material
+
+To employ the trusted boot framework, cryptographic key material needs to be
+created. In the current implementation, two keys are needed to build a valid
+secured boot image: The KAK private key and a CSK private key (both have to be
+2048 bit RSA keys in PEM format). Note that the usage of more than one CSK is
+currently not supported.
+
+NOTE: Since the public key can be generated from the private key, it is
+sufficient to store the private key for each key pair.
+
+OpenSSL can be used to generate the needed files kwb_kak.key and kwb_csk.key
+(the names of these files have to be configured, see the next section on
+kwbimage.cfg settings):
+
+openssl genrsa -out kwb_kak.key 2048
+openssl genrsa -out kwb_csk.key 2048
+
+The generated files have to be placed in the U-Boot root directory.
+
+Alternatively, instead of copying the files, symlinks to the private keys can
+be placed in the U-Boot root directory.
+
+WARNING: Knowledge of the KAK or CSK private key would enable an attacker to
+generate secured boot images containing arbitrary code. Hence, the private keys
+should be carefully guarded.
+
+### Create/Modifiy kwbimage.cfg
+
+The Kirkwook architecture in U-Boot employs a special board-specific
+configuration file (kwbimage.cfg), which controls various boot image settings
+that are interpreted by the BootROM, such as the boot medium. The support the
+trusted boot framework, several new options were added to faciliate
+configuration of the secured boot.
+
+The configuration file's layout has been retained, only the following new
+options were added:
+
+ KAK - The name of the KAK RSA private key file in the U-Boot
+ root directory, without the trailing extension of ".key".
+ CSK - The name of the (active) CSK RSA private key file in the
+ U-Boot root directory, without the trailing extension of
+ ".key".
+ BOX_ID - The BoxID to be used for trusted debugging (a integer
+ value).
+ FLASH_ID - The FlashID to be used for trusted debugging (a integer
+ value).
+ JTAG_DELAY - The JTAG delay to be used for trusted debugging (a
+ integer value).
+ CSK_INDEX - The index of the active CSK (a integer value).
+SEC_SPECIALIZED_IMG - Flag to indicate whether to include the BoxID and FlashID
+ in the image (that is, whether to use the trusted debug
+ mode or not); no parameters.
+ SEC_BOOT_DEV - The boot device from which the trusted boot is allowed to
+ proceed, identified via a numeric ID. The tested values
+ are 0x34 = NOR flash, 0x31 = SDIO/MMC card; for
+ additional ID values, consult the documentation in [1].
+ SEC_FUSE_DUMP - Dump the "fuse prog" commands necessary for writing the
+ correct eFuse values to a text file in the U-Boot root
+ directory. The parameter is the architecture for which to
+ dump the commands (currently only "a38x" is supported).
+
+The parameter values may be hardcoded into the file, but it is also possible to
+employ a dynamic approach of creating a Autoconf-like kwbimage.cfg.in, then
+reading configuration values from Kconfig options or from the board config
+file, and generating the actual kwbimage.cfg from this template using Makefile
+mechanisms (see board/gdsys/a38x/Makefile as an example for this approach).
+
+### Set config options
+
+To enable the generation of trusted boot images, the corresponding support
+needs to be activated, and a index for the active CSK needs to be selected as
+well.
+
+Furthermore, eFuse writing support has to be activated in order to burn the
+eFuse structure's values (this option is just needed for programming the eFuse
+structure; production boot images may disable it).
+
+ARM architecture
+ -> [*] Build image for trusted boot
+ (0) Index of active CSK
+ -> [*] Enable eFuse support
+ [ ] Fake eFuse access (dry run)
+
+### Build and test boot image
+
+The creation of the boot image is done via the usual invocation of make (with a
+suitably set CROSS_COMPILE environment variable, of course). The resulting boot
+image u-boot-spl.kwb can then be tested, if so desired. The hdrparser from [5]
+can be used for this purpose. To build the tool, invoke make in the
+'tools/marvell/doimage_mv' directory of [5], which builds a stand-alone
+hdrparser executable. A test can be conducted by calling hdrparser with the
+produced boot image and the following (mandatory) parameters:
+
+./hdrparser -k 0 -t u-boot-spl.kwb
+
+Here we assume that the CSK index is 0 and the boot image file resides in the
+same directory (adapt accordingly if needed). The tool should report that all
+checksums are valid ("GOOD"), that all signature verifications succeed
+("PASSED"), and, finally, that the overall test was successful
+("T E S T S U C C E E D E D" in the last line of output).
+
+### Burn eFuse structure
+
++----------------------------------------------------------+
+| WARNING: Burning the eFuse structure is a irreversible |
+| operation! Should wrong or corrupted values be used, the |
+| board won't boot anymore, and recovery is likely |
+| impossible! |
++----------------------------------------------------------+
+
+After the build process has finished, and the SEC_FUSE_DUMP option was set in
+the kwbimage.cfg was set, a text file kwb_fuses_a38x.txt should be present in
+the U-Boot top-level directory. It contains all the necessary commands to set
+the eFuse structure to the values needed for the used KAK digest, as well as
+the CSK index, Flash ID and Box ID that were selected in kwbimage.cfg.
+
+Sequentially executing the commands in this file at the U-Boot command prompt
+will write these values to the eFuse structure.
+
+If the SEC_FUSE_DUMP option was not set, the commands needed to burn the fuses
+have to be crafted by hand. The needed fuse lines can be looked up in [1]; a
+rough overview of the process is:
+
+* Burn the KAK public key hash. The hash itself can be found in the file
+ pub_kak_hash.txt in the U-Boot top-level directory; be careful to account for
+ the endianness!
+* Burn the CSK selection, BoxID, and FlashID
+* Enable trusted boot by burning the corresponding fuse (WARNING: this must be
+ the last fuse line written!)
+* Lock the unused fuse lines
+
+The command to employ is the "fuse prog" command previously enabled by setting
+the corresponding configuration option.
+
+For the trusted boot, the fuse prog command has a special syntax, since the
+ARMADA SoC demands that whole fuse lines (64 bit values) have to be written as
+a whole. The fuse prog command itself allows lists of 32 bit words to be
+written at a time, but this is translated to a series of single 32 bit write
+operations to the fuse line, where the individual 32 bit words are identified
+by a "word" counter that is increased for each write.
+
+To work around this restriction, we interpret each line to have three "words"
+(0-2): The first and second words are the values to be written to the fuse
+line, and the third is a lock flag, which is supposed to lock the fuse line
+when set to 1. Writes to the first and second words are memoized between
+function calls, and the fuse line is only really written and locked (on writing
+the third word) if both words were previously set, so that "incomplete" writes
+are prevented. An exception to this is a single write to the third word (index
+2) without previously writing neither the first nor the second word, which
+locks the fuse line without setting any value; this is needed to lock the
+unused fuse lines.
+
+As an example, to write the value 0011223344556677 to fuse line 10, we would
+use the following command:
+
+fuse prog -y 10 0 00112233 44556677 1
+
+Here 10 is the fuse line number, 0 is the index of the first word to be
+written, 00112233 and 44556677 are the values to be written to the fuse line
+(first and second word) and the trailing 1 is the value for the third word
+responsible for locking the line.
+
+A "lock-only" command would look like this:
+
+fuse prog -y 11 2 1
+
+Here 11 is the fuse number, 2 is the index of the first word to be written
+(notice that we only write to word 2 here; the third word for fuse line
+locking), and the 1 is the value for the word we are writing to.
+
+WARNING: According to application note [4], the VHV pin of the SoC must be
+connected to a 1.8V source during eFuse programming, but *must* be disconnected
+for normal operation. The AN [4] describes a software-controlled circuit (based
+on a N-channel or P-channel FET and a free GPIO pin of the SoC) to achieve
+this, but a jumper-based circuit should suffice as well. Regardless of the
+chosen circuit, the issue needs to be addressed accordingly!
+
+7. Work to be done
+------------------
+
+* Add the ability to populate more than one CSK
+* Test secure debug
+* Test on Armada XP
+
+8. Bibliography
+---------------
+
+[1] ARMADA(R) 38x Family High-Performance Single/Dual CPU System on Chip
+ Functional Specification; MV-S109094-00, Rev. C; August 2, 2015,
+ Preliminary
+[2] AN-383: ARMADA(R) 38x Families Secure Boot Mode Support; MV-S302501-00
+ Rev. A; March 11, 2015, Preliminary
+[3] Public-Key Cryptography Standards (PKCS) #1: RSA Cryptography
+ Specifications Version 2.1; February 2003;
+ https://www.ietf.org/rfc/rfc3447.txt
+[4] AN-389: ARMADA(R) VHV Power; MV-S302545-00 Rev. B; January 28, 2016,
+ Released
+[5] Marvell Armada 38x U-Boot support; November 25, 2015;
+ https://github.com/MarvellEmbeddedProcessors/u-boot-marvell
+
+2017-01-05, Mario Six <mario.six@gdsys.cc>
and the board definition files needs:
/* SD/MMC card */
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
#define CONFIG_GENERIC_ATMEL_MCI 1
#define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */
#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
To enable the authenticated or encrypted boot mode of U-Boot, it is
required to set the proper configuration for the target board. This
-is done by adding the following configuration in in the proper config
-file (e.g. include/configs/mx6qarm2.h)
+is done by adding the following configuration in the defconfig file:
-#define CONFIG_SECURE_BOOT
+CONFIG_SECURE_BOOT=y
In addition, the U-Boot image to be programmed into the
boot media needs to be properly constructed, i.e. it must contain a
Here are macro and detailed configuration required to enable DesignWare SDMMC
controller support within SOCFPGA
-#define CONFIG_GENERIC_MMC
--> Enable the generic MMC driver
-
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
--- /dev/null
+STM32 QSPI controller device tree bindings
+--------------------------------------------
+
+Required properties:
+- compatible : should be "st,stm32-qspi".
+- reg : 1. Physical base address and size of SPI registers map.
+ 2. Physical base address & size of mapped NOR Flash.
+- spi-max-frequency : Max supported spi frequency.
+- status : enable in requried dts.
+
+Connected flash properties
+--------------------------
+- spi-max-frequency : Max supported spi frequency.
+- spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
+- spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
+- memory-map : Address and size for memory-mapping the flash
+
+Example:
+ qspi: quadspi@A0001000 {
+ compatible = "st,stm32-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <92>;
+ spi-max-frequency = <108000000>;
+ status = "okay";
+
+ qflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a13", "spi-flash";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ memory-map = <0x90000000 0x1000000>;
+ reg = <0>;
+ };
+ };
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
--- /dev/null
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/ast2500-scu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * For H-PLL and M-PLL the formula is
+ * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
+ * M - Numerator
+ * N - Denumerator
+ * P - Post Divider
+ * They have the same layout in their control register.
+ */
+
+/*
+ * Get the rate of the M-PLL clock from input clock frequency and
+ * the value of the M-PLL Parameter Register.
+ */
+static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
+{
+ const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
+ const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
+ & SCU_MPLL_DENUM_MASK;
+ const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
+ & SCU_MPLL_POST_MASK;
+
+ return (clkin * ((num + 1) / (denum + 1))) / post_div;
+}
+
+/*
+ * Get the rate of the H-PLL clock from input clock frequency and
+ * the value of the H-PLL Parameter Register.
+ */
+static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
+{
+ const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
+ const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
+ & SCU_HPLL_DENUM_MASK;
+ const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
+ & SCU_HPLL_POST_MASK;
+
+ return (clkin * ((num + 1) / (denum + 1))) / post_div;
+}
+
+static ulong ast2500_get_clkin(struct ast2500_scu *scu)
+{
+ return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
+ ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
+}
+
+/**
+ * Get current rate or uart clock
+ *
+ * @scu SCU registers
+ * @uart_index UART index, 1-5
+ *
+ * @return current setting for uart clock rate
+ */
+static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
+{
+ /*
+ * ast2500 datasheet is very confusing when it comes to UART clocks,
+ * especially when CLKIN = 25 MHz. The settings are in
+ * different registers and it is unclear how they interact.
+ *
+ * This has only been tested with default settings and CLKIN = 24 MHz.
+ */
+ ulong uart_clkin;
+
+ if (readl(&scu->misc_ctrl2) &
+ (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
+ uart_clkin = 192 * 1000 * 1000;
+ else
+ uart_clkin = 24 * 1000 * 1000;
+
+ if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
+ uart_clkin /= 13;
+
+ return uart_clkin;
+}
+
+static ulong ast2500_clk_get_rate(struct clk *clk)
+{
+ struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong clkin = ast2500_get_clkin(priv->scu);
+ ulong rate;
+
+ switch (clk->id) {
+ case PLL_HPLL:
+ case ARMCLK:
+ /*
+ * This ignores dynamic/static slowdown of ARMCLK and may
+ * be inaccurate.
+ */
+ rate = ast2500_get_hpll_rate(clkin,
+ readl(&priv->scu->h_pll_param));
+ break;
+ case MCLK_DDR:
+ rate = ast2500_get_mpll_rate(clkin,
+ readl(&priv->scu->m_pll_param));
+ break;
+ case PCLK_UART1:
+ rate = ast2500_get_uart_clk_rate(priv->scu, 1);
+ break;
+ case PCLK_UART2:
+ rate = ast2500_get_uart_clk_rate(priv->scu, 2);
+ break;
+ case PCLK_UART3:
+ rate = ast2500_get_uart_clk_rate(priv->scu, 3);
+ break;
+ case PCLK_UART4:
+ rate = ast2500_get_uart_clk_rate(priv->scu, 4);
+ break;
+ case PCLK_UART5:
+ rate = ast2500_get_uart_clk_rate(priv->scu, 5);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static void ast2500_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+static void ast2500_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
+
+static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
+{
+ ulong clkin = ast2500_get_clkin(scu);
+ u32 mpll_reg;
+
+ /*
+ * There are not that many combinations of numerator, denumerator
+ * and post divider, so just brute force the best combination.
+ * However, to avoid overflow when multiplying, use kHz.
+ */
+ const ulong clkin_khz = clkin / 1000;
+ const ulong rate_khz = rate / 1000;
+ ulong best_num = 0;
+ ulong best_denum = 0;
+ ulong best_post = 0;
+ ulong delta = rate;
+ ulong num, denum, post;
+
+ for (denum = 0; denum <= SCU_MPLL_DENUM_MASK; ++denum) {
+ for (post = 0; post <= SCU_MPLL_POST_MASK; ++post) {
+ num = (rate_khz * (post + 1) / clkin_khz) * (denum + 1);
+ ulong new_rate_khz = (clkin_khz
+ * ((num + 1) / (denum + 1)))
+ / (post + 1);
+
+ /* Keep the rate below requested one. */
+ if (new_rate_khz > rate_khz)
+ continue;
+
+ if (new_rate_khz - rate_khz < delta) {
+ delta = new_rate_khz - rate_khz;
+
+ best_num = num;
+ best_denum = denum;
+ best_post = post;
+
+ if (delta == 0)
+ goto rate_calc_done;
+ }
+ }
+ }
+
+ rate_calc_done:
+ mpll_reg = readl(&scu->m_pll_param);
+ mpll_reg &= ~((SCU_MPLL_POST_MASK << SCU_MPLL_POST_SHIFT)
+ | (SCU_MPLL_NUM_MASK << SCU_MPLL_NUM_SHIFT)
+ | (SCU_MPLL_DENUM_MASK << SCU_MPLL_DENUM_SHIFT));
+ mpll_reg |= (best_post << SCU_MPLL_POST_SHIFT)
+ | (best_num << SCU_MPLL_NUM_SHIFT)
+ | (best_denum << SCU_MPLL_DENUM_SHIFT);
+
+ ast2500_scu_unlock(scu);
+ writel(mpll_reg, &scu->m_pll_param);
+ ast2500_scu_lock(scu);
+
+ return ast2500_get_mpll_rate(clkin, mpll_reg);
+}
+
+static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
+
+ ulong new_rate;
+ switch (clk->id) {
+ case PLL_MPLL:
+ case MCLK_DDR:
+ new_rate = ast2500_configure_ddr(priv->scu, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+struct clk_ops ast2500_clk_ops = {
+ .get_rate = ast2500_clk_get_rate,
+ .set_rate = ast2500_clk_set_rate,
+};
+
+static int ast2500_clk_probe(struct udevice *dev)
+{
+ struct ast2500_clk_priv *priv = dev_get_priv(dev);
+
+ priv->scu = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+
+ return 0;
+}
+
+static int ast2500_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
+ if (ret)
+ debug("Warning: No reset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
+static const struct udevice_id ast2500_clk_ids[] = {
+ { .compatible = "aspeed,ast2500-scu" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_ast2500_scu) = {
+ .name = "aspeed_ast2500_scu",
+ .id = UCLASS_CLK,
+ .of_match = ast2500_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
+ .ops = &ast2500_clk_ops,
+ .bind = ast2500_clk_bind,
+ .probe = ast2500_clk_probe,
+};
.data = (ulong)&uniphier_mio_clk_data,
},
{
- .compatible = "socionext,uniphier-pro5-mio-clock",
+ .compatible = "socionext,uniphier-pro5-sd-clock",
.data = (ulong)&uniphier_mio_clk_data,
},
{
- .compatible = "socionext,uniphier-pxs2-mio-clock",
+ .compatible = "socionext,uniphier-pxs2-sd-clock",
.data = (ulong)&uniphier_mio_clk_data,
},
{
.data = (ulong)&uniphier_mio_clk_data,
},
{
- .compatible = "socionext,uniphier-ld20-mio-clock",
+ .compatible = "socionext,uniphier-ld20-sd-clock",
.data = (ulong)&uniphier_mio_clk_data,
},
{ /* sentinel */ }
#include <common.h>
#include <linux/types.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/sizes.h>
#include <linux/errno.h>
#include <dm/device.h>
-#include <dm/root.h>
#include <i2c.h>
#include <fdtdec.h>
unsigned long timeout; /* time out (us) */
};
-static int poll_status(u32 __iomem *reg, u32 flag)
-{
- int wait = 1000000; /* 1 sec is long enough */
-
- while (readl(reg) & flag) {
- if (wait-- < 0)
- return -EREMOTEIO;
- udelay(1);
- }
-
- return 0;
-}
-
static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
{
+ u32 val;
int ret;
/* bus forcible reset */
writel(I2C_RST_RST, ®s->rst);
- ret = poll_status(®s->rst, I2C_RST_RST);
+ ret = readl_poll_timeout(®s->rst, val, !(val & I2C_RST_RST), 1);
if (ret < 0)
debug("error: fail to reset I2C controller\n");
static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
{
+ u32 val;
int ret;
- ret = poll_status(®s->sr, I2C_SR_DB);
+ ret = readl_poll_timeout(®s->sr, val, !(val & I2C_SR_DB), 100);
if (ret < 0) {
debug("error: device busy too long. reset...\n");
ret = reset_bus(regs);
bool *stop)
{
u32 irq;
- unsigned long wait = dev->timeout;
- int ret = -EREMOTEIO;
-
- do {
- udelay(1);
- irq = readl(&dev->regs->intr);
- } while (!(irq & flags) && wait--);
+ int ret;
- if (wait < 0) {
+ ret = readl_poll_timeout(&dev->regs->intr, irq, irq & flags,
+ dev->timeout);
+ if (ret < 0) {
debug("error: time out\n");
return ret;
}
debug("stop condition\n");
writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
- ret = poll_status(&dev->regs->sr, I2C_SR_DB);
+ ret = check_device_busy(dev->regs);
if (ret < 0)
debug("error: device busy after operation\n");
#include <linux/sizes.h>
#include <linux/errno.h>
#include <dm/device.h>
-#include <dm/root.h>
#include <i2c.h>
#include <fdtdec.h>
If you want MMC/SD/SDIO support, you should say Y here and
also to your specific host controller driver.
+config GENERIC_MMC
+ bool "Generic MMC driver framework"
+ default MMC
+
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
operations too, which can remove the need for malloc support in SPL
and thus further reduce footprint.
-config MSM_SDHCI
- bool "Qualcomm SDHCI controller"
- depends on DM_MMC && BLK && DM_MMC_OPS
- depends on MMC_SDHCI
- help
- Enables support for SDHCI 2.0 controller present on some Qualcomm
- Snapdragon devices. This device is compatible with eMMC v4.5 and
- SD 3.0 specifications. Both SD and eMMC devices are supported.
- Card-detect gpios are not supported.
-
-config ATMEL_SDHCI
- bool "Atmel SDHCI controller support"
- depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
- depends on MMC_SDHCI
- help
- This enables support for the Atmel SDHCI controller, which supports
- the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
- Memory Card Specification V3.0, and the SDIO V3.0 specification.
- It is compliant with the SD Host Controller Standard V3.0
- specification.
-
config MMC_DAVINCI
bool "TI DAVINCI Multimedia Card Interface support"
depends on ARCH_DAVINCI
help
Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
-config PIC32_SDHCI
- bool "Microchip PIC32 on-chip SDHCI support"
- depends on DM_MMC && MACH_PIC32
- depends on MMC_SDHCI
- help
- Support for Microchip PIC32 SDHCI controller.
-
-config ZYNQ_SDHCI
- bool "Arasan SDHCI controller support"
- depends on DM_MMC && OF_CONTROL && BLK && DM_MMC_OPS
- depends on MMC_SDHCI
- help
- Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
-
-config ROCKCHIP_SDHCI
- bool "Arasan SDHCI controller for Rockchip support"
- depends on DM_MMC && BLK && DM_MMC_OPS
- depends on MMC_SDHCI
- help
- Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
-
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
help
This selects support for the SD/MMC Host Controller on UniPhier SoCs.
-config SANDBOX_MMC
+config MMC_SANDBOX
bool "Sandbox MMC support"
- depends on MMC && SANDBOX
+ depends on SANDBOX
+ depends on BLK && DM_MMC_OPS && OF_CONTROL
help
This select a dummy sandbox MMC driver. At present this does nothing
other than allow sandbox to be build with MMC support. This
This enables support for the SDMA (Single Operation DMA) defined
in the SD Host Controller Standard Specification Version 1.00 .
+config MMC_SDHCI_ATMEL
+ bool "Atmel SDHCI controller support"
+ depends on ARCH_AT91
+ depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+ depends on MMC_SDHCI
+ help
+ This enables support for the Atmel SDHCI controller, which supports
+ the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
+ Memory Card Specification V3.0, and the SDIO V3.0 specification.
+ It is compliant with the SD Host Controller Standard V3.0
+ specification.
+
config MMC_SDHCI_BCM2835
tristate "SDHCI support for the BCM2835 SD/MMC Controller"
depends on ARCH_BCM283X
If you have a controller with this interface, say Y here.
+config MMC_SDHCI_MSM
+ bool "Qualcomm SDHCI controller"
+ depends on BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
+ help
+ Enables support for SDHCI 2.0 controller present on some Qualcomm
+ Snapdragon devices. This device is compatible with eMMC v4.5 and
+ SD 3.0 specifications. Both SD and eMMC devices are supported.
+ Card-detect gpios are not supported.
+
config MMC_SDHCI_MV
bool "SDHCI support on Marvell platform"
depends on ARCH_MVEBU
If unsure, say N.
+config MMC_SDHCI_PIC32
+ bool "Microchip PIC32 on-chip SDHCI support"
+ depends on DM_MMC && MACH_PIC32
+ depends on MMC_SDHCI
+ help
+ Support for Microchip PIC32 SDHCI controller.
+
+config MMC_SDHCI_ROCKCHIP
+ bool "Arasan SDHCI controller for Rockchip support"
+ depends on ARCH_ROCKCHIP
+ depends on DM_MMC && BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
+ help
+ Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
+
config MMC_SDHCI_S5P
bool "SDHCI support on Samsung S5P SoC"
depends on MMC_SDHCI
If unsure, say N.
+config MMC_SDHCI_ZYNQ
+ bool "Arasan SDHCI controller support"
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP
+ depends on DM_MMC && OF_CONTROL && BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
+ help
+ Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
+
config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
endif
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
-obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
-ifdef CONFIG_BLK
-ifdef CONFIG_GENERIC_MMC
-obj-$(CONFIG_SANDBOX) += sandbox_mmc.o
-endif
-endif
+obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
-obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
-obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
endif
-obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
-obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o
# SDHCI
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_MSM) += msm_sdhci.o
obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
{ .compatible = "allwinner,sun7i-a20-gmac" },
{ .compatible = "altr,socfpga-stmmac" },
{ .compatible = "amlogic,meson6-dwmac" },
+ { .compatible = "st,stm32-dwmac" },
{ }
};
return genphy_config_aneg(phydev);
}
+static int m88e1680_config(struct phy_device *phydev)
+{
+ /*
+ * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
+ * Errata Section 4.1
+ */
+ u16 reg;
+ int res;
+
+ /* Matrix LED mode (not neede if single LED mode is used */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
+ reg |= (1 << 5);
+ phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
+
+ /* QSGMII TX amplitude change */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
+ phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
+ phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
+
+ /* EEE initialization */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
+ phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
+ phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
+
+ res = genphy_config_aneg(phydev);
+ if (res < 0)
+ return res;
+
+ /* soft reset */
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ reg |= BMCR_RESET;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
+
+ return 0;
+}
+
static struct phy_driver M88E1011S_driver = {
.name = "Marvell 88E1011S",
.uid = 0x1410c60,
.shutdown = &genphy_shutdown,
};
+static struct phy_driver M88E1680_driver = {
+ .name = "Marvell 88E1680",
+ .uid = 0x1410ed0,
+ .mask = 0xffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &m88e1680_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_marvell_init(void)
{
phy_register(&M88E1310_driver);
phy_register(&M88E1011S_driver);
phy_register(&M88E1510_driver);
phy_register(&M88E1518_driver);
+ phy_register(&M88E1680_driver);
return 0;
}
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
+
+static struct phy_driver lan8742_driver = {
+ .name = "SMSC LAN8742",
+ .uid = 0x0007c130,
+ .mask = 0xffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_smsc_init(void)
{
phy_register(&lan8710_driver);
phy_register(&lan911x_driver);
phy_register(&lan8700_driver);
phy_register(&lan8740_driver);
+ phy_register(&lan8742_driver);
return 0;
}
#if defined(CONFIG_ARMADA_38X)
#define PCIE_BASE(if) \
((if) == 0 ? \
- MVEBU_REG_PCIE_BASE + 0x40000 : \
- MVEBU_REG_PCIE_BASE + 0x4000 * (if))
+ MVEBU_REG_PCIE0_BASE : \
+ (MVEBU_REG_PCIE_BASE + 0x4000 * (if - 1)))
/*
* On A38x MV6820 these PEX ports are supported:
* 0 - Port 0.0
- * 1 - Port 0.1
- * 2 - Port 0.2
+ * 1 - Port 1.0
+ * 2 - Port 2.0
+ * 3 - Port 3.0
*/
-#define MAX_PEX 3
+#define MAX_PEX 4
static struct mvebu_pcie pcie_bus[MAX_PEX];
static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
int *mem_target, int *mem_attr)
{
- u8 port[] = { 0, 1, 2 };
- u8 lane[] = { 0, 0, 0 };
- u8 target[] = { 8, 4, 4 };
- u8 attr[] = { 0xe8, 0xe8, 0xd8 };
+ u8 port[] = { 0, 1, 2, 3 };
+ u8 lane[] = { 0, 0, 0, 0 };
+ u8 target[] = { 8, 4, 4, 4 };
+ u8 attr[] = { 0xe8, 0xe8, 0xd8, 0xb8 };
pcie->port = port[pex_idx];
pcie->lane = lane[pex_idx];
mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);
/* Don't read at all from pci registers if port power is down */
- if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
- i += 3;
- debug("%s: skipping port %d\n", __func__, pcie->port);
+ if (SELECT(soc_ctrl, pcie->port) == 0) {
+ if (pcie->lane == 0)
+ debug("%s: skipping port %d\n", __func__, pcie->port);
continue;
}
}
node = fdt_node_offset_by_compatible(blob, -1,
- "marvell,armada-3700-sdio");
+ "marvell,armada-8k-sdhci");
if (node <= 0) {
- debug("No SDIO node in DT, looking for MMC one\n");
- node = fdt_node_offset_by_compatible(blob, -1,
- "marvell,xenon-sdhci");
+ node = fdt_node_offset_by_compatible(
+ blob, -1, "marvell,armada-3700-sdhci");
}
if (node > 0) {
};
};
+config STM32_QSPI
+ bool "STM32F7 QSPI driver"
+ depends on STM32F7
+ help
+ Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash chips on platforms embedding
+ this ST IP core.
+
config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
+obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
--- /dev/null
+/*
+ * (C) Copyright 2016
+ *
+ * Michael Kurz, <michi.kurz@gmail.com>
+ *
+ * STM32 QSPI driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/stm32_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct stm32_qspi_regs {
+ u32 cr; /* 0x00 */
+ u32 dcr; /* 0x04 */
+ u32 sr; /* 0x08 */
+ u32 fcr; /* 0x0C */
+ u32 dlr; /* 0x10 */
+ u32 ccr; /* 0x14 */
+ u32 ar; /* 0x18 */
+ u32 abr; /* 0x1C */
+ u32 dr; /* 0x20 */
+ u32 psmkr; /* 0x24 */
+ u32 psmar; /* 0x28 */
+ u32 pir; /* 0x2C */
+ u32 lptr; /* 0x30 */
+};
+
+/*
+ * QUADSPI control register
+ */
+#define STM32_QSPI_CR_EN BIT(0)
+#define STM32_QSPI_CR_ABORT BIT(1)
+#define STM32_QSPI_CR_DMAEN BIT(2)
+#define STM32_QSPI_CR_TCEN BIT(3)
+#define STM32_QSPI_CR_SSHIFT BIT(4)
+#define STM32_QSPI_CR_DFM BIT(6)
+#define STM32_QSPI_CR_FSEL BIT(7)
+#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
+#define STM32_QSPI_CR_FTHRES_SHIFT (8)
+#define STM32_QSPI_CR_TEIE BIT(16)
+#define STM32_QSPI_CR_TCIE BIT(17)
+#define STM32_QSPI_CR_FTIE BIT(18)
+#define STM32_QSPI_CR_SMIE BIT(19)
+#define STM32_QSPI_CR_TOIE BIT(20)
+#define STM32_QSPI_CR_APMS BIT(22)
+#define STM32_QSPI_CR_PMM BIT(23)
+#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
+#define STM32_QSPI_CR_PRESCALER_SHIFT (24)
+
+/*
+ * QUADSPI device configuration register
+ */
+#define STM32_QSPI_DCR_CKMODE BIT(0)
+#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
+#define STM32_QSPI_DCR_CSHT_SHIFT (8)
+#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
+#define STM32_QSPI_DCR_FSIZE_SHIFT (16)
+
+/*
+ * QUADSPI status register
+ */
+#define STM32_QSPI_SR_TEF BIT(0)
+#define STM32_QSPI_SR_TCF BIT(1)
+#define STM32_QSPI_SR_FTF BIT(2)
+#define STM32_QSPI_SR_SMF BIT(3)
+#define STM32_QSPI_SR_TOF BIT(4)
+#define STM32_QSPI_SR_BUSY BIT(5)
+#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
+#define STM32_QSPI_SR_FLEVEL_SHIFT (8)
+
+/*
+ * QUADSPI flag clear register
+ */
+#define STM32_QSPI_FCR_CTEF BIT(0)
+#define STM32_QSPI_FCR_CTCF BIT(1)
+#define STM32_QSPI_FCR_CSMF BIT(3)
+#define STM32_QSPI_FCR_CTOF BIT(4)
+
+/*
+ * QUADSPI communication configuration register
+ */
+#define STM32_QSPI_CCR_DDRM BIT(31)
+#define STM32_QSPI_CCR_DHHC BIT(30)
+#define STM32_QSPI_CCR_SIOO BIT(28)
+#define STM32_QSPI_CCR_FMODE_SHIFT (26)
+#define STM32_QSPI_CCR_DMODE_SHIFT (24)
+#define STM32_QSPI_CCR_DCYC_SHIFT (18)
+#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
+#define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
+#define STM32_QSPI_CCR_ABMODE_SHIFT (14)
+#define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
+#define STM32_QSPI_CCR_ADMODE_SHIFT (10)
+#define STM32_QSPI_CCR_IMODE_SHIFT (8)
+#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
+
+enum STM32_QSPI_CCR_IMODE {
+ STM32_QSPI_CCR_IMODE_NONE = 0,
+ STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
+ STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
+ STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
+};
+
+enum STM32_QSPI_CCR_ADMODE {
+ STM32_QSPI_CCR_ADMODE_NONE = 0,
+ STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
+ STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
+ STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
+};
+
+enum STM32_QSPI_CCR_ADSIZE {
+ STM32_QSPI_CCR_ADSIZE_8BIT = 0,
+ STM32_QSPI_CCR_ADSIZE_16BIT = 1,
+ STM32_QSPI_CCR_ADSIZE_24BIT = 2,
+ STM32_QSPI_CCR_ADSIZE_32BIT = 3,
+};
+
+enum STM32_QSPI_CCR_ABMODE {
+ STM32_QSPI_CCR_ABMODE_NONE = 0,
+ STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
+ STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
+ STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
+};
+
+enum STM32_QSPI_CCR_ABSIZE {
+ STM32_QSPI_CCR_ABSIZE_8BIT = 0,
+ STM32_QSPI_CCR_ABSIZE_16BIT = 1,
+ STM32_QSPI_CCR_ABSIZE_24BIT = 2,
+ STM32_QSPI_CCR_ABSIZE_32BIT = 3,
+};
+
+enum STM32_QSPI_CCR_DMODE {
+ STM32_QSPI_CCR_DMODE_NONE = 0,
+ STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
+ STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
+ STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
+};
+
+enum STM32_QSPI_CCR_FMODE {
+ STM32_QSPI_CCR_IND_WRITE = 0,
+ STM32_QSPI_CCR_IND_READ = 1,
+ STM32_QSPI_CCR_AUTO_POLL = 2,
+ STM32_QSPI_CCR_MEM_MAP = 3,
+};
+
+/* default SCK frequency, unit: HZ */
+#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
+
+struct stm32_qspi_platdata {
+ u32 base;
+ u32 memory_map;
+ u32 max_hz;
+};
+
+struct stm32_qspi_priv {
+ struct stm32_qspi_regs *regs;
+ u32 max_hz;
+ u32 mode;
+
+ u32 command;
+ u32 address;
+ u32 dummycycles;
+#define CMD_HAS_ADR BIT(24)
+#define CMD_HAS_DUMMY BIT(25)
+#define CMD_HAS_DATA BIT(26)
+};
+
+static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
+{
+ clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
+}
+
+static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
+{
+ setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
+}
+
+static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
+{
+ while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
+ ;
+}
+
+static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
+{
+ while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
+ ;
+}
+
+static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
+{
+ while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
+ ;
+}
+
+static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
+{
+ u32 fsize = fls(size) - 1;
+ clrsetbits_le32(&priv->regs->dcr,
+ STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
+ fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
+}
+
+static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
+{
+ unsigned int ccr_reg = 0;
+ u8 imode, admode, dmode;
+ u32 mode = priv->mode;
+ u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
+
+ imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
+ admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
+
+ if (mode & SPI_RX_QUAD) {
+ dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
+ if (mode & SPI_TX_QUAD) {
+ imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
+ admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
+ }
+ } else if (mode & SPI_RX_DUAL) {
+ dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
+ if (mode & SPI_TX_DUAL) {
+ imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
+ admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
+ }
+ } else {
+ dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
+ }
+
+ if (priv->command & CMD_HAS_DATA)
+ ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
+
+ if (priv->command & CMD_HAS_DUMMY)
+ ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
+ << STM32_QSPI_CCR_DCYC_SHIFT);
+
+ if (priv->command & CMD_HAS_ADR) {
+ ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
+ << STM32_QSPI_CCR_ADSIZE_SHIFT);
+ ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
+ }
+ ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
+ ccr_reg |= cmd;
+ return ccr_reg;
+}
+
+static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
+ struct spi_flash *flash)
+{
+ priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
+ | CMD_HAS_DUMMY;
+ priv->dummycycles = flash->dummy_byte * 8;
+
+ unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
+ ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
+
+ _stm32_qspi_wait_for_not_busy(priv);
+
+ writel(ccr_reg, &priv->regs->ccr);
+
+ priv->dummycycles = 0;
+}
+
+static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
+{
+ setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
+}
+
+static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
+ u32 length)
+{
+ writel(length - 1, &priv->regs->dlr);
+}
+
+static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
+{
+ writel(cr_reg, &priv->regs->ccr);
+
+ if (priv->command & CMD_HAS_ADR)
+ writel(priv->address, &priv->regs->ar);
+}
+
+static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
+ struct spi_flash *flash, unsigned int bitlen,
+ const u8 *dout, u8 *din, unsigned long flags)
+{
+ unsigned int words = bitlen / 8;
+
+ if (flags & SPI_XFER_MMAP) {
+ _stm32_qspi_enable_mmap(priv, flash);
+ return 0;
+ } else if (flags & SPI_XFER_MMAP_END) {
+ _stm32_qspi_disable_mmap(priv);
+ return 0;
+ }
+
+ if (bitlen == 0)
+ return -1;
+
+ if (bitlen % 8) {
+ debug("spi_xfer: Non byte aligned SPI transfer\n");
+ return -1;
+ }
+
+ if (dout && din) {
+ debug("spi_xfer: QSPI cannot have data in and data out set\n");
+ return -1;
+ }
+
+ if (!dout && (flags & SPI_XFER_BEGIN)) {
+ debug("spi_xfer: QSPI transfer must begin with command\n");
+ return -1;
+ }
+
+ if (dout) {
+ if (flags & SPI_XFER_BEGIN) {
+ /* data is command */
+ priv->command = dout[0] | CMD_HAS_DATA;
+ if (words >= 4) {
+ /* address is here too */
+ priv->address = (dout[1] << 16) |
+ (dout[2] << 8) | dout[3];
+ priv->command |= CMD_HAS_ADR;
+ }
+
+ if (words > 4) {
+ /* rest is dummy bytes */
+ priv->dummycycles = (words - 4) * 8;
+ priv->command |= CMD_HAS_DUMMY;
+ }
+
+ if (flags & SPI_XFER_END) {
+ /* command without data */
+ priv->command &= ~(CMD_HAS_DATA);
+ }
+ }
+
+ if (flags & SPI_XFER_END) {
+ u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+ ccr_reg |= STM32_QSPI_CCR_IND_WRITE
+ << STM32_QSPI_CCR_FMODE_SHIFT;
+
+ _stm32_qspi_wait_for_not_busy(priv);
+
+ if (priv->command & CMD_HAS_DATA)
+ _stm32_qspi_set_xfer_length(priv, words);
+
+ _stm32_qspi_start_xfer(priv, ccr_reg);
+
+ debug("%s: write: ccr:0x%08x adr:0x%08x\n",
+ __func__, priv->regs->ccr, priv->regs->ar);
+
+ if (priv->command & CMD_HAS_DATA) {
+ _stm32_qspi_wait_for_ftf(priv);
+
+ debug("%s: words:%d data:", __func__, words);
+
+ int i = 0;
+ while (words > i) {
+ writeb(dout[i], &priv->regs->dr);
+ debug("%02x ", dout[i]);
+ i++;
+ }
+ debug("\n");
+
+ _stm32_qspi_wait_for_complete(priv);
+ } else {
+ _stm32_qspi_wait_for_not_busy(priv);
+ }
+ }
+ } else if (din) {
+ u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+ ccr_reg |= STM32_QSPI_CCR_IND_READ
+ << STM32_QSPI_CCR_FMODE_SHIFT;
+
+ _stm32_qspi_wait_for_not_busy(priv);
+
+ _stm32_qspi_set_xfer_length(priv, words);
+
+ _stm32_qspi_start_xfer(priv, ccr_reg);
+
+ debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
+ priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
+
+ debug("%s: data:", __func__);
+
+ int i = 0;
+ while (words > i) {
+ din[i] = readb(&priv->regs->dr);
+ debug("%02x ", din[i]);
+ i++;
+ }
+ debug("\n");
+ }
+
+ return 0;
+}
+
+static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct fdt_resource res_regs, res_mem;
+ struct stm32_qspi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+ int ret;
+
+ ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+ "QuadSPI", &res_regs);
+ if (ret) {
+ debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+ return -ENOMEM;
+ }
+ ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+ "QuadSPI-memory", &res_mem);
+ if (ret) {
+ debug("Error: can't get mmap base address(ret = %d)!\n", ret);
+ return -ENOMEM;
+ }
+
+ plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+ STM32_QSPI_DEFAULT_SCK_FREQ);
+
+ plat->base = res_regs.start;
+ plat->memory_map = res_mem.start;
+
+ debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
+ __func__,
+ plat->base,
+ plat->memory_map,
+ plat->max_hz
+ );
+
+ return 0;
+}
+
+static int stm32_qspi_probe(struct udevice *bus)
+{
+ struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
+ struct stm32_qspi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_bus *dm_spi_bus;
+
+ dm_spi_bus = bus->uclass_priv;
+
+ dm_spi_bus->max_hz = plat->max_hz;
+
+ priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
+
+ priv->max_hz = plat->max_hz;
+
+ clock_setup(QSPI_CLOCK_CFG);
+
+ setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
+
+ return 0;
+}
+
+static int stm32_qspi_remove(struct udevice *bus)
+{
+ return 0;
+}
+
+static int stm32_qspi_claim_bus(struct udevice *dev)
+{
+ struct stm32_qspi_priv *priv;
+ struct udevice *bus;
+ struct spi_flash *flash;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+ flash = dev_get_uclass_priv(dev);
+
+ _stm32_qspi_set_flash_size(priv, flash->size);
+
+ _stm32_qspi_enable(priv);
+
+ return 0;
+}
+
+static int stm32_qspi_release_bus(struct udevice *dev)
+{
+ struct stm32_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ _stm32_qspi_disable(priv);
+
+ return 0;
+}
+
+static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct stm32_qspi_priv *priv;
+ struct udevice *bus;
+ struct spi_flash *flash;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+ flash = dev_get_uclass_priv(dev);
+
+ return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
+ (u8 *)din, flags);
+}
+
+static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
+{
+ struct stm32_qspi_platdata *plat = bus->platdata;
+ struct stm32_qspi_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->max_hz)
+ speed = plat->max_hz;
+
+ u32 qspi_clk = clock_get(CLOCK_AHB);
+ u32 prescaler = 255;
+ if (speed > 0) {
+ prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
+ if (prescaler > 255)
+ prescaler = 255;
+ else if (prescaler < 0)
+ prescaler = 0;
+ }
+
+ u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
+ csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
+
+ _stm32_qspi_wait_for_not_busy(priv);
+
+ clrsetbits_le32(&priv->regs->cr,
+ STM32_QSPI_CR_PRESCALER_MASK <<
+ STM32_QSPI_CR_PRESCALER_SHIFT,
+ prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
+
+
+ clrsetbits_le32(&priv->regs->dcr,
+ STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
+ csht << STM32_QSPI_DCR_CSHT_SHIFT);
+
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
+ (qspi_clk / (prescaler + 1)));
+
+ return 0;
+}
+
+static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct stm32_qspi_priv *priv = dev_get_priv(bus);
+
+ _stm32_qspi_wait_for_not_busy(priv);
+
+ if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
+ setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
+ else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
+ clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
+ else
+ return -ENODEV;
+
+ if (mode & SPI_CS_HIGH)
+ return -ENODEV;
+
+ if (mode & SPI_RX_QUAD)
+ priv->mode |= SPI_RX_QUAD;
+ else if (mode & SPI_RX_DUAL)
+ priv->mode |= SPI_RX_DUAL;
+ else
+ priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
+
+ if (mode & SPI_TX_QUAD)
+ priv->mode |= SPI_TX_QUAD;
+ else if (mode & SPI_TX_DUAL)
+ priv->mode |= SPI_TX_DUAL;
+ else
+ priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
+
+ debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
+
+ if (mode & SPI_RX_QUAD)
+ debug("quad, tx: ");
+ else if (mode & SPI_RX_DUAL)
+ debug("dual, tx: ");
+ else
+ debug("single, tx: ");
+
+ if (mode & SPI_TX_QUAD)
+ debug("quad\n");
+ else if (mode & SPI_TX_DUAL)
+ debug("dual\n");
+ else
+ debug("single\n");
+
+ return 0;
+}
+
+static const struct dm_spi_ops stm32_qspi_ops = {
+ .claim_bus = stm32_qspi_claim_bus,
+ .release_bus = stm32_qspi_release_bus,
+ .xfer = stm32_qspi_xfer,
+ .set_speed = stm32_qspi_set_speed,
+ .set_mode = stm32_qspi_set_mode,
+};
+
+static const struct udevice_id stm32_qspi_ids[] = {
+ { .compatible = "st,stm32-qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(stm32_qspi) = {
+ .name = "stm32_qspi",
+ .id = UCLASS_SPI,
+ .of_match = stm32_qspi_ids,
+ .ops = &stm32_qspi_ops,
+ .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
+ .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
+ .probe = stm32_qspi_probe,
+ .remove = stm32_qspi_remove,
+};
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
+obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+
+/* Number of Watchdog Timer ticks before reset */
+#define AST_WDT_RESET_TIMEOUT 10
+#define AST_WDT_FOR_RESET 0
+
+static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct ast_wdt *wdt = ast_get_wdt(AST_WDT_FOR_RESET);
+ u32 reset_mode = 0;
+
+ if (IS_ERR(wdt))
+ return PTR_ERR(wdt);
+
+ switch (type) {
+ case SYSRESET_WARM:
+ reset_mode = WDT_CTRL_RESET_CPU;
+ break;
+ case SYSRESET_COLD:
+ reset_mode = WDT_CTRL_RESET_CHIP;
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ /* Clear reset mode bits */
+ clrsetbits_le32(&wdt->ctrl,
+ (WDT_CTRL_RESET_MODE_MASK << WDT_CTRL_RESET_MODE_SHIFT),
+ (reset_mode << WDT_CTRL_RESET_MODE_SHIFT));
+ wdt_start(wdt, AST_WDT_RESET_TIMEOUT);
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops ast_sysreset = {
+ .request = ast_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_ast) = {
+ .name = "ast_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &ast_sysreset,
+};
help
Select this to enable an timer for Omap devices.
+config AST_TIMER
+ bool "Aspeed ast2400/ast2500 timer support"
+ depends on TIMER
+ default y if ARCH_ASPEED
+ help
+ Select this to enable timer for Aspeed ast2400/ast2500 devices.
+ This is a simple sys timer driver, it is compatible with lib/time.c,
+ but does not support any interrupts. Even though SoC has 8 hardware
+ counters, they are all treated as a single device by this driver.
+ This is mostly because they all share several registers which
+ makes it difficult to completely separate them.
+
endmenu
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
+obj-$(CONFIG_AST_TIMER) += ast_timer.o
--- /dev/null
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AST_TICK_TIMER 1
+#define AST_TMC_RELOAD_VAL 0xffffffff
+
+struct ast_timer_priv {
+ struct ast_timer *regs;
+ struct ast_timer_counter *tmc;
+};
+
+static struct ast_timer_counter *ast_get_timer_counter(struct ast_timer *timer,
+ int n)
+{
+ if (n > 3)
+ return &timer->timers2[n - 4];
+ else
+ return &timer->timers1[n - 1];
+}
+
+static int ast_timer_probe(struct udevice *dev)
+{
+ struct ast_timer_priv *priv = dev_get_priv(dev);
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ writel(AST_TMC_RELOAD_VAL, &priv->tmc->reload_val);
+
+ /*
+ * Stop the timer. This will also load reload_val into
+ * the status register.
+ */
+ clrbits_le32(&priv->regs->ctrl1,
+ AST_TMC_EN << AST_TMC_CTRL1_SHIFT(AST_TICK_TIMER));
+ /* Start the timer from the fixed 1MHz clock. */
+ setbits_le32(&priv->regs->ctrl1,
+ (AST_TMC_EN | AST_TMC_1MHZ) <<
+ AST_TMC_CTRL1_SHIFT(AST_TICK_TIMER));
+
+ uc_priv->clock_rate = AST_TMC_RATE;
+
+ return 0;
+}
+
+static int ast_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct ast_timer_priv *priv = dev_get_priv(dev);
+
+ *count = AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
+
+ return 0;
+}
+
+static int ast_timer_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_timer_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ priv->tmc = ast_get_timer_counter(priv->regs, AST_TICK_TIMER);
+
+ return 0;
+}
+
+static const struct timer_ops ast_timer_ops = {
+ .get_count = ast_timer_get_count,
+};
+
+static const struct udevice_id ast_timer_ids[] = {
+ { .compatible = "aspeed,ast2500-timer" },
+ { .compatible = "aspeed,ast2400-timer" },
+ { }
+};
+
+U_BOOT_DRIVER(ast_timer) = {
+ .name = "ast_timer",
+ .id = UCLASS_TIMER,
+ .of_match = ast_timer_ids,
+ .probe = ast_timer_probe,
+ .priv_auto_alloc_size = sizeof(struct ast_timer_priv),
+ .ofdata_to_platdata = ast_timer_ofdata_to_platdata,
+ .ops = &ast_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
to the device using the standard TPM Interface Specification (TIS)
protocol
+config TPM_FLUSH_RESOURCES
+ bool "Enable TPM resource flushing support"
+ depends on TPM
+ help
+ Enable support to flush specific resources (e.g. keys) from the TPM.
+ The functionality is available via the 'tpm' command as well.
endmenu
info.name[0] = 0;
info.type[0] = 0;
info.bootable = 0;
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
info.uuid[0] = 0;
#endif
}
static __u32 get_fatent(fsdata *mydata, __u32 entry)
{
__u32 bufnum;
- __u32 off16, offset;
+ __u32 offset, off8;
__u32 ret = 0x00;
if (CHECK_CLUST(entry, mydata->fatsize)) {
ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]);
break;
case 12:
- off16 = (offset * 3) / 2;
- ret = FAT2CPU16(*(__u16 *)(mydata->fatbuf + off16));
+ off8 = (offset * 3) / 2;
+ /* fatbut + off8 may be unaligned, read in byte granularity */
+ ret = mydata->fatbuf[off8] + (mydata->fatbuf[off8 + 1] << 8);
if (offset & 0x1)
ret >>= 4;
#define CONFIG_GZIP 1
#define CONFIG_ZLIB 1
-#define CONFIG_PARTITIONS 1
#endif
* message that includes some other pre-processor symbols in the text.
*/
-/* We need the part command */
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \
"if " #devtypel " dev ${devnum}; then " \
"setenv devtype " #devtypel "; " \
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define HAVE_BLOCK_DEVICE
#endif
-#if (defined(CONFIG_PARTITION_UUIDS) || \
- defined(CONFIG_EFI_PARTITION) || \
+#if (CONFIG_IS_ENABLED(PARTITION_UUIDS) || \
+ CONFIG_IS_ENABLED(EFI_PARTITION) || \
defined(CONFIG_RANDOM_UUID) || \
defined(CONFIG_CMD_UUID) || \
defined(CONFIG_BOOTP_PXE)) && \
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
#ifdef CONFIG_FMAN_ENET
*/
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_ENV_OVERWRITE
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_TSEC_ENET
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_SUPPORT_VFAT
#undef CONFIG_WATCHDOG /* watchdog disabled */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif
#ifdef CONFIG_CMD_IDE
/* ATA */
-# define CONFIG_DOS_PARTITION
-# define CONFIG_MAC_PARTITION
# define CONFIG_IDE_RESET 1
# define CONFIG_IDE_PREINIT 1
# define CONFIG_ATAPI
#define CONFIG_CMD_IDE
/* ATA */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT 1
#define CONFIG_ATAPI
#endif
/* ATA configuration */
-#define CONFIG_ISO_PARTITION
-#define CONFIG_DOS_PARTITION
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT 1
#define CONFIG_ATAPI
# define CONFIG_CMD_PCI
# endif
# define CONFIG_PCI_OHCI
-# define CONFIG_DOS_PARTITION
# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
# undef CONFIG_SYS_USB_OHCI_CPU_INIT
#endif
#ifdef CONFIG_CMD_USB
-# define CONFIG_DOS_PARTITION
# define CONFIG_USB_OHCI_NEW
# ifndef CONFIG_CMD_PCI
# define CONFIG_CMD_PCI
/************************************************************
* DISK Partition support
************************************************************/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
/************************************************************
* Video support
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
-
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/*
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
|| defined(CONFIG_USB_STORAGE)
- #define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/*
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/*
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#if defined(CONFIG_TSEC_ENET)
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
#endif
/*
#endif
#endif
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_DOS_PARTITION
-#endif
-
/*
* Miscellaneous configurable options
*/
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/*
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
-#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_TSEC_ENET
#endif /* #ifdef CONFIG_FSL_SATA */
#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
|| defined(CONFIG_FSL_SATA)
-#define CONFIG_DOS_PARTITION
#endif
/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_DOS_PARTITION
-#endif
-
#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET
#ifdef CONFIG_USB_EHCI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
-#define CONFIG_DOS_PARTITION
#endif
#endif
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Hash command with SHA acceleration supported in hardware */
/************************************************************
* DISK Partition support
************************************************************/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
/************************************************************
* Video support
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_SUPPORT_VFAT
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define USB_2_0_DEVICE
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/*
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Qman/Bman */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/*
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Qman/Bman */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
#endif
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Qman/Bman */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif
/* Qman/Bman */
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
#endif
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif
/* Qman/Bman */
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_ESDHC_DETECT_QUIRK \
(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif /* #ifndef CONFIG_TQM5200S */
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/* USB */
#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
#define CONFIG_TIMESTAMP /* but print image timestmps */
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
#define CONFIG_TIMESTAMP /* but print image timestmps */
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/*
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_MMC_SPI
#define CONFIG_CMD_MMC_SPI
-#define CONFIG_GENERIC_MMC
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
-#define CONFIG_DOS_PARTITION
#endif
/* Misc Extra Settings */
#undef CONFIG_EEPRO100
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
-#endif /* defined(CONFIG_CMD_IDE) */
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_USB_OHCI
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
/*
* SD (MMC) controller
*/
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_FTSDC010
#define CONFIG_FTSDC010_NUMBER 1
#define CONFIG_FTSDC010_SDIO
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_DOS_PARTITION
/* USB Configs */
#define CONFIG_USB_EHCI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* MMCIF */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xee200000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
-#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-
#ifdef CONFIG_NAND
#define NANDARGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
-#undef CONFIG_PARTITION_UUIDS
-#undef CONFIG_EFI_PARTITION
#endif
/* USB Device Firmware Update support */
#include <configs/ti_am335x_common.h>
/* Mach type */
-#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
/* Clock defines */
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-#define MACH_TYPE_BOSCH_SHC_B 9001
-#define MACH_TYPE_BOSCH_SHC_B2 9002
-#define MACH_TYPE_BOSCH_SHC_C 9003
-#define MACH_TYPE_BOSCH_SHC_C2 9004
-#define MACH_TYPE_BOSCH_SHC_C3 9005
-#define MACH_TYPE_BOSCH_SHC 9006
-#ifdef CONFIG_B_SAMPLE
-# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_B
-#elif defined CONFIG_B2_SAMPLE
-# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_B2
-#elif defined CONFIG_C_SAMPLE
-# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_C
-#elif defined CONFIG_C2_SAMPLE
-# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_C2
-#elif defined CONFIG_C3_SAMPLE
-# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_C3
-#elif defined CONFIG_SERIES
-# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC
-#endif /* #ifdef CONFIG_B_SAMPLE */
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_ENV_OFFSET_REDUND 0x9000 /* 36 kB */
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_ISO_PARTITION
-#endif
#ifndef CONFIG_SHC_ICT
/*
* In builds other than ICT, reset to retry after timeout
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#ifndef CONFIG_SPL_BUILD
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* disable EFI partitions and partition UUID support */
-#undef CONFIG_PARTITION_UUIDS
-#undef CONFIG_EFI_PARTITION
#endif
#if defined(CONFIG_EMMC_BOOT)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_DOS_PARTITION 1
/*
* USB configuration
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/*
* USB configuration
* Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
/* commands to include */
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PART
#define CONFIG_CMD_MTDPARTS
/* I2C */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
-#define CONFIG_PARTITION_UUIDS
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_QSPI_QUAD_SUPPORT
#define CONFIG_TI_EDMA3
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
#include <configs/ti_omap5_common.h>
/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
#define CONFIG_RANDOM_UUID
#define CONFIG_HSMMC2_8BIT
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_IDE
-#define CONFIG_DOS_PARTITION
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTARGS "console=ttySC2,38400"
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
-#define CONFIG_DOS_PARTITION
#ifdef CONFIG_MX6Q
#define CONFIG_CMD_SATA
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC support */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
/*
* SD/MMC
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
#endif
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
-#define MACH_TYPE_APX4DEVKIT 3712
#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
-#endif /* defined(CONFIG_CMD_IDE) */
-
/*
* Dynamic MTD partition support
*/
--- /dev/null
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ * Copyright 2016 IBM Corporation
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AST_COMMON_CONFIG_H
+#define __AST_COMMON_CONFIG_H
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Enable cache controller */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#ifdef CONFIG_PRE_CON_BUF_SZ
+#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + CONFIG_PRE_CON_BUF_SZ)
+#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - CONFIG_PRE_CON_BUF_SZ)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000)
+#define CONFIG_SYS_INIT_RAM_SIZE (36*1024)
+#endif
+
+#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
+ + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_BOOTARGS \
+ "console=ttyS4,115200n8" \
+ " root=/dev/ram rw"
+
+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=yes\0" \
+ "spi_dma=yes\0" \
+ ""
+
+#endif /* __AST_COMMON_CONFIG_H */
#define CONFIG_USB_ATMEL 1
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
-/* FAT */
-#ifdef CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#ifdef CONFIG_AT91SAM9G10EK
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
-/* FAT */
-#ifdef CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet */
#define CONFIG_KS8851_MLL
#define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_DOS_PARTITION
#endif
/* Ethernet - not present */
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
-/* FAT */
-#ifdef CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_USART_BASE ATMEL_BASE_USART1
#define CONFIG_USART_ID 1
/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_USART_ID 1
/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_USART_ID 1
/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64
-/*
- * SD/MMC configuration
- */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/*
* Ethernet PHY configuration
*/
#include <linux/sizes.h>
#include <configs/ti_am335x_common.h>
-#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
-#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
/* FIT support */
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
-#undef CONFIG_PARTITION_UUIDS
-#undef CONFIG_EFI_PARTITION
/*
* Disable CPSW SPL support so we fit within the 101KiB limit.
*/
#define CONFIG_SUPPORT_VFAT
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*-----------------------------------------------------------------------
* PCI stuff
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
-#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-
#ifdef CONFIG_NAND
#define NANDARGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
-#undef CONFIG_PARTITION_UUIDS
-#undef CONFIG_EFI_PARTITION
#endif
/* USB Device Firmware Update support */
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_GENERIC_MMC
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x006ff000
#define CONFIG_KONA_GPIO
/* MMC/SD Driver */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
* This is necessary for the fatls command to work on an SD card
* for example.
*/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
/* version string, parser, etc */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_KONA_GPIO
/* MMC/SD Driver */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
* This is necessary for the fatls command to work on an SD card
* for example.
*/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
/* version string, parser, etc */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * One partition type must be defined for part.c
- * This is necessary for the fatls command to work on an SD card
- * for example.
- */
-#define CONFIG_DOS_PARTITION
-
/* version string, parser, etc */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
* SDH Settings
*/
#if !defined(__ADSPBF512__)
-#define CONFIG_GENERIC_MMC
#define CONFIG_BFIN_SDH
#endif
/*
* SPI_MMC Settings
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
/* #define CONFIG_STAMP_CF */
#if defined(CONFIG_STAMP_CF)
#define CONFIG_MISC_INIT_R
-#define CONFIG_DOS_PARTITION 1
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
* SPI_MMC Settings
*/
#define CONFIG_MMC_SPI
-#ifdef CONFIG_MMC_SPI
-#define CONFIG_GENERIC_MMC
-#endif
/*
* NAND Settings
#if defined(CONFIG_BFIN_IDE)
-#define CONFIG_DOS_PARTITION 1
/*
* IDE/ATA stuff
*/
* SDH Settings
*/
#if !defined(__ADSPBF544__)
-#define CONFIG_GENERIC_MMC
#define CONFIG_BFIN_SDH
#endif
/*
* SDH Settings
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_BFIN_SDH
/*
# endif
# ifdef CONFIG_LIBATA
# define CONFIG_CMD_SATA
-# define CONFIG_DOS_PARTITION
# endif
# ifdef CONFIG_MMC
-# define CONFIG_DOS_PARTITION
# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
# endif
# ifdef CONFIG_MMC_SPI
# endif
# ifdef CONFIG_USB
# define CONFIG_CMD_USB_STORAGE
-# define CONFIG_DOS_PARTITION
# endif
# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
# define CONFIG_CMD_NAND
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
/* USB */
#undef CONFIG_CMD_USB
-#define CONFIG_GENERIC_MMC
-
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MMC/SD IP block */
#if defined(CONFIG_EMMC_BOOT)
- #define CONFIG_GENERIC_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
#endif /* CONFIG_EMMC_BOOT */
* enabled a number of useful commands and support.
*/
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
/* GPIO */
/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
/* Always 64 KiB env size */
* enabled a number of useful commands and support.
*/
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#endif /* CONFIG_MMC, ... */
* Board
*/
#define CONFIG_DRIVER_TI_EMAC
-#define MACH_TYPE_CALIMAIN 3528
#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
/*
#endif
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*-----------------------------------------------------------------------
* PCI stuff
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
+
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
--- /dev/null
+/*
+ * Copyright (C) 2017 Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_CHILIBOARD_H
+#define __CONFIG_CHILIBOARD_H
+
+#define CONFIG_NAND
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_CONS_INDEX 1
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} ${optargs} " \
+ "${mtdparts} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdt_addr} NAND.u-boot-spl-os; " \
+ "nand read ${loadaddr} NAND.kernel; " \
+ "bootz ${loadaddr} - ${fdt_addr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run mmcboot; " \
+ "run nandboot; " \
+ "run netboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "fdt_addr=0x87800000\0" \
+ "boot_fdt=try\0" \
+ "console=ttyO0,115200n8\0" \
+ "image=zImage\0" \
+ "fdt_file=am335x-chiliboard.dtb\0" \
+ "ip_dyn=yes\0" \
+ "optargs=\0" \
+ "loadbootscript=" \
+ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${boot_dir}/${image}\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
+ "${boot_dir}/${fdt_file}\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
+ "${mtdparts} " \
+ "root=${mmcroot}\0" \
+ "mmcloados=run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadimage; then " \
+ "run mmcloados;" \
+ "fi;" \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
+ "${mtdparts} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ NANDARGS
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* SPL */
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
+
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_GPMC_PREFETCH
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define MTDIDS_DEFAULT "nand0=8000000.nand"
+#define MTDPARTS_DEFAULT "mtdparts=8000000.nand:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.file-system)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#undef CONFIG_DM_USB
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#else
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET SZ_128K
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* Network. */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#endif /* ! __CONFIG_CHILIBOARD_H */
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
-/* GPT */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
/*
* SDIO/MMC Card Configuration
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
/* Partition support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT
/*
* SPI_MMC Settings
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
/*
* SPI_MMC Settings
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/* Partitions (for USB) */
-#define CONFIG_MAC_PARTITION 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_ISO_PARTITION 1
/*
* Invoke our last_stage_init function - needed by fwupdate
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
-#define MACH_TYPE_CM_T335 4586 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
/* Clock Defines */
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* USB */
#define CONFIG_USB_OMAP3
#define CONFIG_USB_EHCI
#define CONFIG_OMAP_GPIO
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* USB */
#define CONFIG_USB_MUSB_AM35X
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x81200000\0" \
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
-#define CONFIG_DOS_PARTITION
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_TEGRA_UARTA_SDIO1
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2
+
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC support */
-#define CONFIG_GENERIC_MMC
-
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC support */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_GENERIC_MMC
-
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
/*
* MMC
*/
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_HW_WATCHDOG
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
-#define CONFIG_DOS_PARTITION
/*
* For booting Linux, the board info and command line data
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Hash command with SHA acceleration supported in hardware */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-#define CONFIG_DOS_PARTITION
/* USB DFU support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-#define CONFIG_GENERIC_MMC
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/*
#undef CONFIG_CMD_ENV
#endif
-/* SD/MMC configuration */
-#ifndef CONFIG_USE_NOR
-#define CONFIG_GENERIC_MMC
-#endif
-
-/*
- * Enable MMC commands only when
- * MMC support is present
- */
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#endif
-
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
-#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
-
/* SPI */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* Partition support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT
/*
* SDIO/MMC Card Configuration
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
/*
CONFIG_SYS_SCSI_MAX_LUN)
/* Partition support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT
#define CONFIG_SATA_MV
#define CONFIG_LIBATA
#define CONFIG_LBA48
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT
#define CONFIG_PCMCIA_SLOT_A
#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1
#include <linux/sizes.h>
#include <asm/arch/cpu.h>
-/*
- * Define DevKit3250 machine type by hand until it lands in mach-types
- */
-#define MACH_TYPE_DEVKIT3250 3697
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_DOS_PARTITION
/*
* Pass open firmware flat tree
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_GENERIC_MMC
-
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
-/*
- * Partitions
- */
-#define CONFIG_DOS_PARTITION
#define CONFIG_BZIP2
/*
/*
* Machine number definition
*/
-#define MACH_TYPE_DNS325 3800
#define CONFIG_MACH_TYPE MACH_TYPE_DNS325
/*
#include <configs/ti_omap5_common.h>
/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
#define CONFIG_RANDOM_UUID
#define CONFIG_HSMMC2_8BIT
#define __CONFIG_DRACO_H
#define CONFIG_SIEMENS_DRACO
-#define MACH_TYPE_DRACO 4314
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO
#include "siemens-am33x-common.h"
"led0=103,1,0\0" \
"led1=64,0,1\0"
-#undef CONFIG_DOS_PARTITION
-
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 19000000
-/* This are needed to have proper mmc support */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard410c/u-boot.lds"
/* Fixup - in init code we switch from device to host mode,
/* Extra Commands */
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_GPT
#define CONFIG_CMD_MD5SUM
/* Enable that for switching of boot partitions */
/* Disabled by default as some sub-commands can brick eMMC */
/*#define CONFIG_SUPPORT_EMMC_BOOT */
-#define CONFIG_CMD_PART
#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_TFTP
#define CONFIG_CMD_UNZIP
/* Partition table support */
#define HAVE_BLOCK_DEVICE /* Needed for partition commands */
-#define CONFIG_PARTITION_UUIDS
#include <config_distro_defaults.h>
#ifndef _CONFIG_DREAMPLUG_H
#define _CONFIG_DREAMPLUG_H
-/*
- * FIXME: This belongs in mach-types.h. However, we only pull mach-types
- * from Linus' kernel.org tree. This hasn't been updated primarily due to
- * the recent arch/arm reshuffling. So, in the meantime, we'll place it
- * here.
- */
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_DREAMPLUG
-#error "MACH_TYPE_DREAMPLUG has been defined properly, please remove this."
-#else
-#define MACH_TYPE_DREAMPLUG 3550
-#endif
-
/*
* High Level Configuration Options (easy to change)
*/
#ifndef _CONFIG_DS109_H
#define _CONFIG_DS109_H
-/*
- * FIXME: This belongs in mach-types.h. However, we only pull mach-types
- * from Linus' kernel.org tree. This hasn't been updated primarily due to
- * the recent arch/arm reshuffling. So, in the meantime, we'll place it
- * here.
- */
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_SYNOLOGY
-#error "MACH_TYPE_SYNOLOGY has been defined properly, please remove this."
-#else
-#define MACH_TYPE_SYNOLOGY 527
-#endif
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE 527
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_MACH_TYPE MACH_TYPE_SYNOLOGY
/*
* Commands configuration
#endif
/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_SYS_MVFS
* High Level Configuration Options
*/
#define CONFIG_DUOVERO
-#define MACH_TYPE_OMAP4_DUOVERO 4097 /* Until the next sync */
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP4_DUOVERO
+#define CONFIG_MACH_TYPE MACH_TYPE_DUOVERO
#include <configs/ti_omap4_common.h>
-#undef CONFIG_EFI_PARTITION
-
#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3
-#define MACH_TYPE_ECO5_PK 4017
#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
-#define CONFIG_DOS_PARTITION
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
#define CONFIG_MVSATA_IDE
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MARVELL
#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
"led4=60,0,1\0" \
"led5=63,0,1\0"
-#undef CONFIG_DOS_PARTITION
#undef CONFIG_CMD_FAT
/* Physical Memory Map */
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Set our official architecture number. */
-#define MACH_TYPE_ETHERNUT5 1971
#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
/* CPU information */
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
#endif
#define MTDIDS_DEFAULT "nand0=atmel_nand"
#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
#endif
-#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
- defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
#define CONFIG_LZO
#define CONFIG_RBTREE
--- /dev/null
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ * Copyright 2016 Google Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/aspeed-common.h>
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
+
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+
+/* Memory Info */
+#define CONFIG_SYS_LOAD_ADDR 0x83000000
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_SIZE 0x20000
+
+#endif /* __CONFIG_H */
#define CONFIG_BAUDRATE 115200
/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
/* PWM */
/* Command definition*/
#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_GPT
/* TIZEN THOR downloader support */
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
-/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
-#define MACH_TYPE_SMDK5250 3774
#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
#define CONFIG_EXYNOS5_DT
-#define MACH_TYPE_SMDK5420 8002
-#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE 8002
#define CONFIG_VAR_SIZE_SPL
#define CONFIG_SYS_DCACHE_OFF
-/* Only in case the value is not present in mach-types.h */
-#ifndef MACH_TYPE_FLEA3
-#define MACH_TYPE_FLEA3 3668
-#endif
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* Set TEXT at the beginning of the NOR flash */
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
-/* SD/MMC support */
-#define CONFIG_GENERIC_MMC
-
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_DOS_PARTITION
/* USB Configs */
#ifdef CONFIG_USB
#define CONFIG_SMSTP7_ENA 0x00200000
/* SDHI */
-#define CONFIG_GENERIC_MMC
#define CONFIG_SH_SDHI_FREQ 97500000
#endif /* __GOSE_H */
#ifndef __CONFIG_GPLUGD_H
#define __CONFIG_GPLUGD_H
-/*
- * FIXME: fix for error caused due to recent update to mach-types.h
- */
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_SHEEVAD
-#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this."
-#else
-#define MACH_TYPE_SHEEVAD 2625
-#endif
-
/*
* High Level Configuration Options
*/
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
#define CONFIG_ARMADA100 1 /* SOC Family Name */
#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_TYPE MACH_TYPE_SHEEVAD /* Machine type */
+#define CONFIG_MACH_TYPE MACH_TYPE_GPLUGD /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_TEXT_BASE 0x00f00000
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* __CONFIG_GPLUGD_H */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Supported commands
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Supported commands
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Supported commands
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Supported commands
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Supported commands
#ifndef __CONFIG_H
#define __CONFIG_H
-#define MACH_TYPE_H2200 341
#define CONFIG_MACH_TYPE MACH_TYPE_H2200
#define CONFIG_CPU_PXA25X 1
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_HIKEY_GPIO
/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FS_EXT4
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_CMD_FPGAD
#define CONFIG_CMD_IOLOOP
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
-#define CONFIG_DOS_PARTITION
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYSTEMACE /* Enable SystemACE support */
#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
-#define CONFIG_DOS_PARTITION
/*
* External Bus Controller (EBC) Setup
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
+
/*
* Compression configuration
*/
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
-/*
- * SD/MMC
- */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/*
* GPIO
*/
#define CONFIG_SYS_XLB_PIPELINING 1
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* BOOTP options
#define CONFIG_CMD_SDRAM
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* PCI stuff
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PHY_MICREL
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
-/* MMC/SD */
-#define CONFIG_GENERIC_MMC
-
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
-#define CONFIG_DOS_PARTITION 1
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
#define CONFIG_SYS_NO_FLASH
-/*
- * MMC
- */
-
-#define CONFIG_GENERIC_MMC
-
/*
* Power
*/
#define CONFIG_TWL6030_INPUT
-/*
- * Partitions
- */
-
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
/*
* SPL
*/
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
-
-/* We got removed from Linux mach-types.h */
-#define MACH_TYPE_KM_KIRKWOOD 2255
-
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
#define CONFIG_SMSTP7_ENA 0x00200000
/* SD */
-#define CONFIG_GENERIC_MMC
#define CONFIG_SH_SDHI_FREQ 97500000
#endif /* __KOELSCH_H */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_DOS_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
#elif defined(CONFIG_NETSPACE_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
#elif defined(CONFIG_NETSPACE_LITE_V2)
-#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
#elif defined(CONFIG_NETSPACE_MINI_V2)
-#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
#elif defined(CONFIG_NETSPACE_MAX_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
/*
* Partition support
*/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
/*
* File systems support
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* MMC */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xEE220000
#define CONFIG_SH_MMCIF_CLK 97500000
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-
-/*
- * Enable MMC commands only when
- * MMC support is present
- */
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#endif
-
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
-#define CONFIG_DOS_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
-
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* SATA */
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_SCSI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
#define CONFIG_PCIE1 /* PCIE controller 1 */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* SATA */
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_SCSI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
#define CONFIG_PCIE1 /* PCIE controller 1 */
*/
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
/* SATA */
#define CONFIG_CMD_SCSI
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
* MMC
*/
#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
* MMC
*/
#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* DSPI */
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* EEPROM */
#define CONFIG_ID_EEPROM
#ifndef CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT2
#endif
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 2
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
#define SCSI_DEV_ID 0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043ARDB_H__ */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
#define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \
"$kernel_start $kernel_size;" \
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Debug Server firmware */
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
/* Initial environment variables */
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_MISC_INIT_R
#define CONFIG_CMD_ENV
#define CONFIG_CMD_IDE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* BOOTP options
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
-#define MACH_TYPE_M28EVK 3613
#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_BMP
/*
* U-Boot Commands
*/
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_BMP
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/*
* U-Boot Commands
*/
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
/*
* SD/MMC
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
#define CONFIG_BOARD_EARLY_INIT_R
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
/*
* Command line configuration.
*/
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
+#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+
+/*
+ * Below defines are set but NOT really used since we by
+ * design force U-Boot run when we boot in development
+ * mode from SD card (SD2)
+ */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 2
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#undef CONFIG_SYS_NO_FLASH
+/* NOR 16-bit mode */
+#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_VERIFY
+
+/* NOR Flash MTD */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
+
+/* MTD support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT "nor0=8000000.nor"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=8000000.nor:" \
+ "32m@0x0(mccmon6-image.nor)," \
+ "256k@0x40000(u-boot-env.nor)," \
+ "1m@0x80000(u-boot.nor)," \
+ "8m@0x180000(kernel.nor)," \
+ "8m@0x980000(swupdate-kernel.nor)," \
+ "8m@0x1180000(swupdate-rootfs.nor)," \
+ "128k@0x1980000(kernel-dtb.nor)," \
+ "128k@0x19C0000(swupdate-kernel-dtb.nor)"
+
+/* USB Configs */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc0,115200\0" \
+ "fdtfile=imx6q-mccmon6.dtb\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "boot_os=yes\0" \
+ "download_kernel=" \
+ "tftpboot ${kernel_addr} ${kernel_file};" \
+ "tftpboot ${fdt_addr} ${fdtfile};\0" \
+ "get_boot_medium=" \
+ "setenv boot_medium nor;" \
+ "setexpr.l _src_sbmr1 *0x020d8004;" \
+ "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \
+ "if test ${_b_medium} = 40; then " \
+ "setenv boot_medium sdcard;" \
+ "fi\0" \
+ "kernel_file=uImage\0" \
+ "load_kernel=" \
+ "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
+ "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
+ "boot_sd=" \
+ "echo '#######################';" \
+ "echo '# Factory SDcard Boot #';" \
+ "echo '#######################';" \
+ "setenv mmcdev 1;" \
+ "setenv mmcfactorydev 0;" \
+ "setenv mmcfactorypart 1;" \
+ "run factory_flash_img;\0" \
+ "boot_nor=" \
+ "setenv kernelnor 0x08180000;" \
+ "setenv dtbnor 0x09980000;" \
+ "setenv bootargs console=${console} quiet " \
+ ""MTDPARTS_DEFAULT" " \
+ "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
+ "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
+ "bootm ${kernelnor} - ${dtbloadaddr};\0" \
+ "boot_recovery=" \
+ "echo '#######################';" \
+ "echo '# RECOVERY SWU Boot #';" \
+ "echo '#######################';" \
+ "setenv rootfsloadaddr 0x13000000;" \
+ "setenv swukernelnor 0x08980000;" \
+ "setenv swurootfsnor 0x09180000;" \
+ "setenv swudtbnor 0x099A0000;" \
+ "setenv bootargs console=${console} " \
+ ""MTDPARTS_DEFAULT" " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}::off root=/dev/ram rw;" \
+ "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
+ "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
+ "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
+ "boot_tftp=" \
+ "echo '#######################';" \
+ "echo '# TFTP Boot #';" \
+ "echo '#######################';" \
+ "if run download_kernel; then " \
+ "setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rootwait;" \
+ "bootm ${kernel_addr} - ${fdt_addr};" \
+ "fi\0" \
+ "bootcmd=" \
+ "if test -n ${recovery_status}; then " \
+ "run boot_recovery;" \
+ "else " \
+ "if test ! -n ${boot_medium}; then " \
+ "run get_boot_medium;" \
+ "if test ${boot_medium} = sdcard; then " \
+ "run boot_sd;" \
+ "else " \
+ "run boot_nor;" \
+ "fi;" \
+ "else " \
+ "if test ${boot_medium} = tftp; then " \
+ "run boot_tftp;" \
+ "fi;" \
+ "fi;" \
+ "fi\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "fdt_addr=0x18000000\0" \
+ "bootdev=1\0" \
+ "bootpart=1\0" \
+ "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "netdev=eth0\0" \
+ "load_addr=0x11000000\0" \
+ "dtbloadaddr=0x12000000\0" \
+ "uboot_file=u-boot.img\0" \
+ "SPL_file=SPL\0" \
+ "load_uboot=tftp ${load_addr} ${uboot_file}\0" \
+ "nor_img_addr=0x11000000\0" \
+ "nor_img_file=core-image-lwn-mccmon6.nor\0" \
+ "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
+ "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
+ "nor_img_size=0x02000000\0" \
+ "factory_script_file=factory.scr\0" \
+ "factory_load_script=" \
+ "if test -e mmc ${mmcdev}:${mmcfactorypart} " \
+ "${factory_script_file}; then " \
+ "load mmc ${mmcdev}:${mmcfactorypart} " \
+ "${loadaddr} ${factory_script_file};" \
+ "fi\0" \
+ "factory_script=echo Running factory script from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "factory_flash_img="\
+ "echo 'Flash mccmon6 with factory images'; " \
+ "if run factory_load_script; then " \
+ "run factory_script;" \
+ "else " \
+ "echo No factory script: ${factory_script_file} found on " \
+ "device ${mmcdev};" \
+ "run factory_nor_img;" \
+ "run factory_eMMC_img;" \
+ "fi\0" \
+ "factory_eMMC_img="\
+ "echo 'Update mccmon6 eMMC image'; " \
+ "if load mmc ${mmcdev}:${mmcfactorypart} " \
+ "${loadaddr} ${emmc_img_file}; then " \
+ "setexpr fw_sz ${filesize} / 0x200;" \
+ "setexpr fw_sz ${fw_sz} + 1;" \
+ "mmc dev ${mmcfactorydev};" \
+ "mmc write ${loadaddr} 0x0 ${fw_sz};" \
+ "fi\0" \
+ "factory_nor_img="\
+ "echo 'Update mccmon6 NOR image'; " \
+ "if load mmc ${mmcdev}:${mmcfactorypart} " \
+ "${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "nor_update=" \
+ "protect off ${nor_bank_start} +${nor_img_size};" \
+ "erase ${nor_bank_start} +${nor_img_size};" \
+ "setexpr nor_img_size ${nor_img_size} / 4; " \
+ "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
+ "tftp_nor_uboot="\
+ "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
+ "setenv nor_img_file u-boot.img; " \
+ "setenv nor_img_size 0x80000; " \
+ "setenv nor_bank_start 0x08080000; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "tftp_nor_uImg="\
+ "echo 'Update mccmon6 NOR uImage via TFTP'; " \
+ "setenv nor_img_file uImage; " \
+ "setenv nor_img_size 0x500000; " \
+ "setenv nor_bank_start 0x08180000; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "tftp_nor_img="\
+ "echo 'Update mccmon6 NOR image via TFTP'; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "tftp_nor_SPL="\
+ "if tftp ${load_addr} SPL_padded; then " \
+ "erase 0x08000000 +0x20000;" \
+ "cp.b ${load_addr} 0x08000000 0x20000;" \
+ "fi;\0" \
+ "tftp_sd_SPL="\
+ "if mmc dev 1; then " \
+ "if tftp ${load_addr} ${SPL_file}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${load_addr} 0x2 ${fw_sz};" \
+ "fi;" \
+ "fi;\0" \
+ "tftp_sd_uboot="\
+ "if mmc dev 1; then " \
+ "if run load_uboot; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${load_addr} 0x8A ${fw_sz};" \
+ "fi;" \
+ "fi;\0"
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE (SZ_128K)
+
+/* Envs are stored in NOR flash */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (SZ_128K)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* __CONFIG_H * */
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
-#define MACH_TYPE_MCX 3656
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
/* EHCI */
#define CONFIG_OMAP3_GPIO_2
#undef CONFIG_CMD_FUSE
#undef CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_DOS_PARTITION
/*
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
*/
#define CONFIG_SYS_TEXT_BASE 0x21F00000
-/*
- * since a number of boards are not being listed in linux
- * arch/arm/tools/mach-types any more, the mach-types have to be
- * defined here
- */
-#define MACH_TYPE_MEESC 2165
-#define MACH_TYPE_ETHERCAN2 2407
-
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_GENERIC_MMC
-
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060
#define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET
#define CONFIG_SYS_ATA_STRIDE 4
-#define CONFIG_DOS_PARTITION
/*
* I2C configuration
"mpc5121.nand:-(data)"
#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
-
#define CONFIG_SUPPORT_VFAT
#endif /* defined(CONFIG_CMD_IDE) */
#define CONFIG_SYS_PIO_MODE 1
#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
6 * 1024 * 1024)
-#define MACH_TYPE_AM3517_MT_VENTOUX 3832
#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX
#define CONFIG_BOOTFILE "uImage"
*/
#if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM)
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SUPPORT_VFAT
-/* DISK Partition support */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
/*
* PCI configuration
*/
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
-
#define CONFIG_SUPPORT_VFAT
-/* DISK Partition support */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
#endif /* _CONFIG_MVEBU_DB_88F3720_H */
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define CONFIG_ENV_OVERWRITE
/* ESDHC driver */
-#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_POWER_FSL_MC34704
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
-#define CONFIG_DOS_PARTITION
-
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
/* mmc driver */
-#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/*
* Eth Configs
*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_MII
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_GENERIC_MMC
-
/* bootz: zImage/initrd.img support */
-#define CONFIG_DOS_PARTITION
/* Eth Configs */
#define CONFIG_MII
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* Eth Configs */
#define CONFIG_MII
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* Eth Configs */
#define CONFIG_MII
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_MII
/* Filesystems and image support */
#define CONFIG_SUPPORT_RAW_INITRD
-#define CONFIG_DOS_PARTITION
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_MXC_GPIO
/* MMC */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#include "imx6_spl.h"
#endif
-#define MACH_TYPE_MX6SLEVK 4307
-#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
+#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* I2C Configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
/* NAND flash command */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
-/* Filesystems and image support */
-#define CONFIG_DOS_PARTITION
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_MXC_UART
/* MMC */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#endif
#define _CONFIG_NAS220_H
/*
- * Machine type definition and ID
+ * Machine type ID
*/
-#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS
-#define CONFIG_MACH_TYPE MACH_TYPE_NAS220
+#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS
/*
* High Level Configuration Options (easy to change)
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/*
* EFI partition
*/
-#define CONFIG_EFI_PARTITION
/*
* Date Time
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
+ "usb_pgood_delay=2000\0" \
"mmcdevs=0 1\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootdevs=" CONFIG_DRIVE_TYPES "\0" \
"umsdevs=" CONFIG_UMSDEVS "\0" \
+ "usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
"sf erase 0xc0000 0x2000 && " \
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
/* USB */
#define CONFIG_USB_MUSB_UDC
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
-#define CONFIG_DOS_PARTITION
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /* CONFIG_CMD_IDE */
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_XLB_PIPELINING 1
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_SERIAL2
#endif
-/* Provide MACH_TYPE for compatibility with non-DT kernels */
-#define MACH_TYPE_OMAP3_CAIRO 3063
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
+/* Provide the MACH_TYPE value the vendor kernel requires */
+#define CONFIG_MACH_TYPE 3063
/*-----------------------------------------------------------------------
* FLASH and environment organization
* ----------------------------------------------------------------------------
*/
-/* MMC */
-#define CONFIG_GENERIC_MMC
-
/* SPL */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* Partition tables */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
/* USB
*
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
/* Enhance our eMMC support / experience. */
-#define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
#define CONFIG_HSMMC2_8BIT
#define CONFIG_SUPPORT_EMMC_BOOT
#endif
/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
#undef CONFIG_ENV_IS_IN_MMC
#endif
#endif /*CONFIG_MVSATA_IDE*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_MVEBU_MMC
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
#endif /* CONFIG_CMD_MMC */
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
- || defined(CONFIG_FSL_SATA)
-#define CONFIG_DOS_PARTITION
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
- || defined(CONFIG_FSL_SATA)
-#define CONFIG_DOS_PARTITION
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/*---USB -------------------------------------------*/
#if 0
#define CONFIG_USB_OHCI
-#define CONFIG_DOS_PARTITION
#endif
/*---ATA PCMCIA ------------------------------------*/
#define CONFIG_PCMCIA_SLOT_A
#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1
#define CONFIG_SYS_ATA_STRIDE 4
#define CONFIG_ATAPI 1
-/* we enable IDE and FAT support, so we also need partition support */
-#define CONFIG_DOS_PARTITION 1
-
/* USB */
#define CONFIG_USB_OHCI
#include <configs/ti_am335x_common.h>
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define MACH_TYPE_PCM051 4144 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
/* set to negative value for no autoboot */
/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/* Mach type */
-#define MACH_TYPE_PEPPER 4207 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*-----------------------------------------------------------------------
- * SDHC Configuration
- */
-#define CONFIG_GENERIC_MMC
-
/*--------------------------------------------------
* USB Configuration
*/
* File System Configuration
*/
/* FAT FS */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_PARTITION_UUIDS
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_FAT
#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_PART
/* EXT4 FS */
#define CONFIG_FS_EXT4
#define CONFIG_FSL_USDHC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_EMMC_BOOT
/* USB Configs */
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_TEXT_BASE 0
-#define MACH_TYPE_PM9261 1187
#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
/* clocks */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_TEXT_BASE 0
-#define MACH_TYPE_PM9263 1475
#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
/* clocks */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
-#define MACH_TYPE_PM9G45 2672
#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45
/* ARM asynchronous clock */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
/*
* Machine type definition and ID
*/
-#define MACH_TYPE_POGO_E02 3542
#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02
/*
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* SD */
-#define CONFIG_GENERIC_MMC
#define CONFIG_SH_SDHI_FREQ 97500000
/* Module stop status bits */
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_DOS_PARTITION
#endif
/*
#define __CONFIG_PXM2_H
#define CONFIG_SIEMENS_PXM2
-#define MACH_TYPE_PXM2 4309
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2
#include "siemens-am33x-common.h"
#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
-#define CONFIG_DOS_PARTITION
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CONFIG_IDE_SWAP_IO
#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
-#define CONFIG_DOS_PARTITION
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CONFIG_IDE_SWAP_IO
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
#define CONFIG_LBA48
-#define CONFIG_DOS_PARTITION
/*
* Environment
*/
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IDE
-#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_SH_ZIMAGEBOOT
/* SCIF */
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IDE
-#define CONFIG_DOS_PARTITION
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 115200
"led4=60,0,1\0" \
"led5=63,0,1\0"
-#undef CONFIG_DOS_PARTITION
-
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Support File sytems */
#define CONFIG_FAT_WRITE
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
/* Support File sytems */
#define CONFIG_FAT_WRITE
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SPL_TEXT_BASE 0xff704004
/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
#define CONFIG_FS_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
-#define CONFIG_CMD_PART
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
func(PXE, pxe, na) \
func(DHCP, dchp, na)
- /* Enable gpt partition table */
-#define CONFIG_CMD_GPT
#define CONFIG_RANDOM_UUID
-#define CONFIG_PARTITION_UUIDS
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
#endif
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ *
+ * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
+ * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
+ * rather than obtaining a valid ID:-/
+ *
+ * For the bcm2837, hopefully a machine type is not needed, since everything
+ * is DT.
+ */
+#ifdef CONFIG_BCM2835
+#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
+#endif
+
/* Memory layout */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_VIDEO_BCM2835
#define CONFIG_SYS_WHITE_ON_BLACK
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#ifndef CONFIG_BCM2835
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_COMMAND_HISTORY
-/* Commands */
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
/* ATAGs support for bootm/bootz */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define __CONFIG_RUT_H
#define CONFIG_SIEMENS_RUT
-#define MACH_TYPE_RUT 4316
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
#include "siemens-am33x-common.h"
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
/* #define CONFIG_CMD_EXT2 EXT2 Support */
-#define CONFIG_DOS_PARTITION
#if 0
#define CONFIG_BAUDRATE 115200
/* MMC */
-#define CONFIG_GENERIC_MMC
#define SDHCI_MAX_HOSTS 4
/* PWM */
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_GPT
/* USB Composite download gadget - g_dnl */
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define CONFIG_SAMSUNG_ONENAND 1
#define CONFIG_SYS_ONENAND_BASE 0xB0000000
-#define CONFIG_DOS_PARTITION 1
-
/* write support for filesystems */
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
/* GPT */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#if defined(CONFIG_CMD_USB)
#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
#endif
/* Ethernet Hardware */
/* NAND flash */
#undef CONFIG_CMD_NAND
-/* MMC */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#endif
-
/* USB device */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained"
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* I2C */
#define AT24MAC_ADDR 0x5c
#define AT24MAC_REG 0x9a
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_ATMEL_MCI_8BIT
#endif
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_DOS_PARTITION
#endif
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
#endif
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_DOS_PARTITION
#endif
/* USB device */
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
#endif
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
#endif
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_EXT4_WRITE
#define CONFIG_CMD_CBFS
#define CONFIG_CMD_CRAMFS
-#define CONFIG_CMD_PART
-#define CONFIG_DOS_PARTITION
#define CONFIG_HOST_MAX_DEVICES 4
#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_GPT
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_AMIGA_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_MAC_PARTITION
-
/*
* Size of malloc() pool, before and after relocation
*/
#define CONFIG_SYS_SYSTEMACE_WIDTH 16
#define CONFIG_SYS_SYSTEMACE_BASE 0
-#define CONFIG_GENERIC_MMC
-
#endif
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#undef CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
/* System configuration */
#define CONFIG_MX28 /* i.MX28 SoC */
-#define MACH_TYPE_SC_SPS_1 4172
#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#endif /* CONFIG_440EPX */
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Commands additional to the ones defined in amcc-common.h
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_GENERIC_MMC 1
#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_GENERIC_MMC 1
#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_GENERIC_MMC 1
#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SH_ZIMAGEBOOT
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
* SDIO/MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_MVEBU_MMC
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
#endif /* CONFIG_CMD_MMC */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
-#define CONFIG_DOS_PARTITION
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* MMCIF */
-#define CONFIG_GENERIC_MMC
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xee200000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_SYS_MAXARGS 32
/* setting board specific options */
+#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
#define CONFIG_AUTO_COMPLETE
#define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SAMSUNG_ONENAND 1
#define CONFIG_SYS_ONENAND_BASE 0xE7100000
-#define CONFIG_DOS_PARTITION 1
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
/*
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-#define CONFIG_DOS_PARTITION
-#define CONFIG_PARTITION_UUIDS
/* MMC */
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
/* LCD */
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PART
#endif /* __CONFIG_H */
#define CONFIG_SYS_NO_FLASH
-/*
- * MMC
- */
-
-#define CONFIG_GENERIC_MMC
-
/*
* Power
*/
#define CONFIG_TWL4030_INPUT
-/*
- * Partitions
- */
-
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
/*
* SPL
*/
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_GENERIC_MMC
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#define CONFIG_DOS_PARTITION 1
#endif /* __CONFIG_H */
#define CONFIG_STM32_FLASH
#define CONFIG_STM32X7_SERIAL
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_PHY_SMSC
+
#define CONFIG_STM32_HSE_HZ 25000000
#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+ sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_MALLOC_LEN (16 * 1024)
-#define CONFIG_STACKSIZE (64 << 10)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_STACKSIZE (256 * 1024)
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-/* MMC */
-#define CONFIG_GENERIC_MMC
-
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_CMD_FPGAD
/* mmc config */
#ifdef CONFIG_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SUNXI_SLOT 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
#ifdef CONFIG_MMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
-#define CONFIG_EFI_PARTITION
#endif
#endif
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* EHCI */
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
-#define MACH_TYPE_OMAP3_TAO3530 2836
-
#define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
/* *** Command definition *** */
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_PART
/* Filesystems / image support */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
/*
* SPI_MMC Settings
*/
-#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#ifdef CONFIG_CMD_I2C
#endif
-/* remove MMC support */
-#ifdef CONFIG_GENERIC_MMC
-#undef CONFIG_GENERIC_MMC
-#endif
-#ifdef CONFIG_CMD_MMC
-#endif
-
/* remove partitions/filesystems */
-#ifdef CONFIG_DOS_PARTITION
-#undef CONFIG_DOS_PARTITION
-#endif
-#ifdef CONFIG_EFI_PARTITION
-#undef CONFIG_EFI_PARTITION
-#endif
#ifdef CONFIG_FS_EXT4
#undef CONFIG_FS_EXT4
#endif
#ifdef CONFIG_CMD_USB
#endif
-/* remove part command support */
-#ifdef CONFIG_PARTITION_UUIDS
-#undef CONFIG_PARTITION_UUIDS
-#endif
-
-#ifdef CONFIG_CMD_PART
-#undef CONFIG_CMD_PART
-#endif
-
#endif /* CONFIG_SPL_BUILD */
#endif /* __TEGRA_COMMON_POST_H */
/* turn on command-line edit/hist/auto */
#define CONFIG_COMMAND_HISTORY
-/* turn on commonly used storage-related commands */
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
#define CONFIG_SYS_NO_FLASH
/*
#define CONFIG_SATA_MV
#define CONFIG_LIBATA
#define CONFIG_LBA48
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT
"led0=103,1,0\0" \
"led1=64,0,1\0"
-#undef CONFIG_DOS_PARTITION
-
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
#define CONFIG_OMAP_GPIO
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
/**
* Physical Memory Map
#define CONFIG_CMD_ASKEN
#define CONFIG_OMAP_GPIO
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_FS_FAT
#define CONFIG_DM_I2C_COMPAT
#endif
-/* MMC/SD IP block */
-#define CONFIG_GENERIC_MMC
-
/* McSPI IP block */
#define CONFIG_SPI
* enabled a number of useful commands and support.
*/
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
#endif
/*
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
-/* We wont be loading up OS from SPL for now.. */
-
-/* We do not have MMC support.. yet.. */
-#undef CONFIG_GENERIC_MMC
-
-/* And no support for GPIO, yet.. */
-
/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#define CONFIG_MX6Q
-#define MACH_TYPE_TITANIUM 3769
-#define CONFIG_MACH_TYPE MACH_TYPE_TITANIUM
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE 3769
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_DOS_PARTITION
-
/*
* Diagnostics
*/
#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE 115200
-/* Console configuration */
-
-/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
-#define MACH_TYPE_TRATS 3928
#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
+#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 48000000
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
-#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define CONFIG_HW_WATCHDOG
+#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
+
/* text base address used when linking */
#define CONFIG_SYS_TEXT_BASE 0x90008000
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
/*
* Eth Configs
*/
#include "tam3517-common.h"
-#define MACH_TYPE_TAM3517 2818
#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517
#define CONFIG_TAM3517_SW3_SETTINGS
#include "imx6_spl.h"
-#define MACH_TYPE_UDOO 4800
-#define CONFIG_MACH_TYPE MACH_TYPE_UDOO
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE 4800
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
"initrd_high=0xffffffff\0" \
"fdtfile=undefined\0" \
"fdt_addr=0x83000000\0" \
+ "fdt_addr_r=0x83000000\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcrootfstype=ext4\0" \
"if test $board_name = EXTENDED; then " \
"setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
"if test $fdtfile = UNDEFINED; then " \
- "echo WARNING: Could not determine dtb to use; fi; \0" \
+ "echo WARNING: Could not determine dtb to use; fi\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"ramdisk_addr_r=0x83000000\0" \
- "ramdiskaddr=0x83000000\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
BOOTENV
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#ifdef CONFIG_ARM64
+#define CONFIG_CMD_UNZIP
+#endif
+
/*-----------------------------------------------------------------------
* MMU and Cache Setting
*----------------------------------------------------------------------*/
/* #define CONFIG_ENV_IS_NOWHERE */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET 0x80000
+#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_SIZE 0x2000
/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* USB */
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
#define CONFIG_FAT_WRITE
-#define CONFIG_DOS_PARTITION
/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_GENERIC_MMC
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_CMDLINE_EDITING /* add command line history */
+#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
+/* ARM Trusted Firmware */
+#define BOOT_IMAGES \
+ "second_image=bl1.bin\0" \
+ "third_image=fip.bin\0"
+#else
+#define BOOT_IMAGES \
+ "second_image=u-boot-spl.bin\0" \
+ "third_image=u-boot.bin\0"
+#endif
+
#define CONFIG_BOOTCOMMAND "run $bootmode"
#define CONFIG_ROOTPATH "/nfs/root/path"
"__nfsboot=run tftpboot\0"
#else
#ifdef CONFIG_ARM64
-#define CONFIG_BOOTFILE "Image"
+#define CONFIG_BOOTFILE "Image.gz"
#define LINUXBOOT_CMD "booti"
+#define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0"
#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
-#define KERNEL_SIZE "kernel_size=0x00c00000\0"
-#define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
#else
#define CONFIG_BOOTFILE "zImage"
#define LINUXBOOT_CMD "bootz"
+#define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0"
#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
-#define KERNEL_SIZE "kernel_size=0x00800000\0"
-#define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
#endif
#define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x00100000\0" \
"fdt_addr_r=0x84100000\0" \
"fdt_size=0x00008000\0" \
"kernel_addr=0x00200000\0" \
+ KERNEL_ADDR_LOAD \
KERNEL_ADDR_R \
- KERNEL_SIZE \
- RAMDISK_ADDR \
+ "kernel_size=0x00800000\0" \
+ "ramdisk_addr=0x00a00000\0" \
"ramdisk_addr_r=0x84a00000\0" \
"ramdisk_size=0x00600000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
- "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
+ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
+ "if test $kernel_addr_load = $kernel_addr_r; then " \
+ "true; " \
+ "else " \
+ "unzip $kernel_addr_load $kernel_addr_r; " \
+ "fi && " \
LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
- "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
- "setexpr kernel_size $kernel_size / 4 &&" \
- "cp $kernel_addr $kernel_addr_r $kernel_size &&" \
- "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
- "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
+ "norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \
+ "setexpr kernel_size_div4 $kernel_size / 4 && " \
+ "cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \
+ "setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \
+ "setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \
+ "cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \
+ "setexpr fdt_addr_nor $nor_base + $fdt_addr && " \
+ "setexpr fdt_size_div4 $fdt_size / 4 && " \
+ "cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \
"run boot_common\0" \
- "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
+ "nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
"run boot_common\0" \
- "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
+ "tftpboot=tftpboot $kernel_addr_load $bootfile && " \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
"run boot_common\0" \
- "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
+ "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
"tftpboot $fdt_addr_r $fdt_file &&" \
"setenv ramdisk_addr_r - &&" \
"run boot_common\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"verify=n\0" \
+ "initrd_high=0xffffffffffffffff\0" \
"nor_base=0x42000000\0" \
"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
- "tftpboot $tmp_addr u-boot-spl.bin &&" \
- "setexpr tmp_addr $nor_base + 0x60000 &&" \
- "tftpboot $tmp_addr u-boot.bin\0" \
+ "tftpboot $tmp_addr $second_image && " \
+ "setexpr tmp_addr $nor_base + 0x70000 && " \
+ "tftpboot $tmp_addr $third_image\0" \
"emmcupdate=mmcsetn &&" \
"mmc partconf $mmc_first_dev 0 1 1 &&" \
- "tftpboot u-boot-spl.bin &&" \
- "mmc write $loadaddr 0 80 &&" \
- "tftpboot u-boot.bin &&" \
- "mmc write $loadaddr 80 780\0" \
+ "tftpboot $second_image && " \
+ "mmc write $loadaddr 0 100 && " \
+ "tftpboot $third_image && " \
+ "mmc write $loadaddr 100 700\0" \
"nandupdate=nand erase 0 0x00100000 &&" \
- "tftpboot u-boot-spl.bin &&" \
- "nand write $loadaddr 0 0x00010000 &&" \
- "tftpboot u-boot.bin &&" \
- "nand write $loadaddr 0x00010000 0x000f0000\0" \
+ "tftpboot $second_image && " \
+ "nand write $loadaddr 0 0x00020000 && " \
+ "tftpboot $third_image && " \
+ "nand write $loadaddr 0x00020000 0x000e0000\0" \
+ BOOT_IMAGES \
LINUXBOOT_ENV_SETTINGS
#define CONFIG_SYS_BOOTMAPSZ 0x20000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_NR_DRAM_BANKS 3
/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
#define CONFIG_SYS_MEM_TOP_HIDE 64
+#define CONFIG_PANIC_HANG
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
+
+/* only for SPL */
#if defined(CONFIG_ARM64)
#define CONFIG_SPL_TEXT_BASE 0x30000000
#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
#else
#define CONFIG_SPL_STACK (0x00100000)
#endif
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
-
-#define CONFIG_PANIC_HANG
#define CONFIG_SPL_FRAMEWORK
#ifdef CONFIG_ARM64
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
/* subtract sizeof(struct image_header) */
-#define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
+#define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40)
-#ifdef CONFIG_SPL
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#define CONFIG_SPL_MAX_SIZE 0x14000
+#else
#define CONFIG_SPL_MAX_SIZE 0x10000
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_BSS_START_ADDR 0x30012000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR 0x30016000
#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
-#endif
+
+#define CONFIG_SPL_PAD_TO 0x20000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_GENERIC_MMC
/* USB */
#define CONFIG_USB_EHCI
* PCI - no support
*/
-/*
- * Partitions
- */
-#define CONFIG_MAC_PARTITION 1
-#define CONFIG_DOS_PARTITION 1
-
/*
* USB
*/
#endif
#if defined(CONFIG_CMD_USB)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
#define CONFIG_SUPPORT_VFAT
/*
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
+#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_ENV
-#define CONFIG_DOS_PARTITION
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_GENERIC_MMC
#define CONFIG_ARM_PL180_MMCI
#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#ifdef CONFIG_CMD_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
#define CONFIG_SYS_MMC_CLK_OD 500000
/* For generating MMC partitions */
-#define CONFIG_PARTITION_UUIDS
#define CONFIG_RANDOM_UUID
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
#endif
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "L+G VInCo"
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_DOS_PARTITION
-#endif
-
/* Ethernet Hardware */
#define CONFIG_PHY_SMSC
#define CONFIG_MACB
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_EMMC_RPMB
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
#include "imx6_spl.h"
-#define MACH_TYPE_WANDBOARD 4412
-#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD
+#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
#define CONFIG_TEGRA_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
+
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-/* SD/MMC */
-#define CONFIG_GENERIC_MMC
-
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
* the user plugged the standard 8GB MoviNAND card into J29/HSMMC/POP. If
#define CONFIG_SYS_DCACHE_OFF
-/* Only in case the value is not present in mach-types.h */
-#ifndef MACH_TYPE_FLEA3
-#define MACH_TYPE_FLEA3 3668
-#endif
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* This is required to setup the ESDC controller */
#define CONFIG_RTC_MC13XXX
/* mmc driver */
-#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_CMD_NAND
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_MXC_GPIO
#define CONFIG_NET_RETRY_COUNT 100
* Define work_92105 machine type by hand -- done only for compatibility
* with original board code
*/
-#define MACH_TYPE_WORK_92105 736
-#define CONFIG_MACH_TYPE MACH_TYPE_WORK_92105
+#define CONFIG_MACH_TYPE 736
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_DOS_PARTITION
/*
* No NOR
/* Filesystem support (for USB key) */
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_DOS_PARTITION
/*
#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * DISK Partition support
- ************************************************************/
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-#define CONFIG_CMD_PART
#ifdef CONFIG_SYS_COREBOOT
#define CONFIG_CMD_CBFS
#endif
-#define CONFIG_PARTITION_UUIDS
/* x86 GPIOs are accessed through a PCI device */
#define CONFIG_INTEL_ICH6_GPIO
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
/* Command line configuration */
#define CONFIG_CMD_ENV
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_ISO_PARTITION
-#endif
#define CONFIG_MP
/* BOOTP options */
#endif
#define CONFIG_AUTO_COMPLETE
-#if defined(CONFIG_ZYNQ_SDHCI)
-# define CONFIG_GENERIC_MMC
+#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define CONFIG_SUPPORT_EMMC_BOOT
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# define FAT_ENV_INTERFACE "mmc"
#endif
-#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB)
+#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQMP_USB)
# define CONFIG_FAT_WRITE
#endif
# define CONFIG_FASTBOOT_BUF_ADDR 0x100000
# define CONFIG_FASTBOOT_BUF_SIZE 0x6000000
# define CONFIG_FASTBOOT_FLASH
-# ifdef CONFIG_ZYNQ_SDHCI
+# ifdef CONFIG_MMC_SDHCI_ZYNQ
# define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
# endif
-# define CONFIG_PARTITION_UUIDS
-# define CONFIG_CMD_GPT
# define CONFIG_RANDOM_UUID
# define PARTS_DEFAULT \
"scriptaddr=0x02000000\0" \
"ramdisk_addr_r=0x02100000\0" \
-#if defined(CONFIG_ZYNQ_SDHCI)
+#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
# define BOOT_TARGET_DEVICES_MMC(func)
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
/* MMC support */
-#ifdef CONFIG_ZYNQ_SDHCI
+#ifdef CONFIG_MMC_SDHCI_ZYNQ
# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_DOS_PARTITION
/*
* Command configuration.
#define CONFIG_PHY1_ADDR 3
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440EP
/* USB */
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_DOS_PARTITION
#endif
/*
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
/*
* Environment settings
*/
#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
#endif
/* MMC */
-#if defined(CONFIG_ZYNQ_SDHCI)
-# define CONFIG_GENERIC_MMC
+#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#endif
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
-# if defined(CONFIG_ZYNQ_SDHCI)
+# if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
# define DFU_ALT_INFO
#endif
-#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
+#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQ_USB)
# define CONFIG_SUPPORT_VFAT
# define CONFIG_FAT_WRITE
-# define CONFIG_DOS_PARTITION
#endif
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
/* MMC support */
-#ifdef CONFIG_ZYNQ_SDHCI
+#ifdef CONFIG_MMC_SDHCI_ZYNQ
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
--- /dev/null
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Core Clocks */
+#define PLL_HPLL 1
+#define PLL_DPLL 2
+#define PLL_D2PLL 3
+#define PLL_MPLL 4
+#define ARMCLK 5
+
+
+/* Bus Clocks, derived from core clocks */
+#define BCLK_PCLK 101
+#define BCLK_LHCLK 102
+#define BCLK_MACCLK 103
+#define BCLK_SDCLK 104
+#define BCLK_ARMCLK 105
+
+#define MCLK_DDR 201
+
+/* Special clocks */
+#define PCLK_UART1 501
+#define PCLK_UART2 502
+#define PCLK_UART3 503
+#define PCLK_UART4 504
+#define PCLK_UART5 505
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
+#define __DT_BINDINGS_CLOCK_IMX6SX_H
+
+#define IMX6SX_CLK_DUMMY 0
+#define IMX6SX_CLK_CKIL 1
+#define IMX6SX_CLK_CKIH 2
+#define IMX6SX_CLK_OSC 3
+#define IMX6SX_CLK_PLL1_SYS 4
+#define IMX6SX_CLK_PLL2_BUS 5
+#define IMX6SX_CLK_PLL3_USB_OTG 6
+#define IMX6SX_CLK_PLL4_AUDIO 7
+#define IMX6SX_CLK_PLL5_VIDEO 8
+#define IMX6SX_CLK_PLL6_ENET 9
+#define IMX6SX_CLK_PLL7_USB_HOST 10
+#define IMX6SX_CLK_USBPHY1 11
+#define IMX6SX_CLK_USBPHY2 12
+#define IMX6SX_CLK_USBPHY1_GATE 13
+#define IMX6SX_CLK_USBPHY2_GATE 14
+#define IMX6SX_CLK_PCIE_REF 15
+#define IMX6SX_CLK_PCIE_REF_125M 16
+#define IMX6SX_CLK_ENET_REF 17
+#define IMX6SX_CLK_PLL2_PFD0 18
+#define IMX6SX_CLK_PLL2_PFD1 19
+#define IMX6SX_CLK_PLL2_PFD2 20
+#define IMX6SX_CLK_PLL2_PFD3 21
+#define IMX6SX_CLK_PLL3_PFD0 22
+#define IMX6SX_CLK_PLL3_PFD1 23
+#define IMX6SX_CLK_PLL3_PFD2 24
+#define IMX6SX_CLK_PLL3_PFD3 25
+#define IMX6SX_CLK_PLL2_198M 26
+#define IMX6SX_CLK_PLL3_120M 27
+#define IMX6SX_CLK_PLL3_80M 28
+#define IMX6SX_CLK_PLL3_60M 29
+#define IMX6SX_CLK_TWD 30
+#define IMX6SX_CLK_PLL4_POST_DIV 31
+#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
+#define IMX6SX_CLK_PLL5_POST_DIV 33
+#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
+#define IMX6SX_CLK_STEP 35
+#define IMX6SX_CLK_PLL1_SW 36
+#define IMX6SX_CLK_OCRAM_SEL 37
+#define IMX6SX_CLK_PERIPH_PRE 38
+#define IMX6SX_CLK_PERIPH2_PRE 39
+#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
+#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
+#define IMX6SX_CLK_PCIE_AXI_SEL 42
+#define IMX6SX_CLK_GPU_AXI_SEL 43
+#define IMX6SX_CLK_GPU_CORE_SEL 44
+#define IMX6SX_CLK_EIM_SLOW_SEL 45
+#define IMX6SX_CLK_USDHC1_SEL 46
+#define IMX6SX_CLK_USDHC2_SEL 47
+#define IMX6SX_CLK_USDHC3_SEL 48
+#define IMX6SX_CLK_USDHC4_SEL 49
+#define IMX6SX_CLK_SSI1_SEL 50
+#define IMX6SX_CLK_SSI2_SEL 51
+#define IMX6SX_CLK_SSI3_SEL 52
+#define IMX6SX_CLK_QSPI1_SEL 53
+#define IMX6SX_CLK_PERCLK_SEL 54
+#define IMX6SX_CLK_VID_SEL 55
+#define IMX6SX_CLK_ESAI_SEL 56
+#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
+#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
+#define IMX6SX_CLK_CAN_SEL 59
+#define IMX6SX_CLK_UART_SEL 60
+#define IMX6SX_CLK_QSPI2_SEL 61
+#define IMX6SX_CLK_LDB_DI1_SEL 62
+#define IMX6SX_CLK_LDB_DI0_SEL 63
+#define IMX6SX_CLK_SPDIF_SEL 64
+#define IMX6SX_CLK_AUDIO_SEL 65
+#define IMX6SX_CLK_ENET_PRE_SEL 66
+#define IMX6SX_CLK_ENET_SEL 67
+#define IMX6SX_CLK_M4_PRE_SEL 68
+#define IMX6SX_CLK_M4_SEL 69
+#define IMX6SX_CLK_ECSPI_SEL 70
+#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
+#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
+#define IMX6SX_CLK_LCDIF1_SEL 73
+#define IMX6SX_CLK_LCDIF2_SEL 74
+#define IMX6SX_CLK_DISPLAY_SEL 75
+#define IMX6SX_CLK_CSI_SEL 76
+#define IMX6SX_CLK_CKO1_SEL 77
+#define IMX6SX_CLK_CKO2_SEL 78
+#define IMX6SX_CLK_CKO 79
+#define IMX6SX_CLK_PERIPH_CLK2 80
+#define IMX6SX_CLK_PERIPH2_CLK2 81
+#define IMX6SX_CLK_IPG 82
+#define IMX6SX_CLK_GPU_CORE_PODF 83
+#define IMX6SX_CLK_GPU_AXI_PODF 84
+#define IMX6SX_CLK_LCDIF1_PODF 85
+#define IMX6SX_CLK_QSPI1_PODF 86
+#define IMX6SX_CLK_EIM_SLOW_PODF 87
+#define IMX6SX_CLK_LCDIF2_PODF 88
+#define IMX6SX_CLK_PERCLK 89
+#define IMX6SX_CLK_VID_PODF 90
+#define IMX6SX_CLK_CAN_PODF 91
+#define IMX6SX_CLK_USDHC1_PODF 92
+#define IMX6SX_CLK_USDHC2_PODF 93
+#define IMX6SX_CLK_USDHC3_PODF 94
+#define IMX6SX_CLK_USDHC4_PODF 95
+#define IMX6SX_CLK_UART_PODF 96
+#define IMX6SX_CLK_ESAI_PRED 97
+#define IMX6SX_CLK_ESAI_PODF 98
+#define IMX6SX_CLK_SSI3_PRED 99
+#define IMX6SX_CLK_SSI3_PODF 100
+#define IMX6SX_CLK_SSI1_PRED 101
+#define IMX6SX_CLK_SSI1_PODF 102
+#define IMX6SX_CLK_QSPI2_PRED 103
+#define IMX6SX_CLK_QSPI2_PODF 104
+#define IMX6SX_CLK_SSI2_PRED 105
+#define IMX6SX_CLK_SSI2_PODF 106
+#define IMX6SX_CLK_SPDIF_PRED 107
+#define IMX6SX_CLK_SPDIF_PODF 108
+#define IMX6SX_CLK_AUDIO_PRED 109
+#define IMX6SX_CLK_AUDIO_PODF 110
+#define IMX6SX_CLK_ENET_PODF 111
+#define IMX6SX_CLK_M4_PODF 112
+#define IMX6SX_CLK_ECSPI_PODF 113
+#define IMX6SX_CLK_LCDIF1_PRED 114
+#define IMX6SX_CLK_LCDIF2_PRED 115
+#define IMX6SX_CLK_DISPLAY_PODF 116
+#define IMX6SX_CLK_CSI_PODF 117
+#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
+#define IMX6SX_CLK_LDB_DI0_DIV_7 119
+#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
+#define IMX6SX_CLK_LDB_DI1_DIV_7 121
+#define IMX6SX_CLK_CKO1_PODF 122
+#define IMX6SX_CLK_CKO2_PODF 123
+#define IMX6SX_CLK_PERIPH 124
+#define IMX6SX_CLK_PERIPH2 125
+#define IMX6SX_CLK_OCRAM 126
+#define IMX6SX_CLK_AHB 127
+#define IMX6SX_CLK_MMDC_PODF 128
+#define IMX6SX_CLK_ARM 129
+#define IMX6SX_CLK_AIPS_TZ1 130
+#define IMX6SX_CLK_AIPS_TZ2 131
+#define IMX6SX_CLK_APBH_DMA 132
+#define IMX6SX_CLK_ASRC_GATE 133
+#define IMX6SX_CLK_CAAM_MEM 134
+#define IMX6SX_CLK_CAAM_ACLK 135
+#define IMX6SX_CLK_CAAM_IPG 136
+#define IMX6SX_CLK_CAN1_IPG 137
+#define IMX6SX_CLK_CAN1_SERIAL 138
+#define IMX6SX_CLK_CAN2_IPG 139
+#define IMX6SX_CLK_CAN2_SERIAL 140
+#define IMX6SX_CLK_CPU_DEBUG 141
+#define IMX6SX_CLK_DCIC1 142
+#define IMX6SX_CLK_DCIC2 143
+#define IMX6SX_CLK_AIPS_TZ3 144
+#define IMX6SX_CLK_ECSPI1 145
+#define IMX6SX_CLK_ECSPI2 146
+#define IMX6SX_CLK_ECSPI3 147
+#define IMX6SX_CLK_ECSPI4 148
+#define IMX6SX_CLK_ECSPI5 149
+#define IMX6SX_CLK_EPIT1 150
+#define IMX6SX_CLK_EPIT2 151
+#define IMX6SX_CLK_ESAI_EXTAL 152
+#define IMX6SX_CLK_WAKEUP 153
+#define IMX6SX_CLK_GPT_BUS 154
+#define IMX6SX_CLK_GPT_SERIAL 155
+#define IMX6SX_CLK_GPU 156
+#define IMX6SX_CLK_OCRAM_S 157
+#define IMX6SX_CLK_CANFD 158
+#define IMX6SX_CLK_CSI 159
+#define IMX6SX_CLK_I2C1 160
+#define IMX6SX_CLK_I2C2 161
+#define IMX6SX_CLK_I2C3 162
+#define IMX6SX_CLK_OCOTP 163
+#define IMX6SX_CLK_IOMUXC 164
+#define IMX6SX_CLK_IPMUX1 165
+#define IMX6SX_CLK_IPMUX2 166
+#define IMX6SX_CLK_IPMUX3 167
+#define IMX6SX_CLK_TZASC1 168
+#define IMX6SX_CLK_LCDIF_APB 169
+#define IMX6SX_CLK_PXP_AXI 170
+#define IMX6SX_CLK_M4 171
+#define IMX6SX_CLK_ENET 172
+#define IMX6SX_CLK_DISPLAY_AXI 173
+#define IMX6SX_CLK_LCDIF2_PIX 174
+#define IMX6SX_CLK_LCDIF1_PIX 175
+#define IMX6SX_CLK_LDB_DI0 176
+#define IMX6SX_CLK_QSPI1 177
+#define IMX6SX_CLK_MLB 178
+#define IMX6SX_CLK_MMDC_P0_FAST 179
+#define IMX6SX_CLK_MMDC_P0_IPG 180
+#define IMX6SX_CLK_AXI 181
+#define IMX6SX_CLK_PCIE_AXI 182
+#define IMX6SX_CLK_QSPI2 183
+#define IMX6SX_CLK_PER1_BCH 184
+#define IMX6SX_CLK_PER2_MAIN 185
+#define IMX6SX_CLK_PWM1 186
+#define IMX6SX_CLK_PWM2 187
+#define IMX6SX_CLK_PWM3 188
+#define IMX6SX_CLK_PWM4 189
+#define IMX6SX_CLK_GPMI_BCH_APB 190
+#define IMX6SX_CLK_GPMI_BCH 191
+#define IMX6SX_CLK_GPMI_IO 192
+#define IMX6SX_CLK_GPMI_APB 193
+#define IMX6SX_CLK_ROM 194
+#define IMX6SX_CLK_SDMA 195
+#define IMX6SX_CLK_SPBA 196
+#define IMX6SX_CLK_SPDIF 197
+#define IMX6SX_CLK_SSI1_IPG 198
+#define IMX6SX_CLK_SSI2_IPG 199
+#define IMX6SX_CLK_SSI3_IPG 200
+#define IMX6SX_CLK_SSI1 201
+#define IMX6SX_CLK_SSI2 202
+#define IMX6SX_CLK_SSI3 203
+#define IMX6SX_CLK_UART_IPG 204
+#define IMX6SX_CLK_UART_SERIAL 205
+#define IMX6SX_CLK_SAI1 206
+#define IMX6SX_CLK_SAI2 207
+#define IMX6SX_CLK_USBOH3 208
+#define IMX6SX_CLK_USDHC1 209
+#define IMX6SX_CLK_USDHC2 210
+#define IMX6SX_CLK_USDHC3 211
+#define IMX6SX_CLK_USDHC4 212
+#define IMX6SX_CLK_EIM_SLOW 213
+#define IMX6SX_CLK_PWM8 214
+#define IMX6SX_CLK_VADC 215
+#define IMX6SX_CLK_GIS 216
+#define IMX6SX_CLK_I2C4 217
+#define IMX6SX_CLK_PWM5 218
+#define IMX6SX_CLK_PWM6 219
+#define IMX6SX_CLK_PWM7 220
+#define IMX6SX_CLK_CKO1 221
+#define IMX6SX_CLK_CKO2 222
+#define IMX6SX_CLK_IPP_DI0 223
+#define IMX6SX_CLK_IPP_DI1 224
+#define IMX6SX_CLK_ENET_AHB 225
+#define IMX6SX_CLK_OCRAM_PODF 226
+#define IMX6SX_CLK_GPT_3M 227
+#define IMX6SX_CLK_ENET_PTP 228
+#define IMX6SX_CLK_ENET_PTP_REF 229
+#define IMX6SX_CLK_ENET2_REF 230
+#define IMX6SX_CLK_ENET2_REF_125M 231
+#define IMX6SX_CLK_AUDIO 232
+#define IMX6SX_CLK_LVDS1_SEL 233
+#define IMX6SX_CLK_LVDS1_OUT 234
+#define IMX6SX_CLK_ASRC_IPG 235
+#define IMX6SX_CLK_ASRC_MEM 236
+#define IMX6SX_CLK_SAI1_IPG 237
+#define IMX6SX_CLK_SAI2_IPG 238
+#define IMX6SX_CLK_ESAI_IPG 239
+#define IMX6SX_CLK_ESAI_MEM 240
+#define IMX6SX_CLK_LVDS1_IN 241
+#define IMX6SX_CLK_ANACLK1 242
+#define IMX6SX_PLL1_BYPASS_SRC 243
+#define IMX6SX_PLL2_BYPASS_SRC 244
+#define IMX6SX_PLL3_BYPASS_SRC 245
+#define IMX6SX_PLL4_BYPASS_SRC 246
+#define IMX6SX_PLL5_BYPASS_SRC 247
+#define IMX6SX_PLL6_BYPASS_SRC 248
+#define IMX6SX_PLL7_BYPASS_SRC 249
+#define IMX6SX_CLK_PLL1 250
+#define IMX6SX_CLK_PLL2 251
+#define IMX6SX_CLK_PLL3 252
+#define IMX6SX_CLK_PLL4 253
+#define IMX6SX_CLK_PLL5 254
+#define IMX6SX_CLK_PLL6 255
+#define IMX6SX_CLK_PLL7 256
+#define IMX6SX_PLL1_BYPASS 257
+#define IMX6SX_PLL2_BYPASS 258
+#define IMX6SX_PLL3_BYPASS 259
+#define IMX6SX_PLL4_BYPASS 260
+#define IMX6SX_PLL5_BYPASS 261
+#define IMX6SX_PLL6_BYPASS 262
+#define IMX6SX_PLL7_BYPASS 263
+#define IMX6SX_CLK_SPDIF_GCLK 264
+#define IMX6SX_CLK_CLK_END 265
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
--- /dev/null
+#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H
+#define _DT_BINDINGS_STM32F746_PINFUNC_H
+
+#define STM32F746_PA0_FUNC_GPIO 0x0
+#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F746_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F746_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F746_PA0_FUNC_USART2_CTS 0x8
+#define STM32F746_PA0_FUNC_UART4_TX 0x9
+#define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
+#define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32F746_PA0_FUNC_EVENTOUT 0x10
+#define STM32F746_PA0_FUNC_ANALOG 0x11
+
+#define STM32F746_PA1_FUNC_GPIO 0x100
+#define STM32F746_PA1_FUNC_TIM2_CH2 0x102
+#define STM32F746_PA1_FUNC_TIM5_CH2 0x103
+#define STM32F746_PA1_FUNC_USART2_RTS 0x108
+#define STM32F746_PA1_FUNC_UART4_RX 0x109
+#define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a
+#define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b
+#define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32F746_PA1_FUNC_LCD_R2 0x10f
+#define STM32F746_PA1_FUNC_EVENTOUT 0x110
+#define STM32F746_PA1_FUNC_ANALOG 0x111
+
+#define STM32F746_PA2_FUNC_GPIO 0x200
+#define STM32F746_PA2_FUNC_TIM2_CH3 0x202
+#define STM32F746_PA2_FUNC_TIM5_CH3 0x203
+#define STM32F746_PA2_FUNC_TIM9_CH1 0x204
+#define STM32F746_PA2_FUNC_USART2_TX 0x208
+#define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209
+#define STM32F746_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32F746_PA2_FUNC_LCD_R1 0x20f
+#define STM32F746_PA2_FUNC_EVENTOUT 0x210
+#define STM32F746_PA2_FUNC_ANALOG 0x211
+
+#define STM32F746_PA3_FUNC_GPIO 0x300
+#define STM32F746_PA3_FUNC_TIM2_CH4 0x302
+#define STM32F746_PA3_FUNC_TIM5_CH4 0x303
+#define STM32F746_PA3_FUNC_TIM9_CH2 0x304
+#define STM32F746_PA3_FUNC_USART2_RX 0x308
+#define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32F746_PA3_FUNC_LCD_B5 0x30f
+#define STM32F746_PA3_FUNC_EVENTOUT 0x310
+#define STM32F746_PA3_FUNC_ANALOG 0x311
+
+#define STM32F746_PA4_FUNC_GPIO 0x400
+#define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406
+#define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32F746_PA4_FUNC_USART2_CK 0x408
+#define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32F746_PA4_FUNC_EVENTOUT 0x410
+#define STM32F746_PA4_FUNC_ANALOG 0x411
+
+#define STM32F746_PA5_FUNC_GPIO 0x500
+#define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32F746_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506
+#define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32F746_PA5_FUNC_LCD_R4 0x50f
+#define STM32F746_PA5_FUNC_EVENTOUT 0x510
+#define STM32F746_PA5_FUNC_ANALOG 0x511
+
+#define STM32F746_PA6_FUNC_GPIO 0x600
+#define STM32F746_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32F746_PA6_FUNC_TIM3_CH1 0x603
+#define STM32F746_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32F746_PA6_FUNC_SPI1_MISO 0x606
+#define STM32F746_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32F746_PA6_FUNC_LCD_G2 0x60f
+#define STM32F746_PA6_FUNC_EVENTOUT 0x610
+#define STM32F746_PA6_FUNC_ANALOG 0x611
+
+#define STM32F746_PA7_FUNC_GPIO 0x700
+#define STM32F746_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32F746_PA7_FUNC_TIM3_CH2 0x703
+#define STM32F746_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706
+#define STM32F746_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d
+#define STM32F746_PA7_FUNC_EVENTOUT 0x710
+#define STM32F746_PA7_FUNC_ANALOG 0x711
+
+#define STM32F746_PA8_FUNC_GPIO 0x800
+#define STM32F746_PA8_FUNC_MCO1 0x801
+#define STM32F746_PA8_FUNC_TIM1_CH1 0x802
+#define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804
+#define STM32F746_PA8_FUNC_I2C3_SCL 0x805
+#define STM32F746_PA8_FUNC_USART1_CK 0x808
+#define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32F746_PA8_FUNC_LCD_R6 0x80f
+#define STM32F746_PA8_FUNC_EVENTOUT 0x810
+#define STM32F746_PA8_FUNC_ANALOG 0x811
+
+#define STM32F746_PA9_FUNC_GPIO 0x900
+#define STM32F746_PA9_FUNC_TIM1_CH2 0x902
+#define STM32F746_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906
+#define STM32F746_PA9_FUNC_USART1_TX 0x908
+#define STM32F746_PA9_FUNC_DCMI_D0 0x90e
+#define STM32F746_PA9_FUNC_EVENTOUT 0x910
+#define STM32F746_PA9_FUNC_ANALOG 0x911
+
+#define STM32F746_PA10_FUNC_GPIO 0xa00
+#define STM32F746_PA10_FUNC_TIM1_CH3 0xa02
+#define STM32F746_PA10_FUNC_USART1_RX 0xa08
+#define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b
+#define STM32F746_PA10_FUNC_DCMI_D1 0xa0e
+#define STM32F746_PA10_FUNC_EVENTOUT 0xa10
+#define STM32F746_PA10_FUNC_ANALOG 0xa11
+
+#define STM32F746_PA11_FUNC_GPIO 0xb00
+#define STM32F746_PA11_FUNC_TIM1_CH4 0xb02
+#define STM32F746_PA11_FUNC_USART1_CTS 0xb08
+#define STM32F746_PA11_FUNC_CAN1_RX 0xb0a
+#define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b
+#define STM32F746_PA11_FUNC_LCD_R4 0xb0f
+#define STM32F746_PA11_FUNC_EVENTOUT 0xb10
+#define STM32F746_PA11_FUNC_ANALOG 0xb11
+
+#define STM32F746_PA12_FUNC_GPIO 0xc00
+#define STM32F746_PA12_FUNC_TIM1_ETR 0xc02
+#define STM32F746_PA12_FUNC_USART1_RTS 0xc08
+#define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09
+#define STM32F746_PA12_FUNC_CAN1_TX 0xc0a
+#define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b
+#define STM32F746_PA12_FUNC_LCD_R5 0xc0f
+#define STM32F746_PA12_FUNC_EVENTOUT 0xc10
+#define STM32F746_PA12_FUNC_ANALOG 0xc11
+
+#define STM32F746_PA13_FUNC_GPIO 0xd00
+#define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01
+#define STM32F746_PA13_FUNC_EVENTOUT 0xd10
+#define STM32F746_PA13_FUNC_ANALOG 0xd11
+
+#define STM32F746_PA14_FUNC_GPIO 0xe00
+#define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01
+#define STM32F746_PA14_FUNC_EVENTOUT 0xe10
+#define STM32F746_PA14_FUNC_ANALOG 0xe11
+
+#define STM32F746_PA15_FUNC_GPIO 0xf00
+#define STM32F746_PA15_FUNC_JTDI 0xf01
+#define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02
+#define STM32F746_PA15_FUNC_HDMI_CEC 0xf05
+#define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06
+#define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07
+#define STM32F746_PA15_FUNC_UART4_RTS 0xf09
+#define STM32F746_PA15_FUNC_EVENTOUT 0xf10
+#define STM32F746_PA15_FUNC_ANALOG 0xf11
+
+
+#define STM32F746_PB0_FUNC_GPIO 0x1000
+#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
+#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
+#define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004
+#define STM32F746_PB0_FUNC_UART4_CTS 0x1009
+#define STM32F746_PB0_FUNC_LCD_R3 0x100a
+#define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b
+#define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c
+#define STM32F746_PB0_FUNC_EVENTOUT 0x1010
+#define STM32F746_PB0_FUNC_ANALOG 0x1011
+
+#define STM32F746_PB1_FUNC_GPIO 0x1100
+#define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102
+#define STM32F746_PB1_FUNC_TIM3_CH4 0x1103
+#define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104
+#define STM32F746_PB1_FUNC_LCD_R6 0x110a
+#define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b
+#define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c
+#define STM32F746_PB1_FUNC_EVENTOUT 0x1110
+#define STM32F746_PB1_FUNC_ANALOG 0x1111
+
+#define STM32F746_PB2_FUNC_GPIO 0x1200
+#define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207
+#define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208
+#define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a
+#define STM32F746_PB2_FUNC_EVENTOUT 0x1210
+#define STM32F746_PB2_FUNC_ANALOG 0x1211
+
+#define STM32F746_PB3_FUNC_GPIO 0x1300
+#define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301
+#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
+#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
+#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+#define STM32F746_PB3_FUNC_EVENTOUT 0x1310
+#define STM32F746_PB3_FUNC_ANALOG 0x1311
+
+#define STM32F746_PB4_FUNC_GPIO 0x1400
+#define STM32F746_PB4_FUNC_NJTRST 0x1401
+#define STM32F746_PB4_FUNC_TIM3_CH1 0x1403
+#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
+#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
+#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
+#define STM32F746_PB4_FUNC_EVENTOUT 0x1410
+#define STM32F746_PB4_FUNC_ANALOG 0x1411
+
+#define STM32F746_PB5_FUNC_GPIO 0x1500
+#define STM32F746_PB5_FUNC_TIM3_CH2 0x1503
+#define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505
+#define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506
+#define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507
+#define STM32F746_PB5_FUNC_CAN2_RX 0x150a
+#define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b
+#define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c
+#define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d
+#define STM32F746_PB5_FUNC_DCMI_D10 0x150e
+#define STM32F746_PB5_FUNC_EVENTOUT 0x1510
+#define STM32F746_PB5_FUNC_ANALOG 0x1511
+
+#define STM32F746_PB6_FUNC_GPIO 0x1600
+#define STM32F746_PB6_FUNC_TIM4_CH1 0x1603
+#define STM32F746_PB6_FUNC_HDMI_CEC 0x1604
+#define STM32F746_PB6_FUNC_I2C1_SCL 0x1605
+#define STM32F746_PB6_FUNC_USART1_TX 0x1608
+#define STM32F746_PB6_FUNC_CAN2_TX 0x160a
+#define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b
+#define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d
+#define STM32F746_PB6_FUNC_DCMI_D5 0x160e
+#define STM32F746_PB6_FUNC_EVENTOUT 0x1610
+#define STM32F746_PB6_FUNC_ANALOG 0x1611
+
+#define STM32F746_PB7_FUNC_GPIO 0x1700
+#define STM32F746_PB7_FUNC_TIM4_CH2 0x1703
+#define STM32F746_PB7_FUNC_I2C1_SDA 0x1705
+#define STM32F746_PB7_FUNC_USART1_RX 0x1708
+#define STM32F746_PB7_FUNC_FMC_NL 0x170d
+#define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e
+#define STM32F746_PB7_FUNC_EVENTOUT 0x1710
+#define STM32F746_PB7_FUNC_ANALOG 0x1711
+
+#define STM32F746_PB8_FUNC_GPIO 0x1800
+#define STM32F746_PB8_FUNC_TIM4_CH3 0x1803
+#define STM32F746_PB8_FUNC_TIM10_CH1 0x1804
+#define STM32F746_PB8_FUNC_I2C1_SCL 0x1805
+#define STM32F746_PB8_FUNC_CAN1_RX 0x180a
+#define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c
+#define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d
+#define STM32F746_PB8_FUNC_DCMI_D6 0x180e
+#define STM32F746_PB8_FUNC_LCD_B6 0x180f
+#define STM32F746_PB8_FUNC_EVENTOUT 0x1810
+#define STM32F746_PB8_FUNC_ANALOG 0x1811
+
+#define STM32F746_PB9_FUNC_GPIO 0x1900
+#define STM32F746_PB9_FUNC_TIM4_CH4 0x1903
+#define STM32F746_PB9_FUNC_TIM11_CH1 0x1904
+#define STM32F746_PB9_FUNC_I2C1_SDA 0x1905
+#define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906
+#define STM32F746_PB9_FUNC_CAN1_TX 0x190a
+#define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d
+#define STM32F746_PB9_FUNC_DCMI_D7 0x190e
+#define STM32F746_PB9_FUNC_LCD_B7 0x190f
+#define STM32F746_PB9_FUNC_EVENTOUT 0x1910
+#define STM32F746_PB9_FUNC_ANALOG 0x1911
+
+#define STM32F746_PB10_FUNC_GPIO 0x1a00
+#define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02
+#define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05
+#define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06
+#define STM32F746_PB10_FUNC_USART3_TX 0x1a08
+#define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b
+#define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c
+#define STM32F746_PB10_FUNC_LCD_G4 0x1a0f
+#define STM32F746_PB10_FUNC_EVENTOUT 0x1a10
+#define STM32F746_PB10_FUNC_ANALOG 0x1a11
+
+#define STM32F746_PB11_FUNC_GPIO 0x1b00
+#define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02
+#define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05
+#define STM32F746_PB11_FUNC_USART3_RX 0x1b08
+#define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b
+#define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c
+#define STM32F746_PB11_FUNC_LCD_G5 0x1b0f
+#define STM32F746_PB11_FUNC_EVENTOUT 0x1b10
+#define STM32F746_PB11_FUNC_ANALOG 0x1b11
+
+#define STM32F746_PB12_FUNC_GPIO 0x1c00
+#define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02
+#define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05
+#define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06
+#define STM32F746_PB12_FUNC_USART3_CK 0x1c08
+#define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a
+#define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b
+#define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c
+#define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d
+#define STM32F746_PB12_FUNC_EVENTOUT 0x1c10
+#define STM32F746_PB12_FUNC_ANALOG 0x1c11
+
+#define STM32F746_PB13_FUNC_GPIO 0x1d00
+#define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02
+#define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06
+#define STM32F746_PB13_FUNC_USART3_CTS 0x1d08
+#define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a
+#define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b
+#define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c
+#define STM32F746_PB13_FUNC_EVENTOUT 0x1d10
+#define STM32F746_PB13_FUNC_ANALOG 0x1d11
+
+#define STM32F746_PB14_FUNC_GPIO 0x1e00
+#define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02
+#define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04
+#define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06
+#define STM32F746_PB14_FUNC_USART3_RTS 0x1e08
+#define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a
+#define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d
+#define STM32F746_PB14_FUNC_EVENTOUT 0x1e10
+#define STM32F746_PB14_FUNC_ANALOG 0x1e11
+
+#define STM32F746_PB15_FUNC_GPIO 0x1f00
+#define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01
+#define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02
+#define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04
+#define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06
+#define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a
+#define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d
+#define STM32F746_PB15_FUNC_EVENTOUT 0x1f10
+#define STM32F746_PB15_FUNC_ANALOG 0x1f11
+
+
+#define STM32F746_PC0_FUNC_GPIO 0x2000
+#define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009
+#define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b
+#define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d
+#define STM32F746_PC0_FUNC_LCD_R5 0x200f
+#define STM32F746_PC0_FUNC_EVENTOUT 0x2010
+#define STM32F746_PC0_FUNC_ANALOG 0x2011
+
+#define STM32F746_PC1_FUNC_GPIO 0x2100
+#define STM32F746_PC1_FUNC_TRACED0 0x2101
+#define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106
+#define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107
+#define STM32F746_PC1_FUNC_ETH_MDC 0x210c
+#define STM32F746_PC1_FUNC_EVENTOUT 0x2110
+#define STM32F746_PC1_FUNC_ANALOG 0x2111
+
+#define STM32F746_PC2_FUNC_GPIO 0x2200
+#define STM32F746_PC2_FUNC_SPI2_MISO 0x2206
+#define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b
+#define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c
+#define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d
+#define STM32F746_PC2_FUNC_EVENTOUT 0x2210
+#define STM32F746_PC2_FUNC_ANALOG 0x2211
+
+#define STM32F746_PC3_FUNC_GPIO 0x2300
+#define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306
+#define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b
+#define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c
+#define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d
+#define STM32F746_PC3_FUNC_EVENTOUT 0x2310
+#define STM32F746_PC3_FUNC_ANALOG 0x2311
+
+#define STM32F746_PC4_FUNC_GPIO 0x2400
+#define STM32F746_PC4_FUNC_I2S1_MCK 0x2406
+#define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409
+#define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c
+#define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d
+#define STM32F746_PC4_FUNC_EVENTOUT 0x2410
+#define STM32F746_PC4_FUNC_ANALOG 0x2411
+
+#define STM32F746_PC5_FUNC_GPIO 0x2500
+#define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509
+#define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c
+#define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d
+#define STM32F746_PC5_FUNC_EVENTOUT 0x2510
+#define STM32F746_PC5_FUNC_ANALOG 0x2511
+
+#define STM32F746_PC6_FUNC_GPIO 0x2600
+#define STM32F746_PC6_FUNC_TIM3_CH1 0x2603
+#define STM32F746_PC6_FUNC_TIM8_CH1 0x2604
+#define STM32F746_PC6_FUNC_I2S2_MCK 0x2606
+#define STM32F746_PC6_FUNC_USART6_TX 0x2609
+#define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d
+#define STM32F746_PC6_FUNC_DCMI_D0 0x260e
+#define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f
+#define STM32F746_PC6_FUNC_EVENTOUT 0x2610
+#define STM32F746_PC6_FUNC_ANALOG 0x2611
+
+#define STM32F746_PC7_FUNC_GPIO 0x2700
+#define STM32F746_PC7_FUNC_TIM3_CH2 0x2703
+#define STM32F746_PC7_FUNC_TIM8_CH2 0x2704
+#define STM32F746_PC7_FUNC_I2S3_MCK 0x2707
+#define STM32F746_PC7_FUNC_USART6_RX 0x2709
+#define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d
+#define STM32F746_PC7_FUNC_DCMI_D1 0x270e
+#define STM32F746_PC7_FUNC_LCD_G6 0x270f
+#define STM32F746_PC7_FUNC_EVENTOUT 0x2710
+#define STM32F746_PC7_FUNC_ANALOG 0x2711
+
+#define STM32F746_PC8_FUNC_GPIO 0x2800
+#define STM32F746_PC8_FUNC_TRACED1 0x2801
+#define STM32F746_PC8_FUNC_TIM3_CH3 0x2803
+#define STM32F746_PC8_FUNC_TIM8_CH3 0x2804
+#define STM32F746_PC8_FUNC_UART5_RTS 0x2808
+#define STM32F746_PC8_FUNC_USART6_CK 0x2809
+#define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d
+#define STM32F746_PC8_FUNC_DCMI_D2 0x280e
+#define STM32F746_PC8_FUNC_EVENTOUT 0x2810
+#define STM32F746_PC8_FUNC_ANALOG 0x2811
+
+#define STM32F746_PC9_FUNC_GPIO 0x2900
+#define STM32F746_PC9_FUNC_MCO2 0x2901
+#define STM32F746_PC9_FUNC_TIM3_CH4 0x2903
+#define STM32F746_PC9_FUNC_TIM8_CH4 0x2904
+#define STM32F746_PC9_FUNC_I2C3_SDA 0x2905
+#define STM32F746_PC9_FUNC_I2S_CKIN 0x2906
+#define STM32F746_PC9_FUNC_UART5_CTS 0x2908
+#define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a
+#define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d
+#define STM32F746_PC9_FUNC_DCMI_D3 0x290e
+#define STM32F746_PC9_FUNC_EVENTOUT 0x2910
+#define STM32F746_PC9_FUNC_ANALOG 0x2911
+
+#define STM32F746_PC10_FUNC_GPIO 0x2a00
+#define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07
+#define STM32F746_PC10_FUNC_USART3_TX 0x2a08
+#define STM32F746_PC10_FUNC_UART4_TX 0x2a09
+#define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a
+#define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d
+#define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e
+#define STM32F746_PC10_FUNC_LCD_R2 0x2a0f
+#define STM32F746_PC10_FUNC_EVENTOUT 0x2a10
+#define STM32F746_PC10_FUNC_ANALOG 0x2a11
+
+#define STM32F746_PC11_FUNC_GPIO 0x2b00
+#define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07
+#define STM32F746_PC11_FUNC_USART3_RX 0x2b08
+#define STM32F746_PC11_FUNC_UART4_RX 0x2b09
+#define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a
+#define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d
+#define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e
+#define STM32F746_PC11_FUNC_EVENTOUT 0x2b10
+#define STM32F746_PC11_FUNC_ANALOG 0x2b11
+
+#define STM32F746_PC12_FUNC_GPIO 0x2c00
+#define STM32F746_PC12_FUNC_TRACED3 0x2c01
+#define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07
+#define STM32F746_PC12_FUNC_USART3_CK 0x2c08
+#define STM32F746_PC12_FUNC_UART5_TX 0x2c09
+#define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d
+#define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e
+#define STM32F746_PC12_FUNC_EVENTOUT 0x2c10
+#define STM32F746_PC12_FUNC_ANALOG 0x2c11
+
+#define STM32F746_PC13_FUNC_GPIO 0x2d00
+#define STM32F746_PC13_FUNC_EVENTOUT 0x2d10
+#define STM32F746_PC13_FUNC_ANALOG 0x2d11
+
+#define STM32F746_PC14_FUNC_GPIO 0x2e00
+#define STM32F746_PC14_FUNC_EVENTOUT 0x2e10
+#define STM32F746_PC14_FUNC_ANALOG 0x2e11
+
+#define STM32F746_PC15_FUNC_GPIO 0x2f00
+#define STM32F746_PC15_FUNC_EVENTOUT 0x2f10
+#define STM32F746_PC15_FUNC_ANALOG 0x2f11
+
+
+#define STM32F746_PD0_FUNC_GPIO 0x3000
+#define STM32F746_PD0_FUNC_CAN1_RX 0x300a
+#define STM32F746_PD0_FUNC_FMC_D2 0x300d
+#define STM32F746_PD0_FUNC_EVENTOUT 0x3010
+#define STM32F746_PD0_FUNC_ANALOG 0x3011
+
+#define STM32F746_PD1_FUNC_GPIO 0x3100
+#define STM32F746_PD1_FUNC_CAN1_TX 0x310a
+#define STM32F746_PD1_FUNC_FMC_D3 0x310d
+#define STM32F746_PD1_FUNC_EVENTOUT 0x3110
+#define STM32F746_PD1_FUNC_ANALOG 0x3111
+
+#define STM32F746_PD2_FUNC_GPIO 0x3200
+#define STM32F746_PD2_FUNC_TRACED2 0x3201
+#define STM32F746_PD2_FUNC_TIM3_ETR 0x3203
+#define STM32F746_PD2_FUNC_UART5_RX 0x3209
+#define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d
+#define STM32F746_PD2_FUNC_DCMI_D11 0x320e
+#define STM32F746_PD2_FUNC_EVENTOUT 0x3210
+#define STM32F746_PD2_FUNC_ANALOG 0x3211
+
+#define STM32F746_PD3_FUNC_GPIO 0x3300
+#define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306
+#define STM32F746_PD3_FUNC_USART2_CTS 0x3308
+#define STM32F746_PD3_FUNC_FMC_CLK 0x330d
+#define STM32F746_PD3_FUNC_DCMI_D5 0x330e
+#define STM32F746_PD3_FUNC_LCD_G7 0x330f
+#define STM32F746_PD3_FUNC_EVENTOUT 0x3310
+#define STM32F746_PD3_FUNC_ANALOG 0x3311
+
+#define STM32F746_PD4_FUNC_GPIO 0x3400
+#define STM32F746_PD4_FUNC_USART2_RTS 0x3408
+#define STM32F746_PD4_FUNC_FMC_NOE 0x340d
+#define STM32F746_PD4_FUNC_EVENTOUT 0x3410
+#define STM32F746_PD4_FUNC_ANALOG 0x3411
+
+#define STM32F746_PD5_FUNC_GPIO 0x3500
+#define STM32F746_PD5_FUNC_USART2_TX 0x3508
+#define STM32F746_PD5_FUNC_FMC_NWE 0x350d
+#define STM32F746_PD5_FUNC_EVENTOUT 0x3510
+#define STM32F746_PD5_FUNC_ANALOG 0x3511
+
+#define STM32F746_PD6_FUNC_GPIO 0x3600
+#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
+#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
+#define STM32F746_PD6_FUNC_USART2_RX 0x3608
+#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
+#define STM32F746_PD6_FUNC_DCMI_D10 0x360e
+#define STM32F746_PD6_FUNC_LCD_B2 0x360f
+#define STM32F746_PD6_FUNC_EVENTOUT 0x3610
+#define STM32F746_PD6_FUNC_ANALOG 0x3611
+
+#define STM32F746_PD7_FUNC_GPIO 0x3700
+#define STM32F746_PD7_FUNC_USART2_CK 0x3708
+#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
+#define STM32F746_PD7_FUNC_FMC_NE1 0x370d
+#define STM32F746_PD7_FUNC_EVENTOUT 0x3710
+#define STM32F746_PD7_FUNC_ANALOG 0x3711
+
+#define STM32F746_PD8_FUNC_GPIO 0x3800
+#define STM32F746_PD8_FUNC_USART3_TX 0x3808
+#define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809
+#define STM32F746_PD8_FUNC_FMC_D13 0x380d
+#define STM32F746_PD8_FUNC_EVENTOUT 0x3810
+#define STM32F746_PD8_FUNC_ANALOG 0x3811
+
+#define STM32F746_PD9_FUNC_GPIO 0x3900
+#define STM32F746_PD9_FUNC_USART3_RX 0x3908
+#define STM32F746_PD9_FUNC_FMC_D14 0x390d
+#define STM32F746_PD9_FUNC_EVENTOUT 0x3910
+#define STM32F746_PD9_FUNC_ANALOG 0x3911
+
+#define STM32F746_PD10_FUNC_GPIO 0x3a00
+#define STM32F746_PD10_FUNC_USART3_CK 0x3a08
+#define STM32F746_PD10_FUNC_FMC_D15 0x3a0d
+#define STM32F746_PD10_FUNC_LCD_B3 0x3a0f
+#define STM32F746_PD10_FUNC_EVENTOUT 0x3a10
+#define STM32F746_PD10_FUNC_ANALOG 0x3a11
+
+#define STM32F746_PD11_FUNC_GPIO 0x3b00
+#define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05
+#define STM32F746_PD11_FUNC_USART3_CTS 0x3b08
+#define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a
+#define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b
+#define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d
+#define STM32F746_PD11_FUNC_EVENTOUT 0x3b10
+#define STM32F746_PD11_FUNC_ANALOG 0x3b11
+
+#define STM32F746_PD12_FUNC_GPIO 0x3c00
+#define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03
+#define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04
+#define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05
+#define STM32F746_PD12_FUNC_USART3_RTS 0x3c08
+#define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a
+#define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b
+#define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d
+#define STM32F746_PD12_FUNC_EVENTOUT 0x3c10
+#define STM32F746_PD12_FUNC_ANALOG 0x3c11
+
+#define STM32F746_PD13_FUNC_GPIO 0x3d00
+#define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03
+#define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04
+#define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05
+#define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a
+#define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b
+#define STM32F746_PD13_FUNC_FMC_A18 0x3d0d
+#define STM32F746_PD13_FUNC_EVENTOUT 0x3d10
+#define STM32F746_PD13_FUNC_ANALOG 0x3d11
+
+#define STM32F746_PD14_FUNC_GPIO 0x3e00
+#define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03
+#define STM32F746_PD14_FUNC_UART8_CTS 0x3e09
+#define STM32F746_PD14_FUNC_FMC_D0 0x3e0d
+#define STM32F746_PD14_FUNC_EVENTOUT 0x3e10
+#define STM32F746_PD14_FUNC_ANALOG 0x3e11
+
+#define STM32F746_PD15_FUNC_GPIO 0x3f00
+#define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03
+#define STM32F746_PD15_FUNC_UART8_RTS 0x3f09
+#define STM32F746_PD15_FUNC_FMC_D1 0x3f0d
+#define STM32F746_PD15_FUNC_EVENTOUT 0x3f10
+#define STM32F746_PD15_FUNC_ANALOG 0x3f11
+
+
+#define STM32F746_PE0_FUNC_GPIO 0x4000
+#define STM32F746_PE0_FUNC_TIM4_ETR 0x4003
+#define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004
+#define STM32F746_PE0_FUNC_UART8_RX 0x4009
+#define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b
+#define STM32F746_PE0_FUNC_FMC_NBL0 0x400d
+#define STM32F746_PE0_FUNC_DCMI_D2 0x400e
+#define STM32F746_PE0_FUNC_EVENTOUT 0x4010
+#define STM32F746_PE0_FUNC_ANALOG 0x4011
+
+#define STM32F746_PE1_FUNC_GPIO 0x4100
+#define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104
+#define STM32F746_PE1_FUNC_UART8_TX 0x4109
+#define STM32F746_PE1_FUNC_FMC_NBL1 0x410d
+#define STM32F746_PE1_FUNC_DCMI_D3 0x410e
+#define STM32F746_PE1_FUNC_EVENTOUT 0x4110
+#define STM32F746_PE1_FUNC_ANALOG 0x4111
+
+#define STM32F746_PE2_FUNC_GPIO 0x4200
+#define STM32F746_PE2_FUNC_TRACECLK 0x4201
+#define STM32F746_PE2_FUNC_SPI4_SCK 0x4206
+#define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207
+#define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a
+#define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c
+#define STM32F746_PE2_FUNC_FMC_A23 0x420d
+#define STM32F746_PE2_FUNC_EVENTOUT 0x4210
+#define STM32F746_PE2_FUNC_ANALOG 0x4211
+
+#define STM32F746_PE3_FUNC_GPIO 0x4300
+#define STM32F746_PE3_FUNC_TRACED0 0x4301
+#define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307
+#define STM32F746_PE3_FUNC_FMC_A19 0x430d
+#define STM32F746_PE3_FUNC_EVENTOUT 0x4310
+#define STM32F746_PE3_FUNC_ANALOG 0x4311
+
+#define STM32F746_PE4_FUNC_GPIO 0x4400
+#define STM32F746_PE4_FUNC_TRACED1 0x4401
+#define STM32F746_PE4_FUNC_SPI4_NSS 0x4406
+#define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407
+#define STM32F746_PE4_FUNC_FMC_A20 0x440d
+#define STM32F746_PE4_FUNC_DCMI_D4 0x440e
+#define STM32F746_PE4_FUNC_LCD_B0 0x440f
+#define STM32F746_PE4_FUNC_EVENTOUT 0x4410
+#define STM32F746_PE4_FUNC_ANALOG 0x4411
+
+#define STM32F746_PE5_FUNC_GPIO 0x4500
+#define STM32F746_PE5_FUNC_TRACED2 0x4501
+#define STM32F746_PE5_FUNC_TIM9_CH1 0x4504
+#define STM32F746_PE5_FUNC_SPI4_MISO 0x4506
+#define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507
+#define STM32F746_PE5_FUNC_FMC_A21 0x450d
+#define STM32F746_PE5_FUNC_DCMI_D6 0x450e
+#define STM32F746_PE5_FUNC_LCD_G0 0x450f
+#define STM32F746_PE5_FUNC_EVENTOUT 0x4510
+#define STM32F746_PE5_FUNC_ANALOG 0x4511
+
+#define STM32F746_PE6_FUNC_GPIO 0x4600
+#define STM32F746_PE6_FUNC_TRACED3 0x4601
+#define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602
+#define STM32F746_PE6_FUNC_TIM9_CH2 0x4604
+#define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606
+#define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607
+#define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b
+#define STM32F746_PE6_FUNC_FMC_A22 0x460d
+#define STM32F746_PE6_FUNC_DCMI_D7 0x460e
+#define STM32F746_PE6_FUNC_LCD_G1 0x460f
+#define STM32F746_PE6_FUNC_EVENTOUT 0x4610
+#define STM32F746_PE6_FUNC_ANALOG 0x4611
+
+#define STM32F746_PE7_FUNC_GPIO 0x4700
+#define STM32F746_PE7_FUNC_TIM1_ETR 0x4702
+#define STM32F746_PE7_FUNC_UART7_RX 0x4709
+#define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b
+#define STM32F746_PE7_FUNC_FMC_D4 0x470d
+#define STM32F746_PE7_FUNC_EVENTOUT 0x4710
+#define STM32F746_PE7_FUNC_ANALOG 0x4711
+
+#define STM32F746_PE8_FUNC_GPIO 0x4800
+#define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802
+#define STM32F746_PE8_FUNC_UART7_TX 0x4809
+#define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b
+#define STM32F746_PE8_FUNC_FMC_D5 0x480d
+#define STM32F746_PE8_FUNC_EVENTOUT 0x4810
+#define STM32F746_PE8_FUNC_ANALOG 0x4811
+
+#define STM32F746_PE9_FUNC_GPIO 0x4900
+#define STM32F746_PE9_FUNC_TIM1_CH1 0x4902
+#define STM32F746_PE9_FUNC_UART7_RTS 0x4909
+#define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b
+#define STM32F746_PE9_FUNC_FMC_D6 0x490d
+#define STM32F746_PE9_FUNC_EVENTOUT 0x4910
+#define STM32F746_PE9_FUNC_ANALOG 0x4911
+
+#define STM32F746_PE10_FUNC_GPIO 0x4a00
+#define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02
+#define STM32F746_PE10_FUNC_UART7_CTS 0x4a09
+#define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b
+#define STM32F746_PE10_FUNC_FMC_D7 0x4a0d
+#define STM32F746_PE10_FUNC_EVENTOUT 0x4a10
+#define STM32F746_PE10_FUNC_ANALOG 0x4a11
+
+#define STM32F746_PE11_FUNC_GPIO 0x4b00
+#define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02
+#define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06
+#define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b
+#define STM32F746_PE11_FUNC_FMC_D8 0x4b0d
+#define STM32F746_PE11_FUNC_LCD_G3 0x4b0f
+#define STM32F746_PE11_FUNC_EVENTOUT 0x4b10
+#define STM32F746_PE11_FUNC_ANALOG 0x4b11
+
+#define STM32F746_PE12_FUNC_GPIO 0x4c00
+#define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02
+#define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06
+#define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b
+#define STM32F746_PE12_FUNC_FMC_D9 0x4c0d
+#define STM32F746_PE12_FUNC_LCD_B4 0x4c0f
+#define STM32F746_PE12_FUNC_EVENTOUT 0x4c10
+#define STM32F746_PE12_FUNC_ANALOG 0x4c11
+
+#define STM32F746_PE13_FUNC_GPIO 0x4d00
+#define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02
+#define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06
+#define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b
+#define STM32F746_PE13_FUNC_FMC_D10 0x4d0d
+#define STM32F746_PE13_FUNC_LCD_DE 0x4d0f
+#define STM32F746_PE13_FUNC_EVENTOUT 0x4d10
+#define STM32F746_PE13_FUNC_ANALOG 0x4d11
+
+#define STM32F746_PE14_FUNC_GPIO 0x4e00
+#define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02
+#define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06
+#define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b
+#define STM32F746_PE14_FUNC_FMC_D11 0x4e0d
+#define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f
+#define STM32F746_PE14_FUNC_EVENTOUT 0x4e10
+#define STM32F746_PE14_FUNC_ANALOG 0x4e11
+
+#define STM32F746_PE15_FUNC_GPIO 0x4f00
+#define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02
+#define STM32F746_PE15_FUNC_FMC_D12 0x4f0d
+#define STM32F746_PE15_FUNC_LCD_R7 0x4f0f
+#define STM32F746_PE15_FUNC_EVENTOUT 0x4f10
+#define STM32F746_PE15_FUNC_ANALOG 0x4f11
+
+
+#define STM32F746_PF0_FUNC_GPIO 0x5000
+#define STM32F746_PF0_FUNC_I2C2_SDA 0x5005
+#define STM32F746_PF0_FUNC_FMC_A0 0x500d
+#define STM32F746_PF0_FUNC_EVENTOUT 0x5010
+#define STM32F746_PF0_FUNC_ANALOG 0x5011
+
+#define STM32F746_PF1_FUNC_GPIO 0x5100
+#define STM32F746_PF1_FUNC_I2C2_SCL 0x5105
+#define STM32F746_PF1_FUNC_FMC_A1 0x510d
+#define STM32F746_PF1_FUNC_EVENTOUT 0x5110
+#define STM32F746_PF1_FUNC_ANALOG 0x5111
+
+#define STM32F746_PF2_FUNC_GPIO 0x5200
+#define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205
+#define STM32F746_PF2_FUNC_FMC_A2 0x520d
+#define STM32F746_PF2_FUNC_EVENTOUT 0x5210
+#define STM32F746_PF2_FUNC_ANALOG 0x5211
+
+#define STM32F746_PF3_FUNC_GPIO 0x5300
+#define STM32F746_PF3_FUNC_FMC_A3 0x530d
+#define STM32F746_PF3_FUNC_EVENTOUT 0x5310
+#define STM32F746_PF3_FUNC_ANALOG 0x5311
+
+#define STM32F746_PF4_FUNC_GPIO 0x5400
+#define STM32F746_PF4_FUNC_FMC_A4 0x540d
+#define STM32F746_PF4_FUNC_EVENTOUT 0x5410
+#define STM32F746_PF4_FUNC_ANALOG 0x5411
+
+#define STM32F746_PF5_FUNC_GPIO 0x5500
+#define STM32F746_PF5_FUNC_FMC_A5 0x550d
+#define STM32F746_PF5_FUNC_EVENTOUT 0x5510
+#define STM32F746_PF5_FUNC_ANALOG 0x5511
+
+#define STM32F746_PF6_FUNC_GPIO 0x5600
+#define STM32F746_PF6_FUNC_TIM10_CH1 0x5604
+#define STM32F746_PF6_FUNC_SPI5_NSS 0x5606
+#define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607
+#define STM32F746_PF6_FUNC_UART7_RX 0x5609
+#define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a
+#define STM32F746_PF6_FUNC_EVENTOUT 0x5610
+#define STM32F746_PF6_FUNC_ANALOG 0x5611
+
+#define STM32F746_PF7_FUNC_GPIO 0x5700
+#define STM32F746_PF7_FUNC_TIM11_CH1 0x5704
+#define STM32F746_PF7_FUNC_SPI5_SCK 0x5706
+#define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707
+#define STM32F746_PF7_FUNC_UART7_TX 0x5709
+#define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a
+#define STM32F746_PF7_FUNC_EVENTOUT 0x5710
+#define STM32F746_PF7_FUNC_ANALOG 0x5711
+
+#define STM32F746_PF8_FUNC_GPIO 0x5800
+#define STM32F746_PF8_FUNC_SPI5_MISO 0x5806
+#define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807
+#define STM32F746_PF8_FUNC_UART7_RTS 0x5809
+#define STM32F746_PF8_FUNC_TIM13_CH1 0x580a
+#define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b
+#define STM32F746_PF8_FUNC_EVENTOUT 0x5810
+#define STM32F746_PF8_FUNC_ANALOG 0x5811
+
+#define STM32F746_PF9_FUNC_GPIO 0x5900
+#define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906
+#define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907
+#define STM32F746_PF9_FUNC_UART7_CTS 0x5909
+#define STM32F746_PF9_FUNC_TIM14_CH1 0x590a
+#define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b
+#define STM32F746_PF9_FUNC_EVENTOUT 0x5910
+#define STM32F746_PF9_FUNC_ANALOG 0x5911
+
+#define STM32F746_PF10_FUNC_GPIO 0x5a00
+#define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e
+#define STM32F746_PF10_FUNC_LCD_DE 0x5a0f
+#define STM32F746_PF10_FUNC_EVENTOUT 0x5a10
+#define STM32F746_PF10_FUNC_ANALOG 0x5a11
+
+#define STM32F746_PF11_FUNC_GPIO 0x5b00
+#define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06
+#define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b
+#define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d
+#define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e
+#define STM32F746_PF11_FUNC_EVENTOUT 0x5b10
+#define STM32F746_PF11_FUNC_ANALOG 0x5b11
+
+#define STM32F746_PF12_FUNC_GPIO 0x5c00
+#define STM32F746_PF12_FUNC_FMC_A6 0x5c0d
+#define STM32F746_PF12_FUNC_EVENTOUT 0x5c10
+#define STM32F746_PF12_FUNC_ANALOG 0x5c11
+
+#define STM32F746_PF13_FUNC_GPIO 0x5d00
+#define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05
+#define STM32F746_PF13_FUNC_FMC_A7 0x5d0d
+#define STM32F746_PF13_FUNC_EVENTOUT 0x5d10
+#define STM32F746_PF13_FUNC_ANALOG 0x5d11
+
+#define STM32F746_PF14_FUNC_GPIO 0x5e00
+#define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05
+#define STM32F746_PF14_FUNC_FMC_A8 0x5e0d
+#define STM32F746_PF14_FUNC_EVENTOUT 0x5e10
+#define STM32F746_PF14_FUNC_ANALOG 0x5e11
+
+#define STM32F746_PF15_FUNC_GPIO 0x5f00
+#define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05
+#define STM32F746_PF15_FUNC_FMC_A9 0x5f0d
+#define STM32F746_PF15_FUNC_EVENTOUT 0x5f10
+#define STM32F746_PF15_FUNC_ANALOG 0x5f11
+
+
+#define STM32F746_PG0_FUNC_GPIO 0x6000
+#define STM32F746_PG0_FUNC_FMC_A10 0x600d
+#define STM32F746_PG0_FUNC_EVENTOUT 0x6010
+#define STM32F746_PG0_FUNC_ANALOG 0x6011
+
+#define STM32F746_PG1_FUNC_GPIO 0x6100
+#define STM32F746_PG1_FUNC_FMC_A11 0x610d
+#define STM32F746_PG1_FUNC_EVENTOUT 0x6110
+#define STM32F746_PG1_FUNC_ANALOG 0x6111
+
+#define STM32F746_PG2_FUNC_GPIO 0x6200
+#define STM32F746_PG2_FUNC_FMC_A12 0x620d
+#define STM32F746_PG2_FUNC_EVENTOUT 0x6210
+#define STM32F746_PG2_FUNC_ANALOG 0x6211
+
+#define STM32F746_PG3_FUNC_GPIO 0x6300
+#define STM32F746_PG3_FUNC_FMC_A13 0x630d
+#define STM32F746_PG3_FUNC_EVENTOUT 0x6310
+#define STM32F746_PG3_FUNC_ANALOG 0x6311
+
+#define STM32F746_PG4_FUNC_GPIO 0x6400
+#define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d
+#define STM32F746_PG4_FUNC_EVENTOUT 0x6410
+#define STM32F746_PG4_FUNC_ANALOG 0x6411
+
+#define STM32F746_PG5_FUNC_GPIO 0x6500
+#define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d
+#define STM32F746_PG5_FUNC_EVENTOUT 0x6510
+#define STM32F746_PG5_FUNC_ANALOG 0x6511
+
+#define STM32F746_PG6_FUNC_GPIO 0x6600
+#define STM32F746_PG6_FUNC_DCMI_D12 0x660e
+#define STM32F746_PG6_FUNC_LCD_R7 0x660f
+#define STM32F746_PG6_FUNC_EVENTOUT 0x6610
+#define STM32F746_PG6_FUNC_ANALOG 0x6611
+
+#define STM32F746_PG7_FUNC_GPIO 0x6700
+#define STM32F746_PG7_FUNC_USART6_CK 0x6709
+#define STM32F746_PG7_FUNC_FMC_INT 0x670d
+#define STM32F746_PG7_FUNC_DCMI_D13 0x670e
+#define STM32F746_PG7_FUNC_LCD_CLK 0x670f
+#define STM32F746_PG7_FUNC_EVENTOUT 0x6710
+#define STM32F746_PG7_FUNC_ANALOG 0x6711
+
+#define STM32F746_PG8_FUNC_GPIO 0x6800
+#define STM32F746_PG8_FUNC_SPI6_NSS 0x6806
+#define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808
+#define STM32F746_PG8_FUNC_USART6_RTS 0x6809
+#define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c
+#define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d
+#define STM32F746_PG8_FUNC_EVENTOUT 0x6810
+#define STM32F746_PG8_FUNC_ANALOG 0x6811
+
+#define STM32F746_PG9_FUNC_GPIO 0x6900
+#define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908
+#define STM32F746_PG9_FUNC_USART6_RX 0x6909
+#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
+#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
+#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
+#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
+#define STM32F746_PG9_FUNC_EVENTOUT 0x6910
+#define STM32F746_PG9_FUNC_ANALOG 0x6911
+
+#define STM32F746_PG10_FUNC_GPIO 0x6a00
+#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
+#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
+#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
+#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
+#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
+#define STM32F746_PG10_FUNC_EVENTOUT 0x6a10
+#define STM32F746_PG10_FUNC_ANALOG 0x6a11
+
+#define STM32F746_PG11_FUNC_GPIO 0x6b00
+#define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08
+#define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c
+#define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e
+#define STM32F746_PG11_FUNC_LCD_B3 0x6b0f
+#define STM32F746_PG11_FUNC_EVENTOUT 0x6b10
+#define STM32F746_PG11_FUNC_ANALOG 0x6b11
+
+#define STM32F746_PG12_FUNC_GPIO 0x6c00
+#define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04
+#define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06
+#define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08
+#define STM32F746_PG12_FUNC_USART6_RTS 0x6c09
+#define STM32F746_PG12_FUNC_LCD_B4 0x6c0a
+#define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d
+#define STM32F746_PG12_FUNC_LCD_B1 0x6c0f
+#define STM32F746_PG12_FUNC_EVENTOUT 0x6c10
+#define STM32F746_PG12_FUNC_ANALOG 0x6c11
+
+#define STM32F746_PG13_FUNC_GPIO 0x6d00
+#define STM32F746_PG13_FUNC_TRACED0 0x6d01
+#define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04
+#define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06
+#define STM32F746_PG13_FUNC_USART6_CTS 0x6d09
+#define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c
+#define STM32F746_PG13_FUNC_FMC_A24 0x6d0d
+#define STM32F746_PG13_FUNC_LCD_R0 0x6d0f
+#define STM32F746_PG13_FUNC_EVENTOUT 0x6d10
+#define STM32F746_PG13_FUNC_ANALOG 0x6d11
+
+#define STM32F746_PG14_FUNC_GPIO 0x6e00
+#define STM32F746_PG14_FUNC_TRACED1 0x6e01
+#define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04
+#define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06
+#define STM32F746_PG14_FUNC_USART6_TX 0x6e09
+#define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a
+#define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c
+#define STM32F746_PG14_FUNC_FMC_A25 0x6e0d
+#define STM32F746_PG14_FUNC_LCD_B0 0x6e0f
+#define STM32F746_PG14_FUNC_EVENTOUT 0x6e10
+#define STM32F746_PG14_FUNC_ANALOG 0x6e11
+
+#define STM32F746_PG15_FUNC_GPIO 0x6f00
+#define STM32F746_PG15_FUNC_USART6_CTS 0x6f09
+#define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d
+#define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e
+#define STM32F746_PG15_FUNC_EVENTOUT 0x6f10
+#define STM32F746_PG15_FUNC_ANALOG 0x6f11
+
+
+#define STM32F746_PH0_FUNC_GPIO 0x7000
+#define STM32F746_PH0_FUNC_EVENTOUT 0x7010
+#define STM32F746_PH0_FUNC_ANALOG 0x7011
+
+#define STM32F746_PH1_FUNC_GPIO 0x7100
+#define STM32F746_PH1_FUNC_EVENTOUT 0x7110
+#define STM32F746_PH1_FUNC_ANALOG 0x7111
+
+#define STM32F746_PH2_FUNC_GPIO 0x7200
+#define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204
+#define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a
+#define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b
+#define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c
+#define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d
+#define STM32F746_PH2_FUNC_LCD_R0 0x720f
+#define STM32F746_PH2_FUNC_EVENTOUT 0x7210
+#define STM32F746_PH2_FUNC_ANALOG 0x7211
+
+#define STM32F746_PH3_FUNC_GPIO 0x7300
+#define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a
+#define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b
+#define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c
+#define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d
+#define STM32F746_PH3_FUNC_LCD_R1 0x730f
+#define STM32F746_PH3_FUNC_EVENTOUT 0x7310
+#define STM32F746_PH3_FUNC_ANALOG 0x7311
+
+#define STM32F746_PH4_FUNC_GPIO 0x7400
+#define STM32F746_PH4_FUNC_I2C2_SCL 0x7405
+#define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b
+#define STM32F746_PH4_FUNC_EVENTOUT 0x7410
+#define STM32F746_PH4_FUNC_ANALOG 0x7411
+
+#define STM32F746_PH5_FUNC_GPIO 0x7500
+#define STM32F746_PH5_FUNC_I2C2_SDA 0x7505
+#define STM32F746_PH5_FUNC_SPI5_NSS 0x7506
+#define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d
+#define STM32F746_PH5_FUNC_EVENTOUT 0x7510
+#define STM32F746_PH5_FUNC_ANALOG 0x7511
+
+#define STM32F746_PH6_FUNC_GPIO 0x7600
+#define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605
+#define STM32F746_PH6_FUNC_SPI5_SCK 0x7606
+#define STM32F746_PH6_FUNC_TIM12_CH1 0x760a
+#define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c
+#define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d
+#define STM32F746_PH6_FUNC_DCMI_D8 0x760e
+#define STM32F746_PH6_FUNC_EVENTOUT 0x7610
+#define STM32F746_PH6_FUNC_ANALOG 0x7611
+
+#define STM32F746_PH7_FUNC_GPIO 0x7700
+#define STM32F746_PH7_FUNC_I2C3_SCL 0x7705
+#define STM32F746_PH7_FUNC_SPI5_MISO 0x7706
+#define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c
+#define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d
+#define STM32F746_PH7_FUNC_DCMI_D9 0x770e
+#define STM32F746_PH7_FUNC_EVENTOUT 0x7710
+#define STM32F746_PH7_FUNC_ANALOG 0x7711
+
+#define STM32F746_PH8_FUNC_GPIO 0x7800
+#define STM32F746_PH8_FUNC_I2C3_SDA 0x7805
+#define STM32F746_PH8_FUNC_FMC_D16 0x780d
+#define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e
+#define STM32F746_PH8_FUNC_LCD_R2 0x780f
+#define STM32F746_PH8_FUNC_EVENTOUT 0x7810
+#define STM32F746_PH8_FUNC_ANALOG 0x7811
+
+#define STM32F746_PH9_FUNC_GPIO 0x7900
+#define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905
+#define STM32F746_PH9_FUNC_TIM12_CH2 0x790a
+#define STM32F746_PH9_FUNC_FMC_D17 0x790d
+#define STM32F746_PH9_FUNC_DCMI_D0 0x790e
+#define STM32F746_PH9_FUNC_LCD_R3 0x790f
+#define STM32F746_PH9_FUNC_EVENTOUT 0x7910
+#define STM32F746_PH9_FUNC_ANALOG 0x7911
+
+#define STM32F746_PH10_FUNC_GPIO 0x7a00
+#define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03
+#define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05
+#define STM32F746_PH10_FUNC_FMC_D18 0x7a0d
+#define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e
+#define STM32F746_PH10_FUNC_LCD_R4 0x7a0f
+#define STM32F746_PH10_FUNC_EVENTOUT 0x7a10
+#define STM32F746_PH10_FUNC_ANALOG 0x7a11
+
+#define STM32F746_PH11_FUNC_GPIO 0x7b00
+#define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03
+#define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05
+#define STM32F746_PH11_FUNC_FMC_D19 0x7b0d
+#define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e
+#define STM32F746_PH11_FUNC_LCD_R5 0x7b0f
+#define STM32F746_PH11_FUNC_EVENTOUT 0x7b10
+#define STM32F746_PH11_FUNC_ANALOG 0x7b11
+
+#define STM32F746_PH12_FUNC_GPIO 0x7c00
+#define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03
+#define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05
+#define STM32F746_PH12_FUNC_FMC_D20 0x7c0d
+#define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e
+#define STM32F746_PH12_FUNC_LCD_R6 0x7c0f
+#define STM32F746_PH12_FUNC_EVENTOUT 0x7c10
+#define STM32F746_PH12_FUNC_ANALOG 0x7c11
+
+#define STM32F746_PH13_FUNC_GPIO 0x7d00
+#define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04
+#define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a
+#define STM32F746_PH13_FUNC_FMC_D21 0x7d0d
+#define STM32F746_PH13_FUNC_LCD_G2 0x7d0f
+#define STM32F746_PH13_FUNC_EVENTOUT 0x7d10
+#define STM32F746_PH13_FUNC_ANALOG 0x7d11
+
+#define STM32F746_PH14_FUNC_GPIO 0x7e00
+#define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04
+#define STM32F746_PH14_FUNC_FMC_D22 0x7e0d
+#define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e
+#define STM32F746_PH14_FUNC_LCD_G3 0x7e0f
+#define STM32F746_PH14_FUNC_EVENTOUT 0x7e10
+#define STM32F746_PH14_FUNC_ANALOG 0x7e11
+
+#define STM32F746_PH15_FUNC_GPIO 0x7f00
+#define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04
+#define STM32F746_PH15_FUNC_FMC_D23 0x7f0d
+#define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e
+#define STM32F746_PH15_FUNC_LCD_G4 0x7f0f
+#define STM32F746_PH15_FUNC_EVENTOUT 0x7f10
+#define STM32F746_PH15_FUNC_ANALOG 0x7f11
+
+
+#define STM32F746_PI0_FUNC_GPIO 0x8000
+#define STM32F746_PI0_FUNC_TIM5_CH4 0x8003
+#define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006
+#define STM32F746_PI0_FUNC_FMC_D24 0x800d
+#define STM32F746_PI0_FUNC_DCMI_D13 0x800e
+#define STM32F746_PI0_FUNC_LCD_G5 0x800f
+#define STM32F746_PI0_FUNC_EVENTOUT 0x8010
+#define STM32F746_PI0_FUNC_ANALOG 0x8011
+
+#define STM32F746_PI1_FUNC_GPIO 0x8100
+#define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104
+#define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106
+#define STM32F746_PI1_FUNC_FMC_D25 0x810d
+#define STM32F746_PI1_FUNC_DCMI_D8 0x810e
+#define STM32F746_PI1_FUNC_LCD_G6 0x810f
+#define STM32F746_PI1_FUNC_EVENTOUT 0x8110
+#define STM32F746_PI1_FUNC_ANALOG 0x8111
+
+#define STM32F746_PI2_FUNC_GPIO 0x8200
+#define STM32F746_PI2_FUNC_TIM8_CH4 0x8204
+#define STM32F746_PI2_FUNC_SPI2_MISO 0x8206
+#define STM32F746_PI2_FUNC_FMC_D26 0x820d
+#define STM32F746_PI2_FUNC_DCMI_D9 0x820e
+#define STM32F746_PI2_FUNC_LCD_G7 0x820f
+#define STM32F746_PI2_FUNC_EVENTOUT 0x8210
+#define STM32F746_PI2_FUNC_ANALOG 0x8211
+
+#define STM32F746_PI3_FUNC_GPIO 0x8300
+#define STM32F746_PI3_FUNC_TIM8_ETR 0x8304
+#define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306
+#define STM32F746_PI3_FUNC_FMC_D27 0x830d
+#define STM32F746_PI3_FUNC_DCMI_D10 0x830e
+#define STM32F746_PI3_FUNC_EVENTOUT 0x8310
+#define STM32F746_PI3_FUNC_ANALOG 0x8311
+
+#define STM32F746_PI4_FUNC_GPIO 0x8400
+#define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404
+#define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b
+#define STM32F746_PI4_FUNC_FMC_NBL2 0x840d
+#define STM32F746_PI4_FUNC_DCMI_D5 0x840e
+#define STM32F746_PI4_FUNC_LCD_B4 0x840f
+#define STM32F746_PI4_FUNC_EVENTOUT 0x8410
+#define STM32F746_PI4_FUNC_ANALOG 0x8411
+
+#define STM32F746_PI5_FUNC_GPIO 0x8500
+#define STM32F746_PI5_FUNC_TIM8_CH1 0x8504
+#define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b
+#define STM32F746_PI5_FUNC_FMC_NBL3 0x850d
+#define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e
+#define STM32F746_PI5_FUNC_LCD_B5 0x850f
+#define STM32F746_PI5_FUNC_EVENTOUT 0x8510
+#define STM32F746_PI5_FUNC_ANALOG 0x8511
+
+#define STM32F746_PI6_FUNC_GPIO 0x8600
+#define STM32F746_PI6_FUNC_TIM8_CH2 0x8604
+#define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b
+#define STM32F746_PI6_FUNC_FMC_D28 0x860d
+#define STM32F746_PI6_FUNC_DCMI_D6 0x860e
+#define STM32F746_PI6_FUNC_LCD_B6 0x860f
+#define STM32F746_PI6_FUNC_EVENTOUT 0x8610
+#define STM32F746_PI6_FUNC_ANALOG 0x8611
+
+#define STM32F746_PI7_FUNC_GPIO 0x8700
+#define STM32F746_PI7_FUNC_TIM8_CH3 0x8704
+#define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b
+#define STM32F746_PI7_FUNC_FMC_D29 0x870d
+#define STM32F746_PI7_FUNC_DCMI_D7 0x870e
+#define STM32F746_PI7_FUNC_LCD_B7 0x870f
+#define STM32F746_PI7_FUNC_EVENTOUT 0x8710
+#define STM32F746_PI7_FUNC_ANALOG 0x8711
+
+#define STM32F746_PI8_FUNC_GPIO 0x8800
+#define STM32F746_PI8_FUNC_EVENTOUT 0x8810
+#define STM32F746_PI8_FUNC_ANALOG 0x8811
+
+#define STM32F746_PI9_FUNC_GPIO 0x8900
+#define STM32F746_PI9_FUNC_CAN1_RX 0x890a
+#define STM32F746_PI9_FUNC_FMC_D30 0x890d
+#define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f
+#define STM32F746_PI9_FUNC_EVENTOUT 0x8910
+#define STM32F746_PI9_FUNC_ANALOG 0x8911
+
+#define STM32F746_PI10_FUNC_GPIO 0x8a00
+#define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c
+#define STM32F746_PI10_FUNC_FMC_D31 0x8a0d
+#define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f
+#define STM32F746_PI10_FUNC_EVENTOUT 0x8a10
+#define STM32F746_PI10_FUNC_ANALOG 0x8a11
+
+#define STM32F746_PI11_FUNC_GPIO 0x8b00
+#define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b
+#define STM32F746_PI11_FUNC_EVENTOUT 0x8b10
+#define STM32F746_PI11_FUNC_ANALOG 0x8b11
+
+#define STM32F746_PI12_FUNC_GPIO 0x8c00
+#define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f
+#define STM32F746_PI12_FUNC_EVENTOUT 0x8c10
+#define STM32F746_PI12_FUNC_ANALOG 0x8c11
+
+#define STM32F746_PI13_FUNC_GPIO 0x8d00
+#define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f
+#define STM32F746_PI13_FUNC_EVENTOUT 0x8d10
+#define STM32F746_PI13_FUNC_ANALOG 0x8d11
+
+#define STM32F746_PI14_FUNC_GPIO 0x8e00
+#define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f
+#define STM32F746_PI14_FUNC_EVENTOUT 0x8e10
+#define STM32F746_PI14_FUNC_ANALOG 0x8e11
+
+#define STM32F746_PI15_FUNC_GPIO 0x8f00
+#define STM32F746_PI15_FUNC_LCD_R0 0x8f0f
+#define STM32F746_PI15_FUNC_EVENTOUT 0x8f10
+#define STM32F746_PI15_FUNC_ANALOG 0x8f11
+
+
+#define STM32F746_PJ0_FUNC_GPIO 0x9000
+#define STM32F746_PJ0_FUNC_LCD_R1 0x900f
+#define STM32F746_PJ0_FUNC_EVENTOUT 0x9010
+#define STM32F746_PJ0_FUNC_ANALOG 0x9011
+
+#define STM32F746_PJ1_FUNC_GPIO 0x9100
+#define STM32F746_PJ1_FUNC_LCD_R2 0x910f
+#define STM32F746_PJ1_FUNC_EVENTOUT 0x9110
+#define STM32F746_PJ1_FUNC_ANALOG 0x9111
+
+#define STM32F746_PJ2_FUNC_GPIO 0x9200
+#define STM32F746_PJ2_FUNC_LCD_R3 0x920f
+#define STM32F746_PJ2_FUNC_EVENTOUT 0x9210
+#define STM32F746_PJ2_FUNC_ANALOG 0x9211
+
+#define STM32F746_PJ3_FUNC_GPIO 0x9300
+#define STM32F746_PJ3_FUNC_LCD_R4 0x930f
+#define STM32F746_PJ3_FUNC_EVENTOUT 0x9310
+#define STM32F746_PJ3_FUNC_ANALOG 0x9311
+
+#define STM32F746_PJ4_FUNC_GPIO 0x9400
+#define STM32F746_PJ4_FUNC_LCD_R5 0x940f
+#define STM32F746_PJ4_FUNC_EVENTOUT 0x9410
+#define STM32F746_PJ4_FUNC_ANALOG 0x9411
+
+#define STM32F746_PJ5_FUNC_GPIO 0x9500
+#define STM32F746_PJ5_FUNC_LCD_R6 0x950f
+#define STM32F746_PJ5_FUNC_EVENTOUT 0x9510
+#define STM32F746_PJ5_FUNC_ANALOG 0x9511
+
+#define STM32F746_PJ6_FUNC_GPIO 0x9600
+#define STM32F746_PJ6_FUNC_LCD_R7 0x960f
+#define STM32F746_PJ6_FUNC_EVENTOUT 0x9610
+#define STM32F746_PJ6_FUNC_ANALOG 0x9611
+
+#define STM32F746_PJ7_FUNC_GPIO 0x9700
+#define STM32F746_PJ7_FUNC_LCD_G0 0x970f
+#define STM32F746_PJ7_FUNC_EVENTOUT 0x9710
+#define STM32F746_PJ7_FUNC_ANALOG 0x9711
+
+#define STM32F746_PJ8_FUNC_GPIO 0x9800
+#define STM32F746_PJ8_FUNC_LCD_G1 0x980f
+#define STM32F746_PJ8_FUNC_EVENTOUT 0x9810
+#define STM32F746_PJ8_FUNC_ANALOG 0x9811
+
+#define STM32F746_PJ9_FUNC_GPIO 0x9900
+#define STM32F746_PJ9_FUNC_LCD_G2 0x990f
+#define STM32F746_PJ9_FUNC_EVENTOUT 0x9910
+#define STM32F746_PJ9_FUNC_ANALOG 0x9911
+
+#define STM32F746_PJ10_FUNC_GPIO 0x9a00
+#define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f
+#define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10
+#define STM32F746_PJ10_FUNC_ANALOG 0x9a11
+
+#define STM32F746_PJ11_FUNC_GPIO 0x9b00
+#define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f
+#define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10
+#define STM32F746_PJ11_FUNC_ANALOG 0x9b11
+
+#define STM32F746_PJ12_FUNC_GPIO 0x9c00
+#define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f
+#define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10
+#define STM32F746_PJ12_FUNC_ANALOG 0x9c11
+
+#define STM32F746_PJ13_FUNC_GPIO 0x9d00
+#define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f
+#define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10
+#define STM32F746_PJ13_FUNC_ANALOG 0x9d11
+
+#define STM32F746_PJ14_FUNC_GPIO 0x9e00
+#define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f
+#define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10
+#define STM32F746_PJ14_FUNC_ANALOG 0x9e11
+
+#define STM32F746_PJ15_FUNC_GPIO 0x9f00
+#define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f
+#define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10
+#define STM32F746_PJ15_FUNC_ANALOG 0x9f11
+
+
+#define STM32F746_PK0_FUNC_GPIO 0xa000
+#define STM32F746_PK0_FUNC_LCD_G5 0xa00f
+#define STM32F746_PK0_FUNC_EVENTOUT 0xa010
+#define STM32F746_PK0_FUNC_ANALOG 0xa011
+
+#define STM32F746_PK1_FUNC_GPIO 0xa100
+#define STM32F746_PK1_FUNC_LCD_G6 0xa10f
+#define STM32F746_PK1_FUNC_EVENTOUT 0xa110
+#define STM32F746_PK1_FUNC_ANALOG 0xa111
+
+#define STM32F746_PK2_FUNC_GPIO 0xa200
+#define STM32F746_PK2_FUNC_LCD_G7 0xa20f
+#define STM32F746_PK2_FUNC_EVENTOUT 0xa210
+#define STM32F746_PK2_FUNC_ANALOG 0xa211
+
+#define STM32F746_PK3_FUNC_GPIO 0xa300
+#define STM32F746_PK3_FUNC_LCD_B4 0xa30f
+#define STM32F746_PK3_FUNC_EVENTOUT 0xa310
+#define STM32F746_PK3_FUNC_ANALOG 0xa311
+
+#define STM32F746_PK4_FUNC_GPIO 0xa400
+#define STM32F746_PK4_FUNC_LCD_B5 0xa40f
+#define STM32F746_PK4_FUNC_EVENTOUT 0xa410
+#define STM32F746_PK4_FUNC_ANALOG 0xa411
+
+#define STM32F746_PK5_FUNC_GPIO 0xa500
+#define STM32F746_PK5_FUNC_LCD_B6 0xa50f
+#define STM32F746_PK5_FUNC_EVENTOUT 0xa510
+#define STM32F746_PK5_FUNC_ANALOG 0xa511
+
+#define STM32F746_PK6_FUNC_GPIO 0xa600
+#define STM32F746_PK6_FUNC_LCD_B7 0xa60f
+#define STM32F746_PK6_FUNC_EVENTOUT 0xa610
+#define STM32F746_PK6_FUNC_ANALOG 0xa611
+
+#define STM32F746_PK7_FUNC_GPIO 0xa700
+#define STM32F746_PK7_FUNC_LCD_DE 0xa70f
+#define STM32F746_PK7_FUNC_EVENTOUT 0xa710
+#define STM32F746_PK7_FUNC_ANALOG 0xa711
+
+#endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */
uchar name[32]; /* partition name */
uchar type[32]; /* string type description */
int bootable; /* Active/Bootable flag is set */
-#ifdef CONFIG_PARTITION_UUIDS
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
char uuid[37]; /* filesystem UUID as string, if exists */
#endif
#ifdef CONFIG_PARTITION_TYPE_GUID
#define U_BOOT_PART_TYPE(__name) \
ll_entry_declare(struct part_driver, __name, part_driver)
-#ifdef CONFIG_EFI_PARTITION
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
#include <part_efi.h>
/* disk/part_efi.c */
/**
gpt_header *gpt_head, gpt_entry **gpt_pte);
#endif
-#ifdef CONFIG_DOS_PARTITION
+#if CONFIG_IS_ENABLED(DOS_PARTITION)
/**
* is_valid_dos_buf() - Ensure that a DOS MBR image is valid
*
TPM_NV_INDEX_DIR = 0x10000001,
};
+enum tpm_resource_type {
+ TPM_RT_KEY = 0x00000001,
+ TPM_RT_AUTH = 0x00000002,
+ TPM_RT_HASH = 0x00000003,
+ TPM_RT_TRANS = 0x00000004,
+ TPM_RT_CONTEXT = 0x00000005,
+ TPM_RT_COUNTER = 0x00000006,
+ TPM_RT_DELEGATE = 0x00000007,
+ TPM_RT_DAA_TPM = 0x00000008,
+ TPM_RT_DAA_V0 = 0x00000009,
+ TPM_RT_DAA_V1 = 0x0000000A,
+};
+
+enum tpm_capability_areas {
+ TPM_CAP_ORD = 0x00000001,
+ TPM_CAP_ALG = 0x00000002,
+ TPM_CAP_PID = 0x00000003,
+ TPM_CAP_FLAG = 0x00000004,
+ TPM_CAP_PROPERTY = 0x00000005,
+ TPM_CAP_VERSION = 0x00000006,
+ TPM_CAP_KEY_HANDLE = 0x00000007,
+ TPM_CAP_CHECK_LOADED = 0x00000008,
+ TPM_CAP_SYM_MODE = 0x00000009,
+ TPM_CAP_KEY_STATUS = 0x0000000C,
+ TPM_CAP_NV_LIST = 0x0000000D,
+ TPM_CAP_MFR = 0x00000010,
+ TPM_CAP_NV_INDEX = 0x00000011,
+ TPM_CAP_TRANS_ALG = 0x00000012,
+ TPM_CAP_HANDLE = 0x00000014,
+ TPM_CAP_TRANS_ES = 0x00000015,
+ TPM_CAP_AUTH_ENCRYPT = 0x00000017,
+ TPM_CAP_SELECT_SIZE = 0x00000018,
+ TPM_CAP_DA_LOGIC = 0x00000019,
+ TPM_CAP_VERSION_VAL = 0x0000001A,
+};
+
#define TPM_NV_PER_GLOBALLOCK (1U << 15)
#define TPM_NV_PER_PPWRITE (1U << 0)
#define TPM_NV_PER_READ_STCLEAR (1U << 31)
*/
uint32_t tpm_get_permissions(uint32_t index, uint32_t *perm);
+/**
+ * Flush a resource with a given handle and type from the TPM
+ *
+ * @param key_handle handle of the resource
+ * @param resource_type type of the resource
+ * @return return code of the operation
+ */
+uint32_t tpm_flush_specific(uint32_t key_handle, uint32_t resource_type);
+
#endif /* __TPM_H */
const char *pdevname)
{
int disks = 0;
-#ifdef CONFIG_ISO_PARTITION
+#if CONFIG_IS_ENABLED(ISO_PARTITION)
char devname[32] = { 0 }; /* dp->str is u16[32] long */
disk_partition_t info;
int part = 1;
return 0;
}
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+uint32_t tpm_flush_specific(uint32_t key_handle, uint32_t resource_type)
+{
+ const uint8_t command[18] = {
+ 0x00, 0xc1, /* TPM_TAG */
+ 0x00, 0x00, 0x00, 0x12, /* parameter size */
+ 0x00, 0x00, 0x00, 0xba, /* TPM_COMMAND_CODE */
+ 0x00, 0x00, 0x00, 0x00, /* key handle */
+ 0x00, 0x00, 0x00, 0x00, /* resource type */
+ };
+ const size_t key_handle_offset = 10;
+ const size_t resource_type_offset = 14;
+ uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ uint32_t err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sdd",
+ 0, command, sizeof(command),
+ key_handle_offset, key_handle,
+ resource_type_offset, resource_type))
+ return TPM_LIB_ERROR;
+
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ return 0;
+}
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
+
#ifdef CONFIG_TPM_AUTH_SESSIONS
/**
echo \#include \<config_uncmd_spl.h\>; \
echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\>; \
echo \#include \<asm/config.h\>; \
+ echo \#include \<linux/kconfig.h\>; \
echo \#include \<config_fallbacks.h\>;)
endef
CONFIG_AMCC_DEF_ENV_PPC_OLD
CONFIG_AMCC_DEF_ENV_ROOTPATH
CONFIG_AMCORE
-CONFIG_AMIGA_PARTITION
CONFIG_ANDES_PCU
CONFIG_ANDES_PCU_BASE
CONFIG_AP325RXA
CONFIG_DMC_DDRTR2
CONFIG_DNET_AUTONEG_TIMEOUT
CONFIG_DNP5370_EXT_WD_DISABLE
-CONFIG_DOS_PARTITION
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
CONFIG_EEPROM_BUS_ADDRESS
CONFIG_EEPROM_CHIP_ADDRESS
CONFIG_EEPROM_LAYOUT_HELP_STRING
-CONFIG_EFI_PARTITION
CONFIG_EFLASH_PROTSECTORS
CONFIG_EHCI_DESC_BIG_ENDIAN
CONFIG_EHCI_HCD_INIT_AFTER_RESET
CONFIG_GCOV_KERNEL
CONFIG_GCOV_PROFILE_ALL
CONFIG_GENERIC_ATMEL_MCI
-CONFIG_GENERIC_MMC
CONFIG_GICV2
CONFIG_GICV3
CONFIG_GLOBAL_DATA_NOT_REG10
CONFIG_IRAM_STACK
CONFIG_IRAM_TOP
CONFIG_IRDA_BASE
-CONFIG_ISO_PARTITION
CONFIG_ISP1362_USB
CONFIG_IS_BUILTIN
CONFIG_IS_ENABLED
CONFIG_MAC_ADDR_IN_EEPROM
CONFIG_MAC_ADDR_IN_SPIFLASH
CONFIG_MAC_OFFSET
-CONFIG_MAC_PARTITION
CONFIG_MAKALU
CONFIG_MALLOC_F_ADDR
CONFIG_MALTA
CONFIG_PALMAS_USB_SS_PWR
CONFIG_PANIC_HANG
CONFIG_PARAVIRT
-CONFIG_PARTITIONS
-CONFIG_PARTITION_TYPE_GUID
-CONFIG_PARTITION_UUIDS
CONFIG_PATA_BFIN
CONFIG_PATI
CONFIG_PB1000
HOSTCFLAGS_kwbimage.o += -DCONFIG_SYS_U_BOOT_OFFS=$(CONFIG_SYS_U_BOOT_OFFS)
endif
+ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
+HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
+endif
+
# MXSImage needs LibSSL
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
HOSTLOADLIBES_mkimage += \
$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto")
For those not available from kernel.org, download from the following links.
arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/
- arc_gnu_2015.06_prebuilt_uclibc_le_archs_linux_install.tar.gz
+ download/arc-2016.09-release/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz
blackfin: http://sourceforge.net/projects/adi-toolchain/files/
blackfin-toolchain-elf-gcc-4.5-2014R1_45-RC2.x86_64.tar.bz2
nds32: http://osdk.andestech.com/packages/
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- /* TODO: check i.MX image V1 handling, for now use 'old' style */
- hdr_base = entry_point - 4096;
+ hdr_base = entry_point - imximage_init_loadsize + flash_offset;
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
- if (imximage_version == IMXIMAGE_V2) {
+ if (imximage_version == IMXIMAGE_V1)
+ header_size = sizeof(flash_header_v1_t);
+ else {
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
if (!plugin_image)
header_size += sizeof(dcd_v2_t);
else
header_size += MAX_PLUGIN_CODE_SIZE;
-
- if (imximage_init_loadsize < imximage_ivt_offset + header_size)
- imximage_init_loadsize = imximage_ivt_offset +
- header_size;
}
+ if (imximage_init_loadsize < imximage_ivt_offset + header_size)
+ imximage_init_loadsize = imximage_ivt_offset + header_size;
+
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
/* Parse dcd configuration file */
parse_cfg_file(&imximage_header, params->imagename);
- /* TODO: check i.MX image V1 handling, for now use 'old' style */
- if (imximage_version == IMXIMAGE_V1) {
- alloc_len = 4096;
- header_size = 4096;
- } else {
+ if (imximage_version == IMXIMAGE_V1)
+ header_size = sizeof(imx_header_v1_t);
+ else {
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
if (!plugin_image)
header_size += sizeof(dcd_v2_t);
else
header_size += MAX_PLUGIN_CODE_SIZE;
-
- if (imximage_init_loadsize < imximage_ivt_offset + header_size)
- imximage_init_loadsize = imximage_ivt_offset +
- header_size;
- alloc_len = imximage_init_loadsize - imximage_ivt_offset;
}
+ if (imximage_init_loadsize < imximage_ivt_offset + header_size)
+ imximage_init_loadsize = imximage_ivt_offset + header_size;
+
+ alloc_len = imximage_init_loadsize - imximage_ivt_offset;
+
if (alloc_len < header_size) {
fprintf(stderr, "%s: header error\n",
params->cmdname);
pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
- /* TODO: check i.MX image V1 handling, for now use 'old' style */
- if (imximage_version == IMXIMAGE_V1)
- return 0;
- else
- return pad_len;
+ return pad_len;
}
/*
* Image manipulator for Marvell SoCs
- * supports Kirkwood, Dove, Armada 370, and Armada XP
+ * supports Kirkwood, Dove, Armada 370, Armada XP, and Armada 38x
*
* (C) Copyright 2013 Thomas Petazzoni
* <thomas.petazzoni@free-electrons.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Not implemented: support for the register headers and secure
- * headers in v1 images
+ * Not implemented: support for the register headers in v1 images
*/
#include "imagetool.h"
#include <limits.h>
#include <image.h>
+#include <stdarg.h>
#include <stdint.h>
#include "kwbimage.h"
+#ifdef CONFIG_KWB_SECURE
+#include <openssl/rsa.h>
+#include <openssl/pem.h>
+#include <openssl/err.h>
+#include <openssl/evp.h>
+#endif
+
static struct image_cfg_element *image_cfg;
static int cfgn;
+#ifdef CONFIG_KWB_SECURE
+static int verbose_mode;
+#endif
struct boot_mode {
unsigned int id;
const char *name;
};
+/*
+ * SHA2-256 hash
+ */
+struct hash_v1 {
+ uint8_t hash[32];
+};
+
struct boot_mode boot_modes[] = {
{ 0x4D, "i2c" },
{ 0x5A, "spi" },
#define BINARY_MAX_ARGS 8
/* In-memory representation of a line of the configuration file */
+
+enum image_cfg_type {
+ IMAGE_CFG_VERSION = 0x1,
+ IMAGE_CFG_BOOT_FROM,
+ IMAGE_CFG_DEST_ADDR,
+ IMAGE_CFG_EXEC_ADDR,
+ IMAGE_CFG_NAND_BLKSZ,
+ IMAGE_CFG_NAND_BADBLK_LOCATION,
+ IMAGE_CFG_NAND_ECC_MODE,
+ IMAGE_CFG_NAND_PAGESZ,
+ IMAGE_CFG_BINARY,
+ IMAGE_CFG_PAYLOAD,
+ IMAGE_CFG_DATA,
+ IMAGE_CFG_BAUDRATE,
+ IMAGE_CFG_DEBUG,
+ IMAGE_CFG_KAK,
+ IMAGE_CFG_CSK,
+ IMAGE_CFG_CSK_INDEX,
+ IMAGE_CFG_JTAG_DELAY,
+ IMAGE_CFG_BOX_ID,
+ IMAGE_CFG_FLASH_ID,
+ IMAGE_CFG_SEC_COMMON_IMG,
+ IMAGE_CFG_SEC_SPECIALIZED_IMG,
+ IMAGE_CFG_SEC_BOOT_DEV,
+ IMAGE_CFG_SEC_FUSE_DUMP,
+
+ IMAGE_CFG_COUNT
+} type;
+
+static const char * const id_strs[] = {
+ [IMAGE_CFG_VERSION] = "VERSION",
+ [IMAGE_CFG_BOOT_FROM] = "BOOT_FROM",
+ [IMAGE_CFG_DEST_ADDR] = "DEST_ADDR",
+ [IMAGE_CFG_EXEC_ADDR] = "EXEC_ADDR",
+ [IMAGE_CFG_NAND_BLKSZ] = "NAND_BLKSZ",
+ [IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
+ [IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
+ [IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
+ [IMAGE_CFG_BINARY] = "BINARY",
+ [IMAGE_CFG_PAYLOAD] = "PAYLOAD",
+ [IMAGE_CFG_DATA] = "DATA",
+ [IMAGE_CFG_BAUDRATE] = "BAUDRATE",
+ [IMAGE_CFG_DEBUG] = "DEBUG",
+ [IMAGE_CFG_KAK] = "KAK",
+ [IMAGE_CFG_CSK] = "CSK",
+ [IMAGE_CFG_CSK_INDEX] = "CSK_INDEX",
+ [IMAGE_CFG_JTAG_DELAY] = "JTAG_DELAY",
+ [IMAGE_CFG_BOX_ID] = "BOX_ID",
+ [IMAGE_CFG_FLASH_ID] = "FLASH_ID",
+ [IMAGE_CFG_SEC_COMMON_IMG] = "SEC_COMMON_IMG",
+ [IMAGE_CFG_SEC_SPECIALIZED_IMG] = "SEC_SPECIALIZED_IMG",
+ [IMAGE_CFG_SEC_BOOT_DEV] = "SEC_BOOT_DEV",
+ [IMAGE_CFG_SEC_FUSE_DUMP] = "SEC_FUSE_DUMP"
+};
+
struct image_cfg_element {
- enum {
- IMAGE_CFG_VERSION = 0x1,
- IMAGE_CFG_BOOT_FROM,
- IMAGE_CFG_DEST_ADDR,
- IMAGE_CFG_EXEC_ADDR,
- IMAGE_CFG_NAND_BLKSZ,
- IMAGE_CFG_NAND_BADBLK_LOCATION,
- IMAGE_CFG_NAND_ECC_MODE,
- IMAGE_CFG_NAND_PAGESZ,
- IMAGE_CFG_BINARY,
- IMAGE_CFG_PAYLOAD,
- IMAGE_CFG_DATA,
- IMAGE_CFG_BAUDRATE,
- IMAGE_CFG_DEBUG,
- } type;
+ enum image_cfg_type type;
union {
unsigned int version;
unsigned int bootfrom;
struct ext_hdr_v0_reg regdata;
unsigned int baudrate;
unsigned int debug;
+ const char *key_name;
+ int csk_idx;
+ uint8_t jtag_delay;
+ uint32_t boxid;
+ uint32_t flashid;
+ bool sec_specialized_img;
+ unsigned int sec_boot_dev;
+ const char *name;
};
};
static const char *image_boot_mode_name(unsigned int id)
{
int i;
+
for (i = 0; boot_modes[i].name; i++)
if (boot_modes[i].id == id)
return boot_modes[i].name;
int image_boot_mode_id(const char *boot_mode_name)
{
int i;
+
for (i = 0; boot_modes[i].name; i++)
if (!strcmp(boot_modes[i].name, boot_mode_name))
return boot_modes[i].id;
int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
{
int i;
+
for (i = 0; nand_ecc_modes[i].name; i++)
if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name))
return nand_ecc_modes[i].id;
return count;
}
+#if defined(CONFIG_KWB_SECURE)
+
+static int image_get_csk_index(void)
+{
+ struct image_cfg_element *e;
+
+ e = image_find_option(IMAGE_CFG_CSK_INDEX);
+ if (!e)
+ return -1;
+
+ return e->csk_idx;
+}
+
+static bool image_get_spezialized_img(void)
+{
+ struct image_cfg_element *e;
+
+ e = image_find_option(IMAGE_CFG_SEC_SPECIALIZED_IMG);
+ if (!e)
+ return false;
+
+ return e->sec_specialized_img;
+}
+
+#endif
+
/*
* Compute a 8-bit checksum of a memory area. This algorithm follows
* the requirements of the Marvell SoC BootROM specifications.
}
}
+#if defined(CONFIG_KWB_SECURE)
+static void kwb_msg(const char *fmt, ...)
+{
+ if (verbose_mode) {
+ va_list ap;
+
+ va_start(ap, fmt);
+ vfprintf(stdout, fmt, ap);
+ va_end(ap);
+ }
+}
+
+static int openssl_err(const char *msg)
+{
+ unsigned long ssl_err = ERR_get_error();
+
+ fprintf(stderr, "%s", msg);
+ fprintf(stderr, ": %s\n",
+ ERR_error_string(ssl_err, 0));
+
+ return -1;
+}
+
+static int kwb_load_rsa_key(const char *keydir, const char *name, RSA **p_rsa)
+{
+ char path[PATH_MAX];
+ RSA *rsa;
+ FILE *f;
+
+ if (!keydir)
+ keydir = ".";
+
+ snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
+ f = fopen(path, "r");
+ if (!f) {
+ fprintf(stderr, "Couldn't open RSA private key: '%s': %s\n",
+ path, strerror(errno));
+ return -ENOENT;
+ }
+
+ rsa = PEM_read_RSAPrivateKey(f, 0, NULL, "");
+ if (!rsa) {
+ openssl_err("Failure reading private key");
+ fclose(f);
+ return -EPROTO;
+ }
+ fclose(f);
+ *p_rsa = rsa;
+
+ return 0;
+}
+
+static int kwb_load_cfg_key(struct image_tool_params *params,
+ unsigned int cfg_option, const char *key_name,
+ RSA **p_key)
+{
+ struct image_cfg_element *e_key;
+ RSA *key;
+ int res;
+
+ *p_key = NULL;
+
+ e_key = image_find_option(cfg_option);
+ if (!e_key) {
+ fprintf(stderr, "%s not configured\n", key_name);
+ return -ENOENT;
+ }
+
+ res = kwb_load_rsa_key(params->keydir, e_key->key_name, &key);
+ if (res < 0) {
+ fprintf(stderr, "Failed to load %s\n", key_name);
+ return -ENOENT;
+ }
+
+ *p_key = key;
+
+ return 0;
+}
+
+static int kwb_load_kak(struct image_tool_params *params, RSA **p_kak)
+{
+ return kwb_load_cfg_key(params, IMAGE_CFG_KAK, "KAK", p_kak);
+}
+
+static int kwb_load_csk(struct image_tool_params *params, RSA **p_csk)
+{
+ return kwb_load_cfg_key(params, IMAGE_CFG_CSK, "CSK", p_csk);
+}
+
+static int kwb_compute_pubkey_hash(struct pubkey_der_v1 *pk,
+ struct hash_v1 *hash)
+{
+ EVP_MD_CTX *ctx;
+ unsigned int key_size;
+ unsigned int hash_size;
+ int ret = 0;
+
+ if (!pk || !hash || pk->key[0] != 0x30 || pk->key[1] != 0x82)
+ return -EINVAL;
+
+ key_size = (pk->key[2] << 8) + pk->key[3] + 4;
+
+ ctx = EVP_MD_CTX_create();
+ if (!ctx)
+ return openssl_err("EVP context creation failed");
+
+ EVP_MD_CTX_init(ctx);
+ if (!EVP_DigestInit(ctx, EVP_sha256())) {
+ ret = openssl_err("Digest setup failed");
+ goto hash_err_ctx;
+ }
+
+ if (!EVP_DigestUpdate(ctx, pk->key, key_size)) {
+ ret = openssl_err("Hashing data failed");
+ goto hash_err_ctx;
+ }
+
+ if (!EVP_DigestFinal(ctx, hash->hash, &hash_size)) {
+ ret = openssl_err("Could not obtain hash");
+ goto hash_err_ctx;
+ }
+
+ EVP_MD_CTX_cleanup(ctx);
+
+hash_err_ctx:
+ EVP_MD_CTX_destroy(ctx);
+ return ret;
+}
+
+static int kwb_import_pubkey(RSA **key, struct pubkey_der_v1 *src, char *keyname)
+{
+ RSA *rsa;
+ const unsigned char *ptr;
+
+ if (!key || !src)
+ goto fail;
+
+ ptr = src->key;
+ rsa = d2i_RSAPublicKey(key, &ptr, sizeof(src->key));
+ if (!rsa) {
+ openssl_err("error decoding public key");
+ goto fail;
+ }
+
+ return 0;
+fail:
+ fprintf(stderr, "Failed to decode %s pubkey\n", keyname);
+ return -EINVAL;
+}
+
+static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1 *dst, FILE *hashf,
+ char *keyname)
+{
+ int size_exp, size_mod, size_seq;
+ uint8_t *cur;
+ char *errmsg = "Failed to encode %s\n";
+
+ if (!key || !key->e || !key->n || !dst) {
+ fprintf(stderr, "export pk failed: (%p, %p, %p, %p)",
+ key, key->e, key->n, dst);
+ fprintf(stderr, errmsg, keyname);
+ return -EINVAL;
+ }
+
+ /*
+ * According to the specs, the key should be PKCS#1 DER encoded.
+ * But unfortunately the really required encoding seems to be different;
+ * it violates DER...! (But it still conformes to BER.)
+ * (Length always in long form w/ 2 byte length code; no leading zero
+ * when MSB of first byte is set...)
+ * So we cannot use the encoding func provided by OpenSSL and have to
+ * do the encoding manually.
+ */
+
+ size_exp = BN_num_bytes(key->e);
+ size_mod = BN_num_bytes(key->n);
+ size_seq = 4 + size_mod + 4 + size_exp;
+
+ if (size_mod > 256) {
+ fprintf(stderr, "export pk failed: wrong mod size: %d\n",
+ size_mod);
+ fprintf(stderr, errmsg, keyname);
+ return -EINVAL;
+ }
+
+ if (4 + size_seq > sizeof(dst->key)) {
+ fprintf(stderr, "export pk failed: seq too large (%d, %lu)\n",
+ 4 + size_seq, sizeof(dst->key));
+ fprintf(stderr, errmsg, keyname);
+ return -ENOBUFS;
+ }
+
+ cur = dst->key;
+
+ /* PKCS#1 (RFC3447) RSAPublicKey structure */
+ *cur++ = 0x30; /* SEQUENCE */
+ *cur++ = 0x82;
+ *cur++ = (size_seq >> 8) & 0xFF;
+ *cur++ = size_seq & 0xFF;
+ /* Modulus */
+ *cur++ = 0x02; /* INTEGER */
+ *cur++ = 0x82;
+ *cur++ = (size_mod >> 8) & 0xFF;
+ *cur++ = size_mod & 0xFF;
+ BN_bn2bin(key->n, cur);
+ cur += size_mod;
+ /* Exponent */
+ *cur++ = 0x02; /* INTEGER */
+ *cur++ = 0x82;
+ *cur++ = (size_exp >> 8) & 0xFF;
+ *cur++ = size_exp & 0xFF;
+ BN_bn2bin(key->e, cur);
+
+ if (hashf) {
+ struct hash_v1 pk_hash;
+ int i;
+ int ret = 0;
+
+ ret = kwb_compute_pubkey_hash(dst, &pk_hash);
+ if (ret < 0) {
+ fprintf(stderr, errmsg, keyname);
+ return ret;
+ }
+
+ fprintf(hashf, "SHA256 = ");
+ for (i = 0 ; i < sizeof(pk_hash.hash); ++i)
+ fprintf(hashf, "%02X", pk_hash.hash[i]);
+ fprintf(hashf, "\n");
+ }
+
+ return 0;
+}
+
+int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig, char *signame)
+{
+ EVP_PKEY *evp_key;
+ EVP_MD_CTX *ctx;
+ unsigned int sig_size;
+ int size;
+ int ret = 0;
+
+ evp_key = EVP_PKEY_new();
+ if (!evp_key)
+ return openssl_err("EVP_PKEY object creation failed");
+
+ if (!EVP_PKEY_set1_RSA(evp_key, key)) {
+ ret = openssl_err("EVP key setup failed");
+ goto err_key;
+ }
+
+ size = EVP_PKEY_size(evp_key);
+ if (size > sizeof(sig->sig)) {
+ fprintf(stderr, "Buffer to small for signature (%d bytes)\n",
+ size);
+ ret = -ENOBUFS;
+ goto err_key;
+ }
+
+ ctx = EVP_MD_CTX_create();
+ if (!ctx) {
+ ret = openssl_err("EVP context creation failed");
+ goto err_key;
+ }
+ EVP_MD_CTX_init(ctx);
+ if (!EVP_SignInit(ctx, EVP_sha256())) {
+ ret = openssl_err("Signer setup failed");
+ goto err_ctx;
+ }
+
+ if (!EVP_SignUpdate(ctx, data, datasz)) {
+ ret = openssl_err("Signing data failed");
+ goto err_ctx;
+ }
+
+ if (!EVP_SignFinal(ctx, sig->sig, &sig_size, evp_key)) {
+ ret = openssl_err("Could not obtain signature");
+ goto err_ctx;
+ }
+
+ EVP_MD_CTX_cleanup(ctx);
+ EVP_MD_CTX_destroy(ctx);
+ EVP_PKEY_free(evp_key);
+
+ return 0;
+
+err_ctx:
+ EVP_MD_CTX_destroy(ctx);
+err_key:
+ EVP_PKEY_free(evp_key);
+ fprintf(stderr, "Failed to create %s signature\n", signame);
+ return ret;
+}
+
+int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
+ char *signame)
+{
+ EVP_PKEY *evp_key;
+ EVP_MD_CTX *ctx;
+ int size;
+ int ret = 0;
+
+ evp_key = EVP_PKEY_new();
+ if (!evp_key)
+ return openssl_err("EVP_PKEY object creation failed");
+
+ if (!EVP_PKEY_set1_RSA(evp_key, key)) {
+ ret = openssl_err("EVP key setup failed");
+ goto err_key;
+ }
+
+ size = EVP_PKEY_size(evp_key);
+ if (size > sizeof(sig->sig)) {
+ fprintf(stderr, "Invalid signature size (%d bytes)\n",
+ size);
+ ret = -EINVAL;
+ goto err_key;
+ }
+
+ ctx = EVP_MD_CTX_create();
+ if (!ctx) {
+ ret = openssl_err("EVP context creation failed");
+ goto err_key;
+ }
+ EVP_MD_CTX_init(ctx);
+ if (!EVP_VerifyInit(ctx, EVP_sha256())) {
+ ret = openssl_err("Verifier setup failed");
+ goto err_ctx;
+ }
+
+ if (!EVP_VerifyUpdate(ctx, data, datasz)) {
+ ret = openssl_err("Hashing data failed");
+ goto err_ctx;
+ }
+
+ if (!EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key)) {
+ ret = openssl_err("Could not verify signature");
+ goto err_ctx;
+ }
+
+ EVP_MD_CTX_cleanup(ctx);
+ EVP_MD_CTX_destroy(ctx);
+ EVP_PKEY_free(evp_key);
+
+ return 0;
+
+err_ctx:
+ EVP_MD_CTX_destroy(ctx);
+err_key:
+ EVP_PKEY_free(evp_key);
+ fprintf(stderr, "Failed to verify %s signature\n", signame);
+ return ret;
+}
+
+int kwb_sign_and_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
+ char *signame)
+{
+ if (kwb_sign(key, data, datasz, sig, signame) < 0)
+ return -1;
+
+ if (kwb_verify(key, data, datasz, sig, signame) < 0)
+ return -1;
+
+ return 0;
+}
+
+
+int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
+{
+ struct hash_v1 kak_pub_hash;
+ struct image_cfg_element *e;
+ unsigned int fuse_line;
+ int i, idx;
+ uint8_t *ptr;
+ uint32_t val;
+ int ret = 0;
+
+ if (!out || !sec_hdr)
+ return -EINVAL;
+
+ ret = kwb_compute_pubkey_hash(&sec_hdr->kak, &kak_pub_hash);
+ if (ret < 0)
+ goto done;
+
+ fprintf(out, "# burn KAK pub key hash\n");
+ ptr = kak_pub_hash.hash;
+ for (fuse_line = 26; fuse_line <= 30; ++fuse_line) {
+ fprintf(out, "fuse prog -y %u 0 ", fuse_line);
+
+ for (i = 4; i-- > 0;)
+ fprintf(out, "%02hx", (ushort)ptr[i]);
+ ptr += 4;
+ fprintf(out, " 00");
+
+ if (fuse_line < 30) {
+ for (i = 3; i-- > 0;)
+ fprintf(out, "%02hx", (ushort)ptr[i]);
+ ptr += 3;
+ } else {
+ fprintf(out, "000000");
+ }
+
+ fprintf(out, " 1\n");
+ }
+
+ fprintf(out, "# burn CSK selection\n");
+
+ idx = image_get_csk_index();
+ if (idx < 0 || idx > 15) {
+ ret = -EINVAL;
+ goto done;
+ }
+ if (idx > 0) {
+ for (fuse_line = 31; fuse_line < 31 + idx; ++fuse_line)
+ fprintf(out, "fuse prog -y %u 0 00000001 00000000 1\n",
+ fuse_line);
+ } else {
+ fprintf(out, "# CSK index is 0; no mods needed\n");
+ }
+
+ e = image_find_option(IMAGE_CFG_BOX_ID);
+ if (e) {
+ fprintf(out, "# set box ID\n");
+ fprintf(out, "fuse prog -y 48 0 %08x 00000000 1\n", e->boxid);
+ }
+
+ e = image_find_option(IMAGE_CFG_FLASH_ID);
+ if (e) {
+ fprintf(out, "# set flash ID\n");
+ fprintf(out, "fuse prog -y 47 0 %08x 00000000 1\n", e->flashid);
+ }
+
+ fprintf(out, "# enable secure mode ");
+ fprintf(out, "(must be the last fuse line written)\n");
+
+ val = 1;
+ e = image_find_option(IMAGE_CFG_SEC_BOOT_DEV);
+ if (!e) {
+ fprintf(stderr, "ERROR: secured mode boot device not given\n");
+ ret = -EINVAL;
+ goto done;
+ }
+
+ if (e->sec_boot_dev > 0xff) {
+ fprintf(stderr, "ERROR: secured mode boot device invalid\n");
+ ret = -EINVAL;
+ goto done;
+ }
+
+ val |= (e->sec_boot_dev << 8);
+
+ fprintf(out, "fuse prog -y 24 0 %08x 0103e0a9 1\n", val);
+
+ fprintf(out, "# lock (unused) fuse lines (0-23)s\n");
+ for (fuse_line = 0; fuse_line < 24; ++fuse_line)
+ fprintf(out, "fuse prog -y %u 2 1\n", fuse_line);
+
+ fprintf(out, "# OK, that's all :-)\n");
+
+done:
+ return ret;
+}
+
+static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr)
+{
+ int ret = 0;
+ struct image_cfg_element *e;
+
+ e = image_find_option(IMAGE_CFG_SEC_FUSE_DUMP);
+ if (!e)
+ return 0;
+
+ if (!strcmp(e->name, "a38x")) {
+ FILE *out = fopen("kwb_fuses_a38x.txt", "w+");
+
+ kwb_dump_fuse_cmds_38x(out, sec_hdr);
+ fclose(out);
+ goto done;
+ }
+
+ ret = -ENOSYS;
+
+done:
+ return ret;
+}
+
+#endif
+
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
struct image_cfg_element *e;
size_t headersz;
struct main_hdr_v0 *main_hdr;
- struct ext_hdr_v0 *ext_hdr;
- void *image;
+ uint8_t *image;
int has_ext = 0;
/*
memset(image, 0, headersz);
- main_hdr = image;
+ main_hdr = (struct main_hdr_v0 *)image;
/* Fill in the main header */
main_hdr->blocksize =
/* Generate the ext header */
if (has_ext) {
+ struct ext_hdr_v0 *ext_hdr;
int cfgi, datai;
- ext_hdr = image + sizeof(struct main_hdr_v0);
+ ext_hdr = (struct ext_hdr_v0 *)
+ (image + sizeof(struct main_hdr_v0));
ext_hdr->offset = cpu_to_le32(0x40);
for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
return image;
}
-static size_t image_headersz_v1(struct image_tool_params *params,
- int *hasext)
+static size_t image_headersz_v1(int *hasext)
{
struct image_cfg_element *binarye;
size_t headersz;
- int ret;
/*
* Calculate the size of the header and the size of the
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
+ int ret;
struct stat s;
ret = stat(binarye->binary.file, &s);
*hasext = 1;
}
+#if defined(CONFIG_KWB_SECURE)
+ if (image_get_csk_index() >= 0) {
+ headersz += sizeof(struct secure_hdr_v1);
+ if (hasext)
+ *hasext = 1;
+ }
+#endif
+
#if defined(CONFIG_SYS_U_BOOT_OFFS)
if (headersz > CONFIG_SYS_U_BOOT_OFFS) {
- fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n");
+ fprintf(stderr,
+ "Error: Image header (incl. SPL image) too big!\n");
fprintf(stderr, "header=0x%x CONFIG_SYS_U_BOOT_OFFS=0x%x!\n",
(int)headersz, CONFIG_SYS_U_BOOT_OFFS);
fprintf(stderr, "Increase CONFIG_SYS_U_BOOT_OFFS!\n");
return 0;
- } else {
- headersz = CONFIG_SYS_U_BOOT_OFFS;
}
+
+ headersz = CONFIG_SYS_U_BOOT_OFFS;
#endif
/*
return ALIGN_SUP(headersz, 4096);
}
+int add_binary_header_v1(uint8_t *cur)
+{
+ struct image_cfg_element *binarye;
+ struct opt_hdr_v1 *hdr = (struct opt_hdr_v1 *)cur;
+ uint32_t *args;
+ size_t binhdrsz;
+ struct stat s;
+ int argi;
+ FILE *bin;
+ int ret;
+
+ binarye = image_find_option(IMAGE_CFG_BINARY);
+
+ if (!binarye)
+ return 0;
+
+ hdr->headertype = OPT_HDR_V1_BINARY_TYPE;
+
+ bin = fopen(binarye->binary.file, "r");
+ if (!bin) {
+ fprintf(stderr, "Cannot open binary file %s\n",
+ binarye->binary.file);
+ return -1;
+ }
+
+ fstat(fileno(bin), &s);
+
+ binhdrsz = sizeof(struct opt_hdr_v1) +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t) +
+ s.st_size;
+
+ /*
+ * The size includes the binary image size, rounded
+ * up to a 4-byte boundary. Plus 4 bytes for the
+ * next-header byte and 3-byte alignment at the end.
+ */
+ binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
+ hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
+ hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
+
+ cur += sizeof(struct opt_hdr_v1);
+
+ args = (uint32_t *)cur;
+ *args = cpu_to_le32(binarye->binary.nargs);
+ args++;
+ for (argi = 0; argi < binarye->binary.nargs; argi++)
+ args[argi] = cpu_to_le32(binarye->binary.args[argi]);
+
+ cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
+
+ ret = fread(cur, s.st_size, 1, bin);
+ if (ret != 1) {
+ fprintf(stderr,
+ "Could not read binary image %s\n",
+ binarye->binary.file);
+ return -1;
+ }
+
+ fclose(bin);
+
+ cur += ALIGN_SUP(s.st_size, 4);
+
+ /*
+ * For now, we don't support more than one binary
+ * header, and no other header types are
+ * supported. So, the binary header is necessarily the
+ * last one
+ */
+ *((uint32_t *)cur) = 0x00000000;
+
+ cur += sizeof(uint32_t);
+
+ return 0;
+}
+
+#if defined(CONFIG_KWB_SECURE)
+
+int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
+{
+ FILE *hashf;
+ int res;
+
+ hashf = fopen("pub_kak_hash.txt", "w");
+
+ res = kwb_export_pubkey(kak, &secure_hdr->kak, hashf, "KAK");
+
+ fclose(hashf);
+
+ return res < 0 ? 1 : 0;
+}
+
+int kwb_sign_csk_with_kak(struct image_tool_params *params,
+ struct secure_hdr_v1 *secure_hdr, RSA *csk)
+{
+ RSA *kak = NULL;
+ RSA *kak_pub = NULL;
+ int csk_idx = image_get_csk_index();
+ struct sig_v1 tmp_sig;
+
+ if (csk_idx >= 16) {
+ fprintf(stderr, "Invalid CSK index %d\n", csk_idx);
+ return 1;
+ }
+
+ if (kwb_load_kak(params, &kak) < 0)
+ return 1;
+
+ if (export_pub_kak_hash(kak, secure_hdr))
+ return 1;
+
+ if (kwb_import_pubkey(&kak_pub, &secure_hdr->kak, "KAK") < 0)
+ return 1;
+
+ if (kwb_export_pubkey(csk, &secure_hdr->csk[csk_idx], NULL, "CSK") < 0)
+ return 1;
+
+ if (kwb_sign_and_verify(kak, &secure_hdr->csk,
+ sizeof(secure_hdr->csk) +
+ sizeof(secure_hdr->csksig),
+ &tmp_sig, "CSK") < 0)
+ return 1;
+
+ if (kwb_verify(kak_pub, &secure_hdr->csk,
+ sizeof(secure_hdr->csk) +
+ sizeof(secure_hdr->csksig),
+ &tmp_sig, "CSK (2)") < 0)
+ return 1;
+
+ secure_hdr->csksig = tmp_sig;
+
+ return 0;
+}
+
+int add_secure_header_v1(struct image_tool_params *params, uint8_t *ptr,
+ int payloadsz, size_t headersz, uint8_t *image,
+ struct secure_hdr_v1 *secure_hdr)
+{
+ struct image_cfg_element *e_jtagdelay;
+ struct image_cfg_element *e_boxid;
+ struct image_cfg_element *e_flashid;
+ RSA *csk = NULL;
+ unsigned char *image_ptr;
+ size_t image_size;
+ struct sig_v1 tmp_sig;
+ bool specialized_img = image_get_spezialized_img();
+
+ kwb_msg("Create secure header content\n");
+
+ e_jtagdelay = image_find_option(IMAGE_CFG_JTAG_DELAY);
+ e_boxid = image_find_option(IMAGE_CFG_BOX_ID);
+ e_flashid = image_find_option(IMAGE_CFG_FLASH_ID);
+
+ if (kwb_load_csk(params, &csk) < 0)
+ return 1;
+
+ secure_hdr->headertype = OPT_HDR_V1_SECURE_TYPE;
+ secure_hdr->headersz_msb = 0;
+ secure_hdr->headersz_lsb = cpu_to_le16(sizeof(struct secure_hdr_v1));
+ if (e_jtagdelay)
+ secure_hdr->jtag_delay = e_jtagdelay->jtag_delay;
+ if (e_boxid && specialized_img)
+ secure_hdr->boxid = cpu_to_le32(e_boxid->boxid);
+ if (e_flashid && specialized_img)
+ secure_hdr->flashid = cpu_to_le32(e_flashid->flashid);
+
+ if (kwb_sign_csk_with_kak(params, secure_hdr, csk))
+ return 1;
+
+ image_ptr = ptr + headersz;
+ image_size = payloadsz - headersz;
+
+ if (kwb_sign_and_verify(csk, image_ptr, image_size,
+ &secure_hdr->imgsig, "image") < 0)
+ return 1;
+
+ if (kwb_sign_and_verify(csk, image, headersz, &tmp_sig, "header") < 0)
+ return 1;
+
+ secure_hdr->hdrsig = tmp_sig;
+
+ kwb_dump_fuse_cmds(secure_hdr);
+
+ return 0;
+}
+#endif
+
static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
- int payloadsz)
+ uint8_t *ptr, int payloadsz)
{
- struct image_cfg_element *e, *binarye;
+ struct image_cfg_element *e;
struct main_hdr_v1 *main_hdr;
+#if defined(CONFIG_KWB_SECURE)
+ struct secure_hdr_v1 *secure_hdr = NULL;
+#endif
size_t headersz;
- void *image, *cur;
+ uint8_t *image, *cur;
int hasext = 0;
- int ret;
+ uint8_t *next_ext = NULL;
/*
* Calculate the size of the header and the size of the
* payload
*/
- headersz = image_headersz_v1(params, &hasext);
+ headersz = image_headersz_v1(&hasext);
if (headersz == 0)
return NULL;
memset(image, 0, headersz);
- cur = main_hdr = image;
+ main_hdr = (struct main_hdr_v1 *)image;
+ cur = image;
cur += sizeof(struct main_hdr_v1);
+ next_ext = &main_hdr->ext;
/* Fill the main header */
main_hdr->blocksize =
cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
- main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->destaddr = cpu_to_le32(params->addr)
+ - sizeof(image_header_t);
main_hdr->execaddr = cpu_to_le32(params->ep);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
if (e)
main_hdr->flags = e->debug ? 0x1 : 0;
- binarye = image_find_option(IMAGE_CFG_BINARY);
- if (binarye) {
- struct opt_hdr_v1 *hdr = cur;
- uint32_t *args;
- size_t binhdrsz;
- struct stat s;
- int argi;
- FILE *bin;
+#if defined(CONFIG_KWB_SECURE)
+ if (image_get_csk_index() >= 0) {
+ /*
+ * only reserve the space here; we fill the header later since
+ * we need the header to be complete to compute the signatures
+ */
+ secure_hdr = (struct secure_hdr_v1 *)cur;
+ cur += sizeof(struct secure_hdr_v1);
+ next_ext = &secure_hdr->next;
+ }
+#endif
+ *next_ext = 1;
- hdr->headertype = OPT_HDR_V1_BINARY_TYPE;
+ if (add_binary_header_v1(cur))
+ return NULL;
- bin = fopen(binarye->binary.file, "r");
- if (!bin) {
- fprintf(stderr, "Cannot open binary file %s\n",
- binarye->binary.file);
- return NULL;
- }
+#if defined(CONFIG_KWB_SECURE)
+ if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz,
+ headersz, image, secure_hdr))
+ return NULL;
+#endif
- fstat(fileno(bin), &s);
+ /* Calculate and set the header checksum */
+ main_hdr->checksum = image_checksum8(main_hdr, headersz);
- binhdrsz = sizeof(struct opt_hdr_v1) +
- (binarye->binary.nargs + 2) * sizeof(uint32_t) +
- s.st_size;
+ *imagesz = headersz;
+ return image;
+}
- /*
- * The size includes the binary image size, rounded
- * up to a 4-byte boundary. Plus 4 bytes for the
- * next-header byte and 3-byte alignment at the end.
- */
- binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
- hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
- hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
+int recognize_keyword(char *keyword)
+{
+ int kw_id;
- cur += sizeof(struct opt_hdr_v1);
+ for (kw_id = 1; kw_id < IMAGE_CFG_COUNT; ++kw_id)
+ if (!strcmp(keyword, id_strs[kw_id]))
+ return kw_id;
- args = cur;
- *args = cpu_to_le32(binarye->binary.nargs);
- args++;
- for (argi = 0; argi < binarye->binary.nargs; argi++)
- args[argi] = cpu_to_le32(binarye->binary.args[argi]);
+ return 0;
+}
- cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
+static int image_create_config_parse_oneline(char *line,
+ struct image_cfg_element *el)
+{
+ char *keyword, *saveptr, *value1, *value2;
+ char delimiters[] = " \t";
+ int keyword_id, ret, argi;
+ char *unknown_msg = "Ignoring unknown line '%s'\n";
- ret = fread(cur, s.st_size, 1, bin);
- if (ret != 1) {
- fprintf(stderr,
- "Could not read binary image %s\n",
- binarye->binary.file);
- return NULL;
- }
+ keyword = strtok_r(line, delimiters, &saveptr);
+ keyword_id = recognize_keyword(keyword);
- fclose(bin);
+ if (!keyword_id) {
+ fprintf(stderr, unknown_msg, line);
+ return 0;
+ }
- cur += ALIGN_SUP(s.st_size, 4);
+ el->type = keyword_id;
- /*
- * For now, we don't support more than one binary
- * header, and no other header types are
- * supported. So, the binary header is necessarily the
- * last one
- */
- *((uint32_t *)cur) = 0x00000000;
+ value1 = strtok_r(NULL, delimiters, &saveptr);
- cur += sizeof(uint32_t);
+ if (!value1) {
+ fprintf(stderr, "Parameter missing in line '%s'\n", line);
+ return -1;
}
- /* Calculate and set the header checksum */
- main_hdr->checksum = image_checksum8(main_hdr, headersz);
-
- *imagesz = headersz;
- return image;
-}
+ switch (keyword_id) {
+ case IMAGE_CFG_VERSION:
+ el->version = atoi(value1);
+ break;
+ case IMAGE_CFG_BOOT_FROM:
+ ret = image_boot_mode_id(value1);
-static int image_create_config_parse_oneline(char *line,
- struct image_cfg_element *el)
-{
- char *keyword, *saveptr;
- char deliminiters[] = " \t";
-
- keyword = strtok_r(line, deliminiters, &saveptr);
- if (!strcmp(keyword, "VERSION")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- el->type = IMAGE_CFG_VERSION;
- el->version = atoi(value);
- } else if (!strcmp(keyword, "BOOT_FROM")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- int ret = image_boot_mode_id(value);
if (ret < 0) {
- fprintf(stderr,
- "Invalid boot media '%s'\n", value);
+ fprintf(stderr, "Invalid boot media '%s'\n", value1);
return -1;
}
- el->type = IMAGE_CFG_BOOT_FROM;
el->bootfrom = ret;
- } else if (!strcmp(keyword, "NAND_BLKSZ")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- el->type = IMAGE_CFG_NAND_BLKSZ;
- el->nandblksz = strtoul(value, NULL, 16);
- } else if (!strcmp(keyword, "NAND_BADBLK_LOCATION")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- el->type = IMAGE_CFG_NAND_BADBLK_LOCATION;
- el->nandbadblklocation =
- strtoul(value, NULL, 16);
- } else if (!strcmp(keyword, "NAND_ECC_MODE")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- int ret = image_nand_ecc_mode_id(value);
+ break;
+ case IMAGE_CFG_NAND_BLKSZ:
+ el->nandblksz = strtoul(value1, NULL, 16);
+ break;
+ case IMAGE_CFG_NAND_BADBLK_LOCATION:
+ el->nandbadblklocation = strtoul(value1, NULL, 16);
+ break;
+ case IMAGE_CFG_NAND_ECC_MODE:
+ ret = image_nand_ecc_mode_id(value1);
+
if (ret < 0) {
- fprintf(stderr,
- "Invalid NAND ECC mode '%s'\n", value);
+ fprintf(stderr, "Invalid NAND ECC mode '%s'\n", value1);
return -1;
}
- el->type = IMAGE_CFG_NAND_ECC_MODE;
el->nandeccmode = ret;
- } else if (!strcmp(keyword, "NAND_PAGE_SIZE")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- el->type = IMAGE_CFG_NAND_PAGESZ;
- el->nandpagesz = strtoul(value, NULL, 16);
- } else if (!strcmp(keyword, "BINARY")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- int argi = 0;
-
- el->type = IMAGE_CFG_BINARY;
- el->binary.file = strdup(value);
+ break;
+ case IMAGE_CFG_NAND_PAGESZ:
+ el->nandpagesz = strtoul(value1, NULL, 16);
+ break;
+ case IMAGE_CFG_BINARY:
+ argi = 0;
+
+ el->binary.file = strdup(value1);
while (1) {
- value = strtok_r(NULL, deliminiters, &saveptr);
+ char *value = strtok_r(NULL, delimiters, &saveptr);
+
if (!value)
break;
el->binary.args[argi] = strtoul(value, NULL, 16);
argi++;
if (argi >= BINARY_MAX_ARGS) {
fprintf(stderr,
- "Too many argument for binary\n");
+ "Too many arguments for BINARY\n");
return -1;
}
}
el->binary.nargs = argi;
- } else if (!strcmp(keyword, "DATA")) {
- char *value1 = strtok_r(NULL, deliminiters, &saveptr);
- char *value2 = strtok_r(NULL, deliminiters, &saveptr);
+ break;
+ case IMAGE_CFG_DATA:
+ value2 = strtok_r(NULL, delimiters, &saveptr);
if (!value1 || !value2) {
fprintf(stderr,
return -1;
}
- el->type = IMAGE_CFG_DATA;
el->regdata.raddr = strtoul(value1, NULL, 16);
el->regdata.rdata = strtoul(value2, NULL, 16);
- } else if (!strcmp(keyword, "BAUDRATE")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- el->type = IMAGE_CFG_BAUDRATE;
- el->baudrate = strtoul(value, NULL, 10);
- } else if (!strcmp(keyword, "DEBUG")) {
- char *value = strtok_r(NULL, deliminiters, &saveptr);
- el->type = IMAGE_CFG_DEBUG;
- el->debug = strtoul(value, NULL, 10);
- } else {
- fprintf(stderr, "Ignoring unknown line '%s'\n", line);
+ break;
+ case IMAGE_CFG_BAUDRATE:
+ el->baudrate = strtoul(value1, NULL, 10);
+ break;
+ case IMAGE_CFG_DEBUG:
+ el->debug = strtoul(value1, NULL, 10);
+ break;
+ case IMAGE_CFG_KAK:
+ el->key_name = strdup(value1);
+ break;
+ case IMAGE_CFG_CSK:
+ el->key_name = strdup(value1);
+ break;
+ case IMAGE_CFG_CSK_INDEX:
+ el->csk_idx = strtol(value1, NULL, 0);
+ break;
+ case IMAGE_CFG_JTAG_DELAY:
+ el->jtag_delay = strtoul(value1, NULL, 0);
+ break;
+ case IMAGE_CFG_BOX_ID:
+ el->boxid = strtoul(value1, NULL, 0);
+ break;
+ case IMAGE_CFG_FLASH_ID:
+ el->flashid = strtoul(value1, NULL, 0);
+ break;
+ case IMAGE_CFG_SEC_SPECIALIZED_IMG:
+ el->sec_specialized_img = true;
+ break;
+ case IMAGE_CFG_SEC_COMMON_IMG:
+ el->sec_specialized_img = false;
+ break;
+ case IMAGE_CFG_SEC_BOOT_DEV:
+ el->sec_boot_dev = strtoul(value1, NULL, 0);
+ break;
+ case IMAGE_CFG_SEC_FUSE_DUMP:
+ el->name = strdup(value1);
+ break;
+ default:
+ fprintf(stderr, unknown_msg, line);
}
return 0;
break;
case 1:
- image = image_create_v1(&headersz, params, sbuf->st_size);
+ image = image_create_v1(&headersz, params, ptr, sbuf->st_size);
break;
default:
{
if (type == IH_TYPE_KWBIMAGE)
return EXIT_SUCCESS;
- else
- return EXIT_FAILURE;
+
+ return EXIT_FAILURE;
}
static int kwbimage_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
struct main_hdr_v0 *main_hdr;
- struct ext_hdr_v0 *ext_hdr;
uint8_t checksum;
- main_hdr = (void *)ptr;
+ main_hdr = (struct main_hdr_v0 *)ptr;
checksum = image_checksum8(ptr,
sizeof(struct main_hdr_v0)
- sizeof(uint8_t));
/* Only version 0 extended header has checksum */
if (image_version((void *)ptr) == 0) {
- ext_hdr = (void *)ptr + sizeof(struct main_hdr_v0);
+ struct ext_hdr_v0 *ext_hdr;
+
+ ext_hdr = (struct ext_hdr_v0 *)
+ (ptr + sizeof(struct main_hdr_v0));
checksum = image_checksum8(ext_hdr,
sizeof(struct ext_hdr_v0)
- sizeof(uint8_t));
alloc_len = sizeof(struct main_hdr_v0) +
sizeof(struct ext_hdr_v0);
} else {
- alloc_len = image_headersz_v1(params, NULL);
+ alloc_len = image_headersz_v1(NULL);
}
hdr = malloc(alloc_len);
static int kwbimage_check_params(struct image_tool_params *params)
{
if (!strlen(params->imagename)) {
- fprintf(stderr, "Error:%s - Configuration file not specified, "
- "it is needed for kwbimage generation\n",
- params->cmdname);
+ char *msg = "Configuration file for kwbimage creation omitted";
+
+ fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
return CFG_INVALID;
}
char data[0];
};
+/*
+ * Public Key data in DER format
+ */
+struct pubkey_der_v1 {
+ uint8_t key[524];
+};
+
+/*
+ * Signature (RSA 2048)
+ */
+struct sig_v1 {
+ uint8_t sig[256];
+};
+
+/*
+ * Structure of secure header (Armada 38x)
+ */
+struct secure_hdr_v1 {
+ uint8_t headertype; /* 0x0 */
+ uint8_t headersz_msb; /* 0x1 */
+ uint16_t headersz_lsb; /* 0x2 - 0x3 */
+ uint32_t reserved1; /* 0x4 - 0x7 */
+ struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
+ uint8_t jtag_delay; /* 0x214 */
+ uint8_t reserved2; /* 0x215 */
+ uint16_t reserved3; /* 0x216 - 0x217 */
+ uint32_t boxid; /* 0x218 - 0x21B */
+ uint32_t flashid; /* 0x21C - 0x21F */
+ struct sig_v1 hdrsig; /* 0x220 - 0x31F */
+ struct sig_v1 imgsig; /* 0x320 - 0x41F */
+ struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
+ struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
+ uint8_t next; /* 0x25E0 */
+ uint8_t reserved4; /* 0x25E1 */
+ uint16_t reserved5; /* 0x25E2 - 0x25E3 */
+};
+
/*
* Various values for the opt_hdr_v1->headertype field, describing the
* different types of optional headers. The "secure" header contains
projects / people / ms / u-boot.git / commitdiff
