Add ET131x ethernet driver.
[people/pmueller/ipfire-2.x.git] / src / et131x / et1310_mac.c
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_mac.c - All code and routines pertaining to the MAC
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #include "et131x_version.h"
59 #include "et131x_debug.h"
60 #include "et131x_defs.h"
61
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
66
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
74 #include <linux/in.h>
75 #include <linux/delay.h>
76 #include <asm/io.h>
77 #include <asm/system.h>
78 #include <asm/bitops.h>
79
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/crc32.h>
86
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
90 #include "et1310_mac.h"
91
92 #include "et131x_adapter.h"
93 #include "et131x_initpci.h"
94
95 /* Data for debugging facilities */
96 #ifdef CONFIG_ET131X_DEBUG
97 extern dbg_info_t *et131x_dbginfo;
98 #endif /* CONFIG_ET131X_DEBUG */
99
100 /**
101 * ConfigMacRegs1 - Initialize the first part of MAC regs
102 * @pAdpater: pointer to our adapter structure
103 */
104 void ConfigMACRegs1(struct et131x_adapter *pAdapter)
105 {
106 struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
107 MAC_STATION_ADDR1_t station1;
108 MAC_STATION_ADDR2_t station2;
109 MAC_IPG_t ipg;
110 MAC_HFDP_t hfdp;
111 MII_MGMT_CFG_t mii_mgmt_cfg;
112
113 DBG_ENTER(et131x_dbginfo);
114
115 /* First we need to reset everything. Write to MAC configuration
116 * register 1 to perform reset.
117 */
118 writel(0xC00F0000, &pMac->cfg1.value);
119
120 /* Next lets configure the MAC Inter-packet gap register */
121 ipg.bits.non_B2B_ipg_1 = 0x38; // 58d
122 ipg.bits.non_B2B_ipg_2 = 0x58; // 88d
123 ipg.bits.min_ifg_enforce = 0x50; // 80d
124 ipg.bits.B2B_ipg = 0x60; // 96d
125 writel(ipg.value, &pMac->ipg.value);
126
127 /* Next lets configure the MAC Half Duplex register */
128 hfdp.bits.alt_beb_trunc = 0xA;
129 hfdp.bits.alt_beb_enable = 0x0;
130 hfdp.bits.bp_no_backoff = 0x0;
131 hfdp.bits.no_backoff = 0x0;
132 hfdp.bits.excess_defer = 0x1;
133 hfdp.bits.rexmit_max = 0xF;
134 hfdp.bits.coll_window = 0x37; // 55d
135 writel(hfdp.value, &pMac->hfdp.value);
136
137 /* Next lets configure the MAC Interface Control register */
138 writel(0, &pMac->if_ctrl.value);
139
140 /* Let's move on to setting up the mii managment configuration */
141 mii_mgmt_cfg.bits.reset_mii_mgmt = 0;
142 mii_mgmt_cfg.bits.scan_auto_incremt = 0;
143 mii_mgmt_cfg.bits.preamble_suppress = 0;
144 mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7;
145 writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value);
146
147 /* Next lets configure the MAC Station Address register. These
148 * values are read from the EEPROM during initialization and stored
149 * in the adapter structure. We write what is stored in the adapter
150 * structure to the MAC Station Address registers high and low. This
151 * station address is used for generating and checking pause control
152 * packets.
153 */
154 station2.bits.Octet1 = pAdapter->CurrentAddress[0];
155 station2.bits.Octet2 = pAdapter->CurrentAddress[1];
156 station1.bits.Octet3 = pAdapter->CurrentAddress[2];
157 station1.bits.Octet4 = pAdapter->CurrentAddress[3];
158 station1.bits.Octet5 = pAdapter->CurrentAddress[4];
159 station1.bits.Octet6 = pAdapter->CurrentAddress[5];
160 writel(station1.value, &pMac->station_addr_1.value);
161 writel(station2.value, &pMac->station_addr_2.value);
162
163 /* Max ethernet packet in bytes that will passed by the mac without
164 * being truncated. Allow the MAC to pass 4 more than our max packet
165 * size. This is 4 for the Ethernet CRC.
166 *
167 * Packets larger than (RegistryJumboPacket) that do not contain a
168 * VLAN ID will be dropped by the Rx function.
169 */
170 writel(pAdapter->RegistryJumboPacket + 4, &pMac->max_fm_len.value);
171
172 /* clear out MAC config reset */
173 writel(0, &pMac->cfg1.value);
174
175 DBG_LEAVE(et131x_dbginfo);
176 }
177
178 /**
179 * ConfigMacRegs2 - Initialize the second part of MAC regs
180 * @pAdpater: pointer to our adapter structure
181 */
182 void ConfigMACRegs2(struct et131x_adapter *pAdapter)
183 {
184 int32_t delay = 0;
185 struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
186 MAC_CFG1_t cfg1;
187 MAC_CFG2_t cfg2;
188 MAC_IF_CTRL_t ifctrl;
189 TXMAC_CTL_t ctl;
190
191 DBG_ENTER(et131x_dbginfo);
192
193 ctl.value = readl(&pAdapter->CSRAddress->txmac.ctl.value);
194 cfg1.value = readl(&pMac->cfg1.value);
195 cfg2.value = readl(&pMac->cfg2.value);
196 ifctrl.value = readl(&pMac->if_ctrl.value);
197
198 if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
199 cfg2.bits.if_mode = 0x2;
200 ifctrl.bits.phy_mode = 0x0;
201 } else {
202 cfg2.bits.if_mode = 0x1;
203 ifctrl.bits.phy_mode = 0x1;
204 }
205
206 /* We need to enable Rx/Tx */
207 cfg1.bits.rx_enable = 0x1;
208 cfg1.bits.tx_enable = 0x1;
209
210 /* Set up flow control */
211 cfg1.bits.tx_flow = 0x1;
212
213 if ((pAdapter->FlowControl == RxOnly) ||
214 (pAdapter->FlowControl == Both)) {
215 cfg1.bits.rx_flow = 0x1;
216 } else {
217 cfg1.bits.rx_flow = 0x0;
218 }
219
220 /* Initialize loop back to off */
221 cfg1.bits.loop_back = 0;
222
223 writel(cfg1.value, &pMac->cfg1.value);
224
225 /* Now we need to initialize the MAC Configuration 2 register */
226 cfg2.bits.preamble_len = 0x7;
227 cfg2.bits.huge_frame = 0x0;
228 /* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check
229 * the frame's length field to ensure it matches the actual data
230 * field length. Clear this bit if no length field checking is
231 * desired. Its default is 0.
232 */
233 cfg2.bits.len_check = 0x1;
234
235 if (pAdapter->RegistryPhyLoopbk == false) {
236 cfg2.bits.pad_crc = 0x1;
237 cfg2.bits.crc_enable = 0x1;
238 } else {
239 cfg2.bits.pad_crc = 0;
240 cfg2.bits.crc_enable = 0;
241 }
242
243 /* 1 - full duplex, 0 - half-duplex */
244 cfg2.bits.full_duplex = pAdapter->uiDuplexMode;
245 ifctrl.bits.ghd_mode = !pAdapter->uiDuplexMode;
246
247 writel(ifctrl.value, &pMac->if_ctrl.value);
248 writel(cfg2.value, &pMac->cfg2.value);
249
250 do {
251 udelay(10);
252 delay++;
253 cfg1.value = readl(&pMac->cfg1.value);
254 } while ((!cfg1.bits.syncd_rx_en ||
255 !cfg1.bits.syncd_tx_en) &&
256 delay < 100);
257
258 if (delay == 100) {
259 DBG_ERROR(et131x_dbginfo,
260 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
261 cfg1.value);
262 }
263
264 DBG_TRACE(et131x_dbginfo,
265 "Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
266 pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,
267 readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
268 readl(&pMac->if_ctrl.value));
269
270 /* Enable TXMAC */
271 ctl.bits.txmac_en = 0x1;
272 ctl.bits.fc_disable = 0x1;
273 writel(ctl.value, &pAdapter->CSRAddress->txmac.ctl.value);
274
275 /* Ready to start the RXDMA/TXDMA engine */
276 if (!MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER)) {
277 et131x_rx_dma_enable(pAdapter);
278 et131x_tx_dma_enable(pAdapter);
279 } else {
280 DBG_WARNING(et131x_dbginfo,
281 "Didn't enable Rx/Tx due to low-power mode\n");
282 }
283
284 DBG_LEAVE(et131x_dbginfo);
285 }
286
287 void ConfigRxMacRegs(struct et131x_adapter *pAdapter)
288 {
289 struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac;
290 RXMAC_WOL_SA_LO_t sa_lo;
291 RXMAC_WOL_SA_HI_t sa_hi;
292 RXMAC_PF_CTRL_t pf_ctrl = { 0 };
293
294 DBG_ENTER(et131x_dbginfo);
295
296 /* Disable the MAC while it is being configured (also disable WOL) */
297 writel(0x8, &pRxMac->ctrl.value);
298
299 /* Initialize WOL to disabled. */
300 writel(0, &pRxMac->crc0.value);
301 writel(0, &pRxMac->crc12.value);
302 writel(0, &pRxMac->crc34.value);
303
304 /* We need to set the WOL mask0 - mask4 next. We initialize it to
305 * its default Values of 0x00000000 because there are not WOL masks
306 * as of this time.
307 */
308 writel(0, &pRxMac->mask0_word0);
309 writel(0, &pRxMac->mask0_word1);
310 writel(0, &pRxMac->mask0_word2);
311 writel(0, &pRxMac->mask0_word3);
312
313 writel(0, &pRxMac->mask1_word0);
314 writel(0, &pRxMac->mask1_word1);
315 writel(0, &pRxMac->mask1_word2);
316 writel(0, &pRxMac->mask1_word3);
317
318 writel(0, &pRxMac->mask2_word0);
319 writel(0, &pRxMac->mask2_word1);
320 writel(0, &pRxMac->mask2_word2);
321 writel(0, &pRxMac->mask2_word3);
322
323 writel(0, &pRxMac->mask3_word0);
324 writel(0, &pRxMac->mask3_word1);
325 writel(0, &pRxMac->mask3_word2);
326 writel(0, &pRxMac->mask3_word3);
327
328 writel(0, &pRxMac->mask4_word0);
329 writel(0, &pRxMac->mask4_word1);
330 writel(0, &pRxMac->mask4_word2);
331 writel(0, &pRxMac->mask4_word3);
332
333 /* Lets setup the WOL Source Address */
334 sa_lo.bits.sa3 = pAdapter->CurrentAddress[2];
335 sa_lo.bits.sa4 = pAdapter->CurrentAddress[3];
336 sa_lo.bits.sa5 = pAdapter->CurrentAddress[4];
337 sa_lo.bits.sa6 = pAdapter->CurrentAddress[5];
338 writel(sa_lo.value, &pRxMac->sa_lo.value);
339
340 sa_hi.bits.sa1 = pAdapter->CurrentAddress[0];
341 sa_hi.bits.sa2 = pAdapter->CurrentAddress[1];
342 writel(sa_hi.value, &pRxMac->sa_hi.value);
343
344 /* Disable all Packet Filtering */
345 writel(0, &pRxMac->pf_ctrl.value);
346
347 /* Let's initialize the Unicast Packet filtering address */
348 if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
349 SetupDeviceForUnicast(pAdapter);
350 pf_ctrl.bits.filter_uni_en = 1;
351 } else {
352 writel(0, &pRxMac->uni_pf_addr1.value);
353 writel(0, &pRxMac->uni_pf_addr2.value);
354 writel(0, &pRxMac->uni_pf_addr3.value);
355 }
356
357 /* Let's initialize the Multicast hash */
358 if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
359 pf_ctrl.bits.filter_multi_en = 0;
360 } else {
361 pf_ctrl.bits.filter_multi_en = 1;
362 SetupDeviceForMulticast(pAdapter);
363 }
364
365 /* Runt packet filtering. Didn't work in version A silicon. */
366 pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
367 pf_ctrl.bits.filter_frag_en = 1;
368
369 if (pAdapter->RegistryJumboPacket > 8192) {
370 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
371
372 /* In order to transmit jumbo packets greater than 8k, the
373 * FIFO between RxMAC and RxDMA needs to be reduced in size
374 * to (16k - Jumbo packet size). In order to implement this,
375 * we must use "cut through" mode in the RxMAC, which chops
376 * packets down into segments which are (max_size * 16). In
377 * this case we selected 256 bytes, since this is the size of
378 * the PCI-Express TLP's that the 1310 uses.
379 */
380 mcif_ctrl_max_seg.bits.seg_en = 0x1;
381 mcif_ctrl_max_seg.bits.fc_en = 0x0;
382 mcif_ctrl_max_seg.bits.max_size = 0x10;
383
384 writel(mcif_ctrl_max_seg.value,
385 &pRxMac->mcif_ctrl_max_seg.value);
386 } else {
387 writel(0, &pRxMac->mcif_ctrl_max_seg.value);
388 }
389
390 /* Initialize the MCIF water marks */
391 writel(0, &pRxMac->mcif_water_mark.value);
392
393 /* Initialize the MIF control */
394 writel(0, &pRxMac->mif_ctrl.value);
395
396 /* Initialize the Space Available Register */
397 writel(0, &pRxMac->space_avail.value);
398
399 /* Initialize the the mif_ctrl register
400 * bit 3: Receive code error. One or more nibbles were signaled as
401 * errors during the reception of the packet. Clear this
402 * bit in Gigabit, set it in 100Mbit. This was derived
403 * experimentally at UNH.
404 * bit 4: Receive CRC error. The packet's CRC did not match the
405 * internally generated CRC.
406 * bit 5: Receive length check error. Indicates that frame length
407 * field value in the packet does not match the actual data
408 * byte length and is not a type field.
409 * bit 16: Receive frame truncated.
410 * bit 17: Drop packet enable
411 */
412 if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) {
413 writel(0x30038, &pRxMac->mif_ctrl.value);
414 } else {
415 writel(0x30030, &pRxMac->mif_ctrl.value);
416 }
417
418 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
419 * filter is always enabled since it is where the runt packets are
420 * supposed to be dropped. For version A silicon, runt packet
421 * dropping doesn't work, so it is disabled in the pf_ctrl register,
422 * but we still leave the packet filter on.
423 */
424 writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
425 writel(0x9, &pRxMac->ctrl.value);
426
427 DBG_LEAVE(et131x_dbginfo);
428 }
429
430 void ConfigTxMacRegs(struct et131x_adapter *pAdapter)
431 {
432 struct _TXMAC_t __iomem *pTxMac = &pAdapter->CSRAddress->txmac;
433 TXMAC_CF_PARAM_t Local;
434
435 DBG_ENTER(et131x_dbginfo);
436
437 /* We need to update the Control Frame Parameters
438 * cfpt - control frame pause timer set to 64 (0x40)
439 * cfep - control frame extended pause timer set to 0x0
440 */
441 if (pAdapter->FlowControl == None) {
442 writel(0, &pTxMac->cf_param.value);
443 } else {
444 Local.bits.cfpt = 0x40;
445 Local.bits.cfep = 0x0;
446 writel(Local.value, &pTxMac->cf_param.value);
447 }
448
449 DBG_LEAVE(et131x_dbginfo);
450 }
451
452 void ConfigMacStatRegs(struct et131x_adapter *pAdapter)
453 {
454 struct _MAC_STAT_t __iomem *pDevMacStat =
455 &pAdapter->CSRAddress->macStat;
456
457 DBG_ENTER(et131x_dbginfo);
458
459 /* Next we need to initialize all the MAC_STAT registers to zero on
460 * the device.
461 */
462 writel(0, &pDevMacStat->RFcs);
463 writel(0, &pDevMacStat->RAln);
464 writel(0, &pDevMacStat->RFlr);
465 writel(0, &pDevMacStat->RDrp);
466 writel(0, &pDevMacStat->RCde);
467 writel(0, &pDevMacStat->ROvr);
468 writel(0, &pDevMacStat->RFrg);
469
470 writel(0, &pDevMacStat->TScl);
471 writel(0, &pDevMacStat->TDfr);
472 writel(0, &pDevMacStat->TMcl);
473 writel(0, &pDevMacStat->TLcl);
474 writel(0, &pDevMacStat->TNcl);
475 writel(0, &pDevMacStat->TOvr);
476 writel(0, &pDevMacStat->TUnd);
477
478 /* Unmask any counters that we want to track the overflow of.
479 * Initially this will be all counters. It may become clear later
480 * that we do not need to track all counters.
481 */
482 {
483 MAC_STAT_REG_1_t Carry1M = { 0xffffffff };
484
485 Carry1M.bits.rdrp = 0;
486 Carry1M.bits.rjbr = 1;
487 Carry1M.bits.rfrg = 0;
488 Carry1M.bits.rovr = 0;
489 Carry1M.bits.rund = 1;
490 Carry1M.bits.rcse = 1;
491 Carry1M.bits.rcde = 0;
492 Carry1M.bits.rflr = 0;
493 Carry1M.bits.raln = 0;
494 Carry1M.bits.rxuo = 1;
495 Carry1M.bits.rxpf = 1;
496 Carry1M.bits.rxcf = 1;
497 Carry1M.bits.rbca = 1;
498 Carry1M.bits.rmca = 1;
499 Carry1M.bits.rfcs = 0;
500 Carry1M.bits.rpkt = 1;
501 Carry1M.bits.rbyt = 1;
502 Carry1M.bits.trmgv = 1;
503 Carry1M.bits.trmax = 1;
504 Carry1M.bits.tr1k = 1;
505 Carry1M.bits.tr511 = 1;
506 Carry1M.bits.tr255 = 1;
507 Carry1M.bits.tr127 = 1;
508 Carry1M.bits.tr64 = 1;
509
510 writel(Carry1M.value, &pDevMacStat->Carry1M.value);
511 }
512
513 {
514 MAC_STAT_REG_2_t Carry2M = { 0xffffffff };
515
516 Carry2M.bits.tdrp = 1;
517 Carry2M.bits.tpfh = 1;
518 Carry2M.bits.tncl = 0;
519 Carry2M.bits.txcl = 1;
520 Carry2M.bits.tlcl = 0;
521 Carry2M.bits.tmcl = 0;
522 Carry2M.bits.tscl = 0;
523 Carry2M.bits.tedf = 1;
524 Carry2M.bits.tdfr = 0;
525 Carry2M.bits.txpf = 1;
526 Carry2M.bits.tbca = 1;
527 Carry2M.bits.tmca = 1;
528 Carry2M.bits.tpkt = 1;
529 Carry2M.bits.tbyt = 1;
530 Carry2M.bits.tfrg = 1;
531 Carry2M.bits.tund = 0;
532 Carry2M.bits.tovr = 0;
533 Carry2M.bits.txcf = 1;
534 Carry2M.bits.tfcs = 1;
535 Carry2M.bits.tjbr = 1;
536
537 writel(Carry2M.value, &pDevMacStat->Carry2M.value);
538 }
539
540 DBG_LEAVE(et131x_dbginfo);
541 }
542
543 void ConfigFlowControl(struct et131x_adapter * pAdapter)
544 {
545 if (pAdapter->uiDuplexMode == 0) {
546 pAdapter->FlowControl = None;
547 } else {
548 char RemotePause, RemoteAsyncPause;
549
550 ET1310_PhyAccessMiBit(pAdapter,
551 TRUEPHY_BIT_READ, 5, 10, &RemotePause);
552 ET1310_PhyAccessMiBit(pAdapter,
553 TRUEPHY_BIT_READ, 5, 11,
554 &RemoteAsyncPause);
555
556 if ((RemotePause == TRUEPHY_BIT_SET) &&
557 (RemoteAsyncPause == TRUEPHY_BIT_SET)) {
558 pAdapter->FlowControl = pAdapter->RegistryFlowControl;
559 } else if ((RemotePause == TRUEPHY_BIT_SET) &&
560 (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
561 if (pAdapter->RegistryFlowControl == Both) {
562 pAdapter->FlowControl = Both;
563 } else {
564 pAdapter->FlowControl = None;
565 }
566 } else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&
567 (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
568 pAdapter->FlowControl = None;
569 } else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
570 RemoteAsyncPause == TRUEPHY_SET_BIT) */
571 if (pAdapter->RegistryFlowControl == Both) {
572 pAdapter->FlowControl = RxOnly;
573 } else {
574 pAdapter->FlowControl = None;
575 }
576 }
577 }
578 }
579
580 /**
581 * UpdateMacStatHostCounters - Update the local copy of the statistics
582 * @pAdapter: pointer to the adapter structure
583 */
584 void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter)
585 {
586 struct _ce_stats_t *stats = &pAdapter->Stats;
587 struct _MAC_STAT_t __iomem *pDevMacStat =
588 &pAdapter->CSRAddress->macStat;
589
590 stats->collisions += readl(&pDevMacStat->TNcl);
591 stats->first_collision += readl(&pDevMacStat->TScl);
592 stats->tx_deferred += readl(&pDevMacStat->TDfr);
593 stats->excessive_collisions += readl(&pDevMacStat->TMcl);
594 stats->late_collisions += readl(&pDevMacStat->TLcl);
595 stats->tx_uflo += readl(&pDevMacStat->TUnd);
596 stats->max_pkt_error += readl(&pDevMacStat->TOvr);
597
598 stats->alignment_err += readl(&pDevMacStat->RAln);
599 stats->crc_err += readl(&pDevMacStat->RCde);
600 stats->norcvbuf += readl(&pDevMacStat->RDrp);
601 stats->rx_ov_flow += readl(&pDevMacStat->ROvr);
602 stats->code_violations += readl(&pDevMacStat->RFcs);
603 stats->length_err += readl(&pDevMacStat->RFlr);
604
605 stats->other_errors += readl(&pDevMacStat->RFrg);
606 }
607
608 /**
609 * HandleMacStatInterrupt
610 * @pAdapter: pointer to the adapter structure
611 *
612 * One of the MACSTAT counters has wrapped. Update the local copy of
613 * the statistics held in the adapter structure, checking the "wrap"
614 * bit for each counter.
615 */
616 void HandleMacStatInterrupt(struct et131x_adapter *pAdapter)
617 {
618 MAC_STAT_REG_1_t Carry1;
619 MAC_STAT_REG_2_t Carry2;
620
621 DBG_ENTER(et131x_dbginfo);
622
623 /* Read the interrupt bits from the register(s). These are Clear On
624 * Write.
625 */
626 Carry1.value = readl(&pAdapter->CSRAddress->macStat.Carry1.value);
627 Carry2.value = readl(&pAdapter->CSRAddress->macStat.Carry2.value);
628
629 writel(Carry1.value, &pAdapter->CSRAddress->macStat.Carry1.value);
630 writel(Carry2.value, &pAdapter->CSRAddress->macStat.Carry2.value);
631
632 /* We need to do update the host copy of all the MAC_STAT counters.
633 * For each counter, check it's overflow bit. If the overflow bit is
634 * set, then increment the host version of the count by one complete
635 * revolution of the counter. This routine is called when the counter
636 * block indicates that one of the counters has wrapped.
637 */
638 if (Carry1.bits.rfcs) {
639 pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT;
640 }
641 if (Carry1.bits.raln) {
642 pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT;
643 }
644 if (Carry1.bits.rflr) {
645 pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT;
646 }
647 if (Carry1.bits.rfrg) {
648 pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT;
649 }
650 if (Carry1.bits.rcde) {
651 pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT;
652 }
653 if (Carry1.bits.rovr) {
654 pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
655 }
656 if (Carry1.bits.rdrp) {
657 pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
658 }
659 if (Carry2.bits.tovr) {
660 pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
661 }
662 if (Carry2.bits.tund) {
663 pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
664 }
665 if (Carry2.bits.tscl) {
666 pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT;
667 }
668 if (Carry2.bits.tdfr) {
669 pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
670 }
671 if (Carry2.bits.tmcl) {
672 pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
673 }
674 if (Carry2.bits.tlcl) {
675 pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT;
676 }
677 if (Carry2.bits.tncl) {
678 pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT;
679 }
680
681 DBG_LEAVE(et131x_dbginfo);
682 }
683
684 void SetupDeviceForMulticast(struct et131x_adapter *pAdapter)
685 {
686 struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
687 uint32_t nIndex;
688 uint32_t result;
689 uint32_t hash1 = 0;
690 uint32_t hash2 = 0;
691 uint32_t hash3 = 0;
692 uint32_t hash4 = 0;
693 PM_CSR_t pm_csr;
694
695 DBG_ENTER(et131x_dbginfo);
696
697 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
698 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
699 * specified) then we should pass NO multi-cast addresses to the
700 * driver.
701 */
702 if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
703 DBG_VERBOSE(et131x_dbginfo,
704 "MULTICAST flag is set, MCCount: %d\n",
705 pAdapter->MCAddressCount);
706
707 /* Loop through our multicast array and set up the device */
708 for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) {
709 DBG_VERBOSE(et131x_dbginfo,
710 "MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
711 nIndex,
712 pAdapter->MCList[nIndex][0],
713 pAdapter->MCList[nIndex][1],
714 pAdapter->MCList[nIndex][2],
715 pAdapter->MCList[nIndex][3],
716 pAdapter->MCList[nIndex][4],
717 pAdapter->MCList[nIndex][5]);
718
719 result = ether_crc(6, pAdapter->MCList[nIndex]);
720
721 result = (result & 0x3F800000) >> 23;
722
723 if (result < 32) {
724 hash1 |= (1 << result);
725 } else if ((31 < result) && (result < 64)) {
726 result -= 32;
727 hash2 |= (1 << result);
728 } else if ((63 < result) && (result < 96)) {
729 result -= 64;
730 hash3 |= (1 << result);
731 } else {
732 result -= 96;
733 hash4 |= (1 << result);
734 }
735 }
736 }
737
738 /* Write out the new hash to the device */
739 pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
740 if (pm_csr.bits.pm_phy_sw_coma == 0) {
741 writel(hash1, &rxmac->multi_hash1);
742 writel(hash2, &rxmac->multi_hash2);
743 writel(hash3, &rxmac->multi_hash3);
744 writel(hash4, &rxmac->multi_hash4);
745 }
746
747 DBG_LEAVE(et131x_dbginfo);
748 }
749
750 void SetupDeviceForUnicast(struct et131x_adapter *pAdapter)
751 {
752 struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
753 RXMAC_UNI_PF_ADDR1_t uni_pf1;
754 RXMAC_UNI_PF_ADDR2_t uni_pf2;
755 RXMAC_UNI_PF_ADDR3_t uni_pf3;
756 PM_CSR_t pm_csr;
757
758 DBG_ENTER(et131x_dbginfo);
759
760 /* Set up unicast packet filter reg 3 to be the first two octets of
761 * the MAC address for both address
762 *
763 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
764 * MAC address for second address
765 *
766 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
767 * MAC address for first address
768 */
769 uni_pf3.bits.addr1_1 = pAdapter->CurrentAddress[0];
770 uni_pf3.bits.addr1_2 = pAdapter->CurrentAddress[1];
771 uni_pf3.bits.addr2_1 = pAdapter->CurrentAddress[0];
772 uni_pf3.bits.addr2_2 = pAdapter->CurrentAddress[1];
773
774 uni_pf2.bits.addr2_3 = pAdapter->CurrentAddress[2];
775 uni_pf2.bits.addr2_4 = pAdapter->CurrentAddress[3];
776 uni_pf2.bits.addr2_5 = pAdapter->CurrentAddress[4];
777 uni_pf2.bits.addr2_6 = pAdapter->CurrentAddress[5];
778
779 uni_pf1.bits.addr1_3 = pAdapter->CurrentAddress[2];
780 uni_pf1.bits.addr1_4 = pAdapter->CurrentAddress[3];
781 uni_pf1.bits.addr1_5 = pAdapter->CurrentAddress[4];
782 uni_pf1.bits.addr1_6 = pAdapter->CurrentAddress[5];
783
784 pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
785 if (pm_csr.bits.pm_phy_sw_coma == 0) {
786 writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
787 writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
788 writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);
789 }
790
791 DBG_LEAVE(et131x_dbginfo);
792 }