Add ET131x ethernet driver.
authorArne Fitzenreiter <arne_f@ipfire.org>
Mon, 8 Feb 2010 11:03:51 +0000 (12:03 +0100)
committerArne Fitzenreiter <arne_f@ipfire.org>
Mon, 8 Feb 2010 11:03:51 +0000 (12:03 +0100)
34 files changed:
config/rootfiles/core/37/filelists/files
lfs/et131x [new file with mode: 0644]
make.sh
src/et131x/Kconfig [new file with mode: 0644]
src/et131x/Makefile [new file with mode: 0644]
src/et131x/README [new file with mode: 0644]
src/et131x/et1310_address_map.h [new file with mode: 0644]
src/et131x/et1310_eeprom.c [new file with mode: 0644]
src/et131x/et1310_eeprom.h [new file with mode: 0644]
src/et131x/et1310_jagcore.c [new file with mode: 0644]
src/et131x/et1310_jagcore.h [new file with mode: 0644]
src/et131x/et1310_mac.c [new file with mode: 0644]
src/et131x/et1310_mac.h [new file with mode: 0644]
src/et131x/et1310_phy.c [new file with mode: 0644]
src/et131x/et1310_phy.h [new file with mode: 0644]
src/et131x/et1310_pm.c [new file with mode: 0644]
src/et131x/et1310_pm.h [new file with mode: 0644]
src/et131x/et1310_rx.c [new file with mode: 0644]
src/et131x/et1310_rx.h [new file with mode: 0644]
src/et131x/et1310_tx.c [new file with mode: 0644]
src/et131x/et1310_tx.h [new file with mode: 0644]
src/et131x/et131x_adapter.h [new file with mode: 0644]
src/et131x/et131x_config.c [new file with mode: 0644]
src/et131x/et131x_config.h [new file with mode: 0644]
src/et131x/et131x_debug.c [new file with mode: 0644]
src/et131x/et131x_debug.h [new file with mode: 0644]
src/et131x/et131x_defs.h [new file with mode: 0644]
src/et131x/et131x_initpci.c [new file with mode: 0644]
src/et131x/et131x_initpci.h [new file with mode: 0644]
src/et131x/et131x_isr.c [new file with mode: 0644]
src/et131x/et131x_isr.h [new file with mode: 0644]
src/et131x/et131x_netdev.c [new file with mode: 0644]
src/et131x/et131x_netdev.h [new file with mode: 0644]
src/et131x/et131x_version.h [new file with mode: 0644]

index f981e83..e275dd3 100644 (file)
@@ -5,4 +5,6 @@ lib/modules/2.6.27.42-ipfire/mISDN/hfcsusb.ko
 lib/modules/2.6.27.42-ipfire-xen/mISDN/hfcsusb.ko
 lib/modules/2.6.27.42-ipfire/kernel/driver/hwmon/coretemp.ko
 lib/modules/2.6.27.42-ipfire-xen/kernel/driver/hwmon/coretemp.ko
+lib/modules/2.6.27.42-ipfire/kernel/driver/net/e131x.ko
+lib/modules/2.6.27.42-ipfire-xen/kernel/driver/net/e131x.ko
 srv/web/ipfire/cgi-bin/urlfilter.cgi
diff --git a/lfs/et131x b/lfs/et131x
new file mode 100644 (file)
index 0000000..f23701b
--- /dev/null
@@ -0,0 +1,61 @@
+###############################################################################
+#                                                                             #
+# IPFire.org - A linux based firewall                                         #
+# Copyright (C) 2009  Michael Tremer & Christian Schmidt                      #
+#                                                                             #
+# This program is free software: you can redistribute it and/or modify        #
+# it under the terms of the GNU General Public License as published by        #
+# the Free Software Foundation, either version 3 of the License, or           #
+# (at your option) any later version.                                         #
+#                                                                             #
+# This program is distributed in the hope that it will be useful,             #
+# but WITHOUT ANY WARRANTY; without even the implied warranty of              #
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the               #
+# GNU General Public License for more details.                                #
+#                                                                             #
+# You should have received a copy of the GNU General Public License           #
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.       #
+#                                                                             #
+###############################################################################
+
+###############################################################################
+# Definitions
+###############################################################################
+
+include Config
+
+ifeq "$(XEN)" "1"
+       VERSUFIX = ipfire-xen
+else
+       VERSUFIX = ipfire
+endif
+
+VER        = ipfire-1
+
+THISAPP    = et131x
+DIR_APP    = $(DIR_SRC)/$(THISAPP)
+TARGET     = $(DIR_INFO)/$(THISAPP)-kmod-$(KVER)-$(VERSUFIX)
+
+###############################################################################
+# Top-level Rules
+###############################################################################
+
+install : $(TARGET)
+
+check :
+
+download :
+
+md5 :
+
+###############################################################################
+# Installation Details
+###############################################################################
+
+$(TARGET) : $(patsubst %,$(DIR_DL)/%,$(objects))
+       @$(PREBUILD)
+       @rm -rf $(DIR_APP) && cp -r $(DIR_SRC)/src/$(THISAPP) $(DIR_APP)
+       cd $(DIR_APP) && make -C /lib/modules/$(KVER)-$(VERSUFIX)/build/ SUBDIRS=$(DIR_APP) modules
+       cd $(DIR_APP) && install -m 644 et131x.ko /lib/modules/$(KVER)-$(VERSUFIX)/kernel/drivers/net 
+       @rm -rf $(DIR_APP)
+       @$(POSTBUILD)
diff --git a/make.sh b/make.sh
index 99ab986..6229cd1 100755 (executable)
--- a/make.sh
+++ b/make.sh
@@ -345,6 +345,7 @@ buildipfire() {
   ipfiremake atl2                      XEN=1
   ipfiremake hso                       XEN=1
   ipfiremake e1000e                    XEN=1
+  ipfiremake et131x                    XEN=1
   ipfiremake r8101                     XEN=1
   ipfiremake r8169                     XEN=1
   ipfiremake r8168                     XEN=1
@@ -362,6 +363,7 @@ buildipfire() {
   ipfiremake atl2
   ipfiremake hso
   ipfiremake e1000e
+  ipfiremake et131x
   ipfiremake r8101
   ipfiremake r8169
   ipfiremake r8168
diff --git a/src/et131x/Kconfig b/src/et131x/Kconfig
new file mode 100644 (file)
index 0000000..e11cf34
--- /dev/null
@@ -0,0 +1,18 @@
+config ET131X
+       tristate "Agere ET-1310 Gigabit Ethernet support"
+       depends on NETDEV_1000 && PCI
+       default n
+       ---help---
+         This driver supports Agere ET-1310 ethernet adapters.
+
+         To compile this driver as a module, choose M here. The module
+         will be called et131x.
+
+config ET131X_DEBUG
+       bool "Enable et131x debugging"
+       depends on ET131X
+       default n
+       ---help---
+         Say Y for detailed debug information.
+
+         If in doubt, say N.
diff --git a/src/et131x/Makefile b/src/et131x/Makefile
new file mode 100644 (file)
index 0000000..71640ff
--- /dev/null
@@ -0,0 +1,25 @@
+KSRC ?= /lib/modules/$(shell uname -r)/build
+
+obj-m = et131x.o
+
+et131x-objs := et1310_eeprom.o \
+               et1310_jagcore.o \
+               et1310_mac.o \
+               et1310_phy.o \
+               et1310_pm.o \
+               et1310_rx.o \
+               et1310_tx.o \
+               et131x_config.o \
+               et131x_debug.o \
+               et131x_initpci.o \
+               et131x_isr.o \
+               et131x_netdev.o
+
+all:
+       $(MAKE) -C $(KSRC) SUBDIRS=$(PWD) modules
+
+clean:
+       rm -rf *.ko *.mod.* *.o .*.cmd .tmp_versions Module.symvers
+
+distclean: clean
+       rm -rf cscope.* *~
diff --git a/src/et131x/README b/src/et131x/README
new file mode 100644 (file)
index 0000000..28752a5
--- /dev/null
@@ -0,0 +1,25 @@
+This is a driver for the ET1310 network device.
+
+Based on the driver found at https://sourceforge.net/projects/et131x/
+
+Cleaned up immensely by Olaf Hartman <o.hartmann@telovital.com> and Christoph
+Hellwig <hch@infradead.org>
+
+Note, the powermanagement options were removed from the vendor provided
+driver as they did not build properly at the time.
+
+TODO:
+       - kernel coding style cleanups
+       - forward port for latest network driver changes
+       - kill useless typecasts (e.g. in et1310_phy.c)
+       - alloc_etherdev is initializing memory with zero?!?
+       - add_timer call in et131x_netdev.c is correct?
+       - Add power saving functionality (suspend, sleep, resume)
+       - Implement a few more kernel Parameter (set mac )
+
+Please send patches to:
+       Greg Kroah-Hartman <gregkh@suse.de>
+
+And Cc: Olaf Hartmann <o.hartmann@telovital.com> as he has this device and can
+test any changes.
+
diff --git a/src/et131x/et1310_address_map.h b/src/et131x/et1310_address_map.h
new file mode 100644 (file)
index 0000000..3c85999
--- /dev/null
@@ -0,0 +1,2399 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_address_map.h - Contains the register mapping for the ET1310
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef _ET1310_ADDRESS_MAP_H_
+#define _ET1310_ADDRESS_MAP_H_
+
+
+/* START OF GLOBAL REGISTER ADDRESS MAP */
+
+typedef union _Q_ADDR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:22;  // bits 10-31
+               u32 addr:10;    // bits 0-9
+#else
+               u32 addr:10;    // bits 0-9
+               u32 unused:22;  // bits 10-31
+#endif
+       } bits;
+} Q_ADDR_t, *PQ_ADDR_t;
+
+/*
+ * structure for tx queue start address reg in global address map
+ * located at address 0x0000
+ * Defined earlier (Q_ADDR_t)
+ */
+
+/*
+ * structure for tx queue end address reg in global address map
+ * located at address 0x0004
+ * Defined earlier (Q_ADDR_t)
+ */
+
+/*
+ * structure for rx queue start address reg in global address map
+ * located at address 0x0008
+ * Defined earlier (Q_ADDR_t)
+ */
+
+/*
+ * structure for rx queue end address reg in global address map
+ * located at address 0x000C
+ * Defined earlier (Q_ADDR_t)
+ */
+
+/*
+ * structure for power management control status reg in global address map
+ * located at address 0x0010
+ */
+typedef union _PM_CSR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:22;          // bits 10-31
+               u32 pm_jagcore_rx_rdy:1;        // bit 9
+               u32 pm_jagcore_tx_rdy:1;        // bit 8
+               u32 pm_phy_lped_en:1;   // bit 7
+               u32 pm_phy_sw_coma:1;   // bit 6
+               u32 pm_rxclk_gate:1;    // bit 5
+               u32 pm_txclk_gate:1;    // bit 4
+               u32 pm_sysclk_gate:1;   // bit 3
+               u32 pm_jagcore_rx_en:1; // bit 2
+               u32 pm_jagcore_tx_en:1; // bit 1
+               u32 pm_gigephy_en:1;    // bit 0
+#else
+               u32 pm_gigephy_en:1;    // bit 0
+               u32 pm_jagcore_tx_en:1; // bit 1
+               u32 pm_jagcore_rx_en:1; // bit 2
+               u32 pm_sysclk_gate:1;   // bit 3
+               u32 pm_txclk_gate:1;    // bit 4
+               u32 pm_rxclk_gate:1;    // bit 5
+               u32 pm_phy_sw_coma:1;   // bit 6
+               u32 pm_phy_lped_en:1;   // bit 7
+               u32 pm_jagcore_tx_rdy:1;        // bit 8
+               u32 pm_jagcore_rx_rdy:1;        // bit 9
+               u32 unused:22;          // bits 10-31
+#endif
+       } bits;
+} PM_CSR_t, *PPM_CSR_t;
+
+/*
+ * structure for interrupt status reg in global address map
+ * located at address 0x0018
+ */
+typedef union _INTERRUPT_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused5:11;                 // bits 21-31
+               u32 slv_timeout:1;                      // bit 20
+               u32 mac_stat_interrupt:1;               // bit 19
+               u32 rxmac_interrupt:1;          // bit 18
+               u32 txmac_interrupt:1;          // bit 17
+               u32 phy_interrupt:1;            // bit 16
+               u32 wake_on_lan:1;                      // bit 15
+               u32 watchdog_interrupt:1;               // bit 14
+               u32 unused4:4;                  // bits 10-13
+               u32 rxdma_err:1;                        // bit 9
+               u32 rxdma_pkt_stat_ring_low:1;  // bit 8
+               u32 rxdma_fb_ring1_low:1;               // bit 7
+               u32 rxdma_fb_ring0_low:1;               // bit 6
+               u32 rxdma_xfr_done:1;           // bit 5
+               u32 txdma_err:1;                        // bit 4
+               u32 txdma_isr:1;                        // bit 3
+               u32 unused3:1;                  // bit 2
+               u32 unused2:1;                  // bit 1
+               u32 unused1:1;                  // bit 0
+#else
+               u32 unused1:1;                  // bit 0
+               u32 unused2:1;                  // bit 1
+               u32 unused3:1;                  // bit 2
+               u32 txdma_isr:1;                        // bit 3
+               u32 txdma_err:1;                        // bit 4
+               u32 rxdma_xfr_done:1;           // bit 5
+               u32 rxdma_fb_ring0_low:1;               // bit 6
+               u32 rxdma_fb_ring1_low:1;               // bit 7
+               u32 rxdma_pkt_stat_ring_low:1;  // bit 8
+               u32 rxdma_err:1;                        // bit 9
+               u32 unused4:4;                  // bits 10-13
+               u32 watchdog_interrupt:1;               // bit 14
+               u32 wake_on_lan:1;                      // bit 15
+               u32 phy_interrupt:1;            // bit 16
+               u32 txmac_interrupt:1;          // bit 17
+               u32 rxmac_interrupt:1;          // bit 18
+               u32 mac_stat_interrupt:1;               // bit 19
+               u32 slv_timeout:1;                      // bit 20
+               u32 unused5:11;                 // bits 21-31
+#endif
+       } bits;
+} INTERRUPT_t, *PINTERRUPT_t;
+
+/*
+ * structure for interrupt mask reg in global address map
+ * located at address 0x001C
+ * Defined earlier (INTERRUPT_t), but 'watchdog_interrupt' is not used.
+ */
+
+/*
+ * structure for interrupt alias clear mask reg in global address map
+ * located at address 0x0020
+ * Defined earlier (INTERRUPT_t)
+ */
+
+/*
+ * structure for interrupt status alias reg in global address map
+ * located at address 0x0024
+ * Defined earlier (INTERRUPT_t)
+ */
+
+/*
+ * structure for software reset reg in global address map
+ * located at address 0x0028
+ */
+typedef union _SW_RESET_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 selfclr_disable:1;  // bit 31
+               u32 unused:24;          // bits 7-30
+               u32 mmc_sw_reset:1;     // bit 6
+               u32 mac_stat_sw_reset:1;        // bit 5
+               u32 mac_sw_reset:1;     // bit 4
+               u32 rxmac_sw_reset:1;   // bit 3
+               u32 txmac_sw_reset:1;   // bit 2
+               u32 rxdma_sw_reset:1;   // bit 1
+               u32 txdma_sw_reset:1;   // bit 0
+#else
+               u32 txdma_sw_reset:1;   // bit 0
+               u32 rxdma_sw_reset:1;   // bit 1
+               u32 txmac_sw_reset:1;   // bit 2
+               u32 rxmac_sw_reset:1;   // bit 3
+               u32 mac_sw_reset:1;     // bit 4
+               u32 mac_stat_sw_reset:1;        // bit 5
+               u32 mmc_sw_reset:1;     // bit 6
+               u32 unused:24;          // bits 7-30
+               u32 selfclr_disable:1;  // bit 31
+#endif
+       } bits;
+} SW_RESET_t, *PSW_RESET_t;
+
+/*
+ * structure for SLV Timer reg in global address map
+ * located at address 0x002C
+ */
+typedef union _SLV_TIMER_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:8;   // bits 24-31
+               u32 timer_ini:24;       // bits 0-23
+#else
+               u32 timer_ini:24;       // bits 0-23
+               u32 unused:8;   // bits 24-31
+#endif
+       } bits;
+} SLV_TIMER_t, *PSLV_TIMER_t;
+
+/*
+ * structure for MSI Configuration reg in global address map
+ * located at address 0x0030
+ */
+typedef union _MSI_CONFIG_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused1:13; // bits 19-31
+               u32 msi_tc:3;   // bits 16-18
+               u32 unused2:11; // bits 5-15
+               u32 msi_vector:5;       // bits 0-4
+#else
+               u32 msi_vector:5;       // bits 0-4
+               u32 unused2:11; // bits 5-15
+               u32 msi_tc:3;   // bits 16-18
+               u32 unused1:13; // bits 19-31
+#endif
+       } bits;
+} MSI_CONFIG_t, *PMSI_CONFIG_t;
+
+/*
+ * structure for Loopback reg in global address map
+ * located at address 0x0034
+ */
+typedef union _LOOPBACK_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:30;          // bits 2-31
+               u32 dma_loopback:1;     // bit 1
+               u32 mac_loopback:1;     // bit 0
+#else
+               u32 mac_loopback:1;     // bit 0
+               u32 dma_loopback:1;     // bit 1
+               u32 unused:30;          // bits 2-31
+#endif
+       } bits;
+} LOOPBACK_t, *PLOOPBACK_t;
+
+/*
+ * GLOBAL Module of JAGCore Address Mapping
+ * Located at address 0x0000
+ */
+typedef struct _GLOBAL_t {                     // Location:
+       Q_ADDR_t txq_start_addr;                //  0x0000
+       Q_ADDR_t txq_end_addr;                  //  0x0004
+       Q_ADDR_t rxq_start_addr;                //  0x0008
+       Q_ADDR_t rxq_end_addr;                  //  0x000C
+       PM_CSR_t pm_csr;                        //  0x0010
+       u32 unused;                             //  0x0014
+       INTERRUPT_t int_status;                 //  0x0018
+       INTERRUPT_t int_mask;                   //  0x001C
+       INTERRUPT_t int_alias_clr_en;           //  0x0020
+       INTERRUPT_t int_status_alias;           //  0x0024
+       SW_RESET_t sw_reset;                    //  0x0028
+       SLV_TIMER_t slv_timer;                  //  0x002C
+       MSI_CONFIG_t msi_config;                //  0x0030
+       LOOPBACK_t loopback;                    //  0x0034
+       u32 watchdog_timer;                     //  0x0038
+} GLOBAL_t, *PGLOBAL_t;
+
+/* END OF GLOBAL REGISTER ADDRESS MAP */
+
+
+/* START OF TXDMA REGISTER ADDRESS MAP */
+
+/*
+ * structure for txdma control status reg in txdma address map
+ * located at address 0x1000
+ */
+typedef union _TXDMA_CSR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused2:19;         // bits 13-31
+               u32 traffic_class:4;    // bits 9-12
+               u32 sngl_epkt_mode:1;   // bit 8
+               u32 cache_thrshld:4;    // bits 4-7
+               u32 unused1:2;          // bits 2-3
+               u32 drop_TLP_disable:1; // bit 1
+               u32 halt:1;             // bit 0
+#else
+               u32 halt:1;             // bit 0
+               u32 drop_TLP_disable:1; // bit 1
+               u32 unused1:2;          // bits 2-3
+               u32 cache_thrshld:4;    // bits 4-7
+               u32 sngl_epkt_mode:1;   // bit 8
+               u32 traffic_class:4;    // bits 9-12
+               u32 unused2:19;         // bits 13-31
+#endif
+       } bits;
+} TXDMA_CSR_t, *PTXDMA_CSR_t;
+
+/*
+ * structure for txdma packet ring base address hi reg in txdma address map
+ * located at address 0x1004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring base address low reg in txdma address map
+ * located at address 0x1008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring number of descriptor reg in txdma address
+ * map.  Located at address 0x100C
+ */
+typedef union _TXDMA_PR_NUM_DES_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:22;  // bits 10-31
+               u32 pr_ndes:10; // bits 0-9
+#else
+               u32 pr_ndes:10; // bits 0-9
+               u32 unused:22;  // bits 10-31
+#endif
+       } bits;
+} TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
+
+
+typedef union _DMA10W_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:21;  // bits 11-31
+               u32 wrap:1;     // bit 10
+               u32 val:10;     // bits 0-9
+#else
+               u32 val:10;     // bits 0-9
+               u32 wrap:1;     // bit 10
+               u32 unused:21;  // bits 11-31
+#endif
+       } bits;
+} DMA10W_t, *PDMA10W_t;
+
+/*
+ * structure for txdma tx queue write address reg in txdma address map
+ * located at address 0x1010
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for txdma tx queue write address external reg in txdma address map
+ * located at address 0x1014
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for txdma tx queue read address reg in txdma address map
+ * located at address 0x1018
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for txdma status writeback address hi reg in txdma address map
+ * located at address 0x101C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma status writeback address lo reg in txdma address map
+ * located at address 0x1020
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma service request reg in txdma address map
+ * located at address 0x1024
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for txdma service complete reg in txdma address map
+ * located at address 0x1028
+ * Defined earlier (DMA10W_t)
+ */
+
+typedef union _DMA4W_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:27;  // bits 5-31
+               u32 wrap:1;     // bit 4
+               u32 val:4;              // bit 0-3
+#else
+               u32 val:4;              // bits 0-3
+               u32 wrap:1;     // bit 4
+               u32 unused:27;  // bits 5-31
+#endif
+       } bits;
+} DMA4W_t, *PDMA4W_t;
+
+/*
+ * structure for txdma tx descriptor cache read index reg in txdma address map
+ * located at address 0x102C
+ * Defined earlier (DMA4W_t)
+ */
+
+/*
+ * structure for txdma tx descriptor cache write index reg in txdma address map
+ * located at address 0x1030
+ * Defined earlier (DMA4W_t)
+ */
+
+/*
+ * structure for txdma error reg in txdma address map
+ * located at address 0x1034
+ */
+typedef union _TXDMA_ERROR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused3:22;         // bits 10-31
+               u32 WrbkRewind:1;       // bit 9
+               u32 WrbkResend:1;       // bit 8
+               u32 unused2:2;          // bits 6-7
+               u32 DescrRewind:1;      // bit 5
+               u32 DescrResend:1;      // bit 4
+               u32 unused1:2;          // bits 2-3
+               u32 PyldRewind:1;       // bit 1
+               u32 PyldResend:1;       // bit 0
+#else
+               u32 PyldResend:1;       // bit 0
+               u32 PyldRewind:1;       // bit 1
+               u32 unused1:2;          // bits 2-3
+               u32 DescrResend:1;      // bit 4
+               u32 DescrRewind:1;      // bit 5
+               u32 unused2:2;          // bits 6-7
+               u32 WrbkResend:1;       // bit 8
+               u32 WrbkRewind:1;       // bit 9
+               u32 unused3:22;         // bits 10-31
+#endif
+       } bits;
+} TXDMA_ERROR_t, *PTXDMA_ERROR_t;
+
+/*
+ * Tx DMA Module of JAGCore Address Mapping
+ * Located at address 0x1000
+ */
+typedef struct _TXDMA_t {              // Location:
+       TXDMA_CSR_t csr;                //  0x1000
+       u32 pr_base_hi;                 //  0x1004
+       u32 pr_base_lo;                 //  0x1008
+       TXDMA_PR_NUM_DES_t pr_num_des;  //  0x100C
+       DMA10W_t txq_wr_addr;           //  0x1010
+       DMA10W_t txq_wr_addr_ext;       //  0x1014
+       DMA10W_t txq_rd_addr;           //  0x1018
+       u32 dma_wb_base_hi;             //  0x101C
+       u32 dma_wb_base_lo;             //  0x1020
+       DMA10W_t service_request;       //  0x1024
+       DMA10W_t service_complete;      //  0x1028
+       DMA4W_t cache_rd_index;         //  0x102C
+       DMA4W_t cache_wr_index;         //  0x1030
+       TXDMA_ERROR_t TxDmaError;       //  0x1034
+       u32 DescAbortCount;             //  0x1038
+       u32 PayloadAbortCnt;            //  0x103c
+       u32 WriteBackAbortCnt;          //  0x1040
+       u32 DescTimeoutCnt;             //  0x1044
+       u32 PayloadTimeoutCnt;          //  0x1048
+       u32 WriteBackTimeoutCnt;        //  0x104c
+       u32 DescErrorCount;             //  0x1050
+       u32 PayloadErrorCnt;            //  0x1054
+       u32 WriteBackErrorCnt;          //  0x1058
+       u32 DroppedTLPCount;            //  0x105c
+       DMA10W_t NewServiceComplete;    //  0x1060
+       u32 EthernetPacketCount;        //  0x1064
+} TXDMA_t, *PTXDMA_t;
+
+/* END OF TXDMA REGISTER ADDRESS MAP */
+
+
+/* START OF RXDMA REGISTER ADDRESS MAP */
+
+/*
+ * structure for control status reg in rxdma address map
+ * Located at address 0x2000
+ */
+typedef union _RXDMA_CSR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused2:14;         // bits 18-31
+               u32 halt_status:1;      // bit 17
+               u32 pkt_done_flush:1;   // bit 16
+               u32 pkt_drop_disable:1; // bit 15
+               u32 unused1:1;          // bit 14
+               u32 fbr1_enable:1;      // bit 13
+               u32 fbr1_size:2;        // bits 11-12
+               u32 fbr0_enable:1;      // bit 10
+               u32 fbr0_size:2;        // bits 8-9
+               u32 dma_big_endian:1;   // bit 7
+               u32 pkt_big_endian:1;   // bit 6
+               u32 psr_big_endian:1;   // bit 5
+               u32 fbr_big_endian:1;   // bit 4
+               u32 tc:3;               // bits 1-3
+               u32 halt:1;             // bit 0
+#else
+               u32 halt:1;             // bit 0
+               u32 tc:3;               // bits 1-3
+               u32 fbr_big_endian:1;   // bit 4
+               u32 psr_big_endian:1;   // bit 5
+               u32 pkt_big_endian:1;   // bit 6
+               u32 dma_big_endian:1;   // bit 7
+               u32 fbr0_size:2;        // bits 8-9
+               u32 fbr0_enable:1;      // bit 10
+               u32 fbr1_size:2;        // bits 11-12
+               u32 fbr1_enable:1;      // bit 13
+               u32 unused1:1;          // bit 14
+               u32 pkt_drop_disable:1; // bit 15
+               u32 pkt_done_flush:1;   // bit 16
+               u32 halt_status:1;      // bit 17
+               u32 unused2:14;         // bits 18-31
+#endif
+       } bits;
+} RXDMA_CSR_t, *PRXDMA_CSR_t;
+
+/*
+ * structure for dma writeback lo reg in rxdma address map
+ * located at address 0x2004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for dma writeback hi reg in rxdma address map
+ * located at address 0x2008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for number of packets done reg in rxdma address map
+ * located at address 0x200C
+ */
+typedef union _RXDMA_NUM_PKT_DONE_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:24;  // bits 8-31
+               u32 num_done:8; // bits 0-7
+#else
+               u32 num_done:8; // bits 0-7
+               u32 unused:24;  // bits 8-31
+#endif
+       } bits;
+} RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
+
+/*
+ * structure for max packet time reg in rxdma address map
+ * located at address 0x2010
+ */
+typedef union _RXDMA_MAX_PKT_TIME_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:14;          // bits 18-31
+               u32 time_done:18;       // bits 0-17
+#else
+               u32 time_done:18;       // bits 0-17
+               u32 unused:14;          // bits 18-31
+#endif
+       } bits;
+} RXDMA_MAX_PKT_TIME_t, *PRXDMA_MAX_PKT_TIME_t;
+
+/*
+ * structure for rx queue read address reg in rxdma address map
+ * located at address 0x2014
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for rx queue read address external reg in rxdma address map
+ * located at address 0x2018
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for rx queue write address reg in rxdma address map
+ * located at address 0x201C
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for packet status ring base address lo reg in rxdma address map
+ * located at address 0x2020
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address hi reg in rxdma address map
+ * located at address 0x2024
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring number of descriptors reg in rxdma address
+ * map.  Located at address 0x2028
+ */
+typedef union _RXDMA_PSR_NUM_DES_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:20;          // bits 12-31
+               u32 psr_ndes:12;        // bit 0-11
+#else
+               u32 psr_ndes:12;        // bit 0-11
+               u32 unused:20;          // bits 12-31
+#endif
+       } bits;
+} RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
+
+/*
+ * structure for packet status ring available offset reg in rxdma address map
+ * located at address 0x202C
+ */
+typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:19;          // bits 13-31
+               u32 psr_avail_wrap:1;   // bit 12
+               u32 psr_avail:12;       // bit 0-11
+#else
+               u32 psr_avail:12;       // bit 0-11
+               u32 psr_avail_wrap:1;   // bit 12
+               u32 unused:19;          // bits 13-31
+#endif
+       } bits;
+} RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
+
+/*
+ * structure for packet status ring full offset reg in rxdma address map
+ * located at address 0x2030
+ */
+typedef union _RXDMA_PSR_FULL_OFFSET_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:19;          // bits 13-31
+               u32 psr_full_wrap:1;    // bit 12
+               u32 psr_full:12;        // bit 0-11
+#else
+               u32 psr_full:12;        // bit 0-11
+               u32 psr_full_wrap:1;    // bit 12
+               u32 unused:19;          // bits 13-31
+#endif
+       } bits;
+} RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
+
+/*
+ * structure for packet status ring access index reg in rxdma address map
+ * located at address 0x2034
+ */
+typedef union _RXDMA_PSR_ACCESS_INDEX_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:27;  // bits 5-31
+               u32 psr_ai:5;   // bits 0-4
+#else
+               u32 psr_ai:5;   // bits 0-4
+               u32 unused:27;  // bits 5-31
+#endif
+       } bits;
+} RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
+
+/*
+ * structure for packet status ring minimum descriptors reg in rxdma address
+ * map.  Located at address 0x2038
+ */
+typedef union _RXDMA_PSR_MIN_DES_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:20;  // bits 12-31
+               u32 psr_min:12; // bits 0-11
+#else
+               u32 psr_min:12; // bits 0-11
+               u32 unused:20;  // bits 12-31
+#endif
+       } bits;
+} RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
+
+/*
+ * structure for free buffer ring base lo address reg in rxdma address map
+ * located at address 0x203C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring base hi address reg in rxdma address map
+ * located at address 0x2040
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring number of descriptors reg in rxdma address
+ * map.  Located at address 0x2044
+ */
+typedef union _RXDMA_FBR_NUM_DES_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:22;          // bits 10-31
+               u32 fbr_ndesc:10;       // bits 0-9
+#else
+               u32 fbr_ndesc:10;       // bits 0-9
+               u32 unused:22;          // bits 10-31
+#endif
+       } bits;
+} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
+
+/*
+ * structure for free buffer ring 0 available offset reg in rxdma address map
+ * located at address 0x2048
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for free buffer ring 0 full offset reg in rxdma address map
+ * located at address 0x204C
+ * Defined earlier (DMA10W_t)
+ */
+
+/*
+ * structure for free buffer cache 0 full offset reg in rxdma address map
+ * located at address 0x2050
+ */
+typedef union _RXDMA_FBC_RD_INDEX_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:27;  // bits 5-31
+               u32 fbc_rdi:5;  // bit 0-4
+#else
+               u32 fbc_rdi:5;  // bit 0-4
+               u32 unused:27;  // bits 5-31
+#endif
+       } bits;
+} RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
+
+/*
+ * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
+ * located at address 0x2054
+ */
+typedef union _RXDMA_FBR_MIN_DES_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:22;  // bits 10-31
+               u32 fbr_min:10; // bits 0-9
+#else
+               u32 fbr_min:10; // bits 0-9
+               u32 unused:22;  // bits 10-31
+#endif
+       } bits;
+} RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
+
+/*
+ * structure for free buffer ring 1 base address lo reg in rxdma address map
+ * located at address 0x2058 - 0x205C
+ * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
+ */
+
+/*
+ * structure for free buffer ring 1 number of descriptors reg in rxdma address
+ * map.  Located at address 0x2060
+ * Defined earlier (RXDMA_FBR_NUM_DES_t)
+ */
+
+/*
+ * structure for free buffer ring 1 available offset reg in rxdma address map
+ * located at address 0x2064
+ * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer ring 1 full offset reg in rxdma address map
+ * located at address 0x2068
+ * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer cache 1 read index reg in rxdma address map
+ * located at address 0x206C
+ * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
+ */
+
+/*
+ * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
+ * located at address 0x2070
+ * Defined Earlier (RXDMA_FBR_MIN_DES_t)
+ */
+
+/*
+ * Rx DMA Module of JAGCore Address Mapping
+ * Located at address 0x2000
+ */
+typedef struct _RXDMA_t {                              // Location:
+       RXDMA_CSR_t csr;                                //  0x2000
+       u32 dma_wb_base_lo;                             //  0x2004
+       u32 dma_wb_base_hi;                             //  0x2008
+       RXDMA_NUM_PKT_DONE_t num_pkt_done;              //  0x200C
+       RXDMA_MAX_PKT_TIME_t max_pkt_time;              //  0x2010
+       DMA10W_t rxq_rd_addr;                           //  0x2014
+       DMA10W_t rxq_rd_addr_ext;                       //  0x2018
+       DMA10W_t rxq_wr_addr;                           //  0x201C
+       u32 psr_base_lo;                                //  0x2020
+       u32 psr_base_hi;                                //  0x2024
+       RXDMA_PSR_NUM_DES_t psr_num_des;                //  0x2028
+       RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset;      //  0x202C
+       RXDMA_PSR_FULL_OFFSET_t psr_full_offset;        //  0x2030
+       RXDMA_PSR_ACCESS_INDEX_t psr_access_index;      //  0x2034
+       RXDMA_PSR_MIN_DES_t psr_min_des;                //  0x2038
+       u32 fbr0_base_lo;                               //  0x203C
+       u32 fbr0_base_hi;                               //  0x2040
+       RXDMA_FBR_NUM_DES_t fbr0_num_des;               //  0x2044
+       DMA10W_t fbr0_avail_offset;                     //  0x2048
+       DMA10W_t fbr0_full_offset;                      //  0x204C
+       RXDMA_FBC_RD_INDEX_t fbr0_rd_index;             //  0x2050
+       RXDMA_FBR_MIN_DES_t fbr0_min_des;               //  0x2054
+       u32 fbr1_base_lo;                               //  0x2058
+       u32 fbr1_base_hi;                               //  0x205C
+       RXDMA_FBR_NUM_DES_t fbr1_num_des;               //  0x2060
+       DMA10W_t fbr1_avail_offset;                     //  0x2064
+       DMA10W_t fbr1_full_offset;                      //  0x2068
+       RXDMA_FBC_RD_INDEX_t fbr1_rd_index;             //  0x206C
+       RXDMA_FBR_MIN_DES_t fbr1_min_des;               //  0x2070
+} RXDMA_t, *PRXDMA_t;
+
+/* END OF RXDMA REGISTER ADDRESS MAP */
+
+
+/* START OF TXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for control reg in txmac address map
+ * located at address 0x3000
+ */
+typedef union _TXMAC_CTL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:24;          // bits 8-31
+               u32 cklseg_diable:1;    // bit 7
+               u32 ckbcnt_disable:1;   // bit 6
+               u32 cksegnum:1;         // bit 5
+               u32 async_disable:1;    // bit 4
+               u32 fc_disable:1;       // bit 3
+               u32 mcif_disable:1;     // bit 2
+               u32 mif_disable:1;      // bit 1
+               u32 txmac_en:1;         // bit 0
+#else
+               u32 txmac_en:1;         // bit 0
+               u32 mif_disable:1;      // bit 1 mac interface
+               u32 mcif_disable:1;     // bit 2 mem. contr. interface
+               u32 fc_disable:1;       // bit 3
+               u32 async_disable:1;    // bit 4
+               u32 cksegnum:1;         // bit 5
+               u32 ckbcnt_disable:1;   // bit 6
+               u32 cklseg_diable:1;    // bit 7
+               u32 unused:24;          // bits 8-31
+#endif
+       } bits;
+} TXMAC_CTL_t, *PTXMAC_CTL_t;
+
+/*
+ * structure for shadow pointer reg in txmac address map
+ * located at address 0x3004
+ */
+typedef union _TXMAC_SHADOW_PTR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved2:5;        // bits 27-31
+               u32 txq_rd_ptr:11;      // bits 16-26
+               u32 reserved:5;         // bits 11-15
+               u32 txq_wr_ptr:11;      // bits 0-10
+#else
+               u32 txq_wr_ptr:11;      // bits 0-10
+               u32 reserved:5;         // bits 11-15
+               u32 txq_rd_ptr:11;      // bits 16-26
+               u32 reserved2:5;        // bits 27-31
+#endif
+       } bits;
+} TXMAC_SHADOW_PTR_t, *PTXMAC_SHADOW_PTR_t;
+
+/*
+ * structure for error count reg in txmac address map
+ * located at address 0x3008
+ */
+typedef union _TXMAC_ERR_CNT_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:20;          // bits 12-31
+               u32 reserved:4;         // bits 8-11
+               u32 txq_underrun:4;     // bits 4-7
+               u32 fifo_underrun:4;    // bits 0-3
+#else
+               u32 fifo_underrun:4;    // bits 0-3
+               u32 txq_underrun:4;     // bits 4-7
+               u32 reserved:4;         // bits 8-11
+               u32 unused:20;          // bits 12-31
+#endif
+       } bits;
+} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
+
+/*
+ * structure for max fill reg in txmac address map
+ * located at address 0x300C
+ */
+typedef union _TXMAC_MAX_FILL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:20;          // bits 12-31
+               u32 max_fill:12;        // bits 0-11
+#else
+               u32 max_fill:12;        // bits 0-11
+               u32 unused:20;          // bits 12-31
+#endif
+       } bits;
+} TXMAC_MAX_FILL_t, *PTXMAC_MAX_FILL_t;
+
+/*
+ * structure for cf parameter reg in txmac address map
+ * located at address 0x3010
+ */
+typedef union _TXMAC_CF_PARAM_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 cfep:16;    // bits 16-31
+               u32 cfpt:16;    // bits 0-15
+#else
+               u32 cfpt:16;    // bits 0-15
+               u32 cfep:16;    // bits 16-31
+#endif
+       } bits;
+} TXMAC_CF_PARAM_t, *PTXMAC_CF_PARAM_t;
+
+/*
+ * structure for tx test reg in txmac address map
+ * located at address 0x3014
+ */
+typedef union _TXMAC_TXTEST_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused2:15;         // bits 17-31
+               u32 reserved1:1;        // bit 16
+               u32 txtest_en:1;        // bit 15
+               u32 unused1:4;          // bits 11-14
+               u32 txqtest_ptr:11;     // bits 0-11
+#else
+               u32 txqtest_ptr:11;     // bits 0-10
+               u32 unused1:4;          // bits 11-14
+               u32 txtest_en:1;        // bit 15
+               u32 reserved1:1;        // bit 16
+               u32 unused2:15;         // bits 17-31
+#endif
+       } bits;
+} TXMAC_TXTEST_t, *PTXMAC_TXTEST_t;
+
+/*
+ * structure for error reg in txmac address map
+ * located at address 0x3018
+ */
+typedef union _TXMAC_ERR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused2:23;         // bits 9-31
+               u32 fifo_underrun:1;    // bit 8
+               u32 unused1:2;          // bits 6-7
+               u32 ctrl2_err:1;        // bit 5
+               u32 txq_underrun:1;     // bit 4
+               u32 bcnt_err:1;         // bit 3
+               u32 lseg_err:1;         // bit 2
+               u32 segnum_err:1;       // bit 1
+               u32 seg0_err:1;         // bit 0
+#else
+               u32 seg0_err:1;         // bit 0
+               u32 segnum_err:1;       // bit 1
+               u32 lseg_err:1;         // bit 2
+               u32 bcnt_err:1;         // bit 3
+               u32 txq_underrun:1;     // bit 4
+               u32 ctrl2_err:1;        // bit 5
+               u32 unused1:2;          // bits 6-7
+               u32 fifo_underrun:1;    // bit 8
+               u32 unused2:23;         // bits 9-31
+#endif
+       } bits;
+} TXMAC_ERR_t, *PTXMAC_ERR_t;
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x301C
+ */
+typedef union _TXMAC_ERR_INT_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused2:23;         // bits 9-31
+               u32 fifo_underrun:1;    // bit 8
+               u32 unused1:2;          // bits 6-7
+               u32 ctrl2_err:1;        // bit 5
+               u32 txq_underrun:1;     // bit 4
+               u32 bcnt_err:1;         // bit 3
+               u32 lseg_err:1;         // bit 2
+               u32 segnum_err:1;       // bit 1
+               u32 seg0_err:1;         // bit 0
+#else
+               u32 seg0_err:1;         // bit 0
+               u32 segnum_err:1;       // bit 1
+               u32 lseg_err:1;         // bit 2
+               u32 bcnt_err:1;         // bit 3
+               u32 txq_underrun:1;     // bit 4
+               u32 ctrl2_err:1;        // bit 5
+               u32 unused1:2;          // bits 6-7
+               u32 fifo_underrun:1;    // bit 8
+               u32 unused2:23;         // bits 9-31
+#endif
+       } bits;
+} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x3020
+ */
+typedef union _TXMAC_CP_CTRL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:30;          // bits 2-31
+               u32 bp_req:1;           // bit 1
+               u32 bp_xonxoff:1;       // bit 0
+#else
+               u32 bp_xonxoff:1;       // bit 0
+               u32 bp_req:1;           // bit 1
+               u32 unused:30;          // bits 2-31
+#endif
+       } bits;
+} TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;
+
+/*
+ * Tx MAC Module of JAGCore Address Mapping
+ */
+typedef struct _TXMAC_t {              // Location:
+       TXMAC_CTL_t ctl;                //  0x3000
+       TXMAC_SHADOW_PTR_t shadow_ptr;  //  0x3004
+       TXMAC_ERR_CNT_t err_cnt;        //  0x3008
+       TXMAC_MAX_FILL_t max_fill;      //  0x300C
+       TXMAC_CF_PARAM_t cf_param;      //  0x3010
+       TXMAC_TXTEST_t tx_test;         //  0x3014
+       TXMAC_ERR_t err;                //  0x3018
+       TXMAC_ERR_INT_t err_int;        //  0x301C
+       TXMAC_BP_CTRL_t bp_ctrl;        //  0x3020
+} TXMAC_t, *PTXMAC_t;
+
+/* END OF TXMAC REGISTER ADDRESS MAP */
+
+/* START OF RXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for rxmac control reg in rxmac address map
+ * located at address 0x4000
+ */
+typedef union _RXMAC_CTRL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:25;                // bits 7-31
+               u32 rxmac_int_disable:1;        // bit 6
+               u32 async_disable:1;            // bit 5
+               u32 mif_disable:1;              // bit 4
+               u32 wol_disable:1;              // bit 3
+               u32 pkt_filter_disable:1;       // bit 2
+               u32 mcif_disable:1;             // bit 1
+               u32 rxmac_en:1;                 // bit 0
+#else
+               u32 rxmac_en:1;                 // bit 0
+               u32 mcif_disable:1;             // bit 1
+               u32 pkt_filter_disable:1;       // bit 2
+               u32 wol_disable:1;              // bit 3
+               u32 mif_disable:1;              // bit 4
+               u32 async_disable:1;            // bit 5
+               u32 rxmac_int_disable:1;        // bit 6
+               u32 reserved:25;                // bits 7-31
+#endif
+       } bits;
+} RXMAC_CTRL_t, *PRXMAC_CTRL_t;
+
+/*
+ * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
+ * located at address 0x4004
+ */
+typedef union _RXMAC_WOL_CTL_CRC0_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 crc0:16;            // bits 16-31
+               u32 reserve:4;          // bits 12-15
+               u32 ignore_pp:1;        // bit 11
+               u32 ignore_mp:1;        // bit 10
+               u32 clr_intr:1;         // bit 9
+               u32 ignore_link_chg:1;  // bit 8
+               u32 ignore_uni:1;       // bit 7
+               u32 ignore_multi:1;     // bit 6
+               u32 ignore_broad:1;     // bit 5
+               u32 valid_crc4:1;       // bit 4
+               u32 valid_crc3:1;       // bit 3
+               u32 valid_crc2:1;       // bit 2
+               u32 valid_crc1:1;       // bit 1
+               u32 valid_crc0:1;       // bit 0
+#else
+               u32 valid_crc0:1;       // bit 0
+               u32 valid_crc1:1;       // bit 1
+               u32 valid_crc2:1;       // bit 2
+               u32 valid_crc3:1;       // bit 3
+               u32 valid_crc4:1;       // bit 4
+               u32 ignore_broad:1;     // bit 5
+               u32 ignore_multi:1;     // bit 6
+               u32 ignore_uni:1;       // bit 7
+               u32 ignore_link_chg:1;  // bit 8
+               u32 clr_intr:1;         // bit 9
+               u32 ignore_mp:1;        // bit 10
+               u32 ignore_pp:1;        // bit 11
+               u32 reserve:4;          // bits 12-15
+               u32 crc0:16;            // bits 16-31
+#endif
+       } bits;
+} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
+
+/*
+ * structure for CRC 1 and CRC 2 reg in rxmac address map
+ * located at address 0x4008
+ */
+typedef union _RXMAC_WOL_CRC12_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 crc2:16;    // bits 16-31
+               u32 crc1:16;    // bits 0-15
+#else
+               u32 crc1:16;    // bits 0-15
+               u32 crc2:16;    // bits 16-31
+#endif
+       } bits;
+} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
+
+/*
+ * structure for CRC 3 and CRC 4 reg in rxmac address map
+ * located at address 0x400C
+ */
+typedef union _RXMAC_WOL_CRC34_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 crc4:16;    // bits 16-31
+               u32 crc3:16;    // bits 0-15
+#else
+               u32 crc3:16;    // bits 0-15
+               u32 crc4:16;    // bits 16-31
+#endif
+       } bits;
+} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
+
+/*
+ * structure for Wake On Lan Source Address Lo reg in rxmac address map
+ * located at address 0x4010
+ */
+typedef union _RXMAC_WOL_SA_LO_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 sa3:8;      // bits 24-31
+               u32 sa4:8;      // bits 16-23
+               u32 sa5:8;      // bits 8-15
+               u32 sa6:8;      // bits 0-7
+#else
+               u32 sa6:8;      // bits 0-7
+               u32 sa5:8;      // bits 8-15
+               u32 sa4:8;      // bits 16-23
+               u32 sa3:8;      // bits 24-31
+#endif
+       } bits;
+} RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
+
+/*
+ * structure for Wake On Lan Source Address Hi reg in rxmac address map
+ * located at address 0x4014
+ */
+typedef union _RXMAC_WOL_SA_HI_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:16;        // bits 16-31
+               u32 sa1:8;              // bits 8-15
+               u32 sa2:8;              // bits 0-7
+#else
+               u32 sa2:8;              // bits 0-7
+               u32 sa1:8;              // bits 8-15
+               u32 reserved:16;        // bits 16-31
+#endif
+       } bits;
+} RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
+
+/*
+ * structure for Wake On Lan mask reg in rxmac address map
+ * located at address 0x4018 - 0x4064
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Unicast Paket Filter Address 1 reg in rxmac address map
+ * located at address 0x4068
+ */
+typedef union _RXMAC_UNI_PF_ADDR1_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 addr1_3:8;  // bits 24-31
+               u32 addr1_4:8;  // bits 16-23
+               u32 addr1_5:8;  // bits 8-15
+               u32 addr1_6:8;  // bits 0-7
+#else
+               u32 addr1_6:8;  // bits 0-7
+               u32 addr1_5:8;  // bits 8-15
+               u32 addr1_4:8;  // bits 16-23
+               u32 addr1_3:8;  // bits 24-31
+#endif
+       } bits;
+} RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
+
+/*
+ * structure for Unicast Paket Filter Address 2 reg in rxmac address map
+ * located at address 0x406C
+ */
+typedef union _RXMAC_UNI_PF_ADDR2_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 addr2_3:8;  // bits 24-31
+               u32 addr2_4:8;  // bits 16-23
+               u32 addr2_5:8;  // bits 8-15
+               u32 addr2_6:8;  // bits 0-7
+#else
+               u32 addr2_6:8;  // bits 0-7
+               u32 addr2_5:8;  // bits 8-15
+               u32 addr2_4:8;  // bits 16-23
+               u32 addr2_3:8;  // bits 24-31
+#endif
+       } bits;
+} RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
+
+/*
+ * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
+ * located at address 0x4070
+ */
+typedef union _RXMAC_UNI_PF_ADDR3_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 addr2_1:8;  // bits 24-31
+               u32 addr2_2:8;  // bits 16-23
+               u32 addr1_1:8;  // bits 8-15
+               u32 addr1_2:8;  // bits 0-7
+#else
+               u32 addr1_2:8;  // bits 0-7
+               u32 addr1_1:8;  // bits 8-15
+               u32 addr2_2:8;  // bits 16-23
+               u32 addr2_1:8;  // bits 24-31
+#endif
+       } bits;
+} RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
+
+/*
+ * structure for Multicast Hash reg in rxmac address map
+ * located at address 0x4074 - 0x4080
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Packet Filter Control reg in rxmac address map
+ * located at address 0x4084
+ */
+typedef union _RXMAC_PF_CTRL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused2:9;          // bits 23-31
+               u32 min_pkt_size:7;     // bits 16-22
+               u32 unused1:12;         // bits 4-15
+               u32 filter_frag_en:1;   // bit 3
+               u32 filter_uni_en:1;    // bit 2
+               u32 filter_multi_en:1;  // bit 1
+               u32 filter_broad_en:1;  // bit 0
+#else
+               u32 filter_broad_en:1;  // bit 0
+               u32 filter_multi_en:1;  // bit 1
+               u32 filter_uni_en:1;    // bit 2
+               u32 filter_frag_en:1;   // bit 3
+               u32 unused1:12;         // bits 4-15
+               u32 min_pkt_size:7;     // bits 16-22
+               u32 unused2:9;          // bits 23-31
+#endif
+       } bits;
+} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
+
+/*
+ * structure for Memory Controller Interface Control Max Segment reg in rxmac
+ * address map.  Located at address 0x4088
+ */
+typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:22;        // bits 10-31
+               u32 max_size:8; // bits 2-9
+               u32 fc_en:1;    // bit 1
+               u32 seg_en:1;   // bit 0
+#else
+               u32 seg_en:1;   // bit 0
+               u32 fc_en:1;    // bit 1
+               u32 max_size:8; // bits 2-9
+               u32 reserved:22;        // bits 10-31
+#endif
+       } bits;
+} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
+
+/*
+ * structure for Memory Controller Interface Water Mark reg in rxmac address
+ * map.  Located at address 0x408C
+ */
+typedef union _RXMAC_MCIF_WATER_MARK_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved2:6;        // bits 26-31
+               u32 mark_hi:10; // bits 16-25
+               u32 reserved1:6;        // bits 10-15
+               u32 mark_lo:10; // bits 0-9
+#else
+               u32 mark_lo:10; // bits 0-9
+               u32 reserved1:6;        // bits 10-15
+               u32 mark_hi:10; // bits 16-25
+               u32 reserved2:6;        // bits 26-31
+#endif
+       } bits;
+} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
+
+/*
+ * structure for Rx Queue Dialog reg in rxmac address map.
+ * located at address 0x4090
+ */
+typedef union _RXMAC_RXQ_DIAG_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved2:6;        // bits 26-31
+               u32 rd_ptr:10;  // bits 16-25
+               u32 reserved1:6;        // bits 10-15
+               u32 wr_ptr:10;  // bits 0-9
+#else
+               u32 wr_ptr:10;  // bits 0-9
+               u32 reserved1:6;        // bits 10-15
+               u32 rd_ptr:10;  // bits 16-25
+               u32 reserved2:6;        // bits 26-31
+#endif
+       } bits;
+} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
+
+/*
+ * structure for space availiable reg in rxmac address map.
+ * located at address 0x4094
+ */
+typedef union _RXMAC_SPACE_AVAIL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved2:15;               // bits 17-31
+               u32 space_avail_en:1;   // bit 16
+               u32 reserved1:6;                // bits 10-15
+               u32 space_avail:10;     // bits 0-9
+#else
+               u32 space_avail:10;     // bits 0-9
+               u32 reserved1:6;                // bits 10-15
+               u32 space_avail_en:1;   // bit 16
+               u32 reserved2:15;               // bits 17-31
+#endif
+       } bits;
+} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
+
+/*
+ * structure for management interface reg in rxmac address map.
+ * located at address 0x4098
+ */
+typedef union _RXMAC_MIF_CTL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserve:14;         // bits 18-31
+               u32 drop_pkt_en:1;              // bit 17
+               u32 drop_pkt_mask:17;   // bits 0-16
+#else
+               u32 drop_pkt_mask:17;   // bits 0-16
+               u32 drop_pkt_en:1;              // bit 17
+               u32 reserve:14;         // bits 18-31
+#endif
+       } bits;
+} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
+
+/*
+ * structure for Error reg in rxmac address map.
+ * located at address 0x409C
+ */
+typedef union _RXMAC_ERROR_REG_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserve:28; // bits 4-31
+               u32 mif:1;              // bit 3
+               u32 async:1;    // bit 2
+               u32 pkt_filter:1;       // bit 1
+               u32 mcif:1;     // bit 0
+#else
+               u32 mcif:1;     // bit 0
+               u32 pkt_filter:1;       // bit 1
+               u32 async:1;    // bit 2
+               u32 mif:1;              // bit 3
+               u32 reserve:28; // bits 4-31
+#endif
+       } bits;
+} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
+
+/*
+ * Rx MAC Module of JAGCore Address Mapping
+ */
+typedef struct _RXMAC_t {                              // Location:
+       RXMAC_CTRL_t ctrl;                              //  0x4000
+       RXMAC_WOL_CTL_CRC0_t crc0;                      //  0x4004
+       RXMAC_WOL_CRC12_t crc12;                        //  0x4008
+       RXMAC_WOL_CRC34_t crc34;                        //  0x400C
+       RXMAC_WOL_SA_LO_t sa_lo;                        //  0x4010
+       RXMAC_WOL_SA_HI_t sa_hi;                        //  0x4014
+       u32 mask0_word0;                                //  0x4018
+       u32 mask0_word1;                                //  0x401C
+       u32 mask0_word2;                                //  0x4020
+       u32 mask0_word3;                                //  0x4024
+       u32 mask1_word0;                                //  0x4028
+       u32 mask1_word1;                                //  0x402C
+       u32 mask1_word2;                                //  0x4030
+       u32 mask1_word3;                                //  0x4034
+       u32 mask2_word0;                                //  0x4038
+       u32 mask2_word1;                                //  0x403C
+       u32 mask2_word2;                                //  0x4040
+       u32 mask2_word3;                                //  0x4044
+       u32 mask3_word0;                                //  0x4048
+       u32 mask3_word1;                                //  0x404C
+       u32 mask3_word2;                                //  0x4050
+       u32 mask3_word3;                                //  0x4054
+       u32 mask4_word0;                                //  0x4058
+       u32 mask4_word1;                                //  0x405C
+       u32 mask4_word2;                                //  0x4060
+       u32 mask4_word3;                                //  0x4064
+       RXMAC_UNI_PF_ADDR1_t uni_pf_addr1;              //  0x4068
+       RXMAC_UNI_PF_ADDR2_t uni_pf_addr2;              //  0x406C
+       RXMAC_UNI_PF_ADDR3_t uni_pf_addr3;              //  0x4070
+       u32 multi_hash1;                                //  0x4074
+       u32 multi_hash2;                                //  0x4078
+       u32 multi_hash3;                                //  0x407C
+       u32 multi_hash4;                                //  0x4080
+       RXMAC_PF_CTRL_t pf_ctrl;                        //  0x4084
+       RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;    //  0x4088
+       RXMAC_MCIF_WATER_MARK_t mcif_water_mark;        //  0x408C
+       RXMAC_RXQ_DIAG_t rxq_diag;                      //  0x4090
+       RXMAC_SPACE_AVAIL_t space_avail;                //  0x4094
+
+       RXMAC_MIF_CTL_t mif_ctrl;                       //  0x4098
+       RXMAC_ERROR_REG_t err_reg;                      //  0x409C
+} RXMAC_t, *PRXMAC_t;
+
+/* END OF TXMAC REGISTER ADDRESS MAP */
+
+
+/* START OF MAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for configuration #1 reg in mac address map.
+ * located at address 0x5000
+ */
+typedef union _MAC_CFG1_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 soft_reset:1;               // bit 31
+               u32 sim_reset:1;                // bit 30
+               u32 reserved3:10;               // bits 20-29
+               u32 reset_rx_mc:1;              // bit 19
+               u32 reset_tx_mc:1;              // bit 18
+               u32 reset_rx_fun:1;     // bit 17
+               u32 reset_tx_fun:1;     // bit 16
+               u32 reserved2:7;                // bits 9-15
+               u32 loop_back:1;                // bit 8
+               u32 reserved1:2;                // bits 6-7
+               u32 rx_flow:1;          // bit 5
+               u32 tx_flow:1;          // bit 4
+               u32 syncd_rx_en:1;              // bit 3
+               u32 rx_enable:1;                // bit 2
+               u32 syncd_tx_en:1;              // bit 1
+               u32 tx_enable:1;                // bit 0
+#else
+               u32 tx_enable:1;                // bit 0
+               u32 syncd_tx_en:1;              // bit 1
+               u32 rx_enable:1;                // bit 2
+               u32 syncd_rx_en:1;              // bit 3
+               u32 tx_flow:1;          // bit 4
+               u32 rx_flow:1;          // bit 5
+               u32 reserved1:2;                // bits 6-7
+               u32 loop_back:1;                // bit 8
+               u32 reserved2:7;                // bits 9-15
+               u32 reset_tx_fun:1;     // bit 16
+               u32 reset_rx_fun:1;     // bit 17
+               u32 reset_tx_mc:1;              // bit 18
+               u32 reset_rx_mc:1;              // bit 19
+               u32 reserved3:10;               // bits 20-29
+               u32 sim_reset:1;                // bit 30
+               u32 soft_reset:1;               // bit 31
+#endif
+       } bits;
+} MAC_CFG1_t, *PMAC_CFG1_t;
+
+/*
+ * structure for configuration #2 reg in mac address map.
+ * located at address 0x5004
+ */
+typedef union _MAC_CFG2_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved3:16;               // bits 16-31
+               u32 preamble_len:4;     // bits 12-15
+               u32 reserved2:2;                // bits 10-11
+               u32 if_mode:2;          // bits 8-9
+               u32 reserved1:2;                // bits 6-7
+               u32 huge_frame:1;               // bit 5
+               u32 len_check:1;                // bit 4
+               u32 undefined:1;                // bit 3
+               u32 pad_crc:1;          // bit 2
+               u32 crc_enable:1;               // bit 1
+               u32 full_duplex:1;              // bit 0
+#else
+               u32 full_duplex:1;              // bit 0
+               u32 crc_enable:1;               // bit 1
+               u32 pad_crc:1;          // bit 2
+               u32 undefined:1;                // bit 3
+               u32 len_check:1;                // bit 4
+               u32 huge_frame:1;               // bit 5
+               u32 reserved1:2;                // bits 6-7
+               u32 if_mode:2;          // bits 8-9
+               u32 reserved2:2;                // bits 10-11
+               u32 preamble_len:4;     // bits 12-15
+               u32 reserved3:16;               // bits 16-31
+#endif
+       } bits;
+} MAC_CFG2_t, *PMAC_CFG2_t;
+
+/*
+ * structure for Interpacket gap reg in mac address map.
+ * located at address 0x5008
+ */
+typedef union _MAC_IPG_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:1;         // bit 31
+               u32 non_B2B_ipg_1:7;    // bits 24-30
+               u32 undefined2:1;               // bit 23
+               u32 non_B2B_ipg_2:7;    // bits 16-22
+               u32 min_ifg_enforce:8;  // bits 8-15
+               u32 undefined1:1;               // bit 7
+               u32 B2B_ipg:7;          // bits 0-6
+#else
+               u32 B2B_ipg:7;          // bits 0-6
+               u32 undefined1:1;               // bit 7
+               u32 min_ifg_enforce:8;  // bits 8-15
+               u32 non_B2B_ipg_2:7;    // bits 16-22
+               u32 undefined2:1;               // bit 23
+               u32 non_B2B_ipg_1:7;    // bits 24-30
+               u32 reserved:1;         // bit 31
+#endif
+       } bits;
+} MAC_IPG_t, *PMAC_IPG_t;
+
+/*
+ * structure for half duplex reg in mac address map.
+ * located at address 0x500C
+ */
+typedef union _MAC_HFDP_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved2:8;                // bits 24-31
+               u32 alt_beb_trunc:4;    // bits 23-20
+               u32 alt_beb_enable:1;   // bit 19
+               u32 bp_no_backoff:1;    // bit 18
+               u32 no_backoff:1;               // bit 17
+               u32 excess_defer:1;     // bit 16
+               u32 rexmit_max:4;               // bits 12-15
+               u32 reserved1:2;                // bits 10-11
+               u32 coll_window:10;     // bits 0-9
+#else
+               u32 coll_window:10;     // bits 0-9
+               u32 reserved1:2;                // bits 10-11
+               u32 rexmit_max:4;               // bits 12-15
+               u32 excess_defer:1;     // bit 16
+               u32 no_backoff:1;               // bit 17
+               u32 bp_no_backoff:1;    // bit 18
+               u32 alt_beb_enable:1;   // bit 19
+               u32 alt_beb_trunc:4;    // bits 23-20
+               u32 reserved2:8;                // bits 24-31
+#endif
+       } bits;
+} MAC_HFDP_t, *PMAC_HFDP_t;
+
+/*
+ * structure for Maximum Frame Length reg in mac address map.
+ * located at address 0x5010
+ */
+typedef union _MAC_MAX_FM_LEN_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:16;        // bits 16-31
+               u32 max_len:16; // bits 0-15
+#else
+               u32 max_len:16; // bits 0-15
+               u32 reserved:16;        // bits 16-31
+#endif
+       } bits;
+} MAC_MAX_FM_LEN_t, *PMAC_MAX_FM_LEN_t;
+
+/*
+ * structure for Reserve 1 reg in mac address map.
+ * located at address 0x5014 - 0x5018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Test reg in mac address map.
+ * located at address 0x501C
+ */
+typedef union _MAC_TEST_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:29;  // bits 3-31
+               u32 mac_test:3; // bits 0-2
+#else
+               u32 mac_test:3; // bits 0-2
+               u32 unused:29;  // bits 3-31
+#endif
+       } bits;
+} MAC_TEST_t, *PMAC_TEST_t;
+
+/*
+ * structure for MII Management Configuration reg in mac address map.
+ * located at address 0x5020
+ */
+typedef union _MII_MGMT_CFG_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reset_mii_mgmt:1;   // bit 31
+               u32 reserved:25;                // bits 6-30
+               u32 scan_auto_incremt:1;        // bit 5
+               u32 preamble_suppress:1;        // bit 4
+               u32 undefined:1;                // bit 3
+               u32 mgmt_clk_reset:3;   // bits 0-2
+#else
+               u32 mgmt_clk_reset:3;   // bits 0-2
+               u32 undefined:1;                // bit 3
+               u32 preamble_suppress:1;        // bit 4
+               u32 scan_auto_incremt:1;        // bit 5
+               u32 reserved:25;                // bits 6-30
+               u32 reset_mii_mgmt:1;   // bit 31
+#endif
+       } bits;
+} MII_MGMT_CFG_t, *PMII_MGMT_CFG_t;
+
+/*
+ * structure for MII Management Command reg in mac address map.
+ * located at address 0x5024
+ */
+typedef union _MII_MGMT_CMD_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:30;        // bits 2-31
+               u32 scan_cycle:1;       // bit 1
+               u32 read_cycle:1;       // bit 0
+#else
+               u32 read_cycle:1;       // bit 0
+               u32 scan_cycle:1;       // bit 1
+               u32 reserved:30;        // bits 2-31
+#endif
+       } bits;
+} MII_MGMT_CMD_t, *PMII_MGMT_CMD_t;
+
+/*
+ * structure for MII Management Address reg in mac address map.
+ * located at address 0x5028
+ */
+typedef union _MII_MGMT_ADDR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved2:19;       // bit 13-31
+               u32 phy_addr:5; // bits 8-12
+               u32 reserved1:3;        // bits 5-7
+               u32 reg_addr:5; // bits 0-4
+#else
+               u32 reg_addr:5; // bits 0-4
+               u32 reserved1:3;        // bits 5-7
+               u32 phy_addr:5; // bits 8-12
+               u32 reserved2:19;       // bit 13-31
+#endif
+       } bits;
+} MII_MGMT_ADDR_t, *PMII_MGMT_ADDR_t;
+
+/*
+ * structure for MII Management Control reg in mac address map.
+ * located at address 0x502C
+ */
+typedef union _MII_MGMT_CTRL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:16;        // bits 16-31
+               u32 phy_ctrl:16;        // bits 0-15
+#else
+               u32 phy_ctrl:16;        // bits 0-15
+               u32 reserved:16;        // bits 16-31
+#endif
+       } bits;
+} MII_MGMT_CTRL_t, *PMII_MGMT_CTRL_t;
+
+/*
+ * structure for MII Management Status reg in mac address map.
+ * located at address 0x5030
+ */
+typedef union _MII_MGMT_STAT_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:16;        // bits 16-31
+               u32 phy_stat:16;        // bits 0-15
+#else
+               u32 phy_stat:16;        // bits 0-15
+               u32 reserved:16;        // bits 16-31
+#endif
+       } bits;
+} MII_MGMT_STAT_t, *PMII_MGMT_STAT_t;
+
+/*
+ * structure for MII Management Indicators reg in mac address map.
+ * located at address 0x5034
+ */
+typedef union _MII_MGMT_INDICATOR_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:29;        // bits 3-31
+               u32 not_valid:1;        // bit 2
+               u32 scanning:1; // bit 1
+               u32 busy:1;     // bit 0
+#else
+               u32 busy:1;     // bit 0
+               u32 scanning:1; // bit 1
+               u32 not_valid:1;        // bit 2
+               u32 reserved:29;        // bits 3-31
+#endif
+       } bits;
+} MII_MGMT_INDICATOR_t, *PMII_MGMT_INDICATOR_t;
+
+/*
+ * structure for Interface Control reg in mac address map.
+ * located at address 0x5038
+ */
+typedef union _MAC_IF_CTRL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reset_if_module:1;  // bit 31
+               u32 reserved4:3;                // bit 28-30
+               u32 tbi_mode:1;         // bit 27
+               u32 ghd_mode:1;         // bit 26
+               u32 lhd_mode:1;         // bit 25
+               u32 phy_mode:1;         // bit 24
+               u32 reset_per_mii:1;    // bit 23
+               u32 reserved3:6;                // bits 17-22
+               u32 speed:1;            // bit 16
+               u32 reset_pe100x:1;     // bit 15
+               u32 reserved2:4;                // bits 11-14
+               u32 force_quiet:1;              // bit 10
+               u32 no_cipher:1;                // bit 9
+               u32 disable_link_fail:1;        // bit 8
+               u32 reset_gpsi:1;               // bit 7
+               u32 reserved1:6;                // bits 1-6
+               u32 enab_jab_protect:1; // bit 0
+#else
+               u32 enab_jab_protect:1; // bit 0
+               u32 reserved1:6;                // bits 1-6
+               u32 reset_gpsi:1;               // bit 7
+               u32 disable_link_fail:1;        // bit 8
+               u32 no_cipher:1;                // bit 9
+               u32 force_quiet:1;              // bit 10
+               u32 reserved2:4;                // bits 11-14
+               u32 reset_pe100x:1;     // bit 15
+               u32 speed:1;            // bit 16
+               u32 reserved3:6;                // bits 17-22
+               u32 reset_per_mii:1;    // bit 23
+               u32 phy_mode:1;         // bit 24
+               u32 lhd_mode:1;         // bit 25
+               u32 ghd_mode:1;         // bit 26
+               u32 tbi_mode:1;         // bit 27
+               u32 reserved4:3;                // bit 28-30
+               u32 reset_if_module:1;  // bit 31
+#endif
+       } bits;
+} MAC_IF_CTRL_t, *PMAC_IF_CTRL_t;
+
+/*
+ * structure for Interface Status reg in mac address map.
+ * located at address 0x503C
+ */
+typedef union _MAC_IF_STAT_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:22;                // bits 10-31
+               u32 excess_defer:1;     // bit 9
+               u32 clash:1;            // bit 8
+               u32 phy_jabber:1;               // bit 7
+               u32 phy_link_ok:1;              // bit 6
+               u32 phy_full_duplex:1;  // bit 5
+               u32 phy_speed:1;                // bit 4
+               u32 pe100x_link_fail:1; // bit 3
+               u32 pe10t_loss_carrie:1;        // bit 2
+               u32 pe10t_sqe_error:1;  // bit 1
+               u32 pe10t_jabber:1;     // bit 0
+#else
+               u32 pe10t_jabber:1;     // bit 0
+               u32 pe10t_sqe_error:1;  // bit 1
+               u32 pe10t_loss_carrie:1;        // bit 2
+               u32 pe100x_link_fail:1; // bit 3
+               u32 phy_speed:1;                // bit 4
+               u32 phy_full_duplex:1;  // bit 5
+               u32 phy_link_ok:1;              // bit 6
+               u32 phy_jabber:1;               // bit 7
+               u32 clash:1;            // bit 8
+               u32 excess_defer:1;     // bit 9
+               u32 reserved:22;                // bits 10-31
+#endif
+       } bits;
+} MAC_IF_STAT_t, *PMAC_IF_STAT_t;
+
+/*
+ * structure for Mac Station Address, Part 1 reg in mac address map.
+ * located at address 0x5040
+ */
+typedef union _MAC_STATION_ADDR1_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 Octet6:8;   // bits 24-31
+               u32 Octet5:8;   // bits 16-23
+               u32 Octet4:8;   // bits 8-15
+               u32 Octet3:8;   // bits 0-7
+#else
+               u32 Octet3:8;   // bits 0-7
+               u32 Octet4:8;   // bits 8-15
+               u32 Octet5:8;   // bits 16-23
+               u32 Octet6:8;   // bits 24-31
+#endif
+       } bits;
+} MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
+
+/*
+ * structure for Mac Station Address, Part 2 reg in mac address map.
+ * located at address 0x5044
+ */
+typedef union _MAC_STATION_ADDR2_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 Octet2:8;   // bits 24-31
+               u32 Octet1:8;   // bits 16-23
+               u32 reserved:16;        // bits 0-15
+#else
+               u32 reserved:16;        // bit 0-15
+               u32 Octet1:8;   // bits 16-23
+               u32 Octet2:8;   // bits 24-31
+#endif
+       } bits;
+} MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
+
+/*
+ * MAC Module of JAGCore Address Mapping
+ */
+typedef struct _MAC_t {                                        // Location:
+       MAC_CFG1_t cfg1;                                //  0x5000
+       MAC_CFG2_t cfg2;                                //  0x5004
+       MAC_IPG_t ipg;                                  //  0x5008
+       MAC_HFDP_t hfdp;                                //  0x500C
+       MAC_MAX_FM_LEN_t max_fm_len;                    //  0x5010
+       u32 rsv1;                                       //  0x5014
+       u32 rsv2;                                       //  0x5018
+       MAC_TEST_t mac_test;                            //  0x501C
+       MII_MGMT_CFG_t mii_mgmt_cfg;                    //  0x5020
+       MII_MGMT_CMD_t mii_mgmt_cmd;                    //  0x5024
+       MII_MGMT_ADDR_t mii_mgmt_addr;                  //  0x5028
+       MII_MGMT_CTRL_t mii_mgmt_ctrl;                  //  0x502C
+       MII_MGMT_STAT_t mii_mgmt_stat;                  //  0x5030
+       MII_MGMT_INDICATOR_t mii_mgmt_indicator;        //  0x5034
+       MAC_IF_CTRL_t if_ctrl;                          //  0x5038
+       MAC_IF_STAT_t if_stat;                          //  0x503C
+       MAC_STATION_ADDR1_t station_addr_1;             //  0x5040
+       MAC_STATION_ADDR2_t station_addr_2;             //  0x5044
+} MAC_t, *PMAC_t;
+
+/* END OF MAC REGISTER ADDRESS MAP */
+
+/* START OF MAC STAT REGISTER ADDRESS MAP */
+
+/*
+ * structure for Carry Register One and it's Mask Register reg located in mac
+ * stat address map address 0x6130 and 0x6138.
+ */
+typedef union _MAC_STAT_REG_1_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 tr64:1;     // bit 31
+               u32 tr127:1;    // bit 30
+               u32 tr255:1;    // bit 29
+               u32 tr511:1;    // bit 28
+               u32 tr1k:1;     // bit 27
+               u32 trmax:1;    // bit 26
+               u32 trmgv:1;    // bit 25
+               u32 unused:8;   // bits 17-24
+               u32 rbyt:1;     // bit 16
+               u32 rpkt:1;     // bit 15
+               u32 rfcs:1;     // bit 14
+               u32 rmca:1;     // bit 13
+               u32 rbca:1;     // bit 12
+               u32 rxcf:1;     // bit 11
+               u32 rxpf:1;     // bit 10
+               u32 rxuo:1;     // bit 9
+               u32 raln:1;     // bit 8
+               u32 rflr:1;     // bit 7
+               u32 rcde:1;     // bit 6
+               u32 rcse:1;     // bit 5
+               u32 rund:1;     // bit 4
+               u32 rovr:1;     // bit 3
+               u32 rfrg:1;     // bit 2
+               u32 rjbr:1;     // bit 1
+               u32 rdrp:1;     // bit 0
+#else
+               u32 rdrp:1;     // bit 0
+               u32 rjbr:1;     // bit 1
+               u32 rfrg:1;     // bit 2
+               u32 rovr:1;     // bit 3
+               u32 rund:1;     // bit 4
+               u32 rcse:1;     // bit 5
+               u32 rcde:1;     // bit 6
+               u32 rflr:1;     // bit 7
+               u32 raln:1;     // bit 8
+               u32 rxuo:1;     // bit 9
+               u32 rxpf:1;     // bit 10
+               u32 rxcf:1;     // bit 11
+               u32 rbca:1;     // bit 12
+               u32 rmca:1;     // bit 13
+               u32 rfcs:1;     // bit 14
+               u32 rpkt:1;     // bit 15
+               u32 rbyt:1;     // bit 16
+               u32 unused:8;   // bits 17-24
+               u32 trmgv:1;    // bit 25
+               u32 trmax:1;    // bit 26
+               u32 tr1k:1;     // bit 27
+               u32 tr511:1;    // bit 28
+               u32 tr255:1;    // bit 29
+               u32 tr127:1;    // bit 30
+               u32 tr64:1;     // bit 31
+#endif
+       } bits;
+} MAC_STAT_REG_1_t, *PMAC_STAT_REG_1_t;
+
+/*
+ * structure for Carry Register Two Mask Register reg in mac stat address map.
+ * located at address 0x613C
+ */
+typedef union _MAC_STAT_REG_2_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 unused:12;  // bit 20-31
+               u32 tjbr:1;     // bit 19
+               u32 tfcs:1;     // bit 18
+               u32 txcf:1;     // bit 17
+               u32 tovr:1;     // bit 16
+               u32 tund:1;     // bit 15
+               u32 tfrg:1;     // bit 14
+               u32 tbyt:1;     // bit 13
+               u32 tpkt:1;     // bit 12
+               u32 tmca:1;     // bit 11
+               u32 tbca:1;     // bit 10
+               u32 txpf:1;     // bit 9
+               u32 tdfr:1;     // bit 8
+               u32 tedf:1;     // bit 7
+               u32 tscl:1;     // bit 6
+               u32 tmcl:1;     // bit 5
+               u32 tlcl:1;     // bit 4
+               u32 txcl:1;     // bit 3
+               u32 tncl:1;     // bit 2
+               u32 tpfh:1;     // bit 1
+               u32 tdrp:1;     // bit 0
+#else
+               u32 tdrp:1;     // bit 0
+               u32 tpfh:1;     // bit 1
+               u32 tncl:1;     // bit 2
+               u32 txcl:1;     // bit 3
+               u32 tlcl:1;     // bit 4
+               u32 tmcl:1;     // bit 5
+               u32 tscl:1;     // bit 6
+               u32 tedf:1;     // bit 7
+               u32 tdfr:1;     // bit 8
+               u32 txpf:1;     // bit 9
+               u32 tbca:1;     // bit 10
+               u32 tmca:1;     // bit 11
+               u32 tpkt:1;     // bit 12
+               u32 tbyt:1;     // bit 13
+               u32 tfrg:1;     // bit 14
+               u32 tund:1;     // bit 15
+               u32 tovr:1;     // bit 16
+               u32 txcf:1;     // bit 17
+               u32 tfcs:1;     // bit 18
+               u32 tjbr:1;     // bit 19
+               u32 unused:12;  // bit 20-31
+#endif
+       } bits;
+} MAC_STAT_REG_2_t, *PMAC_STAT_REG_2_t;
+
+/*
+ * MAC STATS Module of JAGCore Address Mapping
+ */
+typedef struct _MAC_STAT_t {           // Location:
+       u32 pad[32];            //  0x6000 - 607C
+
+       // Tx/Rx 0-64 Byte Frame Counter
+       u32 TR64;                       //  0x6080
+
+       // Tx/Rx 65-127 Byte Frame Counter
+       u32 TR127;                      //  0x6084
+
+       // Tx/Rx 128-255 Byte Frame Counter
+       u32 TR255;                      //  0x6088
+
+       // Tx/Rx 256-511 Byte Frame Counter
+       u32 TR511;                      //  0x608C
+
+       // Tx/Rx 512-1023 Byte Frame Counter
+       u32 TR1K;                       //  0x6090
+
+       // Tx/Rx 1024-1518 Byte Frame Counter
+       u32 TRMax;                      //  0x6094
+
+       // Tx/Rx 1519-1522 Byte Good VLAN Frame Count
+       u32 TRMgv;                      //  0x6098
+
+       // Rx Byte Counter
+       u32 RByt;                       //  0x609C
+
+       // Rx Packet Counter
+       u32 RPkt;                       //  0x60A0
+
+       // Rx FCS Error Counter
+       u32 RFcs;                       //  0x60A4
+
+       // Rx Multicast Packet Counter
+       u32 RMca;                       //  0x60A8
+
+       // Rx Broadcast Packet Counter
+       u32 RBca;                       //  0x60AC
+
+       // Rx Control Frame Packet Counter
+       u32 RxCf;                       //  0x60B0
+
+       // Rx Pause Frame Packet Counter
+       u32 RxPf;                       //  0x60B4
+
+       // Rx Unknown OP Code Counter
+       u32 RxUo;                       //  0x60B8
+
+       // Rx Alignment Error Counter
+       u32 RAln;                       //  0x60BC
+
+       // Rx Frame Length Error Counter
+       u32 RFlr;                       //  0x60C0
+
+       // Rx Code Error Counter
+       u32 RCde;                       //  0x60C4
+
+       // Rx Carrier Sense Error Counter
+       u32 RCse;                       //  0x60C8
+
+       // Rx Undersize Packet Counter
+       u32 RUnd;                       //  0x60CC
+
+       // Rx Oversize Packet Counter
+       u32 ROvr;                       //  0x60D0
+
+       // Rx Fragment Counter
+       u32 RFrg;                       //  0x60D4
+
+       // Rx Jabber Counter
+       u32 RJbr;                       //  0x60D8
+
+       // Rx Drop
+       u32 RDrp;                       //  0x60DC
+
+       // Tx Byte Counter
+       u32 TByt;                       //  0x60E0
+
+       // Tx Packet Counter
+       u32 TPkt;                       //  0x60E4
+
+       // Tx Multicast Packet Counter
+       u32 TMca;                       //  0x60E8
+
+       // Tx Broadcast Packet Counter
+       u32 TBca;                       //  0x60EC
+
+       // Tx Pause Control Frame Counter
+       u32 TxPf;                       //  0x60F0
+
+       // Tx Deferral Packet Counter
+       u32 TDfr;                       //  0x60F4
+
+       // Tx Excessive Deferral Packet Counter
+       u32 TEdf;                       //  0x60F8
+
+       // Tx Single Collision Packet Counter
+       u32 TScl;                       //  0x60FC
+
+       // Tx Multiple Collision Packet Counter
+       u32 TMcl;                       //  0x6100
+
+       // Tx Late Collision Packet Counter
+       u32 TLcl;                       //  0x6104
+
+       // Tx Excessive Collision Packet Counter
+       u32 TXcl;                       //  0x6108
+
+       // Tx Total Collision Packet Counter
+       u32 TNcl;                       //  0x610C
+
+       // Tx Pause Frame Honored Counter
+       u32 TPfh;                       //  0x6110
+
+       // Tx Drop Frame Counter
+       u32 TDrp;                       //  0x6114
+
+       // Tx Jabber Frame Counter
+       u32 TJbr;                       //  0x6118
+
+       // Tx FCS Error Counter
+       u32 TFcs;                       //  0x611C
+
+       // Tx Control Frame Counter
+       u32 TxCf;                       //  0x6120
+
+       // Tx Oversize Frame Counter
+       u32 TOvr;                       //  0x6124
+
+       // Tx Undersize Frame Counter
+       u32 TUnd;                       //  0x6128
+
+       // Tx Fragments Frame Counter
+       u32 TFrg;                       //  0x612C
+
+       // Carry Register One Register
+       MAC_STAT_REG_1_t Carry1;        //  0x6130
+
+       // Carry Register Two Register
+       MAC_STAT_REG_2_t Carry2;        //  0x6134
+
+       // Carry Register One Mask Register
+       MAC_STAT_REG_1_t Carry1M;       //  0x6138
+
+       // Carry Register Two Mask Register
+       MAC_STAT_REG_2_t Carry2M;       //  0x613C
+} MAC_STAT_t, *PMAC_STAT_t;
+
+/* END OF MAC STAT REGISTER ADDRESS MAP */
+
+
+/* START OF MMC REGISTER ADDRESS MAP */
+
+/*
+ * structure for Main Memory Controller Control reg in mmc address map.
+ * located at address 0x7000
+ */
+typedef union _MMC_CTRL_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 reserved:25;                // bits 7-31
+               u32 force_ce:1;         // bit 6
+               u32 rxdma_disable:1;    // bit 5
+               u32 txdma_disable:1;    // bit 4
+               u32 txmac_disable:1;    // bit 3
+               u32 rxmac_disable:1;    // bit 2
+               u32 arb_disable:1;              // bit 1
+               u32 mmc_enable:1;               // bit 0
+#else
+               u32 mmc_enable:1;               // bit 0
+               u32 arb_disable:1;              // bit 1
+               u32 rxmac_disable:1;    // bit 2
+               u32 txmac_disable:1;    // bit 3
+               u32 txdma_disable:1;    // bit 4
+               u32 rxdma_disable:1;    // bit 5
+               u32 force_ce:1;         // bit 6
+               u32 reserved:25;                // bits 7-31
+#endif
+       } bits;
+} MMC_CTRL_t, *PMMC_CTRL_t;
+
+/*
+ * structure for Main Memory Controller Host Memory Access Address reg in mmc
+ * address map.  Located at address 0x7004
+ */
+typedef union _MMC_SRAM_ACCESS_t {
+       u32 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u32 byte_enable:16;     // bits 16-31
+               u32 reserved2:2;                // bits 14-15
+               u32 req_addr:10;                // bits 4-13
+               u32 reserved1:1;                // bit 3
+               u32 is_ctrl_word:1;     // bit 2
+               u32 wr_access:1;                // bit 1
+               u32 req_access:1;               // bit 0
+#else
+               u32 req_access:1;               // bit 0
+               u32 wr_access:1;                // bit 1
+               u32 is_ctrl_word:1;     // bit 2
+               u32 reserved1:1;                // bit 3
+               u32 req_addr:10;                // bits 4-13
+               u32 reserved2:2;                // bits 14-15
+               u32 byte_enable:16;     // bits 16-31
+#endif
+       } bits;
+} MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t;
+
+/*
+ * structure for Main Memory Controller Host Memory Access Data reg in mmc
+ * address map.  Located at address 0x7008 - 0x7014
+ * Defined earlier (u32)
+ */
+
+/*
+ * Memory Control Module of JAGCore Address Mapping
+ */
+typedef struct _MMC_t {                        // Location:
+       MMC_CTRL_t mmc_ctrl;            //  0x7000
+       MMC_SRAM_ACCESS_t sram_access;  //  0x7004
+       u32 sram_word1;         //  0x7008
+       u32 sram_word2;         //  0x700C
+       u32 sram_word3;         //  0x7010
+       u32 sram_word4;         //  0x7014
+} MMC_t, *PMMC_t;
+
+/* END OF MMC REGISTER ADDRESS MAP */
+
+
+/* START OF EXP ROM REGISTER ADDRESS MAP */
+
+/*
+ * Expansion ROM Module of JAGCore Address Mapping
+ */
+
+/* Take this out until it is not empty */
+#if 0
+typedef struct _EXP_ROM_t {
+
+} EXP_ROM_t, *PEXP_ROM_t;
+#endif
+
+/* END OF EXP ROM REGISTER ADDRESS MAP */
+
+
+/*
+ * JAGCore Address Mapping
+ */
+typedef struct _ADDRESS_MAP_t {
+       GLOBAL_t global;
+       // unused section of global address map
+       u8 unused_global[4096 - sizeof(GLOBAL_t)];
+       TXDMA_t txdma;
+       // unused section of txdma address map
+       u8 unused_txdma[4096 - sizeof(TXDMA_t)];
+       RXDMA_t rxdma;
+       // unused section of rxdma address map
+       u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
+       TXMAC_t txmac;
+       // unused section of txmac address map
+       u8 unused_txmac[4096 - sizeof(TXMAC_t)];
+       RXMAC_t rxmac;
+       // unused section of rxmac address map
+       u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
+       MAC_t mac;
+       // unused section of mac address map
+       u8 unused_mac[4096 - sizeof(MAC_t)];
+       MAC_STAT_t macStat;
+       // unused section of mac stat address map
+       u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
+       MMC_t mmc;
+       // unused section of mmc address map
+       u8 unused_mmc[4096 - sizeof(MMC_t)];
+       // unused section of address map
+       u8 unused_[1015808];
+
+/* Take this out until it is not empty */
+#if 0
+       EXP_ROM_t exp_rom;
+#endif
+
+       u8 unused_exp_rom[4096];        // MGS-size TBD
+       u8 unused__[524288];    // unused section of address map
+} ADDRESS_MAP_t, *PADDRESS_MAP_t;
+
+#endif /* _ET1310_ADDRESS_MAP_H_ */
diff --git a/src/et131x/et1310_eeprom.c b/src/et131x/et1310_eeprom.c
new file mode 100644 (file)
index 0000000..c2b194e
--- /dev/null
@@ -0,0 +1,480 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_eeprom.c - Code used to access the device's EEPROM
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_debug.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et1310_pm.h"
+#include "et1310_jagcore.h"
+#include "et1310_eeprom.h"
+
+#include "et131x_adapter.h"
+#include "et131x_initpci.h"
+#include "et131x_isr.h"
+
+#include "et1310_tx.h"
+
+
+/*
+ * EEPROM Defines
+ */
+
+/* LBCIF Register Groups (addressed via 32-bit offsets) */
+#define LBCIF_DWORD0_GROUP_OFFSET       0xAC
+#define LBCIF_DWORD1_GROUP_OFFSET       0xB0
+
+/* LBCIF Registers (addressed via 8-bit offsets) */
+#define LBCIF_ADDRESS_REGISTER_OFFSET   0xAC
+#define LBCIF_DATA_REGISTER_OFFSET      0xB0
+#define LBCIF_CONTROL_REGISTER_OFFSET   0xB1
+#define LBCIF_STATUS_REGISTER_OFFSET    0xB2
+
+/* LBCIF Control Register Bits */
+#define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
+#define LBCIF_CONTROL_PAGE_WRITE        0x02
+#define LBCIF_CONTROL_UNUSED1           0x04
+#define LBCIF_CONTROL_EEPROM_RELOAD     0x08
+#define LBCIF_CONTROL_UNUSED2           0x10
+#define LBCIF_CONTROL_TWO_BYTE_ADDR     0x20
+#define LBCIF_CONTROL_I2C_WRITE         0x40
+#define LBCIF_CONTROL_LBCIF_ENABLE      0x80
+
+/* LBCIF Status Register Bits */
+#define LBCIF_STATUS_PHY_QUEUE_AVAIL    0x01
+#define LBCIF_STATUS_I2C_IDLE           0x02
+#define LBCIF_STATUS_ACK_ERROR          0x04
+#define LBCIF_STATUS_GENERAL_ERROR      0x08
+#define LBCIF_STATUS_UNUSED             0x30
+#define LBCIF_STATUS_CHECKSUM_ERROR     0x40
+#define LBCIF_STATUS_EEPROM_PRESENT     0x80
+
+/* Miscellaneous Constraints */
+#define MAX_NUM_REGISTER_POLLS          1000
+#define MAX_NUM_WRITE_RETRIES           2
+
+/*
+ * Define macros that allow individual register values to be extracted from a
+ * DWORD1 register grouping
+ */
+#define EXTRACT_DATA_REGISTER(x)    (uint8_t)(x & 0xFF)
+#define EXTRACT_STATUS_REGISTER(x)  (uint8_t)((x >> 16) & 0xFF)
+#define EXTRACT_CONTROL_REG(x)      (uint8_t)((x >> 8) & 0xFF)
+
+/**
+ * EepromWriteByte - Write a byte to the ET1310's EEPROM
+ * @pAdapter: pointer to our private adapter structure
+ * @unAddress: the address to write
+ * @bData: the value to write
+ * @unEepronId: the ID of the EEPROM
+ * @unAddressingMode: how the EEPROM is to be accessed
+ *
+ * Returns SUCCESS or FAILURE
+ */
+int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
+                       uint8_t bData, uint32_t unEepromId,
+                       uint32_t unAddressingMode)
+{
+        struct pci_dev *pdev = pAdapter->pdev;
+       int32_t nIndex;
+       int32_t nRetries;
+       int32_t nError = false;
+       int32_t nI2CWriteActive = 0;
+       int32_t nWriteSuccessful = 0;
+       uint8_t bControl;
+       uint8_t bStatus = 0;
+       uint32_t unDword1 = 0;
+       uint32_t unData = 0;
+
+       /*
+        * The following excerpt is from "Serial EEPROM HW Design
+        * Specification" Version 0.92 (9/20/2004):
+        *
+        * Single Byte Writes
+        *
+        * For an EEPROM, an I2C single byte write is defined as a START
+        * condition followed by the device address, EEPROM address, one byte
+        * of data and a STOP condition.  The STOP condition will trigger the
+        * EEPROM's internally timed write cycle to the nonvolatile memory.
+        * All inputs are disabled during this write cycle and the EEPROM will
+        * not respond to any access until the internal write is complete.
+        * The steps to execute a single byte write are as follows:
+        *
+        * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
+        *    bits 7,1:0 both equal to 1, at least once after reset.
+        *    Subsequent operations need only to check that bits 1:0 are
+        *    equal to 1 prior to starting a single byte write.
+        *
+        * 2. Write to the LBCIF Control Register:  bit 7=1, bit 6=1, bit 3=0,
+        *    and bits 1:0 both =0.  Bit 5 should be set according to the
+        *    type of EEPROM being accessed (1=two byte addressing, 0=one
+        *    byte addressing).
+        *
+        * 3. Write the address to the LBCIF Address Register.
+        *
+        * 4. Write the data to the LBCIF Data Register (the I2C write will
+        *    begin).
+        *
+        * 5. Monitor bit 1:0 of the LBCIF Status Register.  When bits 1:0 are
+        *    both equal to 1, the I2C write has completed and the internal
+        *    write cycle of the EEPROM is about to start. (bits 1:0 = 01 is
+        *    a legal state while waiting from both equal to 1, but bits
+        *    1:0 = 10 is invalid and implies that something is broken).
+        *
+        * 6. Check bit 3 of the LBCIF Status Register.  If  equal to 1, an
+        *    error has occurred.
+        *
+        * 7. Check bit 2 of the LBCIF Status Register.  If equal to 1 an ACK
+        *    error has occurred on the address phase of the write.  This
+        *    could be due to an actual hardware failure or the EEPROM may
+        *    still be in its internal write cycle from a previous write.
+        *    This write operation was ignored and must be repeated later.
+        *
+        * 8. Set bit 6 of the LBCIF Control Register = 0. If another write is
+        *    required, go to step 1.
+        */
+
+       /* Step 1: */
+       for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+               /* Read registers grouped in DWORD1 */
+               if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
+                                         &unDword1)) {
+                       nError = 1;
+                       break;
+               }
+
+               bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+
+               if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
+                   bStatus & LBCIF_STATUS_I2C_IDLE) {
+                       /* bits 1:0 are equal to 1 */
+                       break;
+               }
+       }
+
+       if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
+               return FAILURE;
+       }
+
+       /* Step 2: */
+       bControl = 0;
+       bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
+
+       if (unAddressingMode == DUAL_BYTE) {
+               bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
+       }
+
+       if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
+                                 bControl)) {
+               return FAILURE;
+       }
+
+       nI2CWriteActive = 1;
+
+       /* Prepare EEPROM address for Step 3 */
+       unAddress |= (unAddressingMode == DUAL_BYTE) ?
+           (unEepromId << 16) : (unEepromId << 8);
+
+       for (nRetries = 0; nRetries < MAX_NUM_WRITE_RETRIES; nRetries++) {
+               /* Step 3:*/
+               if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
+                                          unAddress)) {
+                       break;
+               }
+
+               /* Step 4: */
+               if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET,
+                                         bData)) {
+                       break;
+               }
+
+               /* Step 5: */
+               for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+                       /* Read registers grouped in DWORD1 */
+                       if (pci_read_config_dword(pdev,
+                                                 LBCIF_DWORD1_GROUP_OFFSET,
+                                                 &unDword1)) {
+                               nError = 1;
+                               break;
+                       }
+
+                       bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+
+                       if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
+                           bStatus & LBCIF_STATUS_I2C_IDLE) {
+                               /* I2C write complete */
+                               break;
+                       }
+               }
+
+               if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
+                       break;
+               }
+
+               /*
+                * Step 6: Don't break here if we are revision 1, this is
+                *         so we do a blind write for load bug.
+                */
+               if (bStatus & LBCIF_STATUS_GENERAL_ERROR
+                   && pAdapter->RevisionID == 0) {
+                       break;
+               }
+
+               /* Step 7 */
+               if (bStatus & LBCIF_STATUS_ACK_ERROR) {
+                       /*
+                        * This could be due to an actual hardware failure
+                        * or the EEPROM may still be in its internal write
+                        * cycle from a previous write. This write operation
+                        * was ignored and must be repeated later.
+                        */
+                       udelay(10);
+                       continue;
+               }
+
+               nWriteSuccessful = 1;
+               break;
+       }
+
+       /* Step 8: */
+       udelay(10);
+       nIndex = 0;
+       while (nI2CWriteActive) {
+               bControl &= ~LBCIF_CONTROL_I2C_WRITE;
+
+               if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
+                                         bControl)) {
+                       nWriteSuccessful = 0;
+               }
+
+               /* Do read until internal ACK_ERROR goes away meaning write
+                * completed
+                */
+               do {
+                       pci_write_config_dword(pdev,
+                                              LBCIF_ADDRESS_REGISTER_OFFSET,
+                                              unAddress);
+                       do {
+                               pci_read_config_dword(pdev,
+                                       LBCIF_DATA_REGISTER_OFFSET, &unData);
+                       } while ((unData & 0x00010000) == 0);
+               } while (unData & 0x00040000);
+
+               bControl = EXTRACT_CONTROL_REG(unData);
+
+               if (bControl != 0xC0 || nIndex == 10000) {
+                       break;
+               }
+
+               nIndex++;
+       }
+
+       return nWriteSuccessful ? SUCCESS : FAILURE;
+}
+
+/**
+ * EepromReadByte - Read a byte from the ET1310's EEPROM
+ * @pAdapter: pointer to our private adapter structure
+ * @unAddress: the address from which to read
+ * @pbData: a pointer to a byte in which to store the value of the read
+ * @unEepronId: the ID of the EEPROM
+ * @unAddressingMode: how the EEPROM is to be accessed
+ *
+ * Returns SUCCESS or FAILURE
+ */
+int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
+                      uint8_t *pbData, uint32_t unEepromId,
+                      uint32_t unAddressingMode)
+{
+        struct pci_dev *pdev = pAdapter->pdev;
+       int32_t nIndex;
+       int32_t nError = 0;
+       uint8_t bControl;
+       uint8_t bStatus = 0;
+       uint32_t unDword1 = 0;
+
+       /*
+        * The following excerpt is from "Serial EEPROM HW Design
+        * Specification" Version 0.92 (9/20/2004):
+        *
+        * Single Byte Reads
+        *
+        * A single byte read is similar to the single byte write, with the
+        * exception of the data flow:
+        *
+        * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
+        *    bits 7,1:0 both equal to 1, at least once after reset.
+        *    Subsequent operations need only to check that bits 1:0 are equal
+        *    to 1 prior to starting a single byte read.
+        *
+        * 2. Write to the LBCIF Control Register:  bit 7=1, bit 6=0, bit 3=0,
+        *    and bits 1:0 both =0.  Bit 5 should be set according to the type
+        *    of EEPROM being accessed (1=two byte addressing, 0=one byte
+        *    addressing).
+        *
+        * 3. Write the address to the LBCIF Address Register (I2C read will
+        *    begin).
+        *
+        * 4. Monitor bit 0 of the LBCIF Status Register.  When =1, I2C read
+        *    is complete. (if bit 1 =1 and bit 0 stays =0, a hardware failure
+        *    has occurred).
+        *
+        * 5. Check bit 2 of the LBCIF Status Register.  If =1, then an error
+        *    has occurred.  The data that has been returned from the PHY may
+        *    be invalid.
+        *
+        * 6. Regardless of error status, read data byte from LBCIF Data
+        *    Register.  If another byte is required, go to step 1.
+        */
+
+       /* Step 1: */
+       for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+               /* Read registers grouped in DWORD1 */
+               if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
+                                         &unDword1)) {
+                       nError = 1;
+                       break;
+               }
+
+               bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+
+               if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
+                   bStatus & LBCIF_STATUS_I2C_IDLE) {
+                       /* bits 1:0 are equal to 1 */
+                       break;
+               }
+       }
+
+       if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
+               return FAILURE;
+       }
+
+       /* Step 2: */
+       bControl = 0;
+       bControl |= LBCIF_CONTROL_LBCIF_ENABLE;
+
+       if (unAddressingMode == DUAL_BYTE) {
+               bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
+       }
+
+       if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
+                                 bControl)) {
+               return FAILURE;
+       }
+
+       /* Step 3: */
+       unAddress |= (unAddressingMode == DUAL_BYTE) ?
+           (unEepromId << 16) : (unEepromId << 8);
+
+       if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
+                                  unAddress)) {
+               return FAILURE;
+       }
+
+       /* Step 4: */
+       for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+               /* Read registers grouped in DWORD1 */
+               if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
+                                         &unDword1)) {
+                       nError = 1;
+                       break;
+               }
+
+               bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+
+               if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL
+                   && bStatus & LBCIF_STATUS_I2C_IDLE) {
+                       /* I2C read complete */
+                       break;
+               }
+       }
+
+       if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
+               return FAILURE;
+       }
+
+       /* Step 6: */
+       *pbData = EXTRACT_DATA_REGISTER(unDword1);
+
+       return (bStatus & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;
+}
diff --git a/src/et131x/et1310_eeprom.h b/src/et131x/et1310_eeprom.h
new file mode 100644 (file)
index 0000000..9b6f8ad
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_eeprom.h - Defines, structs, enums, prototypes, etc. used for EEPROM
+ *                   access routines
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET1310_EEPROM_H__
+#define __ET1310_EEPROM_H__
+
+#include "et1310_address_map.h"
+
+#ifndef SUCCESS
+#define SUCCESS                0
+#define FAILURE                1
+#endif
+
+#ifndef READ
+#define READ           0
+#define WRITE          1
+#endif
+
+#ifndef SINGLE_BYTE
+#define SINGLE_BYTE    0
+#define DUAL_BYTE      1
+#endif
+
+/* Forward declaration of the private adapter structure */
+struct et131x_adapter;
+
+int32_t EepromWriteByte(struct et131x_adapter *adapter, u32 unAddress,
+                       u8 bData, u32 unEepromId,
+                       u32 unAddressingMode);
+int32_t EepromReadByte(struct et131x_adapter *adapter, u32 unAddress,
+                      u8 *pbData, u32 unEepromId,
+                      u32 unAddressingMode);
+
+#endif /* _ET1310_EEPROM_H_ */
diff --git a/src/et131x/et1310_jagcore.c b/src/et131x/et1310_jagcore.c
new file mode 100644 (file)
index 0000000..993b30e
--- /dev/null
@@ -0,0 +1,220 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_jagcore.c - All code pertaining to the ET1301/ET131x's JAGcore
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_debug.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et1310_pm.h"
+#include "et1310_jagcore.h"
+
+#include "et131x_adapter.h"
+#include "et131x_initpci.h"
+
+/* Data for debugging facilities */
+#ifdef CONFIG_ET131X_DEBUG
+extern dbg_info_t *et131x_dbginfo;
+#endif /* CONFIG_ET131X_DEBUG */
+
+/**
+ * ConfigGlobalRegs - Used to configure the global registers on the JAGCore
+ * @pAdpater: pointer to our adapter structure
+ */
+void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
+{
+       struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       if (pAdapter->RegistryPhyLoopbk == false) {
+               if (pAdapter->RegistryJumboPacket < 2048) {
+                       /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
+                        * block of RAM that the driver can split between Tx
+                        * and Rx as it desires.  Our default is to split it
+                        * 50/50:
+                        */
+                       writel(0, &pGbl->rxq_start_addr.value);
+                       writel(pAdapter->RegistryRxMemEnd,
+                              &pGbl->rxq_end_addr.value);
+                       writel(pAdapter->RegistryRxMemEnd + 1,
+                              &pGbl->txq_start_addr.value);
+                       writel(INTERNAL_MEM_SIZE - 1,
+                              &pGbl->txq_end_addr.value);
+               } else if (pAdapter->RegistryJumboPacket < 8192) {
+                       /* For jumbo packets > 2k but < 8k, split 50-50. */
+                       writel(0, &pGbl->rxq_start_addr.value);
+                       writel(INTERNAL_MEM_RX_OFFSET,
+                              &pGbl->rxq_end_addr.value);
+                       writel(INTERNAL_MEM_RX_OFFSET + 1,
+                              &pGbl->txq_start_addr.value);
+                       writel(INTERNAL_MEM_SIZE - 1,
+                              &pGbl->txq_end_addr.value);
+               } else {
+                       /* 9216 is the only packet size greater than 8k that
+                        * is available. The Tx buffer has to be big enough
+                        * for one whole packet on the Tx side. We'll make
+                        * the Tx 9408, and give the rest to Rx
+                        */
+                       writel(0x0000, &pGbl->rxq_start_addr.value);
+                       writel(0x01b3, &pGbl->rxq_end_addr.value);
+                       writel(0x01b4, &pGbl->txq_start_addr.value);
+                       writel(INTERNAL_MEM_SIZE - 1,
+                              &pGbl->txq_end_addr.value);
+               }
+
+               /* Initialize the loopback register. Disable all loopbacks. */
+               writel(0, &pGbl->loopback.value);
+       } else {
+               /* For PHY Line loopback, the memory is configured as if Tx
+                * and Rx both have all the memory.  This is because the
+                * RxMAC will write data into the space, and the TxMAC will
+                * read it out.
+                */
+               writel(0, &pGbl->rxq_start_addr.value);
+               writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr.value);
+               writel(0, &pGbl->txq_start_addr.value);
+               writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr.value);
+
+               /* Initialize the loopback register (MAC loopback). */
+               writel(1, &pGbl->loopback.value);
+       }
+
+       /* MSI Register */
+       writel(0, &pGbl->msi_config.value);
+
+       /* By default, disable the watchdog timer.  It will be enabled when
+        * a packet is queued.
+        */
+       writel(0, &pGbl->watchdog_timer);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * ConfigMMCRegs - Used to configure the main memory registers in the JAGCore
+ * @pAdapter: pointer to our adapter structure
+ */
+void ConfigMMCRegs(struct et131x_adapter *pAdapter)
+{
+       MMC_CTRL_t mmc_ctrl = { 0 };
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* All we need to do is initialize the Memory Control Register */
+       mmc_ctrl.bits.force_ce = 0x0;
+       mmc_ctrl.bits.rxdma_disable = 0x0;
+       mmc_ctrl.bits.txdma_disable = 0x0;
+       mmc_ctrl.bits.txmac_disable = 0x0;
+       mmc_ctrl.bits.rxmac_disable = 0x0;
+       mmc_ctrl.bits.arb_disable = 0x0;
+       mmc_ctrl.bits.mmc_enable = 0x1;
+
+       writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void et131x_enable_interrupts(struct et131x_adapter *adapter)
+{
+       uint32_t MaskValue;
+
+       /* Enable all global interrupts */
+       if ((adapter->FlowControl == TxOnly) || (adapter->FlowControl == Both)) {
+               MaskValue = INT_MASK_ENABLE;
+       } else {
+               MaskValue = INT_MASK_ENABLE_NO_FLOW;
+       }
+
+       if (adapter->DriverNoPhyAccess) {
+               MaskValue |= 0x10000;
+       }
+
+       adapter->CachedMaskValue.value = MaskValue;
+       writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
+}
+
+void et131x_disable_interrupts(struct et131x_adapter * adapter)
+{
+       /* Disable all global interrupts */
+       adapter->CachedMaskValue.value = INT_MASK_DISABLE;
+       writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);
+}
diff --git a/src/et131x/et1310_jagcore.h b/src/et131x/et1310_jagcore.h
new file mode 100644 (file)
index 0000000..9fc8293
--- /dev/null
@@ -0,0 +1,112 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_jagcore.h - Defines, structs, enums, prototypes, etc. pertaining to
+ *                    the JAGCore
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET1310_JAGCORE_H__
+#define __ET1310_JAGCORE_H__
+
+#include "et1310_address_map.h"
+
+
+#define INTERNAL_MEM_SIZE       0x400  //1024 of internal memory
+#define INTERNAL_MEM_RX_OFFSET  0x1FF  //50%   Tx, 50%   Rx
+
+#define REGS_MAX_ARRAY          4096
+
+/*
+ * For interrupts, normal running is:
+ *       rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
+ *       watchdog_interrupt & txdma_xfer_done
+ *
+ * In both cases, when flow control is enabled for either Tx or bi-direction,
+ * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
+ * buffer rings are running low.
+ */
+#define INT_MASK_DISABLE            0xffffffff
+
+// NOTE: Masking out MAC_STAT Interrupt for now...
+//#define INT_MASK_ENABLE             0xfff6bf17
+//#define INT_MASK_ENABLE_NO_FLOW     0xfff6bfd7
+#define INT_MASK_ENABLE             0xfffebf17
+#define INT_MASK_ENABLE_NO_FLOW     0xfffebfd7
+
+/* DATA STRUCTURES FOR DIRECT REGISTER ACCESS */
+
+typedef struct {
+       u8 bReadWrite;
+       u32 nRegCount;
+       u32 nData[REGS_MAX_ARRAY];
+       u32 nOffsets[REGS_MAX_ARRAY];
+} JAGCORE_ACCESS_REGS, *PJAGCORE_ACCESS_REGS;
+
+typedef struct {
+       u8 bReadWrite;
+       u32 nDataWidth;
+       u32 nRegCount;
+       u32 nOffsets[REGS_MAX_ARRAY];
+       u32 nData[REGS_MAX_ARRAY];
+} PCI_CFG_SPACE_REGS, *PPCI_CFG_SPACE_REGS;
+
+/* Forward declaration of the private adapter structure */
+struct et131x_adapter;
+
+void ConfigGlobalRegs(struct et131x_adapter *pAdapter);
+void ConfigMMCRegs(struct et131x_adapter *pAdapter);
+void et131x_enable_interrupts(struct et131x_adapter *adapter);
+void et131x_disable_interrupts(struct et131x_adapter *adapter);
+
+#endif /* __ET1310_JAGCORE_H__ */
diff --git a/src/et131x/et1310_mac.c b/src/et131x/et1310_mac.c
new file mode 100644 (file)
index 0000000..1924968
--- /dev/null
@@ -0,0 +1,792 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_mac.c - All code and routines pertaining to the MAC
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_debug.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+
+#include "et1310_phy.h"
+#include "et1310_pm.h"
+#include "et1310_jagcore.h"
+#include "et1310_mac.h"
+
+#include "et131x_adapter.h"
+#include "et131x_initpci.h"
+
+/* Data for debugging facilities */
+#ifdef CONFIG_ET131X_DEBUG
+extern dbg_info_t *et131x_dbginfo;
+#endif /* CONFIG_ET131X_DEBUG */
+
+/**
+ * ConfigMacRegs1 - Initialize the first part of MAC regs
+ * @pAdpater: pointer to our adapter structure
+ */
+void ConfigMACRegs1(struct et131x_adapter *pAdapter)
+{
+       struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
+       MAC_STATION_ADDR1_t station1;
+       MAC_STATION_ADDR2_t station2;
+       MAC_IPG_t ipg;
+       MAC_HFDP_t hfdp;
+       MII_MGMT_CFG_t mii_mgmt_cfg;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* First we need to reset everything.  Write to MAC configuration
+        * register 1 to perform reset.
+        */
+       writel(0xC00F0000, &pMac->cfg1.value);
+
+       /* Next lets configure the MAC Inter-packet gap register */
+       ipg.bits.non_B2B_ipg_1 = 0x38;          // 58d
+       ipg.bits.non_B2B_ipg_2 = 0x58;          // 88d
+       ipg.bits.min_ifg_enforce = 0x50;        // 80d
+       ipg.bits.B2B_ipg = 0x60;                // 96d
+       writel(ipg.value, &pMac->ipg.value);
+
+       /* Next lets configure the MAC Half Duplex register */
+       hfdp.bits.alt_beb_trunc = 0xA;
+       hfdp.bits.alt_beb_enable = 0x0;
+       hfdp.bits.bp_no_backoff = 0x0;
+       hfdp.bits.no_backoff = 0x0;
+       hfdp.bits.excess_defer = 0x1;
+       hfdp.bits.rexmit_max = 0xF;
+       hfdp.bits.coll_window = 0x37;           // 55d
+       writel(hfdp.value, &pMac->hfdp.value);
+
+       /* Next lets configure the MAC Interface Control register */
+       writel(0, &pMac->if_ctrl.value);
+
+       /* Let's move on to setting up the mii managment configuration */
+       mii_mgmt_cfg.bits.reset_mii_mgmt = 0;
+       mii_mgmt_cfg.bits.scan_auto_incremt = 0;
+       mii_mgmt_cfg.bits.preamble_suppress = 0;
+       mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7;
+       writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value);
+
+       /* Next lets configure the MAC Station Address register.  These
+        * values are read from the EEPROM during initialization and stored
+        * in the adapter structure.  We write what is stored in the adapter
+        * structure to the MAC Station Address registers high and low.  This
+        * station address is used for generating and checking pause control
+        * packets.
+        */
+       station2.bits.Octet1 = pAdapter->CurrentAddress[0];
+       station2.bits.Octet2 = pAdapter->CurrentAddress[1];
+       station1.bits.Octet3 = pAdapter->CurrentAddress[2];
+       station1.bits.Octet4 = pAdapter->CurrentAddress[3];
+       station1.bits.Octet5 = pAdapter->CurrentAddress[4];
+       station1.bits.Octet6 = pAdapter->CurrentAddress[5];
+       writel(station1.value, &pMac->station_addr_1.value);
+       writel(station2.value, &pMac->station_addr_2.value);
+
+       /* Max ethernet packet in bytes that will passed by the mac without
+        * being truncated.  Allow the MAC to pass 4 more than our max packet
+        * size.  This is 4 for the Ethernet CRC.
+        *
+        * Packets larger than (RegistryJumboPacket) that do not contain a
+        * VLAN ID will be dropped by the Rx function.
+        */
+       writel(pAdapter->RegistryJumboPacket + 4, &pMac->max_fm_len.value);
+
+       /* clear out MAC config reset */
+       writel(0, &pMac->cfg1.value);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * ConfigMacRegs2 - Initialize the second part of MAC regs
+ * @pAdpater: pointer to our adapter structure
+ */
+void ConfigMACRegs2(struct et131x_adapter *pAdapter)
+{
+       int32_t delay = 0;
+       struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
+       MAC_CFG1_t cfg1;
+       MAC_CFG2_t cfg2;
+       MAC_IF_CTRL_t ifctrl;
+       TXMAC_CTL_t ctl;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       ctl.value = readl(&pAdapter->CSRAddress->txmac.ctl.value);
+       cfg1.value = readl(&pMac->cfg1.value);
+       cfg2.value = readl(&pMac->cfg2.value);
+       ifctrl.value = readl(&pMac->if_ctrl.value);
+
+       if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
+               cfg2.bits.if_mode = 0x2;
+               ifctrl.bits.phy_mode = 0x0;
+       } else {
+               cfg2.bits.if_mode = 0x1;
+               ifctrl.bits.phy_mode = 0x1;
+       }
+
+       /* We need to enable Rx/Tx */
+       cfg1.bits.rx_enable = 0x1;
+       cfg1.bits.tx_enable = 0x1;
+
+       /* Set up flow control */
+       cfg1.bits.tx_flow = 0x1;
+
+       if ((pAdapter->FlowControl == RxOnly) ||
+           (pAdapter->FlowControl == Both)) {
+               cfg1.bits.rx_flow = 0x1;
+       } else {
+               cfg1.bits.rx_flow = 0x0;
+       }
+
+       /* Initialize loop back to off */
+       cfg1.bits.loop_back = 0;
+
+       writel(cfg1.value, &pMac->cfg1.value);
+
+       /* Now we need to initialize the MAC Configuration 2 register */
+       cfg2.bits.preamble_len = 0x7;
+       cfg2.bits.huge_frame = 0x0;
+       /* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check
+        * the frame's length field to ensure it matches the actual data
+        * field length. Clear this bit if no length field checking is
+        * desired. Its default is 0.
+        */
+       cfg2.bits.len_check = 0x1;
+
+       if (pAdapter->RegistryPhyLoopbk == false) {
+               cfg2.bits.pad_crc = 0x1;
+               cfg2.bits.crc_enable = 0x1;
+       } else {
+               cfg2.bits.pad_crc = 0;
+               cfg2.bits.crc_enable = 0;
+       }
+
+       /* 1 - full duplex, 0 - half-duplex */
+       cfg2.bits.full_duplex = pAdapter->uiDuplexMode;
+       ifctrl.bits.ghd_mode = !pAdapter->uiDuplexMode;
+
+       writel(ifctrl.value, &pMac->if_ctrl.value);
+       writel(cfg2.value, &pMac->cfg2.value);
+
+       do {
+               udelay(10);
+               delay++;
+               cfg1.value = readl(&pMac->cfg1.value);
+       } while ((!cfg1.bits.syncd_rx_en ||
+                 !cfg1.bits.syncd_tx_en) &&
+                delay < 100);
+
+       if (delay == 100) {
+               DBG_ERROR(et131x_dbginfo,
+                         "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
+                         cfg1.value);
+       }
+
+       DBG_TRACE(et131x_dbginfo,
+                 "Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
+                 pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,
+                 readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
+                 readl(&pMac->if_ctrl.value));
+
+       /* Enable TXMAC */
+       ctl.bits.txmac_en = 0x1;
+       ctl.bits.fc_disable = 0x1;
+       writel(ctl.value, &pAdapter->CSRAddress->txmac.ctl.value);
+
+       /* Ready to start the RXDMA/TXDMA engine */
+       if (!MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER)) {
+               et131x_rx_dma_enable(pAdapter);
+               et131x_tx_dma_enable(pAdapter);
+       } else {
+               DBG_WARNING(et131x_dbginfo,
+                           "Didn't enable Rx/Tx due to low-power mode\n");
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void ConfigRxMacRegs(struct et131x_adapter *pAdapter)
+{
+       struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac;
+       RXMAC_WOL_SA_LO_t sa_lo;
+       RXMAC_WOL_SA_HI_t sa_hi;
+       RXMAC_PF_CTRL_t pf_ctrl = { 0 };
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Disable the MAC while it is being configured (also disable WOL) */
+       writel(0x8, &pRxMac->ctrl.value);
+
+       /* Initialize WOL to disabled. */
+       writel(0, &pRxMac->crc0.value);
+       writel(0, &pRxMac->crc12.value);
+       writel(0, &pRxMac->crc34.value);
+
+       /* We need to set the WOL mask0 - mask4 next.  We initialize it to
+        * its default Values of 0x00000000 because there are not WOL masks
+        * as of this time.
+        */
+       writel(0, &pRxMac->mask0_word0);
+       writel(0, &pRxMac->mask0_word1);
+       writel(0, &pRxMac->mask0_word2);
+       writel(0, &pRxMac->mask0_word3);
+
+       writel(0, &pRxMac->mask1_word0);
+       writel(0, &pRxMac->mask1_word1);
+       writel(0, &pRxMac->mask1_word2);
+       writel(0, &pRxMac->mask1_word3);
+
+       writel(0, &pRxMac->mask2_word0);
+       writel(0, &pRxMac->mask2_word1);
+       writel(0, &pRxMac->mask2_word2);
+       writel(0, &pRxMac->mask2_word3);
+
+       writel(0, &pRxMac->mask3_word0);
+       writel(0, &pRxMac->mask3_word1);
+       writel(0, &pRxMac->mask3_word2);
+       writel(0, &pRxMac->mask3_word3);
+
+       writel(0, &pRxMac->mask4_word0);
+       writel(0, &pRxMac->mask4_word1);
+       writel(0, &pRxMac->mask4_word2);
+       writel(0, &pRxMac->mask4_word3);
+
+       /* Lets setup the WOL Source Address */
+       sa_lo.bits.sa3 = pAdapter->CurrentAddress[2];
+       sa_lo.bits.sa4 = pAdapter->CurrentAddress[3];
+       sa_lo.bits.sa5 = pAdapter->CurrentAddress[4];
+       sa_lo.bits.sa6 = pAdapter->CurrentAddress[5];
+       writel(sa_lo.value, &pRxMac->sa_lo.value);
+
+       sa_hi.bits.sa1 = pAdapter->CurrentAddress[0];
+       sa_hi.bits.sa2 = pAdapter->CurrentAddress[1];
+       writel(sa_hi.value, &pRxMac->sa_hi.value);
+
+       /* Disable all Packet Filtering */
+       writel(0, &pRxMac->pf_ctrl.value);
+
+       /* Let's initialize the Unicast Packet filtering address */
+       if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
+               SetupDeviceForUnicast(pAdapter);
+               pf_ctrl.bits.filter_uni_en = 1;
+       } else {
+               writel(0, &pRxMac->uni_pf_addr1.value);
+               writel(0, &pRxMac->uni_pf_addr2.value);
+               writel(0, &pRxMac->uni_pf_addr3.value);
+       }
+
+       /* Let's initialize the Multicast hash */
+       if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
+               pf_ctrl.bits.filter_multi_en = 0;
+       } else {
+               pf_ctrl.bits.filter_multi_en = 1;
+               SetupDeviceForMulticast(pAdapter);
+       }
+
+       /* Runt packet filtering.  Didn't work in version A silicon. */
+       pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
+       pf_ctrl.bits.filter_frag_en = 1;
+
+       if (pAdapter->RegistryJumboPacket > 8192) {
+               RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
+
+               /* In order to transmit jumbo packets greater than 8k, the
+                * FIFO between RxMAC and RxDMA needs to be reduced in size
+                * to (16k - Jumbo packet size).  In order to implement this,
+                * we must use "cut through" mode in the RxMAC, which chops
+                * packets down into segments which are (max_size * 16).  In
+                * this case we selected 256 bytes, since this is the size of
+                * the PCI-Express TLP's that the 1310 uses.
+                */
+               mcif_ctrl_max_seg.bits.seg_en = 0x1;
+               mcif_ctrl_max_seg.bits.fc_en = 0x0;
+               mcif_ctrl_max_seg.bits.max_size = 0x10;
+
+               writel(mcif_ctrl_max_seg.value,
+                      &pRxMac->mcif_ctrl_max_seg.value);
+       } else {
+               writel(0, &pRxMac->mcif_ctrl_max_seg.value);
+       }
+
+       /* Initialize the MCIF water marks */
+       writel(0, &pRxMac->mcif_water_mark.value);
+
+       /*  Initialize the MIF control */
+       writel(0, &pRxMac->mif_ctrl.value);
+
+       /* Initialize the Space Available Register */
+       writel(0, &pRxMac->space_avail.value);
+
+       /* Initialize the the mif_ctrl register
+        * bit 3:  Receive code error. One or more nibbles were signaled as
+        *         errors  during the reception of the packet.  Clear this
+        *         bit in Gigabit, set it in 100Mbit.  This was derived
+        *         experimentally at UNH.
+        * bit 4:  Receive CRC error. The packet's CRC did not match the
+        *         internally generated CRC.
+        * bit 5:  Receive length check error. Indicates that frame length
+        *         field value in the packet does not match the actual data
+        *         byte length and is not a type field.
+        * bit 16: Receive frame truncated.
+        * bit 17: Drop packet enable
+        */
+       if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) {
+               writel(0x30038, &pRxMac->mif_ctrl.value);
+       } else {
+               writel(0x30030, &pRxMac->mif_ctrl.value);
+       }
+
+       /* Finally we initialize RxMac to be enabled & WOL disabled.  Packet
+        * filter is always enabled since it is where the runt packets are
+        * supposed to be dropped.  For version A silicon, runt packet
+        * dropping doesn't work, so it is disabled in the pf_ctrl register,
+        * but we still leave the packet filter on.
+        */
+       writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
+       writel(0x9, &pRxMac->ctrl.value);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void ConfigTxMacRegs(struct et131x_adapter *pAdapter)
+{
+       struct _TXMAC_t __iomem *pTxMac = &pAdapter->CSRAddress->txmac;
+       TXMAC_CF_PARAM_t Local;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* We need to update the Control Frame Parameters
+        * cfpt - control frame pause timer set to 64 (0x40)
+        * cfep - control frame extended pause timer set to 0x0
+        */
+       if (pAdapter->FlowControl == None) {
+               writel(0, &pTxMac->cf_param.value);
+       } else {
+               Local.bits.cfpt = 0x40;
+               Local.bits.cfep = 0x0;
+               writel(Local.value, &pTxMac->cf_param.value);
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void ConfigMacStatRegs(struct et131x_adapter *pAdapter)
+{
+       struct _MAC_STAT_t __iomem *pDevMacStat =
+               &pAdapter->CSRAddress->macStat;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Next we need to initialize all the MAC_STAT registers to zero on
+        * the device.
+        */
+       writel(0, &pDevMacStat->RFcs);
+       writel(0, &pDevMacStat->RAln);
+       writel(0, &pDevMacStat->RFlr);
+       writel(0, &pDevMacStat->RDrp);
+       writel(0, &pDevMacStat->RCde);
+       writel(0, &pDevMacStat->ROvr);
+       writel(0, &pDevMacStat->RFrg);
+
+       writel(0, &pDevMacStat->TScl);
+       writel(0, &pDevMacStat->TDfr);
+       writel(0, &pDevMacStat->TMcl);
+       writel(0, &pDevMacStat->TLcl);
+       writel(0, &pDevMacStat->TNcl);
+       writel(0, &pDevMacStat->TOvr);
+       writel(0, &pDevMacStat->TUnd);
+
+       /* Unmask any counters that we want to track the overflow of.
+        * Initially this will be all counters.  It may become clear later
+        * that we do not need to track all counters.
+        */
+       {
+               MAC_STAT_REG_1_t Carry1M = { 0xffffffff };
+
+               Carry1M.bits.rdrp = 0;
+               Carry1M.bits.rjbr = 1;
+               Carry1M.bits.rfrg = 0;
+               Carry1M.bits.rovr = 0;
+               Carry1M.bits.rund = 1;
+               Carry1M.bits.rcse = 1;
+               Carry1M.bits.rcde = 0;
+               Carry1M.bits.rflr = 0;
+               Carry1M.bits.raln = 0;
+               Carry1M.bits.rxuo = 1;
+               Carry1M.bits.rxpf = 1;
+               Carry1M.bits.rxcf = 1;
+               Carry1M.bits.rbca = 1;
+               Carry1M.bits.rmca = 1;
+               Carry1M.bits.rfcs = 0;
+               Carry1M.bits.rpkt = 1;
+               Carry1M.bits.rbyt = 1;
+               Carry1M.bits.trmgv = 1;
+               Carry1M.bits.trmax = 1;
+               Carry1M.bits.tr1k = 1;
+               Carry1M.bits.tr511 = 1;
+               Carry1M.bits.tr255 = 1;
+               Carry1M.bits.tr127 = 1;
+               Carry1M.bits.tr64 = 1;
+
+               writel(Carry1M.value, &pDevMacStat->Carry1M.value);
+       }
+
+       {
+               MAC_STAT_REG_2_t Carry2M = { 0xffffffff };
+
+               Carry2M.bits.tdrp = 1;
+               Carry2M.bits.tpfh = 1;
+               Carry2M.bits.tncl = 0;
+               Carry2M.bits.txcl = 1;
+               Carry2M.bits.tlcl = 0;
+               Carry2M.bits.tmcl = 0;
+               Carry2M.bits.tscl = 0;
+               Carry2M.bits.tedf = 1;
+               Carry2M.bits.tdfr = 0;
+               Carry2M.bits.txpf = 1;
+               Carry2M.bits.tbca = 1;
+               Carry2M.bits.tmca = 1;
+               Carry2M.bits.tpkt = 1;
+               Carry2M.bits.tbyt = 1;
+               Carry2M.bits.tfrg = 1;
+               Carry2M.bits.tund = 0;
+               Carry2M.bits.tovr = 0;
+               Carry2M.bits.txcf = 1;
+               Carry2M.bits.tfcs = 1;
+               Carry2M.bits.tjbr = 1;
+
+               writel(Carry2M.value, &pDevMacStat->Carry2M.value);
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void ConfigFlowControl(struct et131x_adapter * pAdapter)
+{
+       if (pAdapter->uiDuplexMode == 0) {
+               pAdapter->FlowControl = None;
+       } else {
+               char RemotePause, RemoteAsyncPause;
+
+               ET1310_PhyAccessMiBit(pAdapter,
+                                     TRUEPHY_BIT_READ, 5, 10, &RemotePause);
+               ET1310_PhyAccessMiBit(pAdapter,
+                                     TRUEPHY_BIT_READ, 5, 11,
+                                     &RemoteAsyncPause);
+
+               if ((RemotePause == TRUEPHY_BIT_SET) &&
+                   (RemoteAsyncPause == TRUEPHY_BIT_SET)) {
+                       pAdapter->FlowControl = pAdapter->RegistryFlowControl;
+               } else if ((RemotePause == TRUEPHY_BIT_SET) &&
+                          (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
+                       if (pAdapter->RegistryFlowControl == Both) {
+                               pAdapter->FlowControl = Both;
+                       } else {
+                               pAdapter->FlowControl = None;
+                       }
+               } else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&
+                          (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
+                       pAdapter->FlowControl = None;
+               } else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
+                              RemoteAsyncPause == TRUEPHY_SET_BIT) */
+                       if (pAdapter->RegistryFlowControl == Both) {
+                               pAdapter->FlowControl = RxOnly;
+                       } else {
+                               pAdapter->FlowControl = None;
+                       }
+               }
+       }
+}
+
+/**
+ * UpdateMacStatHostCounters - Update the local copy of the statistics
+ * @pAdapter: pointer to the adapter structure
+ */
+void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter)
+{
+       struct _ce_stats_t *stats = &pAdapter->Stats;
+       struct _MAC_STAT_t __iomem *pDevMacStat =
+               &pAdapter->CSRAddress->macStat;
+
+       stats->collisions += readl(&pDevMacStat->TNcl);
+       stats->first_collision += readl(&pDevMacStat->TScl);
+       stats->tx_deferred += readl(&pDevMacStat->TDfr);
+       stats->excessive_collisions += readl(&pDevMacStat->TMcl);
+       stats->late_collisions += readl(&pDevMacStat->TLcl);
+       stats->tx_uflo += readl(&pDevMacStat->TUnd);
+       stats->max_pkt_error += readl(&pDevMacStat->TOvr);
+
+       stats->alignment_err += readl(&pDevMacStat->RAln);
+       stats->crc_err += readl(&pDevMacStat->RCde);
+       stats->norcvbuf += readl(&pDevMacStat->RDrp);
+       stats->rx_ov_flow += readl(&pDevMacStat->ROvr);
+       stats->code_violations += readl(&pDevMacStat->RFcs);
+       stats->length_err += readl(&pDevMacStat->RFlr);
+
+       stats->other_errors += readl(&pDevMacStat->RFrg);
+}
+
+/**
+ * HandleMacStatInterrupt
+ * @pAdapter: pointer to the adapter structure
+ *
+ * One of the MACSTAT counters has wrapped.  Update the local copy of
+ * the statistics held in the adapter structure, checking the "wrap"
+ * bit for each counter.
+ */
+void HandleMacStatInterrupt(struct et131x_adapter *pAdapter)
+{
+       MAC_STAT_REG_1_t Carry1;
+       MAC_STAT_REG_2_t Carry2;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Read the interrupt bits from the register(s).  These are Clear On
+        * Write.
+        */
+       Carry1.value = readl(&pAdapter->CSRAddress->macStat.Carry1.value);
+       Carry2.value = readl(&pAdapter->CSRAddress->macStat.Carry2.value);
+
+       writel(Carry1.value, &pAdapter->CSRAddress->macStat.Carry1.value);
+       writel(Carry2.value, &pAdapter->CSRAddress->macStat.Carry2.value);
+
+       /* We need to do update the host copy of all the MAC_STAT counters.
+        * For each counter, check it's overflow bit.  If the overflow bit is
+        * set, then increment the host version of the count by one complete
+        * revolution of the counter.  This routine is called when the counter
+        * block indicates that one of the counters has wrapped.
+        */
+       if (Carry1.bits.rfcs) {
+               pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT;
+       }
+       if (Carry1.bits.raln) {
+               pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry1.bits.rflr) {
+               pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT;
+       }
+       if (Carry1.bits.rfrg) {
+               pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT;
+       }
+       if (Carry1.bits.rcde) {
+               pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT;
+       }
+       if (Carry1.bits.rovr) {
+               pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
+       }
+       if (Carry1.bits.rdrp) {
+               pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
+       }
+       if (Carry2.bits.tovr) {
+               pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry2.bits.tund) {
+               pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry2.bits.tscl) {
+               pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry2.bits.tdfr) {
+               pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry2.bits.tmcl) {
+               pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry2.bits.tlcl) {
+               pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT;
+       }
+       if (Carry2.bits.tncl) {
+               pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT;
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void SetupDeviceForMulticast(struct et131x_adapter *pAdapter)
+{
+       struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
+       uint32_t nIndex;
+       uint32_t result;
+       uint32_t hash1 = 0;
+       uint32_t hash2 = 0;
+       uint32_t hash3 = 0;
+       uint32_t hash4 = 0;
+       PM_CSR_t pm_csr;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
+        * the multi-cast LIST.  If it is NOT specified, (and "ALL" is not
+        * specified) then we should pass NO multi-cast addresses to the
+        * driver.
+        */
+       if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
+               DBG_VERBOSE(et131x_dbginfo,
+                           "MULTICAST flag is set, MCCount: %d\n",
+                           pAdapter->MCAddressCount);
+
+               /* Loop through our multicast array and set up the device */
+               for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) {
+                       DBG_VERBOSE(et131x_dbginfo,
+                                   "MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
+                                   nIndex,
+                                   pAdapter->MCList[nIndex][0],
+                                   pAdapter->MCList[nIndex][1],
+                                   pAdapter->MCList[nIndex][2],
+                                   pAdapter->MCList[nIndex][3],
+                                   pAdapter->MCList[nIndex][4],
+                                   pAdapter->MCList[nIndex][5]);
+
+                       result = ether_crc(6, pAdapter->MCList[nIndex]);
+
+                       result = (result & 0x3F800000) >> 23;
+
+                       if (result < 32) {
+                               hash1 |= (1 << result);
+                       } else if ((31 < result) && (result < 64)) {
+                               result -= 32;
+                               hash2 |= (1 << result);
+                       } else if ((63 < result) && (result < 96)) {
+                               result -= 64;
+                               hash3 |= (1 << result);
+                       } else {
+                               result -= 96;
+                               hash4 |= (1 << result);
+                       }
+               }
+       }
+
+       /* Write out the new hash to the device */
+       pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
+       if (pm_csr.bits.pm_phy_sw_coma == 0) {
+               writel(hash1, &rxmac->multi_hash1);
+               writel(hash2, &rxmac->multi_hash2);
+               writel(hash3, &rxmac->multi_hash3);
+               writel(hash4, &rxmac->multi_hash4);
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+void SetupDeviceForUnicast(struct et131x_adapter *pAdapter)
+{
+       struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
+       RXMAC_UNI_PF_ADDR1_t uni_pf1;
+       RXMAC_UNI_PF_ADDR2_t uni_pf2;
+       RXMAC_UNI_PF_ADDR3_t uni_pf3;
+       PM_CSR_t pm_csr;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Set up unicast packet filter reg 3 to be the first two octets of
+        * the MAC address for both address
+        *
+        * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
+        * MAC address for second address
+        *
+        * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
+        * MAC address for first address
+        */
+       uni_pf3.bits.addr1_1 = pAdapter->CurrentAddress[0];
+       uni_pf3.bits.addr1_2 = pAdapter->CurrentAddress[1];
+       uni_pf3.bits.addr2_1 = pAdapter->CurrentAddress[0];
+       uni_pf3.bits.addr2_2 = pAdapter->CurrentAddress[1];
+
+       uni_pf2.bits.addr2_3 = pAdapter->CurrentAddress[2];
+       uni_pf2.bits.addr2_4 = pAdapter->CurrentAddress[3];
+       uni_pf2.bits.addr2_5 = pAdapter->CurrentAddress[4];
+       uni_pf2.bits.addr2_6 = pAdapter->CurrentAddress[5];
+
+       uni_pf1.bits.addr1_3 = pAdapter->CurrentAddress[2];
+       uni_pf1.bits.addr1_4 = pAdapter->CurrentAddress[3];
+       uni_pf1.bits.addr1_5 = pAdapter->CurrentAddress[4];
+       uni_pf1.bits.addr1_6 = pAdapter->CurrentAddress[5];
+
+       pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
+       if (pm_csr.bits.pm_phy_sw_coma == 0) {
+               writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
+               writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
+               writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
diff --git a/src/et131x/et1310_mac.h b/src/et131x/et1310_mac.h
new file mode 100644 (file)
index 0000000..bd26cd3
--- /dev/null
@@ -0,0 +1,93 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_mac.h -  Defines, structs, enums, prototypes, etc. pertaining to the
+ *                 MAC.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef _ET1310_MAC_H_
+#define _ET1310_MAC_H_
+
+
+#include "et1310_address_map.h"
+
+
+#define COUNTER_WRAP_28_BIT 0x10000000
+#define COUNTER_WRAP_22_BIT 0x400000
+#define COUNTER_WRAP_16_BIT 0x10000
+#define COUNTER_WRAP_12_BIT 0x1000
+
+#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
+#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
+#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
+#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
+
+#define UPDATE_COUNTER(HostCnt,DevCnt) \
+    HostCnt = HostCnt + DevCnt;
+
+/* Forward declaration of the private adapter structure */
+struct et131x_adapter;
+
+void ConfigMACRegs1(struct et131x_adapter *adapter);
+void ConfigMACRegs2(struct et131x_adapter *adapter);
+void ConfigRxMacRegs(struct et131x_adapter *adapter);
+void ConfigTxMacRegs(struct et131x_adapter *adapter);
+void ConfigMacStatRegs(struct et131x_adapter *adapter);
+void ConfigFlowControl(struct et131x_adapter *adapter);
+void UpdateMacStatHostCounters(struct et131x_adapter *adapter);
+void HandleMacStatInterrupt(struct et131x_adapter *adapter);
+void SetupDeviceForMulticast(struct et131x_adapter *adapter);
+void SetupDeviceForUnicast(struct et131x_adapter *adapter);
+
+#endif /* _ET1310_MAC_H_ */
diff --git a/src/et131x/et1310_phy.c b/src/et131x/et1310_phy.c
new file mode 100644 (file)
index 0000000..6c4fa54
--- /dev/null
@@ -0,0 +1,1281 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_phy.c - Routines for configuring and accessing the PHY
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_debug.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include "et1310_phy.h"
+#include "et1310_pm.h"
+#include "et1310_jagcore.h"
+
+#include "et131x_adapter.h"
+#include "et131x_netdev.h"
+#include "et131x_initpci.h"
+
+#include "et1310_address_map.h"
+#include "et1310_jagcore.h"
+#include "et1310_tx.h"
+#include "et1310_rx.h"
+#include "et1310_mac.h"
+
+/* Data for debugging facilities */
+#ifdef CONFIG_ET131X_DEBUG
+extern dbg_info_t *et131x_dbginfo;
+#endif /* CONFIG_ET131X_DEBUG */
+
+/* Prototypes for functions with local scope */
+static int et131x_xcvr_init(struct et131x_adapter *adapter);
+
+/**
+ * PhyMiRead - Read from the PHY through the MII Interface on the MAC
+ * @adapter: pointer to our private adapter structure
+ * @xcvrAddr: the address of the transciever
+ * @xcvrReg: the register to read
+ * @value: pointer to a 16-bit value in which the value will be stored
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
+             uint8_t xcvrReg, uint16_t *value)
+{
+       struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
+       int status = 0;
+       uint32_t delay;
+       MII_MGMT_ADDR_t miiAddr;
+       MII_MGMT_CMD_t miiCmd;
+       MII_MGMT_INDICATOR_t miiIndicator;
+
+       /* Save a local copy of the registers we are dealing with so we can
+        * set them back
+        */
+       miiAddr.value = readl(&mac->mii_mgmt_addr.value);
+       miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
+
+       /* Stop the current operation */
+       writel(0, &mac->mii_mgmt_cmd.value);
+
+       /* Set up the register we need to read from on the correct PHY */
+       {
+               MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
+
+               mii_mgmt_addr.bits.phy_addr = xcvrAddr;
+               mii_mgmt_addr.bits.reg_addr = xcvrReg;
+               writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
+       }
+
+       /* Kick the read cycle off */
+       delay = 0;
+
+       writel(0x1, &mac->mii_mgmt_cmd.value);
+
+       do {
+               udelay(50);
+               delay++;
+               miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
+       } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
+                delay < 50);
+
+       /* If we hit the max delay, we could not read the register */
+       if (delay >= 50) {
+               DBG_WARNING(et131x_dbginfo,
+                           "xcvrReg 0x%08x could not be read\n", xcvrReg);
+               DBG_WARNING(et131x_dbginfo, "status is  0x%08x\n",
+                           miiIndicator.value);
+
+               status = -EIO;
+       }
+
+       /* If we hit here we were able to read the register and we need to
+        * return the value to the caller
+        */
+       /* TODO: make this stuff a simple readw()?! */
+       {
+               MII_MGMT_STAT_t mii_mgmt_stat;
+
+               mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
+               *value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
+       }
+
+       /* Stop the read operation */
+       writel(0, &mac->mii_mgmt_cmd.value);
+
+       DBG_VERBOSE(et131x_dbginfo, "  xcvr_addr = 0x%02x, "
+                   "xcvr_reg  = 0x%02x, "
+                   "value     = 0x%04x.\n", xcvrAddr, xcvrReg, *value);
+
+       /* set the registers we touched back to the state at which we entered
+        * this function
+        */
+       writel(miiAddr.value, &mac->mii_mgmt_addr.value);
+       writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
+
+       return status;
+}
+
+/**
+ * MiWrite - Write to a PHY register through the MII interface of the MAC
+ * @adapter: pointer to our private adapter structure
+ * @xcvrReg: the register to read
+ * @value: 16-bit value to write
+ *
+ * Return 0 on success, errno on failure (as defined in errno.h)
+ */
+int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
+{
+       struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
+       int status = 0;
+       uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
+       uint32_t delay;
+       MII_MGMT_ADDR_t miiAddr;
+       MII_MGMT_CMD_t miiCmd;
+       MII_MGMT_INDICATOR_t miiIndicator;
+
+       /* Save a local copy of the registers we are dealing with so we can
+        * set them back
+        */
+       miiAddr.value = readl(&mac->mii_mgmt_addr.value);
+       miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
+
+       /* Stop the current operation */
+       writel(0, &mac->mii_mgmt_cmd.value);
+
+       /* Set up the register we need to write to on the correct PHY */
+       {
+               MII_MGMT_ADDR_t mii_mgmt_addr;
+
+               mii_mgmt_addr.bits.phy_addr = xcvrAddr;
+               mii_mgmt_addr.bits.reg_addr = xcvrReg;
+               writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
+       }
+
+       /* Add the value to write to the registers to the mac */
+       writel(value, &mac->mii_mgmt_ctrl.value);
+       delay = 0;
+
+       do {
+               udelay(50);
+               delay++;
+               miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
+       } while (miiIndicator.bits.busy && delay < 100);
+
+       /* If we hit the max delay, we could not write the register */
+       if (delay == 100) {
+               uint16_t TempValue;
+
+               DBG_WARNING(et131x_dbginfo,
+                           "xcvrReg 0x%08x could not be written", xcvrReg);
+               DBG_WARNING(et131x_dbginfo, "status is  0x%08x\n",
+                           miiIndicator.value);
+               DBG_WARNING(et131x_dbginfo, "command is  0x%08x\n",
+                           readl(&mac->mii_mgmt_cmd.value));
+
+               MiRead(adapter, xcvrReg, &TempValue);
+
+               status = -EIO;
+       }
+
+       /* Stop the write operation */
+       writel(0, &mac->mii_mgmt_cmd.value);
+
+       /* set the registers we touched back to the state at which we entered
+         * this function
+         */
+       writel(miiAddr.value, &mac->mii_mgmt_addr.value);
+       writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
+
+       DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, "
+                   "xcvr_reg  = 0x%02x, "
+                   "value     = 0x%04x.\n", xcvrAddr, xcvrReg, value);
+
+       return status;
+}
+
+/**
+ * et131x_xcvr_find - Find the PHY ID
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_xcvr_find(struct et131x_adapter *adapter)
+{
+       int status = -ENODEV;
+       uint8_t xcvr_addr;
+       MI_IDR1_t idr1;
+       MI_IDR2_t idr2;
+       uint32_t xcvr_id;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* We need to get xcvr id and address we just get the first one */
+       for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
+               /* Read the ID from the PHY */
+               PhyMiRead(adapter, xcvr_addr,
+                         (uint8_t) offsetof(MI_REGS_t, idr1),
+                         &idr1.value);
+               PhyMiRead(adapter, xcvr_addr,
+                         (uint8_t) offsetof(MI_REGS_t, idr2),
+                         &idr2.value);
+
+               xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value);
+
+               if ((idr1.value != 0) && (idr1.value != 0xffff)) {
+                       DBG_TRACE(et131x_dbginfo,
+                                 "Xcvr addr: 0x%02x\tXcvr_id: 0x%08x\n",
+                                 xcvr_addr, xcvr_id);
+
+                       adapter->Stats.xcvr_id = xcvr_id;
+                       adapter->Stats.xcvr_addr = xcvr_addr;
+
+                       status = 0;
+                       break;
+               }
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+       return status;
+}
+
+/**
+ * et131x_setphy_normal - Set PHY for normal operation.
+ * @adapter: pointer to our private adapter structure
+ *
+ * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
+ * when going to D3 in WOL mode. Also used during initialization to set the
+ * PHY for normal operation.
+ */
+int et131x_setphy_normal(struct et131x_adapter *adapter)
+{
+       int status;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Make sure the PHY is powered up */
+       ET1310_PhyPowerDown(adapter, 0);
+       status = et131x_xcvr_init(adapter);
+
+       DBG_LEAVE(et131x_dbginfo);
+       return status;
+}
+
+/**
+ * et131x_xcvr_init - Init the phy if we are setting it into force mode
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+static int et131x_xcvr_init(struct et131x_adapter *adapter)
+{
+       int status = 0;
+       MI_IMR_t imr;
+       MI_ISR_t isr;
+       MI_LCR2_t lcr2;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Zero out the adapter structure variable representing BMSR */
+       adapter->Bmsr.value = 0;
+
+       MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value);
+
+       MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value);
+
+       /* Set the link status interrupt only.  Bad behavior when link status
+        * and auto neg are set, we run into a nested interrupt problem
+        */
+       imr.bits.int_en = 0x1;
+       imr.bits.link_status = 0x1;
+       imr.bits.autoneg_status = 0x1;
+
+       MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value);
+
+       /* Set the LED behavior such that LED 1 indicates speed (off =
+        * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
+        * link and activity (on for link, blink off for activity).
+        *
+        * NOTE: Some customizations have been added here for specific
+        * vendors; The LED behavior is now determined by vendor data in the
+        * EEPROM. However, the above description is the default.
+        */
+       if ((adapter->eepromData[1] & 0x4) == 0) {
+               MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
+                      &lcr2.value);
+               if ((adapter->eepromData[1] & 0x8) == 0)
+                       lcr2.bits.led_tx_rx = 0x3;
+               else
+                       lcr2.bits.led_tx_rx = 0x4;
+               lcr2.bits.led_link = 0xa;
+               MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
+                       lcr2.value);
+       }
+
+       /* Determine if we need to go into a force mode and set it */
+       if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
+               if ((adapter->RegistryFlowControl == TxOnly) ||
+                   (adapter->RegistryFlowControl == Both)) {
+                       ET1310_PhyAccessMiBit(adapter,
+                                             TRUEPHY_BIT_SET, 4, 11, NULL);
+               } else {
+                       ET1310_PhyAccessMiBit(adapter,
+                                             TRUEPHY_BIT_CLEAR, 4, 11, NULL);
+               }
+
+               if (adapter->RegistryFlowControl == Both) {
+                       ET1310_PhyAccessMiBit(adapter,
+                                             TRUEPHY_BIT_SET, 4, 10, NULL);
+               } else {
+                       ET1310_PhyAccessMiBit(adapter,
+                                             TRUEPHY_BIT_CLEAR, 4, 10, NULL);
+               }
+
+               /* Set the phy to autonegotiation */
+               ET1310_PhyAutoNeg(adapter, true);
+
+               /* NOTE - Do we need this? */
+               ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
+
+               DBG_LEAVE(et131x_dbginfo);
+               return status;
+       } else {
+               ET1310_PhyAutoNeg(adapter, false);
+
+               /* Set to the correct force mode. */
+               if (adapter->AiForceDpx != 1) {
+                       if ((adapter->RegistryFlowControl == TxOnly) ||
+                           (adapter->RegistryFlowControl == Both)) {
+                               ET1310_PhyAccessMiBit(adapter,
+                                                     TRUEPHY_BIT_SET, 4, 11,
+                                                     NULL);
+                       } else {
+                               ET1310_PhyAccessMiBit(adapter,
+                                                     TRUEPHY_BIT_CLEAR, 4, 11,
+                                                     NULL);
+                       }
+
+                       if (adapter->RegistryFlowControl == Both) {
+                               ET1310_PhyAccessMiBit(adapter,
+                                                     TRUEPHY_BIT_SET, 4, 10,
+                                                     NULL);
+                       } else {
+                               ET1310_PhyAccessMiBit(adapter,
+                                                     TRUEPHY_BIT_CLEAR, 4, 10,
+                                                     NULL);
+                       }
+               } else {
+                       ET1310_PhyAccessMiBit(adapter,
+                                             TRUEPHY_BIT_CLEAR, 4, 10, NULL);
+                       ET1310_PhyAccessMiBit(adapter,
+                                             TRUEPHY_BIT_CLEAR, 4, 11, NULL);
+               }
+
+               switch (adapter->AiForceSpeed) {
+               case 10:
+                       if (adapter->AiForceDpx == 1) {
+                               TPAL_SetPhy10HalfDuplex(adapter);
+                       } else if (adapter->AiForceDpx == 2) {
+                               TPAL_SetPhy10FullDuplex(adapter);
+                       } else {
+                               TPAL_SetPhy10Force(adapter);
+                       }
+                       break;
+               case 100:
+                       if (adapter->AiForceDpx == 1) {
+                               TPAL_SetPhy100HalfDuplex(adapter);
+                       } else if (adapter->AiForceDpx == 2) {
+                               TPAL_SetPhy100FullDuplex(adapter);
+                       } else {
+                               TPAL_SetPhy100Force(adapter);
+                       }
+                       break;
+               case 1000:
+                       TPAL_SetPhy1000FullDuplex(adapter);
+                       break;
+               }
+
+               DBG_LEAVE(et131x_dbginfo);
+               return status;
+       }
+}
+
+void et131x_Mii_check(struct et131x_adapter *pAdapter,
+                     MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
+{
+       uint8_t ucLinkStatus;
+       uint32_t uiAutoNegStatus;
+       uint32_t uiSpeed;
+       uint32_t uiDuplex;
+       uint32_t uiMdiMdix;
+       uint32_t uiMasterSlave;
+       uint32_t uiPolarity;
+       unsigned long lockflags;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       if (bmsr_ints.bits.link_status) {
+               if (bmsr.bits.link_status) {
+                       pAdapter->PoMgmt.TransPhyComaModeOnBoot = 20;
+
+                       /* Update our state variables and indicate the
+                        * connected state
+                        */
+                       spin_lock_irqsave(&pAdapter->Lock, lockflags);
+
+                       pAdapter->MediaState = NETIF_STATUS_MEDIA_CONNECT;
+                       MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION);
+
+                       spin_unlock_irqrestore(&pAdapter->Lock, lockflags);
+
+                       /* Don't indicate state if we're in loopback mode */
+                       if (pAdapter->RegistryPhyLoopbk == false) {
+                               netif_carrier_on(pAdapter->netdev);
+                       }
+               } else {
+                       DBG_WARNING(et131x_dbginfo,
+                                   "Link down cable problem\n");
+
+                       if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
+                               // NOTE - Is there a way to query this without TruePHY?
+                               // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
+                               uint16_t Register18;
+
+                               MiRead(pAdapter, 0x12, &Register18);
+                               MiWrite(pAdapter, 0x12, Register18 | 0x4);
+                               MiWrite(pAdapter, 0x10, Register18 | 0x8402);
+                               MiWrite(pAdapter, 0x11, Register18 | 511);
+                               MiWrite(pAdapter, 0x12, Register18);
+                       }
+
+                       /* For the first N seconds of life, we are in "link
+                        * detection" When we are in this state, we should
+                        * only report "connected". When the LinkDetection
+                        * Timer expires, we can report disconnected (handled
+                        * in the LinkDetectionDPC).
+                        */
+                       if ((MP_IS_FLAG_CLEAR
+                            (pAdapter, fMP_ADAPTER_LINK_DETECTION))
+                           || (pAdapter->MediaState ==
+                               NETIF_STATUS_MEDIA_DISCONNECT)) {
+                               spin_lock_irqsave(&pAdapter->Lock, lockflags);
+                               pAdapter->MediaState =
+                                   NETIF_STATUS_MEDIA_DISCONNECT;
+                               spin_unlock_irqrestore(&pAdapter->Lock,
+                                                      lockflags);
+
+                               /* Only indicate state if we're in loopback
+                                * mode
+                                */
+                               if (pAdapter->RegistryPhyLoopbk == false) {
+                                       netif_carrier_off(pAdapter->netdev);
+                               }
+                       }
+
+                       pAdapter->uiLinkSpeed = 0;
+                       pAdapter->uiDuplexMode = 0;
+
+                       /* Free the packets being actively sent & stopped */
+                       et131x_free_busy_send_packets(pAdapter);
+
+                       /* Re-initialize the send structures */
+                       et131x_init_send(pAdapter);
+
+                       /* Reset the RFD list and re-start RU */
+                       et131x_reset_recv(pAdapter);
+
+                       /*
+                        * Bring the device back to the state it was during
+                        * init prior to autonegotiation being complete. This
+                        * way, when we get the auto-neg complete interrupt,
+                        * we can complete init by calling ConfigMacREGS2.
+                        */
+                       et131x_soft_reset(pAdapter);
+
+                       /* Setup ET1310 as per the documentation */
+                       et131x_adapter_setup(pAdapter);
+
+                       /* Setup the PHY into coma mode until the cable is
+                        * plugged back in
+                        */
+                       if (pAdapter->RegistryPhyComa == 1) {
+                               EnablePhyComa(pAdapter);
+                       }
+               }
+       }
+
+       if (bmsr_ints.bits.auto_neg_complete ||
+           ((pAdapter->AiForceDpx == 3) && (bmsr_ints.bits.link_status))) {
+               if (bmsr.bits.auto_neg_complete || (pAdapter->AiForceDpx == 3)) {
+                       ET1310_PhyLinkStatus(pAdapter,
+                                            &ucLinkStatus, &uiAutoNegStatus,
+                                            &uiSpeed, &uiDuplex, &uiMdiMdix,
+                                            &uiMasterSlave, &uiPolarity);
+
+                       pAdapter->uiLinkSpeed = uiSpeed;
+                       pAdapter->uiDuplexMode = uiDuplex;
+
+                       DBG_TRACE(et131x_dbginfo,
+                                 "pAdapter->uiLinkSpeed 0x%04x, pAdapter->uiDuplex 0x%08x\n",
+                                 pAdapter->uiLinkSpeed,
+                                 pAdapter->uiDuplexMode);
+
+                       pAdapter->PoMgmt.TransPhyComaModeOnBoot = 20;
+
+                       if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
+                               // NOTE - Is there a way to query this without TruePHY?
+                               // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
+                               uint16_t Register18;
+
+                               MiRead(pAdapter, 0x12, &Register18);
+                               MiWrite(pAdapter, 0x12, Register18 | 0x4);
+                               MiWrite(pAdapter, 0x10, Register18 | 0x8402);
+                               MiWrite(pAdapter, 0x11, Register18 | 511);
+                               MiWrite(pAdapter, 0x12, Register18);
+                       }
+
+                       ConfigFlowControl(pAdapter);
+
+                       if ((pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) &&
+                           (pAdapter->RegistryJumboPacket > 2048))
+                       {
+                               ET1310_PhyAndOrReg(pAdapter, 0x16, 0xcfff,
+                                                  0x2000);
+                       }
+
+                       SetRxDmaTimer(pAdapter);
+                       ConfigMACRegs2(pAdapter);
+               }
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
+ * @pAdapter: pointer to the adapter structure
+ *
+ * Also sets the MAC so it is syncd up properly
+ */
+void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* First we need to turn off all other advertisement */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* Set our advertise values accordingly */
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_HALF);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
+ * @pAdapter: pointer to the adapter structure
+ *
+ * Also sets the MAC so it is syncd up properly
+ */
+void TPAL_SetPhy10FullDuplex(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* First we need to turn off all other advertisement */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* Set our advertise values accordingly */
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
+ * @pAdapter: pointer to the adapter structure
+ */
+void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* Disable autoneg */
+       ET1310_PhyAutoNeg(pAdapter, false);
+
+       /* Disable all advertisement */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* Force 10 Mbps */
+       ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_10MBPS);
+
+       /* Force Full duplex */
+       ET1310_PhyDuplexMode(pAdapter, TRUEPHY_DUPLEX_FULL);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
+ * @pAdapter: pointer to the adapter structure
+ *
+ * Also sets the MAC so it is syncd up properly.
+ */
+void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* first we need to turn off all other advertisement */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* Set our advertise values accordingly */
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_HALF);
+
+       /* Set speed */
+       ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_100MBPS);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
+ * @pAdapter: pointer to the adapter structure
+ *
+ * Also sets the MAC so it is syncd up properly
+ */
+void TPAL_SetPhy100FullDuplex(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* First we need to turn off all other advertisement */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* Set our advertise values accordingly */
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
+ * @pAdapter: pointer to the adapter structure
+ */
+void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* Disable autoneg */
+       ET1310_PhyAutoNeg(pAdapter, false);
+
+       /* Disable all advertisement */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* Force 100 Mbps */
+       ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_100MBPS);
+
+       /* Force Full duplex */
+       ET1310_PhyDuplexMode(pAdapter, TRUEPHY_DUPLEX_FULL);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
+ * @pAdapter: pointer to the adapter structure
+ *
+ * Also sets the MAC so it is syncd up properly.
+ */
+void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* first we need to turn off all other advertisement */
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+
+       /* set our advertise values accordingly */
+       ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
+
+       /* power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
+ * @pAdapter: pointer to the adapter structure
+ */
+void TPAL_SetPhyAutoNeg(struct et131x_adapter *pAdapter)
+{
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Power down PHY */
+       ET1310_PhyPowerDown(pAdapter, 1);
+
+       /* Turn on advertisement of all capabilities */
+       ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_BOTH);
+
+       ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_BOTH);
+
+       if (pAdapter->DeviceID != ET131X_PCI_DEVICE_ID_FAST) {
+               ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
+       } else {
+               ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
+       }
+
+       /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
+       ET1310_PhyAutoNeg(pAdapter, true);
+
+       /* Power up PHY */
+       ET1310_PhyPowerDown(pAdapter, 0);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+
+/*
+ * The routines which follow provide low-level access to the PHY, and are used
+ * primarily by the routines above (although there are a few places elsewhere
+ * in the driver where this level of access is required).
+ */
+
+static const uint16_t ConfigPhy[25][2] = {
+       /* Reg      Value      Register */
+       /* Addr                         */
+       {0x880B, 0x0926},       /* AfeIfCreg4B1000Msbs */
+       {0x880C, 0x0926},       /* AfeIfCreg4B100Msbs */
+       {0x880D, 0x0926},       /* AfeIfCreg4B10Msbs */
+
+       {0x880E, 0xB4D3},       /* AfeIfCreg4B1000Lsbs */
+       {0x880F, 0xB4D3},       /* AfeIfCreg4B100Lsbs */
+       {0x8810, 0xB4D3},       /* AfeIfCreg4B10Lsbs */
+
+       {0x8805, 0xB03E},       /* AfeIfCreg3B1000Msbs */
+       {0x8806, 0xB03E},       /* AfeIfCreg3B100Msbs */
+       {0x8807, 0xFF00},       /* AfeIfCreg3B10Msbs */
+
+       {0x8808, 0xE090},       /* AfeIfCreg3B1000Lsbs */
+       {0x8809, 0xE110},       /* AfeIfCreg3B100Lsbs */
+       {0x880A, 0x0000},       /* AfeIfCreg3B10Lsbs */
+
+       {0x300D, 1},            /* DisableNorm */
+
+       {0x280C, 0x0180},       /* LinkHoldEnd */
+
+       {0x1C21, 0x0002},       /* AlphaM */
+
+       {0x3821, 6},            /* FfeLkgTx0 */
+       {0x381D, 1},            /* FfeLkg1g4 */
+       {0x381E, 1},            /* FfeLkg1g5 */
+       {0x381F, 1},            /* FfeLkg1g6 */
+       {0x3820, 1},            /* FfeLkg1g7 */
+
+       {0x8402, 0x01F0},       /* Btinact */
+       {0x800E, 20},           /* LftrainTime */
+       {0x800F, 24},           /* DvguardTime */
+       {0x8010, 46},           /* IdlguardTime */
+
+       {0, 0}
+
+};
+
+/* condensed version of the phy initialization routine */
+void ET1310_PhyInit(struct et131x_adapter *pAdapter)
+{
+       uint16_t usData, usIndex;
+
+       if (pAdapter == NULL) {
+               return;
+       }
+
+       // get the identity (again ?)
+       MiRead(pAdapter, PHY_ID_1, &usData);
+       MiRead(pAdapter, PHY_ID_2, &usData);
+
+       // what does this do/achieve ?
+       MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0002
+       MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0006);
+
+       // read modem register 0402, should I do something with the return data ?
+       MiWrite(pAdapter, PHY_INDEX_REG, 0x0402);
+       MiRead(pAdapter, PHY_DATA_REG, &usData);
+
+       // what does this do/achieve ?
+       MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
+
+       // get the identity (again ?)
+       MiRead(pAdapter, PHY_ID_1, &usData);
+       MiRead(pAdapter, PHY_ID_2, &usData);
+
+       // what does this achieve ?
+       MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0002
+       MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0006);
+
+       // read modem register 0402, should I do something with the return data?
+       MiWrite(pAdapter, PHY_INDEX_REG, 0x0402);
+       MiRead(pAdapter, PHY_DATA_REG, &usData);
+
+       MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
+
+       // what does this achieve (should return 0x1040)
+       MiRead(pAdapter, PHY_CONTROL, &usData);
+       MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0002
+       MiWrite(pAdapter, PHY_CONTROL, 0x1840);
+
+       MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0007);
+
+       // here the writing of the array starts....
+       usIndex = 0;
+       while (ConfigPhy[usIndex][0] != 0x0000) {
+               // write value
+               MiWrite(pAdapter, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
+               MiWrite(pAdapter, PHY_DATA_REG, ConfigPhy[usIndex][1]);
+
+               // read it back
+               MiWrite(pAdapter, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
+               MiRead(pAdapter, PHY_DATA_REG, &usData);
+
+               // do a check on the value read back ?
+               usIndex++;
+       }
+       // here the writing of the array ends...
+
+       MiRead(pAdapter, PHY_CONTROL, &usData); // 0x1840
+       MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0007
+       MiWrite(pAdapter, PHY_CONTROL, 0x1040);
+       MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
+}
+
+void ET1310_PhyReset(struct et131x_adapter *pAdapter)
+{
+       MiWrite(pAdapter, PHY_CONTROL, 0x8000);
+}
+
+void ET1310_PhyPowerDown(struct et131x_adapter *pAdapter, bool down)
+{
+       uint16_t usData;
+
+       MiRead(pAdapter, PHY_CONTROL, &usData);
+
+       if (down == false) {
+               // Power UP
+               usData &= ~0x0800;
+               MiWrite(pAdapter, PHY_CONTROL, usData);
+       } else {
+               // Power DOWN
+               usData |= 0x0800;
+               MiWrite(pAdapter, PHY_CONTROL, usData);
+       }
+}
+
+void ET1310_PhyAutoNeg(struct et131x_adapter *pAdapter, bool enable)
+{
+       uint16_t usData;
+
+       MiRead(pAdapter, PHY_CONTROL, &usData);
+
+       if (enable == true) {
+               // Autonegotiation ON
+               usData |= 0x1000;
+               MiWrite(pAdapter, PHY_CONTROL, usData);
+       } else {
+               // Autonegotiation OFF
+               usData &= ~0x1000;
+               MiWrite(pAdapter, PHY_CONTROL, usData);
+       }
+}
+
+void ET1310_PhyDuplexMode(struct et131x_adapter *pAdapter, uint16_t duplex)
+{
+       uint16_t usData;
+
+       MiRead(pAdapter, PHY_CONTROL, &usData);
+
+       if (duplex == TRUEPHY_DUPLEX_FULL) {
+               // Set Full Duplex
+               usData |= 0x100;
+               MiWrite(pAdapter, PHY_CONTROL, usData);
+       } else {
+               // Set Half Duplex
+               usData &= ~0x100;
+               MiWrite(pAdapter, PHY_CONTROL, usData);
+       }
+}
+
+void ET1310_PhySpeedSelect(struct et131x_adapter *pAdapter, uint16_t speed)
+{
+       uint16_t usData;
+
+       // Read the PHY control register
+       MiRead(pAdapter, PHY_CONTROL, &usData);
+
+       // Clear all Speed settings (Bits 6, 13)
+       usData &= ~0x2040;
+
+       // Reset the speed bits based on user selection
+       switch (speed) {
+       case TRUEPHY_SPEED_10MBPS:
+               // Bits already cleared above, do nothing
+               break;
+
+       case TRUEPHY_SPEED_100MBPS:
+               // 100M == Set bit 13
+               usData |= 0x2000;
+               break;
+
+       case TRUEPHY_SPEED_1000MBPS:
+       default:
+               usData |= 0x0040;
+               break;
+       }
+
+       // Write back the new speed
+       MiWrite(pAdapter, PHY_CONTROL, usData);
+}
+
+void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *pAdapter,
+                                 uint16_t duplex)
+{
+       uint16_t usData;
+
+       // Read the PHY 1000 Base-T Control Register
+       MiRead(pAdapter, PHY_1000_CONTROL, &usData);
+
+       // Clear Bits 8,9
+       usData &= ~0x0300;
+
+       switch (duplex) {
+       case TRUEPHY_ADV_DUPLEX_NONE:
+               // Duplex already cleared, do nothing
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_FULL:
+               // Set Bit 9
+               usData |= 0x0200;
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_HALF:
+               // Set Bit 8
+               usData |= 0x0100;
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_BOTH:
+       default:
+               usData |= 0x0300;
+               break;
+       }
+
+       // Write back advertisement
+       MiWrite(pAdapter, PHY_1000_CONTROL, usData);
+}
+
+void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *pAdapter,
+                                uint16_t duplex)
+{
+       uint16_t usData;
+
+       // Read the Autonegotiation Register (10/100)
+       MiRead(pAdapter, PHY_AUTO_ADVERTISEMENT, &usData);
+
+       // Clear bits 7,8
+       usData &= ~0x0180;
+
+       switch (duplex) {
+       case TRUEPHY_ADV_DUPLEX_NONE:
+               // Duplex already cleared, do nothing
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_FULL:
+               // Set Bit 8
+               usData |= 0x0100;
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_HALF:
+               // Set Bit 7
+               usData |= 0x0080;
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_BOTH:
+       default:
+               // Set Bits 7,8
+               usData |= 0x0180;
+               break;
+       }
+
+       // Write back advertisement
+       MiWrite(pAdapter, PHY_AUTO_ADVERTISEMENT, usData);
+}
+
+void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *pAdapter,
+                               uint16_t duplex)
+{
+       uint16_t usData;
+
+       // Read the Autonegotiation Register (10/100)
+       MiRead(pAdapter, PHY_AUTO_ADVERTISEMENT, &usData);
+
+       // Clear bits 5,6
+       usData &= ~0x0060;
+
+       switch (duplex) {
+       case TRUEPHY_ADV_DUPLEX_NONE:
+               // Duplex already cleared, do nothing
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_FULL:
+               // Set Bit 6
+               usData |= 0x0040;
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_HALF:
+               // Set Bit 5
+               usData |= 0x0020;
+               break;
+
+       case TRUEPHY_ADV_DUPLEX_BOTH:
+       default:
+               // Set Bits 5,6
+               usData |= 0x0060;
+               break;
+       }
+
+       // Write back advertisement
+       MiWrite(pAdapter, PHY_AUTO_ADVERTISEMENT, usData);
+}
+
+void ET1310_PhyLinkStatus(struct et131x_adapter *pAdapter,
+                         uint8_t *ucLinkStatus,
+                         uint32_t *uiAutoNeg,
+                         uint32_t *uiLinkSpeed,
+                         uint32_t *uiDuplexMode,
+                         uint32_t *uiMdiMdix,
+                         uint32_t *uiMasterSlave, uint32_t *uiPolarity)
+{
+       uint16_t usMiStatus = 0;
+       uint16_t us1000BaseT = 0;
+       uint16_t usVmiPhyStatus = 0;
+       uint16_t usControl = 0;
+
+       MiRead(pAdapter, PHY_STATUS, &usMiStatus);
+       MiRead(pAdapter, PHY_1000_STATUS, &us1000BaseT);
+       MiRead(pAdapter, PHY_PHY_STATUS, &usVmiPhyStatus);
+       MiRead(pAdapter, PHY_CONTROL, &usControl);
+
+       if (ucLinkStatus) {
+               *ucLinkStatus =
+                   (unsigned char)((usVmiPhyStatus & 0x0040) ? 1 : 0);
+       }
+
+       if (uiAutoNeg) {
+               *uiAutoNeg =
+                   (usControl & 0x1000) ? ((usVmiPhyStatus & 0x0020) ?
+                                           TRUEPHY_ANEG_COMPLETE :
+                                           TRUEPHY_ANEG_NOT_COMPLETE) :
+                   TRUEPHY_ANEG_DISABLED;
+       }
+
+       if (uiLinkSpeed) {
+               *uiLinkSpeed = (usVmiPhyStatus & 0x0300) >> 8;
+       }
+
+       if (uiDuplexMode) {
+               *uiDuplexMode = (usVmiPhyStatus & 0x0080) >> 7;
+       }
+
+       if (uiMdiMdix) {
+               /* NOTE: Need to complete this */
+               *uiMdiMdix = 0;
+       }
+
+       if (uiMasterSlave) {
+               *uiMasterSlave =
+                   (us1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
+                   TRUEPHY_CFG_SLAVE;
+       }
+
+       if (uiPolarity) {
+               *uiPolarity =
+                   (usVmiPhyStatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
+                   TRUEPHY_POLARITY_NORMAL;
+       }
+}
+
+void ET1310_PhyAndOrReg(struct et131x_adapter *pAdapter,
+                       uint16_t regnum, uint16_t andMask, uint16_t orMask)
+{
+       uint16_t reg;
+
+       // Read the requested register
+       MiRead(pAdapter, regnum, &reg);
+
+       // Apply the AND mask
+       reg &= andMask;
+
+       // Apply the OR mask
+       reg |= orMask;
+
+       // Write the value back to the register
+       MiWrite(pAdapter, regnum, reg);
+}
+
+void ET1310_PhyAccessMiBit(struct et131x_adapter *pAdapter, uint16_t action,
+                          uint16_t regnum, uint16_t bitnum, uint8_t *value)
+{
+       uint16_t reg;
+       uint16_t mask = 0;
+
+       // Create a mask to isolate the requested bit
+       mask = 0x0001 << bitnum;
+
+       // Read the requested register
+       MiRead(pAdapter, regnum, &reg);
+
+       switch (action) {
+       case TRUEPHY_BIT_READ:
+               if (value != NULL) {
+                       *value = (reg & mask) >> bitnum;
+               }
+               break;
+
+       case TRUEPHY_BIT_SET:
+               reg |= mask;
+               MiWrite(pAdapter, regnum, reg);
+               break;
+
+       case TRUEPHY_BIT_CLEAR:
+               reg &= ~mask;
+               MiWrite(pAdapter, regnum, reg);
+               break;
+
+       default:
+               break;
+       }
+}
diff --git a/src/et131x/et1310_phy.h b/src/et131x/et1310_phy.h
new file mode 100644 (file)
index 0000000..d624cbb
--- /dev/null
@@ -0,0 +1,910 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
+ *                PHY.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef _ET1310_PHY_H_
+#define _ET1310_PHY_H_
+
+#include "et1310_address_map.h"
+
+#define TRUEPHY_SUCCESS 0
+#define TRUEPHY_FAILURE 1
+typedef void *TRUEPHY_HANDLE;
+typedef void *TRUEPHY_PLATFORM_HANDLE;
+typedef void *TRUEPHY_OSAL_HANDLE;
+
+/* MI Register Addresses */
+#define MI_CONTROL_REG                      0
+#define MI_STATUS_REG                       1
+#define MI_PHY_IDENTIFIER_1_REG             2
+#define MI_PHY_IDENTIFIER_2_REG             3
+#define MI_AUTONEG_ADVERTISEMENT_REG        4
+#define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
+#define MI_AUTONEG_EXPANSION_REG            6
+#define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG   7
+#define MI_LINK_PARTNER_NEXT_PAGE_REG       8
+#define MI_1000BASET_CONTROL_REG            9
+#define MI_1000BASET_STATUS_REG             10
+#define MI_RESERVED11_REG                   11
+#define MI_RESERVED12_REG                   12
+#define MI_RESERVED13_REG                   13
+#define MI_RESERVED14_REG                   14
+#define MI_EXTENDED_STATUS_REG              15
+
+/* VMI Register Addresses */
+#define VMI_RESERVED16_REG                  16
+#define VMI_RESERVED17_REG                  17
+#define VMI_RESERVED18_REG                  18
+#define VMI_LOOPBACK_CONTROL_REG            19
+#define VMI_RESERVED20_REG                  20
+#define VMI_MI_CONTROL_REG                  21
+#define VMI_PHY_CONFIGURATION_REG           22
+#define VMI_PHY_CONTROL_REG                 23
+#define VMI_INTERRUPT_MASK_REG              24
+#define VMI_INTERRUPT_STATUS_REG            25
+#define VMI_PHY_STATUS_REG                  26
+#define VMI_LED_CONTROL_1_REG               27
+#define VMI_LED_CONTROL_2_REG               28
+#define VMI_RESERVED29_REG                  29
+#define VMI_RESERVED30_REG                  30
+#define VMI_RESERVED31_REG                  31
+
+/* PHY Register Mapping(MI) Management Interface Regs */
+typedef struct _MI_REGS_t {
+       u8 bmcr;                // Basic mode control reg(Reg 0x00)
+       u8 bmsr;                // Basic mode status reg(Reg 0x01)
+       u8 idr1;                // Phy identifier reg 1(Reg 0x02)
+       u8 idr2;                // Phy identifier reg 2(Reg 0x03)
+       u8 anar;                // Auto-Negotiation advertisement(Reg 0x04)
+       u8 anlpar;              // Auto-Negotiation link Partner Ability(Reg 0x05)
+       u8 aner;                // Auto-Negotiation expansion reg(Reg 0x06)
+       u8 annptr;              // Auto-Negotiation next page transmit reg(Reg 0x07)
+       u8 lpnpr;               // link partner next page reg(Reg 0x08)
+       u8 gcr;         // Gigabit basic mode control reg(Reg 0x09)
+       u8 gsr;         // Gigabit basic mode status reg(Reg 0x0A)
+       u8 mi_res1[4];  // Future use by MI working group(Reg 0x0B - 0x0E)
+       u8 esr;         // Extended status reg(Reg 0x0F)
+       u8 mi_res2[3];  // Future use by MI working group(Reg 0x10 - 0x12)
+       u8 loop_ctl;    // Loopback Control Reg(Reg 0x13)
+       u8 mi_res3;     // Future use by MI working group(Reg 0x14)
+       u8 mcr;         // MI Control Reg(Reg 0x15)
+       u8 pcr;         // Configuration Reg(Reg 0x16)
+       u8 phy_ctl;     // PHY Control Reg(Reg 0x17)
+       u8 imr;         // Interrupt Mask Reg(Reg 0x18)
+       u8 isr;         // Interrupt Status Reg(Reg 0x19)
+       u8 psr;         // PHY Status Reg(Reg 0x1A)
+       u8 lcr1;                // LED Control 1 Reg(Reg 0x1B)
+       u8 lcr2;                // LED Control 2 Reg(Reg 0x1C)
+       u8 mi_res4[3];  // Future use by MI working group(Reg 0x1D - 0x1F)
+} MI_REGS_t, *PMI_REGS_t;
+
+/* MI Register 0: Basic mode control register */
+typedef union _MI_BMCR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 reset:1;            // bit 15
+               u16 loopback:1;         // bit 14
+               u16 speed_sel:1;                // bit 13
+               u16 enable_autoneg:1;   // bit 12
+               u16 power_down:1;               // bit 11
+               u16 isolate:1;          // bit 10
+               u16 restart_autoneg:1;  // bit 9
+               u16 duplex_mode:1;              // bit 8
+               u16 col_test:1;         // bit 7
+               u16 speed_1000_sel:1;   // bit 6
+               u16 res1:6;             // bits 0-5
+#else
+               u16 res1:6;             // bits 0-5
+               u16 speed_1000_sel:1;   // bit 6
+               u16 col_test:1;         // bit 7
+               u16 duplex_mode:1;              // bit 8
+               u16 restart_autoneg:1;  // bit 9
+               u16 isolate:1;          // bit 10
+               u16 power_down:1;               // bit 11
+               u16 enable_autoneg:1;   // bit 12
+               u16 speed_sel:1;                // bit 13
+               u16 loopback:1;         // bit 14
+               u16 reset:1;            // bit 15
+#endif
+       } bits;
+} MI_BMCR_t, *PMI_BMCR_t;
+
+/* MI Register 1:  Basic mode status register */
+typedef union _MI_BMSR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 link_100T4:1;               // bit 15
+               u16 link_100fdx:1;              // bit 14
+               u16 link_100hdx:1;              // bit 13
+               u16 link_10fdx:1;               // bit 12
+               u16 link_10hdx:1;               // bit 11
+               u16 link_100T2fdx:1;    // bit 10
+               u16 link_100T2hdx:1;    // bit 9
+               u16 extend_status:1;    // bit 8
+               u16 res1:1;             // bit 7
+               u16 preamble_supress:1; // bit 6
+               u16 auto_neg_complete:1;        // bit 5
+               u16 remote_fault:1;     // bit 4
+               u16 auto_neg_able:1;    // bit 3
+               u16 link_status:1;              // bit 2
+               u16 jabber_detect:1;    // bit 1
+               u16 ext_cap:1;          // bit 0
+#else
+               u16 ext_cap:1;          // bit 0
+               u16 jabber_detect:1;    // bit 1
+               u16 link_status:1;              // bit 2
+               u16 auto_neg_able:1;    // bit 3
+               u16 remote_fault:1;     // bit 4
+               u16 auto_neg_complete:1;        // bit 5
+               u16 preamble_supress:1; // bit 6
+               u16 res1:1;             // bit 7
+               u16 extend_status:1;    // bit 8
+               u16 link_100T2hdx:1;    // bit 9
+               u16 link_100T2fdx:1;    // bit 10
+               u16 link_10hdx:1;               // bit 11
+               u16 link_10fdx:1;               // bit 12
+               u16 link_100hdx:1;              // bit 13
+               u16 link_100fdx:1;              // bit 14
+               u16 link_100T4:1;               // bit 15
+#endif
+       } bits;
+} MI_BMSR_t, *PMI_BMSR_t;
+
+/* MI Register 2: Physical Identifier 1 */
+typedef union _MI_IDR1_t {
+       u16 value;
+       struct {
+               u16 ieee_address:16;    // 0x0282 default(bits 0-15)
+       } bits;
+} MI_IDR1_t, *PMI_IDR1_t;
+
+/* MI Register 3: Physical Identifier 2 */
+typedef union _MI_IDR2_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 ieee_address:6;     // 111100 default(bits 10-15)
+               u16 model_no:6;         // 000001 default(bits 4-9)
+               u16 rev_no:4;           // 0010   default(bits 0-3)
+#else
+               u16 rev_no:4;           // 0010   default(bits 0-3)
+               u16 model_no:6;         // 000001 default(bits 4-9)
+               u16 ieee_address:6;     // 111100 default(bits 10-15)
+#endif
+       } bits;
+} MI_IDR2_t, *PMI_IDR2_t;
+
+/* MI Register 4: Auto-negotiation advertisement register */
+typedef union _MI_ANAR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 np_indication:1;    // bit 15
+               u16 res2:1;             // bit 14
+               u16 remote_fault:1;     // bit 13
+               u16 res1:1;             // bit 12
+               u16 cap_asmpause:1;     // bit 11
+               u16 cap_pause:1;                // bit 10
+               u16 cap_100T4:1;                // bit 9
+               u16 cap_100fdx:1;               // bit 8
+               u16 cap_100hdx:1;               // bit 7
+               u16 cap_10fdx:1;                // bit 6
+               u16 cap_10hdx:1;                // bit 5
+               u16 selector:5;         // bits 0-4
+#else
+               u16 selector:5;         // bits 0-4
+               u16 cap_10hdx:1;                // bit 5
+               u16 cap_10fdx:1;                // bit 6
+               u16 cap_100hdx:1;               // bit 7
+               u16 cap_100fdx:1;               // bit 8
+               u16 cap_100T4:1;                // bit 9
+               u16 cap_pause:1;                // bit 10
+               u16 cap_asmpause:1;     // bit 11
+               u16 res1:1;             // bit 12
+               u16 remote_fault:1;     // bit 13
+               u16 res2:1;             // bit 14
+               u16 np_indication:1;    // bit 15
+#endif
+       } bits;
+} MI_ANAR_t, *PMI_ANAR_t;
+
+/* MI Register 5: Auto-negotiation link partner advertisement register */
+typedef struct _MI_ANLPAR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 np_indication:1;    // bit 15
+               u16 acknowledge:1;              // bit 14
+               u16 remote_fault:1;     // bit 13
+               u16 res1:1;             // bit 12
+               u16 cap_asmpause:1;     // bit 11
+               u16 cap_pause:1;                // bit 10
+               u16 cap_100T4:1;                // bit 9
+               u16 cap_100fdx:1;               // bit 8
+               u16 cap_100hdx:1;               // bit 7
+               u16 cap_10fdx:1;                // bit 6
+               u16 cap_10hdx:1;                // bit 5
+               u16 selector:5;         // bits 0-4
+#else
+               u16 selector:5;         // bits 0-4
+               u16 cap_10hdx:1;                // bit 5
+               u16 cap_10fdx:1;                // bit 6
+               u16 cap_100hdx:1;               // bit 7
+               u16 cap_100fdx:1;               // bit 8
+               u16 cap_100T4:1;                // bit 9
+               u16 cap_pause:1;                // bit 10
+               u16 cap_asmpause:1;     // bit 11
+               u16 res1:1;             // bit 12
+               u16 remote_fault:1;     // bit 13
+               u16 acknowledge:1;              // bit 14
+               u16 np_indication:1;    // bit 15
+#endif
+       } bits;
+} MI_ANLPAR_t, *PMI_ANLPAR_t;
+
+/* MI Register 6: Auto-negotiation expansion register */
+typedef union _MI_ANER_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res:11;     // bits 5-15
+               u16 pdf:1;              // bit 4
+               u16 lp_np_able:1;       // bit 3
+               u16 np_able:1;  // bit 2
+               u16 page_rx:1;  // bit 1
+               u16 lp_an_able:1;       // bit 0
+#else
+               u16 lp_an_able:1;       // bit 0
+               u16 page_rx:1;  // bit 1
+               u16 np_able:1;  // bit 2
+               u16 lp_np_able:1;       // bit 3
+               u16 pdf:1;              // bit 4
+               u16 res:11;     // bits 5-15
+#endif
+       } bits;
+} MI_ANER_t, *PMI_ANER_t;
+
+/* MI Register 7: Auto-negotiation next page transmit reg(0x07) */
+typedef union _MI_ANNPTR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 np:1;               // bit 15
+               u16 res1:1;     // bit 14
+               u16 msg_page:1; // bit 13
+               u16 ack2:1;     // bit 12
+               u16 toggle:1;   // bit 11
+               u16 msg:11;     // bits 0-10
+#else
+               u16 msg:11;     // bits 0-10
+               u16 toggle:1;   // bit 11
+               u16 ack2:1;     // bit 12
+               u16 msg_page:1; // bit 13
+               u16 res1:1;     // bit 14
+               u16 np:1;               // bit 15
+#endif
+       } bits;
+} MI_ANNPTR_t, *PMI_ANNPTR_t;
+
+/* MI Register 8: Link Partner Next Page Reg(0x08) */
+typedef union _MI_LPNPR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 np:1;               // bit 15
+               u16 ack:1;              // bit 14
+               u16 msg_page:1; // bit 13
+               u16 ack2:1;     // bit 12
+               u16 toggle:1;   // bit 11
+               u16 msg:11;     // bits 0-10
+#else
+               u16 msg:11;     // bits 0-10
+               u16 toggle:1;   // bit 11
+               u16 ack2:1;     // bit 12
+               u16 msg_page:1; // bit 13
+               u16 ack:1;              // bit 14
+               u16 np:1;               // bit 15
+#endif
+       } bits;
+} MI_LPNPR_t, *PMI_LPNPR_t;
+
+/* MI Register 9: 1000BaseT Control Reg(0x09) */
+typedef union _MI_GCR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 test_mode:3;                // bits 13-15
+               u16 ms_config_en:1;     // bit 12
+               u16 ms_value:1;         // bit 11
+               u16 port_type:1;                // bit 10
+               u16 link_1000fdx:1;     // bit 9
+               u16 link_1000hdx:1;     // bit 8
+               u16 res:8;                      // bit 0-7
+#else
+               u16 res:8;                      // bit 0-7
+               u16 link_1000hdx:1;     // bit 8
+               u16 link_1000fdx:1;     // bit 9
+               u16 port_type:1;                // bit 10
+               u16 ms_value:1;         // bit 11
+               u16 ms_config_en:1;     // bit 12
+               u16 test_mode:3;                // bits 13-15
+#endif
+       } bits;
+} MI_GCR_t, *PMI_GCR_t;
+
+/* MI Register 10: 1000BaseT Status Reg(0x0A) */
+typedef union _MI_GSR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 ms_config_fault:1;  // bit 15
+               u16 ms_resolve:1;               // bit 14
+               u16 local_rx_status:1;  // bit 13
+               u16 remote_rx_status:1; // bit 12
+               u16 link_1000fdx:1;     // bit 11
+               u16 link_1000hdx:1;     // bit 10
+               u16 res:2;                      // bits 8-9
+               u16 idle_err_cnt:8;     // bits 0-7
+#else
+               u16 idle_err_cnt:8;     // bits 0-7
+               u16 res:2;                      // bits 8-9
+               u16 link_1000hdx:1;     // bit 10
+               u16 link_1000fdx:1;     // bit 11
+               u16 remote_rx_status:1; // bit 12
+               u16 local_rx_status:1;  // bit 13
+               u16 ms_resolve:1;               // bit 14
+               u16 ms_config_fault:1;  // bit 15
+#endif
+       } bits;
+} MI_GSR_t, *PMI_GSR_t;
+
+/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
+typedef union _MI_RES_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res15:1;    // bit 15
+               u16 res14:1;    // bit 14
+               u16 res13:1;    // bit 13
+               u16 res12:1;    // bit 12
+               u16 res11:1;    // bit 11
+               u16 res10:1;    // bit 10
+               u16 res9:1;     // bit 9
+               u16 res8:1;     // bit 8
+               u16 res7:1;     // bit 7
+               u16 res6:1;     // bit 6
+               u16 res5:1;     // bit 5
+               u16 res4:1;     // bit 4
+               u16 res3:1;     // bit 3
+               u16 res2:1;     // bit 2
+               u16 res1:1;     // bit 1
+               u16 res0:1;     // bit 0
+#else
+               u16 res0:1;     // bit 0
+               u16 res1:1;     // bit 1
+               u16 res2:1;     // bit 2
+               u16 res3:1;     // bit 3
+               u16 res4:1;     // bit 4
+               u16 res5:1;     // bit 5
+               u16 res6:1;     // bit 6
+               u16 res7:1;     // bit 7
+               u16 res8:1;     // bit 8
+               u16 res9:1;     // bit 9
+               u16 res10:1;    // bit 10
+               u16 res11:1;    // bit 11
+               u16 res12:1;    // bit 12
+               u16 res13:1;    // bit 13
+               u16 res14:1;    // bit 14
+               u16 res15:1;    // bit 15
+#endif
+       } bits;
+} MI_RES_t, *PMI_RES_t;
+
+/* MI Register 15: Extended status Reg(0x0F) */
+typedef union _MI_ESR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 link_1000Xfdx:1;    // bit 15
+               u16 link_1000Xhdx:1;    // bit 14
+               u16 link_1000fdx:1;     // bit 13
+               u16 link_1000hdx:1;     // bit 12
+               u16 res:12;             // bit 0-11
+#else
+               u16 res:12;             // bit 0-11
+               u16 link_1000hdx:1;     // bit 12
+               u16 link_1000fdx:1;     // bit 13
+               u16 link_1000Xhdx:1;    // bit 14
+               u16 link_1000Xfdx:1;    // bit 15
+#endif
+       } bits;
+} MI_ESR_t, *PMI_ESR_t;
+
+/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
+
+/* MI Register 19: Loopback Control Reg(0x13) */
+typedef union _MI_LCR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 mii_en:1;           // bit 15
+               u16 pcs_en:1;           // bit 14
+               u16 pmd_en:1;           // bit 13
+               u16 all_digital_en:1;   // bit 12
+               u16 replica_en:1;               // bit 11
+               u16 line_driver_en:1;   // bit 10
+               u16 res:10;             // bit 0-9
+#else
+               u16 res:10;             // bit 0-9
+               u16 line_driver_en:1;   // bit 10
+               u16 replica_en:1;               // bit 11
+               u16 all_digital_en:1;   // bit 12
+               u16 pmd_en:1;           // bit 13
+               u16 pcs_en:1;           // bit 14
+               u16 mii_en:1;           // bit 15
+#endif
+       } bits;
+} MI_LCR_t, *PMI_LCR_t;
+
+/* MI Register 20: Reserved Reg(0x14) */
+
+/* MI Register 21: Management Interface Control Reg(0x15) */
+typedef union _MI_MICR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res1:5;             // bits 11-15
+               u16 mi_error_count:7;   // bits 4-10
+               u16 res2:1;             // bit 3
+               u16 ignore_10g_fr:1;    // bit 2
+               u16 res3:1;             // bit 1
+               u16 preamble_supress_en:1;      // bit 0
+#else
+               u16 preamble_supress_en:1;      // bit 0
+               u16 res3:1;             // bit 1
+               u16 ignore_10g_fr:1;    // bit 2
+               u16 res2:1;             // bit 3
+               u16 mi_error_count:7;   // bits 4-10
+               u16 res1:5;             // bits 11-15
+#endif
+       } bits;
+} MI_MICR_t, *PMI_MICR_t;
+
+/* MI Register 22: PHY Configuration Reg(0x16) */
+typedef union _MI_PHY_CONFIG_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 crs_tx_en:1;                // bit 15
+               u16 res1:1;             // bit 14
+               u16 tx_fifo_depth:2;    // bits 12-13
+               u16 speed_downshift:2;  // bits 10-11
+               u16 pbi_detect:1;               // bit 9
+               u16 tbi_rate:1;         // bit 8
+               u16 alternate_np:1;     // bit 7
+               u16 group_mdio_en:1;    // bit 6
+               u16 tx_clock_en:1;              // bit 5
+               u16 sys_clock_en:1;     // bit 4
+               u16 res2:1;             // bit 3
+               u16 mac_if_mode:3;              // bits 0-2
+#else
+               u16 mac_if_mode:3;              // bits 0-2
+               u16 res2:1;             // bit 3
+               u16 sys_clock_en:1;     // bit 4
+               u16 tx_clock_en:1;              // bit 5
+               u16 group_mdio_en:1;    // bit 6
+               u16 alternate_np:1;     // bit 7
+               u16 tbi_rate:1;         // bit 8
+               u16 pbi_detect:1;               // bit 9
+               u16 speed_downshift:2;  // bits 10-11
+               u16 tx_fifo_depth:2;    // bits 12-13
+               u16 res1:1;             // bit 14
+               u16 crs_tx_en:1;                // bit 15
+#endif
+       } bits;
+} MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
+
+/* MI Register 23: PHY CONTROL Reg(0x17) */
+typedef union _MI_PHY_CONTROL_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res1:1;             // bit 15
+               u16 tdr_en:1;           // bit 14
+               u16 res2:1;             // bit 13
+               u16 downshift_attempts:2;       // bits 11-12
+               u16 res3:5;             // bit 6-10
+               u16 jabber_10baseT:1;   // bit 5
+               u16 sqe_10baseT:1;              // bit 4
+               u16 tp_loopback_10baseT:1;      // bit 3
+               u16 preamble_gen_en:1;  // bit 2
+               u16 res4:1;             // bit 1
+               u16 force_int:1;                // bit 0
+#else
+               u16 force_int:1;                // bit 0
+               u16 res4:1;             // bit 1
+               u16 preamble_gen_en:1;  // bit 2
+               u16 tp_loopback_10baseT:1;      // bit 3
+               u16 sqe_10baseT:1;              // bit 4
+               u16 jabber_10baseT:1;   // bit 5
+               u16 res3:5;             // bit 6-10
+               u16 downshift_attempts:2;       // bits 11-12
+               u16 res2:1;             // bit 13
+               u16 tdr_en:1;           // bit 14
+               u16 res1:1;             // bit 15
+#endif
+       } bits;
+} MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
+
+/* MI Register 24: Interrupt Mask Reg(0x18) */
+typedef union _MI_IMR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res1:6;             // bits 10-15
+               u16 mdio_sync_lost:1;   // bit 9
+               u16 autoneg_status:1;   // bit 8
+               u16 hi_bit_err:1;               // bit 7
+               u16 np_rx:1;            // bit 6
+               u16 err_counter_full:1; // bit 5
+               u16 fifo_over_underflow:1;      // bit 4
+               u16 rx_status:1;                // bit 3
+               u16 link_status:1;              // bit 2
+               u16 automatic_speed:1;  // bit 1
+               u16 int_en:1;           // bit 0
+#else
+               u16 int_en:1;           // bit 0
+               u16 automatic_speed:1;  // bit 1
+               u16 link_status:1;              // bit 2
+               u16 rx_status:1;                // bit 3
+               u16 fifo_over_underflow:1;      // bit 4
+               u16 err_counter_full:1; // bit 5
+               u16 np_rx:1;            // bit 6
+               u16 hi_bit_err:1;               // bit 7
+               u16 autoneg_status:1;   // bit 8
+               u16 mdio_sync_lost:1;   // bit 9
+               u16 res1:6;             // bits 10-15
+#endif
+       } bits;
+} MI_IMR_t, *PMI_IMR_t;
+
+/* MI Register 25: Interrupt Status Reg(0x19) */
+typedef union _MI_ISR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res1:6;             // bits 10-15
+               u16 mdio_sync_lost:1;   // bit 9
+               u16 autoneg_status:1;   // bit 8
+               u16 hi_bit_err:1;               // bit 7
+               u16 np_rx:1;            // bit 6
+               u16 err_counter_full:1; // bit 5
+               u16 fifo_over_underflow:1;      // bit 4
+               u16 rx_status:1;                // bit 3
+               u16 link_status:1;              // bit 2
+               u16 automatic_speed:1;  // bit 1
+               u16 int_en:1;           // bit 0
+#else
+               u16 int_en:1;           // bit 0
+               u16 automatic_speed:1;  // bit 1
+               u16 link_status:1;              // bit 2
+               u16 rx_status:1;                // bit 3
+               u16 fifo_over_underflow:1;      // bit 4
+               u16 err_counter_full:1; // bit 5
+               u16 np_rx:1;            // bit 6
+               u16 hi_bit_err:1;               // bit 7
+               u16 autoneg_status:1;   // bit 8
+               u16 mdio_sync_lost:1;   // bit 9
+               u16 res1:6;             // bits 10-15
+#endif
+       } bits;
+} MI_ISR_t, *PMI_ISR_t;
+
+/* MI Register 26: PHY Status Reg(0x1A) */
+typedef union _MI_PSR_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res1:1;             // bit 15
+               u16 autoneg_fault:2;    // bit 13-14
+               u16 autoneg_status:1;   // bit 12
+               u16 mdi_x_status:1;     // bit 11
+               u16 polarity_status:1;  // bit 10
+               u16 speed_status:2;     // bits 8-9
+               u16 duplex_status:1;    // bit 7
+               u16 link_status:1;              // bit 6
+               u16 tx_status:1;                // bit 5
+               u16 rx_status:1;                // bit 4
+               u16 collision_status:1; // bit 3
+               u16 autoneg_en:1;               // bit 2
+               u16 pause_en:1;         // bit 1
+               u16 asymmetric_dir:1;   // bit 0
+#else
+               u16 asymmetric_dir:1;   // bit 0
+               u16 pause_en:1;         // bit 1
+               u16 autoneg_en:1;               // bit 2
+               u16 collision_status:1; // bit 3
+               u16 rx_status:1;                // bit 4
+               u16 tx_status:1;                // bit 5
+               u16 link_status:1;              // bit 6
+               u16 duplex_status:1;    // bit 7
+               u16 speed_status:2;     // bits 8-9
+               u16 polarity_status:1;  // bit 10
+               u16 mdi_x_status:1;     // bit 11
+               u16 autoneg_status:1;   // bit 12
+               u16 autoneg_fault:2;    // bit 13-14
+               u16 res1:1;             // bit 15
+#endif
+       } bits;
+} MI_PSR_t, *PMI_PSR_t;
+
+/* MI Register 27: LED Control Reg 1(0x1B) */
+typedef union _MI_LCR1_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 res1:2;             // bits 14-15
+               u16 led_dup_indicate:2; // bits 12-13
+               u16 led_10baseT:2;              // bits 10-11
+               u16 led_collision:2;    // bits 8-9
+               u16 res2:2;             // bits 6-7
+               u16 res3:2;             // bits 4-5
+               u16 pulse_dur:2;                // bits 2-3
+               u16 pulse_stretch1:1;   // bit 1
+               u16 pulse_stretch0:1;   // bit 0
+#else
+               u16 pulse_stretch0:1;   // bit 0
+               u16 pulse_stretch1:1;   // bit 1
+               u16 pulse_dur:2;                // bits 2-3
+               u16 res3:2;             // bits 4-5
+               u16 res2:2;             // bits 6-7
+               u16 led_collision:2;    // bits 8-9
+               u16 led_10baseT:2;              // bits 10-11
+               u16 led_dup_indicate:2; // bits 12-13
+               u16 res1:2;             // bits 14-15
+#endif
+       } bits;
+} MI_LCR1_t, *PMI_LCR1_t;
+
+/* MI Register 28: LED Control Reg 2(0x1C) */
+typedef union _MI_LCR2_t {
+       u16 value;
+       struct {
+#ifdef _BIT_FIELDS_HTOL
+               u16 led_link:4;         // bits 12-15
+               u16 led_tx_rx:4;                // bits 8-11
+               u16 led_100BaseTX:4;    // bits 4-7
+               u16 led_1000BaseT:4;    // bits 0-3
+#else
+               u16 led_1000BaseT:4;    // bits 0-3
+               u16 led_100BaseTX:4;    // bits 4-7
+               u16 led_tx_rx:4;                // bits 8-11
+               u16 led_link:4;         // bits 12-15
+#endif
+       } bits;
+} MI_LCR2_t, *PMI_LCR2_t;
+
+/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
+
+/* TruePHY headers */
+typedef struct _TRUEPHY_ACCESS_MI_REGS_ {
+       TRUEPHY_HANDLE hTruePhy;
+       int32_t nPhyId;
+       u8 bReadWrite;
+       u8 *pbyRegs;
+       u8 *pwData;
+       int32_t nRegCount;
+} TRUEPHY_ACCESS_MI_REGS, *PTRUEPHY_ACCESS_MI_REGS;
+
+/* TruePHY headers */
+typedef struct _TAG_TPAL_ACCESS_MI_REGS_ {
+       u32 nPhyId;
+       u8 bReadWrite;
+       u32 nRegCount;
+       u16 Data[4096];
+       u8 Regs[4096];
+} TPAL_ACCESS_MI_REGS, *PTPAL_ACCESS_MI_REGS;
+
+
+typedef TRUEPHY_HANDLE TPAL_HANDLE;
+
+/* Forward declaration of the private adapter structure */
+struct et131x_adapter;
+
+/* OS Specific Functions*/
+void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *adapter);
+void TPAL_SetPhy10FullDuplex(struct et131x_adapter *adapter);
+void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter);
+void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *adapter);
+void TPAL_SetPhy100FullDuplex(struct et131x_adapter *adapter);
+void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter);
+void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *adapter);
+void TPAL_SetPhyAutoNeg(struct et131x_adapter *adapter);
+
+/* Prototypes for ET1310_phy.c */
+int et131x_xcvr_find(struct et131x_adapter *adapter);
+int et131x_setphy_normal(struct et131x_adapter *adapter);
+int32_t PhyMiRead(struct et131x_adapter *adapter,
+              u8 xcvrAddr, u8 xcvrReg, u16 *value);
+
+/* static inline function does not work because et131x_adapter is not always
+ * defined
+ */
+#define MiRead(adapter, xcvrReg, value) \
+       PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value))
+
+int32_t MiWrite(struct et131x_adapter *adapter,
+               u8 xcvReg, u16 value);
+void et131x_Mii_check(struct et131x_adapter *pAdapter,
+                     MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints);
+
+/* This last is not strictly required (the driver could call the TPAL
+ * version instead), but this sets the adapter up correctly, and calls the
+ * access routine indirectly.  This protects the driver from changes in TPAL.
+ */
+void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
+
+/* Defines for PHY access routines */
+
+// Define bit operation flags
+#define TRUEPHY_BIT_CLEAR               0
+#define TRUEPHY_BIT_SET                 1
+#define TRUEPHY_BIT_READ                2
+
+// Define read/write operation flags
+#ifndef TRUEPHY_READ
+#define TRUEPHY_READ                    0
+#define TRUEPHY_WRITE                   1
+#define TRUEPHY_MASK                    2
+#endif
+
+// Define speeds
+#define TRUEPHY_SPEED_10MBPS            0
+#define TRUEPHY_SPEED_100MBPS           1
+#define TRUEPHY_SPEED_1000MBPS          2
+
+// Define duplex modes
+#define TRUEPHY_DUPLEX_HALF             0
+#define TRUEPHY_DUPLEX_FULL             1
+
+// Define master/slave configuration values
+#define TRUEPHY_CFG_SLAVE               0
+#define TRUEPHY_CFG_MASTER              1
+
+// Define MDI/MDI-X settings
+#define TRUEPHY_MDI                     0
+#define TRUEPHY_MDIX                    1
+#define TRUEPHY_AUTO_MDI_MDIX           2
+
+// Define 10Base-T link polarities
+#define TRUEPHY_POLARITY_NORMAL         0
+#define TRUEPHY_POLARITY_INVERTED       1
+
+// Define auto-negotiation results
+#define TRUEPHY_ANEG_NOT_COMPLETE       0
+#define TRUEPHY_ANEG_COMPLETE           1
+#define TRUEPHY_ANEG_DISABLED           2
+
+/* Define duplex advertisment flags */
+#define TRUEPHY_ADV_DUPLEX_NONE         0x00
+#define TRUEPHY_ADV_DUPLEX_FULL         0x01
+#define TRUEPHY_ADV_DUPLEX_HALF         0x02
+#define TRUEPHY_ADV_DUPLEX_BOTH     \
+    (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
+
+#define PHY_CONTROL                0x00        //#define TRU_MI_CONTROL_REGISTER                 0
+#define PHY_STATUS                 0x01        //#define TRU_MI_STATUS_REGISTER                  1
+#define PHY_ID_1                   0x02        //#define TRU_MI_PHY_IDENTIFIER_1_REGISTER        2
+#define PHY_ID_2                   0x03        //#define TRU_MI_PHY_IDENTIFIER_2_REGISTER        3
+#define PHY_AUTO_ADVERTISEMENT     0x04        //#define TRU_MI_ADVERTISEMENT_REGISTER           4
+#define PHY_AUTO_LINK_PARTNER      0x05        //#define TRU_MI_LINK_PARTNER_ABILITY_REGISTER    5
+#define PHY_AUTO_EXPANSION         0x06        //#define TRU_MI_EXPANSION_REGISTER               6
+#define PHY_AUTO_NEXT_PAGE_TX      0x07        //#define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER      7
+#define PHY_LINK_PARTNER_NEXT_PAGE 0x08        //#define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER  8
+#define PHY_1000_CONTROL           0x09        //#define TRU_MI_1000BASET_CONTROL_REGISTER       9
+#define PHY_1000_STATUS            0x0A        //#define TRU_MI_1000BASET_STATUS_REGISTER        10
+
+#define PHY_EXTENDED_STATUS        0x0F        //#define TRU_MI_EXTENDED_STATUS_REGISTER         15
+
+// some defines for modem registers that seem to be 'reserved'
+#define PHY_INDEX_REG              0x10
+#define PHY_DATA_REG               0x11
+
+#define PHY_MPHY_CONTROL_REG       0x12        //#define TRU_VMI_MPHY_CONTROL_REGISTER           18
+
+#define PHY_LOOPBACK_CONTROL       0x13        //#define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER     19
+                                       //#define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER     20
+#define PHY_REGISTER_MGMT_CONTROL  0x15        //#define TRU_VMI_MI_SEQ_CONTROL_REGISTER         21
+#define PHY_CONFIG                 0x16        //#define TRU_VMI_CONFIGURATION_REGISTER          22
+#define PHY_PHY_CONTROL            0x17        //#define TRU_VMI_PHY_CONTROL_REGISTER            23
+#define PHY_INTERRUPT_MASK         0x18        //#define TRU_VMI_INTERRUPT_MASK_REGISTER         24
+#define PHY_INTERRUPT_STATUS       0x19        //#define TRU_VMI_INTERRUPT_STATUS_REGISTER       25
+#define PHY_PHY_STATUS             0x1A        //#define TRU_VMI_PHY_STATUS_REGISTER             26
+#define PHY_LED_1                  0x1B        //#define TRU_VMI_LED_CONTROL_1_REGISTER          27
+#define PHY_LED_2                  0x1C        //#define TRU_VMI_LED_CONTROL_2_REGISTER          28
+                                       //#define TRU_VMI_LINK_CONTROL_REGISTER           29
+                                       //#define TRU_VMI_TIMING_CONTROL_REGISTER
+
+/* Prototypes for PHY access routines */
+void ET1310_PhyInit(struct et131x_adapter *adapter);
+void ET1310_PhyReset(struct et131x_adapter *adapter);
+void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down);
+void ET1310_PhyAutoNeg(struct et131x_adapter *adapter, bool enable);
+void ET1310_PhyDuplexMode(struct et131x_adapter *adapter, u16 duplex);
+void ET1310_PhySpeedSelect(struct et131x_adapter *adapter, u16 speed);
+void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter,
+                                 u16 duplex);
+void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
+                                u16 duplex);
+void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
+                               u16 duplex);
+void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
+                         u8 *ucLinkStatus,
+                         u32 *uiAutoNeg,
+                         u32 *uiLinkSpeed,
+                         u32 *uiDuplexMode,
+                         u32 *uiMdiMdix,
+                         u32 *uiMasterSlave, u32 *uiPolarity);
+void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
+                       u16 regnum, u16 andMask, u16 orMask);
+void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,
+                          u16 action,
+                          u16 regnum, u16 bitnum, u8 *value);
+
+#endif /* _ET1310_PHY_H_ */
diff --git a/src/et131x/et1310_pm.c b/src/et131x/et1310_pm.c
new file mode 100644 (file)
index 0000000..9539bc6
--- /dev/null
@@ -0,0 +1,207 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_pm.c - All power management related code (not completely implemented)
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_debug.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et1310_pm.h"
+#include "et1310_jagcore.h"
+#include "et1310_mac.h"
+#include "et1310_rx.h"
+
+#include "et131x_adapter.h"
+#include "et131x_initpci.h"
+
+/* Data for debugging facilities */
+#ifdef CONFIG_ET131X_DEBUG
+extern dbg_info_t *et131x_dbginfo;
+#endif /* CONFIG_ET131X_DEBUG */
+
+/**
+ * EnablePhyComa - called when network cable is unplugged
+ * @pAdapter: pointer to our adapter structure
+ *
+ * driver receive an phy status change interrupt while in D0 and check that
+ * phy_status is down.
+ *
+ *          -- gate off JAGCore;
+ *          -- set gigE PHY in Coma mode
+ *          -- wake on phy_interrupt; Perform software reset JAGCore,
+ *             re-initialize jagcore and gigE PHY
+ *
+ *      Add D0-ASPM-PhyLinkDown Support:
+ *          -- while in D0, when there is a phy_interrupt indicating phy link
+ *             down status, call the MPSetPhyComa routine to enter this active
+ *             state power saving mode
+ *          -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
+ *       indicating linkup status, call the MPDisablePhyComa routine to
+ *             restore JAGCore and gigE PHY
+ */
+void EnablePhyComa(struct et131x_adapter *pAdapter)
+{
+       unsigned long lockflags;
+       PM_CSR_t GlobalPmCSR;
+       int32_t LoopCounter = 10;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
+
+       /* Save the GbE PHY speed and duplex modes. Need to restore this
+        * when cable is plugged back in
+        */
+       pAdapter->PoMgmt.PowerDownSpeed = pAdapter->AiForceSpeed;
+       pAdapter->PoMgmt.PowerDownDuplex = pAdapter->AiForceDpx;
+
+       /* Stop sending packets. */
+       spin_lock_irqsave(&pAdapter->SendHWLock, lockflags);
+       MP_SET_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);
+       spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags);
+
+       /* Wait for outstanding Receive packets */
+       while ((MP_GET_RCV_REF(pAdapter) != 0) && (LoopCounter-- > 0)) {
+               mdelay(2);
+       }
+
+       /* Gate off JAGCore 3 clock domains */
+       GlobalPmCSR.bits.pm_sysclk_gate = 0;
+       GlobalPmCSR.bits.pm_txclk_gate = 0;
+       GlobalPmCSR.bits.pm_rxclk_gate = 0;
+       writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
+
+       /* Program gigE PHY in to Coma mode */
+       GlobalPmCSR.bits.pm_phy_sw_coma = 1;
+       writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * DisablePhyComa - Disable the Phy Coma Mode
+ * @pAdapter: pointer to our adapter structure
+ */
+void DisablePhyComa(struct et131x_adapter *pAdapter)
+{
+       PM_CSR_t GlobalPmCSR;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
+
+       /* Disable phy_sw_coma register and re-enable JAGCore clocks */
+       GlobalPmCSR.bits.pm_sysclk_gate = 1;
+       GlobalPmCSR.bits.pm_txclk_gate = 1;
+       GlobalPmCSR.bits.pm_rxclk_gate = 1;
+       GlobalPmCSR.bits.pm_phy_sw_coma = 0;
+       writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
+
+       /* Restore the GbE PHY speed and duplex modes;
+        * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
+        */
+       pAdapter->AiForceSpeed = pAdapter->PoMgmt.PowerDownSpeed;
+       pAdapter->AiForceDpx = pAdapter->PoMgmt.PowerDownDuplex;
+
+       /* Re-initialize the send structures */
+       et131x_init_send(pAdapter);
+
+       /* Reset the RFD list and re-start RU  */
+       et131x_reset_recv(pAdapter);
+
+       /* Bring the device back to the state it was during init prior to
+         * autonegotiation being complete.  This way, when we get the auto-neg
+         * complete interrupt, we can complete init by calling ConfigMacREGS2.
+         */
+       et131x_soft_reset(pAdapter);
+
+       /* setup et1310 as per the documentation ?? */
+       et131x_adapter_setup(pAdapter);
+
+       /* Allow Tx to restart */
+       MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);
+
+       /* Need to re-enable Rx. */
+       et131x_rx_dma_enable(pAdapter);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
diff --git a/src/et131x/et1310_pm.h b/src/et131x/et1310_pm.h
new file mode 100644 (file)
index 0000000..6802338
--- /dev/null
@@ -0,0 +1,125 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_pm.h - Defines, structs, enums, prototypes, etc. pertaining to power
+ *               management.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef _ET1310_PM_H_
+#define _ET1310_PM_H_
+
+#include "et1310_address_map.h"
+
+#define MAX_WOL_PACKET_SIZE    0x80
+#define MAX_WOL_MASK_SIZE      ( MAX_WOL_PACKET_SIZE / 8 )
+#define NUM_WOL_PATTERNS       0x5
+#define CRC16_POLY             0x1021
+
+/* Definition of NDIS_DEVICE_POWER_STATE */
+typedef enum {
+       NdisDeviceStateUnspecified = 0,
+       NdisDeviceStateD0,
+       NdisDeviceStateD1,
+       NdisDeviceStateD2,
+       NdisDeviceStateD3
+} NDIS_DEVICE_POWER_STATE;
+
+typedef struct _MP_POWER_MGMT {
+       /* variable putting the phy into coma mode when boot up with no cable
+        * plugged in after 5 seconds
+        */
+       u8 TransPhyComaModeOnBoot;
+
+       /* Array holding the five CRC values that the device is currently
+        * using for WOL.  This will be queried when a pattern is to be
+        * removed.
+        */
+       u32 localWolAndCrc0;
+       u16 WOLPatternList[NUM_WOL_PATTERNS];
+       u8 WOLMaskList[NUM_WOL_PATTERNS][MAX_WOL_MASK_SIZE];
+       u32 WOLMaskSize[NUM_WOL_PATTERNS];
+
+       /* IP address */
+       union {
+               u32 u32;
+               u8 u8[4];
+       } IPAddress;
+
+       /* Current Power state of the adapter. */
+       NDIS_DEVICE_POWER_STATE PowerState;
+       bool WOLState;
+       bool WOLEnabled;
+       bool Failed10Half;
+       bool bFailedStateTransition;
+
+       /* Next two used to save power information at power down. This
+        * information will be used during power up to set up parts of Power
+        * Management in JAGCore
+        */
+       u32 tx_en;
+       u32 rx_en;
+       u16 PowerDownSpeed;
+       u8 PowerDownDuplex;
+} MP_POWER_MGMT, *PMP_POWER_MGMT;
+
+/* Forward declaration of the private adapter structure
+ * ( IS THERE A WAY TO DO THIS WITH A TYPEDEF??? )
+ */
+struct et131x_adapter;
+
+u16 CalculateCCITCRC16(u8 *Pattern, u8 *Mask, u32 MaskSize);
+void EnablePhyComa(struct et131x_adapter *adapter);
+void DisablePhyComa(struct et131x_adapter *adapter);
+
+#endif /* _ET1310_PM_H_ */
diff --git a/src/et131x/et1310_rx.c b/src/et131x/et1310_rx.c
new file mode 100644 (file)
index 0000000..ec98da5
--- /dev/null
@@ -0,0 +1,1391 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_rx.c - Routines used to perform data reception
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_debug.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et1310_pm.h"
+#include "et1310_jagcore.h"
+
+#include "et131x_adapter.h"
+#include "et131x_initpci.h"
+
+#include "et1310_rx.h"
+
+/* Data for debugging facilities */
+#ifdef CONFIG_ET131X_DEBUG
+extern dbg_info_t *et131x_dbginfo;
+#endif /* CONFIG_ET131X_DEBUG */
+
+
+void nic_return_rfd(struct et131x_adapter *pAdapter, PMP_RFD pMpRfd);
+
+/**
+ * et131x_rx_dma_memory_alloc
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h)
+ *
+ * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
+ * and the Packet Status Ring.
+ */
+int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
+{
+       uint32_t OuterLoop, InnerLoop;
+       uint32_t bufsize;
+       uint32_t pktStatRingSize, FBRChunkSize;
+       RX_RING_t *rx_ring;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Setup some convenience pointers */
+       rx_ring = (RX_RING_t *) & adapter->RxRing;
+
+       /* Alloc memory for the lookup table */
+#ifdef USE_FBR0
+       rx_ring->Fbr[0] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
+#endif
+
+       rx_ring->Fbr[1] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
+
+       /* The first thing we will do is configure the sizes of the buffer
+        * rings. These will change based on jumbo packet support.  Larger
+        * jumbo packets increases the size of each entry in FBR0, and the
+        * number of entries in FBR0, while at the same time decreasing the
+        * number of entries in FBR1.
+        *
+        * FBR1 holds "large" frames, FBR0 holds "small" frames.  If FBR1
+        * entries are huge in order to accomodate a "jumbo" frame, then it
+        * will have less entries.  Conversely, FBR1 will now be relied upon
+        * to carry more "normal" frames, thus it's entry size also increases
+        * and the number of entries goes up too (since it now carries
+        * "small" + "regular" packets.
+        *
+        * In this scheme, we try to maintain 512 entries between the two
+        * rings. Also, FBR1 remains a constant size - when it's size doubles
+        * the number of entries halves.  FBR0 increases in size, however.
+        */
+
+       if (adapter->RegistryJumboPacket < 2048) {
+#ifdef USE_FBR0
+               rx_ring->Fbr0BufferSize = 256;
+               rx_ring->Fbr0NumEntries = 512;
+#endif
+               rx_ring->Fbr1BufferSize = 2048;
+               rx_ring->Fbr1NumEntries = 512;
+       } else if (adapter->RegistryJumboPacket < 4096) {
+#ifdef USE_FBR0
+               rx_ring->Fbr0BufferSize = 512;
+               rx_ring->Fbr0NumEntries = 1024;
+#endif
+               rx_ring->Fbr1BufferSize = 4096;
+               rx_ring->Fbr1NumEntries = 512;
+       } else {
+#ifdef USE_FBR0
+               rx_ring->Fbr0BufferSize = 1024;
+               rx_ring->Fbr0NumEntries = 768;
+#endif
+               rx_ring->Fbr1BufferSize = 16384;
+               rx_ring->Fbr1NumEntries = 128;
+       }
+
+#ifdef USE_FBR0
+       adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr0NumEntries +
+           adapter->RxRing.Fbr1NumEntries;
+#else
+       adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr1NumEntries;
+#endif
+
+       /* Allocate an area of memory for Free Buffer Ring 1 */
+       bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
+       rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev,
+                                                   bufsize,
+                                                   &rx_ring->pFbr1RingPa);
+       if (!rx_ring->pFbr1RingVa) {
+               DBG_ERROR(et131x_dbginfo,
+                         "Cannot alloc memory for Free Buffer Ring 1\n");
+               DBG_LEAVE(et131x_dbginfo);
+               return -ENOMEM;
+       }
+
+       /* Save physical address
+        *
+        * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+        * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+        * are ever returned, make sure the high part is retrieved here
+        * before storing the adjusted address.
+        */
+       rx_ring->Fbr1Realpa = rx_ring->pFbr1RingPa;
+
+       /* Align Free Buffer Ring 1 on a 4K boundary */
+       et131x_align_allocated_memory(adapter,
+                                     &rx_ring->Fbr1Realpa,
+                                     &rx_ring->Fbr1offset, 0x0FFF);
+
+       rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa +
+                                       rx_ring->Fbr1offset);
+
+#ifdef USE_FBR0
+       /* Allocate an area of memory for Free Buffer Ring 0 */
+       bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
+       rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev,
+                                                   bufsize,
+                                                   &rx_ring->pFbr0RingPa);
+       if (!rx_ring->pFbr0RingVa) {
+               DBG_ERROR(et131x_dbginfo,
+                         "Cannot alloc memory for Free Buffer Ring 0\n");
+               DBG_LEAVE(et131x_dbginfo);
+               return -ENOMEM;
+       }
+
+       /* Save physical address
+        *
+        * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+        * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+        * are ever returned, make sure the high part is retrieved here before
+        * storing the adjusted address.
+        */
+       rx_ring->Fbr0Realpa = rx_ring->pFbr0RingPa;
+
+       /* Align Free Buffer Ring 0 on a 4K boundary */
+       et131x_align_allocated_memory(adapter,
+                                     &rx_ring->Fbr0Realpa,
+                                     &rx_ring->Fbr0offset, 0x0FFF);
+
+       rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa +
+                                       rx_ring->Fbr0offset);
+#endif
+
+       for (OuterLoop = 0; OuterLoop < (rx_ring->Fbr1NumEntries / FBR_CHUNKS);
+            OuterLoop++) {
+               uint64_t Fbr1Offset;
+               uint64_t Fbr1TempPa;
+               uint32_t Fbr1Align;
+
+               /* This code allocates an area of memory big enough for N
+                * free buffers + (buffer_size - 1) so that the buffers can
+                * be aligned on 4k boundaries.  If each buffer were aligned
+                * to a buffer_size boundary, the effect would be to double
+                * the size of FBR0.  By allocating N buffers at once, we
+                * reduce this overhead.
+                */
+               if (rx_ring->Fbr1BufferSize > 4096) {
+                       Fbr1Align = 4096;
+               } else {
+                       Fbr1Align = rx_ring->Fbr1BufferSize;
+               }
+
+               FBRChunkSize =
+                   (FBR_CHUNKS * rx_ring->Fbr1BufferSize) + Fbr1Align - 1;
+               rx_ring->Fbr1MemVa[OuterLoop] =
+                   pci_alloc_consistent(adapter->pdev, FBRChunkSize,
+                                        &rx_ring->Fbr1MemPa[OuterLoop]);
+
+               if (!rx_ring->Fbr1MemVa[OuterLoop]) {
+                       DBG_ERROR(et131x_dbginfo, "Could not alloc memory\n");
+                       DBG_LEAVE(et131x_dbginfo);
+                       return -ENOMEM;
+               }
+
+               /* See NOTE in "Save Physical Address" comment above */
+               Fbr1TempPa = rx_ring->Fbr1MemPa[OuterLoop];
+
+               et131x_align_allocated_memory(adapter,
+                                             &Fbr1TempPa,
+                                             &Fbr1Offset, (Fbr1Align - 1));
+
+               for (InnerLoop = 0; InnerLoop < FBR_CHUNKS; InnerLoop++) {
+                       uint32_t index = (OuterLoop * FBR_CHUNKS) + InnerLoop;
+
+                       /* Save the Virtual address of this index for quick
+                        * access later
+                        */
+                       rx_ring->Fbr[1]->Va[index] =
+                           (uint8_t *) rx_ring->Fbr1MemVa[OuterLoop] +
+                           (InnerLoop * rx_ring->Fbr1BufferSize) + Fbr1Offset;
+
+                       /* now store the physical address in the descriptor
+                        * so the device can access it
+                        */
+                       rx_ring->Fbr[1]->PAHigh[index] =
+                           (uint32_t) (Fbr1TempPa >> 32);
+                       rx_ring->Fbr[1]->PALow[index] = (uint32_t) Fbr1TempPa;
+
+                       Fbr1TempPa += rx_ring->Fbr1BufferSize;
+
+                       rx_ring->Fbr[1]->Buffer1[index] =
+                           rx_ring->Fbr[1]->Va[index];
+                       rx_ring->Fbr[1]->Buffer2[index] =
+                           rx_ring->Fbr[1]->Va[index] - 4;
+               }
+       }
+
+#ifdef USE_FBR0
+       /* Same for FBR0 (if in use) */
+       for (OuterLoop = 0; OuterLoop < (rx_ring->Fbr0NumEntries / FBR_CHUNKS);
+            OuterLoop++) {
+               uint64_t Fbr0Offset;
+               uint64_t Fbr0TempPa;
+
+               FBRChunkSize = ((FBR_CHUNKS + 1) * rx_ring->Fbr0BufferSize) - 1;
+               rx_ring->Fbr0MemVa[OuterLoop] =
+                   pci_alloc_consistent(adapter->pdev, FBRChunkSize,
+                                        &rx_ring->Fbr0MemPa[OuterLoop]);
+
+               if (!rx_ring->Fbr0MemVa[OuterLoop]) {
+                       DBG_ERROR(et131x_dbginfo, "Could not alloc memory\n");
+                       DBG_LEAVE(et131x_dbginfo);
+                       return -ENOMEM;
+               }
+
+               /* See NOTE in "Save Physical Address" comment above */
+               Fbr0TempPa = rx_ring->Fbr0MemPa[OuterLoop];
+
+               et131x_align_allocated_memory(adapter,
+                                             &Fbr0TempPa,
+                                             &Fbr0Offset,
+                                             rx_ring->Fbr0BufferSize - 1);
+
+               for (InnerLoop = 0; InnerLoop < FBR_CHUNKS; InnerLoop++) {
+                       uint32_t index = (OuterLoop * FBR_CHUNKS) + InnerLoop;
+
+                       rx_ring->Fbr[0]->Va[index] =
+                           (uint8_t *) rx_ring->Fbr0MemVa[OuterLoop] +
+                           (InnerLoop * rx_ring->Fbr0BufferSize) + Fbr0Offset;
+
+                       rx_ring->Fbr[0]->PAHigh[index] =
+                           (uint32_t) (Fbr0TempPa >> 32);
+                       rx_ring->Fbr[0]->PALow[index] = (uint32_t) Fbr0TempPa;
+
+                       Fbr0TempPa += rx_ring->Fbr0BufferSize;
+
+                       rx_ring->Fbr[0]->Buffer1[index] =
+                           rx_ring->Fbr[0]->Va[index];
+                       rx_ring->Fbr[0]->Buffer2[index] =
+                           rx_ring->Fbr[0]->Va[index] - 4;
+               }
+       }
+#endif
+
+       /* Allocate an area of memory for FIFO of Packet Status ring entries */
+       pktStatRingSize =
+           sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
+
+       rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev,
+                                                 pktStatRingSize + 0x0fff,
+                                                 &rx_ring->pPSRingPa);
+
+       if (!rx_ring->pPSRingVa) {
+               DBG_ERROR(et131x_dbginfo,
+                         "Cannot alloc memory for Packet Status Ring\n");
+               DBG_LEAVE(et131x_dbginfo);
+               return -ENOMEM;
+       }
+
+       /* Save physical address
+        *
+        * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
+        * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+        * are ever returned, make sure the high part is retrieved here before
+        * storing the adjusted address.
+        */
+       rx_ring->pPSRingRealPa = rx_ring->pPSRingPa;
+
+       /* Align Packet Status Ring on a 4K boundary */
+       et131x_align_allocated_memory(adapter,
+                                     &rx_ring->pPSRingRealPa,
+                                     &rx_ring->pPSRingOffset, 0x0FFF);
+
+       rx_ring->pPSRingVa = (void *)((uint8_t *) rx_ring->pPSRingVa +
+                                     rx_ring->pPSRingOffset);
+
+       /* Allocate an area of memory for writeback of status information */
+       rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev,
+                                                   sizeof(RX_STATUS_BLOCK_t) +
+                                                   0x7, &rx_ring->pRxStatusPa);
+       if (!rx_ring->pRxStatusVa) {
+               DBG_ERROR(et131x_dbginfo,
+                         "Cannot alloc memory for Status Block\n");
+               DBG_LEAVE(et131x_dbginfo);
+               return -ENOMEM;
+       }
+
+       /* Save physical address */
+       rx_ring->RxStatusRealPA = rx_ring->pRxStatusPa;
+
+       /* Align write back on an 8 byte boundary */
+       et131x_align_allocated_memory(adapter,
+                                     &rx_ring->RxStatusRealPA,
+                                     &rx_ring->RxStatusOffset, 0x07);
+
+       rx_ring->pRxStatusVa = (void *)((uint8_t *) rx_ring->pRxStatusVa +
+                                       rx_ring->RxStatusOffset);
+       rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD;
+
+       /* Recv
+        * pci_pool_create initializes a lookaside list. After successful
+        * creation, nonpaged fixed-size blocks can be allocated from and
+        * freed to the lookaside list.
+        * RFDs will be allocated from this pool.
+        */
+       rx_ring->RecvLookaside = kmem_cache_create(adapter->netdev->name,
+                                                  sizeof(MP_RFD),
+                                                  0,
+                                                  SLAB_CACHE_DMA |
+                                                  SLAB_HWCACHE_ALIGN,
+                                                  NULL);
+
+       MP_SET_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE);
+
+       /* The RFDs are going to be put on lists later on, so initialize the
+        * lists now.
+        */
+       INIT_LIST_HEAD(&rx_ring->RecvList);
+       INIT_LIST_HEAD(&rx_ring->RecvPendingList);
+
+       DBG_LEAVE(et131x_dbginfo);
+       return 0;
+}
+
+/**
+ * et131x_rx_dma_memory_free - Free all memory allocated within this module.
+ * @adapter: pointer to our private adapter structure
+ */
+void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
+{
+       uint32_t index;
+       uint32_t bufsize;
+       uint32_t pktStatRingSize;
+       PMP_RFD pMpRfd;
+       RX_RING_t *rx_ring;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Setup some convenience pointers */
+       rx_ring = (RX_RING_t *) & adapter->RxRing;
+
+       /* Free RFDs and associated packet descriptors */
+       DBG_ASSERT(rx_ring->nReadyRecv == rx_ring->NumRfd);
+
+       while (!list_empty(&rx_ring->RecvList)) {
+               pMpRfd = (MP_RFD *) list_entry(rx_ring->RecvList.next,
+                                              MP_RFD, list_node);
+
+               list_del(&pMpRfd->list_node);
+               et131x_rfd_resources_free(adapter, pMpRfd);
+       }
+
+       while (!list_empty(&rx_ring->RecvPendingList)) {
+               pMpRfd = (MP_RFD *) list_entry(rx_ring->RecvPendingList.next,
+                                              MP_RFD, list_node);
+               list_del(&pMpRfd->list_node);
+               et131x_rfd_resources_free(adapter, pMpRfd);
+       }
+
+       /* Free Free Buffer Ring 1 */
+       if (rx_ring->pFbr1RingVa) {
+               /* First the packet memory */
+               for (index = 0; index <
+                    (rx_ring->Fbr1NumEntries / FBR_CHUNKS); index++) {
+                       if (rx_ring->Fbr1MemVa[index]) {
+                               uint32_t Fbr1Align;
+
+                               if (rx_ring->Fbr1BufferSize > 4096) {
+                                       Fbr1Align = 4096;
+                               } else {
+                                       Fbr1Align = rx_ring->Fbr1BufferSize;
+                               }
+
+                               bufsize =
+                                   (rx_ring->Fbr1BufferSize * FBR_CHUNKS) +
+                                   Fbr1Align - 1;
+
+                               pci_free_consistent(adapter->pdev,
+                                                   bufsize,
+                                                   rx_ring->Fbr1MemVa[index],
+                                                   rx_ring->Fbr1MemPa[index]);
+
+                               rx_ring->Fbr1MemVa[index] = NULL;
+                       }
+               }
+
+               /* Now the FIFO itself */
+               rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa -
+                                               rx_ring->Fbr1offset);
+
+               bufsize =
+                   (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
+
+               pci_free_consistent(adapter->pdev,
+                                   bufsize,
+                                   rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa);
+
+               rx_ring->pFbr1RingVa = NULL;
+       }
+
+#ifdef USE_FBR0
+       /* Now the same for Free Buffer Ring 0 */
+       if (rx_ring->pFbr0RingVa) {
+               /* First the packet memory */
+               for (index = 0; index <
+                    (rx_ring->Fbr0NumEntries / FBR_CHUNKS); index++) {
+                       if (rx_ring->Fbr0MemVa[index]) {
+                               bufsize =
+                                   (rx_ring->Fbr0BufferSize *
+                                    (FBR_CHUNKS + 1)) - 1;
+
+                               pci_free_consistent(adapter->pdev,
+                                                   bufsize,
+                                                   rx_ring->Fbr0MemVa[index],
+                                                   rx_ring->Fbr0MemPa[index]);
+
+                               rx_ring->Fbr0MemVa[index] = NULL;
+                       }
+               }
+
+               /* Now the FIFO itself */
+               rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa -
+                                               rx_ring->Fbr0offset);
+
+               bufsize =
+                   (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
+
+               pci_free_consistent(adapter->pdev,
+                                   bufsize,
+                                   rx_ring->pFbr0RingVa, rx_ring->pFbr0RingPa);
+
+               rx_ring->pFbr0RingVa = NULL;
+       }
+#endif
+
+       /* Free Packet Status Ring */
+       if (rx_ring->pPSRingVa) {
+               rx_ring->pPSRingVa = (void *)((uint8_t *) rx_ring->pPSRingVa -
+                                             rx_ring->pPSRingOffset);
+
+               pktStatRingSize =
+                   sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
+
+               pci_free_consistent(adapter->pdev,
+                                   pktStatRingSize + 0x0fff,
+                                   rx_ring->pPSRingVa, rx_ring->pPSRingPa);
+
+               rx_ring->pPSRingVa = NULL;
+       }
+
+       /* Free area of memory for the writeback of status information */
+       if (rx_ring->pRxStatusVa) {
+               rx_ring->pRxStatusVa = (void *)((uint8_t *) rx_ring->pRxStatusVa -
+                                               rx_ring->RxStatusOffset);
+
+               pci_free_consistent(adapter->pdev,
+                                   sizeof(RX_STATUS_BLOCK_t) + 0x7,
+                                   rx_ring->pRxStatusVa, rx_ring->pRxStatusPa);
+
+               rx_ring->pRxStatusVa = NULL;
+       }
+
+       /* Free receive buffer pool */
+
+       /* Free receive packet pool */
+
+       /* Destroy the lookaside (RFD) pool */
+       if (MP_TEST_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE)) {
+               kmem_cache_destroy(rx_ring->RecvLookaside);
+               MP_CLEAR_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE);
+       }
+
+       /* Free the FBR Lookup Table */
+#ifdef USE_FBR0
+       kfree(rx_ring->Fbr[0]);
+#endif
+
+       kfree(rx_ring->Fbr[1]);
+
+       /* Reset Counters */
+       rx_ring->nReadyRecv = 0;
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * et131x_init_recv - Initialize receive data structures.
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h)
+ */
+int et131x_init_recv(struct et131x_adapter *adapter)
+{
+       int status = -ENOMEM;
+       PMP_RFD pMpRfd = NULL;
+       uint32_t RfdCount;
+       uint32_t TotalNumRfd = 0;
+       RX_RING_t *rx_ring = NULL;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Setup some convenience pointers */
+       rx_ring = (RX_RING_t *) & adapter->RxRing;
+
+       /* Setup each RFD */
+       for (RfdCount = 0; RfdCount < rx_ring->NumRfd; RfdCount++) {
+               pMpRfd = (MP_RFD *) kmem_cache_alloc(rx_ring->RecvLookaside,
+                                                    GFP_ATOMIC | GFP_DMA);
+
+               if (!pMpRfd) {
+                       DBG_ERROR(et131x_dbginfo,
+                                 "Couldn't alloc RFD out of kmem_cache\n");
+                       status = -ENOMEM;
+                       continue;
+               }
+
+               status = et131x_rfd_resources_alloc(adapter, pMpRfd);
+               if (status != 0) {
+                       DBG_ERROR(et131x_dbginfo,
+                                 "Couldn't alloc packet for RFD\n");
+                       kmem_cache_free(rx_ring->RecvLookaside, pMpRfd);
+                       continue;
+               }
+
+               /* Add this RFD to the RecvList */
+               list_add_tail(&pMpRfd->list_node, &rx_ring->RecvList);
+
+               /* Increment both the available RFD's, and the total RFD's. */
+               rx_ring->nReadyRecv++;
+               TotalNumRfd++;
+       }
+
+       if (TotalNumRfd > NIC_MIN_NUM_RFD) {
+               status = 0;
+       }
+
+       rx_ring->NumRfd = TotalNumRfd;
+
+       if (status != 0) {
+               kmem_cache_free(rx_ring->RecvLookaside, pMpRfd);
+               DBG_ERROR(et131x_dbginfo,
+                         "Allocation problems in et131x_init_recv\n");
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+       return status;
+}
+
+/**
+ * et131x_rfd_resources_alloc
+ * @adapter: pointer to our private adapter structure
+ * @pMpRfd: pointer to a RFD
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h)
+ */
+int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
+{
+       pMpRfd->Packet = NULL;
+
+       return 0;
+}
+
+/**
+ * et131x_rfd_resources_free - Free the packet allocated for the given RFD
+ * @adapter: pointer to our private adapter structure
+ * @pMpRfd: pointer to a RFD
+ */
+void et131x_rfd_resources_free(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
+{
+       pMpRfd->Packet = NULL;
+       kmem_cache_free(adapter->RxRing.RecvLookaside, pMpRfd);
+}
+
+/**
+ * ConfigRxDmaRegs - Start of Rx_DMA init sequence
+ * @pAdapter: pointer to our adapter structure
+ */
+void ConfigRxDmaRegs(struct et131x_adapter *pAdapter)
+{
+       struct _RXDMA_t __iomem *pRxDma = &pAdapter->CSRAddress->rxdma;
+       struct _rx_ring_t *pRxLocal = &pAdapter->RxRing;
+       PFBR_DESC_t pFbrEntry;
+       uint32_t iEntry;
+       RXDMA_PSR_NUM_DES_t psr_num_des;
+       unsigned long lockflags;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Halt RXDMA to perform the reconfigure.  */
+       et131x_rx_dma_disable(pAdapter);
+
+       /* Load the completion writeback physical address
+        *
+        * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
+        * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+        * are ever returned, make sure the high part is retrieved here
+        * before storing the adjusted address.
+        */
+       writel((uint32_t) (pRxLocal->RxStatusRealPA >> 32),
+              &pRxDma->dma_wb_base_hi);
+       writel((uint32_t) pRxLocal->RxStatusRealPA, &pRxDma->dma_wb_base_lo);
+
+       memset(pRxLocal->pRxStatusVa, 0, sizeof(RX_STATUS_BLOCK_t));
+
+       /* Set the address and parameters of the packet status ring into the
+        * 1310's registers
+        */
+       writel((uint32_t) (pRxLocal->pPSRingRealPa >> 32),
+              &pRxDma->psr_base_hi);
+       writel((uint32_t) pRxLocal->pPSRingRealPa, &pRxDma->psr_base_lo);
+       writel(pRxLocal->PsrNumEntries - 1, &pRxDma->psr_num_des.value);
+       writel(0, &pRxDma->psr_full_offset.value);
+
+       psr_num_des.value = readl(&pRxDma->psr_num_des.value);
+       writel((psr_num_des.bits.psr_ndes * LO_MARK_PERCENT_FOR_PSR) / 100,
+              &pRxDma->psr_min_des.value);
+
+       spin_lock_irqsave(&pAdapter->RcvLock, lockflags);
+
+       /* These local variables track the PSR in the adapter structure */
+       pRxLocal->local_psr_full.bits.psr_full = 0;
+       pRxLocal->local_psr_full.bits.psr_full_wrap = 0;
+
+       /* Now's the best time to initialize FBR1 contents */
+       pFbrEntry = (PFBR_DESC_t) pRxLocal->pFbr1RingVa;
+       for (iEntry = 0; iEntry < pRxLocal->Fbr1NumEntries; iEntry++) {
+               pFbrEntry->addr_hi = pRxLocal->Fbr[1]->PAHigh[iEntry];
+               pFbrEntry->addr_lo = pRxLocal->Fbr[1]->PALow[iEntry];
+               pFbrEntry->word2.bits.bi = iEntry;
+               pFbrEntry++;
+       }
+
+       /* Set the address and parameters of Free buffer ring 1 (and 0 if
+        * required) into the 1310's registers
+        */
+       writel((uint32_t) (pRxLocal->Fbr1Realpa >> 32), &pRxDma->fbr1_base_hi);
+       writel((uint32_t) pRxLocal->Fbr1Realpa, &pRxDma->fbr1_base_lo);
+       writel(pRxLocal->Fbr1NumEntries - 1, &pRxDma->fbr1_num_des.value);
+
+       {
+               DMA10W_t fbr1_full = { 0 };
+
+               fbr1_full.bits.val = 0;
+               fbr1_full.bits.wrap = 1;
+               writel(fbr1_full.value, &pRxDma->fbr1_full_offset.value);
+       }
+
+       /* This variable tracks the free buffer ring 1 full position, so it
+        * has to match the above.
+        */
+       pRxLocal->local_Fbr1_full.bits.val = 0;
+       pRxLocal->local_Fbr1_full.bits.wrap = 1;
+       writel(((pRxLocal->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+              &pRxDma->fbr1_min_des.value);
+
+#ifdef USE_FBR0
+       /* Now's the best time to initialize FBR0 contents */
+       pFbrEntry = (PFBR_DESC_t) pRxLocal->pFbr0RingVa;
+       for (iEntry = 0; iEntry < pRxLocal->Fbr0NumEntries; iEntry++) {
+               pFbrEntry->addr_hi = pRxLocal->Fbr[0]->PAHigh[iEntry];
+               pFbrEntry->addr_lo = pRxLocal->Fbr[0]->PALow[iEntry];
+               pFbrEntry->word2.bits.bi = iEntry;
+               pFbrEntry++;
+       }
+
+       writel((uint32_t) (pRxLocal->Fbr0Realpa >> 32), &pRxDma->fbr0_base_hi);
+       writel((uint32_t) pRxLocal->Fbr0Realpa, &pRxDma->fbr0_base_lo);
+       writel(pRxLocal->Fbr0NumEntries - 1, &pRxDma->fbr0_num_des.value);
+
+       {
+               DMA10W_t fbr0_full = { 0 };
+
+               fbr0_full.bits.val = 0;
+               fbr0_full.bits.wrap = 1;
+               writel(fbr0_full.value, &pRxDma->fbr0_full_offset.value);
+       }
+
+       /* This variable tracks the free buffer ring 0 full position, so it
+        * has to match the above.
+        */
+       pRxLocal->local_Fbr0_full.bits.val = 0;
+       pRxLocal->local_Fbr0_full.bits.wrap = 1;
+       writel(((pRxLocal->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+              &pRxDma->fbr0_min_des.value);
+#endif
+
+       /* Program the number of packets we will receive before generating an
+        * interrupt.
+        * For version B silicon, this value gets updated once autoneg is
+        *complete.
+        */
+       writel(pAdapter->RegistryRxNumBuffers, &pRxDma->num_pkt_done.value);
+
+       /* The "time_done" is not working correctly to coalesce interrupts
+        * after a given time period, but rather is giving us an interrupt
+        * regardless of whether we have received packets.
+        * This value gets updated once autoneg is complete.
+        */
+       writel(pAdapter->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
+
+       spin_unlock_irqrestore(&pAdapter->RcvLock, lockflags);
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * SetRxDmaTimer - Set the heartbeat timer according to line rate.
+ * @pAdapter: pointer to our adapter structure
+ */
+void SetRxDmaTimer(struct et131x_adapter *pAdapter)
+{
+       /* For version B silicon, we do not use the RxDMA timer for 10 and 100
+        * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
+        */
+       if ((pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) ||
+           (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS)) {
+               writel(0, &pAdapter->CSRAddress->rxdma.max_pkt_time.value);
+               writel(1, &pAdapter->CSRAddress->rxdma.num_pkt_done.value);
+       }
+}
+
+/**
+ * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
+ * @pAdapter: pointer to our adapter structure
+ */
+void et131x_rx_dma_disable(struct et131x_adapter *pAdapter)
+{
+       RXDMA_CSR_t csr;
+
+       DBG_ENTER(et131x_dbginfo);
+
+       /* Setup the receive dma configuration register */
+       writel(0x00002001, &pAdapter->CSRAddress->rxdma.csr.value);
+       csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
+       if (csr.bits.halt_status != 1) {
+               udelay(5);
+               csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
+               if (csr.bits.halt_status != 1) {
+                       DBG_ERROR(et131x_dbginfo,
+                                 "RX Dma failed to enter halt state. CSR 0x%08x\n",
+                                 csr.value);
+               }
+       }
+
+       DBG_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
+ * @pAdapter: pointer to our adapter structure
+ */
+void et131x_rx_dma_enable(struct et131x_adapter *pAdapter)
+{
+       DBG_RX_ENTER(et131x_dbginfo);
+
+       if (pAdapter->RegistryPhyLoopbk) {
+       /* RxDMA is disabled for loopback operation. */
+               writel(0x1, &pAdapter->CSRAddress->rxdma.csr.value);
+       } else {
+       /* Setup the receive dma configuration register for normal operation */
+               RXDMA_CSR_t csr = { 0 };
+
+               csr.bits.fbr1_enable = 1;
+               if (pAdapter->RxRing.Fbr1BufferSize == 4096) {
+                       csr.bits.fbr1_size = 1;
+               } else if (pAdapter->RxRing.Fbr1BufferSize == 8192) {
+                       csr.bits.fbr1_size = 2;
+               } else if (pAdapter->RxRing.Fbr1BufferSize == 16384) {
+                       csr.bits.fbr1_size = 3;
+               }
+#ifdef USE_FBR0
+               csr.bits.fbr0_enable = 1;
+               if (pAdapter->RxRing.Fbr0BufferSize == 256) {
+                       csr.bits.fbr0_size = 1;
+               } else if (pAdapter->RxRing.Fbr0BufferSize == 512) {
+                       csr.bits.fbr0_size = 2;
+               } else if (pAdapter->RxRing.Fbr0BufferSize == 1024) {
+                       csr.bits.fbr0_size = 3;
+               }
+#endif
+               writel(csr.value, &pAdapter->CSRAddress->rxdma.csr.value);
+
+               csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
+               if (csr.bits.halt_status != 0) {
+                       udelay(5);
+                       csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
+                       if (csr.bits.halt_status != 0) {
+                               DBG_ERROR(et131x_dbginfo,
+                                         "RX Dma failed to exit halt state.  CSR 0x%08x\n",
+                                         csr.value);
+                       }
+               }
+       }
+
+       DBG_RX_LEAVE(et131x_dbginfo);
+}
+
+/**
+ * nic_rx_pkts - Checks the hardware for available packets
+ * @pAdapter: pointer to our adapter
+ *
+ * Returns pMpRfd, a pointer to our MPRFD.
+ *
+ * Checks the hardware for available packets, using completion ring
+ * If packets are available, it gets an RFD from the RecvList, attaches
+ * the packet to it, puts the RFD in the RecvPendList, and also returns
+ * the pointer to the RFD.
+ */
+PMP_RFD nic_rx_pkts(struct et131x_adapter *pAdapter)
+{
+       struct _rx_ring_t *pRxLocal = &pAdapter->RxRing;
+       PRX_STATUS_BLOCK_t pRxStatusBlock;
+       PPKT_STAT_DESC_t pPSREntry;
+       PMP_RFD pMpRfd;
+       uint32_t nIndex;
+       uint8_t *pBufVa;
+       unsigned long lockflags;
+       struct list_head *element;
+       uint8_t ringIndex;
+       uint16_t bufferIndex;
+       uint32_t localLen;
+       PKT_STAT_DESC_WORD0_t Word0;
+
+
+       DBG_RX_ENTER(et131x_dbginfo);
+
+       /* RX Status block is written by the DMA engine prior to every
+        * interrupt. It contains the next to be used entry in the Packet
+        * Status Ring, and also the two Free Buffer rings.
+        */
+       pRxStatusBlock = (PRX_STATUS_BLOCK_t) pRxLocal->pRxStatusVa;
+
+       if (pRxStatusBlock->Word1.bits.PSRoffset ==
+                       pRxLocal->local_psr_full.bits.psr_full &&
+           pRxStatusBlock->Word1.bits.PSRwrap ==
+                       pRxLocal->local_psr_full.bits.psr_full_wrap) {
+               /* Looks like this ring is not updated yet */
+               DBG_RX(et131x_dbginfo, "(0)\n");
+               DBG_RX_LEAVE(et131x_dbginfo);
+               return NULL;
+       }
+
+       /* The packet status ring indicates that data is available. */
+       pPSREntry = (PPKT_STAT_DESC_t) (pRxLocal->pPSRingVa) +
+                       pRxLocal->local_psr_full.bits.psr_full;
+
+       /* Grab any information that is required once the PSR is
+        * advanced, since we can no longer rely on the memory being
+        * accurate
+        */
+       localLen = pPSREntry->word1.bits.length;
+       ringIndex = (uint8_t) pPSREntry->word1.bits.ri;
+       bufferIndex = (uint16_t) pPSREntry->word1.bits.bi;
+       Word0 = pPSREntry->word0;
+
+       DBG_RX(et131x_dbginfo, "RX PACKET STATUS\n");
+       DBG_RX(et131x_dbginfo, "\tlength      : %d\n", localLen);
+       DBG_RX(et131x_dbginfo, "\tringIndex   : %d\n", ringIndex);
+       DBG_RX(et131x_dbginfo, "\tbufferIndex : %d\n", bufferIndex);
+       DBG_RX(et131x_dbginfo, "\tword0       : 0x%08x\n", Word0.value);
+
+#if 0
+       /* Check the Status Word that the MAC has appended to the PSR
+        * entry in case the MAC has detected errors.
+        */
+       if (Word0.value & ALCATEL_BAD_STATUS) {
+               DBG_ERROR(et131x_dbginfo,
+                         "NICRxPkts >> Alcatel Status Word error."
+                         "Value 0x%08x\n", pPSREntry->word0.value);
+       }
+#endif
+
+       /* Indicate that we have used this PSR entry. */
+       if (++pRxLocal->local_psr_full.bits.psr_full >
+           pRxLocal->PsrNumEntries - 1) {
+               pRxLocal->local_psr_full.bits.psr_full = 0;
+               pRxLocal->local_psr_full.bits.psr_full_wrap ^= 1;
+       }
+
+       writel(pRxLocal->local_psr_full.value,
+              &pAdapter->CSRAddress->rxdma.psr_full_offset.value);
+
+#ifndef USE_FBR0
+       if (ringIndex != 1) {
+               DBG_ERROR(et131x_dbginfo,
+                         "NICRxPkts PSR Entry %d indicates "
+                         "Buffer Ring 0 in use\n",
+                         pRxLocal->local_psr_full.bits.psr_full);
+               DBG_RX_LEAVE(et131x_dbginfo);
+               return NULL;
+       }
+#endif
+
+#ifdef USE_FBR0
+       if (ringIndex > 1 ||
+           (ringIndex == 0 &&
+            bufferIndex > pRxLocal->Fbr0NumEntries - 1) ||
+           (ringIndex == 1 &&
+            bufferIndex > pRxLocal->Fbr1NumEntries - 1))
+#else
+       if (ringIndex != 1 ||
+           bufferIndex > pRxLocal->Fbr1NumEntries - 1)
+#endif
+       {
+               /* Illegal buffer or ring index cannot be used by S/W*/
+               DBG_ERROR(et131x_dbginfo,
+                         "NICRxPkts PSR Entry %d indicates "
+                         "length of %d and/or bad bi(%d)\n",
+                         pRxLocal->local_psr_full.bits.psr_full,
+                         localLen, bufferIndex);
+               DBG_RX_LEAVE(et131x_dbginfo);
+               return NULL;
+       }
+
+       /* Get and fill the RFD. */
+       spin_lock_irqsave(&pAdapter->RcvLock, lockflags);
+
+       pMpRfd = NULL;
+       element = pRxLocal->RecvList.next;
+       pMpRfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
+
+       if (pMpRfd == NULL) {
+               DBG_RX(et131x_dbginfo,
+                      "NULL RFD returned from RecvList via list_entry()\n");
+               DBG_RX_LEAVE(et131x_dbginfo);
+               spin_unlock_irqrestore(&pAdapter->RcvLock, lockflags);
+               return NULL;
+       }
+