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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
213516ef | 2 | Copyright (C) 1999-2023 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
4de283e4 TT |
20 | #include "inferior.h" |
21 | #include "gdbcore.h" | |
22 | #include "regcache.h" | |
23 | #include "target.h" | |
24 | #include "linux-nat.h" | |
25 | #include "target-descriptions.h" | |
26 | #include "auxv.h" | |
27 | #include "observable.h" | |
28 | #include "gdbthread.h" | |
29 | ||
d105cce5 | 30 | #include "aarch32-tdep.h" |
4de283e4 TT |
31 | #include "arm-tdep.h" |
32 | #include "arm-linux-tdep.h" | |
33 | #include "aarch32-linux-nat.h" | |
aeb98c60 | 34 | |
3b273a55 | 35 | #include <elf/common.h> |
ed9a39eb | 36 | #include <sys/user.h> |
4de283e4 | 37 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 38 | #include <sys/utsname.h> |
4de283e4 | 39 | #include <sys/procfs.h> |
ed9a39eb | 40 | |
d55e5aa6 | 41 | #include "nat/linux-ptrace.h" |
4de283e4 | 42 | #include "linux-tdep.h" |
95855ca8 | 43 | |
0963b4bd | 44 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
45 | #include "gregset.h" |
46 | ||
9308fc88 DJ |
47 | /* Defines ps_err_e, struct ps_prochandle. */ |
48 | #include "gdb_proc_service.h" | |
49 | ||
50 | #ifndef PTRACE_GET_THREAD_AREA | |
51 | #define PTRACE_GET_THREAD_AREA 22 | |
52 | #endif | |
53 | ||
05a4558a DJ |
54 | #ifndef PTRACE_GETWMMXREGS |
55 | #define PTRACE_GETWMMXREGS 18 | |
56 | #define PTRACE_SETWMMXREGS 19 | |
57 | #endif | |
58 | ||
3b273a55 RE |
59 | #ifndef PTRACE_GETVFPREGS |
60 | #define PTRACE_GETVFPREGS 27 | |
61 | #define PTRACE_SETVFPREGS 28 | |
62 | #endif | |
63 | ||
e3039479 UW |
64 | #ifndef PTRACE_GETHBPREGS |
65 | #define PTRACE_GETHBPREGS 29 | |
66 | #define PTRACE_SETHBPREGS 30 | |
67 | #endif | |
68 | ||
f6ac5f3d PA |
69 | class arm_linux_nat_target final : public linux_nat_target |
70 | { | |
71 | public: | |
72 | /* Add our register access methods. */ | |
73 | void fetch_registers (struct regcache *, int) override; | |
74 | void store_registers (struct regcache *, int) override; | |
75 | ||
76 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
77 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
78 | ||
79 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
80 | ||
81 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
82 | ||
83 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
84 | ||
85 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
86 | struct expression *) override; | |
87 | ||
88 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
89 | struct expression *) override; | |
57810aa7 | 90 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 91 | |
57810aa7 | 92 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 93 | |
57810aa7 | 94 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d PA |
95 | |
96 | const struct target_desc *read_description () override; | |
135340af PA |
97 | |
98 | /* Override linux_nat_target low methods. */ | |
99 | ||
100 | /* Handle thread creation and exit. */ | |
101 | void low_new_thread (struct lwp_info *lp) override; | |
102 | void low_delete_thread (struct arch_lwp_info *lp) override; | |
103 | void low_prepare_to_resume (struct lwp_info *lp) override; | |
104 | ||
105 | /* Handle process creation and exit. */ | |
106 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
107 | void low_forget_process (pid_t pid) override; | |
f6ac5f3d PA |
108 | }; |
109 | ||
110 | static arm_linux_nat_target the_arm_linux_nat_target; | |
111 | ||
41c49b06 | 112 | /* Get the whole floating point state of the process and store it |
c6b92abd | 113 | into regcache. */ |
ed9a39eb JM |
114 | |
115 | static void | |
56be3814 | 116 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 117 | { |
41c49b06 | 118 | int ret, regno, tid; |
cb587d83 | 119 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 120 | |
41c49b06 | 121 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 122 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 123 | |
ed9a39eb | 124 | /* Read the floating point state. */ |
0bdb2f78 | 125 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
126 | { |
127 | struct iovec iov; | |
128 | ||
129 | iov.iov_base = &fp; | |
130 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
131 | ||
132 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
133 | } | |
134 | else | |
135 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
136 | ||
ed9a39eb | 137 | if (ret < 0) |
deb70aa0 | 138 | perror_with_name (_("Unable to fetch the floating point registers")); |
ed9a39eb JM |
139 | |
140 | /* Fetch fpsr. */ | |
73e1c03f | 141 | regcache->raw_supply (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
142 | |
143 | /* Fetch the floating point registers. */ | |
34e8f22d | 144 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 145 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
146 | } |
147 | ||
148 | /* Save the whole floating point state of the process using | |
c6b92abd | 149 | the contents from regcache. */ |
ed9a39eb JM |
150 | |
151 | static void | |
56be3814 | 152 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 153 | { |
41c49b06 | 154 | int ret, regno, tid; |
cb587d83 | 155 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 156 | |
41c49b06 | 157 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 158 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 159 | |
41c49b06 | 160 | /* Read the floating point state. */ |
0bdb2f78 | 161 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
162 | { |
163 | elf_fpregset_t fpregs; | |
164 | struct iovec iov; | |
165 | ||
166 | iov.iov_base = &fpregs; | |
167 | iov.iov_len = sizeof (fpregs); | |
168 | ||
169 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
170 | } | |
171 | else | |
172 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
173 | ||
41c49b06 | 174 | if (ret < 0) |
deb70aa0 | 175 | perror_with_name (_("Unable to fetch the floating point registers")); |
41c49b06 | 176 | |
ed9a39eb | 177 | /* Store fpsr. */ |
0ec9f114 | 178 | if (REG_VALID == regcache->get_register_status (ARM_FPS_REGNUM)) |
34a79281 | 179 | regcache->raw_collect (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
180 | |
181 | /* Store the floating point registers. */ | |
34e8f22d | 182 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
0ec9f114 | 183 | if (REG_VALID == regcache->get_register_status (regno)) |
56be3814 | 184 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 185 | |
0bdb2f78 | 186 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
187 | { |
188 | struct iovec iov; | |
189 | ||
190 | iov.iov_base = &fp; | |
191 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
192 | ||
193 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
194 | } | |
195 | else | |
196 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
197 | ||
ed9a39eb | 198 | if (ret < 0) |
deb70aa0 | 199 | perror_with_name (_("Unable to store floating point registers")); |
ed9a39eb JM |
200 | } |
201 | ||
202 | /* Fetch all general registers of the process and store into | |
c6b92abd | 203 | regcache. */ |
ed9a39eb JM |
204 | |
205 | static void | |
56be3814 | 206 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 207 | { |
cf4088a9 | 208 | int ret, tid; |
c2152441 | 209 | elf_gregset_t regs; |
ed9a39eb | 210 | |
41c49b06 | 211 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 212 | tid = regcache->ptid ().lwp (); |
10766686 | 213 | |
0bdb2f78 | 214 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
215 | { |
216 | struct iovec iov; | |
217 | ||
218 | iov.iov_base = ®s; | |
219 | iov.iov_len = sizeof (regs); | |
220 | ||
221 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
222 | } | |
223 | else | |
224 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
225 | ||
ed9a39eb | 226 | if (ret < 0) |
deb70aa0 | 227 | perror_with_name (_("Unable to fetch general registers")); |
ed9a39eb | 228 | |
f1b67888 | 229 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
230 | } |
231 | ||
ed9a39eb | 232 | static void |
56be3814 | 233 | store_regs (const struct regcache *regcache) |
ed9a39eb | 234 | { |
cf4088a9 | 235 | int ret, tid; |
c2152441 | 236 | elf_gregset_t regs; |
ed9a39eb | 237 | |
41c49b06 | 238 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 239 | tid = regcache->ptid ().lwp (); |
10766686 | 240 | |
41c49b06 | 241 | /* Fetch the general registers. */ |
0bdb2f78 | 242 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
243 | { |
244 | struct iovec iov; | |
245 | ||
246 | iov.iov_base = ®s; | |
247 | iov.iov_len = sizeof (regs); | |
248 | ||
249 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
250 | } | |
251 | else | |
252 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
253 | ||
ed9a39eb | 254 | if (ret < 0) |
deb70aa0 | 255 | perror_with_name (_("Unable to fetch general registers")); |
ed9a39eb | 256 | |
f1b67888 | 257 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 258 | |
0bdb2f78 | 259 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
260 | { |
261 | struct iovec iov; | |
262 | ||
263 | iov.iov_base = ®s; | |
264 | iov.iov_len = sizeof (regs); | |
265 | ||
266 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
267 | } | |
268 | else | |
269 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
270 | |
271 | if (ret < 0) | |
deb70aa0 | 272 | perror_with_name (_("Unable to store general registers")); |
ed9a39eb JM |
273 | } |
274 | ||
05a4558a DJ |
275 | /* Fetch all WMMX registers of the process and store into |
276 | regcache. */ | |
277 | ||
05a4558a | 278 | static void |
56be3814 | 279 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
280 | { |
281 | char regbuf[IWMMXT_REGS_SIZE]; | |
282 | int ret, regno, tid; | |
283 | ||
284 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 285 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
286 | |
287 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
288 | if (ret < 0) | |
deb70aa0 | 289 | perror_with_name (_("Unable to fetch WMMX registers")); |
05a4558a DJ |
290 | |
291 | for (regno = 0; regno < 16; regno++) | |
73e1c03f | 292 | regcache->raw_supply (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
293 | |
294 | for (regno = 0; regno < 2; regno++) | |
73e1c03f SM |
295 | regcache->raw_supply (regno + ARM_WCSSF_REGNUM, |
296 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
297 | |
298 | for (regno = 0; regno < 4; regno++) | |
73e1c03f SM |
299 | regcache->raw_supply (regno + ARM_WCGR0_REGNUM, |
300 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
301 | } |
302 | ||
303 | static void | |
56be3814 | 304 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
305 | { |
306 | char regbuf[IWMMXT_REGS_SIZE]; | |
307 | int ret, regno, tid; | |
308 | ||
309 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 310 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
311 | |
312 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
313 | if (ret < 0) | |
deb70aa0 | 314 | perror_with_name (_("Unable to fetch WMMX registers")); |
05a4558a DJ |
315 | |
316 | for (regno = 0; regno < 16; regno++) | |
0ec9f114 | 317 | if (REG_VALID == regcache->get_register_status (regno + ARM_WR0_REGNUM)) |
34a79281 | 318 | regcache->raw_collect (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
319 | |
320 | for (regno = 0; regno < 2; regno++) | |
0ec9f114 | 321 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCSSF_REGNUM)) |
34a79281 SM |
322 | regcache->raw_collect (regno + ARM_WCSSF_REGNUM, |
323 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
324 | |
325 | for (regno = 0; regno < 4; regno++) | |
0ec9f114 | 326 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCGR0_REGNUM)) |
34a79281 SM |
327 | regcache->raw_collect (regno + ARM_WCGR0_REGNUM, |
328 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
329 | |
330 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
331 | ||
332 | if (ret < 0) | |
deb70aa0 | 333 | perror_with_name (_("Unable to store WMMX registers")); |
05a4558a DJ |
334 | } |
335 | ||
3b273a55 RE |
336 | static void |
337 | fetch_vfp_regs (struct regcache *regcache) | |
338 | { | |
350fab54 | 339 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 340 | int ret, tid; |
ac7936df | 341 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 342 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
3b273a55 RE |
343 | |
344 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 345 | tid = regcache->ptid ().lwp (); |
3b273a55 | 346 | |
0bdb2f78 | 347 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
348 | { |
349 | struct iovec iov; | |
350 | ||
351 | iov.iov_base = regbuf; | |
350fab54 | 352 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
353 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
354 | } | |
355 | else | |
356 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
357 | ||
3b273a55 | 358 | if (ret < 0) |
deb70aa0 | 359 | perror_with_name (_("Unable to fetch VFP registers")); |
3b273a55 | 360 | |
f1b67888 YQ |
361 | aarch32_vfp_regcache_supply (regcache, regbuf, |
362 | tdep->vfp_register_count); | |
3b273a55 RE |
363 | } |
364 | ||
365 | static void | |
366 | store_vfp_regs (const struct regcache *regcache) | |
367 | { | |
350fab54 | 368 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 369 | int ret, tid; |
ac7936df | 370 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 371 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
3b273a55 RE |
372 | |
373 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 374 | tid = regcache->ptid ().lwp (); |
3b273a55 | 375 | |
0bdb2f78 | 376 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
377 | { |
378 | struct iovec iov; | |
379 | ||
380 | iov.iov_base = regbuf; | |
350fab54 | 381 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
382 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
383 | } | |
384 | else | |
385 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
386 | ||
3b273a55 | 387 | if (ret < 0) |
deb70aa0 | 388 | perror_with_name (_("Unable to fetch VFP registers (for update)")); |
3b273a55 | 389 | |
f1b67888 YQ |
390 | aarch32_vfp_regcache_collect (regcache, regbuf, |
391 | tdep->vfp_register_count); | |
3b273a55 | 392 | |
0bdb2f78 | 393 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
394 | { |
395 | struct iovec iov; | |
396 | ||
397 | iov.iov_base = regbuf; | |
350fab54 | 398 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
399 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); |
400 | } | |
401 | else | |
402 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
403 | |
404 | if (ret < 0) | |
deb70aa0 | 405 | perror_with_name (_("Unable to store VFP registers")); |
3b273a55 RE |
406 | } |
407 | ||
ed9a39eb JM |
408 | /* Fetch registers from the child process. Fetch all registers if |
409 | regno == -1, otherwise fetch all general registers or all floating | |
410 | point registers depending upon the value of regno. */ | |
411 | ||
f6ac5f3d PA |
412 | void |
413 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 414 | { |
ac7936df | 415 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 416 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
330c6ca9 | 417 | |
41c49b06 SB |
418 | if (-1 == regno) |
419 | { | |
56be3814 | 420 | fetch_regs (regcache); |
a56cc1ce | 421 | if (tdep->have_wmmx_registers) |
56be3814 | 422 | fetch_wmmx_regs (regcache); |
330c6ca9 | 423 | if (tdep->vfp_register_count > 0) |
3b273a55 | 424 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
425 | if (tdep->have_fpa_registers) |
426 | fetch_fpregs (regcache); | |
41c49b06 | 427 | } |
4bd2e1b2 | 428 | else |
41c49b06 | 429 | { |
05a4558a | 430 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 431 | fetch_regs (regcache); |
05a4558a | 432 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 433 | fetch_fpregs (regcache); |
a56cc1ce | 434 | else if (tdep->have_wmmx_registers |
05a4558a | 435 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 436 | fetch_wmmx_regs (regcache); |
330c6ca9 | 437 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 438 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
439 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
440 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 441 | fetch_vfp_regs (regcache); |
41c49b06 | 442 | } |
ed9a39eb JM |
443 | } |
444 | ||
445 | /* Store registers back into the inferior. Store all registers if | |
446 | regno == -1, otherwise store all general registers or all floating | |
447 | point registers depending upon the value of regno. */ | |
448 | ||
f6ac5f3d PA |
449 | void |
450 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 451 | { |
ac7936df | 452 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 453 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
330c6ca9 | 454 | |
41c49b06 SB |
455 | if (-1 == regno) |
456 | { | |
56be3814 | 457 | store_regs (regcache); |
a56cc1ce | 458 | if (tdep->have_wmmx_registers) |
56be3814 | 459 | store_wmmx_regs (regcache); |
330c6ca9 | 460 | if (tdep->vfp_register_count > 0) |
3b273a55 | 461 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
462 | if (tdep->have_fpa_registers) |
463 | store_fpregs (regcache); | |
41c49b06 SB |
464 | } |
465 | else | |
466 | { | |
05a4558a | 467 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 468 | store_regs (regcache); |
05a4558a | 469 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 470 | store_fpregs (regcache); |
a56cc1ce | 471 | else if (tdep->have_wmmx_registers |
05a4558a | 472 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 473 | store_wmmx_regs (regcache); |
330c6ca9 | 474 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 475 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
476 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
477 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 478 | store_vfp_regs (regcache); |
41c49b06 | 479 | } |
ed9a39eb JM |
480 | } |
481 | ||
cb587d83 DJ |
482 | /* Wrapper functions for the standard regset handling, used by |
483 | thread debugging. */ | |
41c49b06 SB |
484 | |
485 | void | |
7f7fe91e UW |
486 | fill_gregset (const struct regcache *regcache, |
487 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 488 | { |
7f7fe91e | 489 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
490 | } |
491 | ||
41c49b06 | 492 | void |
7f7fe91e | 493 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 494 | { |
7f7fe91e | 495 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
496 | } |
497 | ||
41c49b06 | 498 | void |
7f7fe91e UW |
499 | fill_fpregset (const struct regcache *regcache, |
500 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 501 | { |
7f7fe91e | 502 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
503 | } |
504 | ||
505 | /* Fill GDB's register array with the floating-point register values | |
506 | in *fpregsetp. */ | |
507 | ||
508 | void | |
7f7fe91e | 509 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 510 | { |
7f7fe91e | 511 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
512 | } |
513 | ||
9308fc88 DJ |
514 | /* Fetch the thread-local storage pointer for libthread_db. */ |
515 | ||
516 | ps_err_e | |
754653a7 | 517 | ps_get_thread_area (struct ps_prochandle *ph, |
dda83cd7 | 518 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
519 | { |
520 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
521 | return PS_ERR; | |
522 | ||
523 | /* IDX is the bias from the thread pointer to the beginning of the | |
524 | thread descriptor. It has to be subtracted due to implementation | |
525 | quirks in libthread_db. */ | |
526 | *base = (void *) ((char *)*base - idx); | |
527 | ||
528 | return PS_OK; | |
529 | } | |
530 | ||
f6ac5f3d PA |
531 | const struct target_desc * |
532 | arm_linux_nat_target::read_description () | |
05a4558a | 533 | { |
a4a688ff JB |
534 | if (inferior_ptid == null_ptid) |
535 | return this->beneath ()->read_description (); | |
536 | ||
82d23ca8 | 537 | CORE_ADDR arm_hwcap = linux_get_hwcap (); |
05a4558a | 538 | |
0bdb2f78 | 539 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
540 | { |
541 | elf_gregset_t gpregs; | |
542 | struct iovec iov; | |
fbf3c4b9 | 543 | int tid = inferior_ptid.pid (); |
7efe48d1 YQ |
544 | |
545 | iov.iov_base = &gpregs; | |
546 | iov.iov_len = sizeof (gpregs); | |
547 | ||
548 | /* Check if PTRACE_GETREGSET works. */ | |
549 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 550 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 551 | else |
0bdb2f78 | 552 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
553 | } |
554 | ||
3b273a55 | 555 | if (arm_hwcap & HWCAP_IWMMXT) |
92d48a1e | 556 | return arm_read_description (ARM_FP_TYPE_IWMMXT, false); |
3b273a55 RE |
557 | |
558 | if (arm_hwcap & HWCAP_VFP) | |
559 | { | |
166a82be AH |
560 | /* Make sure that the kernel supports reading VFP registers. Support was |
561 | added in 2.6.30. */ | |
fbf3c4b9 | 562 | int pid = inferior_ptid.pid (); |
166a82be AH |
563 | errno = 0; |
564 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
565 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
566 | return nullptr; | |
3b273a55 RE |
567 | |
568 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
569 | Neon with VFPv3-D32. */ | |
570 | if (arm_hwcap & HWCAP_NEON) | |
d105cce5 | 571 | return aarch32_read_description (); |
3b273a55 | 572 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
92d48a1e | 573 | return arm_read_description (ARM_FP_TYPE_VFPV3, false); |
d105cce5 | 574 | |
92d48a1e | 575 | return arm_read_description (ARM_FP_TYPE_VFPV2, false); |
3b273a55 RE |
576 | } |
577 | ||
4360561f | 578 | return this->beneath ()->read_description (); |
05a4558a DJ |
579 | } |
580 | ||
e3039479 UW |
581 | /* Information describing the hardware breakpoint capabilities. */ |
582 | struct arm_linux_hwbp_cap | |
583 | { | |
584 | gdb_byte arch; | |
585 | gdb_byte max_wp_length; | |
586 | gdb_byte wp_count; | |
587 | gdb_byte bp_count; | |
588 | }; | |
589 | ||
638c5f49 OJ |
590 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
591 | assume a maximum number of supported break-/watchpoints. */ | |
592 | #define MAX_BPTS 16 | |
593 | #define MAX_WPTS 16 | |
594 | ||
e3039479 UW |
595 | /* Get hold of the Hardware Breakpoint information for the target we are |
596 | attached to. Returns NULL if the kernel doesn't support Hardware | |
597 | breakpoints at all, or a pointer to the information structure. */ | |
598 | static const struct arm_linux_hwbp_cap * | |
599 | arm_linux_get_hwbp_cap (void) | |
600 | { | |
601 | /* The info structure we return. */ | |
602 | static struct arm_linux_hwbp_cap info; | |
603 | ||
604 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
605 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
606 | means INFO is in an initialized state. */ | |
607 | static int available = -1; | |
608 | ||
609 | if (available == -1) | |
610 | { | |
611 | int tid; | |
612 | unsigned int val; | |
613 | ||
e38504b3 | 614 | tid = inferior_ptid.lwp (); |
e3039479 UW |
615 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
616 | available = 0; | |
617 | else | |
618 | { | |
619 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
620 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
621 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
622 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
623 | |
624 | if (info.wp_count > MAX_WPTS) | |
dda83cd7 SM |
625 | { |
626 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
627 | supports %d"), MAX_WPTS, info.wp_count); | |
628 | info.wp_count = MAX_WPTS; | |
629 | } | |
638c5f49 OJ |
630 | |
631 | if (info.bp_count > MAX_BPTS) | |
dda83cd7 SM |
632 | { |
633 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
634 | supports %d"), MAX_BPTS, info.bp_count); | |
635 | info.bp_count = MAX_BPTS; | |
636 | } | |
e3039479 UW |
637 | available = (info.arch != 0); |
638 | } | |
639 | } | |
640 | ||
641 | return available == 1 ? &info : NULL; | |
642 | } | |
643 | ||
644 | /* How many hardware breakpoints are available? */ | |
645 | static int | |
646 | arm_linux_get_hw_breakpoint_count (void) | |
647 | { | |
648 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
649 | return cap != NULL ? cap->bp_count : 0; | |
650 | } | |
651 | ||
652 | /* How many hardware watchpoints are available? */ | |
653 | static int | |
654 | arm_linux_get_hw_watchpoint_count (void) | |
655 | { | |
656 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
657 | return cap != NULL ? cap->wp_count : 0; | |
658 | } | |
659 | ||
660 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
661 | there is not an appropriate resource available, otherwise returns 1. */ | |
f6ac5f3d PA |
662 | int |
663 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
664 | int cnt, int ot) | |
e3039479 UW |
665 | { |
666 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
667 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
668 | { | |
dbbf180a YQ |
669 | int count = arm_linux_get_hw_watchpoint_count (); |
670 | ||
671 | if (count == 0) | |
672 | return 0; | |
673 | else if (cnt + ot > count) | |
e3039479 UW |
674 | return -1; |
675 | } | |
676 | else if (type == bp_hardware_breakpoint) | |
677 | { | |
dbbf180a YQ |
678 | int count = arm_linux_get_hw_breakpoint_count (); |
679 | ||
680 | if (count == 0) | |
681 | return 0; | |
682 | else if (cnt > count) | |
e3039479 UW |
683 | return -1; |
684 | } | |
685 | else | |
06d16ec9 | 686 | gdb_assert_not_reached ("unknown breakpoint type"); |
e3039479 UW |
687 | |
688 | return 1; | |
689 | } | |
690 | ||
691 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
692 | typedef enum | |
693 | { | |
694 | arm_hwbp_break = 0, | |
695 | arm_hwbp_load = 1, | |
696 | arm_hwbp_store = 2, | |
697 | arm_hwbp_access = 3 | |
698 | } arm_hwbp_type; | |
699 | ||
700 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
701 | typedef unsigned int arm_hwbp_control_t; | |
702 | ||
703 | /* Structure used to keep track of hardware break-/watch-points. */ | |
704 | struct arm_linux_hw_breakpoint | |
705 | { | |
706 | /* Address to break on, or being watched. */ | |
707 | unsigned int address; | |
708 | /* Control register for break-/watch- point. */ | |
709 | arm_hwbp_control_t control; | |
710 | }; | |
711 | ||
638c5f49 OJ |
712 | /* Structure containing arrays of per process hardware break-/watchpoints |
713 | for caching address and control information. | |
e3039479 UW |
714 | |
715 | The Linux ptrace interface to hardware break-/watch-points presents the | |
716 | values in a vector centred around 0 (which is used fo generic information). | |
717 | Positive indicies refer to breakpoint addresses/control registers, negative | |
718 | indices to watchpoint addresses/control registers. | |
719 | ||
720 | The Linux vector is indexed as follows: | |
721 | -((i << 1) + 2): Control register for watchpoint i. | |
722 | -((i << 1) + 1): Address register for watchpoint i. | |
dda83cd7 | 723 | 0: Information register. |
e3039479 UW |
724 | ((i << 1) + 1): Address register for breakpoint i. |
725 | ((i << 1) + 2): Control register for breakpoint i. | |
726 | ||
727 | This structure is used as a per-thread cache of the state stored by the | |
728 | kernel, so that we don't need to keep calling into the kernel to find a | |
729 | free breakpoint. | |
730 | ||
731 | We treat break-/watch-points with their enable bit clear as being deleted. | |
732 | */ | |
638c5f49 | 733 | struct arm_linux_debug_reg_state |
e3039479 | 734 | { |
638c5f49 OJ |
735 | /* Hardware breakpoints for this process. */ |
736 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
737 | /* Hardware watchpoints for this process. */ | |
738 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
739 | }; | |
740 | ||
741 | /* Per-process arch-specific data we want to keep. */ | |
742 | struct arm_linux_process_info | |
e3039479 | 743 | { |
638c5f49 OJ |
744 | /* Linked list. */ |
745 | struct arm_linux_process_info *next; | |
746 | /* The process identifier. */ | |
747 | pid_t pid; | |
748 | /* Hardware break-/watchpoints state information. */ | |
749 | struct arm_linux_debug_reg_state state; | |
e3039479 | 750 | |
638c5f49 OJ |
751 | }; |
752 | ||
753 | /* Per-thread arch-specific data we want to keep. */ | |
754 | struct arch_lwp_info | |
755 | { | |
756 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
757 | char bpts_changed[MAX_BPTS]; | |
758 | char wpts_changed[MAX_WPTS]; | |
759 | }; | |
760 | ||
761 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
762 | ||
763 | /* Find process data for process PID. */ | |
764 | ||
765 | static struct arm_linux_process_info * | |
766 | arm_linux_find_process_pid (pid_t pid) | |
767 | { | |
768 | struct arm_linux_process_info *proc; | |
769 | ||
770 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
771 | if (proc->pid == pid) | |
772 | return proc; | |
773 | ||
774 | return NULL; | |
775 | } | |
776 | ||
777 | /* Add process data for process PID. Returns newly allocated info | |
778 | object. */ | |
779 | ||
780 | static struct arm_linux_process_info * | |
781 | arm_linux_add_process (pid_t pid) | |
782 | { | |
783 | struct arm_linux_process_info *proc; | |
e3039479 | 784 | |
8d749320 | 785 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 786 | proc->pid = pid; |
e3039479 | 787 | |
638c5f49 OJ |
788 | proc->next = arm_linux_process_list; |
789 | arm_linux_process_list = proc; | |
790 | ||
791 | return proc; | |
792 | } | |
793 | ||
794 | /* Get data specific info for process PID, creating it if necessary. | |
795 | Never returns NULL. */ | |
796 | ||
797 | static struct arm_linux_process_info * | |
798 | arm_linux_process_info_get (pid_t pid) | |
799 | { | |
800 | struct arm_linux_process_info *proc; | |
801 | ||
802 | proc = arm_linux_find_process_pid (pid); | |
803 | if (proc == NULL) | |
804 | proc = arm_linux_add_process (pid); | |
805 | ||
806 | return proc; | |
807 | } | |
808 | ||
809 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
810 | data structures that keep track of debug register state. */ | |
811 | ||
135340af PA |
812 | void |
813 | arm_linux_nat_target::low_forget_process (pid_t pid) | |
638c5f49 OJ |
814 | { |
815 | struct arm_linux_process_info *proc, **proc_link; | |
816 | ||
817 | proc = arm_linux_process_list; | |
818 | proc_link = &arm_linux_process_list; | |
819 | ||
820 | while (proc != NULL) | |
821 | { | |
822 | if (proc->pid == pid) | |
e3039479 | 823 | { |
638c5f49 OJ |
824 | *proc_link = proc->next; |
825 | ||
826 | xfree (proc); | |
827 | return; | |
e3039479 UW |
828 | } |
829 | ||
638c5f49 OJ |
830 | proc_link = &proc->next; |
831 | proc = *proc_link; | |
832 | } | |
833 | } | |
834 | ||
835 | /* Get hardware break-/watchpoint state for process PID. */ | |
836 | ||
837 | static struct arm_linux_debug_reg_state * | |
838 | arm_linux_get_debug_reg_state (pid_t pid) | |
839 | { | |
840 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
841 | } |
842 | ||
843 | /* Initialize an ARM hardware break-/watch-point control register value. | |
844 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
845 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
846 | */ | |
847 | static arm_hwbp_control_t | |
848 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
849 | arm_hwbp_type hwbp_type, | |
850 | int enable) | |
851 | { | |
852 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
853 | gdb_assert (hwbp_type != arm_hwbp_break | |
854 | || ((byte_address_select & 0xfU) != 0)); | |
855 | ||
856 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
857 | } | |
858 | ||
859 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
860 | static int | |
861 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
862 | { | |
863 | return control & 0x1; | |
864 | } | |
865 | ||
866 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
867 | static arm_hwbp_control_t | |
868 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
869 | { | |
870 | return control & ~0x1; | |
871 | } | |
872 | ||
873 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
874 | enabled, and will point to the placed address of BP_TGT. */ | |
875 | static void | |
876 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
877 | struct bp_target_info *bp_tgt, | |
878 | struct arm_linux_hw_breakpoint *p) | |
879 | { | |
880 | unsigned mask; | |
0d5ed153 | 881 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
882 | |
883 | /* We have to create a mask for the control register which says which bits | |
884 | of the word pointed to by address to break on. */ | |
885 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
886 | { |
887 | mask = 0x3; | |
888 | address &= ~1; | |
889 | } | |
e3039479 | 890 | else |
fcf303ab UW |
891 | { |
892 | mask = 0xf; | |
893 | address &= ~3; | |
894 | } | |
e3039479 | 895 | |
fcf303ab | 896 | p->address = (unsigned int) address; |
e3039479 UW |
897 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
898 | } | |
899 | ||
8156fe7f | 900 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 901 | given when asked to set a watchpoint. */ |
e3039479 | 902 | static arm_hwbp_type |
f486487f | 903 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 904 | { |
8156fe7f | 905 | if (type == hw_read) |
e3039479 | 906 | return arm_hwbp_load; |
8156fe7f | 907 | else if (type == hw_write) |
e3039479 UW |
908 | return arm_hwbp_store; |
909 | else | |
910 | return arm_hwbp_access; | |
911 | } | |
912 | ||
913 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
914 | to LEN. The type of watchpoint is given in RW. */ | |
915 | static void | |
f486487f SM |
916 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
917 | enum target_hw_bp_type type, | |
e3039479 UW |
918 | struct arm_linux_hw_breakpoint *p) |
919 | { | |
920 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
921 | unsigned mask; | |
922 | ||
923 | gdb_assert (cap != NULL); | |
924 | gdb_assert (cap->max_wp_length != 0); | |
925 | ||
926 | mask = (1 << len) - 1; | |
927 | ||
928 | p->address = (unsigned int) addr; | |
929 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 930 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
931 | } |
932 | ||
933 | /* Are two break-/watch-points equal? */ | |
934 | static int | |
935 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
936 | const struct arm_linux_hw_breakpoint *p2) | |
937 | { | |
938 | return p1->address == p2->address && p1->control == p2->control; | |
939 | } | |
940 | ||
638c5f49 OJ |
941 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
942 | the current process. */ | |
943 | ||
638c5f49 | 944 | static int |
d3a70e03 | 945 | update_registers_callback (struct lwp_info *lwp, int watch, int index) |
638c5f49 | 946 | { |
638c5f49 OJ |
947 | if (lwp->arch_private == NULL) |
948 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
949 | ||
950 | /* The actual update is done later just before resuming the lwp, | |
951 | we just mark that the registers need updating. */ | |
d3a70e03 TT |
952 | if (watch) |
953 | lwp->arch_private->wpts_changed[index] = 1; | |
638c5f49 | 954 | else |
d3a70e03 | 955 | lwp->arch_private->bpts_changed[index] = 1; |
638c5f49 OJ |
956 | |
957 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
958 | we can update its breakpoint registers. */ | |
959 | if (!lwp->stopped) | |
960 | linux_stop_lwp (lwp); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
e3039479 UW |
965 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
966 | =1) BPT for thread TID. */ | |
967 | static void | |
968 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
dda83cd7 | 969 | int watchpoint) |
e3039479 | 970 | { |
638c5f49 OJ |
971 | int pid; |
972 | ptid_t pid_ptid; | |
e3039479 UW |
973 | gdb_byte count, i; |
974 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 975 | |
e99b03dc | 976 | pid = inferior_ptid.pid (); |
f2907e49 | 977 | pid_ptid = ptid_t (pid); |
e3039479 UW |
978 | |
979 | if (watchpoint) | |
980 | { | |
981 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 982 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
983 | } |
984 | else | |
985 | { | |
986 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 987 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
988 | } |
989 | ||
990 | for (i = 0; i < count; ++i) | |
991 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
992 | { | |
dda83cd7 SM |
993 | bpts[i] = *bpt; |
994 | iterate_over_lwps (pid_ptid, | |
d3a70e03 TT |
995 | [=] (struct lwp_info *info) |
996 | { | |
3a0e45b2 AH |
997 | return update_registers_callback (info, watchpoint, |
998 | i); | |
d3a70e03 | 999 | }); |
dda83cd7 | 1000 | break; |
e3039479 UW |
1001 | } |
1002 | ||
1003 | gdb_assert (i != count); | |
1004 | } | |
1005 | ||
1006 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1007 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1008 | static void | |
1009 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
dda83cd7 | 1010 | int watchpoint) |
e3039479 | 1011 | { |
638c5f49 | 1012 | int pid; |
e3039479 | 1013 | gdb_byte count, i; |
638c5f49 OJ |
1014 | ptid_t pid_ptid; |
1015 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 1016 | |
e99b03dc | 1017 | pid = inferior_ptid.pid (); |
f2907e49 | 1018 | pid_ptid = ptid_t (pid); |
e3039479 UW |
1019 | |
1020 | if (watchpoint) | |
1021 | { | |
1022 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1023 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1024 | } |
1025 | else | |
1026 | { | |
1027 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1028 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1029 | } |
1030 | ||
1031 | for (i = 0; i < count; ++i) | |
1032 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1033 | { | |
dda83cd7 | 1034 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); |
3a0e45b2 AH |
1035 | iterate_over_lwps (pid_ptid, |
1036 | [=] (struct lwp_info *info) | |
1037 | { | |
1038 | return update_registers_callback (info, watchpoint, | |
1039 | i); | |
1040 | }); | |
dda83cd7 | 1041 | break; |
e3039479 UW |
1042 | } |
1043 | ||
1044 | gdb_assert (i != count); | |
1045 | } | |
1046 | ||
1047 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1048 | int |
1049 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1050 | struct bp_target_info *bp_tgt) | |
e3039479 | 1051 | { |
e3039479 UW |
1052 | struct arm_linux_hw_breakpoint p; |
1053 | ||
1054 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1055 | return -1; | |
1056 | ||
1057 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1058 | |
1059 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1060 | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1065 | int |
1066 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1067 | struct bp_target_info *bp_tgt) | |
e3039479 | 1068 | { |
e3039479 UW |
1069 | struct arm_linux_hw_breakpoint p; |
1070 | ||
1071 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1072 | return -1; | |
1073 | ||
1074 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1075 | |
1076 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1077 | |
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1082 | ADDR? */ | |
f6ac5f3d PA |
1083 | int |
1084 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e3039479 UW |
1085 | { |
1086 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1087 | CORE_ADDR max_wp_length, aligned_addr; | |
1088 | ||
1089 | /* Can not set watchpoints for zero or negative lengths. */ | |
1090 | if (len <= 0) | |
1091 | return 0; | |
1092 | ||
1093 | /* Need to be able to use the ptrace interface. */ | |
1094 | if (cap == NULL || cap->wp_count == 0) | |
1095 | return 0; | |
1096 | ||
1097 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1098 | range covered by a watchpoint. */ | |
1099 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1100 | aligned_addr = addr & ~(max_wp_length - 1); | |
1101 | ||
1102 | if (aligned_addr + max_wp_length < addr + len) | |
1103 | return 0; | |
1104 | ||
1105 | /* The current ptrace interface can only handle watchpoints that are a | |
1106 | power of 2. */ | |
1107 | if ((len & (len - 1)) != 0) | |
1108 | return 0; | |
1109 | ||
1110 | /* All tests passed so we must be able to set a watchpoint. */ | |
1111 | return 1; | |
1112 | } | |
1113 | ||
1114 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1115 | int |
1116 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1117 | enum target_hw_bp_type rw, | |
1118 | struct expression *cond) | |
e3039479 | 1119 | { |
e3039479 UW |
1120 | struct arm_linux_hw_breakpoint p; |
1121 | ||
1122 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1123 | return -1; | |
1124 | ||
1125 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1126 | |
1127 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1128 | |
1129 | return 0; | |
1130 | } | |
1131 | ||
1132 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1133 | int |
1134 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, | |
1135 | int len, enum target_hw_bp_type rw, | |
1136 | struct expression *cond) | |
e3039479 | 1137 | { |
e3039479 UW |
1138 | struct arm_linux_hw_breakpoint p; |
1139 | ||
1140 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1141 | return -1; | |
1142 | ||
1143 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1144 | |
1145 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1146 | |
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | /* What was the data address the target was stopped on accessing. */ | |
57810aa7 | 1151 | bool |
f6ac5f3d | 1152 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e3039479 | 1153 | { |
f865ee35 JK |
1154 | siginfo_t siginfo; |
1155 | int slot; | |
1156 | ||
1157 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 1158 | return false; |
e3039479 UW |
1159 | |
1160 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1161 | if (siginfo.si_signo != SIGTRAP |
1162 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 1163 | return false; |
e3039479 UW |
1164 | |
1165 | /* We must be able to set hardware watchpoints. */ | |
1166 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1167 | return 0; | |
1168 | ||
f865ee35 JK |
1169 | slot = siginfo.si_errno; |
1170 | ||
e3039479 UW |
1171 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1172 | a watchpoint. */ | |
1173 | if (slot >= 0) | |
57810aa7 | 1174 | return false; |
e3039479 | 1175 | |
f865ee35 | 1176 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 1177 | return true; |
e3039479 UW |
1178 | } |
1179 | ||
1180 | /* Has the target been stopped by hitting a watchpoint? */ | |
57810aa7 | 1181 | bool |
f6ac5f3d | 1182 | arm_linux_nat_target::stopped_by_watchpoint () |
e3039479 UW |
1183 | { |
1184 | CORE_ADDR addr; | |
f6ac5f3d | 1185 | return stopped_data_address (&addr); |
e3039479 UW |
1186 | } |
1187 | ||
57810aa7 | 1188 | bool |
f6ac5f3d PA |
1189 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
1190 | CORE_ADDR start, | |
1191 | int length) | |
e3039479 UW |
1192 | { |
1193 | return start <= addr && start + length - 1 >= addr; | |
1194 | } | |
1195 | ||
1196 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1197 | in the parent thread to the child thread. */ | |
135340af PA |
1198 | void |
1199 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e3039479 | 1200 | { |
638c5f49 OJ |
1201 | int i; |
1202 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1203 | ||
1204 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1205 | for this thread need to be initialized. */ | |
e3039479 | 1206 | |
638c5f49 | 1207 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1208 | { |
638c5f49 OJ |
1209 | info->bpts_changed[i] = 1; |
1210 | info->wpts_changed[i] = 1; | |
e3039479 | 1211 | } |
638c5f49 OJ |
1212 | |
1213 | lp->arch_private = info; | |
e3039479 UW |
1214 | } |
1215 | ||
466eecee SM |
1216 | /* Function to call when a thread is being deleted. */ |
1217 | ||
135340af PA |
1218 | void |
1219 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) | |
466eecee SM |
1220 | { |
1221 | xfree (arch_lwp); | |
1222 | } | |
1223 | ||
638c5f49 OJ |
1224 | /* Called when resuming a thread. |
1225 | The hardware debug registers are updated when there is any change. */ | |
1226 | ||
135340af PA |
1227 | void |
1228 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) | |
e3039479 | 1229 | { |
638c5f49 OJ |
1230 | int pid, i; |
1231 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1232 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1233 | ||
e38504b3 | 1234 | pid = lwp->ptid.lwp (); |
e99b03dc TT |
1235 | bpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->bpts; |
1236 | wpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->wpts; | |
638c5f49 OJ |
1237 | |
1238 | /* NULL means this is the main thread still going through the shell, | |
1239 | or, no watchpoint has been set yet. In that case, there's | |
1240 | nothing to do. */ | |
1241 | if (arm_lwp_info == NULL) | |
1242 | return; | |
e3039479 | 1243 | |
638c5f49 OJ |
1244 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1245 | if (arm_lwp_info->bpts_changed[i]) | |
1246 | { | |
dda83cd7 SM |
1247 | errno = 0; |
1248 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1249 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1250 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1251 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1252 | ||
1253 | if (bpts[i].control != 0) | |
1254 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1255 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1256 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1257 | ||
1258 | arm_lwp_info->bpts_changed[i] = 0; | |
638c5f49 | 1259 | } |
e3039479 | 1260 | |
638c5f49 OJ |
1261 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1262 | if (arm_lwp_info->wpts_changed[i]) | |
1263 | { | |
dda83cd7 SM |
1264 | errno = 0; |
1265 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1266 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1267 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1268 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1269 | ||
1270 | if (wpts[i].control != 0) | |
1271 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1272 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1273 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1274 | ||
1275 | arm_lwp_info->wpts_changed[i] = 0; | |
638c5f49 OJ |
1276 | } |
1277 | } | |
1278 | ||
1279 | /* linux_nat_new_fork hook. */ | |
1280 | ||
135340af PA |
1281 | void |
1282 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) | |
638c5f49 OJ |
1283 | { |
1284 | pid_t parent_pid; | |
1285 | struct arm_linux_debug_reg_state *parent_state; | |
1286 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1287 | |
638c5f49 OJ |
1288 | /* NULL means no watchpoint has ever been set in the parent. In |
1289 | that case, there's nothing to do. */ | |
1290 | if (parent->arch_private == NULL) | |
1291 | return; | |
e3039479 | 1292 | |
638c5f49 OJ |
1293 | /* GDB core assumes the child inherits the watchpoints/hw |
1294 | breakpoints of the parent, and will remove them all from the | |
1295 | forked off process. Copy the debug registers mirrors into the | |
1296 | new process so that all breakpoints and watchpoints can be | |
1297 | removed together. */ | |
e3039479 | 1298 | |
e99b03dc | 1299 | parent_pid = parent->ptid.pid (); |
638c5f49 OJ |
1300 | parent_state = arm_linux_get_debug_reg_state (parent_pid); |
1301 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1302 | *child_state = *parent_state; | |
e3039479 UW |
1303 | } |
1304 | ||
6c265988 | 1305 | void _initialize_arm_linux_nat (); |
ed9a39eb | 1306 | void |
6c265988 | 1307 | _initialize_arm_linux_nat () |
ed9a39eb | 1308 | { |
10d6c8cd | 1309 | /* Register the target. */ |
f6ac5f3d | 1310 | linux_target = &the_arm_linux_nat_target; |
d9f719f1 | 1311 | add_inf_child_target (&the_arm_linux_nat_target); |
ed9a39eb | 1312 | } |