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51d21d60 | 1 | /* Target-dependent code for the S12Z, for the GDB. |
1d506c26 | 2 | Copyright (C) 2018-2024 Free Software Foundation, Inc. |
51d21d60 JD |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | /* Much of this file is shamelessly copied from or1k-tdep.c and others. */ | |
20 | ||
51d21d60 JD |
21 | |
22 | #include "arch-utils.h" | |
82ca8957 | 23 | #include "dwarf2/frame.h" |
268a13a5 | 24 | #include "gdbsupport/errors.h" |
51d21d60 JD |
25 | #include "frame-unwind.h" |
26 | #include "gdbcore.h" | |
5b9707eb | 27 | #include "cli/cli-cmds.h" |
51d21d60 JD |
28 | #include "inferior.h" |
29 | #include "opcode/s12z.h" | |
30 | #include "trad-frame.h" | |
31 | #include "remote.h" | |
f16f7b7c | 32 | #include "opcodes/s12z-opc.h" |
76eb8ef1 | 33 | #include "gdbarch.h" |
c8154ce0 | 34 | #include "disasm.h" |
51d21d60 JD |
35 | |
36 | /* Two of the registers included in S12Z_N_REGISTERS are | |
37 | the CCH and CCL "registers" which are just views into | |
38 | the CCW register. */ | |
39 | #define N_PHYSICAL_REGISTERS (S12Z_N_REGISTERS - 2) | |
40 | ||
41 | ||
c3247a98 JD |
42 | /* A permutation of all the physical registers. Indexing this array |
43 | with an integer from gdb's internal representation will return the | |
44 | register enum. */ | |
51d21d60 JD |
45 | static const int reg_perm[N_PHYSICAL_REGISTERS] = |
46 | { | |
47 | REG_D0, | |
48 | REG_D1, | |
49 | REG_D2, | |
50 | REG_D3, | |
51 | REG_D4, | |
52 | REG_D5, | |
53 | REG_D6, | |
54 | REG_D7, | |
55 | REG_X, | |
56 | REG_Y, | |
57 | REG_S, | |
58 | REG_P, | |
59 | REG_CCW | |
60 | }; | |
61 | ||
c3247a98 JD |
62 | /* The inverse of the above permutation. Indexing this |
63 | array with a register enum (e.g. REG_D2) will return the register | |
64 | number in gdb's internal representation. */ | |
65 | static const int inv_reg_perm[N_PHYSICAL_REGISTERS] = | |
66 | { | |
67 | 2, 3, 4, 5, /* d2, d3, d4, d5 */ | |
68 | 0, 1, /* d0, d1 */ | |
69 | 6, 7, /* d6, d7 */ | |
70 | 8, 9, 10, 11, 12 /* x, y, s, p, ccw */ | |
71 | }; | |
51d21d60 JD |
72 | |
73 | /* Return the name of the register REGNUM. */ | |
74 | static const char * | |
75 | s12z_register_name (struct gdbarch *gdbarch, int regnum) | |
76 | { | |
77 | /* Registers is declared in opcodes/s12z.h. */ | |
78 | return registers[reg_perm[regnum]].name; | |
79 | } | |
80 | ||
81 | static CORE_ADDR | |
82 | s12z_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
83 | { | |
84 | CORE_ADDR start_pc = 0; | |
85 | ||
86 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
87 | { | |
88 | CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc); | |
89 | ||
90 | if (prologue_end != 0) | |
dda83cd7 | 91 | return prologue_end; |
51d21d60 JD |
92 | } |
93 | ||
422186a9 TT |
94 | warning (_("%s Failed to find end of prologue PC = %08x"), |
95 | __FUNCTION__, (unsigned int) pc); | |
51d21d60 JD |
96 | |
97 | return pc; | |
98 | } | |
99 | ||
51d21d60 JD |
100 | static struct type * |
101 | s12z_register_type (struct gdbarch *gdbarch, int reg_nr) | |
102 | { | |
103 | switch (registers[reg_perm[reg_nr]].bytes) | |
104 | { | |
105 | case 1: | |
106 | return builtin_type (gdbarch)->builtin_uint8; | |
107 | case 2: | |
108 | return builtin_type (gdbarch)->builtin_uint16; | |
109 | case 3: | |
110 | return builtin_type (gdbarch)->builtin_uint24; | |
111 | case 4: | |
112 | return builtin_type (gdbarch)->builtin_uint32; | |
113 | default: | |
114 | return builtin_type (gdbarch)->builtin_uint32; | |
115 | } | |
116 | return builtin_type (gdbarch)->builtin_int0; | |
117 | } | |
118 | ||
119 | ||
120 | static int | |
121 | s12z_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int num) | |
122 | { | |
123 | switch (num) | |
124 | { | |
125 | case 15: return REG_S; | |
126 | case 7: return REG_X; | |
127 | case 8: return REG_Y; | |
128 | case 42: return REG_D0; | |
129 | case 43: return REG_D1; | |
130 | case 44: return REG_D2; | |
131 | case 45: return REG_D3; | |
132 | case 46: return REG_D4; | |
133 | case 47: return REG_D5; | |
134 | case 48: return REG_D6; | |
135 | case 49: return REG_D7; | |
136 | } | |
137 | return -1; | |
138 | } | |
139 | ||
140 | ||
141 | /* Support functions for frame handling. */ | |
142 | ||
c5358db4 JD |
143 | /* A struct (based on mem_read_abstraction_base) to read memory |
144 | through the disassemble_info API. */ | |
145 | struct mem_read_abstraction | |
146 | { | |
147 | struct mem_read_abstraction_base base; /* The parent struct. */ | |
148 | bfd_vma memaddr; /* Where to read from. */ | |
85102364 | 149 | struct disassemble_info* info; /* The disassembler to use for reading. */ |
c5358db4 JD |
150 | }; |
151 | ||
152 | /* Advance the reader by one byte. */ | |
153 | static void | |
154 | advance (struct mem_read_abstraction_base *b) | |
155 | { | |
156 | struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b; | |
157 | mra->memaddr++; | |
158 | } | |
159 | ||
160 | /* Return the current position of the reader. */ | |
161 | static bfd_vma | |
162 | posn (struct mem_read_abstraction_base *b) | |
163 | { | |
164 | struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b; | |
165 | return mra->memaddr; | |
166 | } | |
167 | ||
168 | /* Read the N bytes at OFFSET using B. The bytes read are stored in BYTES. | |
169 | It is the caller's responsibility to ensure that this is of at least N | |
170 | in size. */ | |
171 | static int | |
172 | abstract_read_memory (struct mem_read_abstraction_base *b, | |
173 | int offset, | |
174 | size_t n, bfd_byte *bytes) | |
175 | { | |
176 | struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b; | |
177 | ||
178 | int status = | |
179 | (*mra->info->read_memory_func) (mra->memaddr + offset, | |
180 | bytes, n, mra->info); | |
181 | ||
182 | if (status != 0) | |
183 | { | |
184 | (*mra->info->memory_error_func) (status, mra->memaddr, mra->info); | |
185 | return -1; | |
186 | } | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | ||
192 | /* Return the stack adjustment caused by a push or pull instruction. */ | |
193 | static int | |
194 | push_pull_get_stack_adjustment (int n_operands, | |
195 | struct operand *const *operands) | |
196 | { | |
197 | int stack_adjustment = 0; | |
198 | gdb_assert (n_operands > 0); | |
199 | if (operands[0]->cl == OPND_CL_REGISTER_ALL) | |
200 | stack_adjustment = 26; /* All the regs are involved. */ | |
201 | else if (operands[0]->cl == OPND_CL_REGISTER_ALL16) | |
202 | stack_adjustment = 4 * 2; /* All four 16 bit regs are involved. */ | |
203 | else | |
204 | for (int i = 0; i < n_operands; ++i) | |
205 | { | |
206 | if (operands[i]->cl != OPND_CL_REGISTER) | |
207 | continue; /* I don't think this can ever happen. */ | |
208 | const struct register_operand *op | |
209 | = (const struct register_operand *) operands[i]; | |
210 | switch (op->reg) | |
211 | { | |
212 | case REG_X: | |
213 | case REG_Y: | |
214 | stack_adjustment += 3; | |
215 | break; | |
216 | case REG_D7: | |
217 | case REG_D6: | |
218 | stack_adjustment += 4; | |
219 | break; | |
220 | case REG_D2: | |
221 | case REG_D3: | |
222 | case REG_D4: | |
223 | case REG_D5: | |
224 | stack_adjustment += 2; | |
225 | break; | |
226 | case REG_D0: | |
227 | case REG_D1: | |
228 | case REG_CCL: | |
229 | case REG_CCH: | |
230 | stack_adjustment += 1; | |
231 | break; | |
232 | default: | |
233 | gdb_assert_not_reached ("Invalid register in push/pull operation."); | |
234 | break; | |
235 | } | |
236 | } | |
237 | return stack_adjustment; | |
238 | } | |
239 | ||
51d21d60 JD |
240 | /* Initialize a prologue cache. */ |
241 | ||
242 | static struct trad_frame_cache * | |
8480a37e | 243 | s12z_frame_cache (const frame_info_ptr &this_frame, void **prologue_cache) |
51d21d60 JD |
244 | { |
245 | struct trad_frame_cache *info; | |
246 | ||
247 | CORE_ADDR this_sp; | |
248 | CORE_ADDR this_sp_for_id; | |
249 | ||
250 | CORE_ADDR start_addr; | |
251 | CORE_ADDR end_addr; | |
252 | ||
253 | /* Nothing to do if we already have this info. */ | |
254 | if (NULL != *prologue_cache) | |
255 | return (struct trad_frame_cache *) *prologue_cache; | |
256 | ||
257 | /* Get a new prologue cache and populate it with default values. */ | |
258 | info = trad_frame_cache_zalloc (this_frame); | |
259 | *prologue_cache = info; | |
260 | ||
261 | /* Find the start address of this function (which is a normal frame, even | |
262 | if the next frame is the sentinel frame) and the end of its prologue. */ | |
263 | CORE_ADDR this_pc = get_frame_pc (this_frame); | |
264 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
265 | find_pc_partial_function (this_pc, NULL, &start_addr, NULL); | |
266 | ||
267 | /* Get the stack pointer if we have one (if there's no process executing | |
268 | yet we won't have a frame. */ | |
269 | this_sp = (NULL == this_frame) ? 0 : | |
270 | get_frame_register_unsigned (this_frame, REG_S); | |
271 | ||
272 | /* Return early if GDB couldn't find the function. */ | |
273 | if (start_addr == 0) | |
274 | { | |
422186a9 | 275 | warning (_("Couldn't find function including address %s SP is %s"), |
dda83cd7 SM |
276 | paddress (gdbarch, this_pc), |
277 | paddress (gdbarch, this_sp)); | |
51d21d60 JD |
278 | |
279 | /* JPB: 28-Apr-11. This is a temporary patch, to get round GDB | |
280 | crashing right at the beginning. Build the frame ID as best we | |
281 | can. */ | |
282 | trad_frame_set_id (info, frame_id_build (this_sp, this_pc)); | |
283 | ||
284 | return info; | |
285 | } | |
286 | ||
287 | /* The default frame base of this frame (for ID purposes only - frame | |
288 | base is an overloaded term) is its stack pointer. For now we use the | |
289 | value of the SP register in this frame. However if the PC is in the | |
290 | prologue of this frame, before the SP has been set up, then the value | |
291 | will actually be that of the prev frame, and we'll need to adjust it | |
292 | later. */ | |
293 | trad_frame_set_this_base (info, this_sp); | |
294 | this_sp_for_id = this_sp; | |
295 | ||
296 | /* We should only examine code that is in the prologue. This is all code | |
297 | up to (but not including) end_addr. We should only populate the cache | |
298 | while the address is up to (but not including) the PC or end_addr, | |
299 | whichever is first. */ | |
300 | end_addr = s12z_skip_prologue (gdbarch, start_addr); | |
301 | ||
302 | /* All the following analysis only occurs if we are in the prologue and | |
303 | have executed the code. Check we have a sane prologue size, and if | |
304 | zero we are frameless and can give up here. */ | |
305 | if (end_addr < start_addr) | |
306 | error (_("end addr %s is less than start addr %s"), | |
307 | paddress (gdbarch, end_addr), paddress (gdbarch, start_addr)); | |
308 | ||
309 | CORE_ADDR addr = start_addr; /* Where we have got to? */ | |
310 | int frame_size = 0; | |
311 | int saved_frame_size = 0; | |
51d21d60 | 312 | |
8b39b1e7 | 313 | struct gdb_non_printing_memory_disassembler dis (gdbarch); |
51d21d60 | 314 | |
c5358db4 JD |
315 | struct mem_read_abstraction mra; |
316 | mra.base.read = (int (*)(mem_read_abstraction_base*, | |
317 | int, size_t, bfd_byte*)) abstract_read_memory; | |
318 | mra.base.advance = advance ; | |
319 | mra.base.posn = posn; | |
8b39b1e7 | 320 | mra.info = dis.disasm_info (); |
51d21d60 | 321 | |
c5358db4 JD |
322 | while (this_pc > addr) |
323 | { | |
324 | enum optr optr = OP_INVALID; | |
325 | short osize; | |
326 | int n_operands = 0; | |
327 | struct operand *operands[6]; | |
328 | mra.memaddr = addr; | |
329 | int n_bytes = | |
330 | decode_s12z (&optr, &osize, &n_operands, operands, | |
331 | (mem_read_abstraction_base *) &mra); | |
332 | ||
333 | switch (optr) | |
334 | { | |
335 | case OP_tbNE: | |
336 | case OP_tbPL: | |
337 | case OP_tbMI: | |
338 | case OP_tbGT: | |
339 | case OP_tbLE: | |
340 | case OP_dbNE: | |
341 | case OP_dbEQ: | |
342 | case OP_dbPL: | |
343 | case OP_dbMI: | |
344 | case OP_dbGT: | |
345 | case OP_dbLE: | |
346 | /* Conditional Branches. If any of these are encountered, then | |
347 | it is likely that a RTS will terminate it. So we need to save | |
348 | the frame size so it can be restored. */ | |
349 | saved_frame_size = frame_size; | |
350 | break; | |
351 | case OP_rts: | |
352 | /* Restore the frame size from a previously saved value. */ | |
353 | frame_size = saved_frame_size; | |
354 | break; | |
355 | case OP_push: | |
356 | frame_size += push_pull_get_stack_adjustment (n_operands, operands); | |
357 | break; | |
358 | case OP_pull: | |
359 | frame_size -= push_pull_get_stack_adjustment (n_operands, operands); | |
360 | break; | |
361 | case OP_lea: | |
362 | if (operands[0]->cl == OPND_CL_REGISTER) | |
363 | { | |
364 | int reg = ((struct register_operand *) (operands[0]))->reg; | |
365 | if ((reg == REG_S) && (operands[1]->cl == OPND_CL_MEMORY)) | |
366 | { | |
367 | const struct memory_operand *mo | |
368 | = (const struct memory_operand * ) operands[1]; | |
369 | if (mo->n_regs == 1 && !mo->indirect | |
370 | && mo->regs[0] == REG_S | |
371 | && mo->mutation == OPND_RM_NONE) | |
372 | { | |
373 | /* LEA S, (xxx, S) -- Decrement the stack. This is | |
374 | almost certainly the start of a frame. */ | |
375 | int simm = (signed char) mo->base_offset; | |
376 | frame_size -= simm; | |
377 | } | |
378 | } | |
379 | } | |
380 | break; | |
381 | default: | |
382 | break; | |
383 | } | |
384 | addr += n_bytes; | |
385 | for (int o = 0; o < n_operands; ++o) | |
386 | free (operands[o]); | |
51d21d60 JD |
387 | } |
388 | ||
389 | /* If the PC has not actually got to this point, then the frame | |
390 | base will be wrong, and we adjust it. */ | |
391 | if (this_pc < addr) | |
392 | { | |
393 | /* Only do if executing. */ | |
394 | if (0 != this_sp) | |
dda83cd7 SM |
395 | { |
396 | this_sp_for_id = this_sp - frame_size; | |
397 | trad_frame_set_this_base (info, this_sp_for_id); | |
398 | } | |
51d21d60 JD |
399 | trad_frame_set_reg_value (info, REG_S, this_sp + 3); |
400 | trad_frame_set_reg_addr (info, REG_P, this_sp); | |
401 | } | |
402 | else | |
403 | { | |
7b5227d1 | 404 | gdb_assert (this_sp == this_sp_for_id); |
51d21d60 | 405 | /* The stack pointer of the prev frame is frame_size greater |
dda83cd7 SM |
406 | than the stack pointer of this frame plus one address |
407 | size (caused by the JSR or BSR). */ | |
51d21d60 | 408 | trad_frame_set_reg_value (info, REG_S, |
dda83cd7 | 409 | this_sp + frame_size + 3); |
51d21d60 JD |
410 | trad_frame_set_reg_addr (info, REG_P, this_sp + frame_size); |
411 | } | |
412 | ||
413 | ||
414 | /* Build the frame ID. */ | |
415 | trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr)); | |
416 | ||
417 | return info; | |
418 | } | |
419 | ||
420 | /* Implement the this_id function for the stub unwinder. */ | |
421 | static void | |
8480a37e | 422 | s12z_frame_this_id (const frame_info_ptr &this_frame, |
51d21d60 JD |
423 | void **prologue_cache, struct frame_id *this_id) |
424 | { | |
425 | struct trad_frame_cache *info = s12z_frame_cache (this_frame, | |
426 | prologue_cache); | |
427 | ||
428 | trad_frame_get_id (info, this_id); | |
429 | } | |
430 | ||
431 | ||
432 | /* Implement the prev_register function for the stub unwinder. */ | |
433 | static struct value * | |
8480a37e | 434 | s12z_frame_prev_register (const frame_info_ptr &this_frame, |
51d21d60 JD |
435 | void **prologue_cache, int regnum) |
436 | { | |
437 | struct trad_frame_cache *info = s12z_frame_cache (this_frame, | |
438 | prologue_cache); | |
439 | ||
440 | return trad_frame_get_register (info, this_frame, regnum); | |
441 | } | |
442 | ||
443 | /* Data structures for the normal prologue-analysis-based unwinder. */ | |
444 | static const struct frame_unwind s12z_frame_unwind = { | |
a154d838 | 445 | "s12z prologue", |
51d21d60 JD |
446 | NORMAL_FRAME, |
447 | default_frame_unwind_stop_reason, | |
448 | s12z_frame_this_id, | |
449 | s12z_frame_prev_register, | |
450 | NULL, | |
451 | default_frame_sniffer, | |
452 | NULL, | |
453 | }; | |
454 | ||
455 | ||
456 | constexpr gdb_byte s12z_break_insn[] = {0x00}; | |
457 | ||
458 | typedef BP_MANIPULATION (s12z_break_insn) s12z_breakpoint; | |
459 | ||
ab25d9bb | 460 | struct s12z_gdbarch_tdep : gdbarch_tdep_base |
51d21d60 JD |
461 | { |
462 | }; | |
463 | ||
464 | /* A vector of human readable characters representing the | |
465 | bits in the CCW register. Unused bits are represented as '-'. | |
466 | Lowest significant bit comes first. */ | |
467 | static const char ccw_bits[] = | |
468 | { | |
469 | 'C', /* Carry */ | |
470 | 'V', /* Two's Complement Overflow */ | |
471 | 'Z', /* Zero */ | |
472 | 'N', /* Negative */ | |
473 | 'I', /* Interrupt */ | |
474 | '-', | |
475 | 'X', /* Non-Maskable Interrupt */ | |
476 | 'S', /* STOP Disable */ | |
477 | '0', /* Interrupt priority level */ | |
478 | '0', /* ditto */ | |
479 | '0', /* ditto */ | |
480 | '-', | |
481 | '-', | |
482 | '-', | |
483 | '-', | |
484 | 'U' /* User/Supervisor State. */ | |
485 | }; | |
486 | ||
487 | /* Print a human readable representation of the CCW register. | |
488 | For example: "u----000SX-Inzvc" corresponds to the value | |
489 | 0xD0. */ | |
490 | static void | |
491 | s12z_print_ccw_info (struct gdbarch *gdbarch, | |
dda83cd7 | 492 | struct ui_file *file, |
8480a37e | 493 | const frame_info_ptr &frame, |
dda83cd7 | 494 | int reg) |
51d21d60 | 495 | { |
a7952927 | 496 | value *v = value_of_register (reg, get_next_frame_sentinel_okay (frame)); |
51d21d60 JD |
497 | const char *name = gdbarch_register_name (gdbarch, reg); |
498 | uint32_t ccw = value_as_long (v); | |
0426ad51 | 499 | gdb_puts (name, file); |
51d21d60 JD |
500 | size_t len = strlen (name); |
501 | const int stop_1 = 15; | |
502 | const int stop_2 = 17; | |
503 | for (int i = 0; i < stop_1 - len; ++i) | |
a11ac3b3 | 504 | gdb_putc (' ', file); |
6cb06a8c | 505 | gdb_printf (file, "0x%04x", ccw); |
51d21d60 | 506 | for (int i = 0; i < stop_2 - len; ++i) |
a11ac3b3 | 507 | gdb_putc (' ', file); |
51d21d60 JD |
508 | for (int b = 15; b >= 0; --b) |
509 | { | |
510 | if (ccw & (0x1u << b)) | |
dda83cd7 SM |
511 | { |
512 | if (ccw_bits[b] == 0) | |
a11ac3b3 | 513 | gdb_putc ('1', file); |
dda83cd7 | 514 | else |
a11ac3b3 | 515 | gdb_putc (ccw_bits[b], file); |
dda83cd7 | 516 | } |
51d21d60 | 517 | else |
a11ac3b3 | 518 | gdb_putc (tolower (ccw_bits[b]), file); |
51d21d60 | 519 | } |
a11ac3b3 | 520 | gdb_putc ('\n', file); |
51d21d60 JD |
521 | } |
522 | ||
523 | static void | |
524 | s12z_print_registers_info (struct gdbarch *gdbarch, | |
525 | struct ui_file *file, | |
8480a37e | 526 | const frame_info_ptr &frame, |
51d21d60 JD |
527 | int regnum, int print_all) |
528 | { | |
529 | const int numregs = (gdbarch_num_regs (gdbarch) | |
530 | + gdbarch_num_pseudo_regs (gdbarch)); | |
531 | ||
532 | if (regnum == -1) | |
533 | { | |
534 | for (int reg = 0; reg < numregs; reg++) | |
dda83cd7 SM |
535 | { |
536 | if (REG_CCW == reg_perm[reg]) | |
537 | { | |
538 | s12z_print_ccw_info (gdbarch, file, frame, reg); | |
539 | continue; | |
540 | } | |
541 | default_print_registers_info (gdbarch, file, frame, reg, print_all); | |
542 | } | |
51d21d60 JD |
543 | } |
544 | else if (REG_CCW == reg_perm[regnum]) | |
545 | s12z_print_ccw_info (gdbarch, file, frame, regnum); | |
546 | else | |
547 | default_print_registers_info (gdbarch, file, frame, regnum, print_all); | |
548 | } | |
549 | ||
550 | \f | |
551 | ||
c3247a98 JD |
552 | |
553 | static void | |
554 | s12z_extract_return_value (struct type *type, struct regcache *regcache, | |
dda83cd7 | 555 | void *valbuf) |
c3247a98 JD |
556 | { |
557 | int reg = -1; | |
558 | ||
df86565b | 559 | switch (type->length ()) |
c3247a98 JD |
560 | { |
561 | case 0: /* Nothing to do */ | |
562 | return; | |
563 | ||
564 | case 1: | |
565 | reg = REG_D0; | |
566 | break; | |
567 | ||
568 | case 2: | |
569 | reg = REG_D2; | |
570 | break; | |
571 | ||
572 | case 3: | |
573 | reg = REG_X; | |
574 | break; | |
575 | ||
576 | case 4: | |
577 | reg = REG_D6; | |
578 | break; | |
579 | ||
580 | default: | |
581 | error (_("bad size for return value")); | |
582 | return; | |
583 | } | |
584 | ||
585 | regcache->cooked_read (inv_reg_perm[reg], (gdb_byte *) valbuf); | |
586 | } | |
587 | ||
51d21d60 JD |
588 | static enum return_value_convention |
589 | s12z_return_value (struct gdbarch *gdbarch, struct value *function, | |
dda83cd7 SM |
590 | struct type *type, struct regcache *regcache, |
591 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
51d21d60 | 592 | { |
78134374 SM |
593 | if (type->code () == TYPE_CODE_STRUCT |
594 | || type->code () == TYPE_CODE_UNION | |
595 | || type->code () == TYPE_CODE_ARRAY | |
df86565b | 596 | || type->length () > 4) |
c3247a98 JD |
597 | return RETURN_VALUE_STRUCT_CONVENTION; |
598 | ||
599 | if (readbuf) | |
600 | s12z_extract_return_value (type, regcache, readbuf); | |
601 | ||
51d21d60 JD |
602 | return RETURN_VALUE_REGISTER_CONVENTION; |
603 | } | |
604 | ||
605 | ||
606 | static void | |
607 | show_bdccsr_command (const char *args, int from_tty) | |
608 | { | |
609 | struct string_file output; | |
610 | target_rcmd ("bdccsr", &output); | |
611 | ||
6cb06a8c | 612 | gdb_printf ("The current BDCCSR value is %s\n", output.string().c_str()); |
51d21d60 JD |
613 | } |
614 | ||
615 | static struct gdbarch * | |
616 | s12z_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
617 | { | |
2b16913c SM |
618 | gdbarch *gdbarch |
619 | = gdbarch_alloc (&info, gdbarch_tdep_up (new s12z_gdbarch_tdep)); | |
51d21d60 JD |
620 | |
621 | add_cmd ("bdccsr", class_support, show_bdccsr_command, | |
622 | _("Show the current value of the microcontroller's BDCCSR."), | |
dda83cd7 | 623 | &maintenanceinfolist); |
51d21d60 JD |
624 | |
625 | /* Target data types. */ | |
626 | set_gdbarch_short_bit (gdbarch, 16); | |
627 | set_gdbarch_int_bit (gdbarch, 16); | |
628 | set_gdbarch_long_bit (gdbarch, 32); | |
629 | set_gdbarch_long_long_bit (gdbarch, 32); | |
630 | set_gdbarch_ptr_bit (gdbarch, 24); | |
631 | set_gdbarch_addr_bit (gdbarch, 24); | |
632 | set_gdbarch_char_signed (gdbarch, 0); | |
633 | ||
634 | set_gdbarch_ps_regnum (gdbarch, REG_CCW); | |
635 | set_gdbarch_pc_regnum (gdbarch, REG_P); | |
636 | set_gdbarch_sp_regnum (gdbarch, REG_S); | |
637 | ||
638 | ||
639 | set_gdbarch_print_registers_info (gdbarch, s12z_print_registers_info); | |
640 | ||
641 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, | |
642 | s12z_breakpoint::kind_from_pc); | |
643 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
644 | s12z_breakpoint::bp_from_kind); | |
645 | ||
646 | set_gdbarch_num_regs (gdbarch, N_PHYSICAL_REGISTERS); | |
647 | set_gdbarch_register_name (gdbarch, s12z_register_name); | |
648 | set_gdbarch_skip_prologue (gdbarch, s12z_skip_prologue); | |
649 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
650 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, s12z_dwarf_reg_to_regnum); | |
651 | ||
652 | set_gdbarch_register_type (gdbarch, s12z_register_type); | |
653 | ||
51d21d60 | 654 | frame_unwind_append_unwinder (gdbarch, &s12z_frame_unwind); |
85102364 | 655 | /* Currently, the only known producer for this architecture, produces buggy |
51d21d60 JD |
656 | dwarf CFI. So don't append a dwarf unwinder until the situation is |
657 | better understood. */ | |
658 | ||
659 | set_gdbarch_return_value (gdbarch, s12z_return_value); | |
660 | ||
661 | return gdbarch; | |
662 | } | |
663 | ||
6c265988 | 664 | void _initialize_s12z_tdep (); |
51d21d60 | 665 | void |
6c265988 | 666 | _initialize_s12z_tdep () |
51d21d60 JD |
667 | { |
668 | gdbarch_register (bfd_arch_s12z, s12z_gdbarch_init, NULL); | |
669 | } |