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Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
1d506c26 | 3 | Copyright (C) 1993-2024 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
c906108c | 22 | |
ec452525 | 23 | #include "extract-store-integer.h" |
c906108c | 24 | #include "frame.h" |
1c0159e0 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
82ca8957 | 27 | #include "dwarf2/frame.h" |
c906108c | 28 | #include "symtab.h" |
c906108c | 29 | #include "gdbtypes.h" |
5b9707eb | 30 | #include "cli/cli-cmds.h" |
c906108c SS |
31 | #include "gdbcore.h" |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
73c1f219 | 34 | #include "inferior.h" |
b4a20239 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
3b2ca824 | 37 | #include "target-float.h" |
4be87837 | 38 | #include "osabi.h" |
dda63807 | 39 | #include "reggroups.h" |
c9ac0a72 | 40 | #include "regset.h" |
cb2cf4ce | 41 | #include "objfiles.h" |
c906108c | 42 | |
ab3b8126 JT |
43 | #include "sh-tdep.h" |
44 | ||
d658f924 | 45 | #include "elf-bfd.h" |
1a8629c7 MS |
46 | #include "solib-svr4.h" |
47 | ||
55ff77ac | 48 | /* sh flags */ |
283150cd | 49 | #include "elf/sh.h" |
fa8f86ff | 50 | #include "dwarf2.h" |
c378eb4e | 51 | /* registers numbers shared with the simulator. */ |
d026e67e | 52 | #include "sim/sim-sh.h" |
325fac50 | 53 | #include <algorithm> |
283150cd | 54 | |
c055b101 CV |
55 | /* List of "set sh ..." and "show sh ..." commands. */ |
56 | static struct cmd_list_element *setshcmdlist = NULL; | |
57 | static struct cmd_list_element *showshcmdlist = NULL; | |
58 | ||
59 | static const char sh_cc_gcc[] = "gcc"; | |
60 | static const char sh_cc_renesas[] = "renesas"; | |
40478521 | 61 | static const char *const sh_cc_enum[] = { |
c055b101 CV |
62 | sh_cc_gcc, |
63 | sh_cc_renesas, | |
64 | NULL | |
65 | }; | |
66 | ||
67 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
68 | ||
da962468 | 69 | #define SH_NUM_REGS 67 |
88e04cc1 | 70 | |
1c0159e0 | 71 | struct sh_frame_cache |
cc17453a | 72 | { |
1c0159e0 CV |
73 | /* Base address. */ |
74 | CORE_ADDR base; | |
75 | LONGEST sp_offset; | |
76 | CORE_ADDR pc; | |
77 | ||
c378eb4e | 78 | /* Flag showing that a frame has been created in the prologue code. */ |
1c0159e0 CV |
79 | int uses_fp; |
80 | ||
81 | /* Saved registers. */ | |
82 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
83 | CORE_ADDR saved_sp; | |
63978407 | 84 | }; |
c906108c | 85 | |
c055b101 CV |
86 | static int |
87 | sh_is_renesas_calling_convention (struct type *func_type) | |
88 | { | |
ca193e27 TS |
89 | int val = 0; |
90 | ||
91 | if (func_type) | |
92 | { | |
93 | func_type = check_typedef (func_type); | |
94 | ||
78134374 | 95 | if (func_type->code () == TYPE_CODE_PTR) |
27710edb | 96 | func_type = check_typedef (func_type->target_type ()); |
ca193e27 | 97 | |
78134374 | 98 | if (func_type->code () == TYPE_CODE_FUNC |
dda83cd7 SM |
99 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) |
100 | val = 1; | |
ca193e27 TS |
101 | } |
102 | ||
103 | if (sh_active_calling_convention == sh_cc_renesas) | |
104 | val = 1; | |
105 | ||
106 | return val; | |
c055b101 CV |
107 | } |
108 | ||
fa88f677 | 109 | static const char * |
d93859e2 | 110 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 111 | { |
a121b7c1 | 112 | static const char *register_names[] = { |
617daa0e CV |
113 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
114 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
9a972b54 | 115 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr" |
cc17453a | 116 | }; |
9a972b54 | 117 | |
9b9e61c7 | 118 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 119 | return ""; |
cc17453a EZ |
120 | return register_names[reg_nr]; |
121 | } | |
122 | ||
fa88f677 | 123 | static const char * |
d93859e2 | 124 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 125 | { |
a121b7c1 | 126 | static const char *register_names[] = { |
617daa0e CV |
127 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
128 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
129 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
130 | "", "", | |
131 | "", "", "", "", "", "", "", "", | |
132 | "", "", "", "", "", "", "", "", | |
133 | "ssr", "spc", | |
cc17453a | 134 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
9a972b54 | 135 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
cc17453a | 136 | }; |
9a972b54 | 137 | |
9b9e61c7 | 138 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 139 | return ""; |
cc17453a EZ |
140 | return register_names[reg_nr]; |
141 | } | |
142 | ||
fa88f677 | 143 | static const char * |
d93859e2 | 144 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 145 | { |
a121b7c1 | 146 | static const char *register_names[] = { |
617daa0e CV |
147 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
148 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
149 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 150 | "fpul", "fpscr", |
617daa0e CV |
151 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
152 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
153 | "ssr", "spc", | |
cc17453a EZ |
154 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
155 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
156 | }; | |
9b9e61c7 | 157 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 158 | return ""; |
cc17453a EZ |
159 | return register_names[reg_nr]; |
160 | } | |
161 | ||
2d188dd3 | 162 | static const char * |
d93859e2 | 163 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 164 | { |
a121b7c1 | 165 | static const char *register_names[] = { |
617daa0e CV |
166 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
167 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
168 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 169 | "fpul", "fpscr", |
617daa0e CV |
170 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
171 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
da962468 | 172 | }; |
9b9e61c7 | 173 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 174 | return ""; |
da962468 CV |
175 | return register_names[reg_nr]; |
176 | } | |
177 | ||
178 | static const char * | |
d93859e2 | 179 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 | 180 | { |
a121b7c1 | 181 | static const char *register_names[] = { |
da962468 CV |
182 | /* general registers 0-15 */ |
183 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
184 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
185 | /* 16 - 22 */ | |
186 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
187 | /* 23, 24 */ | |
188 | "fpul", "fpscr", | |
189 | /* floating point registers 25 - 40 */ | |
190 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
191 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
192 | /* 41, 42 */ | |
193 | "", "", | |
194 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 195 | the bank register (63). */ |
da962468 CV |
196 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
197 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
198 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
199 | /* 63: register bank number, not a real register but used to | |
200 | communicate the register bank currently get/set. This register | |
201 | is hidden to the user, who manipulates it using the pseudo | |
202 | register called "bank" (67). See below. */ | |
203 | "", | |
204 | /* 64 - 66 */ | |
205 | "ibcr", "ibnr", "tbr", | |
206 | /* 67: register bank number, the user visible pseudo register. */ | |
207 | "bank", | |
208 | /* double precision (pseudo) 68 - 75 */ | |
209 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
210 | }; | |
9b9e61c7 | 211 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 212 | return ""; |
da962468 CV |
213 | return register_names[reg_nr]; |
214 | } | |
215 | ||
216 | static const char * | |
d93859e2 | 217 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 | 218 | { |
a121b7c1 | 219 | static const char *register_names[] = { |
da962468 CV |
220 | /* general registers 0-15 */ |
221 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
222 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
223 | /* 16 - 22 */ | |
224 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
225 | /* 23, 24 */ | |
226 | "", "", | |
227 | /* floating point registers 25 - 40 */ | |
228 | "", "", "", "", "", "", "", "", | |
229 | "", "", "", "", "", "", "", "", | |
230 | /* 41, 42 */ | |
231 | "", "", | |
232 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 233 | the bank register (63). */ |
da962468 CV |
234 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
235 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
236 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
237 | /* 63: register bank number, not a real register but used to | |
238 | communicate the register bank currently get/set. This register | |
239 | is hidden to the user, who manipulates it using the pseudo | |
240 | register called "bank" (67). See below. */ | |
241 | "", | |
242 | /* 64 - 66 */ | |
243 | "ibcr", "ibnr", "tbr", | |
244 | /* 67: register bank number, the user visible pseudo register. */ | |
245 | "bank", | |
9a972b54 | 246 | /* double precision (pseudo) 68 - 75: report blank, see below. */ |
2d188dd3 | 247 | }; |
9b9e61c7 | 248 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 249 | return ""; |
2d188dd3 NC |
250 | return register_names[reg_nr]; |
251 | } | |
252 | ||
fa88f677 | 253 | static const char * |
d93859e2 | 254 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 255 | { |
a121b7c1 | 256 | static const char *register_names[] = { |
617daa0e CV |
257 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
258 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
259 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
260 | "", "dsr", | |
261 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
262 | "y0", "y1", "", "", "", "", "", "mod", | |
263 | "", "", | |
9a972b54 | 264 | "rs", "re", |
cc17453a | 265 | }; |
9b9e61c7 | 266 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 267 | return ""; |
cc17453a EZ |
268 | return register_names[reg_nr]; |
269 | } | |
270 | ||
fa88f677 | 271 | static const char * |
d93859e2 | 272 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 273 | { |
a121b7c1 | 274 | static const char *register_names[] = { |
617daa0e CV |
275 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
276 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
277 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
278 | "", "dsr", | |
279 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
280 | "y0", "y1", "", "", "", "", "", "mod", | |
281 | "ssr", "spc", | |
282 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 | 283 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
cc17453a | 284 | }; |
9b9e61c7 | 285 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 286 | return ""; |
cc17453a EZ |
287 | return register_names[reg_nr]; |
288 | } | |
289 | ||
fa88f677 | 290 | static const char * |
d93859e2 | 291 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 292 | { |
a121b7c1 | 293 | static const char *register_names[] = { |
a38d2a54 | 294 | /* general registers 0-15 */ |
617daa0e CV |
295 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
296 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 297 | /* 16 - 22 */ |
617daa0e | 298 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 299 | /* 23, 24 */ |
53116e27 | 300 | "fpul", "fpscr", |
a38d2a54 | 301 | /* floating point registers 25 - 40 */ |
617daa0e CV |
302 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
303 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 304 | /* 41, 42 */ |
617daa0e | 305 | "ssr", "spc", |
a38d2a54 | 306 | /* bank 0 43 - 50 */ |
53116e27 | 307 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 308 | /* bank 1 51 - 58 */ |
53116e27 | 309 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a6521d9a | 310 | /* 59 - 66 */ |
da962468 | 311 | "", "", "", "", "", "", "", "", |
c378eb4e | 312 | /* pseudo bank register. */ |
da962468 | 313 | "", |
a6521d9a | 314 | /* double precision (pseudo) 68 - 75 */ |
617daa0e | 315 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a6521d9a | 316 | /* vectors (pseudo) 76 - 79 */ |
617daa0e | 317 | "fv0", "fv4", "fv8", "fv12", |
a6521d9a TS |
318 | /* FIXME: missing XF */ |
319 | /* FIXME: missing XD */ | |
53116e27 | 320 | }; |
9b9e61c7 | 321 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 322 | return ""; |
53116e27 EZ |
323 | return register_names[reg_nr]; |
324 | } | |
325 | ||
474e5826 | 326 | static const char * |
d93859e2 | 327 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 | 328 | { |
a121b7c1 | 329 | static const char *register_names[] = { |
474e5826 CV |
330 | /* general registers 0-15 */ |
331 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
332 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
333 | /* 16 - 22 */ | |
334 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
335 | /* 23, 24 */ | |
336 | "", "", | |
337 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
338 | "", "", "", "", "", "", "", "", | |
339 | "", "", "", "", "", "", "", "", | |
340 | /* 41, 42 */ | |
341 | "ssr", "spc", | |
342 | /* bank 0 43 - 50 */ | |
343 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
344 | /* bank 1 51 - 58 */ | |
345 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
a6521d9a | 346 | /* 59 - 66 */ |
da962468 | 347 | "", "", "", "", "", "", "", "", |
c378eb4e | 348 | /* pseudo bank register. */ |
da962468 | 349 | "", |
a6521d9a | 350 | /* double precision (pseudo) 68 - 75 -- not for nofpu target */ |
474e5826 | 351 | "", "", "", "", "", "", "", "", |
9a972b54 AB |
352 | /* vectors (pseudo) 76 - 79 -- not for nofpu target: report blank |
353 | below. */ | |
474e5826 | 354 | }; |
9b9e61c7 | 355 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 356 | return ""; |
474e5826 CV |
357 | return register_names[reg_nr]; |
358 | } | |
359 | ||
360 | static const char * | |
d93859e2 | 361 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 | 362 | { |
a121b7c1 | 363 | static const char *register_names[] = { |
474e5826 CV |
364 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
365 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
366 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
367 | "", "dsr", | |
368 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
369 | "y0", "y1", "", "", "", "", "", "mod", | |
370 | "ssr", "spc", | |
371 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 | 372 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
474e5826 | 373 | }; |
9b9e61c7 | 374 | if (reg_nr >= ARRAY_SIZE (register_names)) |
9a972b54 | 375 | return ""; |
474e5826 CV |
376 | return register_names[reg_nr]; |
377 | } | |
378 | ||
cd6c3b4f YQ |
379 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
380 | ||
d19280ad YQ |
381 | static int |
382 | sh_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cc17453a | 383 | { |
d19280ad YQ |
384 | return 2; |
385 | } | |
386 | ||
cd6c3b4f YQ |
387 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
388 | ||
d19280ad YQ |
389 | static const gdb_byte * |
390 | sh_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
391 | { | |
392 | *size = kind; | |
617daa0e | 393 | |
bac718a6 | 394 | /* For remote stub targets, trapa #20 is used. */ |
d777bf0d | 395 | if (strcmp (target_shortname (), "remote") == 0) |
bac718a6 UW |
396 | { |
397 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
398 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
399 | ||
67d57894 | 400 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 401 | return big_remote_breakpoint; |
bac718a6 | 402 | else |
d19280ad | 403 | return little_remote_breakpoint; |
bac718a6 | 404 | } |
d19280ad YQ |
405 | else |
406 | { | |
407 | /* 0xc3c3 is trapa #c3, and it works in big and little endian | |
408 | modes. */ | |
409 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; | |
bac718a6 | 410 | |
d19280ad YQ |
411 | return breakpoint; |
412 | } | |
cc17453a | 413 | } |
c906108c SS |
414 | |
415 | /* Prologue looks like | |
1c0159e0 CV |
416 | mov.l r14,@-r15 |
417 | sts.l pr,@-r15 | |
418 | mov.l <regs>,@-r15 | |
419 | sub <room_for_loca_vars>,r15 | |
420 | mov r15,r14 | |
8db62801 | 421 | |
c378eb4e | 422 | Actually it can be more complicated than this but that's it, basically. */ |
c906108c | 423 | |
1c0159e0 CV |
424 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
425 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
426 | ||
5f883edd FF |
427 | /* JSR @Rm 0100mmmm00001011 */ |
428 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
429 | ||
8db62801 EZ |
430 | /* STS.L PR,@-r15 0100111100100010 |
431 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 432 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 433 | |
03131d99 CV |
434 | /* STS.L MACL,@-r15 0100111100010010 |
435 | r15-4-->r15, MACL-->(r15) */ | |
436 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
437 | ||
8db62801 EZ |
438 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
439 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 440 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 441 | |
8db62801 EZ |
442 | /* MOV r15,r14 0110111011110011 |
443 | r15-->r14 */ | |
c906108c | 444 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
445 | |
446 | /* ADD #imm,r15 01111111iiiiiiii | |
447 | r15+imm-->r15 */ | |
1c0159e0 | 448 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 449 | |
c906108c SS |
450 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
451 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
452 | |
453 | /* ADD r3,r15 0011111100111100 | |
454 | r15+r3-->r15 */ | |
c906108c | 455 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
456 | |
457 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 458 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 459 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 | 460 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
c378eb4e | 461 | make this entirely clear. */ |
1c0159e0 CV |
462 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
463 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
464 | ||
465 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
466 | #define IS_MOV_ARG_TO_REG(x) \ | |
467 | (((x) & 0xf00f) == 0x6003 && \ | |
468 | ((x) & 0x00f0) >= 0x0040 && \ | |
469 | ((x) & 0x00f0) <= 0x0070) | |
470 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
471 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
472 | (((x) & 0xff0f) == 0x2e02 && \ | |
473 | ((x) & 0x00f0) >= 0x0040 && \ | |
474 | ((x) & 0x00f0) <= 0x0070) | |
475 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
476 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
477 | (((x) & 0xff00) == 0x1e00 && \ | |
478 | ((x) & 0x00f0) >= 0x0040 && \ | |
479 | ((x) & 0x00f0) <= 0x0070) | |
480 | ||
481 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
482 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
483 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
484 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
485 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
486 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
487 | /* SUB Rn,R15 00111111nnnn1000 */ |
488 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 489 | |
1c0159e0 | 490 | #define FPSCR_SZ (1 << 20) |
cc17453a | 491 | |
c378eb4e | 492 | /* The following instructions are used for epilogue testing. */ |
1c0159e0 CV |
493 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) |
494 | #define IS_RTS(x) ((x) == 0x000b) | |
495 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 496 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
497 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
498 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
499 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 500 | |
cc17453a | 501 | static CORE_ADDR |
e17a4113 | 502 | sh_analyze_prologue (struct gdbarch *gdbarch, |
5cbb9812 | 503 | CORE_ADDR pc, CORE_ADDR limit_pc, |
d2ca4222 | 504 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 505 | { |
e17a4113 | 506 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 | 507 | ULONGEST inst; |
1c0159e0 CV |
508 | int offset; |
509 | int sav_offset = 0; | |
c906108c | 510 | int r3_val = 0; |
1c0159e0 | 511 | int reg, sav_reg = -1; |
cc17453a | 512 | |
1c0159e0 | 513 | cache->uses_fp = 0; |
5cbb9812 | 514 | for (; pc < limit_pc; pc += 2) |
cc17453a | 515 | { |
e17a4113 | 516 | inst = read_memory_unsigned_integer (pc, 2, byte_order); |
c378eb4e | 517 | /* See where the registers will be saved to. */ |
f2ea0907 | 518 | if (IS_PUSH (inst)) |
cc17453a | 519 | { |
1c0159e0 CV |
520 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
521 | cache->sp_offset += 4; | |
cc17453a | 522 | } |
f2ea0907 | 523 | else if (IS_STS (inst)) |
cc17453a | 524 | { |
1c0159e0 CV |
525 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
526 | cache->sp_offset += 4; | |
cc17453a | 527 | } |
03131d99 CV |
528 | else if (IS_MACL_STS (inst)) |
529 | { | |
530 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
531 | cache->sp_offset += 4; | |
532 | } | |
f2ea0907 | 533 | else if (IS_MOV_R3 (inst)) |
cc17453a | 534 | { |
f2ea0907 | 535 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 536 | } |
f2ea0907 | 537 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
538 | { |
539 | r3_val <<= 1; | |
540 | } | |
f2ea0907 | 541 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 542 | { |
1c0159e0 | 543 | cache->sp_offset += -r3_val; |
cc17453a | 544 | } |
f2ea0907 | 545 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 546 | { |
1c0159e0 CV |
547 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
548 | cache->sp_offset -= offset; | |
c906108c | 549 | } |
1c0159e0 | 550 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 551 | { |
1c0159e0 CV |
552 | if (sav_reg < 0) |
553 | { | |
554 | reg = GET_TARGET_REG (inst); | |
555 | if (reg < 14) | |
556 | { | |
557 | sav_reg = reg; | |
a2b4a96c | 558 | offset = (inst & 0xff) << 1; |
1c0159e0 | 559 | sav_offset = |
e17a4113 | 560 | read_memory_integer ((pc + 4) + offset, 2, byte_order); |
1c0159e0 CV |
561 | } |
562 | } | |
c906108c | 563 | } |
1c0159e0 | 564 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 565 | { |
1c0159e0 CV |
566 | if (sav_reg < 0) |
567 | { | |
a2b4a96c | 568 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
569 | if (reg < 14) |
570 | { | |
571 | sav_reg = reg; | |
a2b4a96c | 572 | offset = (inst & 0xff) << 2; |
1c0159e0 | 573 | sav_offset = |
e17a4113 UW |
574 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, |
575 | 4, byte_order); | |
1c0159e0 CV |
576 | } |
577 | } | |
c906108c | 578 | } |
5cbb9812 TS |
579 | else if (IS_MOVI20 (inst) |
580 | && (pc + 2 < limit_pc)) | |
dda83cd7 | 581 | { |
03131d99 CV |
582 | if (sav_reg < 0) |
583 | { | |
584 | reg = GET_TARGET_REG (inst); | |
585 | if (reg < 14) | |
dda83cd7 | 586 | { |
03131d99 CV |
587 | sav_reg = reg; |
588 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
c378eb4e | 589 | /* MOVI20 is a 32 bit instruction! */ |
03131d99 | 590 | pc += 2; |
e17a4113 UW |
591 | sav_offset |
592 | |= read_memory_unsigned_integer (pc, 2, byte_order); | |
03131d99 CV |
593 | /* Now sav_offset contains an unsigned 20 bit value. |
594 | It must still get sign extended. */ | |
595 | if (sav_offset & 0x00080000) | |
596 | sav_offset |= 0xfff00000; | |
597 | } | |
598 | } | |
599 | } | |
1c0159e0 | 600 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 601 | { |
1c0159e0 CV |
602 | reg = GET_SOURCE_REG (inst); |
603 | if (sav_reg > 0 && reg == sav_reg) | |
604 | { | |
605 | sav_reg = -1; | |
606 | } | |
607 | cache->sp_offset += sav_offset; | |
c906108c | 608 | } |
f2ea0907 | 609 | else if (IS_FPUSH (inst)) |
c906108c | 610 | { |
d2ca4222 | 611 | if (fpscr & FPSCR_SZ) |
c906108c | 612 | { |
1c0159e0 | 613 | cache->sp_offset += 8; |
c906108c SS |
614 | } |
615 | else | |
616 | { | |
1c0159e0 | 617 | cache->sp_offset += 4; |
c906108c SS |
618 | } |
619 | } | |
f2ea0907 | 620 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 621 | { |
5cbb9812 TS |
622 | pc += 2; |
623 | /* Don't go any further than six more instructions. */ | |
325fac50 | 624 | limit_pc = std::min (limit_pc, pc + (2 * 6)); |
5cbb9812 | 625 | |
960ccd7d | 626 | cache->uses_fp = 1; |
1c0159e0 CV |
627 | /* At this point, only allow argument register moves to other |
628 | registers or argument register moves to @(X,fp) which are | |
629 | moving the register arguments onto the stack area allocated | |
630 | by a former add somenumber to SP call. Don't allow moving | |
c378eb4e | 631 | to an fp indirect address above fp + cache->sp_offset. */ |
5cbb9812 | 632 | for (; pc < limit_pc; pc += 2) |
1c0159e0 | 633 | { |
e17a4113 | 634 | inst = read_memory_integer (pc, 2, byte_order); |
1c0159e0 | 635 | if (IS_MOV_ARG_TO_IND_R14 (inst)) |
617daa0e | 636 | { |
1c0159e0 CV |
637 | reg = GET_SOURCE_REG (inst); |
638 | if (cache->sp_offset > 0) | |
617daa0e | 639 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
640 | } |
641 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 642 | { |
1c0159e0 CV |
643 | reg = GET_SOURCE_REG (inst); |
644 | offset = (inst & 0xf) * 4; | |
645 | if (cache->sp_offset > offset) | |
646 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
647 | } | |
648 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 649 | continue; |
1c0159e0 CV |
650 | else |
651 | break; | |
652 | } | |
653 | break; | |
654 | } | |
5f883edd FF |
655 | else if (IS_JSR (inst)) |
656 | { | |
657 | /* We have found a jsr that has been scheduled into the prologue. | |
658 | If we continue the scan and return a pc someplace after this, | |
659 | then setting a breakpoint on this function will cause it to | |
660 | appear to be called after the function it is calling via the | |
661 | jsr, which will be very confusing. Most likely the next | |
662 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
c378eb4e | 663 | so, note that before returning the current pc. */ |
5cbb9812 TS |
664 | if (pc + 2 < limit_pc) |
665 | { | |
666 | inst = read_memory_integer (pc + 2, 2, byte_order); | |
667 | if (IS_MOV_SP_FP (inst)) | |
668 | cache->uses_fp = 1; | |
669 | } | |
5f883edd FF |
670 | break; |
671 | } | |
c378eb4e MS |
672 | #if 0 /* This used to just stop when it found an instruction |
673 | that was not considered part of the prologue. Now, | |
674 | we just keep going looking for likely | |
675 | instructions. */ | |
c906108c SS |
676 | else |
677 | break; | |
2bfa91ee | 678 | #endif |
c906108c SS |
679 | } |
680 | ||
1c0159e0 CV |
681 | return pc; |
682 | } | |
c906108c | 683 | |
c378eb4e | 684 | /* Skip any prologue before the guts of a function. */ |
1c0159e0 | 685 | static CORE_ADDR |
8a8bc27f | 686 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 687 | { |
5cbb9812 | 688 | CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; |
1c0159e0 CV |
689 | struct sh_frame_cache cache; |
690 | ||
691 | /* See if we can determine the end of the prologue via the symbol table. | |
692 | If so, then return either PC, or the PC after the prologue, whichever | |
693 | is greater. */ | |
5cbb9812 | 694 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
8a8bc27f TS |
695 | { |
696 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); | |
697 | if (post_prologue_pc != 0) | |
dda83cd7 | 698 | return std::max (pc, post_prologue_pc); |
8a8bc27f | 699 | } |
cc17453a | 700 | |
8a8bc27f TS |
701 | /* Can't determine prologue from the symbol table, need to examine |
702 | instructions. */ | |
c906108c | 703 | |
5cbb9812 TS |
704 | /* Find an upper limit on the function prologue using the debug |
705 | information. If the debug information could not be used to provide | |
706 | that bound, then use an arbitrary large number as the upper bound. */ | |
707 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
708 | if (limit_pc == 0) | |
709 | /* Don't go any further than 28 instructions. */ | |
710 | limit_pc = pc + (2 * 28); | |
711 | ||
712 | /* Do not allow limit_pc to be past the function end, if we know | |
713 | where that end is... */ | |
714 | if (func_end_addr != 0) | |
325fac50 | 715 | limit_pc = std::min (limit_pc, func_end_addr); |
5cbb9812 | 716 | |
1c0159e0 | 717 | cache.sp_offset = -4; |
5cbb9812 | 718 | post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); |
8a8bc27f TS |
719 | if (cache.uses_fp) |
720 | pc = post_prologue_pc; | |
c906108c | 721 | |
1c0159e0 CV |
722 | return pc; |
723 | } | |
724 | ||
2e952408 | 725 | /* The ABI says: |
9a5cef92 EZ |
726 | |
727 | Aggregate types not bigger than 8 bytes that have the same size and | |
728 | alignment as one of the integer scalar types are returned in the | |
729 | same registers as the integer type they match. | |
730 | ||
731 | For example, a 2-byte aligned structure with size 2 bytes has the | |
732 | same size and alignment as a short int, and will be returned in R0. | |
733 | A 4-byte aligned structure with size 8 bytes has the same size and | |
734 | alignment as a long long int, and will be returned in R0 and R1. | |
735 | ||
736 | When an aggregate type is returned in R0 and R1, R0 contains the | |
737 | first four bytes of the aggregate, and R1 contains the | |
c378eb4e | 738 | remainder. If the size of the aggregate type is not a multiple of 4 |
9a5cef92 | 739 | bytes, the aggregate is tail-padded up to a multiple of 4 |
c378eb4e | 740 | bytes. The value of the padding is undefined. For little-endian |
9a5cef92 EZ |
741 | targets the padding will appear at the most significant end of the |
742 | last element, for big-endian targets the padding appears at the | |
743 | least significant end of the last element. | |
744 | ||
c378eb4e | 745 | All other aggregate types are returned by address. The caller |
9a5cef92 | 746 | function passes the address of an area large enough to hold the |
c378eb4e | 747 | aggregate value in R2. The called function stores the result in |
7fe958be | 748 | this location. |
9a5cef92 EZ |
749 | |
750 | To reiterate, structs smaller than 8 bytes could also be returned | |
751 | in memory, if they don't pass the "same size and alignment as an | |
752 | integer type" rule. | |
753 | ||
754 | For example, in | |
755 | ||
756 | struct s { char c[3]; } wibble; | |
757 | struct s foo(void) { return wibble; } | |
758 | ||
759 | the return value from foo() will be in memory, not | |
760 | in R0, because there is no 3-byte integer type. | |
761 | ||
7fe958be EZ |
762 | Similarly, in |
763 | ||
764 | struct s { char c[2]; } wibble; | |
765 | struct s foo(void) { return wibble; } | |
766 | ||
767 | because a struct containing two chars has alignment 1, that matches | |
768 | type char, but size 2, that matches type short. There's no integer | |
769 | type that has alignment 1 and size 2, so the struct is returned in | |
c378eb4e | 770 | memory. */ |
9a5cef92 | 771 | |
1c0159e0 | 772 | static int |
c055b101 | 773 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 | 774 | { |
df86565b | 775 | int len = type->length (); |
1f704f76 | 776 | int nelem = type->num_fields (); |
3f997a97 | 777 | |
c055b101 | 778 | /* The Renesas ABI returns aggregate types always on stack. */ |
78134374 SM |
779 | if (renesas_abi && (type->code () == TYPE_CODE_STRUCT |
780 | || type->code () == TYPE_CODE_UNION)) | |
c055b101 CV |
781 | return 1; |
782 | ||
3f997a97 CV |
783 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
784 | fit in two registers anyway) use struct convention. */ | |
785 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
786 | return 1; | |
787 | ||
788 | /* Scalar types and aggregate types with exactly one field are aligned | |
789 | by definition. They are returned in registers. */ | |
790 | if (nelem <= 1) | |
791 | return 0; | |
792 | ||
793 | /* If the first field in the aggregate has the same length as the entire | |
794 | aggregate type, the type is returned in registers. */ | |
df86565b | 795 | if (type->field (0).type ()->length () == len) |
3f997a97 CV |
796 | return 0; |
797 | ||
798 | /* If the size of the aggregate is 8 bytes and the first field is | |
799 | of size 4 bytes its alignment is equal to long long's alignment, | |
800 | so it's returned in registers. */ | |
df86565b | 801 | if (len == 8 && type->field (0).type ()->length () == 4) |
3f997a97 CV |
802 | return 0; |
803 | ||
804 | /* Otherwise use struct convention. */ | |
805 | return 1; | |
283150cd EZ |
806 | } |
807 | ||
c055b101 CV |
808 | static int |
809 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
810 | { | |
811 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
df86565b | 812 | if (renesas_abi && type->num_fields () == 0 && type->length () >= 8) |
c055b101 CV |
813 | return 1; |
814 | return sh_use_struct_convention (renesas_abi, type); | |
815 | } | |
816 | ||
19f59343 MS |
817 | static CORE_ADDR |
818 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
819 | { | |
820 | return sp & ~3; | |
821 | } | |
822 | ||
55ff77ac | 823 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
824 | Setup the function arguments for calling a function in the inferior. |
825 | ||
85a453d5 | 826 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
827 | which are dedicated for passing function arguments. Up to the first |
828 | four arguments (depending on size) may go into these registers. | |
829 | The rest go on the stack. | |
830 | ||
6df2bf50 MS |
831 | MVS: Except on SH variants that have floating point registers. |
832 | In that case, float and double arguments are passed in the same | |
833 | manner, but using FP registers instead of GP registers. | |
834 | ||
c906108c SS |
835 | Arguments that are smaller than 4 bytes will still take up a whole |
836 | register or a whole 32-bit word on the stack, and will be | |
837 | right-justified in the register or the stack word. This includes | |
838 | chars, shorts, and small aggregate types. | |
839 | ||
840 | Arguments that are larger than 4 bytes may be split between two or | |
841 | more registers. If there are not enough registers free, an argument | |
842 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 843 | stack. This includes doubles, long longs, and larger aggregates. |
c906108c SS |
844 | As far as I know, there is no upper limit to the size of aggregates |
845 | that will be passed in this way; in other words, the convention of | |
846 | passing a pointer to a large aggregate instead of a copy is not used. | |
847 | ||
6df2bf50 | 848 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 849 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
850 | aggregate argument onto the stack (and not place it in registers) |
851 | if it is larger than 16 bytes (four GP registers). | |
852 | ||
c906108c SS |
853 | An exceptional case exists for struct arguments (and possibly other |
854 | aggregates such as arrays) if the size is larger than 4 bytes but | |
855 | not a multiple of 4 bytes. In this case the argument is never split | |
856 | between the registers and the stack, but instead is copied in its | |
857 | entirety onto the stack, AND also copied into as many registers as | |
858 | there is room for. In other words, space in registers permitting, | |
859 | two copies of the same argument are passed in. As far as I can tell, | |
860 | only the one on the stack is used, although that may be a function | |
861 | of the level of compiler optimization. I suspect this is a compiler | |
862 | bug. Arguments of these odd sizes are left-justified within the | |
863 | word (as opposed to arguments smaller than 4 bytes, which are | |
864 | right-justified). | |
c5aa993b | 865 | |
c906108c SS |
866 | If the function is to return an aggregate type such as a struct, it |
867 | is either returned in the normal return value register R0 (if its | |
868 | size is no greater than one byte), or else the caller must allocate | |
869 | space into which the callee will copy the return value (if the size | |
870 | is greater than one byte). In this case, a pointer to the return | |
871 | value location is passed into the callee in register R2, which does | |
872 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 873 | to R7. */ |
c906108c | 874 | |
405feb71 | 875 | /* Helper function to justify value in register according to endianness. */ |
948f8e3d | 876 | static const gdb_byte * |
d93859e2 | 877 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 | 878 | { |
948f8e3d | 879 | static gdb_byte valbuf[4]; |
e5e33cd9 | 880 | |
617daa0e | 881 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
882 | if (len < 4) |
883 | { | |
c378eb4e | 884 | /* value gets right-justified in the register or stack word. */ |
d93859e2 | 885 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
efaf1ae0 | 886 | memcpy (valbuf + (4 - len), val->contents ().data (), len); |
e5e33cd9 | 887 | else |
efaf1ae0 | 888 | memcpy (valbuf, val->contents ().data (), len); |
e5e33cd9 CV |
889 | return valbuf; |
890 | } | |
efaf1ae0 | 891 | return val->contents ().data (); |
617daa0e | 892 | } |
e5e33cd9 | 893 | |
c378eb4e | 894 | /* Helper function to eval number of bytes to allocate on stack. */ |
e5e33cd9 CV |
895 | static CORE_ADDR |
896 | sh_stack_allocsize (int nargs, struct value **args) | |
897 | { | |
898 | int stack_alloc = 0; | |
899 | while (nargs-- > 0) | |
d0c97917 | 900 | stack_alloc += ((args[nargs]->type ()->length () + 3) & ~3); |
e5e33cd9 CV |
901 | return stack_alloc; |
902 | } | |
903 | ||
904 | /* Helper functions for getting the float arguments right. Registers usage | |
405feb71 | 905 | depends on the ABI and the endianness. The comments should enlighten how |
c378eb4e | 906 | it's intended to work. */ |
e5e33cd9 | 907 | |
c378eb4e | 908 | /* This array stores which of the float arg registers are already in use. */ |
e5e33cd9 CV |
909 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; |
910 | ||
c378eb4e | 911 | /* This function just resets the above array to "no reg used so far". */ |
e5e33cd9 CV |
912 | static void |
913 | sh_init_flt_argreg (void) | |
914 | { | |
915 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
916 | } | |
917 | ||
918 | /* This function returns the next register to use for float arg passing. | |
919 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
920 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
921 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
922 | ||
923 | Note that register number 0 in flt_argreg_array corresponds with the | |
924 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
925 | 29) the parity of the register number is preserved, which is important | |
c378eb4e | 926 | for the double register passing test (see the "argreg & 1" test below). */ |
e5e33cd9 | 927 | static int |
c055b101 | 928 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
929 | { |
930 | int argreg; | |
931 | ||
c378eb4e | 932 | /* First search for the next free register. */ |
617daa0e CV |
933 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
934 | ++argreg) | |
e5e33cd9 CV |
935 | if (!flt_argreg_array[argreg]) |
936 | break; | |
937 | ||
c378eb4e | 938 | /* No register left? */ |
e5e33cd9 CV |
939 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
940 | return FLOAT_ARGLAST_REGNUM + 1; | |
941 | ||
942 | if (len == 8) | |
943 | { | |
c378eb4e | 944 | /* Doubles are always starting in a even register number. */ |
e5e33cd9 | 945 | if (argreg & 1) |
617daa0e | 946 | { |
c055b101 CV |
947 | /* In gcc ABI, the skipped register is lost for further argument |
948 | passing now. Not so in Renesas ABI. */ | |
949 | if (!sh_is_renesas_calling_convention (func_type)) | |
950 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
951 | |
952 | ++argreg; | |
953 | ||
c378eb4e | 954 | /* No register left? */ |
e5e33cd9 CV |
955 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
956 | return FLOAT_ARGLAST_REGNUM + 1; | |
957 | } | |
c378eb4e | 958 | /* Also mark the next register as used. */ |
e5e33cd9 CV |
959 | flt_argreg_array[argreg + 1] = 1; |
960 | } | |
c055b101 CV |
961 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
962 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 | 963 | { |
c378eb4e | 964 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ |
e5e33cd9 CV |
965 | if (!flt_argreg_array[argreg + 1]) |
966 | ++argreg; | |
967 | } | |
968 | flt_argreg_array[argreg] = 1; | |
969 | return FLOAT_ARG0_REGNUM + argreg; | |
970 | } | |
971 | ||
afce3d2a CV |
972 | /* Helper function which figures out, if a type is treated like a float type. |
973 | ||
2e952408 | 974 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
975 | Structures with exactly one member, which is of type float or double, are |
976 | treated exactly as the base types float or double: | |
977 | ||
978 | struct sf { | |
979 | float f; | |
980 | }; | |
981 | ||
982 | struct sd { | |
983 | double d; | |
984 | }; | |
985 | ||
986 | are handled the same way as just | |
987 | ||
988 | float f; | |
989 | ||
990 | double d; | |
991 | ||
992 | As a result, arguments of these struct types are pushed into floating point | |
993 | registers exactly as floats or doubles, using the same decision algorithm. | |
994 | ||
995 | The same is valid if these types are used as function return types. The | |
996 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
997 | or even using struct convention as it is for other structs. */ | |
998 | ||
999 | static int | |
1000 | sh_treat_as_flt_p (struct type *type) | |
1001 | { | |
afce3d2a | 1002 | /* Ordinary float types are obviously treated as float. */ |
78134374 | 1003 | if (type->code () == TYPE_CODE_FLT) |
afce3d2a CV |
1004 | return 1; |
1005 | /* Otherwise non-struct types are not treated as float. */ | |
78134374 | 1006 | if (type->code () != TYPE_CODE_STRUCT) |
afce3d2a | 1007 | return 0; |
405feb71 | 1008 | /* Otherwise structs with more than one member are not treated as float. */ |
1f704f76 | 1009 | if (type->num_fields () != 1) |
afce3d2a CV |
1010 | return 0; |
1011 | /* Otherwise if the type of that member is float, the whole type is | |
1012 | treated as float. */ | |
940da03e | 1013 | if (type->field (0).type ()->code () == TYPE_CODE_FLT) |
afce3d2a CV |
1014 | return 1; |
1015 | /* Otherwise it's not treated as float. */ | |
1016 | return 0; | |
1017 | } | |
1018 | ||
cc17453a | 1019 | static CORE_ADDR |
617daa0e | 1020 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1021 | struct value *function, |
617daa0e | 1022 | struct regcache *regcache, |
6df2bf50 | 1023 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1024 | struct value **args, |
cf84fa6b | 1025 | CORE_ADDR sp, function_call_return_method return_method, |
6df2bf50 MS |
1026 | CORE_ADDR struct_addr) |
1027 | { | |
e17a4113 | 1028 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1029 | int stack_offset = 0; |
1030 | int argreg = ARG0_REGNUM; | |
8748518b | 1031 | int flt_argreg = 0; |
6df2bf50 | 1032 | int argnum; |
d0c97917 | 1033 | struct type *func_type = function->type (); |
6df2bf50 MS |
1034 | struct type *type; |
1035 | CORE_ADDR regval; | |
948f8e3d | 1036 | const gdb_byte *val; |
8748518b | 1037 | int len, reg_size = 0; |
afce3d2a CV |
1038 | int pass_on_stack = 0; |
1039 | int treat_as_flt; | |
c055b101 CV |
1040 | int last_reg_arg = INT_MAX; |
1041 | ||
1042 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1043 | non-vararg argument to be on the stack, no matter how many | |
1044 | registers have been used so far. */ | |
1045 | if (sh_is_renesas_calling_convention (func_type) | |
a409645d | 1046 | && func_type->has_varargs ()) |
1f704f76 | 1047 | last_reg_arg = func_type->num_fields () - 2; |
6df2bf50 | 1048 | |
c378eb4e | 1049 | /* First force sp to a 4-byte alignment. */ |
6df2bf50 MS |
1050 | sp = sh_frame_align (gdbarch, sp); |
1051 | ||
c378eb4e | 1052 | /* Make room on stack for args. */ |
e5e33cd9 CV |
1053 | sp -= sh_stack_allocsize (nargs, args); |
1054 | ||
c378eb4e | 1055 | /* Initialize float argument mechanism. */ |
e5e33cd9 | 1056 | sh_init_flt_argreg (); |
6df2bf50 MS |
1057 | |
1058 | /* Now load as many as possible of the first arguments into | |
1059 | registers, and push the rest onto the stack. There are 16 bytes | |
1060 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1061 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1062 | { |
d0c97917 | 1063 | type = args[argnum]->type (); |
df86565b | 1064 | len = type->length (); |
d93859e2 | 1065 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1066 | |
1067 | /* Some decisions have to be made how various types are handled. | |
dda83cd7 | 1068 | This also differs in different ABIs. */ |
e5e33cd9 | 1069 | pass_on_stack = 0; |
e5e33cd9 | 1070 | |
c378eb4e | 1071 | /* Find out the next register to use for a floating point value. */ |
afce3d2a CV |
1072 | treat_as_flt = sh_treat_as_flt_p (type); |
1073 | if (treat_as_flt) | |
c055b101 CV |
1074 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1075 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1076 | on stack. */ | |
1077 | else if (sh_is_renesas_calling_convention (func_type) | |
78134374 SM |
1078 | && ((type->code () == TYPE_CODE_INT && len == 8) |
1079 | || type->code () == TYPE_CODE_STRUCT | |
1080 | || type->code () == TYPE_CODE_UNION)) | |
c055b101 | 1081 | pass_on_stack = 1; |
afce3d2a CV |
1082 | /* In contrast to non-FPU CPUs, arguments are never split between |
1083 | registers and stack. If an argument doesn't fit in the remaining | |
1084 | registers it's always pushed entirely on the stack. */ | |
1085 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1086 | pass_on_stack = 1; | |
48db5a3c | 1087 | |
6df2bf50 MS |
1088 | while (len > 0) |
1089 | { | |
afce3d2a CV |
1090 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1091 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
dda83cd7 | 1092 | || pass_on_stack)) |
c055b101 | 1093 | || argnum > last_reg_arg) |
617daa0e | 1094 | { |
c378eb4e | 1095 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1096 | reg_size = (len + 3) & ~3; |
1097 | write_memory (sp + stack_offset, val, reg_size); | |
1098 | stack_offset += reg_size; | |
6df2bf50 | 1099 | } |
afce3d2a | 1100 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1101 | { |
e5e33cd9 CV |
1102 | /* Argument goes in a float argument register. */ |
1103 | reg_size = register_size (gdbarch, flt_argreg); | |
e17a4113 | 1104 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
2e952408 | 1105 | /* In little endian mode, float types taking two registers |
dda83cd7 | 1106 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must |
2e952408 CV |
1107 | be stored swapped in the argument registers. The below |
1108 | code first writes the first 32 bits in the next but one | |
1109 | register, increments the val and len values accordingly | |
1110 | and then proceeds as normal by writing the second 32 bits | |
c378eb4e | 1111 | into the next register. */ |
b47193f7 | 1112 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
df86565b | 1113 | && type->length () == 2 * reg_size) |
dda83cd7 | 1114 | { |
2e952408 CV |
1115 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, |
1116 | regval); | |
1117 | val += reg_size; | |
1118 | len -= reg_size; | |
c378eb4e MS |
1119 | regval = extract_unsigned_integer (val, reg_size, |
1120 | byte_order); | |
2e952408 | 1121 | } |
6df2bf50 MS |
1122 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1123 | } | |
afce3d2a | 1124 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1125 | { |
6df2bf50 | 1126 | /* there's room in a register */ |
e5e33cd9 | 1127 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1128 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
6df2bf50 MS |
1129 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1130 | } | |
c378eb4e MS |
1131 | /* Store the value one register at a time or in one step on |
1132 | stack. */ | |
e5e33cd9 CV |
1133 | len -= reg_size; |
1134 | val += reg_size; | |
6df2bf50 MS |
1135 | } |
1136 | } | |
1137 | ||
cf84fa6b | 1138 | if (return_method == return_method_struct) |
c055b101 CV |
1139 | { |
1140 | if (sh_is_renesas_calling_convention (func_type)) | |
1141 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1142 | the stack and store the struct return address there. */ | |
e17a4113 | 1143 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1144 | else |
1145 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1146 | its own dedicated register. */ | |
1147 | regcache_cooked_write_unsigned (regcache, | |
1148 | STRUCT_RETURN_REGNUM, struct_addr); | |
1149 | } | |
1150 | ||
c378eb4e | 1151 | /* Store return address. */ |
55ff77ac | 1152 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1153 | |
1154 | /* Update stack pointer. */ | |
3e8c568d | 1155 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1156 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1157 | |
1158 | return sp; | |
1159 | } | |
1160 | ||
1161 | static CORE_ADDR | |
617daa0e | 1162 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1163 | struct value *function, |
617daa0e CV |
1164 | struct regcache *regcache, |
1165 | CORE_ADDR bp_addr, | |
1166 | int nargs, struct value **args, | |
cf84fa6b AH |
1167 | CORE_ADDR sp, |
1168 | function_call_return_method return_method, | |
6df2bf50 | 1169 | CORE_ADDR struct_addr) |
c906108c | 1170 | { |
e17a4113 | 1171 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1172 | int stack_offset = 0; |
1173 | int argreg = ARG0_REGNUM; | |
c906108c | 1174 | int argnum; |
d0c97917 | 1175 | struct type *func_type = function->type (); |
c906108c SS |
1176 | struct type *type; |
1177 | CORE_ADDR regval; | |
948f8e3d | 1178 | const gdb_byte *val; |
c055b101 CV |
1179 | int len, reg_size = 0; |
1180 | int pass_on_stack = 0; | |
1181 | int last_reg_arg = INT_MAX; | |
1182 | ||
1183 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1184 | non-vararg argument to be on the stack, no matter how many | |
1185 | registers have been used so far. */ | |
1186 | if (sh_is_renesas_calling_convention (func_type) | |
a409645d | 1187 | && func_type->has_varargs ()) |
1f704f76 | 1188 | last_reg_arg = func_type->num_fields () - 2; |
c906108c | 1189 | |
c378eb4e | 1190 | /* First force sp to a 4-byte alignment. */ |
19f59343 | 1191 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1192 | |
c378eb4e | 1193 | /* Make room on stack for args. */ |
e5e33cd9 | 1194 | sp -= sh_stack_allocsize (nargs, args); |
c906108c | 1195 | |
c906108c SS |
1196 | /* Now load as many as possible of the first arguments into |
1197 | registers, and push the rest onto the stack. There are 16 bytes | |
1198 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1199 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1200 | { |
d0c97917 | 1201 | type = args[argnum]->type (); |
df86565b | 1202 | len = type->length (); |
d93859e2 | 1203 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1204 | |
c055b101 | 1205 | /* Some decisions have to be made how various types are handled. |
c378eb4e | 1206 | This also differs in different ABIs. */ |
c055b101 CV |
1207 | pass_on_stack = 0; |
1208 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1209 | Same goes for aggregate types. */ | |
1210 | if (sh_is_renesas_calling_convention (func_type) | |
78134374 SM |
1211 | && ((type->code () == TYPE_CODE_INT && len >= 8) |
1212 | || (type->code () == TYPE_CODE_FLT && len >= 8) | |
1213 | || type->code () == TYPE_CODE_STRUCT | |
1214 | || type->code () == TYPE_CODE_UNION)) | |
c055b101 | 1215 | pass_on_stack = 1; |
c906108c SS |
1216 | while (len > 0) |
1217 | { | |
c055b101 CV |
1218 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1219 | || argnum > last_reg_arg) | |
617daa0e | 1220 | { |
e5e33cd9 | 1221 | /* The remainder of the data goes entirely on the stack, |
dda83cd7 | 1222 | 4-byte aligned. */ |
e5e33cd9 CV |
1223 | reg_size = (len + 3) & ~3; |
1224 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1225 | stack_offset += reg_size; |
c906108c | 1226 | } |
e5e33cd9 | 1227 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1228 | { |
c378eb4e | 1229 | /* There's room in a register. */ |
e5e33cd9 | 1230 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1231 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
48db5a3c | 1232 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1233 | } |
e5e33cd9 CV |
1234 | /* Store the value reg_size bytes at a time. This means that things |
1235 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1236 | on the stack. */ |
e5e33cd9 CV |
1237 | len -= reg_size; |
1238 | val += reg_size; | |
c906108c SS |
1239 | } |
1240 | } | |
48db5a3c | 1241 | |
cf84fa6b | 1242 | if (return_method == return_method_struct) |
c055b101 CV |
1243 | { |
1244 | if (sh_is_renesas_calling_convention (func_type)) | |
1245 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1246 | the stack and store the struct return address there. */ | |
e17a4113 | 1247 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1248 | else |
1249 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1250 | its own dedicated register. */ | |
1251 | regcache_cooked_write_unsigned (regcache, | |
1252 | STRUCT_RETURN_REGNUM, struct_addr); | |
1253 | } | |
1254 | ||
c378eb4e | 1255 | /* Store return address. */ |
55ff77ac | 1256 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1257 | |
1258 | /* Update stack pointer. */ | |
3e8c568d | 1259 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1260 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1261 | |
c906108c SS |
1262 | return sp; |
1263 | } | |
1264 | ||
cc17453a EZ |
1265 | /* Find a function's return value in the appropriate registers (in |
1266 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1267 | containing the (raw) register state a function return value of type | |
1268 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1269 | static void | |
3ffc5b9b | 1270 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1271 | gdb_byte *valbuf) |
c906108c | 1272 | { |
ac7936df | 1273 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1274 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
df86565b | 1275 | int len = type->length (); |
617daa0e | 1276 | |
cc17453a | 1277 | if (len <= 4) |
3116c80a | 1278 | { |
48db5a3c CV |
1279 | ULONGEST c; |
1280 | ||
1281 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
e17a4113 | 1282 | store_unsigned_integer (valbuf, len, byte_order, c); |
3116c80a | 1283 | } |
48db5a3c | 1284 | else if (len == 8) |
3116c80a | 1285 | { |
48db5a3c CV |
1286 | int i, regnum = R0_REGNUM; |
1287 | for (i = 0; i < len; i += 4) | |
0b883586 | 1288 | regcache->raw_read (regnum++, valbuf + i); |
3116c80a EZ |
1289 | } |
1290 | else | |
8a3fe4f8 | 1291 | error (_("bad size for return value")); |
3116c80a EZ |
1292 | } |
1293 | ||
1294 | static void | |
3ffc5b9b | 1295 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1296 | gdb_byte *valbuf) |
3116c80a | 1297 | { |
ac7936df | 1298 | struct gdbarch *gdbarch = regcache->arch (); |
afce3d2a | 1299 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1300 | { |
df86565b | 1301 | int len = type->length (); |
d93859e2 | 1302 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1303 | for (i = 0; i < len; i += 4) |
d93859e2 | 1304 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
0b883586 | 1305 | regcache->raw_read (regnum++, |
948f8e3d | 1306 | valbuf + len - 4 - i); |
2e952408 | 1307 | else |
0b883586 | 1308 | regcache->raw_read (regnum++, valbuf + i); |
3116c80a | 1309 | } |
cc17453a | 1310 | else |
3ffc5b9b | 1311 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1312 | } |
c906108c | 1313 | |
cc17453a EZ |
1314 | /* Write into appropriate registers a function return value |
1315 | of type TYPE, given in virtual format. | |
1316 | If the architecture is sh4 or sh3e, store a function's return value | |
1317 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e MS |
1318 | depending on the type of the return value. In all the other cases |
1319 | the result is stored in r0, left-justified. */ | |
cc17453a | 1320 | static void |
3ffc5b9b | 1321 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1322 | const gdb_byte *valbuf) |
cc17453a | 1323 | { |
ac7936df | 1324 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1325 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
48db5a3c | 1326 | ULONGEST val; |
df86565b | 1327 | int len = type->length (); |
d19b71be | 1328 | |
48db5a3c | 1329 | if (len <= 4) |
d19b71be | 1330 | { |
e17a4113 | 1331 | val = extract_unsigned_integer (valbuf, len, byte_order); |
48db5a3c | 1332 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); |
d19b71be MS |
1333 | } |
1334 | else | |
48db5a3c CV |
1335 | { |
1336 | int i, regnum = R0_REGNUM; | |
1337 | for (i = 0; i < len; i += 4) | |
10eaee5f | 1338 | regcache->raw_write (regnum++, valbuf + i); |
48db5a3c | 1339 | } |
cc17453a | 1340 | } |
c906108c | 1341 | |
cc17453a | 1342 | static void |
3ffc5b9b | 1343 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1344 | const gdb_byte *valbuf) |
cc17453a | 1345 | { |
ac7936df | 1346 | struct gdbarch *gdbarch = regcache->arch (); |
afce3d2a | 1347 | if (sh_treat_as_flt_p (type)) |
48db5a3c | 1348 | { |
df86565b | 1349 | int len = type->length (); |
d93859e2 | 1350 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1351 | for (i = 0; i < len; i += 4) |
d93859e2 | 1352 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
10eaee5f | 1353 | regcache->raw_write (regnum++, |
948f8e3d | 1354 | valbuf + len - 4 - i); |
c8a3b559 | 1355 | else |
10eaee5f | 1356 | regcache->raw_write (regnum++, valbuf + i); |
48db5a3c | 1357 | } |
cc17453a | 1358 | else |
3ffc5b9b | 1359 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1360 | } |
1361 | ||
c0409442 | 1362 | static enum return_value_convention |
6a3a010b | 1363 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1364 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1365 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1366 | { |
d0c97917 | 1367 | struct type *func_type = function ? function->type () : NULL; |
6a3a010b | 1368 | |
24b21115 SM |
1369 | if (sh_use_struct_convention_nofpu |
1370 | (sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1371 | return RETURN_VALUE_STRUCT_CONVENTION; |
1372 | if (writebuf) | |
3ffc5b9b | 1373 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1374 | else if (readbuf) |
3ffc5b9b | 1375 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1376 | return RETURN_VALUE_REGISTER_CONVENTION; |
1377 | } | |
1378 | ||
1379 | static enum return_value_convention | |
6a3a010b | 1380 | sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1381 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1382 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1383 | { |
d0c97917 | 1384 | struct type *func_type = function ? function->type () : NULL; |
6a3a010b | 1385 | |
c055b101 CV |
1386 | if (sh_use_struct_convention ( |
1387 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1388 | return RETURN_VALUE_STRUCT_CONVENTION; |
1389 | if (writebuf) | |
3ffc5b9b | 1390 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1391 | else if (readbuf) |
3ffc5b9b | 1392 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1393 | return RETURN_VALUE_REGISTER_CONVENTION; |
1394 | } | |
1395 | ||
da962468 CV |
1396 | static struct type * |
1397 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1398 | { | |
b47193f7 | 1399 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 | 1400 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1401 | return builtin_type (gdbarch)->builtin_float; |
da962468 | 1402 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1403 | return builtin_type (gdbarch)->builtin_double; |
afdd600c SM |
1404 | else if (reg_nr == PC_REGNUM || reg_nr == PR_REGNUM || reg_nr == VBR_REGNUM |
1405 | || reg_nr == SPC_REGNUM) | |
1406 | return builtin_type (gdbarch)->builtin_func_ptr; | |
1407 | else if (reg_nr == R0_REGNUM + 15 || reg_nr == GBR_REGNUM) | |
1408 | return builtin_type (gdbarch)->builtin_data_ptr; | |
da962468 | 1409 | else |
0dfff4cb | 1410 | return builtin_type (gdbarch)->builtin_int; |
da962468 CV |
1411 | } |
1412 | ||
cc17453a EZ |
1413 | /* Return the GDB type object for the "standard" data type |
1414 | of data in register N. */ | |
cc17453a | 1415 | static struct type * |
48db5a3c | 1416 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1417 | { |
b47193f7 | 1418 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1419 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1420 | return builtin_type (gdbarch)->builtin_float; |
afdd600c SM |
1421 | else if (reg_nr == PC_REGNUM || reg_nr == PR_REGNUM || reg_nr == VBR_REGNUM |
1422 | || reg_nr == SPC_REGNUM) | |
1423 | return builtin_type (gdbarch)->builtin_func_ptr; | |
1424 | else if (reg_nr == R0_REGNUM + 15 || reg_nr == GBR_REGNUM) | |
1425 | return builtin_type (gdbarch)->builtin_data_ptr; | |
8db62801 | 1426 | else |
0dfff4cb | 1427 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1428 | } |
1429 | ||
7f4dbe94 | 1430 | static struct type * |
0dfff4cb | 1431 | sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) |
7f4dbe94 | 1432 | { |
e3506a9f UW |
1433 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1434 | 0, high); | |
7f4dbe94 EZ |
1435 | } |
1436 | ||
53116e27 | 1437 | static struct type * |
48db5a3c | 1438 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 1439 | { |
b47193f7 | 1440 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1441 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1442 | return builtin_type (gdbarch)->builtin_float; |
617daa0e | 1443 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1444 | return builtin_type (gdbarch)->builtin_double; |
617daa0e | 1445 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
0dfff4cb | 1446 | return sh_sh4_build_float_register_type (gdbarch, 3); |
afdd600c SM |
1447 | else if (reg_nr == PC_REGNUM || reg_nr == PR_REGNUM || reg_nr == VBR_REGNUM |
1448 | || reg_nr == SPC_REGNUM) | |
1449 | return builtin_type (gdbarch)->builtin_func_ptr; | |
1450 | else if (reg_nr == R0_REGNUM + 15 || reg_nr == GBR_REGNUM) | |
1451 | return builtin_type (gdbarch)->builtin_data_ptr; | |
53116e27 | 1452 | else |
0dfff4cb | 1453 | return builtin_type (gdbarch)->builtin_int; |
53116e27 EZ |
1454 | } |
1455 | ||
cc17453a | 1456 | static struct type * |
48db5a3c | 1457 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1458 | { |
afdd600c SM |
1459 | if (reg_nr == PC_REGNUM || reg_nr == PR_REGNUM || reg_nr == VBR_REGNUM |
1460 | || reg_nr == SPC_REGNUM) | |
1461 | return builtin_type (gdbarch)->builtin_func_ptr; | |
1462 | else if (reg_nr == R0_REGNUM + 15 || reg_nr == GBR_REGNUM) | |
1463 | return builtin_type (gdbarch)->builtin_data_ptr; | |
1464 | else | |
1465 | return builtin_type (gdbarch)->builtin_int; | |
cc17453a EZ |
1466 | } |
1467 | ||
dda63807 AS |
1468 | /* Is a register in a reggroup? |
1469 | The default code in reggroup.c doesn't identify system registers, some | |
1470 | float registers or any of the vector registers. | |
1471 | TODO: sh2a and dsp registers. */ | |
63807e1d | 1472 | static int |
dda63807 | 1473 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
dbf5d61b | 1474 | const struct reggroup *reggroup) |
dda63807 | 1475 | { |
637b2f86 | 1476 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
dda63807 AS |
1477 | return 0; |
1478 | ||
1479 | if (reggroup == float_reggroup | |
1480 | && (regnum == FPUL_REGNUM | |
1481 | || regnum == FPSCR_REGNUM)) | |
1482 | return 1; | |
1483 | ||
1484 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
1485 | { | |
1486 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
1487 | return 1; | |
1488 | if (reggroup == general_reggroup) | |
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | if (regnum == VBR_REGNUM | |
1493 | || regnum == SR_REGNUM | |
1494 | || regnum == FPSCR_REGNUM | |
1495 | || regnum == SSR_REGNUM | |
1496 | || regnum == SPC_REGNUM) | |
1497 | { | |
1498 | if (reggroup == system_reggroup) | |
1499 | return 1; | |
1500 | if (reggroup == general_reggroup) | |
1501 | return 0; | |
1502 | } | |
1503 | ||
1504 | /* The default code can cope with any other registers. */ | |
1505 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1506 | } | |
1507 | ||
fb409745 | 1508 | /* On the sh4, the DRi pseudo registers are problematic if the target |
c378eb4e | 1509 | is little endian. When the user writes one of those registers, for |
a6521d9a | 1510 | instance with 'set var $dr0=1', we want the double to be stored |
fb409745 | 1511 | like this: |
a6521d9a TS |
1512 | fr0 = 0x00 0x00 0xf0 0x3f |
1513 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1514 | |
1515 | This corresponds to little endian byte order & big endian word | |
1516 | order. However if we let gdb write the register w/o conversion, it | |
1517 | will write fr0 and fr1 this way: | |
a6521d9a TS |
1518 | fr0 = 0x00 0x00 0x00 0x00 |
1519 | fr1 = 0x00 0x00 0xf0 0x3f | |
fb409745 EZ |
1520 | because it will consider fr0 and fr1 as a single LE stretch of memory. |
1521 | ||
1522 | To achieve what we want we must force gdb to store things in | |
1523 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1524 | include/floatformat.h and libiberty/floatformat.c. | |
1525 | ||
1526 | In case the target is big endian, there is no problem, the | |
1527 | raw bytes will look like: | |
a6521d9a TS |
1528 | fr0 = 0x3f 0xf0 0x00 0x00 |
1529 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1530 | |
1531 | The other pseudo registers (the FVs) also don't pose a problem | |
c378eb4e | 1532 | because they are stored as 4 individual FP elements. */ |
fb409745 | 1533 | |
96a5a1d3 UW |
1534 | static struct type * |
1535 | sh_littlebyte_bigword_type (struct gdbarch *gdbarch) | |
1536 | { | |
08106042 | 1537 | sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); |
96a5a1d3 UW |
1538 | |
1539 | if (tdep->sh_littlebyte_bigword_type == NULL) | |
77c5f496 TT |
1540 | { |
1541 | type_allocator alloc (gdbarch); | |
1542 | tdep->sh_littlebyte_bigword_type | |
1543 | = init_float_type (alloc, -1, "builtin_type_sh_littlebyte_bigword", | |
1544 | floatformats_ieee_double_littlebyte_bigword); | |
1545 | } | |
96a5a1d3 UW |
1546 | |
1547 | return tdep->sh_littlebyte_bigword_type; | |
1548 | } | |
1549 | ||
7bd872fe | 1550 | static void |
a6521d9a | 1551 | sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1552 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1553 | { |
a6521d9a TS |
1554 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1555 | { | |
1556 | /* It is a no-op. */ | |
1557 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1558 | return; | |
1559 | } | |
1560 | ||
617daa0e | 1561 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
3b2ca824 UW |
1562 | target_float_convert (from, sh_littlebyte_bigword_type (gdbarch), |
1563 | to, type); | |
283150cd | 1564 | else |
617daa0e CV |
1565 | error |
1566 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1567 | } |
1568 | ||
1569 | static void | |
a6521d9a | 1570 | sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
948f8e3d | 1571 | int regnum, const gdb_byte *from, gdb_byte *to) |
283150cd | 1572 | { |
a6521d9a TS |
1573 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1574 | { | |
1575 | /* It is a no-op. */ | |
1576 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1577 | return; | |
1578 | } | |
1579 | ||
617daa0e | 1580 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
3b2ca824 UW |
1581 | target_float_convert (from, type, |
1582 | to, sh_littlebyte_bigword_type (gdbarch)); | |
283150cd | 1583 | else |
8a3fe4f8 | 1584 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
1585 | } |
1586 | ||
c378eb4e | 1587 | /* For vectors of 4 floating point registers. */ |
1c0159e0 | 1588 | static int |
d93859e2 | 1589 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
1590 | { |
1591 | int fp_regnum; | |
1592 | ||
d93859e2 | 1593 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1594 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1595 | return fp_regnum; |
1596 | } | |
1597 | ||
c378eb4e | 1598 | /* For double precision floating point registers, i.e 2 fp regs. */ |
1c0159e0 | 1599 | static int |
d93859e2 | 1600 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
1601 | { |
1602 | int fp_regnum; | |
1603 | ||
d93859e2 | 1604 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1605 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1606 | return fp_regnum; |
1607 | } | |
1608 | ||
05d1431c PA |
1609 | /* Concatenate PORTIONS contiguous raw registers starting at |
1610 | BASE_REGNUM into BUFFER. */ | |
1611 | ||
1612 | static enum register_status | |
1613 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
849d0ba8 | 1614 | readable_regcache *regcache, |
05d1431c PA |
1615 | int portions, |
1616 | int base_regnum, gdb_byte *buffer) | |
1617 | { | |
1618 | int portion; | |
1619 | ||
1620 | for (portion = 0; portion < portions; portion++) | |
1621 | { | |
1622 | enum register_status status; | |
1623 | gdb_byte *b; | |
1624 | ||
1625 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
03f50fc8 | 1626 | status = regcache->raw_read (base_regnum + portion, b); |
05d1431c PA |
1627 | if (status != REG_VALID) |
1628 | return status; | |
1629 | } | |
1630 | ||
1631 | return REG_VALID; | |
1632 | } | |
1633 | ||
1634 | static enum register_status | |
849d0ba8 | 1635 | sh_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
18cf8b5b | 1636 | int reg_nr, gdb_byte *buffer) |
53116e27 | 1637 | { |
05d1431c | 1638 | int base_regnum; |
05d1431c | 1639 | enum register_status status; |
53116e27 | 1640 | |
9bed62d7 | 1641 | if (reg_nr == PSEUDO_BANK_REGNUM) |
03f50fc8 | 1642 | return regcache->raw_read (BANK_REGNUM, buffer); |
05d1431c | 1643 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
7bd872fe | 1644 | { |
4a8a33c8 AH |
1645 | /* Enough space for two float registers. */ |
1646 | gdb_byte temp_buffer[4 * 2]; | |
d93859e2 | 1647 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 1648 | |
c378eb4e | 1649 | /* Build the value in the provided buffer. */ |
7bd872fe | 1650 | /* Read the real regs for which this one is an alias. */ |
05d1431c PA |
1651 | status = pseudo_register_read_portions (gdbarch, regcache, |
1652 | 2, base_regnum, temp_buffer); | |
1653 | if (status == REG_VALID) | |
1654 | { | |
405feb71 | 1655 | /* We must pay attention to the endianness. */ |
a6521d9a | 1656 | sh_register_convert_to_virtual (gdbarch, reg_nr, |
05d1431c PA |
1657 | register_type (gdbarch, reg_nr), |
1658 | temp_buffer, buffer); | |
1659 | } | |
1660 | return status; | |
7bd872fe | 1661 | } |
617daa0e | 1662 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1663 | { |
d93859e2 | 1664 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
1665 | |
1666 | /* Read the real regs for which this one is an alias. */ | |
05d1431c PA |
1667 | return pseudo_register_read_portions (gdbarch, regcache, |
1668 | 4, base_regnum, buffer); | |
53116e27 | 1669 | } |
05d1431c PA |
1670 | else |
1671 | gdb_assert_not_reached ("invalid pseudo register number"); | |
53116e27 EZ |
1672 | } |
1673 | ||
a78f21af | 1674 | static void |
d8124050 | 1675 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1676 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
1677 | { |
1678 | int base_regnum, portion; | |
1679 | ||
9bed62d7 CV |
1680 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1681 | { | |
1682 | /* When the bank register is written to, the whole register bank | |
dda83cd7 | 1683 | is switched and all values in the bank registers must be read |
c378eb4e | 1684 | from the target/sim again. We're just invalidating the regcache |
9bed62d7 CV |
1685 | so that a re-read happens next time it's necessary. */ |
1686 | int bregnum; | |
1687 | ||
10eaee5f | 1688 | regcache->raw_write (BANK_REGNUM, buffer); |
9bed62d7 | 1689 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) |
dda83cd7 | 1690 | regcache->invalidate (bregnum); |
9bed62d7 CV |
1691 | } |
1692 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 1693 | { |
4a8a33c8 AH |
1694 | /* Enough space for two float registers. */ |
1695 | gdb_byte temp_buffer[4 * 2]; | |
d93859e2 | 1696 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 1697 | |
405feb71 | 1698 | /* We must pay attention to the endianness. */ |
a6521d9a | 1699 | sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
b66ba949 | 1700 | reg_nr, buffer, temp_buffer); |
7bd872fe | 1701 | |
53116e27 EZ |
1702 | /* Write the real regs for which this one is an alias. */ |
1703 | for (portion = 0; portion < 2; portion++) | |
10eaee5f | 1704 | regcache->raw_write (base_regnum + portion, |
0818c12a | 1705 | (temp_buffer |
617daa0e CV |
1706 | + register_size (gdbarch, |
1707 | base_regnum) * portion)); | |
53116e27 | 1708 | } |
617daa0e | 1709 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1710 | { |
d93859e2 | 1711 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
1712 | |
1713 | /* Write the real regs for which this one is an alias. */ | |
1714 | for (portion = 0; portion < 4; portion++) | |
10eaee5f | 1715 | regcache->raw_write (base_regnum + portion, |
948f8e3d | 1716 | (buffer |
617daa0e CV |
1717 | + register_size (gdbarch, |
1718 | base_regnum) * portion)); | |
53116e27 EZ |
1719 | } |
1720 | } | |
1721 | ||
2f14585c | 1722 | static int |
e7faf938 | 1723 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 1724 | { |
e7faf938 MD |
1725 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
1726 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
1727 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
1728 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
1729 | if (nr == MOD_REGNUM) | |
2f14585c | 1730 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 1731 | if (nr == RS_REGNUM) |
2f14585c | 1732 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 1733 | if (nr == RE_REGNUM) |
2f14585c | 1734 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
1735 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
1736 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
1737 | return nr; |
1738 | } | |
1c0159e0 | 1739 | |
da962468 | 1740 | static int |
e7faf938 | 1741 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
1742 | { |
1743 | switch (nr) | |
1744 | { | |
1745 | case TBR_REGNUM: | |
dda83cd7 | 1746 | return SIM_SH_TBR_REGNUM; |
da962468 | 1747 | case IBNR_REGNUM: |
dda83cd7 | 1748 | return SIM_SH_IBNR_REGNUM; |
da962468 | 1749 | case IBCR_REGNUM: |
dda83cd7 | 1750 | return SIM_SH_IBCR_REGNUM; |
da962468 | 1751 | case BANK_REGNUM: |
dda83cd7 | 1752 | return SIM_SH_BANK_REGNUM; |
da962468 | 1753 | case MACLB_REGNUM: |
dda83cd7 | 1754 | return SIM_SH_BANK_MACL_REGNUM; |
da962468 | 1755 | case GBRB_REGNUM: |
dda83cd7 | 1756 | return SIM_SH_BANK_GBR_REGNUM; |
da962468 | 1757 | case PRB_REGNUM: |
dda83cd7 | 1758 | return SIM_SH_BANK_PR_REGNUM; |
da962468 | 1759 | case IVNB_REGNUM: |
dda83cd7 | 1760 | return SIM_SH_BANK_IVN_REGNUM; |
da962468 | 1761 | case MACHB_REGNUM: |
dda83cd7 | 1762 | return SIM_SH_BANK_MACH_REGNUM; |
da962468 | 1763 | default: |
dda83cd7 | 1764 | break; |
da962468 | 1765 | } |
e7faf938 | 1766 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
1767 | } |
1768 | ||
357d3800 AS |
1769 | /* Set up the register unwinding such that call-clobbered registers are |
1770 | not displayed in frames >0 because the true value is not certain. | |
1771 | The 'undefined' registers will show up as 'not available' unless the | |
1772 | CFI says otherwise. | |
1773 | ||
1774 | This function is currently set up for SH4 and compatible only. */ | |
1775 | ||
1776 | static void | |
1777 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
dda83cd7 | 1778 | struct dwarf2_frame_state_reg *reg, |
8480a37e | 1779 | const frame_info_ptr &this_frame) |
357d3800 AS |
1780 | { |
1781 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 1782 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
1783 | reg->how = DWARF2_FRAME_REG_RA; |
1784 | ||
1785 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 1786 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
1787 | reg->how = DWARF2_FRAME_REG_CFA; |
1788 | ||
1789 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
1790 | while the below is SH specific. */ | |
1791 | ||
1792 | /* Caller save registers. */ | |
1793 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
1794 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
1795 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
1796 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
1797 | || (regnum == MACH_REGNUM) | |
1798 | || (regnum == MACL_REGNUM) | |
1799 | || (regnum == FPUL_REGNUM) | |
1800 | || (regnum == SR_REGNUM)) | |
1801 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1802 | ||
1803 | /* Callee save registers. */ | |
1804 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
1805 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
1806 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
1807 | || (regnum == FV0_REGNUM+3)) | |
1808 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1809 | ||
1810 | /* Other registers. These are not in the ABI and may or may not | |
1811 | mean anything in frames >0 so don't show them. */ | |
1812 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
1813 | || (regnum == GBR_REGNUM) | |
1814 | || (regnum == VBR_REGNUM) | |
1815 | || (regnum == FPSCR_REGNUM) | |
1816 | || (regnum == SSR_REGNUM) | |
1817 | || (regnum == SPC_REGNUM)) | |
1818 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1819 | } | |
1820 | ||
1c0159e0 CV |
1821 | static struct sh_frame_cache * |
1822 | sh_alloc_frame_cache (void) | |
1823 | { | |
1824 | struct sh_frame_cache *cache; | |
1825 | int i; | |
1826 | ||
1827 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
1828 | ||
1829 | /* Base address. */ | |
1830 | cache->base = 0; | |
1831 | cache->saved_sp = 0; | |
1832 | cache->sp_offset = 0; | |
1833 | cache->pc = 0; | |
1834 | ||
1835 | /* Frameless until proven otherwise. */ | |
1836 | cache->uses_fp = 0; | |
617daa0e | 1837 | |
1c0159e0 CV |
1838 | /* Saved registers. We initialize these to -1 since zero is a valid |
1839 | offset (that's where fp is supposed to be stored). */ | |
1840 | for (i = 0; i < SH_NUM_REGS; i++) | |
1841 | { | |
1842 | cache->saved_regs[i] = -1; | |
1843 | } | |
617daa0e | 1844 | |
1c0159e0 | 1845 | return cache; |
617daa0e | 1846 | } |
1c0159e0 CV |
1847 | |
1848 | static struct sh_frame_cache * | |
8480a37e | 1849 | sh_frame_cache (const frame_info_ptr &this_frame, void **this_cache) |
1c0159e0 | 1850 | { |
e17a4113 | 1851 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1c0159e0 CV |
1852 | struct sh_frame_cache *cache; |
1853 | CORE_ADDR current_pc; | |
1854 | int i; | |
1855 | ||
1856 | if (*this_cache) | |
19ba03f4 | 1857 | return (struct sh_frame_cache *) *this_cache; |
1c0159e0 CV |
1858 | |
1859 | cache = sh_alloc_frame_cache (); | |
1860 | *this_cache = cache; | |
1861 | ||
1862 | /* In principle, for normal frames, fp holds the frame pointer, | |
1863 | which holds the base address for the current stack frame. | |
1864 | However, for functions that don't need it, the frame pointer is | |
1865 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 1866 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 1867 | cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); |
1c0159e0 CV |
1868 | if (cache->base == 0) |
1869 | return cache; | |
1870 | ||
94afd7a6 UW |
1871 | cache->pc = get_frame_func (this_frame); |
1872 | current_pc = get_frame_pc (this_frame); | |
1c0159e0 | 1873 | if (cache->pc != 0) |
d2ca4222 UW |
1874 | { |
1875 | ULONGEST fpscr; | |
9fc05685 KB |
1876 | |
1877 | /* Check for the existence of the FPSCR register. If it exists, | |
1878 | fetch its value for use in prologue analysis. Passing a zero | |
1879 | value is the best choice for architecture variants upon which | |
1880 | there's no FPSCR register. */ | |
1881 | if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) | |
1882 | fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); | |
1883 | else | |
1884 | fpscr = 0; | |
1885 | ||
e17a4113 | 1886 | sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); |
d2ca4222 | 1887 | } |
617daa0e | 1888 | |
1c0159e0 CV |
1889 | if (!cache->uses_fp) |
1890 | { | |
1891 | /* We didn't find a valid frame, which means that CACHE->base | |
dda83cd7 SM |
1892 | currently holds the frame pointer for our calling frame. If |
1893 | we're at the start of a function, or somewhere half-way its | |
1894 | prologue, the function's frame probably hasn't been fully | |
1895 | setup yet. Try to reconstruct the base address for the stack | |
1896 | frame by looking at the stack pointer. For truly "frameless" | |
1897 | functions this might work too. */ | |
94afd7a6 | 1898 | cache->base = get_frame_register_unsigned |
e17a4113 | 1899 | (this_frame, gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1900 | } |
1901 | ||
1902 | /* Now that we have the base address for the stack frame we can | |
1903 | calculate the value of sp in the calling frame. */ | |
1904 | cache->saved_sp = cache->base + cache->sp_offset; | |
1905 | ||
1906 | /* Adjust all the saved registers such that they contain addresses | |
1907 | instead of offsets. */ | |
1908 | for (i = 0; i < SH_NUM_REGS; i++) | |
1909 | if (cache->saved_regs[i] != -1) | |
1910 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
1911 | ||
1912 | return cache; | |
1913 | } | |
1914 | ||
94afd7a6 | 1915 | static struct value * |
8480a37e | 1916 | sh_frame_prev_register (const frame_info_ptr &this_frame, |
94afd7a6 | 1917 | void **this_cache, int regnum) |
1c0159e0 | 1918 | { |
94afd7a6 UW |
1919 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1920 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); | |
1c0159e0 CV |
1921 | |
1922 | gdb_assert (regnum >= 0); | |
1923 | ||
b47193f7 | 1924 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 1925 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
1c0159e0 CV |
1926 | |
1927 | /* The PC of the previous frame is stored in the PR register of | |
1928 | the current frame. Frob regnum so that we pull the value from | |
1929 | the correct place. */ | |
b47193f7 | 1930 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
1931 | regnum = PR_REGNUM; |
1932 | ||
1933 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
94afd7a6 | 1934 | return frame_unwind_got_memory (this_frame, regnum, |
dda83cd7 | 1935 | cache->saved_regs[regnum]); |
1c0159e0 | 1936 | |
94afd7a6 | 1937 | return frame_unwind_got_register (this_frame, regnum, regnum); |
1c0159e0 CV |
1938 | } |
1939 | ||
1940 | static void | |
8480a37e | 1941 | sh_frame_this_id (const frame_info_ptr &this_frame, void **this_cache, |
617daa0e CV |
1942 | struct frame_id *this_id) |
1943 | { | |
94afd7a6 | 1944 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
1c0159e0 CV |
1945 | |
1946 | /* This marks the outermost frame. */ | |
1947 | if (cache->base == 0) | |
1948 | return; | |
1949 | ||
1950 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 1951 | } |
1c0159e0 | 1952 | |
617daa0e | 1953 | static const struct frame_unwind sh_frame_unwind = { |
a154d838 | 1954 | "sh prologue", |
1c0159e0 | 1955 | NORMAL_FRAME, |
8fbca658 | 1956 | default_frame_unwind_stop_reason, |
1c0159e0 | 1957 | sh_frame_this_id, |
94afd7a6 UW |
1958 | sh_frame_prev_register, |
1959 | NULL, | |
1960 | default_frame_sniffer | |
1c0159e0 CV |
1961 | }; |
1962 | ||
1c0159e0 | 1963 | static CORE_ADDR |
8480a37e | 1964 | sh_frame_base_address (const frame_info_ptr &this_frame, void **this_cache) |
617daa0e | 1965 | { |
94afd7a6 | 1966 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
617daa0e | 1967 | |
1c0159e0 CV |
1968 | return cache->base; |
1969 | } | |
617daa0e CV |
1970 | |
1971 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
1972 | &sh_frame_unwind, |
1973 | sh_frame_base_address, | |
1974 | sh_frame_base_address, | |
1975 | sh_frame_base_address | |
617daa0e | 1976 | }; |
1c0159e0 | 1977 | |
cb2cf4ce | 1978 | static struct sh_frame_cache * |
8480a37e | 1979 | sh_make_stub_cache (const frame_info_ptr &this_frame) |
cb2cf4ce TS |
1980 | { |
1981 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1982 | struct sh_frame_cache *cache; | |
1983 | ||
1984 | cache = sh_alloc_frame_cache (); | |
1985 | ||
1986 | cache->saved_sp | |
1987 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
1988 | ||
1989 | return cache; | |
1990 | } | |
1991 | ||
1992 | static void | |
8480a37e | 1993 | sh_stub_this_id (const frame_info_ptr &this_frame, void **this_cache, |
dda83cd7 | 1994 | struct frame_id *this_id) |
cb2cf4ce TS |
1995 | { |
1996 | struct sh_frame_cache *cache; | |
1997 | ||
1998 | if (*this_cache == NULL) | |
1999 | *this_cache = sh_make_stub_cache (this_frame); | |
19ba03f4 | 2000 | cache = (struct sh_frame_cache *) *this_cache; |
cb2cf4ce TS |
2001 | |
2002 | *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); | |
2003 | } | |
2004 | ||
2005 | static int | |
2006 | sh_stub_unwind_sniffer (const struct frame_unwind *self, | |
8480a37e | 2007 | const frame_info_ptr &this_frame, |
dda83cd7 | 2008 | void **this_prologue_cache) |
cb2cf4ce TS |
2009 | { |
2010 | CORE_ADDR addr_in_block; | |
2011 | ||
2012 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 2013 | if (in_plt_section (addr_in_block)) |
cb2cf4ce TS |
2014 | return 1; |
2015 | ||
2016 | return 0; | |
2017 | } | |
2018 | ||
2019 | static const struct frame_unwind sh_stub_unwind = | |
2020 | { | |
a154d838 | 2021 | "sh stub", |
cb2cf4ce TS |
2022 | NORMAL_FRAME, |
2023 | default_frame_unwind_stop_reason, | |
2024 | sh_stub_this_id, | |
2025 | sh_frame_prev_register, | |
2026 | NULL, | |
2027 | sh_stub_unwind_sniffer | |
2028 | }; | |
2029 | ||
c9cf6e20 MG |
2030 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2031 | ||
2032 | The epilogue is defined here as the area at the end of a function, | |
1c0159e0 | 2033 | either on the `ret' instruction itself or after an instruction which |
c378eb4e | 2034 | destroys the function's stack frame. */ |
c9cf6e20 | 2035 | |
1c0159e0 | 2036 | static int |
c9cf6e20 | 2037 | sh_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
1c0159e0 | 2038 | { |
e17a4113 | 2039 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
2040 | CORE_ADDR func_addr = 0, func_end = 0; |
2041 | ||
2042 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2043 | { | |
2044 | ULONGEST inst; | |
2045 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
dda83cd7 SM |
2046 | for a nop and some fixed data (e.g. big offsets) which are |
2047 | unfortunately also treated as part of the function (which | |
2048 | means, they are below func_end. */ | |
1c0159e0 CV |
2049 | CORE_ADDR addr = func_end - 28; |
2050 | if (addr < func_addr + 4) | |
617daa0e | 2051 | addr = func_addr + 4; |
1c0159e0 CV |
2052 | if (pc < addr) |
2053 | return 0; | |
2054 | ||
c378eb4e | 2055 | /* First search forward until hitting an rts. */ |
1c0159e0 | 2056 | while (addr < func_end |
e17a4113 | 2057 | && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) |
1c0159e0 CV |
2058 | addr += 2; |
2059 | if (addr >= func_end) | |
617daa0e | 2060 | return 0; |
1c0159e0 CV |
2061 | |
2062 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
dda83cd7 SM |
2063 | either before or after the rts. If not, then the function has |
2064 | probably no "normal" epilogue and we bail out here. */ | |
e17a4113 UW |
2065 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
2066 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, | |
2067 | byte_order))) | |
617daa0e | 2068 | addr -= 2; |
e17a4113 UW |
2069 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, |
2070 | byte_order))) | |
1c0159e0 CV |
2071 | return 0; |
2072 | ||
e17a4113 | 2073 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 | 2074 | |
c378eb4e | 2075 | /* Step over possible lds.l @r15+,macl. */ |
03131d99 CV |
2076 | if (IS_MACL_LDS (inst)) |
2077 | { | |
2078 | addr -= 2; | |
e17a4113 | 2079 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 CV |
2080 | } |
2081 | ||
c378eb4e | 2082 | /* Step over possible lds.l @r15+,pr. */ |
1c0159e0 | 2083 | if (IS_LDS (inst)) |
617daa0e | 2084 | { |
1c0159e0 | 2085 | addr -= 2; |
e17a4113 | 2086 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2087 | } |
2088 | ||
c378eb4e | 2089 | /* Step over possible mov r14,r15. */ |
1c0159e0 | 2090 | if (IS_MOV_FP_SP (inst)) |
617daa0e | 2091 | { |
1c0159e0 | 2092 | addr -= 2; |
e17a4113 | 2093 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2094 | } |
2095 | ||
2096 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
dda83cd7 | 2097 | instructions. */ |
1c0159e0 | 2098 | while (addr > func_addr + 4 |
617daa0e | 2099 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2100 | { |
2101 | addr -= 2; | |
e17a4113 | 2102 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2103 | } |
2104 | ||
03131d99 | 2105 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
dda83cd7 | 2106 | That's allowed for the epilogue. */ |
03131d99 | 2107 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a |
dda83cd7 SM |
2108 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) |
2109 | && addr > func_addr + 6 | |
e17a4113 UW |
2110 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, |
2111 | byte_order))) | |
03131d99 CV |
2112 | addr -= 4; |
2113 | ||
1c0159e0 CV |
2114 | if (pc >= addr) |
2115 | return 1; | |
2116 | } | |
2117 | return 0; | |
2118 | } | |
c9ac0a72 AS |
2119 | |
2120 | ||
2121 | /* Supply register REGNUM from the buffer specified by REGS and LEN | |
2122 | in the register set REGSET to register cache REGCACHE. | |
2123 | REGTABLE specifies where each register can be found in REGS. | |
2124 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2125 | ||
2126 | void | |
2127 | sh_corefile_supply_regset (const struct regset *regset, | |
2128 | struct regcache *regcache, | |
2129 | int regnum, const void *regs, size_t len) | |
2130 | { | |
ac7936df | 2131 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 2132 | sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); |
c9ac0a72 AS |
2133 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset |
2134 | ? tdep->core_gregmap | |
2135 | : tdep->core_fpregmap); | |
2136 | int i; | |
2137 | ||
2138 | for (i = 0; regmap[i].regnum != -1; i++) | |
2139 | { | |
2140 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2141 | && regmap[i].offset + 4 <= len) | |
73e1c03f SM |
2142 | regcache->raw_supply |
2143 | (regmap[i].regnum, (char *) regs + regmap[i].offset); | |
c9ac0a72 AS |
2144 | } |
2145 | } | |
2146 | ||
2147 | /* Collect register REGNUM in the register set REGSET from register cache | |
2148 | REGCACHE into the buffer specified by REGS and LEN. | |
2149 | REGTABLE specifies where each register can be found in REGS. | |
2150 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2151 | ||
2152 | void | |
2153 | sh_corefile_collect_regset (const struct regset *regset, | |
2154 | const struct regcache *regcache, | |
2155 | int regnum, void *regs, size_t len) | |
2156 | { | |
ac7936df | 2157 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 2158 | sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); |
c9ac0a72 AS |
2159 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset |
2160 | ? tdep->core_gregmap | |
2161 | : tdep->core_fpregmap); | |
2162 | int i; | |
2163 | ||
2164 | for (i = 0; regmap[i].regnum != -1; i++) | |
2165 | { | |
2166 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2167 | && regmap[i].offset + 4 <= len) | |
34a79281 | 2168 | regcache->raw_collect (regmap[i].regnum, |
c9ac0a72 AS |
2169 | (char *)regs + regmap[i].offset); |
2170 | } | |
2171 | } | |
2172 | ||
2173 | /* The following two regsets have the same contents, so it is tempting to | |
2174 | unify them, but they are distiguished by their address, so don't. */ | |
2175 | ||
3ca7dae4 | 2176 | const struct regset sh_corefile_gregset = |
c9ac0a72 AS |
2177 | { |
2178 | NULL, | |
2179 | sh_corefile_supply_regset, | |
2180 | sh_corefile_collect_regset | |
2181 | }; | |
2182 | ||
3ca7dae4 | 2183 | static const struct regset sh_corefile_fpregset = |
c9ac0a72 AS |
2184 | { |
2185 | NULL, | |
2186 | sh_corefile_supply_regset, | |
2187 | sh_corefile_collect_regset | |
2188 | }; | |
2189 | ||
c6d41a6f AA |
2190 | static void |
2191 | sh_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
2192 | iterate_over_regset_sections_cb *cb, | |
2193 | void *cb_data, | |
2194 | const struct regcache *regcache) | |
c9ac0a72 | 2195 | { |
08106042 | 2196 | sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); |
c9ac0a72 | 2197 | |
c6d41a6f | 2198 | if (tdep->core_gregmap != NULL) |
a616bb94 AH |
2199 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, |
2200 | &sh_corefile_gregset, NULL, cb_data); | |
c9ac0a72 | 2201 | |
c6d41a6f | 2202 | if (tdep->core_fpregmap != NULL) |
a616bb94 AH |
2203 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, |
2204 | &sh_corefile_fpregset, NULL, cb_data); | |
c9ac0a72 | 2205 | } |
18648a37 YQ |
2206 | |
2207 | /* This is the implementation of gdbarch method | |
2208 | return_in_first_hidden_param_p. */ | |
2209 | ||
2210 | static int | |
2211 | sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
2212 | struct type *type) | |
2213 | { | |
2214 | return 0; | |
2215 | } | |
2216 | ||
ccf00f21 | 2217 | \f |
cc17453a EZ |
2218 | |
2219 | static struct gdbarch * | |
fba45db2 | 2220 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2221 | { |
4be87837 DJ |
2222 | /* If there is already a candidate, use it. */ |
2223 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2224 | if (arches != NULL) | |
2225 | return arches->gdbarch; | |
cc17453a EZ |
2226 | |
2227 | /* None found, create a new architecture from the information | |
c378eb4e | 2228 | provided. */ |
2b16913c SM |
2229 | gdbarch *gdbarch |
2230 | = gdbarch_alloc (&info, gdbarch_tdep_up (new sh_gdbarch_tdep)); | |
cc17453a | 2231 | |
48db5a3c CV |
2232 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2233 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2234 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2235 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
53375380 PA |
2236 | |
2237 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2238 | set_gdbarch_wchar_signed (gdbarch, 0); | |
2239 | ||
48db5a3c CV |
2240 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
2241 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2242 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2243 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2244 | |
f2ea0907 | 2245 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2246 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2247 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2248 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2249 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2250 | ||
1c0159e0 | 2251 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2252 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2253 | |
04180708 YQ |
2254 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh_breakpoint_kind_from_pc); |
2255 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh_sw_breakpoint_from_kind); | |
48db5a3c | 2256 | |
2f14585c | 2257 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2258 | |
c0409442 | 2259 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2260 | |
48db5a3c CV |
2261 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2262 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2263 | |
1c0159e0 | 2264 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
18648a37 YQ |
2265 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
2266 | sh_return_in_first_hidden_param_p); | |
1c0159e0 | 2267 | |
48db5a3c CV |
2268 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2269 | ||
19f59343 | 2270 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2271 | frame_base_set_default (gdbarch, &sh_frame_base); |
2272 | ||
c9cf6e20 | 2273 | set_gdbarch_stack_frame_destroyed_p (gdbarch, sh_stack_frame_destroyed_p); |
cc17453a | 2274 | |
357d3800 AS |
2275 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2276 | ||
c6d41a6f AA |
2277 | set_gdbarch_iterate_over_regset_sections |
2278 | (gdbarch, sh_iterate_over_regset_sections); | |
c9ac0a72 | 2279 | |
cc17453a | 2280 | switch (info.bfd_arch_info->mach) |
8db62801 | 2281 | { |
cc17453a | 2282 | case bfd_mach_sh: |
48db5a3c | 2283 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2284 | break; |
1c0159e0 | 2285 | |
cc17453a | 2286 | case bfd_mach_sh2: |
48db5a3c | 2287 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2288 | break; |
1c0159e0 | 2289 | |
2d188dd3 | 2290 | case bfd_mach_sh2e: |
c378eb4e | 2291 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2292 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2293 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2294 | |
2295 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2296 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2297 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2298 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2299 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2300 | break; |
1c0159e0 | 2301 | |
da962468 CV |
2302 | case bfd_mach_sh2a: |
2303 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2304 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2305 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2306 | ||
2307 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2308 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2309 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
7f0f3b0f SM |
2310 | set_gdbarch_deprecated_pseudo_register_write (gdbarch, |
2311 | sh_pseudo_register_write); | |
c0409442 | 2312 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2313 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2314 | break; | |
2315 | ||
2316 | case bfd_mach_sh2a_nofpu: | |
2317 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2318 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2319 | ||
2320 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2321 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
7f0f3b0f SM |
2322 | set_gdbarch_deprecated_pseudo_register_write (gdbarch, |
2323 | sh_pseudo_register_write); | |
da962468 CV |
2324 | break; |
2325 | ||
cc17453a | 2326 | case bfd_mach_sh_dsp: |
48db5a3c | 2327 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2328 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2329 | break; |
1c0159e0 | 2330 | |
cc17453a | 2331 | case bfd_mach_sh3: |
4e6cbc38 AS |
2332 | case bfd_mach_sh3_nommu: |
2333 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2334 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2335 | break; |
1c0159e0 | 2336 | |
cc17453a | 2337 | case bfd_mach_sh3e: |
4e6cbc38 | 2338 | case bfd_mach_sh2a_or_sh3e: |
c378eb4e | 2339 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2340 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2341 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2342 | |
2343 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2344 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2345 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2346 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2347 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2348 | break; |
1c0159e0 | 2349 | |
cc17453a | 2350 | case bfd_mach_sh3_dsp: |
48db5a3c | 2351 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2352 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2353 | break; |
1c0159e0 | 2354 | |
cc17453a | 2355 | case bfd_mach_sh4: |
474e5826 | 2356 | case bfd_mach_sh4a: |
46e8a76b | 2357 | case bfd_mach_sh2a_or_sh4: |
48db5a3c | 2358 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2359 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2360 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2361 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 | 2362 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
7f0f3b0f SM |
2363 | set_gdbarch_deprecated_pseudo_register_write (gdbarch, |
2364 | sh_pseudo_register_write); | |
c0409442 | 2365 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2366 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2367 | break; |
1c0159e0 | 2368 | |
474e5826 CV |
2369 | case bfd_mach_sh4_nofpu: |
2370 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2371 | case bfd_mach_sh4_nommu_nofpu: |
2372 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
474e5826 CV |
2373 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2374 | break; | |
2375 | ||
2376 | case bfd_mach_sh4al_dsp: | |
2377 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2378 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2379 | break; | |
2380 | ||
cc17453a | 2381 | default: |
b58cbbf2 | 2382 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2383 | break; |
8db62801 | 2384 | } |
cc17453a | 2385 | |
4be87837 DJ |
2386 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2387 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2388 | |
94afd7a6 | 2389 | dwarf2_append_unwinders (gdbarch); |
cb2cf4ce | 2390 | frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); |
94afd7a6 | 2391 | frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); |
1c0159e0 | 2392 | |
cc17453a | 2393 | return gdbarch; |
8db62801 EZ |
2394 | } |
2395 | ||
6c265988 | 2396 | void _initialize_sh_tdep (); |
c906108c | 2397 | void |
6c265988 | 2398 | _initialize_sh_tdep () |
c906108c | 2399 | { |
f2ea0907 | 2400 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2401 | |
f54bdb6d SM |
2402 | add_setshow_prefix_cmd ("sh", no_class, |
2403 | _("SH specific commands."), | |
2404 | _("SH specific commands."), | |
2405 | &setshcmdlist, &showshcmdlist, | |
2406 | &setlist, &showlist); | |
c055b101 CV |
2407 | |
2408 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
2409 | &sh_active_calling_convention, | |
2410 | _("Set calling convention used when calling target " | |
2411 | "functions from GDB."), | |
2412 | _("Show calling convention used when calling target " | |
2413 | "functions from GDB."), | |
2414 | _("gcc - Use GCC calling convention (default).\n" | |
2415 | "renesas - Enforce Renesas calling convention."), | |
2416 | NULL, NULL, | |
2417 | &setshcmdlist, &showshcmdlist); | |
c906108c | 2418 | } |