projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a06ea964 NC |
1 | /* aarch64-tbl.h -- AArch64 opcode description table and instruction |
| 2 | operand description table. | |
| 219d1afa | 3 | Copyright (C) 2012-2018 Free Software Foundation, Inc. |
| a06ea964 NC |
4 | |
| 5 | This file is part of the GNU opcodes library. | |
| 6 | ||
| 7 | This library is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | It is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with this file; see the file COPYING. If not, write to the | |
| 19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 20 | MA 02110-1301, USA. */ | |
| 21 | ||
| 22 | #include "aarch64-opc.h" | |
| 23 | ||
| 20f55f38 SN |
24 | #ifndef VERIFIER |
| 25 | #error VERIFIER must be defined. | |
| 26 | #endif | |
| 27 | ||
| a06ea964 NC |
28 | /* Operand type. */ |
| 29 | ||
| 30 | #define OPND(x) AARCH64_OPND_##x | |
| 31 | #define OP0() {} | |
| 32 | #define OP1(a) {OPND(a)} | |
| 33 | #define OP2(a,b) {OPND(a), OPND(b)} | |
| 34 | #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} | |
| 35 | #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} | |
| 36 | #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} | |
| 37 | ||
| 38 | #define QLF(x) AARCH64_OPND_QLF_##x | |
| 39 | #define QLF1(a) {QLF(a)} | |
| 40 | #define QLF2(a,b) {QLF(a), QLF(b)} | |
| 41 | #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} | |
| 42 | #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} | |
| 43 | #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} | |
| 44 | ||
| 45 | /* Qualifiers list. */ | |
| 46 | ||
| 47 | /* e.g. MSR <systemreg>, <Xt>. */ | |
| 48 | #define QL_SRC_X \ | |
| 49 | { \ | |
| 50 | QLF2(NIL,X), \ | |
| 51 | } | |
| 52 | ||
| 53 | /* e.g. MRS <Xt>, <systemreg>. */ | |
| 54 | #define QL_DST_X \ | |
| 55 | { \ | |
| 56 | QLF2(X,NIL), \ | |
| 57 | } | |
| 58 | ||
| 59 | /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ | |
| 60 | #define QL_SYS \ | |
| 61 | { \ | |
| a6a51754 | 62 | QLF5(NIL,CR,CR,NIL,X), \ |
| a06ea964 NC |
63 | } |
| 64 | ||
| 65 | /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ | |
| 66 | #define QL_SYSL \ | |
| 67 | { \ | |
| a6a51754 | 68 | QLF5(X,NIL,CR,CR,NIL), \ |
| a06ea964 NC |
69 | } |
| 70 | ||
| 71 | /* e.g. ADRP <Xd>, <label>. */ | |
| 72 | #define QL_ADRP \ | |
| 73 | { \ | |
| 74 | QLF2(X,NIL), \ | |
| 75 | } | |
| 76 | ||
| 77 | /* e.g. B.<cond> <label>. */ | |
| 78 | #define QL_PCREL_NIL \ | |
| 79 | { \ | |
| 80 | QLF1(NIL), \ | |
| 81 | } | |
| 82 | ||
| 83 | /* e.g. TBZ <Xt>, #<imm>, <label>. */ | |
| 84 | #define QL_PCREL_14 \ | |
| 85 | { \ | |
| 86 | QLF3(X,imm_0_63,NIL), \ | |
| 87 | } | |
| 88 | ||
| 89 | /* e.g. BL <label>. */ | |
| 90 | #define QL_PCREL_26 \ | |
| 91 | { \ | |
| 92 | QLF1(NIL), \ | |
| 93 | } | |
| 94 | ||
| 95 | /* e.g. LDRSW <Xt>, <label>. */ | |
| 96 | #define QL_X_PCREL \ | |
| 97 | { \ | |
| 98 | QLF2(X,NIL), \ | |
| 99 | } | |
| 100 | ||
| 101 | /* e.g. LDR <Wt>, <label>. */ | |
| 102 | #define QL_R_PCREL \ | |
| 103 | { \ | |
| 104 | QLF2(W,NIL), \ | |
| 105 | QLF2(X,NIL), \ | |
| 106 | } | |
| 107 | ||
| 108 | /* e.g. LDR <Dt>, <label>. */ | |
| 109 | #define QL_FP_PCREL \ | |
| 110 | { \ | |
| 111 | QLF2(S_S,NIL), \ | |
| 112 | QLF2(S_D,NIL), \ | |
| 113 | QLF2(S_Q,NIL), \ | |
| 114 | } | |
| 115 | ||
| 116 | /* e.g. PRFM <prfop>, <label>. */ | |
| 117 | #define QL_PRFM_PCREL \ | |
| 118 | { \ | |
| 119 | QLF2(NIL,NIL), \ | |
| 120 | } | |
| 121 | ||
| 122 | /* e.g. BR <Xn>. */ | |
| 123 | #define QL_I1X \ | |
| 124 | { \ | |
| 125 | QLF1(X), \ | |
| 126 | } | |
| 127 | ||
| 128 | /* e.g. RBIT <Wd>, <Wn>. */ | |
| 129 | #define QL_I2SAME \ | |
| 130 | { \ | |
| 131 | QLF2(W,W), \ | |
| 132 | QLF2(X,X), \ | |
| 133 | } | |
| 134 | ||
| 135 | /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */ | |
| 136 | #define QL_I2_EXT \ | |
| 137 | { \ | |
| 138 | QLF2(W,W), \ | |
| 139 | QLF2(X,W), \ | |
| 140 | QLF2(X,X), \ | |
| 141 | } | |
| 142 | ||
| 143 | /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */ | |
| 144 | #define QL_I2SP \ | |
| 145 | { \ | |
| 146 | QLF2(WSP,W), \ | |
| 147 | QLF2(W,WSP), \ | |
| 148 | QLF2(SP,X), \ | |
| 149 | QLF2(X,SP), \ | |
| 150 | } | |
| 151 | ||
| 152 | /* e.g. REV <Wd>, <Wn>. */ | |
| 153 | #define QL_I2SAMEW \ | |
| 154 | { \ | |
| 155 | QLF2(W,W), \ | |
| 156 | } | |
| 157 | ||
| 158 | /* e.g. REV32 <Xd>, <Xn>. */ | |
| 159 | #define QL_I2SAMEX \ | |
| 160 | { \ | |
| 161 | QLF2(X,X), \ | |
| 162 | } | |
| 163 | ||
| 164 | #define QL_I2SAMER \ | |
| 165 | { \ | |
| 166 | QLF2(W,W), \ | |
| 167 | QLF2(X,X), \ | |
| 168 | } | |
| 169 | ||
| e60bb1dd YZ |
170 | /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */ |
| 171 | #define QL_I3SAMEW \ | |
| 172 | { \ | |
| 173 | QLF3(W,W,W), \ | |
| 174 | } | |
| 175 | ||
| a06ea964 NC |
176 | /* e.g. SMULH <Xd>, <Xn>, <Xm>. */ |
| 177 | #define QL_I3SAMEX \ | |
| 178 | { \ | |
| 179 | QLF3(X,X,X), \ | |
| 180 | } | |
| 181 | ||
| e60bb1dd YZ |
182 | /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */ |
| 183 | #define QL_I3WWX \ | |
| 184 | { \ | |
| 185 | QLF3(W,W,X), \ | |
| 186 | } | |
| 187 | ||
| a06ea964 NC |
188 | /* e.g. UDIV <Xd>, <Xn>, <Xm>. */ |
| 189 | #define QL_I3SAMER \ | |
| 190 | { \ | |
| 191 | QLF3(W,W,W), \ | |
| 192 | QLF3(X,X,X), \ | |
| 193 | } | |
| 194 | ||
| 195 | /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */ | |
| 196 | #define QL_I3_EXT \ | |
| 197 | { \ | |
| 198 | QLF3(W,W,W), \ | |
| 199 | QLF3(X,X,W), \ | |
| 200 | QLF3(X,X,X), \ | |
| 201 | } | |
| 202 | ||
| 203 | /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */ | |
| 204 | #define QL_I4SAMER \ | |
| 205 | { \ | |
| 206 | QLF4(W,W,W,W), \ | |
| 207 | QLF4(X,X,X,X), \ | |
| 208 | } | |
| 209 | ||
| 210 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
| 211 | #define QL_I3SAMEL \ | |
| 212 | { \ | |
| 213 | QLF3(X,W,W), \ | |
| 214 | } | |
| 215 | ||
| 216 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
| 217 | #define QL_I4SAMEL \ | |
| 218 | { \ | |
| 219 | QLF4(X,W,W,X), \ | |
| 220 | } | |
| 221 | ||
| 222 | /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */ | |
| 223 | #define QL_CSEL \ | |
| 224 | { \ | |
| 225 | QLF4(W, W, W, NIL), \ | |
| 226 | QLF4(X, X, X, NIL), \ | |
| 227 | } | |
| 228 | ||
| 229 | /* e.g. CSET <Wd>, <cond>. */ | |
| 230 | #define QL_DST_R \ | |
| 231 | { \ | |
| 232 | QLF2(W, NIL), \ | |
| 233 | QLF2(X, NIL), \ | |
| 234 | } | |
| 235 | ||
| 236 | /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */ | |
| 237 | #define QL_BF \ | |
| 238 | { \ | |
| 239 | QLF4(W,W,imm_0_31,imm_0_31), \ | |
| 240 | QLF4(X,X,imm_0_63,imm_0_63), \ | |
| 241 | } | |
| 242 | ||
| d685192a MW |
243 | /* e.g. BFC <Wd>, #<immr>, #<imms>. */ |
| 244 | #define QL_BF1 \ | |
| 245 | { \ | |
| 246 | QLF3 (W, imm_0_31, imm_1_32), \ | |
| 247 | QLF3 (X, imm_0_63, imm_1_64), \ | |
| 248 | } | |
| 249 | ||
| a06ea964 NC |
250 | /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ |
| 251 | #define QL_BF2 \ | |
| 252 | { \ | |
| 253 | QLF4(W,W,imm_0_31,imm_1_32), \ | |
| 254 | QLF4(X,X,imm_0_63,imm_1_64), \ | |
| 255 | } | |
| 256 | ||
| 257 | /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */ | |
| 258 | #define QL_FIX2FP \ | |
| 259 | { \ | |
| 260 | QLF3(S_D,W,imm_1_32), \ | |
| 261 | QLF3(S_S,W,imm_1_32), \ | |
| 262 | QLF3(S_D,X,imm_1_64), \ | |
| 263 | QLF3(S_S,X,imm_1_64), \ | |
| 264 | } | |
| 265 | ||
| 622b9eb1 MW |
266 | /* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */ |
| 267 | #define QL_FIX2FP_H \ | |
| 268 | { \ | |
| 269 | QLF3 (S_H, W, imm_1_32), \ | |
| 270 | QLF3 (S_H, X, imm_1_64), \ | |
| 271 | } | |
| 272 | ||
| a06ea964 NC |
273 | /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */ |
| 274 | #define QL_FP2FIX \ | |
| 275 | { \ | |
| 276 | QLF3(W,S_D,imm_1_32), \ | |
| 277 | QLF3(W,S_S,imm_1_32), \ | |
| 278 | QLF3(X,S_D,imm_1_64), \ | |
| 279 | QLF3(X,S_S,imm_1_64), \ | |
| 280 | } | |
| 281 | ||
| 622b9eb1 MW |
282 | /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */ |
| 283 | #define QL_FP2FIX_H \ | |
| 284 | { \ | |
| 285 | QLF3 (W, S_H, imm_1_32), \ | |
| 286 | QLF3 (X, S_H, imm_1_64), \ | |
| 287 | } | |
| 288 | ||
| a06ea964 NC |
289 | /* e.g. SCVTF <Dd>, <Wn>. */ |
| 290 | #define QL_INT2FP \ | |
| 291 | { \ | |
| 292 | QLF2(S_D,W), \ | |
| 293 | QLF2(S_S,W), \ | |
| 294 | QLF2(S_D,X), \ | |
| 295 | QLF2(S_S,X), \ | |
| 296 | } | |
| 297 | ||
| cb366992 EB |
298 | /* e.g. FMOV <Dd>, <Xn>. */ |
| 299 | #define QL_INT2FP_FMOV \ | |
| 300 | { \ | |
| 301 | QLF2(S_S,W), \ | |
| 302 | QLF2(S_D,X), \ | |
| 303 | } | |
| 304 | ||
| 622b9eb1 MW |
305 | /* e.g. SCVTF <Hd>, <Wn>. */ |
| 306 | #define QL_INT2FP_H \ | |
| 307 | { \ | |
| 308 | QLF2 (S_H, W), \ | |
| 309 | QLF2 (S_H, X), \ | |
| 310 | } | |
| 311 | ||
| a06ea964 NC |
312 | /* e.g. FCVTNS <Xd>, <Dn>. */ |
| 313 | #define QL_FP2INT \ | |
| 314 | { \ | |
| 315 | QLF2(W,S_D), \ | |
| 316 | QLF2(W,S_S), \ | |
| 317 | QLF2(X,S_D), \ | |
| 318 | QLF2(X,S_S), \ | |
| 319 | } | |
| 320 | ||
| cb366992 EB |
321 | /* e.g. FMOV <Xd>, <Dn>. */ |
| 322 | #define QL_FP2INT_FMOV \ | |
| 323 | { \ | |
| 324 | QLF2(W,S_S), \ | |
| 325 | QLF2(X,S_D), \ | |
| 326 | } | |
| 327 | ||
| 622b9eb1 MW |
328 | /* e.g. FCVTNS <Hd>, <Wn>. */ |
| 329 | #define QL_FP2INT_H \ | |
| 330 | { \ | |
| 331 | QLF2 (W, S_H), \ | |
| 332 | QLF2 (X, S_H), \ | |
| 333 | } | |
| 334 | ||
| ccfc90a3 SN |
335 | /* e.g. FJCVTZS <Wd>, <Dn>. */ |
| 336 | #define QL_FP2INT_W_D \ | |
| 337 | { \ | |
| 338 | QLF2 (W, S_D), \ | |
| 339 | } | |
| 340 | ||
| a06ea964 NC |
341 | /* e.g. FMOV <Xd>, <Vn>.D[1]. */ |
| 342 | #define QL_XVD1 \ | |
| 343 | { \ | |
| 344 | QLF2(X,S_D), \ | |
| 345 | } | |
| 346 | ||
| 347 | /* e.g. FMOV <Vd>.D[1], <Xn>. */ | |
| 348 | #define QL_VD1X \ | |
| 349 | { \ | |
| 350 | QLF2(S_D,X), \ | |
| 351 | } | |
| 352 | ||
| 353 | /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */ | |
| 354 | #define QL_EXTR \ | |
| 355 | { \ | |
| 356 | QLF4(W,W,W,imm_0_31), \ | |
| 357 | QLF4(X,X,X,imm_0_63), \ | |
| 358 | } | |
| 359 | ||
| 360 | /* e.g. LSL <Wd>, <Wn>, #<uimm>. */ | |
| 361 | #define QL_SHIFT \ | |
| 362 | { \ | |
| 363 | QLF3(W,W,imm_0_31), \ | |
| 364 | QLF3(X,X,imm_0_63), \ | |
| 365 | } | |
| 366 | ||
| 367 | /* e.g. UXTH <Xd>, <Wn>. */ | |
| 368 | #define QL_EXT \ | |
| 369 | { \ | |
| 370 | QLF2(W,W), \ | |
| 371 | QLF2(X,W), \ | |
| 372 | } | |
| 373 | ||
| 374 | /* e.g. UXTW <Xd>, <Wn>. */ | |
| 375 | #define QL_EXT_W \ | |
| 376 | { \ | |
| 377 | QLF2(X,W), \ | |
| 378 | } | |
| 379 | ||
| 380 | /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */ | |
| 381 | #define QL_SSHIFT \ | |
| 382 | { \ | |
| 383 | QLF3(S_B , S_B , S_B ), \ | |
| 384 | QLF3(S_H , S_H , S_H ), \ | |
| 385 | QLF3(S_S , S_S , S_S ), \ | |
| 386 | QLF3(S_D , S_D , S_D ) \ | |
| 387 | } | |
| 388 | ||
| 389 | /* e.g. SSHR <V><d>, <V><n>, #<shift>. */ | |
| 390 | #define QL_SSHIFT_D \ | |
| 391 | { \ | |
| 392 | QLF3(S_D , S_D , S_D ) \ | |
| 393 | } | |
| 394 | ||
| 395 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
| 396 | #define QL_SSHIFT_SD \ | |
| 397 | { \ | |
| 398 | QLF3(S_S , S_S , S_S ), \ | |
| 399 | QLF3(S_D , S_D , S_D ) \ | |
| 400 | } | |
| 401 | ||
| 4fd0a9fd MW |
402 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| 403 | #define QL_SSHIFT_H \ | |
| 404 | { \ | |
| 405 | QLF3 (S_H, S_H, S_H) \ | |
| 406 | } | |
| 407 | ||
| a06ea964 NC |
408 | /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ |
| 409 | #define QL_SSHIFTN \ | |
| 410 | { \ | |
| 411 | QLF3(S_B , S_H , S_B ), \ | |
| 412 | QLF3(S_H , S_S , S_H ), \ | |
| 413 | QLF3(S_S , S_D , S_S ), \ | |
| 414 | } | |
| 415 | ||
| 416 | /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>. | |
| 417 | The register operand variant qualifiers are deliberately used for the | |
| 418 | immediate operand to ease the operand encoding/decoding and qualifier | |
| 419 | sequence matching. */ | |
| 420 | #define QL_VSHIFT \ | |
| 421 | { \ | |
| 422 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 423 | QLF3(V_16B, V_16B, V_16B), \ | |
| 424 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 425 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 426 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 427 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 428 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 429 | } | |
| 430 | ||
| 431 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
| 432 | #define QL_VSHIFT_SD \ | |
| 433 | { \ | |
| 434 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 435 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 436 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 437 | } | |
| 438 | ||
| b5b0f34c MW |
439 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| 440 | #define QL_VSHIFT_H \ | |
| 441 | { \ | |
| 442 | QLF3 (V_4H, V_4H, V_4H), \ | |
| 443 | QLF3 (V_8H, V_8H, V_8H) \ | |
| 444 | } | |
| 445 | ||
| a06ea964 NC |
446 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ |
| 447 | #define QL_VSHIFTN \ | |
| 448 | { \ | |
| 449 | QLF3(V_8B , V_8H , V_8B ), \ | |
| 450 | QLF3(V_4H , V_4S , V_4H ), \ | |
| 451 | QLF3(V_2S , V_2D , V_2S ), \ | |
| 452 | } | |
| 453 | ||
| 454 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ | |
| 455 | #define QL_VSHIFTN2 \ | |
| 456 | { \ | |
| 457 | QLF3(V_16B, V_8H, V_16B), \ | |
| 458 | QLF3(V_8H , V_4S , V_8H ), \ | |
| 459 | QLF3(V_4S , V_2D , V_4S ), \ | |
| 460 | } | |
| 461 | ||
| 462 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. | |
| 463 | the 3rd qualifier is used to help the encoding. */ | |
| 464 | #define QL_VSHIFTL \ | |
| 465 | { \ | |
| 466 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 467 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 468 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 469 | } | |
| 470 | ||
| 471 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 472 | #define QL_VSHIFTL2 \ | |
| 473 | { \ | |
| 474 | QLF3(V_8H , V_16B, V_16B), \ | |
| 475 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 476 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 477 | } | |
| 478 | ||
| 479 | /* e.g. TBL. */ | |
| 480 | #define QL_TABLE \ | |
| 481 | { \ | |
| 482 | QLF3(V_8B , V_16B, V_8B ), \ | |
| 483 | QLF3(V_16B, V_16B, V_16B), \ | |
| 484 | } | |
| 485 | ||
| 486 | /* e.g. SHA1H. */ | |
| 487 | #define QL_2SAMES \ | |
| 488 | { \ | |
| 489 | QLF2(S_S, S_S), \ | |
| 490 | } | |
| 491 | ||
| 492 | /* e.g. ABS <V><d>, <V><n>. */ | |
| 493 | #define QL_2SAMED \ | |
| 494 | { \ | |
| 495 | QLF2(S_D, S_D), \ | |
| 496 | } | |
| 497 | ||
| 498 | /* e.g. CMGT <V><d>, <V><n>, #0. */ | |
| 499 | #define QL_SISD_CMP_0 \ | |
| 500 | { \ | |
| 501 | QLF3(S_D, S_D, NIL), \ | |
| 502 | } | |
| 503 | ||
| 504 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ | |
| 505 | #define QL_SISD_FCMP_0 \ | |
| 506 | { \ | |
| 507 | QLF3(S_S, S_S, NIL), \ | |
| 508 | QLF3(S_D, S_D, NIL), \ | |
| 509 | } | |
| 510 | ||
| 80776b29 MW |
511 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ |
| 512 | #define QL_SISD_FCMP_H_0 \ | |
| 513 | { \ | |
| 514 | QLF3 (S_H, S_H, NIL), \ | |
| 515 | } | |
| 516 | ||
| a06ea964 NC |
517 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
| 518 | #define QL_SISD_PAIR \ | |
| 519 | { \ | |
| 520 | QLF2(S_S, V_2S), \ | |
| 521 | QLF2(S_D, V_2D), \ | |
| 522 | } | |
| 523 | ||
| b195470d MW |
524 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
| 525 | #define QL_SISD_PAIR_H \ | |
| 526 | { \ | |
| 527 | QLF2 (S_H, V_2H), \ | |
| 528 | } | |
| 529 | ||
| a06ea964 NC |
530 | /* e.g. ADDP <V><d>, <Vn>.<T>. */ |
| 531 | #define QL_SISD_PAIR_D \ | |
| 532 | { \ | |
| 533 | QLF2(S_D, V_2D), \ | |
| 534 | } | |
| 535 | ||
| 536 | /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */ | |
| 537 | #define QL_S_2SAME \ | |
| 538 | { \ | |
| 539 | QLF2(S_B, S_B), \ | |
| 540 | QLF2(S_H, S_H), \ | |
| 541 | QLF2(S_S, S_S), \ | |
| 542 | QLF2(S_D, S_D), \ | |
| 543 | } | |
| 544 | ||
| 545 | /* e.g. FCVTNS <V><d>, <V><n>. */ | |
| 546 | #define QL_S_2SAMESD \ | |
| 547 | { \ | |
| 548 | QLF2(S_S, S_S), \ | |
| 549 | QLF2(S_D, S_D), \ | |
| 550 | } | |
| 551 | ||
| 80776b29 MW |
552 | /* e.g. FCVTNS <V><d>, <V><n>. */ |
| 553 | #define QL_S_2SAMEH \ | |
| 554 | { \ | |
| 555 | QLF2 (S_H, S_H), \ | |
| 556 | } | |
| 557 | ||
| a06ea964 NC |
558 | /* e.g. SQXTN <Vb><d>, <Va><n>. */ |
| 559 | #define QL_SISD_NARROW \ | |
| 560 | { \ | |
| 561 | QLF2(S_B, S_H), \ | |
| 562 | QLF2(S_H, S_S), \ | |
| 563 | QLF2(S_S, S_D), \ | |
| 564 | } | |
| 565 | ||
| 566 | /* e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
| 567 | #define QL_SISD_NARROW_S \ | |
| 568 | { \ | |
| 569 | QLF2(S_S, S_D), \ | |
| 570 | } | |
| 571 | ||
| 572 | /* e.g. FCVT. */ | |
| 573 | #define QL_FCVT \ | |
| 574 | { \ | |
| 575 | QLF2(S_S, S_H), \ | |
| 576 | QLF2(S_S, S_D), \ | |
| 577 | QLF2(S_D, S_H), \ | |
| 578 | QLF2(S_D, S_S), \ | |
| 579 | QLF2(S_H, S_S), \ | |
| 580 | QLF2(S_H, S_D), \ | |
| 581 | } | |
| 582 | ||
| 583 | /* FMOV <Dd>, <Dn>. */ | |
| 584 | #define QL_FP2 \ | |
| 585 | { \ | |
| 586 | QLF2(S_S, S_S), \ | |
| 587 | QLF2(S_D, S_D), \ | |
| 588 | } | |
| 589 | ||
| 622b9eb1 MW |
590 | /* FMOV <Hd>, <Hn>. */ |
| 591 | #define QL_FP2_H \ | |
| 592 | { \ | |
| 593 | QLF2 (S_H, S_H), \ | |
| 594 | } | |
| 595 | ||
| a06ea964 NC |
596 | /* e.g. SQADD <V><d>, <V><n>, <V><m>. */ |
| 597 | #define QL_S_3SAME \ | |
| 598 | { \ | |
| 599 | QLF3(S_B, S_B, S_B), \ | |
| 600 | QLF3(S_H, S_H, S_H), \ | |
| 601 | QLF3(S_S, S_S, S_S), \ | |
| 602 | QLF3(S_D, S_D, S_D), \ | |
| 603 | } | |
| 604 | ||
| 605 | /* e.g. CMGE <V><d>, <V><n>, <V><m>. */ | |
| 606 | #define QL_S_3SAMED \ | |
| 607 | { \ | |
| 608 | QLF3(S_D, S_D, S_D), \ | |
| 609 | } | |
| 610 | ||
| 611 | /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */ | |
| 612 | #define QL_SISD_HS \ | |
| 613 | { \ | |
| 614 | QLF3(S_H, S_H, S_H), \ | |
| 615 | QLF3(S_S, S_S, S_S), \ | |
| 616 | } | |
| 617 | ||
| 618 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */ | |
| 619 | #define QL_SISDL_HS \ | |
| 620 | { \ | |
| 621 | QLF3(S_S, S_H, S_H), \ | |
| 622 | QLF3(S_D, S_S, S_S), \ | |
| 623 | } | |
| 624 | ||
| 625 | /* FMUL <Sd>, <Sn>, <Sm>. */ | |
| 626 | #define QL_FP3 \ | |
| 627 | { \ | |
| 628 | QLF3(S_S, S_S, S_S), \ | |
| 629 | QLF3(S_D, S_D, S_D), \ | |
| 630 | } | |
| 631 | ||
| 622b9eb1 MW |
632 | /* FMUL <Hd>, <Hn>, <Hm>. */ |
| 633 | #define QL_FP3_H \ | |
| 634 | { \ | |
| 635 | QLF3 (S_H, S_H, S_H), \ | |
| 636 | } | |
| 637 | ||
| a06ea964 NC |
638 | /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */ |
| 639 | #define QL_FP4 \ | |
| 640 | { \ | |
| 641 | QLF4(S_S, S_S, S_S, S_S), \ | |
| 642 | QLF4(S_D, S_D, S_D, S_D), \ | |
| 643 | } | |
| 644 | ||
| 622b9eb1 MW |
645 | /* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */ |
| 646 | #define QL_FP4_H \ | |
| 647 | { \ | |
| 648 | QLF4 (S_H, S_H, S_H, S_H), \ | |
| 649 | } | |
| 650 | ||
| a06ea964 NC |
651 | /* e.g. FCMP <Dn>, #0.0. */ |
| 652 | #define QL_DST_SD \ | |
| 653 | { \ | |
| 654 | QLF2(S_S, NIL), \ | |
| 655 | QLF2(S_D, NIL), \ | |
| 656 | } | |
| 657 | ||
| 622b9eb1 MW |
658 | /* e.g. FCMP <Hn>, #0.0. */ |
| 659 | #define QL_DST_H \ | |
| 660 | { \ | |
| 661 | QLF2 (S_H, NIL), \ | |
| 662 | } | |
| 663 | ||
| a06ea964 NC |
664 | /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */ |
| 665 | #define QL_FP_COND \ | |
| 666 | { \ | |
| 667 | QLF4(S_S, S_S, S_S, NIL), \ | |
| 668 | QLF4(S_D, S_D, S_D, NIL), \ | |
| 669 | } | |
| 670 | ||
| 622b9eb1 MW |
671 | /* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */ |
| 672 | #define QL_FP_COND_H \ | |
| 673 | { \ | |
| 674 | QLF4 (S_H, S_H, S_H, NIL), \ | |
| 675 | } | |
| 676 | ||
| a06ea964 NC |
677 | /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */ |
| 678 | #define QL_CCMP \ | |
| 679 | { \ | |
| 680 | QLF4(W, W, NIL, NIL), \ | |
| 681 | QLF4(X, X, NIL, NIL), \ | |
| 682 | } | |
| 683 | ||
| 684 | /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */ | |
| 685 | #define QL_CCMP_IMM \ | |
| 686 | { \ | |
| 687 | QLF4(W, NIL, NIL, NIL), \ | |
| 688 | QLF4(X, NIL, NIL, NIL), \ | |
| 689 | } | |
| 690 | ||
| 691 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ | |
| 692 | #define QL_FCCMP \ | |
| 693 | { \ | |
| 694 | QLF4(S_S, S_S, NIL, NIL), \ | |
| 695 | QLF4(S_D, S_D, NIL, NIL), \ | |
| 696 | } | |
| 697 | ||
| 622b9eb1 MW |
698 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ |
| 699 | #define QL_FCCMP_H \ | |
| 700 | { \ | |
| 701 | QLF4 (S_H, S_H, NIL, NIL), \ | |
| 702 | } | |
| 703 | ||
| a06ea964 NC |
704 | /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */ |
| 705 | #define QL_DUP_VX \ | |
| 706 | { \ | |
| 707 | QLF2(V_8B , S_B ), \ | |
| 708 | QLF2(V_16B, S_B ), \ | |
| 709 | QLF2(V_4H , S_H ), \ | |
| 710 | QLF2(V_8H , S_H ), \ | |
| 711 | QLF2(V_2S , S_S ), \ | |
| 712 | QLF2(V_4S , S_S ), \ | |
| 713 | QLF2(V_2D , S_D ), \ | |
| 714 | } | |
| 715 | ||
| 716 | /* e.g. DUP <Vd>.<T>, <Wn>. */ | |
| 717 | #define QL_DUP_VR \ | |
| 718 | { \ | |
| 719 | QLF2(V_8B , W ), \ | |
| 720 | QLF2(V_16B, W ), \ | |
| 721 | QLF2(V_4H , W ), \ | |
| 722 | QLF2(V_8H , W ), \ | |
| 723 | QLF2(V_2S , W ), \ | |
| 724 | QLF2(V_4S , W ), \ | |
| 725 | QLF2(V_2D , X ), \ | |
| 726 | } | |
| 727 | ||
| 728 | /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */ | |
| 729 | #define QL_INS_XR \ | |
| 730 | { \ | |
| 731 | QLF2(S_H , W ), \ | |
| 732 | QLF2(S_S , W ), \ | |
| 733 | QLF2(S_D , X ), \ | |
| 734 | QLF2(S_B , W ), \ | |
| 735 | } | |
| 736 | ||
| 737 | /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 738 | #define QL_SMOV \ | |
| 739 | { \ | |
| 740 | QLF2(W , S_H), \ | |
| 741 | QLF2(X , S_H), \ | |
| 742 | QLF2(X , S_S), \ | |
| 743 | QLF2(W , S_B), \ | |
| 744 | QLF2(X , S_B), \ | |
| 745 | } | |
| 746 | ||
| 747 | /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 748 | #define QL_UMOV \ | |
| 749 | { \ | |
| 750 | QLF2(W , S_H), \ | |
| 751 | QLF2(W , S_S), \ | |
| 752 | QLF2(X , S_D), \ | |
| 753 | QLF2(W , S_B), \ | |
| 754 | } | |
| 755 | ||
| 756 | /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 757 | #define QL_MOV \ | |
| 758 | { \ | |
| 759 | QLF2(W , S_S), \ | |
| 760 | QLF2(X , S_D), \ | |
| 761 | } | |
| 762 | ||
| 763 | /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */ | |
| 764 | #define QL_V2SAME \ | |
| 765 | { \ | |
| 766 | QLF2(V_8B , V_8B ), \ | |
| 767 | QLF2(V_16B, V_16B), \ | |
| 768 | QLF2(V_4H , V_4H ), \ | |
| 769 | QLF2(V_8H , V_8H ), \ | |
| 770 | QLF2(V_2S , V_2S ), \ | |
| 771 | QLF2(V_4S , V_4S ), \ | |
| 772 | QLF2(V_2D , V_2D ), \ | |
| 773 | } | |
| 774 | ||
| 775 | /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */ | |
| 776 | #define QL_V2SAMES \ | |
| 777 | { \ | |
| 778 | QLF2(V_2S , V_2S ), \ | |
| 779 | QLF2(V_4S , V_4S ), \ | |
| 780 | } | |
| 781 | ||
| 782 | /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */ | |
| 783 | #define QL_V2SAMEBH \ | |
| 784 | { \ | |
| 785 | QLF2(V_8B , V_8B ), \ | |
| 786 | QLF2(V_16B, V_16B), \ | |
| 787 | QLF2(V_4H , V_4H ), \ | |
| 788 | QLF2(V_8H , V_8H ), \ | |
| 789 | } | |
| 790 | ||
| 791 | /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */ | |
| 792 | #define QL_V2SAMESD \ | |
| 793 | { \ | |
| 794 | QLF2(V_2S , V_2S ), \ | |
| 795 | QLF2(V_4S , V_4S ), \ | |
| 796 | QLF2(V_2D , V_2D ), \ | |
| 797 | } | |
| 798 | ||
| 799 | /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */ | |
| 800 | #define QL_V2SAMEBHS \ | |
| 801 | { \ | |
| 802 | QLF2(V_8B , V_8B ), \ | |
| 803 | QLF2(V_16B, V_16B), \ | |
| 804 | QLF2(V_4H , V_4H ), \ | |
| 805 | QLF2(V_8H , V_8H ), \ | |
| 806 | QLF2(V_2S , V_2S ), \ | |
| 807 | QLF2(V_4S , V_4S ), \ | |
| 808 | } | |
| 809 | ||
| f3aa142b MW |
810 | /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */ |
| 811 | #define QL_V2SAMEH \ | |
| 812 | { \ | |
| 813 | QLF2 (V_4H, V_4H), \ | |
| 814 | QLF2 (V_8H, V_8H), \ | |
| 815 | } | |
| 816 | ||
| a06ea964 NC |
817 | /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ |
| 818 | #define QL_V2SAMEB \ | |
| 819 | { \ | |
| 820 | QLF2(V_8B , V_8B ), \ | |
| 821 | QLF2(V_16B, V_16B), \ | |
| 822 | } | |
| 823 | ||
| 824 | /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 825 | #define QL_V2PAIRWISELONGBHS \ | |
| 826 | { \ | |
| 827 | QLF2(V_4H , V_8B ), \ | |
| 828 | QLF2(V_8H , V_16B), \ | |
| 829 | QLF2(V_2S , V_4H ), \ | |
| 830 | QLF2(V_4S , V_8H ), \ | |
| 831 | QLF2(V_1D , V_2S ), \ | |
| 832 | QLF2(V_2D , V_4S ), \ | |
| 833 | } | |
| 834 | ||
| 835 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 836 | #define QL_V2LONGBHS \ | |
| 837 | { \ | |
| 838 | QLF2(V_8H , V_8B ), \ | |
| 839 | QLF2(V_4S , V_4H ), \ | |
| 840 | QLF2(V_2D , V_2S ), \ | |
| 841 | } | |
| 842 | ||
| 843 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 844 | #define QL_V2LONGBHS2 \ | |
| 845 | { \ | |
| 846 | QLF2(V_8H , V_16B), \ | |
| 847 | QLF2(V_4S , V_8H ), \ | |
| 848 | QLF2(V_2D , V_4S ), \ | |
| 849 | } | |
| 850 | ||
| 851 | /* */ | |
| 852 | #define QL_V3SAME \ | |
| 853 | { \ | |
| 854 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 855 | QLF3(V_16B, V_16B, V_16B), \ | |
| 856 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 857 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 858 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 859 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 860 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 861 | } | |
| 862 | ||
| 863 | /* e.g. SHADD. */ | |
| 864 | #define QL_V3SAMEBHS \ | |
| 865 | { \ | |
| 866 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 867 | QLF3(V_16B, V_16B, V_16B), \ | |
| 868 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 869 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 870 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 871 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 872 | } | |
| 873 | ||
| 874 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 875 | #define QL_V2NARRS \ | |
| 876 | { \ | |
| 877 | QLF2(V_2S , V_2D ), \ | |
| 878 | } | |
| 879 | ||
| 880 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 881 | #define QL_V2NARRS2 \ | |
| 882 | { \ | |
| 883 | QLF2(V_4S , V_2D ), \ | |
| 884 | } | |
| 885 | ||
| 886 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 887 | #define QL_V2NARRHS \ | |
| 888 | { \ | |
| 889 | QLF2(V_4H , V_4S ), \ | |
| 890 | QLF2(V_2S , V_2D ), \ | |
| 891 | } | |
| 892 | ||
| 893 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 894 | #define QL_V2NARRHS2 \ | |
| 895 | { \ | |
| 896 | QLF2(V_8H , V_4S ), \ | |
| 897 | QLF2(V_4S , V_2D ), \ | |
| 898 | } | |
| 899 | ||
| 900 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 901 | #define QL_V2LONGHS \ | |
| 902 | { \ | |
| 903 | QLF2(V_4S , V_4H ), \ | |
| 904 | QLF2(V_2D , V_2S ), \ | |
| 905 | } | |
| 906 | ||
| 907 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 908 | #define QL_V2LONGHS2 \ | |
| 909 | { \ | |
| 910 | QLF2(V_4S , V_8H ), \ | |
| 911 | QLF2(V_2D , V_4S ), \ | |
| 912 | } | |
| 913 | ||
| 914 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 915 | #define QL_V2NARRBHS \ | |
| 916 | { \ | |
| 917 | QLF2(V_8B , V_8H ), \ | |
| 918 | QLF2(V_4H , V_4S ), \ | |
| 919 | QLF2(V_2S , V_2D ), \ | |
| 920 | } | |
| 921 | ||
| 922 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 923 | #define QL_V2NARRBHS2 \ | |
| 924 | { \ | |
| 925 | QLF2(V_16B, V_8H ), \ | |
| 926 | QLF2(V_8H , V_4S ), \ | |
| 927 | QLF2(V_4S , V_2D ), \ | |
| 928 | } | |
| 929 | ||
| 930 | /* e.g. ORR. */ | |
| 931 | #define QL_V2SAMEB \ | |
| 932 | { \ | |
| 933 | QLF2(V_8B , V_8B ), \ | |
| 934 | QLF2(V_16B, V_16B), \ | |
| 935 | } | |
| 936 | ||
| 937 | /* e.g. AESE. */ | |
| 938 | #define QL_V2SAME16B \ | |
| 939 | { \ | |
| 940 | QLF2(V_16B, V_16B), \ | |
| 941 | } | |
| 942 | ||
| 943 | /* e.g. SHA1SU1. */ | |
| 944 | #define QL_V2SAME4S \ | |
| 945 | { \ | |
| 946 | QLF2(V_4S, V_4S), \ | |
| 947 | } | |
| 948 | ||
| 949 | /* e.g. SHA1SU0. */ | |
| 950 | #define QL_V3SAME4S \ | |
| 951 | { \ | |
| 952 | QLF3(V_4S, V_4S, V_4S), \ | |
| 953 | } | |
| 954 | ||
| 955 | /* e.g. SHADD. */ | |
| 956 | #define QL_V3SAMEB \ | |
| 957 | { \ | |
| 958 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 959 | QLF3(V_16B, V_16B, V_16B), \ | |
| 960 | } | |
| 961 | ||
| 962 | /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */ | |
| 963 | #define QL_VEXT \ | |
| 964 | { \ | |
| 965 | QLF4(V_8B , V_8B , V_8B , imm_0_7), \ | |
| 966 | QLF4(V_16B, V_16B, V_16B, imm_0_15), \ | |
| 967 | } | |
| 968 | ||
| 969 | /* e.g. . */ | |
| 970 | #define QL_V3SAMEHS \ | |
| 971 | { \ | |
| 972 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 973 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 974 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 975 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 976 | } | |
| 977 | ||
| 978 | /* */ | |
| 979 | #define QL_V3SAMESD \ | |
| 980 | { \ | |
| 981 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 982 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 983 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 984 | } | |
| 985 | ||
| c2c4ff8d SN |
986 | /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */ |
| 987 | #define QL_V3SAMEHSD_ROT \ | |
| 988 | { \ | |
| 989 | QLF4 (V_4H, V_4H, V_4H, NIL), \ | |
| 990 | QLF4 (V_8H, V_8H, V_8H, NIL), \ | |
| 991 | QLF4 (V_2S, V_2S, V_2S, NIL), \ | |
| 992 | QLF4 (V_4S, V_4S, V_4S, NIL), \ | |
| 993 | QLF4 (V_2D, V_2D, V_2D, NIL), \ | |
| 994 | } | |
| 995 | ||
| 51d543ed MW |
996 | /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */ |
| 997 | #define QL_V3SAMEH \ | |
| 998 | { \ | |
| 999 | QLF3 (V_4H , V_4H , V_4H ), \ | |
| 1000 | QLF3 (V_8H , V_8H , V_8H ), \ | |
| 1001 | } | |
| 1002 | ||
| a06ea964 NC |
1003 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
| 1004 | #define QL_V3LONGHS \ | |
| 1005 | { \ | |
| 1006 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 1007 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 1008 | } | |
| 1009 | ||
| 1010 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 1011 | #define QL_V3LONGHS2 \ | |
| 1012 | { \ | |
| 1013 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 1014 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 1015 | } | |
| 1016 | ||
| 1017 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 1018 | #define QL_V3LONGBHS \ | |
| 1019 | { \ | |
| 1020 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 1021 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 1022 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 1023 | } | |
| 1024 | ||
| 1025 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 1026 | #define QL_V3LONGBHS2 \ | |
| 1027 | { \ | |
| 1028 | QLF3(V_8H , V_16B , V_16B ), \ | |
| 1029 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 1030 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 1031 | } | |
| 1032 | ||
| 1033 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
| 1034 | #define QL_V3WIDEBHS \ | |
| 1035 | { \ | |
| 1036 | QLF3(V_8H , V_8H , V_8B ), \ | |
| 1037 | QLF3(V_4S , V_4S , V_4H ), \ | |
| 1038 | QLF3(V_2D , V_2D , V_2S ), \ | |
| 1039 | } | |
| 1040 | ||
| 1041 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
| 1042 | #define QL_V3WIDEBHS2 \ | |
| 1043 | { \ | |
| 1044 | QLF3(V_8H , V_8H , V_16B ), \ | |
| 1045 | QLF3(V_4S , V_4S , V_8H ), \ | |
| 1046 | QLF3(V_2D , V_2D , V_4S ), \ | |
| 1047 | } | |
| 1048 | ||
| 1049 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
| 1050 | #define QL_V3NARRBHS \ | |
| 1051 | { \ | |
| 1052 | QLF3(V_8B , V_8H , V_8H ), \ | |
| 1053 | QLF3(V_4H , V_4S , V_4S ), \ | |
| 1054 | QLF3(V_2S , V_2D , V_2D ), \ | |
| 1055 | } | |
| 1056 | ||
| 1057 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
| 1058 | #define QL_V3NARRBHS2 \ | |
| 1059 | { \ | |
| 1060 | QLF3(V_16B , V_8H , V_8H ), \ | |
| 1061 | QLF3(V_8H , V_4S , V_4S ), \ | |
| 1062 | QLF3(V_4S , V_2D , V_2D ), \ | |
| 1063 | } | |
| 1064 | ||
| 1065 | /* e.g. PMULL. */ | |
| 1066 | #define QL_V3LONGB \ | |
| 1067 | { \ | |
| 1068 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 1069 | } | |
| 1070 | ||
| 1071 | /* e.g. PMULL crypto. */ | |
| 1072 | #define QL_V3LONGD \ | |
| 1073 | { \ | |
| 1074 | QLF3(V_1Q , V_1D , V_1D ), \ | |
| 1075 | } | |
| 1076 | ||
| 1077 | /* e.g. PMULL2. */ | |
| 1078 | #define QL_V3LONGB2 \ | |
| 1079 | { \ | |
| 1080 | QLF3(V_8H , V_16B, V_16B), \ | |
| 1081 | } | |
| 1082 | ||
| 1083 | /* e.g. PMULL2 crypto. */ | |
| 1084 | #define QL_V3LONGD2 \ | |
| 1085 | { \ | |
| 1086 | QLF3(V_1Q , V_2D , V_2D ), \ | |
| 1087 | } | |
| 1088 | ||
| 1089 | /* e.g. SHA1C. */ | |
| 1090 | #define QL_SHAUPT \ | |
| 1091 | { \ | |
| 1092 | QLF3(S_Q, S_S, V_4S), \ | |
| 1093 | } | |
| 1094 | ||
| 1095 | /* e.g. SHA256H2. */ | |
| 1096 | #define QL_SHA256UPT \ | |
| 1097 | { \ | |
| 1098 | QLF3(S_Q, S_Q, V_4S), \ | |
| 1099 | } | |
| 1100 | ||
| 1101 | /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */ | |
| 1102 | #define QL_W1_LDST_EXC \ | |
| 1103 | { \ | |
| 1104 | QLF2(W, NIL), \ | |
| 1105 | } | |
| 1106 | ||
| 1107 | /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */ | |
| 1108 | #define QL_R1NIL \ | |
| 1109 | { \ | |
| 1110 | QLF2(W, NIL), \ | |
| 1111 | QLF2(X, NIL), \ | |
| 1112 | } | |
| 1113 | ||
| 1114 | /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
| 1115 | #define QL_W2_LDST_EXC \ | |
| 1116 | { \ | |
| 1117 | QLF3(W, W, NIL), \ | |
| 1118 | } | |
| 1119 | ||
| 1120 | /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */ | |
| 1121 | #define QL_R2_LDST_EXC \ | |
| 1122 | { \ | |
| 1123 | QLF3(W, W, NIL), \ | |
| 1124 | QLF3(W, X, NIL), \ | |
| 1125 | } | |
| 1126 | ||
| 3f06e550 SN |
1127 | /* e.g. LDRAA <Xt>, [<Xn|SP>{,#imm}]. */ |
| 1128 | #define QL_X1NIL \ | |
| 1129 | { \ | |
| 1130 | QLF2(X, NIL), \ | |
| 1131 | } | |
| 1132 | ||
| a06ea964 NC |
1133 | /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| 1134 | #define QL_R2NIL \ | |
| 1135 | { \ | |
| 1136 | QLF3(W, W, NIL), \ | |
| 1137 | QLF3(X, X, NIL), \ | |
| 1138 | } | |
| 1139 | ||
| ee804238 JW |
1140 | /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ |
| 1141 | #define QL_R4NIL \ | |
| 1142 | { \ | |
| 1143 | QLF5(W, W, W, W, NIL), \ | |
| 1144 | QLF5(X, X, X, X, NIL), \ | |
| 1145 | } | |
| 1146 | ||
| a06ea964 NC |
1147 | /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| 1148 | #define QL_R3_LDST_EXC \ | |
| 1149 | { \ | |
| 1150 | QLF4(W, W, W, NIL), \ | |
| 1151 | QLF4(W, X, X, NIL), \ | |
| 1152 | } | |
| 1153 | ||
| 1154 | /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1155 | #define QL_LDST_FP \ | |
| 1156 | { \ | |
| 1157 | QLF2(S_B, S_B), \ | |
| 1158 | QLF2(S_H, S_H), \ | |
| 1159 | QLF2(S_S, S_S), \ | |
| 1160 | QLF2(S_D, S_D), \ | |
| 1161 | QLF2(S_Q, S_Q), \ | |
| 1162 | } | |
| 1163 | ||
| 1164 | /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1165 | #define QL_LDST_R \ | |
| 1166 | { \ | |
| 1167 | QLF2(W, S_S), \ | |
| 1168 | QLF2(X, S_D), \ | |
| 1169 | } | |
| 1170 | ||
| 1171 | /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1172 | #define QL_LDST_W8 \ | |
| 1173 | { \ | |
| 1174 | QLF2(W, S_B), \ | |
| 1175 | } | |
| 1176 | ||
| 1177 | /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1178 | #define QL_LDST_R8 \ | |
| 1179 | { \ | |
| 1180 | QLF2(W, S_B), \ | |
| 1181 | QLF2(X, S_B), \ | |
| 1182 | } | |
| 1183 | ||
| 1184 | /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1185 | #define QL_LDST_W16 \ | |
| 1186 | { \ | |
| 1187 | QLF2(W, S_H), \ | |
| 1188 | } | |
| 1189 | ||
| 1190 | /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1191 | #define QL_LDST_X32 \ | |
| 1192 | { \ | |
| 1193 | QLF2(X, S_S), \ | |
| 1194 | } | |
| 1195 | ||
| 1196 | /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1197 | #define QL_LDST_R16 \ | |
| 1198 | { \ | |
| 1199 | QLF2(W, S_H), \ | |
| 1200 | QLF2(X, S_H), \ | |
| 1201 | } | |
| 1202 | ||
| 1203 | /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1204 | #define QL_LDST_PRFM \ | |
| 1205 | { \ | |
| 1206 | QLF2(NIL, S_D), \ | |
| 1207 | } | |
| 1208 | ||
| 1209 | /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ | |
| 1210 | #define QL_LDST_PAIR_X32 \ | |
| 1211 | { \ | |
| 1212 | QLF3(X, X, S_S), \ | |
| 1213 | } | |
| 1214 | ||
| 1215 | /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */ | |
| 1216 | #define QL_LDST_PAIR_R \ | |
| 1217 | { \ | |
| 1218 | QLF3(W, W, S_S), \ | |
| 1219 | QLF3(X, X, S_D), \ | |
| 1220 | } | |
| 1221 | ||
| 1222 | /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ | |
| 1223 | #define QL_LDST_PAIR_FP \ | |
| 1224 | { \ | |
| 1225 | QLF3(S_S, S_S, S_S), \ | |
| 1226 | QLF3(S_D, S_D, S_D), \ | |
| 1227 | QLF3(S_Q, S_Q, S_Q), \ | |
| 1228 | } | |
| 1229 | ||
| 1230 | /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
| 1231 | #define QL_SIMD_LDST \ | |
| 1232 | { \ | |
| 1233 | QLF2(V_8B, NIL), \ | |
| 1234 | QLF2(V_16B, NIL), \ | |
| 1235 | QLF2(V_4H, NIL), \ | |
| 1236 | QLF2(V_8H, NIL), \ | |
| 1237 | QLF2(V_2S, NIL), \ | |
| 1238 | QLF2(V_4S, NIL), \ | |
| 1239 | QLF2(V_2D, NIL), \ | |
| 1240 | } | |
| 1241 | ||
| 1242 | /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
| 1243 | #define QL_SIMD_LDST_ANY \ | |
| 1244 | { \ | |
| 1245 | QLF2(V_8B, NIL), \ | |
| 1246 | QLF2(V_16B, NIL), \ | |
| 1247 | QLF2(V_4H, NIL), \ | |
| 1248 | QLF2(V_8H, NIL), \ | |
| 1249 | QLF2(V_2S, NIL), \ | |
| 1250 | QLF2(V_4S, NIL), \ | |
| 1251 | QLF2(V_1D, NIL), \ | |
| 1252 | QLF2(V_2D, NIL), \ | |
| 1253 | } | |
| 1254 | ||
| 1255 | /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */ | |
| 1256 | #define QL_SIMD_LDSTONE \ | |
| 1257 | { \ | |
| 1258 | QLF2(S_B, NIL), \ | |
| 1259 | QLF2(S_H, NIL), \ | |
| 1260 | QLF2(S_S, NIL), \ | |
| 1261 | QLF2(S_D, NIL), \ | |
| 1262 | } | |
| 1263 | ||
| 1264 | /* e.g. ADDV <V><d>, <Vn>.<T>. */ | |
| 1265 | #define QL_XLANES \ | |
| 1266 | { \ | |
| 1267 | QLF2(S_B, V_8B), \ | |
| 1268 | QLF2(S_B, V_16B), \ | |
| 1269 | QLF2(S_H, V_4H), \ | |
| 1270 | QLF2(S_H, V_8H), \ | |
| 1271 | QLF2(S_S, V_4S), \ | |
| 1272 | } | |
| 1273 | ||
| 1274 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ | |
| 1275 | #define QL_XLANES_FP \ | |
| 1276 | { \ | |
| 1277 | QLF2(S_S, V_4S), \ | |
| 1278 | } | |
| 1279 | ||
| bb515fea MW |
1280 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ |
| 1281 | #define QL_XLANES_FP_H \ | |
| 1282 | { \ | |
| 1283 | QLF2 (S_H, V_4H), \ | |
| 1284 | QLF2 (S_H, V_8H), \ | |
| 1285 | } | |
| 1286 | ||
| a06ea964 NC |
1287 | /* e.g. SADDLV <V><d>, <Vn>.<T>. */ |
| 1288 | #define QL_XLANES_L \ | |
| 1289 | { \ | |
| 1290 | QLF2(S_H, V_8B), \ | |
| 1291 | QLF2(S_H, V_16B), \ | |
| 1292 | QLF2(S_S, V_4H), \ | |
| 1293 | QLF2(S_S, V_8H), \ | |
| 1294 | QLF2(S_D, V_4S), \ | |
| 1295 | } | |
| 1296 | ||
| 1297 | /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */ | |
| 1298 | #define QL_ELEMENT \ | |
| 1299 | { \ | |
| 1300 | QLF3(V_4H, V_4H, S_H), \ | |
| 1301 | QLF3(V_8H, V_8H, S_H), \ | |
| 1302 | QLF3(V_2S, V_2S, S_S), \ | |
| 1303 | QLF3(V_4S, V_4S, S_S), \ | |
| 1304 | } | |
| 1305 | ||
| 1306 | /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
| 1307 | #define QL_ELEMENT_L \ | |
| 1308 | { \ | |
| 1309 | QLF3(V_4S, V_4H, S_H), \ | |
| 1310 | QLF3(V_2D, V_2S, S_S), \ | |
| 1311 | } | |
| 1312 | ||
| 1313 | /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
| 1314 | #define QL_ELEMENT_L2 \ | |
| 1315 | { \ | |
| 1316 | QLF3(V_4S, V_8H, S_H), \ | |
| 1317 | QLF3(V_2D, V_4S, S_S), \ | |
| 1318 | } | |
| 1319 | ||
| 1320 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ | |
| 1321 | #define QL_ELEMENT_FP \ | |
| 1322 | { \ | |
| 1323 | QLF3(V_2S, V_2S, S_S), \ | |
| 1324 | QLF3(V_4S, V_4S, S_S), \ | |
| 1325 | QLF3(V_2D, V_2D, S_D), \ | |
| 1326 | } | |
| 1327 | ||
| 42f23f62 MW |
1328 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ |
| 1329 | #define QL_ELEMENT_FP_H \ | |
| 1330 | { \ | |
| 1331 | QLF3 (V_4H, V_4H, S_H), \ | |
| 1332 | QLF3 (V_8H, V_8H, S_H), \ | |
| 1333 | } | |
| 1334 | ||
| c2c4ff8d SN |
1335 | /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>. */ |
| 1336 | #define QL_ELEMENT_ROT \ | |
| 1337 | { \ | |
| 1338 | QLF4 (V_4H, V_4H, S_H, NIL), \ | |
| 1339 | QLF4 (V_8H, V_8H, S_H, NIL), \ | |
| 1340 | QLF4 (V_4S, V_4S, S_S, NIL), \ | |
| 1341 | } | |
| 1342 | ||
| a06ea964 NC |
1343 | /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ |
| 1344 | #define QL_SIMD_IMM_S0W \ | |
| 1345 | { \ | |
| 1346 | QLF2(V_2S, LSL), \ | |
| 1347 | QLF2(V_4S, LSL), \ | |
| 1348 | } | |
| 1349 | ||
| 1350 | /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */ | |
| 1351 | #define QL_SIMD_IMM_S1W \ | |
| 1352 | { \ | |
| 1353 | QLF2(V_2S, MSL), \ | |
| 1354 | QLF2(V_4S, MSL), \ | |
| 1355 | } | |
| 1356 | ||
| 1357 | /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */ | |
| 1358 | #define QL_SIMD_IMM_S0H \ | |
| 1359 | { \ | |
| 1360 | QLF2(V_4H, LSL), \ | |
| 1361 | QLF2(V_8H, LSL), \ | |
| 1362 | } | |
| 1363 | ||
| 1364 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ | |
| 1365 | #define QL_SIMD_IMM_S \ | |
| 1366 | { \ | |
| 1367 | QLF2(V_2S, NIL), \ | |
| 1368 | QLF2(V_4S, NIL), \ | |
| 1369 | } | |
| 1370 | ||
| f5555712 | 1371 | /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ |
| a06ea964 NC |
1372 | #define QL_SIMD_IMM_B \ |
| 1373 | { \ | |
| f5555712 YZ |
1374 | QLF2(V_8B, LSL), \ |
| 1375 | QLF2(V_16B, LSL), \ | |
| a06ea964 NC |
1376 | } |
| 1377 | /* e.g. MOVI <Dd>, #<imm>. */ | |
| 1378 | #define QL_SIMD_IMM_D \ | |
| 1379 | { \ | |
| 1380 | QLF2(S_D, NIL), \ | |
| 1381 | } | |
| 1382 | ||
| 4b5fc357 MW |
1383 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ |
| 1384 | #define QL_SIMD_IMM_H \ | |
| 1385 | { \ | |
| 1386 | QLF2 (V_4H, NIL), \ | |
| 1387 | QLF2 (V_8H, NIL), \ | |
| 1388 | } | |
| 1389 | ||
| a06ea964 NC |
1390 | /* e.g. MOVI <Vd>.2D, #<imm>. */ |
| 1391 | #define QL_SIMD_IMM_V2D \ | |
| 1392 | { \ | |
| 1393 | QLF2(V_2D, NIL), \ | |
| 1394 | } | |
| c0890d26 RS |
1395 | |
| 1396 | /* The naming convention for SVE macros is: | |
| 1397 | ||
| 1398 | OP_SVE_<operands>[_<sizes>]* | |
| 1399 | ||
| 1400 | <operands> contains one character per operand, using the following scheme: | |
| 1401 | ||
| 1402 | - U: the operand is unqualified (NIL). | |
| 1403 | ||
| 1404 | - [BHSD]: the operand has a S_[BHSD] qualifier and the choice of | |
| 1405 | qualifier is the same for all variants. This is used for both | |
| 1406 | .[BHSD] suffixes on an SVE predicate or vector register and | |
| 1407 | scalar FPRs of the form [BHSD]<number>. | |
| 1408 | ||
| 1409 | - [WX]: the operand has a [WX] qualifier and the choice of qualifier | |
| 1410 | is the same for all variants. | |
| 1411 | ||
| 1412 | - [ZM]: the operand has a /[ZM] suffix and the choice of suffix | |
| 1413 | is the same for all variants. | |
| 1414 | ||
| 1415 | - V: the operand has a S_[BHSD] qualifier and the choice of qualifier | |
| 1416 | is not the same for all variants. | |
| 1417 | ||
| 1418 | - R: the operand has a [WX] qualifier and the choice of qualifier is | |
| 1419 | not the same for all variants. | |
| 1420 | ||
| 1421 | - P: the operand has a /[ZM] suffix and the choice of suffix is not | |
| 1422 | the same for all variants. | |
| 1423 | ||
| 1424 | The _<sizes>, if present, give the subset of [BHSD] that are accepted | |
| 1425 | by the V entries in <operands>. */ | |
| 1426 | #define OP_SVE_B \ | |
| 1427 | { \ | |
| 1428 | QLF1(S_B), \ | |
| 1429 | } | |
| 1430 | #define OP_SVE_BB \ | |
| 1431 | { \ | |
| 1432 | QLF2(S_B,S_B), \ | |
| 1433 | } | |
| 1434 | #define OP_SVE_BBBU \ | |
| 1435 | { \ | |
| 1436 | QLF4(S_B,S_B,S_B,NIL), \ | |
| 1437 | } | |
| 1438 | #define OP_SVE_BMB \ | |
| 1439 | { \ | |
| 1440 | QLF3(S_B,P_M,S_B), \ | |
| 1441 | } | |
| 1442 | #define OP_SVE_BPB \ | |
| 1443 | { \ | |
| 1444 | QLF3(S_B,P_Z,S_B), \ | |
| 1445 | QLF3(S_B,P_M,S_B), \ | |
| 1446 | } | |
| 1447 | #define OP_SVE_BUB \ | |
| 1448 | { \ | |
| 1449 | QLF3(S_B,NIL,S_B), \ | |
| 1450 | } | |
| 1451 | #define OP_SVE_BUBB \ | |
| 1452 | { \ | |
| 1453 | QLF4(S_B,NIL,S_B,S_B), \ | |
| 1454 | } | |
| 1455 | #define OP_SVE_BUU \ | |
| 1456 | { \ | |
| 1457 | QLF3(S_B,NIL,NIL), \ | |
| 1458 | } | |
| 1459 | #define OP_SVE_BZ \ | |
| 1460 | { \ | |
| 1461 | QLF2(S_B,P_Z), \ | |
| 1462 | } | |
| 1463 | #define OP_SVE_BZB \ | |
| 1464 | { \ | |
| 1465 | QLF3(S_B,P_Z,S_B), \ | |
| 1466 | } | |
| 1467 | #define OP_SVE_BZBB \ | |
| 1468 | { \ | |
| 1469 | QLF4(S_B,P_Z,S_B,S_B), \ | |
| 1470 | } | |
| 1471 | #define OP_SVE_BZU \ | |
| 1472 | { \ | |
| 1473 | QLF3(S_B,P_Z,NIL), \ | |
| 1474 | } | |
| 1475 | #define OP_SVE_DD \ | |
| 1476 | { \ | |
| 1477 | QLF2(S_D,S_D), \ | |
| 1478 | } | |
| 1479 | #define OP_SVE_DDD \ | |
| 1480 | { \ | |
| 1481 | QLF3(S_D,S_D,S_D), \ | |
| 1482 | } | |
| 1483 | #define OP_SVE_DMD \ | |
| 1484 | { \ | |
| 1485 | QLF3(S_D,P_M,S_D), \ | |
| 1486 | } | |
| 1487 | #define OP_SVE_DMH \ | |
| 1488 | { \ | |
| 1489 | QLF3(S_D,P_M,S_H), \ | |
| 1490 | } | |
| 1491 | #define OP_SVE_DMS \ | |
| 1492 | { \ | |
| 1493 | QLF3(S_D,P_M,S_S), \ | |
| 1494 | } | |
| 1495 | #define OP_SVE_DU \ | |
| 1496 | { \ | |
| 1497 | QLF2(S_D,NIL), \ | |
| 1498 | } | |
| 1499 | #define OP_SVE_DUD \ | |
| 1500 | { \ | |
| 1501 | QLF3(S_D,NIL,S_D), \ | |
| 1502 | } | |
| 1503 | #define OP_SVE_DUU \ | |
| 1504 | { \ | |
| 1505 | QLF3(S_D,NIL,NIL), \ | |
| 1506 | } | |
| 1507 | #define OP_SVE_DUV_BHS \ | |
| 1508 | { \ | |
| 1509 | QLF3(S_D,NIL,S_B), \ | |
| 1510 | QLF3(S_D,NIL,S_H), \ | |
| 1511 | QLF3(S_D,NIL,S_S), \ | |
| 1512 | } | |
| 1513 | #define OP_SVE_DUV_BHSD \ | |
| 1514 | { \ | |
| 1515 | QLF3(S_D,NIL,S_B), \ | |
| 1516 | QLF3(S_D,NIL,S_H), \ | |
| 1517 | QLF3(S_D,NIL,S_S), \ | |
| 1518 | QLF3(S_D,NIL,S_D), \ | |
| 1519 | } | |
| 1520 | #define OP_SVE_DZD \ | |
| 1521 | { \ | |
| 1522 | QLF3(S_D,P_Z,S_D), \ | |
| 1523 | } | |
| 1524 | #define OP_SVE_DZU \ | |
| 1525 | { \ | |
| 1526 | QLF3(S_D,P_Z,NIL), \ | |
| 1527 | } | |
| 1528 | #define OP_SVE_HB \ | |
| 1529 | { \ | |
| 1530 | QLF2(S_H,S_B), \ | |
| 1531 | } | |
| 582e12bf RS |
1532 | #define OP_SVE_HMH \ |
| 1533 | { \ | |
| 1534 | QLF3(S_H,P_M,S_H), \ | |
| 1535 | } | |
| c0890d26 RS |
1536 | #define OP_SVE_HMD \ |
| 1537 | { \ | |
| 1538 | QLF3(S_H,P_M,S_D), \ | |
| 1539 | } | |
| 1540 | #define OP_SVE_HMS \ | |
| 1541 | { \ | |
| 1542 | QLF3(S_H,P_M,S_S), \ | |
| 1543 | } | |
| 1544 | #define OP_SVE_HU \ | |
| 1545 | { \ | |
| 1546 | QLF2(S_H,NIL), \ | |
| 1547 | } | |
| 1548 | #define OP_SVE_HUU \ | |
| 1549 | { \ | |
| 1550 | QLF3(S_H,NIL,NIL), \ | |
| 1551 | } | |
| 1552 | #define OP_SVE_HZU \ | |
| 1553 | { \ | |
| 1554 | QLF3(S_H,P_Z,NIL), \ | |
| 1555 | } | |
| 1556 | #define OP_SVE_RR \ | |
| 1557 | { \ | |
| 1558 | QLF2(W,W), \ | |
| 1559 | QLF2(X,X), \ | |
| 1560 | } | |
| 1561 | #define OP_SVE_RURV_BHSD \ | |
| 1562 | { \ | |
| 1563 | QLF4(W,NIL,W,S_B), \ | |
| 1564 | QLF4(W,NIL,W,S_H), \ | |
| 1565 | QLF4(W,NIL,W,S_S), \ | |
| 1566 | QLF4(X,NIL,X,S_D), \ | |
| 1567 | } | |
| 1568 | #define OP_SVE_RUV_BHSD \ | |
| 1569 | { \ | |
| 1570 | QLF3(W,NIL,S_B), \ | |
| 1571 | QLF3(W,NIL,S_H), \ | |
| 1572 | QLF3(W,NIL,S_S), \ | |
| 1573 | QLF3(X,NIL,S_D), \ | |
| 1574 | } | |
| 1575 | #define OP_SVE_SMD \ | |
| 1576 | { \ | |
| 1577 | QLF3(S_S,P_M,S_D), \ | |
| 1578 | } | |
| 1579 | #define OP_SVE_SMH \ | |
| 1580 | { \ | |
| 1581 | QLF3(S_S,P_M,S_H), \ | |
| 1582 | } | |
| 1583 | #define OP_SVE_SMS \ | |
| 1584 | { \ | |
| 1585 | QLF3(S_S,P_M,S_S), \ | |
| 1586 | } | |
| 1587 | #define OP_SVE_SU \ | |
| 1588 | { \ | |
| 1589 | QLF2(S_S,NIL), \ | |
| 1590 | } | |
| 1591 | #define OP_SVE_SUS \ | |
| 1592 | { \ | |
| 1593 | QLF3(S_S,NIL,S_S), \ | |
| 1594 | } | |
| 1595 | #define OP_SVE_SUU \ | |
| 1596 | { \ | |
| 1597 | QLF3(S_S,NIL,NIL), \ | |
| 1598 | } | |
| 1599 | #define OP_SVE_SZS \ | |
| 1600 | { \ | |
| 1601 | QLF3(S_S,P_Z,S_S), \ | |
| 1602 | } | |
| 1603 | #define OP_SVE_SZU \ | |
| 1604 | { \ | |
| 1605 | QLF3(S_S,P_Z,NIL), \ | |
| 1606 | } | |
| 1607 | #define OP_SVE_UB \ | |
| 1608 | { \ | |
| 1609 | QLF2(NIL,S_B), \ | |
| 1610 | } | |
| 1611 | #define OP_SVE_UUD \ | |
| 1612 | { \ | |
| 1613 | QLF3(NIL,NIL,S_D), \ | |
| 1614 | } | |
| 1615 | #define OP_SVE_UUS \ | |
| 1616 | { \ | |
| 1617 | QLF3(NIL,NIL,S_S), \ | |
| 1618 | } | |
| 1619 | #define OP_SVE_VMR_BHSD \ | |
| 1620 | { \ | |
| 1621 | QLF3(S_B,P_M,W), \ | |
| 1622 | QLF3(S_H,P_M,W), \ | |
| 1623 | QLF3(S_S,P_M,W), \ | |
| 1624 | QLF3(S_D,P_M,X), \ | |
| 1625 | } | |
| 582e12bf | 1626 | #define OP_SVE_VMU_HSD \ |
| c0890d26 | 1627 | { \ |
| 582e12bf | 1628 | QLF3(S_H,P_M,NIL), \ |
| c0890d26 RS |
1629 | QLF3(S_S,P_M,NIL), \ |
| 1630 | QLF3(S_D,P_M,NIL), \ | |
| 1631 | } | |
| 1632 | #define OP_SVE_VMVD_BHS \ | |
| 1633 | { \ | |
| 1634 | QLF4(S_B,P_M,S_B,S_D), \ | |
| 1635 | QLF4(S_H,P_M,S_H,S_D), \ | |
| 1636 | QLF4(S_S,P_M,S_S,S_D), \ | |
| 1637 | } | |
| 1638 | #define OP_SVE_VMVU_BHSD \ | |
| 1639 | { \ | |
| 1640 | QLF4(S_B,P_M,S_B,NIL), \ | |
| 1641 | QLF4(S_H,P_M,S_H,NIL), \ | |
| 1642 | QLF4(S_S,P_M,S_S,NIL), \ | |
| 1643 | QLF4(S_D,P_M,S_D,NIL), \ | |
| 1644 | } | |
| 582e12bf | 1645 | #define OP_SVE_VMVU_HSD \ |
| c0890d26 | 1646 | { \ |
| 582e12bf | 1647 | QLF4(S_H,P_M,S_H,NIL), \ |
| c0890d26 RS |
1648 | QLF4(S_S,P_M,S_S,NIL), \ |
| 1649 | QLF4(S_D,P_M,S_D,NIL), \ | |
| 1650 | } | |
| 1651 | #define OP_SVE_VMVV_BHSD \ | |
| 1652 | { \ | |
| 1653 | QLF4(S_B,P_M,S_B,S_B), \ | |
| 1654 | QLF4(S_H,P_M,S_H,S_H), \ | |
| 1655 | QLF4(S_S,P_M,S_S,S_S), \ | |
| 1656 | QLF4(S_D,P_M,S_D,S_D), \ | |
| 1657 | } | |
| 582e12bf RS |
1658 | #define OP_SVE_VMVV_HSD \ |
| 1659 | { \ | |
| 1660 | QLF4(S_H,P_M,S_H,S_H), \ | |
| 1661 | QLF4(S_S,P_M,S_S,S_S), \ | |
| 1662 | QLF4(S_D,P_M,S_D,S_D), \ | |
| 1663 | } | |
| c0890d26 RS |
1664 | #define OP_SVE_VMVV_SD \ |
| 1665 | { \ | |
| 1666 | QLF4(S_S,P_M,S_S,S_S), \ | |
| 1667 | QLF4(S_D,P_M,S_D,S_D), \ | |
| 1668 | } | |
| 582e12bf RS |
1669 | #define OP_SVE_VMVVU_HSD \ |
| 1670 | { \ | |
| 1671 | QLF5(S_H,P_M,S_H,S_H,NIL), \ | |
| 1672 | QLF5(S_S,P_M,S_S,S_S,NIL), \ | |
| 1673 | QLF5(S_D,P_M,S_D,S_D,NIL), \ | |
| 1674 | } | |
| c0890d26 RS |
1675 | #define OP_SVE_VMV_BHSD \ |
| 1676 | { \ | |
| 1677 | QLF3(S_B,P_M,S_B), \ | |
| 1678 | QLF3(S_H,P_M,S_H), \ | |
| 1679 | QLF3(S_S,P_M,S_S), \ | |
| 1680 | QLF3(S_D,P_M,S_D), \ | |
| 1681 | } | |
| 1682 | #define OP_SVE_VMV_HSD \ | |
| 1683 | { \ | |
| 1684 | QLF3(S_H,P_M,S_H), \ | |
| 1685 | QLF3(S_S,P_M,S_S), \ | |
| 1686 | QLF3(S_D,P_M,S_D), \ | |
| 1687 | } | |
| 1688 | #define OP_SVE_VMV_SD \ | |
| 1689 | { \ | |
| 1690 | QLF3(S_S,P_M,S_S), \ | |
| 1691 | QLF3(S_D,P_M,S_D), \ | |
| 1692 | } | |
| 582e12bf | 1693 | #define OP_SVE_VM_HSD \ |
| c0890d26 | 1694 | { \ |
| 582e12bf | 1695 | QLF2(S_H,P_M), \ |
| c0890d26 RS |
1696 | QLF2(S_S,P_M), \ |
| 1697 | QLF2(S_D,P_M), \ | |
| 1698 | } | |
| 1699 | #define OP_SVE_VPU_BHSD \ | |
| 1700 | { \ | |
| 1701 | QLF3(S_B,P_Z,NIL), \ | |
| 1702 | QLF3(S_B,P_M,NIL), \ | |
| 1703 | QLF3(S_H,P_Z,NIL), \ | |
| 1704 | QLF3(S_H,P_M,NIL), \ | |
| 1705 | QLF3(S_S,P_Z,NIL), \ | |
| 1706 | QLF3(S_S,P_M,NIL), \ | |
| 1707 | QLF3(S_D,P_Z,NIL), \ | |
| 1708 | QLF3(S_D,P_M,NIL), \ | |
| 1709 | } | |
| 1710 | #define OP_SVE_VPV_BHSD \ | |
| 1711 | { \ | |
| 1712 | QLF3(S_B,P_Z,S_B), \ | |
| 1713 | QLF3(S_B,P_M,S_B), \ | |
| 1714 | QLF3(S_H,P_Z,S_H), \ | |
| 1715 | QLF3(S_H,P_M,S_H), \ | |
| 1716 | QLF3(S_S,P_Z,S_S), \ | |
| 1717 | QLF3(S_S,P_M,S_S), \ | |
| 1718 | QLF3(S_D,P_Z,S_D), \ | |
| 1719 | QLF3(S_D,P_M,S_D), \ | |
| 1720 | } | |
| 1721 | #define OP_SVE_VRR_BHSD \ | |
| 1722 | { \ | |
| 1723 | QLF3(S_B,W,W), \ | |
| 1724 | QLF3(S_H,W,W), \ | |
| 1725 | QLF3(S_S,W,W), \ | |
| 1726 | QLF3(S_D,X,X), \ | |
| 1727 | } | |
| 1728 | #define OP_SVE_VRU_BHSD \ | |
| 1729 | { \ | |
| 1730 | QLF3(S_B,W,NIL), \ | |
| 1731 | QLF3(S_H,W,NIL), \ | |
| 1732 | QLF3(S_S,W,NIL), \ | |
| 1733 | QLF3(S_D,X,NIL), \ | |
| 1734 | } | |
| 1735 | #define OP_SVE_VR_BHSD \ | |
| 1736 | { \ | |
| 1737 | QLF2(S_B,W), \ | |
| 1738 | QLF2(S_H,W), \ | |
| 1739 | QLF2(S_S,W), \ | |
| 1740 | QLF2(S_D,X), \ | |
| 1741 | } | |
| 1742 | #define OP_SVE_VUR_BHSD \ | |
| 1743 | { \ | |
| 1744 | QLF3(S_B,NIL,W), \ | |
| 1745 | QLF3(S_H,NIL,W), \ | |
| 1746 | QLF3(S_S,NIL,W), \ | |
| 1747 | QLF3(S_D,NIL,X), \ | |
| 1748 | } | |
| 1749 | #define OP_SVE_VUU_BHSD \ | |
| 1750 | { \ | |
| 1751 | QLF3(S_B,NIL,NIL), \ | |
| 1752 | QLF3(S_H,NIL,NIL), \ | |
| 1753 | QLF3(S_S,NIL,NIL), \ | |
| 1754 | QLF3(S_D,NIL,NIL), \ | |
| 1755 | } | |
| 1756 | #define OP_SVE_VUVV_BHSD \ | |
| 1757 | { \ | |
| 1758 | QLF4(S_B,NIL,S_B,S_B), \ | |
| 1759 | QLF4(S_H,NIL,S_H,S_H), \ | |
| 1760 | QLF4(S_S,NIL,S_S,S_S), \ | |
| 1761 | QLF4(S_D,NIL,S_D,S_D), \ | |
| 1762 | } | |
| 582e12bf | 1763 | #define OP_SVE_VUVV_HSD \ |
| c0890d26 | 1764 | { \ |
| 582e12bf | 1765 | QLF4(S_H,NIL,S_H,S_H), \ |
| c0890d26 RS |
1766 | QLF4(S_S,NIL,S_S,S_S), \ |
| 1767 | QLF4(S_D,NIL,S_D,S_D), \ | |
| 1768 | } | |
| 1769 | #define OP_SVE_VUV_BHSD \ | |
| 1770 | { \ | |
| 1771 | QLF3(S_B,NIL,S_B), \ | |
| 1772 | QLF3(S_H,NIL,S_H), \ | |
| 1773 | QLF3(S_S,NIL,S_S), \ | |
| 1774 | QLF3(S_D,NIL,S_D), \ | |
| 1775 | } | |
| 582e12bf RS |
1776 | #define OP_SVE_VUV_HSD \ |
| 1777 | { \ | |
| 1778 | QLF3(S_H,NIL,S_H), \ | |
| 1779 | QLF3(S_S,NIL,S_S), \ | |
| 1780 | QLF3(S_D,NIL,S_D), \ | |
| 1781 | } | |
| c0890d26 RS |
1782 | #define OP_SVE_VUV_SD \ |
| 1783 | { \ | |
| 1784 | QLF3(S_S,NIL,S_S), \ | |
| 1785 | QLF3(S_D,NIL,S_D), \ | |
| 1786 | } | |
| 1787 | #define OP_SVE_VU_BHSD \ | |
| 1788 | { \ | |
| 1789 | QLF2(S_B,NIL), \ | |
| 1790 | QLF2(S_H,NIL), \ | |
| 1791 | QLF2(S_S,NIL), \ | |
| 1792 | QLF2(S_D,NIL), \ | |
| 1793 | } | |
| 1794 | #define OP_SVE_VU_HSD \ | |
| 1795 | { \ | |
| 1796 | QLF2(S_H,NIL), \ | |
| 1797 | QLF2(S_S,NIL), \ | |
| 1798 | QLF2(S_D,NIL), \ | |
| 1799 | } | |
| 582e12bf | 1800 | #define OP_SVE_VU_HSD \ |
| c0890d26 | 1801 | { \ |
| 582e12bf | 1802 | QLF2(S_H,NIL), \ |
| c0890d26 RS |
1803 | QLF2(S_S,NIL), \ |
| 1804 | QLF2(S_D,NIL), \ | |
| 1805 | } | |
| 1806 | #define OP_SVE_VVD_BHS \ | |
| 1807 | { \ | |
| 1808 | QLF3(S_B,S_B,S_D), \ | |
| 1809 | QLF3(S_H,S_H,S_D), \ | |
| 1810 | QLF3(S_S,S_S,S_D), \ | |
| 1811 | } | |
| 1812 | #define OP_SVE_VVU_BHSD \ | |
| 1813 | { \ | |
| 1814 | QLF3(S_B,S_B,NIL), \ | |
| 1815 | QLF3(S_H,S_H,NIL), \ | |
| 1816 | QLF3(S_S,S_S,NIL), \ | |
| 1817 | QLF3(S_D,S_D,NIL), \ | |
| 1818 | } | |
| 582e12bf RS |
1819 | #define OP_SVE_VVVU_H \ |
| 1820 | { \ | |
| 1821 | QLF4(S_H,S_H,S_H,NIL), \ | |
| 1822 | } | |
| 1823 | #define OP_SVE_VVVU_S \ | |
| c0890d26 RS |
1824 | { \ |
| 1825 | QLF4(S_S,S_S,S_S,NIL), \ | |
| 582e12bf RS |
1826 | } |
| 1827 | #define OP_SVE_VVVU_HSD \ | |
| 1828 | { \ | |
| 1829 | QLF4(S_H,S_H,S_H,NIL), \ | |
| 1830 | QLF4(S_S,S_S,S_S,NIL), \ | |
| c0890d26 RS |
1831 | QLF4(S_D,S_D,S_D,NIL), \ |
| 1832 | } | |
| 1833 | #define OP_SVE_VVV_BHSD \ | |
| 1834 | { \ | |
| 1835 | QLF3(S_B,S_B,S_B), \ | |
| 1836 | QLF3(S_H,S_H,S_H), \ | |
| 1837 | QLF3(S_S,S_S,S_S), \ | |
| 1838 | QLF3(S_D,S_D,S_D), \ | |
| 1839 | } | |
| 582e12bf RS |
1840 | #define OP_SVE_VVV_D \ |
| 1841 | { \ | |
| 1842 | QLF3(S_D,S_D,S_D), \ | |
| 1843 | } | |
| 1844 | #define OP_SVE_VVV_D_H \ | |
| 1845 | { \ | |
| 1846 | QLF3(S_D,S_H,S_H), \ | |
| 1847 | } | |
| 1848 | #define OP_SVE_VVV_H \ | |
| c0890d26 | 1849 | { \ |
| 582e12bf RS |
1850 | QLF3(S_H,S_H,S_H), \ |
| 1851 | } | |
| 1852 | #define OP_SVE_VVV_HSD \ | |
| 1853 | { \ | |
| 1854 | QLF3(S_H,S_H,S_H), \ | |
| c0890d26 RS |
1855 | QLF3(S_S,S_S,S_S), \ |
| 1856 | QLF3(S_D,S_D,S_D), \ | |
| 1857 | } | |
| 582e12bf RS |
1858 | #define OP_SVE_VVV_S \ |
| 1859 | { \ | |
| 1860 | QLF3(S_S,S_S,S_S), \ | |
| 1861 | } | |
| 1862 | #define OP_SVE_VVV_S_B \ | |
| 1863 | { \ | |
| 1864 | QLF3(S_S,S_B,S_B), \ | |
| 1865 | } | |
| 1866 | #define OP_SVE_VVV_SD_BH \ | |
| 1867 | { \ | |
| 1868 | QLF3(S_S,S_B,S_B), \ | |
| 1869 | QLF3(S_D,S_H,S_H), \ | |
| 1870 | } | |
| c0890d26 RS |
1871 | #define OP_SVE_VV_BHSD \ |
| 1872 | { \ | |
| 1873 | QLF2(S_B,S_B), \ | |
| 1874 | QLF2(S_H,S_H), \ | |
| 1875 | QLF2(S_S,S_S), \ | |
| 1876 | QLF2(S_D,S_D), \ | |
| 1877 | } | |
| 582e12bf RS |
1878 | #define OP_SVE_VV_BHSDQ \ |
| 1879 | { \ | |
| 1880 | QLF2(S_B,S_B), \ | |
| 1881 | QLF2(S_H,S_H), \ | |
| 1882 | QLF2(S_S,S_S), \ | |
| 1883 | QLF2(S_D,S_D), \ | |
| 1884 | QLF2(S_Q,S_Q), \ | |
| 1885 | } | |
| 1886 | #define OP_SVE_VV_HSD \ | |
| 1887 | { \ | |
| 1888 | QLF2(S_H,S_H), \ | |
| 1889 | QLF2(S_S,S_S), \ | |
| 1890 | QLF2(S_D,S_D), \ | |
| 1891 | } | |
| c0890d26 RS |
1892 | #define OP_SVE_VV_HSD_BHS \ |
| 1893 | { \ | |
| 1894 | QLF2(S_H,S_B), \ | |
| 1895 | QLF2(S_S,S_H), \ | |
| 1896 | QLF2(S_D,S_S), \ | |
| 1897 | } | |
| 1898 | #define OP_SVE_VV_SD \ | |
| 1899 | { \ | |
| 1900 | QLF2(S_S,S_S), \ | |
| 1901 | QLF2(S_D,S_D), \ | |
| 1902 | } | |
| 1903 | #define OP_SVE_VWW_BHSD \ | |
| 1904 | { \ | |
| 1905 | QLF3(S_B,W,W), \ | |
| 1906 | QLF3(S_H,W,W), \ | |
| 1907 | QLF3(S_S,W,W), \ | |
| 1908 | QLF3(S_D,W,W), \ | |
| 1909 | } | |
| 1910 | #define OP_SVE_VXX_BHSD \ | |
| 1911 | { \ | |
| 1912 | QLF3(S_B,X,X), \ | |
| 1913 | QLF3(S_H,X,X), \ | |
| 1914 | QLF3(S_S,X,X), \ | |
| 1915 | QLF3(S_D,X,X), \ | |
| 1916 | } | |
| 1917 | #define OP_SVE_VZVD_BHS \ | |
| 1918 | { \ | |
| 1919 | QLF4(S_B,P_Z,S_B,S_D), \ | |
| 1920 | QLF4(S_H,P_Z,S_H,S_D), \ | |
| 1921 | QLF4(S_S,P_Z,S_S,S_D), \ | |
| 1922 | } | |
| 1923 | #define OP_SVE_VZVU_BHSD \ | |
| 1924 | { \ | |
| 1925 | QLF4(S_B,P_Z,S_B,NIL), \ | |
| 1926 | QLF4(S_H,P_Z,S_H,NIL), \ | |
| 1927 | QLF4(S_S,P_Z,S_S,NIL), \ | |
| 1928 | QLF4(S_D,P_Z,S_D,NIL), \ | |
| 1929 | } | |
| 1930 | #define OP_SVE_VZVV_BHSD \ | |
| 1931 | { \ | |
| 1932 | QLF4(S_B,P_Z,S_B,S_B), \ | |
| 1933 | QLF4(S_H,P_Z,S_H,S_H), \ | |
| 1934 | QLF4(S_S,P_Z,S_S,S_S), \ | |
| 1935 | QLF4(S_D,P_Z,S_D,S_D), \ | |
| 1936 | } | |
| 582e12bf | 1937 | #define OP_SVE_VZVV_HSD \ |
| c0890d26 | 1938 | { \ |
| 582e12bf | 1939 | QLF4(S_H,P_Z,S_H,S_H), \ |
| c0890d26 RS |
1940 | QLF4(S_S,P_Z,S_S,S_S), \ |
| 1941 | QLF4(S_D,P_Z,S_D,S_D), \ | |
| 1942 | } | |
| 582e12bf | 1943 | #define OP_SVE_VZV_HSD \ |
| c0890d26 | 1944 | { \ |
| 582e12bf | 1945 | QLF3(S_H,P_Z,S_H), \ |
| c0890d26 RS |
1946 | QLF3(S_S,P_Z,S_S), \ |
| 1947 | QLF3(S_D,P_Z,S_D), \ | |
| 1948 | } | |
| 582e12bf | 1949 | #define OP_SVE_V_HSD \ |
| c0890d26 | 1950 | { \ |
| 582e12bf | 1951 | QLF1(S_H), \ |
| c0890d26 RS |
1952 | QLF1(S_S), \ |
| 1953 | QLF1(S_D), \ | |
| 1954 | } | |
| 1955 | #define OP_SVE_WU \ | |
| 1956 | { \ | |
| 1957 | QLF2(W,NIL), \ | |
| 1958 | } | |
| 1959 | #define OP_SVE_WV_BHSD \ | |
| 1960 | { \ | |
| 1961 | QLF2(W,S_B), \ | |
| 1962 | QLF2(W,S_H), \ | |
| 1963 | QLF2(W,S_S), \ | |
| 1964 | QLF2(W,S_D), \ | |
| 1965 | } | |
| 1966 | #define OP_SVE_XU \ | |
| 1967 | { \ | |
| 1968 | QLF2(X,NIL), \ | |
| 1969 | } | |
| 1970 | #define OP_SVE_XUV_BHSD \ | |
| 1971 | { \ | |
| 1972 | QLF3(X,NIL,S_B), \ | |
| 1973 | QLF3(X,NIL,S_H), \ | |
| 1974 | QLF3(X,NIL,S_S), \ | |
| 1975 | QLF3(X,NIL,S_D), \ | |
| 1976 | } | |
| 1977 | #define OP_SVE_XVW_BHSD \ | |
| 1978 | { \ | |
| 1979 | QLF3(X,S_B,W), \ | |
| 1980 | QLF3(X,S_H,W), \ | |
| 1981 | QLF3(X,S_S,W), \ | |
| 1982 | QLF3(X,S_D,W), \ | |
| 1983 | } | |
| 1984 | #define OP_SVE_XV_BHSD \ | |
| 1985 | { \ | |
| 1986 | QLF2(X,S_B), \ | |
| 1987 | QLF2(X,S_H), \ | |
| 1988 | QLF2(X,S_S), \ | |
| 1989 | QLF2(X,S_D), \ | |
| 1990 | } | |
| 1991 | #define OP_SVE_XWU \ | |
| 1992 | { \ | |
| 1993 | QLF3(X,W,NIL), \ | |
| 1994 | } | |
| 1995 | #define OP_SVE_XXU \ | |
| 1996 | { \ | |
| 1997 | QLF3(X,X,NIL), \ | |
| 1998 | } | |
| 65a55fbb TC |
1999 | /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */ |
| 2000 | #define QL_V3DOT \ | |
| 2001 | { \ | |
| 2002 | QLF3(V_2S, V_8B, V_8B), \ | |
| 2003 | QLF3(V_4S, V_16B, V_16B),\ | |
| 2004 | } | |
| 2005 | ||
| 2006 | /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */ | |
| 2007 | #define QL_V2DOT \ | |
| 2008 | { \ | |
| 00c2093f TC |
2009 | QLF3(V_2S, V_8B, S_4B),\ |
| 2010 | QLF3(V_4S, V_16B, S_4B),\ | |
| 65a55fbb | 2011 | } |
| 1a7ed57c TC |
2012 | |
| 2013 | /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D\f. */ | |
| 2014 | #define QL_SHA512UPT \ | |
| 2015 | { \ | |
| 2016 | QLF3(S_Q, S_Q, V_2D), \ | |
| 2017 | } | |
| 2018 | ||
| 2019 | /* e.g. SHA512SU0 <Vd.2D>, <Vn>.2D\f. */ | |
| 2020 | #define QL_V2SAME2D \ | |
| 2021 | { \ | |
| 2022 | QLF2(V_2D, V_2D), \ | |
| 2023 | } | |
| 2024 | ||
| 2025 | /* e.g. SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D>. */ | |
| 2026 | #define QL_V3SAME2D \ | |
| 2027 | { \ | |
| 2028 | QLF3(V_2D, V_2D, V_2D), \ | |
| 2029 | } | |
| 2030 | ||
| 2031 | /* e.g. EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B. */ | |
| 2032 | #define QL_V4SAME16B \ | |
| 2033 | { \ | |
| 2034 | QLF4(V_16B, V_16B, V_16B, V_16B), \ | |
| 2035 | } | |
| 2036 | ||
| 2037 | /* e.g. SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S. */ | |
| 2038 | #define QL_V4SAME4S \ | |
| 2039 | { \ | |
| 2040 | QLF4(V_4S, V_4S, V_4S, V_4S), \ | |
| 2041 | } | |
| 2042 | ||
| 2043 | /* e.g. XAR <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6>. */ | |
| 2044 | #define QL_XAR \ | |
| 2045 | { \ | |
| 2046 | QLF4(V_2D, V_2D, V_2D, imm_0_63), \ | |
| 2047 | } | |
| 2048 | ||
| 2049 | /* e.g. SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]. */ | |
| 2050 | #define QL_SM3TT \ | |
| 2051 | { \ | |
| 2052 | QLF3(V_4S, V_4S, S_S),\ | |
| 2053 | } | |
| 2054 | ||
| 2055 | /* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.2H. */ | |
| 2056 | #define QL_V3FML2S \ | |
| 2057 | { \ | |
| 2058 | QLF3(V_2S, V_2H, V_2H),\ | |
| 2059 | } | |
| 2060 | ||
| 2061 | /* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.4H. */ | |
| 2062 | #define QL_V3FML4S \ | |
| 2063 | { \ | |
| 2064 | QLF3(V_4S, V_4H, V_4H),\ | |
| 2065 | } | |
| 2066 | ||
| 2067 | /* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.H[<index>]. */ | |
| 2068 | #define QL_V2FML2S \ | |
| 2069 | { \ | |
| 2070 | QLF3(V_2S, V_2H, S_H),\ | |
| 2071 | } | |
| 2072 | ||
| 2073 | /* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.H[<index>]. */ | |
| 2074 | #define QL_V2FML4S \ | |
| 2075 | { \ | |
| 2076 | QLF3(V_4S, V_4H, S_H),\ | |
| 2077 | } | |
| 2078 | ||
| 2079 | /* e.g. RMIF <Xn>, #<shift>, #<mask>. */ | |
| 2080 | #define QL_RMIF \ | |
| 2081 | { \ | |
| 2082 | QLF3(X, imm_0_63, imm_0_15),\ | |
| 2083 | } | |
| 2084 | ||
| 2085 | /* e.g. SETF8 <Wn>. */ | |
| 2086 | #define QL_SETF \ | |
| 2087 | { \ | |
| 2088 | QLF1(W), \ | |
| 2089 | } | |
| 2090 | ||
| 2091 | /* e.g. STLURB <Wt>, [<Xn|SP>{,#<simm>}]. */ | |
| 2092 | #define QL_STLW \ | |
| 2093 | { \ | |
| 2094 | QLF2(W, NIL), \ | |
| 2095 | } | |
| 2096 | ||
| 2097 | /* e.g. STLURB <Xt>, [<Xn|SP>{,#<simm>}]. */ | |
| 2098 | #define QL_STLX \ | |
| 2099 | { \ | |
| 2100 | QLF2(X, NIL), \ | |
| 2101 | } | |
| a06ea964 NC |
2102 | \f |
| 2103 | /* Opcode table. */ | |
| 2104 | ||
| 2105 | static const aarch64_feature_set aarch64_feature_v8 = | |
| 2106 | AARCH64_FEATURE (AARCH64_FEATURE_V8, 0); | |
| 2107 | static const aarch64_feature_set aarch64_feature_fp = | |
| 2108 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0); | |
| 2109 | static const aarch64_feature_set aarch64_feature_simd = | |
| 2110 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0); | |
| 2111 | static const aarch64_feature_set aarch64_feature_crypto = | |
| c0e7cef7 | 2112 | AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_AES |
| fadfa6b0 | 2113 | | AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); |
| e60bb1dd YZ |
2114 | static const aarch64_feature_set aarch64_feature_crc = |
| 2115 | AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); | |
| ee804238 JW |
2116 | static const aarch64_feature_set aarch64_feature_lse = |
| 2117 | AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); | |
| 290806fd MW |
2118 | static const aarch64_feature_set aarch64_feature_lor = |
| 2119 | AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); | |
| 9e1f0fa7 MW |
2120 | static const aarch64_feature_set aarch64_feature_rdma = |
| 2121 | AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); | |
| c8a6db6f MW |
2122 | static const aarch64_feature_set aarch64_feature_ras = |
| 2123 | AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0); | |
| d685192a MW |
2124 | static const aarch64_feature_set aarch64_feature_v8_2 = |
| 2125 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0); | |
| 3bd894a7 MW |
2126 | static const aarch64_feature_set aarch64_feature_fp_f16 = |
| 2127 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); | |
| 40d16a76 MW |
2128 | static const aarch64_feature_set aarch64_feature_simd_f16 = |
| 2129 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0); | |
| 1e6f4800 MW |
2130 | static const aarch64_feature_set aarch64_feature_stat_profile = |
| 2131 | AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0); | |
| c0890d26 RS |
2132 | static const aarch64_feature_set aarch64_feature_sve = |
| 2133 | AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0); | |
| 8787d804 SN |
2134 | static const aarch64_feature_set aarch64_feature_v8_3 = |
| 2135 | AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0); | |
| ccfc90a3 SN |
2136 | static const aarch64_feature_set aarch64_feature_fp_v8_3 = |
| 2137 | AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0); | |
| f482d304 RS |
2138 | static const aarch64_feature_set aarch64_feature_compnum = |
| 2139 | AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0); | |
| d74d4880 SN |
2140 | static const aarch64_feature_set aarch64_feature_rcpc = |
| 2141 | AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0); | |
| 65a55fbb TC |
2142 | static const aarch64_feature_set aarch64_feature_dotprod = |
| 2143 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_DOTPROD, 0); | |
| c0e7cef7 NC |
2144 | static const aarch64_feature_set aarch64_feature_sha2 = |
| 2145 | AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_SHA2, 0); | |
| 2146 | static const aarch64_feature_set aarch64_feature_aes = | |
| 2147 | AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0); | |
| b6b9ca0c TC |
2148 | static const aarch64_feature_set aarch64_feature_v8_4 = |
| 2149 | AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0); | |
| 2150 | static const aarch64_feature_set aarch64_feature_crypto_v8_2 = | |
| fadfa6b0 TC |
2151 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO |
| 2152 | | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); | |
| b6b9ca0c | 2153 | static const aarch64_feature_set aarch64_feature_sm4 = |
| fadfa6b0 TC |
2154 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4 |
| 2155 | | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); | |
| b6b9ca0c TC |
2156 | static const aarch64_feature_set aarch64_feature_sha3 = |
| 2157 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SHA2 | |
| fadfa6b0 | 2158 | | AARCH64_FEATURE_SHA3 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); |
| b6b9ca0c | 2159 | static const aarch64_feature_set aarch64_feature_fp_16_v8_2 = |
| d0f7791c TC |
2160 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16_FML |
| 2161 | | AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); | |
| 70d56181 SD |
2162 | static const aarch64_feature_set aarch64_feature_v8_5 = |
| 2163 | AARCH64_FEATURE (AARCH64_FEATURE_V8_5, 0); | |
| 13c60ad7 SD |
2164 | static const aarch64_feature_set aarch64_feature_flagmanip = |
| 2165 | AARCH64_FEATURE (AARCH64_FEATURE_FLAGMANIP, 0); | |
| 2166 | static const aarch64_feature_set aarch64_feature_frintts = | |
| 2167 | AARCH64_FEATURE (AARCH64_FEATURE_FRINTTS, 0); | |
| 68dfbb92 SD |
2168 | static const aarch64_feature_set aarch64_feature_sb = |
| 2169 | AARCH64_FEATURE (AARCH64_FEATURE_SB, 0); | |
| 2ac435d4 SD |
2170 | static const aarch64_feature_set aarch64_feature_predres = |
| 2171 | AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); | |
| ff605452 SD |
2172 | static const aarch64_feature_set aarch64_feature_bti = |
| 2173 | AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0); | |
| 73b605ec SD |
2174 | static const aarch64_feature_set aarch64_feature_memtag = |
| 2175 | AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0); | |
| 70d56181 | 2176 | |
| a06ea964 | 2177 | |
| 4bd13cde NC |
2178 | #define CORE &aarch64_feature_v8 |
| 2179 | #define FP &aarch64_feature_fp | |
| 2180 | #define SIMD &aarch64_feature_simd | |
| 2181 | #define CRYPTO &aarch64_feature_crypto | |
| 2182 | #define CRC &aarch64_feature_crc | |
| 2183 | #define LSE &aarch64_feature_lse | |
| 2184 | #define LOR &aarch64_feature_lor | |
| 2185 | #define RDMA &aarch64_feature_rdma | |
| 2186 | #define FP_F16 &aarch64_feature_fp_f16 | |
| 40d16a76 | 2187 | #define SIMD_F16 &aarch64_feature_simd_f16 |
| 4bd13cde | 2188 | #define RAS &aarch64_feature_ras |
| 1e6f4800 | 2189 | #define STAT_PROFILE &aarch64_feature_stat_profile |
| 4bd13cde | 2190 | #define ARMV8_2 &aarch64_feature_v8_2 |
| c0890d26 | 2191 | #define SVE &aarch64_feature_sve |
| 8787d804 | 2192 | #define ARMV8_3 &aarch64_feature_v8_3 |
| ccfc90a3 | 2193 | #define FP_V8_3 &aarch64_feature_fp_v8_3 |
| f482d304 | 2194 | #define COMPNUM &aarch64_feature_compnum |
| d74d4880 | 2195 | #define RCPC &aarch64_feature_rcpc |
| c0e7cef7 NC |
2196 | #define SHA2 &aarch64_feature_sha2 |
| 2197 | #define AES &aarch64_feature_aes | |
| b6b9ca0c TC |
2198 | #define ARMV8_4 &aarch64_feature_v8_4 |
| 2199 | #define SHA3 &aarch64_feature_sha3 | |
| 2200 | #define SM4 &aarch64_feature_sm4 | |
| 2201 | #define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2 | |
| 2202 | #define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2 | |
| 65a55fbb | 2203 | #define DOTPROD &aarch64_feature_dotprod |
| 70d56181 | 2204 | #define ARMV8_5 &aarch64_feature_v8_5 |
| 13c60ad7 SD |
2205 | #define FLAGMANIP &aarch64_feature_flagmanip |
| 2206 | #define FRINTTS &aarch64_feature_frintts | |
| 68dfbb92 | 2207 | #define SB &aarch64_feature_sb |
| 2ac435d4 | 2208 | #define PREDRES &aarch64_feature_predres |
| ff605452 | 2209 | #define BTI &aarch64_feature_bti |
| 73b605ec | 2210 | #define MEMTAG &aarch64_feature_memtag |
| 4bd13cde | 2211 | |
| 9d30b0bd | 2212 | #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2213 | { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 9d30b0bd | 2214 | #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2215 | { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 9d30b0bd | 2216 | #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2217 | { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2218 | #define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2219 | { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2220 | #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2221 | { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2222 | #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2223 | { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2224 | #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2225 | { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2226 | #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2227 | { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2228 | #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2229 | { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2230 | #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2231 | { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 344bde0a | 2232 | #define V8_2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2233 | { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2, OPS, QUALS, FLAGS, 0, 0, NULL } |
| c0890d26 RS |
2234 | #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
| 2235 | { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ | |
| eae424ae TC |
2236 | FLAGS | F_STRICT, 0, TIED, NULL } |
| 2237 | #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
| 2238 | { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ | |
| 2239 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
| 8787d804 | 2240 | #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2241 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, 0, NULL } |
| f482d304 | 2242 | #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2243 | { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } |
| d74d4880 | 2244 | #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2245 | { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL } |
| c0e7cef7 | 2246 | #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2247 | { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL } |
| c0e7cef7 | 2248 | #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2249 | { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c | 2250 | #define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2251 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c TC |
2252 | #define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2253 | { NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL } | |
| 2254 | #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
| eae424ae | 2255 | { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c | 2256 | #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2257 | { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c | 2258 | #define FP16_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2259 | { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 65a55fbb | 2260 | #define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2261 | { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 70d56181 SD |
2262 | #define V8_5_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2263 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 13c60ad7 SD |
2264 | #define FLAGMANIP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2265 | { NAME, OPCODE, MASK, CLASS, 0, FLAGMANIP, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 2266 | #define FRINTTS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
| 2267 | { NAME, OPCODE, MASK, CLASS, 0, FRINTTS, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 68dfbb92 SD |
2268 | #define SB_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2269 | { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 2ac435d4 SD |
2270 | #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2271 | { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| ff605452 SD |
2272 | #define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2273 | { NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 73b605ec SD |
2274 | #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2275 | { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| a06ea964 NC |
2276 | |
| 2277 | struct aarch64_opcode aarch64_opcode_table[] = | |
| 2278 | { | |
| 2279 | /* Add/subtract (with carry). */ | |
| 9d30b0bd RS |
2280 | CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
| 2281 | CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
| 2282 | CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2283 | CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), | |
| 2284 | CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2285 | CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), | |
| a06ea964 | 2286 | /* Add/subtract (extended register). */ |
| 9d30b0bd RS |
2287 | CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), |
| 2288 | CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), | |
| 2289 | CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), | |
| 2290 | CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), | |
| 2291 | CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), | |
| 2292 | CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), | |
| a06ea964 | 2293 | /* Add/subtract (immediate). */ |
| 5ce912d8 | 2294 | CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| 9d30b0bd RS |
2295 | CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), |
| 2296 | CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
| 2297 | CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), | |
| 2298 | CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF), | |
| 2299 | CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
| 2300 | CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), | |
| a06ea964 | 2301 | /* Add/subtract (shifted register). */ |
| 9d30b0bd RS |
2302 | CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
| 2303 | CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2304 | CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), | |
| 2305 | CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2306 | CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), | |
| 2307 | CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 514cd3a0 | 2308 | CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1), |
| 9d30b0bd | 2309 | CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
| a06ea964 | 2310 | /* AdvSIMD across lanes. */ |
| 9d30b0bd RS |
2311 | SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |
| 2312 | SIMD_INSN ("smaxv", 0x0e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2313 | SIMD_INSN ("sminv", 0x0e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2314 | SIMD_INSN ("addv", 0x0e31b800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2315 | SIMD_INSN ("uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), | |
| 2316 | SIMD_INSN ("umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2317 | SIMD_INSN ("uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2318 | SIMD_INSN ("fmaxnmv",0x2e30c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), | |
| 4bd13cde | 2319 | SF16_INSN ("fmaxnmv",0x0e30c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| 9d30b0bd | 2320 | SIMD_INSN ("fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| 4bd13cde | 2321 | SF16_INSN ("fmaxv", 0x0e30f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| 9d30b0bd | 2322 | SIMD_INSN ("fminnmv",0x2eb0c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| 4bd13cde | 2323 | SF16_INSN ("fminnmv",0x0eb0c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| 9d30b0bd | 2324 | SIMD_INSN ("fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| 4bd13cde | 2325 | SF16_INSN ("fminv", 0x0eb0f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| a06ea964 | 2326 | /* AdvSIMD three different. */ |
| 9d30b0bd RS |
2327 | SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| 2328 | SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2329 | SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2330 | SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2331 | SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2332 | SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2333 | SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2334 | SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2335 | SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2336 | SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2337 | SIMD_INSN ("sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2338 | SIMD_INSN ("sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2339 | SIMD_INSN ("subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2340 | SIMD_INSN ("subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2341 | SIMD_INSN ("sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2342 | SIMD_INSN ("sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2343 | SIMD_INSN ("smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2344 | SIMD_INSN ("smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2345 | SIMD_INSN ("sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
| 2346 | SIMD_INSN ("sqdmlal2",0x4e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
| 2347 | SIMD_INSN ("smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2348 | SIMD_INSN ("smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2349 | SIMD_INSN ("sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
| 2350 | SIMD_INSN ("sqdmlsl2",0x4e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
| 2351 | SIMD_INSN ("smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2352 | SIMD_INSN ("smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2353 | SIMD_INSN ("sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
| 2354 | SIMD_INSN ("sqdmull2",0x4e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
| 2355 | SIMD_INSN ("pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0), | |
| c0e7cef7 | 2356 | AES_INSN ("pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0), |
| 9d30b0bd | 2357 | SIMD_INSN ("pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0), |
| c0e7cef7 | 2358 | AES_INSN ("pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0), |
| 9d30b0bd RS |
2359 | SIMD_INSN ("uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| 2360 | SIMD_INSN ("uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2361 | SIMD_INSN ("uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2362 | SIMD_INSN ("uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2363 | SIMD_INSN ("usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2364 | SIMD_INSN ("usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2365 | SIMD_INSN ("usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2366 | SIMD_INSN ("usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2367 | SIMD_INSN ("raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2368 | SIMD_INSN ("raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2369 | SIMD_INSN ("uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2370 | SIMD_INSN ("uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2371 | SIMD_INSN ("rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2372 | SIMD_INSN ("rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2373 | SIMD_INSN ("uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2374 | SIMD_INSN ("uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2375 | SIMD_INSN ("umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2376 | SIMD_INSN ("umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2377 | SIMD_INSN ("umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2378 | SIMD_INSN ("umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2379 | SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2380 | SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| a06ea964 | 2381 | /* AdvSIMD vector x indexed element. */ |
| 369c9167 TC |
2382 | SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), |
| 2383 | SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 45a28947 TC |
2384 | SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), |
| 2385 | SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2386 | SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2387 | SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2388 | SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2389 | SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2390 | SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2391 | SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2392 | SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2393 | SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2394 | SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2395 | SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2396 | SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 9d30b0bd | 2397 | SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| 369c9167 | 2398 | SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 9d30b0bd | 2399 | SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| 369c9167 | 2400 | SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 9d30b0bd | 2401 | SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| 369c9167 | 2402 | SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 45a28947 TC |
2403 | SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), |
| 2404 | SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2405 | SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2406 | SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2407 | SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2408 | SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2409 | SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2410 | SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 9d30b0bd | 2411 | SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| 369c9167 TC |
2412 | SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 2413 | RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2414 | RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| f482d304 | 2415 | CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ), |
| a06ea964 | 2416 | /* AdvSIMD EXT. */ |
| 9d30b0bd | 2417 | SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), |
| a06ea964 | 2418 | /* AdvSIMD modified immediate. */ |
| 9d30b0bd RS |
2419 | SIMD_INSN ("movi", 0x0f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| 2420 | SIMD_INSN ("orr", 0x0f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), | |
| 2421 | SIMD_INSN ("movi", 0x0f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2422 | SIMD_INSN ("orr", 0x0f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2423 | SIMD_INSN ("movi", 0x0f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), | |
| 2424 | SIMD_INSN ("movi", 0x0f00e400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ), | |
| 2425 | SIMD_INSN ("fmov", 0x0f00f400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ), | |
| 4bd13cde | 2426 | SF16_INSN ("fmov", 0x0f00fc00, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ), |
| 9d30b0bd RS |
2427 | SIMD_INSN ("mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| 2428 | SIMD_INSN ("bic", 0x2f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), | |
| 2429 | SIMD_INSN ("mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2430 | SIMD_INSN ("bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2431 | SIMD_INSN ("mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), | |
| 2432 | SIMD_INSN ("movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ), | |
| 2433 | SIMD_INSN ("movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ), | |
| 2434 | SIMD_INSN ("fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ), | |
| a06ea964 | 2435 | /* AdvSIMD copy. */ |
| 9d30b0bd RS |
2436 | SIMD_INSN ("dup", 0x0e000400, 0xbfe0fc00, asimdins, 0, OP2 (Vd, En), QL_DUP_VX, F_T), |
| 2437 | SIMD_INSN ("dup", 0x0e000c00, 0xbfe0fc00, asimdins, 0, OP2 (Vd, Rn), QL_DUP_VR, F_T), | |
| 2438 | SIMD_INSN ("smov",0x0e002c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q), | |
| 2439 | SIMD_INSN ("umov",0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q), | |
| 2440 | SIMD_INSN ("mov", 0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q), | |
| 2441 | SIMD_INSN ("ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS), | |
| 2442 | SIMD_INSN ("mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS), | |
| 2443 | SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS), | |
| 2444 | SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_ALIAS), | |
| a06ea964 | 2445 | /* AdvSIMD two-reg misc. */ |
| 13c60ad7 SD |
2446 | FRINTTS_INSN ("frint32z", 0x0e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 2447 | FRINTTS_INSN ("frint32x", 0x2e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 2448 | FRINTTS_INSN ("frint64z", 0x0e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 2449 | FRINTTS_INSN ("frint64x", 0x2e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 9d30b0bd RS |
2450 | SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), |
| 2451 | SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
| 2452 | SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2453 | SIMD_INSN ("suqadd",0x0e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2454 | SIMD_INSN ("cls", 0x0e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), | |
| 2455 | SIMD_INSN ("cnt", 0x0e205800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
| 2456 | SIMD_INSN ("sadalp",0x0e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2457 | SIMD_INSN ("sqabs", 0x0e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2458 | SIMD_INSN ("cmgt", 0x0e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2459 | SIMD_INSN ("cmeq", 0x0e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2460 | SIMD_INSN ("cmlt", 0x0e20a800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2461 | SIMD_INSN ("abs", 0x0e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2462 | SIMD_INSN ("xtn", 0x0e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2463 | SIMD_INSN ("xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 2464 | SIMD_INSN ("sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2465 | SIMD_INSN ("sqxtn2",0x4e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 5ce912d8 RS |
2466 | SIMD_INSN ("fcvtn", 0x0e216800, 0xffbffc00, asimdmisc, OP_FCVTN, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC), |
| 2467 | SIMD_INSN ("fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC), | |
| 2468 | SIMD_INSN ("fcvtl", 0x0e217800, 0xffbffc00, asimdmisc, OP_FCVTL, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC), | |
| 2469 | SIMD_INSN ("fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC), | |
| 9d30b0bd | 2470 | SIMD_INSN ("frintn", 0x0e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2471 | SF16_INSN ("frintn", 0x0e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2472 | SIMD_INSN ("frintm", 0x0e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2473 | SF16_INSN ("frintm", 0x0e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2474 | SIMD_INSN ("fcvtns", 0x0e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2475 | SF16_INSN ("fcvtns", 0x0e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2476 | SIMD_INSN ("fcvtms", 0x0e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2477 | SF16_INSN ("fcvtms", 0x0e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2478 | SIMD_INSN ("fcvtas", 0x0e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2479 | SF16_INSN ("fcvtas", 0x0e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2480 | SIMD_INSN ("scvtf", 0x0e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2481 | SF16_INSN ("scvtf", 0x0e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2482 | SIMD_INSN ("fcmgt", 0x0ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2483 | SF16_INSN ("fcmgt", 0x0ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2484 | SIMD_INSN ("fcmeq", 0x0ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2485 | SF16_INSN ("fcmeq", 0x0ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2486 | SIMD_INSN ("fcmlt", 0x0ea0e800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2487 | SF16_INSN ("fcmlt", 0x0ef8e800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2488 | SIMD_INSN ("fabs", 0x0ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2489 | SF16_INSN ("fabs", 0x0ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2490 | SIMD_INSN ("frintp", 0x0ea18800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2491 | SF16_INSN ("frintp", 0x0ef98800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2492 | SIMD_INSN ("frintz", 0x0ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2493 | SF16_INSN ("frintz", 0x0ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2494 | SIMD_INSN ("fcvtps", 0x0ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2495 | SF16_INSN ("fcvtps", 0x0ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2496 | SIMD_INSN ("fcvtzs", 0x0ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2497 | SF16_INSN ("fcvtzs", 0x0ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2498 | SIMD_INSN ("urecpe", 0x0ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
| 2499 | SIMD_INSN ("frecpe", 0x0ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2500 | SF16_INSN ("frecpe", 0x0ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2501 | SIMD_INSN ("rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ), |
| 2502 | SIMD_INSN ("uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2503 | SIMD_INSN ("usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2504 | SIMD_INSN ("clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), | |
| 2505 | SIMD_INSN ("uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2506 | SIMD_INSN ("sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2507 | SIMD_INSN ("cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2508 | SIMD_INSN ("cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2509 | SIMD_INSN ("neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2510 | SIMD_INSN ("sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2511 | SIMD_INSN ("sqxtun2",0x6e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 2512 | SIMD_INSN ("shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ), | |
| 2513 | SIMD_INSN ("shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ), | |
| 2514 | SIMD_INSN ("uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2515 | SIMD_INSN ("uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 2516 | SIMD_INSN ("fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS, 0), | |
| 2517 | SIMD_INSN ("fcvtxn2",0x6e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS2, 0), | |
| 2518 | SIMD_INSN ("frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2519 | SF16_INSN ("frinta", 0x2e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2520 | SIMD_INSN ("frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2521 | SF16_INSN ("frintx", 0x2e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2522 | SIMD_INSN ("fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2523 | SF16_INSN ("fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2524 | SIMD_INSN ("fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2525 | SF16_INSN ("fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2526 | SIMD_INSN ("fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2527 | SF16_INSN ("fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2528 | SIMD_INSN ("ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2529 | SF16_INSN ("ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2530 | SIMD_INSN ("not", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS), |
| 2531 | SIMD_INSN ("mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS), | |
| 2532 | SIMD_INSN ("rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
| 2533 | SIMD_INSN ("fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2534 | SF16_INSN ("fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2535 | SIMD_INSN ("fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2536 | SF16_INSN ("fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2537 | SIMD_INSN ("fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2538 | SF16_INSN ("fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2539 | SIMD_INSN ("frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2540 | SF16_INSN ("frinti", 0x2ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2541 | SIMD_INSN ("fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2542 | SF16_INSN ("fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2543 | SIMD_INSN ("fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2544 | SF16_INSN ("fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2545 | SIMD_INSN ("ursqrte",0x2ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
| 2546 | SIMD_INSN ("frsqrte",0x2ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2547 | SF16_INSN ("frsqrte",0x2ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2548 | SIMD_INSN ("fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2549 | SF16_INSN ("fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| a06ea964 | 2550 | /* AdvSIMD ZIP/UZP/TRN. */ |
| 9d30b0bd RS |
2551 | SIMD_INSN ("uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| 2552 | SIMD_INSN ("trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2553 | SIMD_INSN ("zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2554 | SIMD_INSN ("uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2555 | SIMD_INSN ("trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2556 | SIMD_INSN ("zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| a06ea964 | 2557 | /* AdvSIMD three same. */ |
| 9d30b0bd RS |
2558 | SIMD_INSN ("shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| 2559 | SIMD_INSN ("sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2560 | SIMD_INSN ("srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2561 | SIMD_INSN ("shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2562 | SIMD_INSN ("sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2563 | SIMD_INSN ("cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2564 | SIMD_INSN ("cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2565 | SIMD_INSN ("sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2566 | SIMD_INSN ("sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2567 | SIMD_INSN ("srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2568 | SIMD_INSN ("sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2569 | SIMD_INSN ("smax", 0xe206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2570 | SIMD_INSN ("smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2571 | SIMD_INSN ("sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2572 | SIMD_INSN ("saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2573 | SIMD_INSN ("add", 0xe208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2574 | SIMD_INSN ("cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2575 | SIMD_INSN ("mla", 0xe209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2576 | SIMD_INSN ("mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2577 | SIMD_INSN ("smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2578 | SIMD_INSN ("sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2579 | SIMD_INSN ("sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
| 2580 | SIMD_INSN ("addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2581 | SIMD_INSN ("fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2582 | SF16_INSN ("fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2583 | SIMD_INSN ("fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2584 | SF16_INSN ("fmla", 0xe400c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2585 | SIMD_INSN ("fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2586 | SF16_INSN ("fadd", 0xe401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2587 | SIMD_INSN ("fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2588 | SF16_INSN ("fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2589 | SIMD_INSN ("fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2590 | SF16_INSN ("fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2591 | SIMD_INSN ("fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2592 | SF16_INSN ("fmax", 0xe403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2593 | SIMD_INSN ("frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2594 | SF16_INSN ("frecps", 0xe403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2595 | SIMD_INSN ("and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2596 | SIMD_INSN ("bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 2597 | SIMD_INSN ("fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2598 | SF16_INSN ("fminnm", 0xec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2599 | SIMD_INSN ("fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2600 | SF16_INSN ("fmls", 0xec00c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2601 | SIMD_INSN ("fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2602 | SF16_INSN ("fsub", 0xec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2603 | SIMD_INSN ("fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2604 | SF16_INSN ("fmin", 0xec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2605 | SIMD_INSN ("frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2606 | SF16_INSN ("frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2607 | SIMD_INSN ("orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ), |
| 5ce912d8 | 2608 | SIMD_INSN ("mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV), |
| 9d30b0bd RS |
2609 | SIMD_INSN ("orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2610 | SIMD_INSN ("uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2611 | SIMD_INSN ("uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2612 | SIMD_INSN ("urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2613 | SIMD_INSN ("uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2614 | SIMD_INSN ("uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2615 | SIMD_INSN ("cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2616 | SIMD_INSN ("cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2617 | SIMD_INSN ("ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2618 | SIMD_INSN ("uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2619 | SIMD_INSN ("urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2620 | SIMD_INSN ("uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2621 | SIMD_INSN ("umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2622 | SIMD_INSN ("umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2623 | SIMD_INSN ("uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2624 | SIMD_INSN ("uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2625 | SIMD_INSN ("sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2626 | SIMD_INSN ("cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2627 | SIMD_INSN ("mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2628 | SIMD_INSN ("pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 2629 | SIMD_INSN ("umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2630 | SIMD_INSN ("uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2631 | SIMD_INSN ("sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
| 2632 | SIMD_INSN ("fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2633 | SF16_INSN ("fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2634 | SIMD_INSN ("faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2635 | SF16_INSN ("faddp", 0x2e401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2636 | SIMD_INSN ("fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2637 | SF16_INSN ("fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2638 | SIMD_INSN ("fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2639 | SF16_INSN ("fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2640 | SIMD_INSN ("facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2641 | SF16_INSN ("facge", 0x2e402c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2642 | SIMD_INSN ("fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2643 | SF16_INSN ("fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2644 | SIMD_INSN ("fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2645 | SF16_INSN ("fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2646 | SIMD_INSN ("eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2647 | SIMD_INSN ("bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 2648 | SIMD_INSN ("fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2649 | SF16_INSN ("fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2650 | SIMD_INSN ("fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2651 | SF16_INSN ("fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2652 | SIMD_INSN ("fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2653 | SF16_INSN ("fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2654 | SIMD_INSN ("facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2655 | SF16_INSN ("facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2656 | SIMD_INSN ("fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2657 | SF16_INSN ("fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2658 | SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2659 | SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 9e1f0fa7 | 2660 | /* AdvSIMD three same extension. */ |
| 10bba94b TC |
2661 | RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
| 2662 | RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
| f482d304 RS |
2663 | CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ), |
| 2664 | CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ), | |
| a06ea964 | 2665 | /* AdvSIMD shift by immediate. */ |
| 9d30b0bd RS |
2666 | SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| 2667 | SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2668 | SIMD_INSN ("srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2669 | SIMD_INSN ("srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2670 | SIMD_INSN ("shl", 0xf005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2671 | SIMD_INSN ("sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2672 | SIMD_INSN ("shrn", 0xf008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2673 | SIMD_INSN ("shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2674 | SIMD_INSN ("rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2675 | SIMD_INSN ("rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2676 | SIMD_INSN ("sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2677 | SIMD_INSN ("sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2678 | SIMD_INSN ("sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2679 | SIMD_INSN ("sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2680 | SIMD_INSN ("sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), | |
| 5ce912d8 | 2681 | SIMD_INSN ("sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
| 9d30b0bd | 2682 | SIMD_INSN ("sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
| 5ce912d8 | 2683 | SIMD_INSN ("sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
| 9d30b0bd | 2684 | SIMD_INSN ("scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2685 | SF16_INSN ("scvtf", 0xf10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| 9d30b0bd | 2686 | SIMD_INSN ("fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2687 | SF16_INSN ("fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| 9d30b0bd RS |
2688 | SIMD_INSN ("ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| 2689 | SIMD_INSN ("usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2690 | SIMD_INSN ("urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2691 | SIMD_INSN ("ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2692 | SIMD_INSN ("sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2693 | SIMD_INSN ("sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2694 | SIMD_INSN ("sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2695 | SIMD_INSN ("uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2696 | SIMD_INSN ("sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2697 | SIMD_INSN ("sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2698 | SIMD_INSN ("sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2699 | SIMD_INSN ("sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2700 | SIMD_INSN ("uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2701 | SIMD_INSN ("uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2702 | SIMD_INSN ("uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2703 | SIMD_INSN ("uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2704 | SIMD_INSN ("ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), | |
| 5ce912d8 | 2705 | SIMD_INSN ("uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
| 9d30b0bd | 2706 | SIMD_INSN ("ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
| 5ce912d8 | 2707 | SIMD_INSN ("uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
| 9d30b0bd | 2708 | SIMD_INSN ("ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2709 | SF16_INSN ("ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| 9d30b0bd | 2710 | SIMD_INSN ("fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2711 | SF16_INSN ("fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| a06ea964 | 2712 | /* AdvSIMD TBL/TBX. */ |
| 9d30b0bd RS |
2713 | SIMD_INSN ("tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), |
| 2714 | SIMD_INSN ("tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), | |
| a06ea964 | 2715 | /* AdvSIMD scalar three different. */ |
| 9d30b0bd RS |
2716 | SIMD_INSN ("sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), |
| 2717 | SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), | |
| 2718 | SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), | |
| a06ea964 | 2719 | /* AdvSIMD scalar x indexed element. */ |
| 45a28947 TC |
2720 | SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), |
| 2721 | SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), | |
| 2722 | SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), | |
| 2723 | SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| 2724 | SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| 9d30b0bd | 2725 | SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), |
| 369c9167 | 2726 | SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2727 | SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), |
| 369c9167 | 2728 | SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2729 | SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), |
| 369c9167 | 2730 | SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2731 | SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), |
| 369c9167 TC |
2732 | SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 2733 | RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| 2734 | RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| a06ea964 | 2735 | /* AdvSIMD load/store multiple structures. */ |
| 9d30b0bd RS |
2736 | SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), |
| 2737 | SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2738 | SIMD_INSN ("st2", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2739 | SIMD_INSN ("st3", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| 2740 | SIMD_INSN ("ld4", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), | |
| 2741 | SIMD_INSN ("ld1", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2742 | SIMD_INSN ("ld2", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2743 | SIMD_INSN ("ld3", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| a06ea964 | 2744 | /* AdvSIMD load/store multiple structures (post-indexed). */ |
| 9d30b0bd RS |
2745 | SIMD_INSN ("st4", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), |
| 2746 | SIMD_INSN ("st1", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2747 | SIMD_INSN ("st2", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2748 | SIMD_INSN ("st3", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| 2749 | SIMD_INSN ("ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), | |
| 2750 | SIMD_INSN ("ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2751 | SIMD_INSN ("ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2752 | SIMD_INSN ("ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| a06ea964 | 2753 | /* AdvSIMD load/store single structure. */ |
| 9d30b0bd RS |
2754 | SIMD_INSN ("st1", 0xd000000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), |
| 2755 | SIMD_INSN ("st3", 0xd002000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), | |
| 2756 | SIMD_INSN ("st2", 0xd200000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), | |
| 2757 | SIMD_INSN ("st4", 0xd202000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), | |
| 2758 | SIMD_INSN ("ld1", 0xd400000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), | |
| 2759 | SIMD_INSN ("ld3", 0xd402000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), | |
| 792f174f NC |
2760 | SIMD_INSN ("ld1r", 0xd40c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), |
| 2761 | SIMD_INSN ("ld3r", 0xd40e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), | |
| 9d30b0bd RS |
2762 | SIMD_INSN ("ld2", 0xd600000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), |
| 2763 | SIMD_INSN ("ld4", 0xd602000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), | |
| 792f174f NC |
2764 | SIMD_INSN ("ld2r", 0xd60c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), |
| 2765 | SIMD_INSN ("ld4r", 0xd60e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), | |
| a06ea964 | 2766 | /* AdvSIMD load/store single structure (post-indexed). */ |
| 9d30b0bd RS |
2767 | SIMD_INSN ("st1", 0xd800000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), |
| 2768 | SIMD_INSN ("st3", 0xd802000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), | |
| 2769 | SIMD_INSN ("st2", 0xda00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), | |
| 2770 | SIMD_INSN ("st4", 0xda02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), | |
| 2771 | SIMD_INSN ("ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), | |
| 2772 | SIMD_INSN ("ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), | |
| 792f174f NC |
2773 | SIMD_INSN ("ld1r", 0xdc0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), |
| 2774 | SIMD_INSN ("ld3r", 0xdc0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), | |
| 9d30b0bd RS |
2775 | SIMD_INSN ("ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), |
| 2776 | SIMD_INSN ("ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), | |
| 792f174f NC |
2777 | SIMD_INSN ("ld2r", 0xde0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), |
| 2778 | SIMD_INSN ("ld4r", 0xde0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), | |
| a06ea964 | 2779 | /* AdvSIMD scalar two-reg misc. */ |
| 9d30b0bd RS |
2780 | SIMD_INSN ("suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), |
| 2781 | SIMD_INSN ("sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), | |
| 2782 | SIMD_INSN ("cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2783 | SIMD_INSN ("cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2784 | SIMD_INSN ("cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2785 | SIMD_INSN ("abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), | |
| 2786 | SIMD_INSN ("sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
| 2787 | SIMD_INSN ("fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), | |
| 4bd13cde | 2788 | SF16_INSN ("fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2789 | SIMD_INSN ("fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2790 | SF16_INSN ("fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2791 | SIMD_INSN ("fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2792 | SF16_INSN ("fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2793 | SIMD_INSN ("scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2794 | SF16_INSN ("scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2795 | SIMD_INSN ("fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2796 | SF16_INSN ("fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2797 | SIMD_INSN ("fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2798 | SF16_INSN ("fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2799 | SIMD_INSN ("fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2800 | SF16_INSN ("fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2801 | SIMD_INSN ("fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2802 | SF16_INSN ("fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2803 | SIMD_INSN ("fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2804 | SF16_INSN ("fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2805 | SIMD_INSN ("frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2806 | SF16_INSN ("frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2807 | SIMD_INSN ("frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2808 | SF16_INSN ("frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd RS |
2809 | SIMD_INSN ("usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), |
| 2810 | SIMD_INSN ("sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), | |
| 2811 | SIMD_INSN ("cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2812 | SIMD_INSN ("cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2813 | SIMD_INSN ("neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), | |
| 2814 | SIMD_INSN ("sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
| 2815 | SIMD_INSN ("uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
| 5ce912d8 | 2816 | SIMD_INSN ("fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC), |
| 9d30b0bd | 2817 | SIMD_INSN ("fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2818 | SF16_INSN ("fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2819 | SIMD_INSN ("fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2820 | SF16_INSN ("fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2821 | SIMD_INSN ("fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2822 | SF16_INSN ("fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2823 | SIMD_INSN ("ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2824 | SF16_INSN ("ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2825 | SIMD_INSN ("fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2826 | SF16_INSN ("fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2827 | SIMD_INSN ("fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2828 | SF16_INSN ("fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2829 | SIMD_INSN ("fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2830 | SF16_INSN ("fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2831 | SIMD_INSN ("fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2832 | SF16_INSN ("fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2833 | SIMD_INSN ("frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2834 | SF16_INSN ("frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| a06ea964 | 2835 | /* AdvSIMD scalar copy. */ |
| 9d30b0bd RS |
2836 | SIMD_INSN ("dup", 0x5e000400, 0xffe0fc00, asisdone, 0, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS), |
| 2837 | SIMD_INSN ("mov", 0x5e000400, 0xffe0fc00, asisdone, 0, OP2 (Sd, En), QL_S_2SAME, F_ALIAS), | |
| a06ea964 | 2838 | /* AdvSIMD scalar pairwise. */ |
| 9d30b0bd RS |
2839 | SIMD_INSN ("addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ), |
| 2840 | SIMD_INSN ("fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), | |
| 4bd13cde | 2841 | SF16_INSN ("fmaxnmp", 0x5e30c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2842 | SIMD_INSN ("faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2843 | SF16_INSN ("faddp", 0x5e30d800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2844 | SIMD_INSN ("fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2845 | SF16_INSN ("fmaxp", 0x5e30f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2846 | SIMD_INSN ("fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2847 | SF16_INSN ("fminnmp", 0x5eb0c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2848 | SIMD_INSN ("fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2849 | SF16_INSN ("fminp", 0x5eb0f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| a06ea964 | 2850 | /* AdvSIMD scalar three same. */ |
| 9d30b0bd RS |
2851 | SIMD_INSN ("sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), |
| 2852 | SIMD_INSN ("sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2853 | SIMD_INSN ("sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2854 | SIMD_INSN ("sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2855 | SIMD_INSN ("sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
| 2856 | SIMD_INSN ("fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), | |
| 4bd13cde | 2857 | SF16_INSN ("fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2858 | SIMD_INSN ("fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2859 | SF16_INSN ("fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2860 | SIMD_INSN ("frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2861 | SF16_INSN ("frecps", 0x5e403c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2862 | SIMD_INSN ("frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2863 | SF16_INSN ("frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd RS |
2864 | SIMD_INSN ("cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), |
| 2865 | SIMD_INSN ("cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2866 | SIMD_INSN ("sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2867 | SIMD_INSN ("srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2868 | SIMD_INSN ("add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2869 | SIMD_INSN ("cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2870 | SIMD_INSN ("uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2871 | SIMD_INSN ("uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2872 | SIMD_INSN ("uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2873 | SIMD_INSN ("uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2874 | SIMD_INSN ("sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
| 2875 | SIMD_INSN ("fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), | |
| 4bd13cde | 2876 | SF16_INSN ("fcmge", 0x7e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2877 | SIMD_INSN ("facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2878 | SF16_INSN ("facge", 0x7e402c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2879 | SIMD_INSN ("fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2880 | SF16_INSN ("fabd", 0x7ec01400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2881 | SIMD_INSN ("fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2882 | SF16_INSN ("fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2883 | SIMD_INSN ("facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2884 | SF16_INSN ("facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd RS |
2885 | SIMD_INSN ("cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), |
| 2886 | SIMD_INSN ("cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2887 | SIMD_INSN ("ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2888 | SIMD_INSN ("urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2889 | SIMD_INSN ("sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2890 | SIMD_INSN ("cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 9e1f0fa7 | 2891 | /* AdvSIMDs scalar three same extension. */ |
| 4bd13cde NC |
2892 | RDMA_INSN ("sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), |
| 2893 | RDMA_INSN ("sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
| a06ea964 | 2894 | /* AdvSIMD scalar shift by immediate. */ |
| 9d30b0bd RS |
2895 | SIMD_INSN ("sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), |
| 2896 | SIMD_INSN ("ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2897 | SIMD_INSN ("srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2898 | SIMD_INSN ("srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2899 | SIMD_INSN ("shl", 0x5f005400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), | |
| 2900 | SIMD_INSN ("sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
| 2901 | SIMD_INSN ("sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2902 | SIMD_INSN ("sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2903 | SIMD_INSN ("scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), | |
| 4bd13cde | 2904 | SF16_INSN ("scvtf", 0x5f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| 9d30b0bd | 2905 | SIMD_INSN ("fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), |
| 4bd13cde | 2906 | SF16_INSN ("fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| 9d30b0bd RS |
2907 | SIMD_INSN ("ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), |
| 2908 | SIMD_INSN ("usra", 0x7f001400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2909 | SIMD_INSN ("urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2910 | SIMD_INSN ("ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2911 | SIMD_INSN ("sri", 0x7f004400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2912 | SIMD_INSN ("sli", 0x7f005400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), | |
| 2913 | SIMD_INSN ("sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
| 2914 | SIMD_INSN ("uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
| 2915 | SIMD_INSN ("sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2916 | SIMD_INSN ("sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2917 | SIMD_INSN ("uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2918 | SIMD_INSN ("uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2919 | SIMD_INSN ("ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), | |
| 4bd13cde | 2920 | SF16_INSN ("ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| 9d30b0bd | 2921 | SIMD_INSN ("fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), |
| 4bd13cde | 2922 | SF16_INSN ("fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| a06ea964 | 2923 | /* Bitfield. */ |
| 9d30b0bd | 2924 | CORE_INSN ("sbfm", 0x13000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 RS |
2925 | CORE_INSN ("sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 2926 | CORE_INSN ("sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), | |
| 9d30b0bd RS |
2927 | CORE_INSN ("sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), |
| 2928 | CORE_INSN ("sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), | |
| 2929 | CORE_INSN ("sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3), | |
| 5ce912d8 | 2930 | CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), |
| 9d30b0bd | 2931 | CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 | 2932 | CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 344bde0a | 2933 | V8_2_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV), |
| 5ce912d8 | 2934 | CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 9d30b0bd | 2935 | CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 RS |
2936 | CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 2937 | CORE_INSN ("ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), | |
| 2938 | CORE_INSN ("uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3), | |
| 2939 | CORE_INSN ("uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3), | |
| 2940 | CORE_INSN ("lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), | |
| 2941 | CORE_INSN ("lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), | |
| a06ea964 | 2942 | /* Unconditional branch (immediate). */ |
| 5ce912d8 RS |
2943 | CORE_INSN ("b", 0x14000000, 0xfc000000, branch_imm, OP_B, OP1 (ADDR_PCREL26), QL_PCREL_26, 0), |
| 2944 | CORE_INSN ("bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, OP1 (ADDR_PCREL26), QL_PCREL_26, 0), | |
| a06ea964 | 2945 | /* Unconditional branch (register). */ |
| 9d30b0bd RS |
2946 | CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0), |
| 2947 | CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0), | |
| 2948 | CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)), | |
| 2949 | CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0), | |
| 2950 | CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0), | |
| 74f5402d SN |
2951 | V8_3_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), |
| 2952 | V8_3_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
| 2953 | V8_3_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
| 2954 | V8_3_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
| 2955 | V8_3_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 2956 | V8_3_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 2957 | V8_3_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 2958 | V8_3_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 2959 | V8_3_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| 2960 | V8_3_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| 2961 | V8_3_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| 2962 | V8_3_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| a06ea964 | 2963 | /* Compare & branch (immediate). */ |
| 9d30b0bd RS |
2964 | CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), |
| 2965 | CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), | |
| a06ea964 | 2966 | /* Conditional branch (immediate). */ |
| 9d30b0bd | 2967 | CORE_INSN ("b.c", 0x54000000, 0xff000010, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND), |
| a06ea964 | 2968 | /* Conditional compare (immediate). */ |
| 9d30b0bd RS |
2969 | CORE_INSN ("ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), |
| 2970 | CORE_INSN ("ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), | |
| a06ea964 | 2971 | /* Conditional compare (register). */ |
| 9d30b0bd RS |
2972 | CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), |
| 2973 | CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), | |
| a06ea964 | 2974 | /* Conditional select. */ |
| 9d30b0bd RS |
2975 | CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF), |
| 2976 | CORE_INSN ("csinc", 0x1a800400, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), | |
| 5ce912d8 RS |
2977 | CORE_INSN ("cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
| 2978 | CORE_INSN ("cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV), | |
| 9d30b0bd | 2979 | CORE_INSN ("csinv", 0x5a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 RS |
2980 | CORE_INSN ("cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
| 2981 | CORE_INSN ("csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV), | |
| 9d30b0bd | 2982 | CORE_INSN ("csneg", 0x5a800400, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 | 2983 | CORE_INSN ("cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
| a06ea964 | 2984 | /* Crypto AES. */ |
| c0e7cef7 NC |
2985 | AES_INSN ("aese", 0x4e284800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), |
| 2986 | AES_INSN ("aesd", 0x4e285800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
| 2987 | AES_INSN ("aesmc", 0x4e286800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
| 2988 | AES_INSN ("aesimc", 0x4e287800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
| a06ea964 | 2989 | /* Crypto two-reg SHA. */ |
| c0e7cef7 NC |
2990 | SHA2_INSN ("sha1h", 0x5e280800, 0xfffffc00, cryptosha2, OP2 (Fd, Fn), QL_2SAMES, 0), |
| 2991 | SHA2_INSN ("sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
| 2992 | SHA2_INSN ("sha256su0",0x5e282800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
| a06ea964 | 2993 | /* Crypto three-reg SHA. */ |
| c0e7cef7 NC |
2994 | SHA2_INSN ("sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), |
| 2995 | SHA2_INSN ("sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), | |
| 2996 | SHA2_INSN ("sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), | |
| 2997 | SHA2_INSN ("sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 2998 | SHA2_INSN ("sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), | |
| 2999 | SHA2_INSN ("sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), | |
| 3000 | SHA2_INSN ("sha256su1",0x5e006000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| a06ea964 | 3001 | /* Data-processing (1 source). */ |
| 9d30b0bd RS |
3002 | CORE_INSN ("rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), |
| 3003 | CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
| 3004 | CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0), | |
| 3005 | CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1), | |
| 344bde0a | 3006 | V8_2_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS), |
| 9d30b0bd RS |
3007 | CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), |
| 3008 | CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
| 3009 | CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0), | |
| a2cfc830 SN |
3010 | V8_3_INSN ("pacia", 0xdac10000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), |
| 3011 | V8_3_INSN ("pacib", 0xdac10400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3012 | V8_3_INSN ("pacda", 0xdac10800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3013 | V8_3_INSN ("pacdb", 0xdac10c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3014 | V8_3_INSN ("autia", 0xdac11000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3015 | V8_3_INSN ("autib", 0xdac11400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3016 | V8_3_INSN ("autda", 0xdac11800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3017 | V8_3_INSN ("autdb", 0xdac11c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3018 | V8_3_INSN ("paciza", 0xdac123e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3019 | V8_3_INSN ("pacizb", 0xdac127e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3020 | V8_3_INSN ("pacdza", 0xdac12be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3021 | V8_3_INSN ("pacdzb", 0xdac12fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3022 | V8_3_INSN ("autiza", 0xdac133e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3023 | V8_3_INSN ("autizb", 0xdac137e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3024 | V8_3_INSN ("autdza", 0xdac13be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3025 | V8_3_INSN ("autdzb", 0xdac13fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3026 | V8_3_INSN ("xpaci", 0xdac143e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3027 | V8_3_INSN ("xpacd", 0xdac147e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| a06ea964 | 3028 | /* Data-processing (2 source). */ |
| 9d30b0bd RS |
3029 | CORE_INSN ("udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
| 3030 | CORE_INSN ("sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
| 3031 | CORE_INSN ("lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3032 | CORE_INSN ("lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| 3033 | CORE_INSN ("lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3034 | CORE_INSN ("lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| 3035 | CORE_INSN ("asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3036 | CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| 3037 | CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3038 | CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| c84364ec | 3039 | V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0), |
| e60bb1dd | 3040 | /* CRC instructions. */ |
| 4bd13cde NC |
3041 | _CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), |
| 3042 | _CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3043 | _CRC_INSN ("crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3044 | _CRC_INSN ("crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), | |
| 3045 | _CRC_INSN ("crc32cb",0x1ac05000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3046 | _CRC_INSN ("crc32ch",0x1ac05400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3047 | _CRC_INSN ("crc32cw",0x1ac05800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3048 | _CRC_INSN ("crc32cx",0x9ac05c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), | |
| a06ea964 | 3049 | /* Data-processing (3 source). */ |
| 9d30b0bd RS |
3050 | CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), |
| 3051 | CORE_INSN ("mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), | |
| 3052 | CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), | |
| 3053 | CORE_INSN ("mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), | |
| 3054 | CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3055 | CORE_INSN ("smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3056 | CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3057 | CORE_INSN ("smnegl",0x9b20fc00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3058 | CORE_INSN ("smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), | |
| 3059 | CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3060 | CORE_INSN ("umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3061 | CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3062 | CORE_INSN ("umnegl",0x9ba0fc00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3063 | CORE_INSN ("umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), | |
| a06ea964 | 3064 | /* Excep'n generation. */ |
| 9d30b0bd RS |
3065 | CORE_INSN ("svc", 0xd4000001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), |
| 3066 | CORE_INSN ("hvc", 0xd4000002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3067 | CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3068 | CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3069 | CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3070 | CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
| 3071 | CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
| 3072 | CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
| a06ea964 | 3073 | /* Extract. */ |
| 9d30b0bd | 3074 | CORE_INSN ("extr", 0x13800000, 0x7fa00000, extract, 0, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 | 3075 | CORE_INSN ("ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV), |
| a06ea964 | 3076 | /* Floating-point<->fixed-point conversions. */ |
| 9d30b0bd | 3077 | __FP_INSN ("scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3078 | FF16_INSN ("scvtf", 0x1ec20000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3079 | __FP_INSN ("ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3080 | FF16_INSN ("ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3081 | __FP_INSN ("fcvtzs",0x1e180000, 0x7f3f0000, float2fix, 0, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), |
| 4bd13cde | 3082 | FF16_INSN ("fcvtzs",0x1ed80000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3083 | __FP_INSN ("fcvtzu",0x1e190000, 0x7f3f0000, float2fix, 0, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), |
| 4bd13cde | 3084 | FF16_INSN ("fcvtzu",0x1ed90000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), |
| a06ea964 | 3085 | /* Floating-point<->integer conversions. */ |
| 9d30b0bd | 3086 | __FP_INSN ("fcvtns",0x1e200000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3087 | FF16_INSN ("fcvtns",0x1ee00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3088 | __FP_INSN ("fcvtnu",0x1e210000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3089 | FF16_INSN ("fcvtnu",0x1ee10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3090 | __FP_INSN ("scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3091 | FF16_INSN ("scvtf", 0x1ee20000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3092 | __FP_INSN ("ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3093 | FF16_INSN ("ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3094 | __FP_INSN ("fcvtas",0x1e240000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3095 | FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3096 | __FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3097 | FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| cb366992 | 3098 | __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF), |
| 4bd13cde | 3099 | FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| cb366992 | 3100 | __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF), |
| 4bd13cde | 3101 | FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3102 | __FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3103 | FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3104 | __FP_INSN ("fcvtpu",0x1e290000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3105 | FF16_INSN ("fcvtpu",0x1ee90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3106 | __FP_INSN ("fcvtms",0x1e300000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3107 | FF16_INSN ("fcvtms",0x1ef00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3108 | __FP_INSN ("fcvtmu",0x1e310000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3109 | FF16_INSN ("fcvtmu",0x1ef10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3110 | __FP_INSN ("fcvtzs",0x1e380000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3111 | FF16_INSN ("fcvtzs",0x1ef80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3112 | __FP_INSN ("fcvtzu",0x1e390000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3113 | FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd RS |
3114 | __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0), |
| 3115 | __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0), | |
| eae424ae | 3116 | {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL }, |
| a06ea964 | 3117 | /* Floating-point conditional compare. */ |
| 9d30b0bd | 3118 | __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), |
| 4bd13cde | 3119 | FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), |
| 9d30b0bd | 3120 | __FP_INSN ("fccmpe",0x1e200410, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), |
| 4bd13cde | 3121 | FF16_INSN ("fccmpe",0x1ee00410, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), |
| a06ea964 | 3122 | /* Floating-point compare. */ |
| 9d30b0bd | 3123 | __FP_INSN ("fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3124 | FF16_INSN ("fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3125 | __FP_INSN ("fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3126 | FF16_INSN ("fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3127 | __FP_INSN ("fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), |
| 4bd13cde | 3128 | FF16_INSN ("fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3129 | __FP_INSN ("fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), |
| 4bd13cde | 3130 | FF16_INSN ("fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), |
| 13c60ad7 SD |
3131 | /* Data processing instructions ARMv8.5-A. */ |
| 3132 | FLAGMANIP_INSN ("xaflag", 0xd500403f, 0xffffffff, 0, OP0 (), {}, 0), | |
| 3133 | FLAGMANIP_INSN ("axflag", 0xd500405f, 0xffffffff, 0, OP0 (), {}, 0), | |
| 3134 | FRINTTS_INSN ("frint32z", 0x1e284000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| 3135 | FRINTTS_INSN ("frint32x", 0x1e28c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| 3136 | FRINTTS_INSN ("frint64z", 0x1e294000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| 3137 | FRINTTS_INSN ("frint64x", 0x1e29c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| a06ea964 | 3138 | /* Floating-point data-processing (1 source). */ |
| 9d30b0bd | 3139 | __FP_INSN ("fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3140 | FF16_INSN ("fmov", 0x1ee04000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3141 | __FP_INSN ("fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3142 | FF16_INSN ("fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3143 | __FP_INSN ("fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3144 | FF16_INSN ("fneg", 0x1ee14000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3145 | __FP_INSN ("fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3146 | FF16_INSN ("fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 5ce912d8 | 3147 | __FP_INSN ("fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC), |
| 9d30b0bd | 3148 | __FP_INSN ("frintn",0x1e244000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3149 | FF16_INSN ("frintn",0x1ee44000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3150 | __FP_INSN ("frintp",0x1e24c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3151 | FF16_INSN ("frintp",0x1ee4c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3152 | __FP_INSN ("frintm",0x1e254000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3153 | FF16_INSN ("frintm",0x1ee54000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3154 | __FP_INSN ("frintz",0x1e25c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3155 | FF16_INSN ("frintz",0x1ee5c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3156 | __FP_INSN ("frinta",0x1e264000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3157 | FF16_INSN ("frinta",0x1ee64000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3158 | __FP_INSN ("frintx",0x1e274000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3159 | FF16_INSN ("frintx",0x1ee74000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3160 | __FP_INSN ("frinti",0x1e27c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3161 | FF16_INSN ("frinti",0x1ee7c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| a06ea964 | 3162 | /* Floating-point data-processing (2 source). */ |
| 9d30b0bd | 3163 | __FP_INSN ("fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3164 | FF16_INSN ("fmul", 0x1ee00800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3165 | __FP_INSN ("fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3166 | FF16_INSN ("fdiv", 0x1ee01800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3167 | __FP_INSN ("fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3168 | FF16_INSN ("fadd", 0x1ee02800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3169 | __FP_INSN ("fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3170 | FF16_INSN ("fsub", 0x1ee03800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3171 | __FP_INSN ("fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3172 | FF16_INSN ("fmax", 0x1ee04800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3173 | __FP_INSN ("fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3174 | FF16_INSN ("fmin", 0x1ee05800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3175 | __FP_INSN ("fmaxnm",0x1e206800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3176 | FF16_INSN ("fmaxnm",0x1ee06800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3177 | __FP_INSN ("fminnm",0x1e207800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3178 | FF16_INSN ("fminnm",0x1ee07800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3179 | __FP_INSN ("fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3180 | FF16_INSN ("fnmul", 0x1ee08800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| a06ea964 | 3181 | /* Floating-point data-processing (3 source). */ |
| 9d30b0bd | 3182 | __FP_INSN ("fmadd", 0x1f000000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3183 | FF16_INSN ("fmadd", 0x1fc00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| 9d30b0bd | 3184 | __FP_INSN ("fmsub", 0x1f008000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3185 | FF16_INSN ("fmsub", 0x1fc08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| 9d30b0bd | 3186 | __FP_INSN ("fnmadd",0x1f200000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3187 | FF16_INSN ("fnmadd",0x1fe00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| 9d30b0bd | 3188 | __FP_INSN ("fnmsub",0x1f208000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3189 | FF16_INSN ("fnmsub",0x1fe08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| a06ea964 | 3190 | /* Floating-point immediate. */ |
| 9d30b0bd | 3191 | __FP_INSN ("fmov", 0x1e201000, 0xff201fe0, floatimm, 0, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE), |
| 4bd13cde | 3192 | FF16_INSN ("fmov", 0x1ee01000, 0xff201fe0, floatimm, OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE), |
| a06ea964 | 3193 | /* Floating-point conditional select. */ |
| 9d30b0bd | 3194 | __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE), |
| 4bd13cde | 3195 | FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE), |
| a06ea964 | 3196 | /* Load/store register (immediate indexed). */ |
| 9d30b0bd RS |
3197 | CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
| 3198 | CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
| 3199 | CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
| 3200 | CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3201 | CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3202 | CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3203 | CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3204 | CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
| 3205 | CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3206 | CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3207 | CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
| a06ea964 | 3208 | /* Load/store register (unsigned immediate). */ |
| 5ce912d8 RS |
3209 | CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0), |
| 3210 | CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0), | |
| 3211 | CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE), | |
| 3212 | CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0), | |
| 3213 | CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0), | |
| 3214 | CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0), | |
| 3215 | CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0), | |
| 3216 | CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE), | |
| 3217 | CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3218 | CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3219 | CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0), | |
| 3220 | CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0), | |
| a06ea964 | 3221 | /* Load/store register (register offset). */ |
| 9d30b0bd RS |
3222 | CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), |
| 3223 | CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), | |
| 3224 | CORE_INSN ("ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE), | |
| 3225 | CORE_INSN ("str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), | |
| 3226 | CORE_INSN ("ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), | |
| 3227 | CORE_INSN ("strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), | |
| 3228 | CORE_INSN ("ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), | |
| 3229 | CORE_INSN ("ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE), | |
| 3230 | CORE_INSN ("str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3231 | CORE_INSN ("ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3232 | CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0), | |
| 3233 | CORE_INSN ("prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0), | |
| a06ea964 | 3234 | /* Load/store register (unprivileged). */ |
| 9d30b0bd RS |
3235 | CORE_INSN ("sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
| 3236 | CORE_INSN ("ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
| 3237 | CORE_INSN ("ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
| 3238 | CORE_INSN ("sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3239 | CORE_INSN ("ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3240 | CORE_INSN ("ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
| 3241 | CORE_INSN ("sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3242 | CORE_INSN ("ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3243 | CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
| a06ea964 | 3244 | /* Load/store register (unscaled immediate). */ |
| 5ce912d8 RS |
3245 | CORE_INSN ("sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
| 3246 | CORE_INSN ("ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
| 3247 | CORE_INSN ("ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
| 3248 | CORE_INSN ("stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3249 | CORE_INSN ("ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3250 | CORE_INSN ("sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3251 | CORE_INSN ("ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3252 | CORE_INSN ("ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
| 3253 | CORE_INSN ("stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3254 | CORE_INSN ("ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3255 | CORE_INSN ("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
| 3256 | CORE_INSN ("prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0), | |
| 3f06e550 SN |
3257 | /* Load/store register (scaled signed immediate). */ |
| 3258 | V8_3_INSN ("ldraa", 0xf8200400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0), | |
| 3259 | V8_3_INSN ("ldrab", 0xf8a00400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0), | |
| a06ea964 | 3260 | /* Load/store exclusive. */ |
| 9d30b0bd RS |
3261 | CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), |
| 3262 | CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3263 | CORE_INSN ("ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3264 | CORE_INSN ("ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3265 | CORE_INSN ("stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3266 | CORE_INSN ("ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3267 | CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3268 | CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3269 | CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3270 | CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3271 | CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| f311ba7e | 3272 | CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |
| 9d30b0bd RS |
3273 | CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), |
| 3274 | CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), | |
| 3275 | CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), | |
| 3276 | CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), | |
| 3277 | CORE_INSN ("ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3278 | CORE_INSN ("ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3279 | CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), | |
| 3280 | CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), | |
| 3281 | CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3282 | CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| d74d4880 SN |
3283 | RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |
| 3284 | RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3285 | RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 290806fd | 3286 | /* Limited Ordering Regions load/store instructions. */ |
| 4bd13cde NC |
3287 | _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), |
| 3288 | _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3289 | _LOR_INSN ("ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3290 | _LOR_INSN ("stllr", 0x889f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3291 | _LOR_INSN ("stllrb", 0x089f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3292 | _LOR_INSN ("stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| a06ea964 | 3293 | /* Load/store no-allocate pair (offset). */ |
| 9d30b0bd RS |
3294 | CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
| 3295 | CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
| 3296 | CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| 3297 | CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| a06ea964 | 3298 | /* Load/store register pair (offset). */ |
| 9d30b0bd RS |
3299 | CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
| 3300 | CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
| 3301 | CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| 3302 | CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| eae424ae | 3303 | {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)}, |
| a06ea964 | 3304 | /* Load/store register pair (indexed). */ |
| 9d30b0bd RS |
3305 | CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
| 3306 | CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
| 3307 | CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| 3308 | CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| eae424ae | 3309 | {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)}, |
| a06ea964 | 3310 | /* Load register (literal). */ |
| 5ce912d8 RS |
3311 | CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q), |
| 3312 | CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0), | |
| 3313 | CORE_INSN ("ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0), | |
| 3314 | CORE_INSN ("prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0), | |
| a06ea964 | 3315 | /* Logical (immediate). */ |
| 9d30b0bd | 3316 | CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 | 3317 | CORE_INSN ("bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF), |
| 9d30b0bd | 3318 | CORE_INSN ("orr", 0x32000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 | 3319 | CORE_INSN ("mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV), |
| 9d30b0bd RS |
3320 | CORE_INSN ("eor", 0x52000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF), |
| 3321 | CORE_INSN ("ands", 0x72000000, 0x7f800000, log_imm, 0, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
| 3322 | CORE_INSN ("tst", 0x7200001f, 0x7f80001f, log_imm, 0, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF), | |
| a06ea964 | 3323 | /* Logical (shifted register). */ |
| 9d30b0bd RS |
3324 | CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
| 3325 | CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| 3326 | CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 3327 | CORE_INSN ("mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
| 5ce912d8 | 3328 | CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO), |
| 9d30b0bd RS |
3329 | CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| 3330 | CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
| 3331 | CORE_INSN ("eor", 0x4a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| 3332 | CORE_INSN ("eon", 0x4a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| 3333 | CORE_INSN ("ands", 0x6a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 3334 | CORE_INSN ("tst", 0x6a00001f, 0x7f20001f, log_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
| 3335 | CORE_INSN ("bics", 0x6a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| ee804238 | 3336 | /* LSE extension (atomic). */ |
| 4bd13cde NC |
3337 | _LSE_INSN ("casb", 0x8a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), |
| 3338 | _LSE_INSN ("cash", 0x48a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3339 | _LSE_INSN ("cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3340 | _LSE_INSN ("casab", 0x8e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3341 | _LSE_INSN ("caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3342 | _LSE_INSN ("casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3343 | _LSE_INSN ("casah", 0x48e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3344 | _LSE_INSN ("caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3345 | _LSE_INSN ("casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3346 | _LSE_INSN ("casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3347 | _LSE_INSN ("casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3348 | _LSE_INSN ("casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3349 | _LSE_INSN ("casp", 0x8207c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3350 | _LSE_INSN ("caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3351 | _LSE_INSN ("caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3352 | _LSE_INSN ("caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3353 | _LSE_INSN ("swpb", 0x38208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3354 | _LSE_INSN ("swph", 0x78208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3355 | _LSE_INSN ("swp", 0xb8208000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3356 | _LSE_INSN ("swpab", 0x38a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3357 | _LSE_INSN ("swplb", 0x38608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3358 | _LSE_INSN ("swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3359 | _LSE_INSN ("swpah", 0x78a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3360 | _LSE_INSN ("swplh", 0x78608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3361 | _LSE_INSN ("swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3362 | _LSE_INSN ("swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3363 | _LSE_INSN ("swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3364 | _LSE_INSN ("swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3365 | _LSE_INSN ("ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3366 | _LSE_INSN ("ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3367 | _LSE_INSN ("ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3368 | _LSE_INSN ("ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3369 | _LSE_INSN ("ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3370 | _LSE_INSN ("ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3371 | _LSE_INSN ("ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3372 | _LSE_INSN ("ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3373 | _LSE_INSN ("ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3374 | _LSE_INSN ("ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3375 | _LSE_INSN ("ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3376 | _LSE_INSN ("ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3377 | _LSE_INSN ("ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3378 | _LSE_INSN ("ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3379 | _LSE_INSN ("ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3380 | _LSE_INSN ("ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3381 | _LSE_INSN ("ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3382 | _LSE_INSN ("ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3383 | _LSE_INSN ("ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3384 | _LSE_INSN ("ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3385 | _LSE_INSN ("ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3386 | _LSE_INSN ("ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3387 | _LSE_INSN ("ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3388 | _LSE_INSN ("ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3389 | _LSE_INSN ("ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3390 | _LSE_INSN ("ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3391 | _LSE_INSN ("ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3392 | _LSE_INSN ("ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3393 | _LSE_INSN ("ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3394 | _LSE_INSN ("ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3395 | _LSE_INSN ("ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3396 | _LSE_INSN ("ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3397 | _LSE_INSN ("ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3398 | _LSE_INSN ("ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3399 | _LSE_INSN ("ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3400 | _LSE_INSN ("ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3401 | _LSE_INSN ("ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3402 | _LSE_INSN ("ldseth", 0x78203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3403 | _LSE_INSN ("ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3404 | _LSE_INSN ("ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3405 | _LSE_INSN ("ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3406 | _LSE_INSN ("ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3407 | _LSE_INSN ("ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3408 | _LSE_INSN ("ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3409 | _LSE_INSN ("ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3410 | _LSE_INSN ("ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3411 | _LSE_INSN ("ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3412 | _LSE_INSN ("ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3413 | _LSE_INSN ("ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3414 | _LSE_INSN ("ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3415 | _LSE_INSN ("ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3416 | _LSE_INSN ("ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3417 | _LSE_INSN ("ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3418 | _LSE_INSN ("ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3419 | _LSE_INSN ("ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3420 | _LSE_INSN ("ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3421 | _LSE_INSN ("ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3422 | _LSE_INSN ("ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3423 | _LSE_INSN ("ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3424 | _LSE_INSN ("ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3425 | _LSE_INSN ("ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3426 | _LSE_INSN ("ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3427 | _LSE_INSN ("ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3428 | _LSE_INSN ("ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3429 | _LSE_INSN ("ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3430 | _LSE_INSN ("ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3431 | _LSE_INSN ("ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3432 | _LSE_INSN ("ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3433 | _LSE_INSN ("ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3434 | _LSE_INSN ("ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3435 | _LSE_INSN ("ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3436 | _LSE_INSN ("ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3437 | _LSE_INSN ("ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3438 | _LSE_INSN ("ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3439 | _LSE_INSN ("ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3440 | _LSE_INSN ("ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3441 | _LSE_INSN ("ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3442 | _LSE_INSN ("ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3443 | _LSE_INSN ("ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3444 | _LSE_INSN ("ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3445 | _LSE_INSN ("ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3446 | _LSE_INSN ("ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3447 | _LSE_INSN ("ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3448 | _LSE_INSN ("ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3449 | _LSE_INSN ("lduminb", 0x38207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3450 | _LSE_INSN ("lduminh", 0x78207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3451 | _LSE_INSN ("ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3452 | _LSE_INSN ("lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3453 | _LSE_INSN ("lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3454 | _LSE_INSN ("lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3455 | _LSE_INSN ("lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3456 | _LSE_INSN ("lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3457 | _LSE_INSN ("lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3458 | _LSE_INSN ("ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3459 | _LSE_INSN ("lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3460 | _LSE_INSN ("lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3461 | _LSE_INSN ("staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3462 | _LSE_INSN ("staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3463 | _LSE_INSN ("stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3464 | _LSE_INSN ("staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3465 | _LSE_INSN ("staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3466 | _LSE_INSN ("staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3467 | _LSE_INSN ("stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3468 | _LSE_INSN ("stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3469 | _LSE_INSN ("stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3470 | _LSE_INSN ("stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3471 | _LSE_INSN ("stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3472 | _LSE_INSN ("stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3473 | _LSE_INSN ("steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3474 | _LSE_INSN ("steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3475 | _LSE_INSN ("steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3476 | _LSE_INSN ("steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3477 | _LSE_INSN ("steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3478 | _LSE_INSN ("steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3479 | _LSE_INSN ("stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3480 | _LSE_INSN ("stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3481 | _LSE_INSN ("stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3482 | _LSE_INSN ("stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3483 | _LSE_INSN ("stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3484 | _LSE_INSN ("stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3485 | _LSE_INSN ("stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3486 | _LSE_INSN ("stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3487 | _LSE_INSN ("stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3488 | _LSE_INSN ("stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3489 | _LSE_INSN ("stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3490 | _LSE_INSN ("stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3491 | _LSE_INSN ("stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3492 | _LSE_INSN ("stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3493 | _LSE_INSN ("stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3494 | _LSE_INSN ("stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3495 | _LSE_INSN ("stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3496 | _LSE_INSN ("stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3497 | _LSE_INSN ("stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3498 | _LSE_INSN ("stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3499 | _LSE_INSN ("stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3500 | _LSE_INSN ("stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3501 | _LSE_INSN ("stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3502 | _LSE_INSN ("stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3503 | _LSE_INSN ("stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3504 | _LSE_INSN ("stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3505 | _LSE_INSN ("stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3506 | _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3507 | _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3508 | _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| a06ea964 | 3509 | /* Move wide (immediate). */ |
| 5ce912d8 RS |
3510 | CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), |
| 3511 | CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), | |
| 3512 | CORE_INSN ("movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), | |
| 3513 | CORE_INSN ("mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), | |
| 3514 | CORE_INSN ("movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, OP2 (Rd, HALF), QL_DST_R, F_SF), | |
| a06ea964 | 3515 | /* PC-rel. addressing. */ |
| 9d30b0bd RS |
3516 | CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0), |
| 3517 | CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0), | |
| a06ea964 | 3518 | /* System. */ |
| f9830ec1 | 3519 | CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), |
| 9d30b0bd RS |
3520 | CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), |
| 3521 | CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| be2e7d95 | 3522 | CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
| ff605452 | 3523 | BTI_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)), |
| 9d30b0bd RS |
3524 | CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
| 3525 | CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3526 | CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3527 | CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3528 | CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 8787d804 SN |
3529 | V8_3_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), |
| 3530 | V8_3_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3531 | V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3532 | V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3533 | V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| eae424ae TC |
3534 | {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, 0, 0, NULL}, |
| 3535 | {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, 0, 0, NULL}, | |
| 9d30b0bd | 3536 | CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), |
| cde3679e NC |
3537 | CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS), |
| 3538 | CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3539 | CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 9d30b0bd RS |
3540 | CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0), |
| 3541 | CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)), | |
| 68dfbb92 | 3542 | SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0), |
| a6a51754 | 3543 | CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), |
| 9d30b0bd RS |
3544 | CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), |
| 3545 | CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), | |
| 3546 | CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), | |
| 3547 | CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), | |
| 2ac435d4 SD |
3548 | PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), |
| 3549 | PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), | |
| 3550 | PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), | |
| f9830ec1 | 3551 | CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE), |
| a6a51754 | 3552 | CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0), |
| f9830ec1 | 3553 | CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ), |
| 8787d804 SN |
3554 | V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), |
| 3555 | V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3556 | V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3557 | V8_3_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3558 | V8_3_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3559 | V8_3_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3560 | V8_3_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3561 | V8_3_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| a06ea964 | 3562 | /* Test & branch (immediate). */ |
| 9d30b0bd RS |
3563 | CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), |
| 3564 | CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), | |
| a06ea964 | 3565 | /* The old UAL conditional branch mnemonics (to aid portability). */ |
| 9d30b0bd RS |
3566 | CORE_INSN ("beq", 0x54000000, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), |
| 3567 | CORE_INSN ("bne", 0x54000001, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3568 | CORE_INSN ("bcs", 0x54000002, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3569 | CORE_INSN ("bhs", 0x54000002, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3570 | CORE_INSN ("bcc", 0x54000003, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3571 | CORE_INSN ("blo", 0x54000003, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3572 | CORE_INSN ("bmi", 0x54000004, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3573 | CORE_INSN ("bpl", 0x54000005, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3574 | CORE_INSN ("bvs", 0x54000006, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3575 | CORE_INSN ("bvc", 0x54000007, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3576 | CORE_INSN ("bhi", 0x54000008, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3577 | CORE_INSN ("bls", 0x54000009, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3578 | CORE_INSN ("bge", 0x5400000a, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3579 | CORE_INSN ("blt", 0x5400000b, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3580 | CORE_INSN ("bgt", 0x5400000c, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3581 | CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| c0890d26 | 3582 | /* SVE instructions. */ |
| 582e12bf RS |
3583 | _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0), |
| 3584 | _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0), | |
| c0890d26 | 3585 | _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0), |
| 582e12bf | 3586 | _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), |
| c0890d26 RS |
3587 | _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0), |
| 3588 | _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), | |
| 582e12bf | 3589 | _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), |
| c0890d26 RS |
3590 | _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0), |
| 3591 | _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0), | |
| eae424ae | 3592 | _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3593 | _SVE_INSN ("mov", 0x0520c000, 0xff20c000, sve_size_bhsd, OP_MOV_Z_P_Z, OP3 (SVE_Zd, SVE_Pg4_10, SVE_Zn), OP_SVE_VMV_BHSD, F_ALIAS | F_MISC, 0), |
| eae424ae | 3594 | _SVE_INSNC ("mov", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3595 | _SVE_INSN ("mov", 0x25004000, 0xfff0c210, sve_misc, OP_MOVZ_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), |
| 3596 | _SVE_INSN ("mov", 0x25004210, 0xfff0c210, sve_misc, OP_MOVM_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BMB, F_ALIAS | F_MISC, 0), | |
| eae424ae | 3597 | _SVE_INSNC ("mov", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3598 | _SVE_INSN ("movs", 0x25c04000, 0xfff0c210, sve_misc, OP_MOVS_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), |
| 3599 | _SVE_INSN ("movs", 0x25404000, 0xfff0c210, sve_misc, OP_MOVZS_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
| 3600 | _SVE_INSN ("not", 0x25004200, 0xfff0c210, sve_misc, OP_NOT_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
| 3601 | _SVE_INSN ("nots", 0x25404200, 0xfff0c210, sve_misc, OP_NOTS_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
| eae424ae | 3602 | _SVE_INSNC ("abs", 0x0416a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3603 | _SVE_INSN ("add", 0x04200000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
| eae424ae TC |
3604 | _SVE_INSNC ("add", 0x2520c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 3605 | _SVE_INSNC ("add", 0x04000000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
3606 | _SVE_INSN ("addpl", 0x04605000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), |
| 3607 | _SVE_INSN ("addvl", 0x04205000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), | |
| 3608 | _SVE_INSN ("adr", 0x0420a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_SXTW), OP_SVE_DD, 0, 0), | |
| 3609 | _SVE_INSN ("adr", 0x0460a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_UXTW), OP_SVE_DD, 0, 0), | |
| 3610 | _SVE_INSN ("adr", 0x04a0a000, 0xffa0f000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_LSL), OP_SVE_VV_SD, 0, 0), | |
| 3611 | _SVE_INSN ("and", 0x04203000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
| eae424ae TC |
3612 | _SVE_INSNC ("and", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
| 3613 | _SVE_INSNC ("and", 0x041a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
3614 | _SVE_INSN ("and", 0x25004000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
| 3615 | _SVE_INSN ("ands", 0x25404000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
| 3616 | _SVE_INSN ("andv", 0x041a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 3617 | _SVE_INSN ("asr", 0x04208000, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), | |
| 3618 | _SVE_INSN ("asr", 0x04209000, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
| eae424ae TC |
3619 | _SVE_INSNC ("asr", 0x04108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 3620 | _SVE_INSNC ("asr", 0x04188000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
| 3621 | _SVE_INSNC ("asr", 0x04008000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3622 | _SVE_INSNC ("asrd", 0x04048000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3623 | _SVE_INSNC ("asrr", 0x04148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 3624 | _SVE_INSN ("bic", 0x04e03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), |
| eae424ae | 3625 | _SVE_INSNC ("bic", 0x041b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 RS |
3626 | _SVE_INSN ("bic", 0x25004010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 3627 | _SVE_INSN ("bics", 0x25404010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3628 | _SVE_INSN ("brka", 0x25104000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0), | |
| 3629 | _SVE_INSN ("brkas", 0x25504000, 0xffffc210, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, 0, 0), | |
| 3630 | _SVE_INSN ("brkb", 0x25904000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0), | |
| 3631 | _SVE_INSN ("brkbs", 0x25d04000, 0xffffc210, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, 0, 0), | |
| 3632 | _SVE_INSN ("brkn", 0x25184000, 0xffffc210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pd), OP_SVE_BZBB, 0, 3), | |
| 3633 | _SVE_INSN ("brkns", 0x25584000, 0xffffc210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pd), OP_SVE_BZBB, 0, 3), | |
| 3634 | _SVE_INSN ("brkpa", 0x2500c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3635 | _SVE_INSN ("brkpas", 0x2540c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3636 | _SVE_INSN ("brkpb", 0x2500c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3637 | _SVE_INSN ("brkpbs", 0x2540c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| eae424ae | 3638 | _SVE_INSNC ("clasta", 0x05288000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 RS |
3639 | _SVE_INSN ("clasta", 0x052a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2), |
| 3640 | _SVE_INSN ("clasta", 0x0530a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2), | |
| eae424ae | 3641 | _SVE_INSNC ("clastb", 0x05298000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 RS |
3642 | _SVE_INSN ("clastb", 0x052b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2), |
| 3643 | _SVE_INSN ("clastb", 0x0531a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2), | |
| eae424ae TC |
3644 | _SVE_INSNC ("cls", 0x0418a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| 3645 | _SVE_INSNC ("clz", 0x0419a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3646 | _SVE_INSN ("cmpeq", 0x24002000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), |
| 3647 | _SVE_INSN ("cmpeq", 0x2400a000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0), | |
| 3648 | _SVE_INSN ("cmpeq", 0x25008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3649 | _SVE_INSN ("cmpge", 0x24004000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3650 | _SVE_INSN ("cmpge", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3651 | _SVE_INSN ("cmpge", 0x25000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3652 | _SVE_INSN ("cmpgt", 0x24004010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3653 | _SVE_INSN ("cmpgt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3654 | _SVE_INSN ("cmpgt", 0x25000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3655 | _SVE_INSN ("cmphi", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3656 | _SVE_INSN ("cmphi", 0x2400c010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3657 | _SVE_INSN ("cmphi", 0x24200010, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3658 | _SVE_INSN ("cmphs", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3659 | _SVE_INSN ("cmphs", 0x2400c000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3660 | _SVE_INSN ("cmphs", 0x24200000, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3661 | _SVE_INSN ("cmple", 0x24006010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3662 | _SVE_INSN ("cmple", 0x25002010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3663 | _SVE_INSN ("cmplo", 0x2400e000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3664 | _SVE_INSN ("cmplo", 0x24202000, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3665 | _SVE_INSN ("cmpls", 0x2400e010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3666 | _SVE_INSN ("cmpls", 0x24202010, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3667 | _SVE_INSN ("cmplt", 0x24006000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3668 | _SVE_INSN ("cmplt", 0x25002000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3669 | _SVE_INSN ("cmpne", 0x24002010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3670 | _SVE_INSN ("cmpne", 0x2400a010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0), | |
| 3671 | _SVE_INSN ("cmpne", 0x25008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| eae424ae TC |
3672 | _SVE_INSNC ("cnot", 0x041ba000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| 3673 | _SVE_INSNC ("cnt", 0x041aa000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3674 | _SVE_INSN ("cntb", 0x0420e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 3675 | _SVE_INSN ("cntd", 0x04e0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 3676 | _SVE_INSN ("cnth", 0x0460e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 3677 | _SVE_INSN ("cntp", 0x25208000, 0xff3fc200, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0), | |
| 3678 | _SVE_INSN ("cntw", 0x04a0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 3679 | _SVE_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0), | |
| eae424ae TC |
3680 | _SVE_INSNC ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), |
| 3681 | _SVE_INSNC ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), | |
| 3682 | _SVE_INSNC ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3683 | _SVE_INSN ("ctermeq", 0x25a02000, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0), |
| 3684 | _SVE_INSN ("ctermne", 0x25a02010, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0), | |
| 3685 | _SVE_INSN ("decb", 0x0430e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 3686 | _SVE_INSNC ("decd", 0x04f0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3687 | _SVE_INSN ("decd", 0x04f0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3688 | _SVE_INSNC ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3689 | _SVE_INSN ("dech", 0x0470e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3690 | _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3691 | _SVE_INSN ("decp", 0x252d8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| eae424ae | 3692 | _SVE_INSNC ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3693 | _SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 3694 | _SVE_INSN ("dup", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_HAS_ALIAS, 0), | |
| 582e12bf | 3695 | _SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_HAS_ALIAS, 0), |
| c0890d26 RS |
3696 | _SVE_INSN ("dup", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0), |
| 3697 | _SVE_INSN ("dupm", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0), | |
| 3698 | _SVE_INSN ("eor", 0x04a03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
| eae424ae TC |
3699 | _SVE_INSNC ("eor", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
| 3700 | _SVE_INSNC ("eor", 0x04190000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
3701 | _SVE_INSN ("eor", 0x25004200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
| 3702 | _SVE_INSN ("eors", 0x25404200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
| 3703 | _SVE_INSN ("eorv", 0x04192000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| eae424ae TC |
3704 | _SVE_INSNC ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1), |
| 3705 | _SVE_INSNC ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3706 | _SVE_INSNC ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3707 | _SVE_INSN ("facge", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), |
| 3708 | _SVE_INSN ("facgt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
| 3709 | _SVE_INSN ("fadd", 0x65000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| eae424ae TC |
3710 | _SVE_INSNC ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3711 | _SVE_INSNC ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3712 | _SVE_INSN ("fadda", 0x65182000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_HSD, 0, 2), |
| 3713 | _SVE_INSN ("faddv", 0x65002000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
| eae424ae TC |
3714 | _SVE_INSNC ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3715 | _SVE_INSNC ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3716 | _SVE_INSNC ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, C_SCAN_MOVPRFX, 0), | |
| 3717 | _SVE_INSNC ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3718 | _SVE_INSN ("fcmeq", 0x65122000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), |
| 3719 | _SVE_INSN ("fcmeq", 0x65006000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
| 3720 | _SVE_INSN ("fcmge", 0x65102000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3721 | _SVE_INSN ("fcmge", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
| 3722 | _SVE_INSN ("fcmgt", 0x65102010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3723 | _SVE_INSN ("fcmgt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
| 3724 | _SVE_INSN ("fcmle", 0x65112010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3725 | _SVE_INSN ("fcmlt", 0x65112000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3726 | _SVE_INSN ("fcmne", 0x65132000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3727 | _SVE_INSN ("fcmne", 0x65006010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
| 3728 | _SVE_INSN ("fcmuo", 0x6500c000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
| eae424ae TC |
3729 | _SVE_INSNC ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), |
| 3730 | _SVE_INSNC ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3731 | _SVE_INSNC ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3732 | _SVE_INSNC ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3733 | _SVE_INSNC ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3734 | _SVE_INSNC ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3735 | _SVE_INSNC ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3736 | _SVE_INSNC ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3737 | _SVE_INSNC ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3738 | _SVE_INSNC ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3739 | _SVE_INSNC ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3740 | _SVE_INSNC ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3741 | _SVE_INSNC ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3742 | _SVE_INSNC ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3743 | _SVE_INSNC ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3744 | _SVE_INSNC ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3745 | _SVE_INSNC ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3746 | _SVE_INSNC ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3747 | _SVE_INSNC ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3748 | _SVE_INSNC ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3749 | _SVE_INSNC ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3750 | _SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3751 | _SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3752 | _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0), |
| 3753 | _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), | |
| eae424ae TC |
3754 | _SVE_INSNC ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 3755 | _SVE_INSNC ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3756 | _SVE_INSNC ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3757 | _SVE_INSNC ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3758 | _SVE_INSNC ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3759 | _SVE_INSN ("fmaxnmv", 0x65042000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), |
| 3760 | _SVE_INSN ("fmaxv", 0x65062000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
| eae424ae TC |
3761 | _SVE_INSNC ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3762 | _SVE_INSNC ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3763 | _SVE_INSNC ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3764 | _SVE_INSNC ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3765 | _SVE_INSN ("fminnmv", 0x65052000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), |
| 3766 | _SVE_INSN ("fminv", 0x65072000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
| eae424ae TC |
3767 | _SVE_INSNC ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 3768 | _SVE_INSNC ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), | |
| 3769 | _SVE_INSNC ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
| 3770 | _SVE_INSNC ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), | |
| 3771 | _SVE_INSNC ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3772 | _SVE_INSNC ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), | |
| 3773 | _SVE_INSNC ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
| 3774 | _SVE_INSNC ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), | |
| 3775 | _SVE_INSNC ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf | 3776 | _SVE_INSN ("fmul", 0x65000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
| eae424ae TC |
3777 | _SVE_INSNC ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3778 | _SVE_INSNC ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3779 | _SVE_INSN ("fmul", 0x64202000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0), |
| 3780 | _SVE_INSN ("fmul", 0x64a02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0), | |
| 3781 | _SVE_INSN ("fmul", 0x64e02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0), | |
| eae424ae TC |
3782 | _SVE_INSNC ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3783 | _SVE_INSNC ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3784 | _SVE_INSNC ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3785 | _SVE_INSNC ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3786 | _SVE_INSNC ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3787 | _SVE_INSNC ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3788 | _SVE_INSN ("frecpe", 0x650e3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), |
| 3789 | _SVE_INSN ("frecps", 0x65001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| eae424ae TC |
3790 | _SVE_INSNC ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 3791 | _SVE_INSNC ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3792 | _SVE_INSNC ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3793 | _SVE_INSNC ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3794 | _SVE_INSNC ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3795 | _SVE_INSNC ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3796 | _SVE_INSNC ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3797 | _SVE_INSNC ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3798 | _SVE_INSN ("frsqrte", 0x650f3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), |
| 3799 | _SVE_INSN ("frsqrts", 0x65001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| eae424ae TC |
3800 | _SVE_INSNC ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3801 | _SVE_INSNC ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf | 3802 | _SVE_INSN ("fsub", 0x65000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
| eae424ae TC |
3803 | _SVE_INSNC ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3804 | _SVE_INSNC ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3805 | _SVE_INSNC ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3806 | _SVE_INSNC ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3807 | _SVE_INSNC ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, C_SCAN_MOVPRFX, 1), | |
| 582e12bf RS |
3808 | _SVE_INSN ("ftsmul", 0x65000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
| 3809 | _SVE_INSN ("ftssel", 0x0420b000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| c0890d26 | 3810 | _SVE_INSN ("incb", 0x0430e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3811 | _SVE_INSNC ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3812 | _SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3813 | _SVE_INSNC ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3814 | _SVE_INSN ("inch", 0x0470e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3815 | _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3816 | _SVE_INSN ("incp", 0x252c8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| eae424ae | 3817 | _SVE_INSNC ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3818 | _SVE_INSN ("incw", 0x04b0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 3819 | _SVE_INSN ("index", 0x04204c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, Rm), OP_SVE_VRR_BHSD, 0, 0), | |
| 3820 | _SVE_INSN ("index", 0x04204000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, SVE_SIMM5B), OP_SVE_VUU_BHSD, 0, 0), | |
| 3821 | _SVE_INSN ("index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0), | |
| 3822 | _SVE_INSN ("index", 0x04204800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, Rm), OP_SVE_VUR_BHSD, 0, 0), | |
| eae424ae TC |
3823 | _SVE_INSNC ("insr", 0x05243800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Rm), OP_SVE_VR_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| 3824 | _SVE_INSNC ("insr", 0x05343800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Vm), OP_SVE_VV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3825 | _SVE_INSN ("lasta", 0x0520a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0), |
| 3826 | _SVE_INSN ("lasta", 0x05228000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 3827 | _SVE_INSN ("lastb", 0x0521a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0), | |
| 3828 | _SVE_INSN ("lastb", 0x05238000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 3829 | _SVE_INSN ("ld1b", 0x84004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3830 | _SVE_INSN ("ld1b", 0xa4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
| 3831 | _SVE_INSN ("ld1b", 0xa4204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), | |
| 3832 | _SVE_INSN ("ld1b", 0xa4404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), | |
| 3833 | _SVE_INSN ("ld1b", 0xa4604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), | |
| 3834 | _SVE_INSN ("ld1b", 0xc4004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3835 | _SVE_INSN ("ld1b", 0xc440c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3836 | _SVE_INSN ("ld1b", 0x8420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 3837 | _SVE_INSN ("ld1b", 0xa400a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), | |
| 3838 | _SVE_INSN ("ld1b", 0xa420a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 3839 | _SVE_INSN ("ld1b", 0xa440a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3840 | _SVE_INSN ("ld1b", 0xa460a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3841 | _SVE_INSN ("ld1b", 0xc420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| 3842 | _SVE_INSN ("ld1d", 0xa5e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
| 3843 | _SVE_INSN ("ld1d", 0xc5804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3844 | _SVE_INSN ("ld1d", 0xc5a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3845 | _SVE_INSN ("ld1d", 0xc5c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3846 | _SVE_INSN ("ld1d", 0xc5e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0), | |
| 3847 | _SVE_INSN ("ld1d", 0xa5e0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3848 | _SVE_INSN ("ld1d", 0xc5a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0), | |
| 3849 | _SVE_INSN ("ld1h", 0x84804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3850 | _SVE_INSN ("ld1h", 0x84a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3851 | _SVE_INSN ("ld1h", 0xa4a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| 3852 | _SVE_INSN ("ld1h", 0xa4c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SZU, F_OD(1), 0), | |
| 3853 | _SVE_INSN ("ld1h", 0xa4e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
| 3854 | _SVE_INSN ("ld1h", 0xc4804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3855 | _SVE_INSN ("ld1h", 0xc4a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3856 | _SVE_INSN ("ld1h", 0xc4c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3857 | _SVE_INSN ("ld1h", 0xc4e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 3858 | _SVE_INSN ("ld1h", 0x84a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 3859 | _SVE_INSN ("ld1h", 0xa4a0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 3860 | _SVE_INSN ("ld1h", 0xa4c0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3861 | _SVE_INSN ("ld1h", 0xa4e0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3862 | _SVE_INSN ("ld1h", 0xc4a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| 3863 | _SVE_INSN ("ld1rb", 0x84408000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_BZU, F_OD(1), 0), | |
| 3864 | _SVE_INSN ("ld1rb", 0x8440a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0), | |
| 3865 | _SVE_INSN ("ld1rb", 0x8440c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0), | |
| 3866 | _SVE_INSN ("ld1rb", 0x8440e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0), | |
| 3867 | _SVE_INSN ("ld1rd", 0x85c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x8), OP_SVE_DZU, F_OD(1), 0), | |
| 3868 | _SVE_INSN ("ld1rh", 0x84c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_HZU, F_OD(1), 0), | |
| 3869 | _SVE_INSN ("ld1rh", 0x84c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0), | |
| 3870 | _SVE_INSN ("ld1rh", 0x84c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0), | |
| 582e12bf RS |
3871 | _SVE_INSN ("ld1rqb", 0xa4002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_BZU, F_OD(1), 0), |
| 3872 | _SVE_INSN ("ld1rqb", 0xa4000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
| 3873 | _SVE_INSN ("ld1rqd", 0xa5802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_DZU, F_OD(1), 0), | |
| 3874 | _SVE_INSN ("ld1rqd", 0xa5800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
| 3875 | _SVE_INSN ("ld1rqh", 0xa4802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_HZU, F_OD(1), 0), | |
| 3876 | _SVE_INSN ("ld1rqh", 0xa4800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| 3877 | _SVE_INSN ("ld1rqw", 0xa5002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_SZU, F_OD(1), 0), | |
| 3878 | _SVE_INSN ("ld1rqw", 0xa5000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| c0890d26 RS |
3879 | _SVE_INSN ("ld1rsb", 0x85c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0), |
| 3880 | _SVE_INSN ("ld1rsb", 0x85c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0), | |
| 3881 | _SVE_INSN ("ld1rsb", 0x85c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0), | |
| 3882 | _SVE_INSN ("ld1rsh", 0x85408000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0), | |
| 3883 | _SVE_INSN ("ld1rsh", 0x8540a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0), | |
| 3884 | _SVE_INSN ("ld1rsw", 0x84c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_DZU, F_OD(1), 0), | |
| 3885 | _SVE_INSN ("ld1rw", 0x8540c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_SZU, F_OD(1), 0), | |
| 3886 | _SVE_INSN ("ld1rw", 0x8540e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_DZU, F_OD(1), 0), | |
| 3887 | _SVE_INSN ("ld1sb", 0x84000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3888 | _SVE_INSN ("ld1sb", 0xa5804000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), | |
| 3889 | _SVE_INSN ("ld1sb", 0xa5a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), | |
| 3890 | _SVE_INSN ("ld1sb", 0xa5c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), | |
| 3891 | _SVE_INSN ("ld1sb", 0xc4000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3892 | _SVE_INSN ("ld1sb", 0xc4408000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3893 | _SVE_INSN ("ld1sb", 0x84208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 3894 | _SVE_INSN ("ld1sb", 0xa580a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3895 | _SVE_INSN ("ld1sb", 0xa5a0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3896 | _SVE_INSN ("ld1sb", 0xa5c0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 3897 | _SVE_INSN ("ld1sb", 0xc4208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| 3898 | _SVE_INSN ("ld1sh", 0x84800000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3899 | _SVE_INSN ("ld1sh", 0x84a00000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3900 | _SVE_INSN ("ld1sh", 0xa5004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
| 3901 | _SVE_INSN ("ld1sh", 0xa5204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SZU, F_OD(1), 0), | |
| 3902 | _SVE_INSN ("ld1sh", 0xc4800000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3903 | _SVE_INSN ("ld1sh", 0xc4a00000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3904 | _SVE_INSN ("ld1sh", 0xc4c08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3905 | _SVE_INSN ("ld1sh", 0xc4e08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 3906 | _SVE_INSN ("ld1sh", 0x84a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 3907 | _SVE_INSN ("ld1sh", 0xa500a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3908 | _SVE_INSN ("ld1sh", 0xa520a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3909 | _SVE_INSN ("ld1sh", 0xc4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| 3910 | _SVE_INSN ("ld1sw", 0xa4804000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DZU, F_OD(1), 0), | |
| 3911 | _SVE_INSN ("ld1sw", 0xc5000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3912 | _SVE_INSN ("ld1sw", 0xc5200000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3913 | _SVE_INSN ("ld1sw", 0xc5408000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3914 | _SVE_INSN ("ld1sw", 0xc5608000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 3915 | _SVE_INSN ("ld1sw", 0xa480a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3916 | _SVE_INSN ("ld1sw", 0xc5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| 3917 | _SVE_INSN ("ld1w", 0x85004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3918 | _SVE_INSN ("ld1w", 0x85204000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3919 | _SVE_INSN ("ld1w", 0xa5404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| 3920 | _SVE_INSN ("ld1w", 0xa5604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DZU, F_OD(1), 0), | |
| 3921 | _SVE_INSN ("ld1w", 0xc5004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3922 | _SVE_INSN ("ld1w", 0xc5204000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3923 | _SVE_INSN ("ld1w", 0xc540c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3924 | _SVE_INSN ("ld1w", 0xc560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 3925 | _SVE_INSN ("ld1w", 0x8520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0), | |
| 3926 | _SVE_INSN ("ld1w", 0xa540a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3927 | _SVE_INSN ("ld1w", 0xa560a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3928 | _SVE_INSN ("ld1w", 0xc520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| 3929 | _SVE_INSN ("ld2b", 0xa420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(2), 0), | |
| 3930 | _SVE_INSN ("ld2b", 0xa420e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, F_OD(2), 0), | |
| 3931 | _SVE_INSN ("ld2d", 0xa5a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(2), 0), | |
| 3932 | _SVE_INSN ("ld2d", 0xa5a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, F_OD(2), 0), | |
| 3933 | _SVE_INSN ("ld2h", 0xa4a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(2), 0), | |
| 3934 | _SVE_INSN ("ld2h", 0xa4a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, F_OD(2), 0), | |
| 3935 | _SVE_INSN ("ld2w", 0xa520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(2), 0), | |
| 3936 | _SVE_INSN ("ld2w", 0xa520e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, F_OD(2), 0), | |
| 3937 | _SVE_INSN ("ld3b", 0xa440c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(3), 0), | |
| 3938 | _SVE_INSN ("ld3b", 0xa440e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_BZU, F_OD(3), 0), | |
| 3939 | _SVE_INSN ("ld3d", 0xa5c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(3), 0), | |
| 3940 | _SVE_INSN ("ld3d", 0xa5c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_DZU, F_OD(3), 0), | |
| 3941 | _SVE_INSN ("ld3h", 0xa4c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(3), 0), | |
| 3942 | _SVE_INSN ("ld3h", 0xa4c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_HZU, F_OD(3), 0), | |
| 3943 | _SVE_INSN ("ld3w", 0xa540c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(3), 0), | |
| 3944 | _SVE_INSN ("ld3w", 0xa540e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_SZU, F_OD(3), 0), | |
| 3945 | _SVE_INSN ("ld4b", 0xa460c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(4), 0), | |
| 3946 | _SVE_INSN ("ld4b", 0xa460e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, F_OD(4), 0), | |
| 3947 | _SVE_INSN ("ld4d", 0xa5e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(4), 0), | |
| 3948 | _SVE_INSN ("ld4d", 0xa5e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, F_OD(4), 0), | |
| 3949 | _SVE_INSN ("ld4h", 0xa4e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(4), 0), | |
| 3950 | _SVE_INSN ("ld4h", 0xa4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, F_OD(4), 0), | |
| 3951 | _SVE_INSN ("ld4w", 0xa560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(4), 0), | |
| 3952 | _SVE_INSN ("ld4w", 0xa560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, F_OD(4), 0), | |
| c8d59609 | 3953 | |
| c0890d26 RS |
3954 | _SVE_INSN ("ldff1b", 0x84006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 3955 | _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, F_OD(1), 0), | |
| c8d59609 | 3956 | _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, F_OD(1), 0), |
| c0890d26 | 3957 | _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0), |
| c8d59609 | 3958 | _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
| c0890d26 | 3959 | _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 3960 | _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 3961 | _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 3962 | _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
3963 | _SVE_INSN ("ldff1b", 0xc4006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 3964 | _SVE_INSN ("ldff1b", 0xc440e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3965 | _SVE_INSN ("ldff1b", 0x8420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 3966 | _SVE_INSN ("ldff1b", 0xc420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 3967 | |
| c0890d26 | 3968 | _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 3969 | _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
3970 | _SVE_INSN ("ldff1d", 0xc5806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 3971 | _SVE_INSN ("ldff1d", 0xc5a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3972 | _SVE_INSN ("ldff1d", 0xc5c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3973 | _SVE_INSN ("ldff1d", 0xc5e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0), | |
| 3974 | _SVE_INSN ("ldff1d", 0xc5a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 3975 | |
| c0890d26 RS |
3976 | _SVE_INSN ("ldff1h", 0x84806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 3977 | _SVE_INSN ("ldff1h", 0x84a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3978 | _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| c8d59609 | 3979 | _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
| c0890d26 | 3980 | _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 3981 | _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 3982 | _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 3983 | _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
3984 | _SVE_INSN ("ldff1h", 0xc4806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 3985 | _SVE_INSN ("ldff1h", 0xc4a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3986 | _SVE_INSN ("ldff1h", 0xc4c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3987 | _SVE_INSN ("ldff1h", 0xc4e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 3988 | _SVE_INSN ("ldff1h", 0x84a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 3989 | _SVE_INSN ("ldff1h", 0xc4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 3990 | |
| c0890d26 RS |
3991 | _SVE_INSN ("ldff1sb", 0x84002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 3992 | _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0), | |
| c8d59609 | 3993 | _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 | 3994 | _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 3995 | _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 3996 | _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0), |
| c8d59609 | 3997 | _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
| c0890d26 RS |
3998 | _SVE_INSN ("ldff1sb", 0xc4002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 3999 | _SVE_INSN ("ldff1sb", 0xc440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4000 | _SVE_INSN ("ldff1sb", 0x8420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 4001 | _SVE_INSN ("ldff1sb", 0xc420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4002 | |
| c0890d26 RS |
4003 | _SVE_INSN ("ldff1sh", 0x84802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4004 | _SVE_INSN ("ldff1sh", 0x84a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4005 | _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
| c8d59609 | 4006 | _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 | 4007 | _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 4008 | _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 RS |
4009 | _SVE_INSN ("ldff1sh", 0xc4802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4010 | _SVE_INSN ("ldff1sh", 0xc4a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4011 | _SVE_INSN ("ldff1sh", 0xc4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4012 | _SVE_INSN ("ldff1sh", 0xc4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 4013 | _SVE_INSN ("ldff1sh", 0x84a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 4014 | _SVE_INSN ("ldff1sh", 0xc4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4015 | |
| c0890d26 | 4016 | _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4017 | _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4018 | _SVE_INSN ("ldff1sw", 0xc5002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4019 | _SVE_INSN ("ldff1sw", 0xc5202000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4020 | _SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4021 | _SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 4022 | _SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4023 | |
| c0890d26 RS |
4024 | _SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4025 | _SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4026 | _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| c8d59609 | 4027 | _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 4028 | _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4029 | _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4030 | _SVE_INSN ("ldff1w", 0xc5006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4031 | _SVE_INSN ("ldff1w", 0xc5206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4032 | _SVE_INSN ("ldff1w", 0xc540e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4033 | _SVE_INSN ("ldff1w", 0xc560e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 4034 | _SVE_INSN ("ldff1w", 0x8520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0), | |
| 4035 | _SVE_INSN ("ldff1w", 0xc520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4036 | |
| c0890d26 RS |
4037 | _SVE_INSN ("ldnf1b", 0xa410a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), |
| 4038 | _SVE_INSN ("ldnf1b", 0xa430a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4039 | _SVE_INSN ("ldnf1b", 0xa450a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4040 | _SVE_INSN ("ldnf1b", 0xa470a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4041 | _SVE_INSN ("ldnf1d", 0xa5f0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4042 | _SVE_INSN ("ldnf1h", 0xa4b0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4043 | _SVE_INSN ("ldnf1h", 0xa4d0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4044 | _SVE_INSN ("ldnf1h", 0xa4f0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4045 | _SVE_INSN ("ldnf1sb", 0xa590a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4046 | _SVE_INSN ("ldnf1sb", 0xa5b0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4047 | _SVE_INSN ("ldnf1sb", 0xa5d0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4048 | _SVE_INSN ("ldnf1sh", 0xa510a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4049 | _SVE_INSN ("ldnf1sh", 0xa530a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4050 | _SVE_INSN ("ldnf1sw", 0xa490a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4051 | _SVE_INSN ("ldnf1w", 0xa550a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4052 | _SVE_INSN ("ldnf1w", 0xa570a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4053 | _SVE_INSN ("ldnt1b", 0xa400c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
| 4054 | _SVE_INSN ("ldnt1b", 0xa400e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), | |
| 4055 | _SVE_INSN ("ldnt1d", 0xa580c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
| 4056 | _SVE_INSN ("ldnt1d", 0xa580e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4057 | _SVE_INSN ("ldnt1h", 0xa480c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| 4058 | _SVE_INSN ("ldnt1h", 0xa480e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4059 | _SVE_INSN ("ldnt1w", 0xa500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| 4060 | _SVE_INSN ("ldnt1w", 0xa500e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4061 | _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4062 | _SVE_INSN ("ldr", 0x85804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4063 | _SVE_INSN ("lsl", 0x04208c00, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), | |
| 4064 | _SVE_INSN ("lsl", 0x04209c00, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
| eae424ae TC |
4065 | _SVE_INSNC ("lsl", 0x04138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 4066 | _SVE_INSNC ("lsl", 0x041b8000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
| 4067 | _SVE_INSNC ("lsl", 0x04038000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4068 | _SVE_INSNC ("lslr", 0x04178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4069 | _SVE_INSN ("lsr", 0x04208400, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), |
| 4070 | _SVE_INSN ("lsr", 0x04209400, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
| eae424ae TC |
4071 | _SVE_INSNC ("lsr", 0x04118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 4072 | _SVE_INSNC ("lsr", 0x04198000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
| 4073 | _SVE_INSNC ("lsr", 0x04018000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4074 | _SVE_INSNC ("lsrr", 0x04158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4075 | _SVE_INSNC ("mad", 0x0400c000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4076 | _SVE_INSNC ("mla", 0x04004000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4077 | _SVE_INSNC ("mls", 0x04006000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4078 | _SVE_INSNC ("movprfx", 0x0420bc00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), {}, F_SCAN, C_SCAN_MOVPRFX, 0), | |
| 4079 | _SVE_INSNC ("movprfx", 0x04102000, 0xff3ee000, sve_movprfx, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VPV_BHSD, F_SCAN, C_SCAN_MOVPRFX, 0), | |
| 4080 | _SVE_INSNC ("msb", 0x0400e000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4081 | _SVE_INSNC ("mul", 0x2530c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
| 4082 | _SVE_INSNC ("mul", 0x04100000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4083 | _SVE_INSN ("nand", 0x25804210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 4084 | _SVE_INSN ("nands", 0x25c04210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| eae424ae | 4085 | _SVE_INSNC ("neg", 0x0417a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4086 | _SVE_INSN ("nor", 0x25804200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 4087 | _SVE_INSN ("nors", 0x25c04200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| eae424ae | 4088 | _SVE_INSNC ("not", 0x041ea000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4089 | _SVE_INSN ("orn", 0x25804010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 4090 | _SVE_INSN ("orns", 0x25c04010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 4091 | _SVE_INSN ("orr", 0x04603000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, F_HAS_ALIAS, 0), | |
| eae424ae TC |
4092 | _SVE_INSNC ("orr", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
| 4093 | _SVE_INSNC ("orr", 0x04180000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4094 | _SVE_INSN ("orr", 0x25804000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
| 4095 | _SVE_INSN ("orrs", 0x25c04000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
| 4096 | _SVE_INSN ("orv", 0x04182000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 4097 | _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0), | |
| 4098 | _SVE_INSN ("pfirst", 0x2558c000, 0xfffffe10, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_BUB, 0, 2), | |
| 4099 | _SVE_INSN ("pnext", 0x2519c400, 0xff3ffe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_VUV_BHSD, 0, 2), | |
| 4100 | _SVE_INSN ("prfb", 0x8400c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX), {}, 0, 0), | |
| 4101 | _SVE_INSN ("prfb", 0x84200000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_UUS, 0, 0), | |
| 4102 | _SVE_INSN ("prfb", 0xc4200000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_UUD, 0, 0), | |
| 4103 | _SVE_INSN ("prfb", 0xc4608000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_UUD, 0, 0), | |
| 4104 | _SVE_INSN ("prfb", 0x8400e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_UUS, 0, 0), | |
| 4105 | _SVE_INSN ("prfb", 0x85c00000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4106 | _SVE_INSN ("prfb", 0xc400e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_UUD, 0, 0), | |
| 4107 | _SVE_INSN ("prfd", 0x84206000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_UUS, 0, 0), | |
| 4108 | _SVE_INSN ("prfd", 0x8580c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL3), {}, 0, 0), | |
| 4109 | _SVE_INSN ("prfd", 0xc4206000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_UUD, 0, 0), | |
| 4110 | _SVE_INSN ("prfd", 0xc460e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_UUD, 0, 0), | |
| 4111 | _SVE_INSN ("prfd", 0x8580e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_UUS, 0, 0), | |
| 4112 | _SVE_INSN ("prfd", 0x85c06000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4113 | _SVE_INSN ("prfd", 0xc580e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_UUD, 0, 0), | |
| 4114 | _SVE_INSN ("prfh", 0x84202000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_UUS, 0, 0), | |
| 4115 | _SVE_INSN ("prfh", 0x8480c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL1), {}, 0, 0), | |
| 4116 | _SVE_INSN ("prfh", 0xc4202000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_UUD, 0, 0), | |
| 4117 | _SVE_INSN ("prfh", 0xc460a000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_UUD, 0, 0), | |
| 4118 | _SVE_INSN ("prfh", 0x8480e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_UUS, 0, 0), | |
| 4119 | _SVE_INSN ("prfh", 0x85c02000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4120 | _SVE_INSN ("prfh", 0xc480e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_UUD, 0, 0), | |
| 4121 | _SVE_INSN ("prfw", 0x84204000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_UUS, 0, 0), | |
| 4122 | _SVE_INSN ("prfw", 0x8500c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL2), {}, 0, 0), | |
| 4123 | _SVE_INSN ("prfw", 0xc4204000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_UUD, 0, 0), | |
| 4124 | _SVE_INSN ("prfw", 0xc460c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_UUD, 0, 0), | |
| 4125 | _SVE_INSN ("prfw", 0x8500e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_UUS, 0, 0), | |
| 4126 | _SVE_INSN ("prfw", 0x85c04000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4127 | _SVE_INSN ("prfw", 0xc500e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_UUD, 0, 0), | |
| 4128 | _SVE_INSN ("ptest", 0x2550c000, 0xffffc21f, sve_misc, 0, OP2 (SVE_Pg4_10, SVE_Pn), OP_SVE_UB, 0, 0), | |
| 4129 | _SVE_INSN ("ptrue", 0x2518e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4130 | _SVE_INSN ("ptrues", 0x2519e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4131 | _SVE_INSN ("punpkhi", 0x05314000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0), | |
| 4132 | _SVE_INSN ("punpklo", 0x05304000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0), | |
| eae424ae | 4133 | _SVE_INSNC ("rbit", 0x05278000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4134 | _SVE_INSN ("rdffr", 0x2519f000, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0), |
| 4135 | _SVE_INSN ("rdffr", 0x2518f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0), | |
| 4136 | _SVE_INSN ("rdffrs", 0x2558f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0), | |
| 4137 | _SVE_INSN ("rdvl", 0x04bf5000, 0xfffff800, sve_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0), | |
| 4138 | _SVE_INSN ("rev", 0x05344000, 0xff3ffe10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_VV_BHSD, 0, 0), | |
| 4139 | _SVE_INSN ("rev", 0x05383800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHSD, 0, 0), | |
| eae424ae TC |
4140 | _SVE_INSNC ("revb", 0x05248000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 4141 | _SVE_INSNC ("revh", 0x05a58000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
| 4142 | _SVE_INSNC ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4143 | _SVE_INSNC ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4144 | _SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0), |
| eae424ae TC |
4145 | _SVE_INSNC ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), |
| 4146 | _SVE_INSNC ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4147 | _SVE_INSNC ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4148 | _SVE_INSNC ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4149 | _SVE_INSNC ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4150 | _SVE_INSNC ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4151 | _SVE_INSNC ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4152 | _SVE_INSNC ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4153 | _SVE_INSNC ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4154 | _SVE_INSNC ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
| 4155 | _SVE_INSNC ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), | |
| 4156 | _SVE_INSNC ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
4157 | _SVE_INSN ("sel", 0x0520c000, 0xff20c000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg4_10, SVE_Zn, SVE_Zm_16), OP_SVE_VUVV_BHSD, F_HAS_ALIAS, 0), |
| 4158 | _SVE_INSN ("sel", 0x25004210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BUBB, F_HAS_ALIAS, 0), | |
| 4159 | _SVE_INSN ("setffr", 0x252c9000, 0xffffffff, sve_misc, 0, OP0 (), {}, 0, 0), | |
| eae424ae TC |
4160 | _SVE_INSNC ("smax", 0x2528c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4161 | _SVE_INSNC ("smax", 0x04080000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4162 | _SVE_INSN ("smaxv", 0x04082000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae TC |
4163 | _SVE_INSNC ("smin", 0x252ac000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4164 | _SVE_INSNC ("smin", 0x040a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4165 | _SVE_INSN ("sminv", 0x040a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae TC |
4166 | _SVE_INSNC ("smulh", 0x04120000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 4167 | _SVE_INSNC ("splice", 0x052c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4168 | _SVE_INSN ("sqadd", 0x04201000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
| eae424ae | 4169 | _SVE_INSNC ("sqadd", 0x2524c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4170 | _SVE_INSN ("sqdecb", 0x0430f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4171 | _SVE_INSN ("sqdecb", 0x0420f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4172 | _SVE_INSNC ("sqdecd", 0x04e0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4173 | _SVE_INSN ("sqdecd", 0x04f0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4174 | _SVE_INSN ("sqdecd", 0x04e0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4175 | _SVE_INSNC ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4176 | _SVE_INSN ("sqdech", 0x0470f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4177 | _SVE_INSN ("sqdech", 0x0460f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4178 | _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4179 | _SVE_INSN ("sqdecp", 0x252a8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| 4180 | _SVE_INSN ("sqdecp", 0x252a8800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), | |
| eae424ae | 4181 | _SVE_INSNC ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4182 | _SVE_INSN ("sqdecw", 0x04b0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4183 | _SVE_INSN ("sqdecw", 0x04a0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| 4184 | _SVE_INSN ("sqincb", 0x0430f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4185 | _SVE_INSN ("sqincb", 0x0420f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4186 | _SVE_INSNC ("sqincd", 0x04e0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4187 | _SVE_INSN ("sqincd", 0x04f0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4188 | _SVE_INSN ("sqincd", 0x04e0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4189 | _SVE_INSNC ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4190 | _SVE_INSN ("sqinch", 0x0470f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4191 | _SVE_INSN ("sqinch", 0x0460f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4192 | _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4193 | _SVE_INSN ("sqincp", 0x25288c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| 4194 | _SVE_INSN ("sqincp", 0x25288800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), | |
| eae424ae | 4195 | _SVE_INSNC ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4196 | _SVE_INSN ("sqincw", 0x04b0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4197 | _SVE_INSN ("sqincw", 0x04a0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| 4198 | _SVE_INSN ("sqsub", 0x04201800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4199 | _SVE_INSNC ("sqsub", 0x2526c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4200 | _SVE_INSN ("st1b", 0xe4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0), |
| 4201 | _SVE_INSN ("st1b", 0xe4008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4202 | _SVE_INSN ("st1b", 0xe400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4203 | _SVE_INSN ("st1b", 0xe4204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HUU, F_OD(1), 0), | |
| 4204 | _SVE_INSN ("st1b", 0xe4404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SUU, F_OD(1), 0), | |
| 4205 | _SVE_INSN ("st1b", 0xe4408000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4206 | _SVE_INSN ("st1b", 0xe4604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DUU, F_OD(1), 0), | |
| 4207 | _SVE_INSN ("st1b", 0xe400e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BUU, F_OD(1), 0), | |
| 4208 | _SVE_INSN ("st1b", 0xe420e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
| 4209 | _SVE_INSN ("st1b", 0xe440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DUD, F_OD(1), 0), | |
| 4210 | _SVE_INSN ("st1b", 0xe440e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4211 | _SVE_INSN ("st1b", 0xe460a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SUS, F_OD(1), 0), | |
| 4212 | _SVE_INSN ("st1b", 0xe460e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4213 | _SVE_INSN ("st1d", 0xe5808000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4214 | _SVE_INSN ("st1d", 0xe580a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4215 | _SVE_INSN ("st1d", 0xe5a08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4216 | _SVE_INSN ("st1d", 0xe5a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DUD, F_OD(1), 0), | |
| 4217 | _SVE_INSN ("st1d", 0xe5e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(1), 0), | |
| 4218 | _SVE_INSN ("st1d", 0xe5c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DUD, F_OD(1), 0), | |
| 4219 | _SVE_INSN ("st1d", 0xe5e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4220 | _SVE_INSN ("st1h", 0xe4808000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4221 | _SVE_INSN ("st1h", 0xe480a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4222 | _SVE_INSN ("st1h", 0xe4a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(1), 0), | |
| 4223 | _SVE_INSN ("st1h", 0xe4a08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4224 | _SVE_INSN ("st1h", 0xe4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DUD, F_OD(1), 0), | |
| 4225 | _SVE_INSN ("st1h", 0xe4c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SUU, F_OD(1), 0), | |
| 4226 | _SVE_INSN ("st1h", 0xe4c08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4227 | _SVE_INSN ("st1h", 0xe4e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DUU, F_OD(1), 0), | |
| 4228 | _SVE_INSN ("st1h", 0xe4e08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4229 | _SVE_INSN ("st1h", 0xe4a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
| 4230 | _SVE_INSN ("st1h", 0xe4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DUD, F_OD(1), 0), | |
| 4231 | _SVE_INSN ("st1h", 0xe4c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4232 | _SVE_INSN ("st1h", 0xe4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SUS, F_OD(1), 0), | |
| 4233 | _SVE_INSN ("st1h", 0xe4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4234 | _SVE_INSN ("st1w", 0xe5008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4235 | _SVE_INSN ("st1w", 0xe500a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4236 | _SVE_INSN ("st1w", 0xe5208000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4237 | _SVE_INSN ("st1w", 0xe520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DUD, F_OD(1), 0), | |
| 4238 | _SVE_INSN ("st1w", 0xe5404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0), | |
| 4239 | _SVE_INSN ("st1w", 0xe5408000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4240 | _SVE_INSN ("st1w", 0xe5604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DUU, F_OD(1), 0), | |
| 4241 | _SVE_INSN ("st1w", 0xe5608000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4242 | _SVE_INSN ("st1w", 0xe540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DUD, F_OD(1), 0), | |
| 4243 | _SVE_INSN ("st1w", 0xe540e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4244 | _SVE_INSN ("st1w", 0xe560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SUS, F_OD(1), 0), | |
| 4245 | _SVE_INSN ("st1w", 0xe560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4246 | _SVE_INSN ("st2b", 0xe4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(2), 0), | |
| 4247 | _SVE_INSN ("st2b", 0xe430e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, F_OD(2), 0), | |
| 4248 | _SVE_INSN ("st2d", 0xe5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(2), 0), | |
| 4249 | _SVE_INSN ("st2d", 0xe5b0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, F_OD(2), 0), | |
| 4250 | _SVE_INSN ("st2h", 0xe4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(2), 0), | |
| 4251 | _SVE_INSN ("st2h", 0xe4b0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, F_OD(2), 0), | |
| 4252 | _SVE_INSN ("st2w", 0xe5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(2), 0), | |
| 4253 | _SVE_INSN ("st2w", 0xe530e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, F_OD(2), 0), | |
| 4254 | _SVE_INSN ("st3b", 0xe4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(3), 0), | |
| 4255 | _SVE_INSN ("st3b", 0xe450e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_BUU, F_OD(3), 0), | |
| 4256 | _SVE_INSN ("st3d", 0xe5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(3), 0), | |
| 4257 | _SVE_INSN ("st3d", 0xe5d0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_DUU, F_OD(3), 0), | |
| 4258 | _SVE_INSN ("st3h", 0xe4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(3), 0), | |
| 4259 | _SVE_INSN ("st3h", 0xe4d0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_HUU, F_OD(3), 0), | |
| 4260 | _SVE_INSN ("st3w", 0xe5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(3), 0), | |
| 4261 | _SVE_INSN ("st3w", 0xe550e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_SUU, F_OD(3), 0), | |
| 4262 | _SVE_INSN ("st4b", 0xe4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(4), 0), | |
| 4263 | _SVE_INSN ("st4b", 0xe470e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, F_OD(4), 0), | |
| 4264 | _SVE_INSN ("st4d", 0xe5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(4), 0), | |
| 4265 | _SVE_INSN ("st4d", 0xe5f0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, F_OD(4), 0), | |
| 4266 | _SVE_INSN ("st4h", 0xe4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(4), 0), | |
| 4267 | _SVE_INSN ("st4h", 0xe4f0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, F_OD(4), 0), | |
| 4268 | _SVE_INSN ("st4w", 0xe5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(4), 0), | |
| 4269 | _SVE_INSN ("st4w", 0xe570e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, F_OD(4), 0), | |
| 4270 | _SVE_INSN ("stnt1b", 0xe4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0), | |
| 4271 | _SVE_INSN ("stnt1b", 0xe410e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BUU, F_OD(1), 0), | |
| 4272 | _SVE_INSN ("stnt1d", 0xe5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(1), 0), | |
| 4273 | _SVE_INSN ("stnt1d", 0xe590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4274 | _SVE_INSN ("stnt1h", 0xe4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(1), 0), | |
| 4275 | _SVE_INSN ("stnt1h", 0xe490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
| 4276 | _SVE_INSN ("stnt1w", 0xe5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0), | |
| 4277 | _SVE_INSN ("stnt1w", 0xe510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4278 | _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4279 | _SVE_INSN ("str", 0xe5804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4280 | _SVE_INSN ("sub", 0x04200400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae TC |
4281 | _SVE_INSNC ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4282 | _SVE_INSNC ("sub", 0x04010000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4283 | _SVE_INSNC ("subr", 0x2523c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
| 4284 | _SVE_INSNC ("subr", 0x04030000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4285 | _SVE_INSN ("sunpkhi", 0x05313800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
| 4286 | _SVE_INSN ("sunpklo", 0x05303800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), | |
| eae424ae TC |
4287 | _SVE_INSNC ("sxtb", 0x0410a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 4288 | _SVE_INSNC ("sxth", 0x0492a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
| 4289 | _SVE_INSNC ("sxtw", 0x04d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
4290 | _SVE_INSN ("tbl", 0x05203000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0), |
| 4291 | _SVE_INSN ("trn1", 0x05205000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4292 | _SVE_INSN ("trn1", 0x05207000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4293 | _SVE_INSN ("trn2", 0x05205400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4294 | _SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4295 | _SVE_INSNC ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 | 4296 | _SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0), |
| eae424ae TC |
4297 | _SVE_INSNC ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), |
| 4298 | _SVE_INSNC ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4299 | _SVE_INSNC ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4300 | _SVE_INSNC ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4301 | _SVE_INSNC ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4302 | _SVE_INSNC ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4303 | _SVE_INSNC ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4304 | _SVE_INSNC ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4305 | _SVE_INSNC ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4306 | _SVE_INSNC ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
| 4307 | _SVE_INSNC ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), | |
| 4308 | _SVE_INSNC ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0), | |
| 4309 | _SVE_INSNC ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
| 4310 | _SVE_INSNC ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4311 | _SVE_INSN ("umaxv", 0x04092000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae TC |
4312 | _SVE_INSNC ("umin", 0x252bc000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4313 | _SVE_INSNC ("umin", 0x040b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4314 | _SVE_INSN ("uminv", 0x040b2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae | 4315 | _SVE_INSNC ("umulh", 0x04130000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 | 4316 | _SVE_INSN ("uqadd", 0x04201400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
| eae424ae | 4317 | _SVE_INSNC ("uqadd", 0x2525c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4318 | _SVE_INSN ("uqdecb", 0x0420fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4319 | _SVE_INSN ("uqdecb", 0x0430fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4320 | _SVE_INSNC ("uqdecd", 0x04e0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4321 | _SVE_INSN ("uqdecd", 0x04e0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4322 | _SVE_INSN ("uqdecd", 0x04f0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4323 | _SVE_INSNC ("uqdech", 0x0460cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4324 | _SVE_INSN ("uqdech", 0x0460fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4325 | _SVE_INSN ("uqdech", 0x0470fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4326 | _SVE_INSNC ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4327 | _SVE_INSN ("uqdecp", 0x252b8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0), |
| 4328 | _SVE_INSN ("uqdecp", 0x252b8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), | |
| eae424ae | 4329 | _SVE_INSNC ("uqdecw", 0x04a0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4330 | _SVE_INSN ("uqdecw", 0x04a0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4331 | _SVE_INSN ("uqdecw", 0x04b0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4332 | _SVE_INSN ("uqincb", 0x0420f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4333 | _SVE_INSN ("uqincb", 0x0430f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4334 | _SVE_INSNC ("uqincd", 0x04e0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4335 | _SVE_INSN ("uqincd", 0x04e0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4336 | _SVE_INSN ("uqincd", 0x04f0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4337 | _SVE_INSNC ("uqinch", 0x0460c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4338 | _SVE_INSN ("uqinch", 0x0460f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4339 | _SVE_INSN ("uqinch", 0x0470f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4340 | _SVE_INSNC ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4341 | _SVE_INSN ("uqincp", 0x25298800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0), |
| 4342 | _SVE_INSN ("uqincp", 0x25298c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), | |
| eae424ae | 4343 | _SVE_INSNC ("uqincw", 0x04a0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4344 | _SVE_INSN ("uqincw", 0x04a0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4345 | _SVE_INSN ("uqincw", 0x04b0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4346 | _SVE_INSN ("uqsub", 0x04201c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4347 | _SVE_INSNC ("uqsub", 0x2527c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4348 | _SVE_INSN ("uunpkhi", 0x05333800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
| 4349 | _SVE_INSN ("uunpklo", 0x05323800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), | |
| eae424ae TC |
4350 | _SVE_INSNC ("uxtb", 0x0411a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 4351 | _SVE_INSNC ("uxth", 0x0493a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
| 4352 | _SVE_INSNC ("uxtw", 0x04d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
4353 | _SVE_INSN ("uzp1", 0x05204800, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), |
| 4354 | _SVE_INSN ("uzp1", 0x05206800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4355 | _SVE_INSN ("uzp2", 0x05204c00, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4356 | _SVE_INSN ("uzp2", 0x05206c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4357 | _SVE_INSN ("whilele", 0x25200410, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4358 | _SVE_INSN ("whilele", 0x25201410, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4359 | _SVE_INSN ("whilelo", 0x25200c00, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4360 | _SVE_INSN ("whilelo", 0x25201c00, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4361 | _SVE_INSN ("whilels", 0x25200c10, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4362 | _SVE_INSN ("whilels", 0x25201c10, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4363 | _SVE_INSN ("whilelt", 0x25200400, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4364 | _SVE_INSN ("whilelt", 0x25201400, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4365 | _SVE_INSN ("wrffr", 0x25289000, 0xfffffe1f, sve_misc, 0, OP1 (SVE_Pn), OP_SVE_B, 0, 0), | |
| 4366 | _SVE_INSN ("zip1", 0x05204000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4367 | _SVE_INSN ("zip1", 0x05206000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4368 | _SVE_INSN ("zip2", 0x05204400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4369 | _SVE_INSN ("zip2", 0x05206400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4370 | _SVE_INSNC ("bic", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4371 | _SVE_INSN ("cmple", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), |
| 4372 | _SVE_INSN ("cmplo", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
| 4373 | _SVE_INSN ("cmpls", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
| 4374 | _SVE_INSN ("cmplt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
| eae424ae | 4375 | _SVE_INSNC ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), |
| 582e12bf RS |
4376 | _SVE_INSN ("facle", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), |
| 4377 | _SVE_INSN ("faclt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
| 4378 | _SVE_INSN ("fcmle", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
| 4379 | _SVE_INSN ("fcmlt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
| 4380 | _SVE_INSN ("fmov", 0x2538c000, 0xff3fffe0, sve_size_hsd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_HSD, F_ALIAS | F_PSEUDO, 0), | |
| eae424ae TC |
4381 | _SVE_INSNC ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 0), |
| 4382 | _SVE_INSNC ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), | |
| 4bd13cde | 4383 | |
| 65a55fbb TC |
4384 | /* SIMD Dot Product (optional in v8.2-A). */ |
| 4385 | DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), | |
| 4386 | DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), | |
| ff329288 TC |
4387 | DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), |
| 4388 | DOT_INSN ("sdot", 0xf00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), | |
| e9dbdd80 TC |
4389 | /* Crypto SHA2 (optional in ARMv8.2-a). */ |
| 4390 | SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), | |
| 4391 | SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), | |
| 4392 | SHA2_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0), | |
| 4393 | SHA2_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), | |
| 4394 | /* Crypto SHA3 (optional in ARMv8.2-a). */ | |
| 4395 | SHA3_INSN ("eor3", 0xce000000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), | |
| 4396 | SHA3_INSN ("rax1", 0xce608c00, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), | |
| 4397 | SHA3_INSN ("xar", 0xce800000, 0xffe00000, cryptosha3, OP4 (Vd, Vn, Vm, IMM), QL_XAR, 0), | |
| 4398 | SHA3_INSN ("bcax", 0xce200000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), | |
| 4399 | /* Crypto SM3 (optional in ARMv8.2-a). */ | |
| 4400 | SM4_INSN ("sm3ss1", 0xce400000, 0xffe08000, cryptosm3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME4S, 0), | |
| 4401 | SM4_INSN ("sm3tt1a", 0xce408000, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4402 | SM4_INSN ("sm3tt1b", 0xce408400, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4403 | SM4_INSN ("sm3tt2a", 0xce408800, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4404 | SM4_INSN ("sm3tt2b", 0xce408c00, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4405 | SM4_INSN ("sm3partw1", 0xce60c000, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 4406 | SM4_INSN ("sm3partw2", 0xce60c400, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 4407 | /* Crypto SM4 (optional in ARMv8.2-a). */ | |
| 4408 | SM4_INSN ("sm4e", 0xcec08400, 0xfffffc00, cryptosm4, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
| 4409 | SM4_INSN ("sm4ekey", 0xce60c800, 0xffe0fc00, cryptosm4, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 4410 | /* Crypto FP16 (optional in ARMv8.2-a). */ | |
| 4411 | FP16_V8_2_INSN ("fmlal", 0xe20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4412 | FP16_V8_2_INSN ("fmlsl", 0xea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4413 | FP16_V8_2_INSN ("fmlal2", 0x2e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4414 | FP16_V8_2_INSN ("fmlsl2", 0x2ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4415 | ||
| 4416 | FP16_V8_2_INSN ("fmlal", 0x4e20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4417 | FP16_V8_2_INSN ("fmlsl", 0x4ea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4418 | FP16_V8_2_INSN ("fmlal2", 0x6e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4419 | FP16_V8_2_INSN ("fmlsl2", 0x6ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4420 | ||
| 369c9167 TC |
4421 | FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), |
| 4422 | FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
| 4423 | FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
| 4424 | FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
| e9dbdd80 | 4425 | |
| 369c9167 TC |
4426 | FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), |
| 4427 | FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
| 4428 | FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
| 4429 | FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
| e9dbdd80 TC |
4430 | /* System extensions ARMv8.4-a. */ |
| 4431 | V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0), | |
| 4432 | V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0), | |
| 4433 | V8_4_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), | |
| 4434 | V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), | |
| 4435 | /* Memory access instructions ARMv8.4-a. */ | |
| 4436 | V8_4_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4437 | V8_4_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4438 | V8_4_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4439 | V8_4_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4440 | V8_4_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4441 | V8_4_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4442 | V8_4_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4443 | V8_4_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4444 | V8_4_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4445 | V8_4_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4446 | V8_4_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4447 | V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4448 | V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| eae424ae | 4449 | {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, |
| a06ea964 NC |
4450 | }; |
| 4451 | ||
| 4452 | #ifdef AARCH64_OPERANDS | |
| 4453 | #undef AARCH64_OPERANDS | |
| 4454 | #endif | |
| 4455 | ||
| 4456 | /* Macro-based operand decription; this will be fed into aarch64-gen for it | |
| 4457 | to generate the structure aarch64_operands and the function | |
| 4458 | aarch64_insert_operand and aarch64_extract_operand. | |
| 4459 | ||
| 4460 | These inserters and extracters in the description execute the conversion | |
| 4461 | between the aarch64_opnd_info and value in the operand-related instruction | |
| 4462 | field(s). */ | |
| 4463 | ||
| 4464 | /* Y expects arguments (left to right) to be operand class, inserter/extractor | |
| 4465 | name suffix, operand name, flags, related bitfield(s) and description. | |
| 4466 | X only differs from Y by having the operand inserter and extractor names | |
| 4467 | listed separately. */ | |
| 4468 | ||
| 4469 | #define AARCH64_OPERANDS \ | |
| 4470 | Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \ | |
| 4471 | Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ | |
| 4472 | Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ | |
| 4473 | Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ | |
| 4474 | Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ | |
| 4475 | Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ | |
| 4476 | Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \ | |
| 4477 | X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \ | |
| 4478 | "an integer register") \ | |
| 4479 | Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \ | |
| 4480 | "an integer or stack pointer register") \ | |
| 4481 | Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ | |
| 4482 | "an integer or stack pointer register") \ | |
| c84364ec SN |
4483 | Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \ |
| 4484 | "an integer or stack pointer register") \ | |
| ee804238 JW |
4485 | X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ |
| 4486 | "the second reg of a pair") \ | |
| a06ea964 NC |
4487 | Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ |
| 4488 | "an integer register with optional extension") \ | |
| 4489 | Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \ | |
| 4490 | "an integer register with optional shift") \ | |
| 4491 | Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \ | |
| 4492 | Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \ | |
| 4493 | Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \ | |
| 4494 | Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \ | |
| 4495 | Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \ | |
| 4496 | Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \ | |
| 4497 | Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \ | |
| 4498 | Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \ | |
| 4499 | Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \ | |
| f42f1a1d | 4500 | Y(SIMD_REG, regno, "Va", 0, F(FLD_Ra), "a SIMD vector register") \ |
| a06ea964 NC |
4501 | Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \ |
| 4502 | Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \ | |
| 4503 | Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \ | |
| 4504 | Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \ | |
| 4505 | "the top half of a 128-bit FP/SIMD register") \ | |
| 4506 | Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \ | |
| 4507 | "the top half of a 128-bit FP/SIMD register") \ | |
| 4508 | Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \ | |
| 4509 | "a SIMD vector element") \ | |
| 4510 | Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \ | |
| 4511 | "a SIMD vector element") \ | |
| 4512 | Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ | |
| 4513 | "a SIMD vector element") \ | |
| 369c9167 TC |
4514 | Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ |
| 4515 | "a SIMD vector element limited to V0-V15") \ | |
| a06ea964 NC |
4516 | Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ |
| 4517 | "a SIMD vector register list") \ | |
| 4518 | Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ | |
| 4519 | "a SIMD vector register list") \ | |
| 4520 | Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \ | |
| 4521 | "a SIMD vector register list") \ | |
| 4522 | Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \ | |
| 4523 | "a SIMD vector element list") \ | |
| a6a51754 | 4524 | Y(IMMEDIATE, imm, "CRn", 0, F(FLD_CRn), \ |
| a06ea964 | 4525 | "a 4-bit opcode field named for historical reasons C0 - C15") \ |
| a6a51754 | 4526 | Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm), \ |
| a06ea964 NC |
4527 | "a 4-bit opcode field named for historical reasons C0 - C15") \ |
| 4528 | Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \ | |
| 4529 | "an immediate as the index of the least significant byte") \ | |
| f42f1a1d TC |
4530 | Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_2), \ |
| 4531 | "an immediate as the index of the least significant byte") \ | |
| a06ea964 NC |
4532 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ |
| 4533 | "a left shift amount for an AdvSIMD register") \ | |
| 4534 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \ | |
| 4535 | "a right shift amount for an AdvSIMD register") \ | |
| 4536 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \ | |
| 4537 | "an immediate") \ | |
| 4538 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \ | |
| 4539 | "an 8-bit unsigned immediate with optional shift") \ | |
| 4540 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \ | |
| 4541 | "an 8-bit floating-point constant") \ | |
| 4542 | X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \ | |
| 4543 | "an immediate shift amount of 8, 16 or 32") \ | |
| 4544 | X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \ | |
| 4545 | X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \ | |
| aa2aa4c6 | 4546 | Y(IMMEDIATE, fpimm, "FPIMM", 0, F(FLD_imm8), \ |
| a06ea964 NC |
4547 | "an 8-bit floating-point constant") \ |
| 4548 | Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ | |
| 4549 | "the right rotate amount") \ | |
| 4550 | Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \ | |
| 4551 | "the leftmost bit number to be moved from the source") \ | |
| 4552 | Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \ | |
| 4553 | "the width of the bit-field") \ | |
| f42f1a1d TC |
4554 | Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \ |
| 4555 | Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_2), "an immediate") \ | |
| a06ea964 NC |
4556 | Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ |
| 4557 | "a 3-bit unsigned immediate") \ | |
| 4558 | Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ | |
| 4559 | "a 3-bit unsigned immediate") \ | |
| 4560 | Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ | |
| 4561 | "a 4-bit unsigned immediate") \ | |
| 4562 | Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ | |
| 4563 | "a 7-bit unsigned immediate") \ | |
| 4564 | Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ | |
| 4565 | "the bit number to be tested") \ | |
| 4566 | Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ | |
| 4567 | "a 16-bit unsigned immediate") \ | |
| 4568 | Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ | |
| 4569 | "a 5-bit unsigned immediate") \ | |
| e950b345 RS |
4570 | Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ |
| 4571 | "a 5-bit signed immediate") \ | |
| a06ea964 NC |
4572 | Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ |
| 4573 | "a flag bit specifier giving an alternative value for each flag") \ | |
| 4574 | Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ | |
| 4575 | "Logical immediate") \ | |
| 4576 | Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ | |
| 4577 | "a 12-bit unsigned immediate with optional left shift of 12 bits")\ | |
| 4578 | Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \ | |
| 4579 | "a 16-bit immediate with optional left shift") \ | |
| 4580 | Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ | |
| 4581 | "the number of bits after the binary point in the fixed-point value")\ | |
| 4582 | X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \ | |
| 582e12bf | 4583 | Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD_rotate1), \ |
| c2c4ff8d | 4584 | "a 2-bit rotation specifier for complex arithmetic operations") \ |
| 582e12bf | 4585 | Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD_rotate2), \ |
| c2c4ff8d | 4586 | "a 2-bit rotation specifier for complex arithmetic operations") \ |
| 582e12bf | 4587 | Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD_rotate3), \ |
| c2c4ff8d | 4588 | "a 1-bit rotation specifier for complex arithmetic operations") \ |
| 68a64283 YZ |
4589 | Y(COND, cond, "COND", 0, F(), "a condition") \ |
| 4590 | Y(COND, cond, "COND1", 0, F(), \ | |
| 4591 | "one of the standard conditions, excluding AL and NV.") \ | |
| a06ea964 NC |
4592 | X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\ |
| 4593 | "21-bit PC-relative address of a 4KB page") \ | |
| 4594 | Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 4595 | F(FLD_imm14), "14-bit PC-relative address") \ | |
| 4596 | Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 4597 | F(FLD_imm19), "19-bit PC-relative address") \ | |
| 4598 | Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \ | |
| 4599 | "21-bit PC-relative address") \ | |
| 4600 | Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 4601 | F(FLD_imm26), "26-bit PC-relative address") \ | |
| 4602 | Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ | |
| 4603 | "an address with base register (no offset)") \ | |
| 4604 | Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ | |
| 4605 | "an address with register offset") \ | |
| 4606 | Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ | |
| 4607 | "an address with 7-bit signed immediate offset") \ | |
| 4608 | Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ | |
| 4609 | "an address with 9-bit signed immediate offset") \ | |
| 4610 | Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \ | |
| 4611 | "an address with 9-bit negative or unaligned immediate offset") \ | |
| 3f06e550 SN |
4612 | Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\ |
| 4613 | "an address with 10-bit scaled, signed immediate offset") \ | |
| a06ea964 NC |
4614 | Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \ |
| 4615 | "an address with scaled, unsigned immediate offset") \ | |
| 4616 | Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \ | |
| 4617 | "an address with base register (no offset)") \ | |
| f42f1a1d TC |
4618 | Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\ |
| 4619 | "an address with an optional 8-bit signed immediate offset") \ | |
| a06ea964 NC |
4620 | Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \ |
| 4621 | "a post-indexed address with immediate or register increment") \ | |
| 4622 | Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \ | |
| 4623 | Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \ | |
| 4624 | "a PSTATE field name") \ | |
| 4625 | Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \ | |
| 4626 | "an address translation operation specifier") \ | |
| 4627 | Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \ | |
| 4628 | "a data cache maintenance operation specifier") \ | |
| 4629 | Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \ | |
| 9ed608f9 | 4630 | "an instruction cache maintenance operation specifier") \ |
| a06ea964 NC |
4631 | Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ |
| 4632 | "a TBL invalidation operation specifier") \ | |
| 2ac435d4 SD |
4633 | Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \ |
| 4634 | "a Speculation Restriction option name (RCTX)") \ | |
| a06ea964 NC |
4635 | Y(SYSTEM, barrier, "BARRIER", 0, F(), \ |
| 4636 | "a barrier option name") \ | |
| 4637 | Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ | |
| 4638 | "the ISB option name SY or an optional 4-bit unsigned immediate") \ | |
| 4639 | Y(SYSTEM, prfop, "PRFOP", 0, F(), \ | |
| 1e6f4800 | 4640 | "a prefetch operation specifier") \ |
| 4df068de | 4641 | Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \ |
| f11ad6bc | 4642 | "the PSB option name CSYNC") \ |
| ff605452 SD |
4643 | Y(SYSTEM, hint, "BTI", 0, F (), \ |
| 4644 | "BTI targets j/c/jc") \ | |
| 582e12bf RS |
4645 | Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ |
| 4646 | 4 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4647 | "an address with a 4-bit signed offset, multiplied by 16") \ | |
| 98907a70 RS |
4648 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \ |
| 4649 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4650 | "an address with a 4-bit signed offset, multiplied by VL") \ | |
| 4651 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x2xVL", \ | |
| 4652 | 1 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4653 | "an address with a 4-bit signed offset, multiplied by 2*VL") \ | |
| 4654 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x3xVL", \ | |
| 4655 | 2 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4656 | "an address with a 4-bit signed offset, multiplied by 3*VL") \ | |
| 4657 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x4xVL", \ | |
| 4658 | 3 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4659 | "an address with a 4-bit signed offset, multiplied by 4*VL") \ | |
| 4660 | Y(ADDRESS, sve_addr_ri_s6xvl, "SVE_ADDR_RI_S6xVL", \ | |
| 4661 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4662 | "an address with a 6-bit signed offset, multiplied by VL") \ | |
| 4663 | Y(ADDRESS, sve_addr_ri_s9xvl, "SVE_ADDR_RI_S9xVL", \ | |
| 4664 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4665 | "an address with a 9-bit signed offset, multiplied by VL") \ | |
| 4df068de RS |
4666 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6", 0 << OPD_F_OD_LSB, \ |
| 4667 | F(FLD_Rn), "an address with a 6-bit unsigned offset") \ | |
| 4668 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB, \ | |
| 4669 | F(FLD_Rn), \ | |
| 4670 | "an address with a 6-bit unsigned offset, multiplied by 2") \ | |
| 4671 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB, \ | |
| 4672 | F(FLD_Rn), \ | |
| 4673 | "an address with a 6-bit unsigned offset, multiplied by 4") \ | |
| 4674 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB, \ | |
| 4675 | F(FLD_Rn), \ | |
| 4676 | "an address with a 6-bit unsigned offset, multiplied by 8") \ | |
| c8d59609 NC |
4677 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_R", 0 << OPD_F_OD_LSB, \ |
| 4678 | F(FLD_Rn,FLD_Rm), "an address with an optional scalar register offset") \ | |
| 4df068de RS |
4679 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR", 0 << OPD_F_OD_LSB, \ |
| 4680 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4681 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB, \ | |
| 4682 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4683 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB, \ | |
| 4684 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4685 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB, \ | |
| 4686 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4687 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX", \ | |
| 4688 | (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4689 | "an address with a scalar register offset") \ | |
| 4690 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL1", \ | |
| 4691 | (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4692 | "an address with a scalar register offset") \ | |
| 4693 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL2", \ | |
| 4694 | (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4695 | "an address with a scalar register offset") \ | |
| 4696 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ | |
| 4697 | (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4698 | "an address with a scalar register offset") \ | |
| 4699 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB, \ | |
| 4700 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4701 | "an address with a vector register offset") \ | |
| 4702 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB, \ | |
| 4703 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4704 | "an address with a vector register offset") \ | |
| 4705 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB, \ | |
| 4706 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4707 | "an address with a vector register offset") \ | |
| 4708 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB, \ | |
| 4709 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4710 | "an address with a vector register offset") \ | |
| 4711 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_14", \ | |
| 4712 | 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4713 | "an address with a vector register offset") \ | |
| 4714 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_22", \ | |
| 4715 | 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4716 | "an address with a vector register offset") \ | |
| 4717 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_14", \ | |
| 4718 | 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4719 | "an address with a vector register offset") \ | |
| 4720 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_22", \ | |
| 4721 | 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4722 | "an address with a vector register offset") \ | |
| 4723 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_14", \ | |
| 4724 | 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4725 | "an address with a vector register offset") \ | |
| 4726 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_22", \ | |
| 4727 | 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4728 | "an address with a vector register offset") \ | |
| 4729 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_14", \ | |
| 4730 | 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4731 | "an address with a vector register offset") \ | |
| 4732 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_22", \ | |
| 4733 | 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4734 | "an address with a vector register offset") \ | |
| 4735 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5", 0 << OPD_F_OD_LSB, \ | |
| 4736 | F(FLD_SVE_Zn), "an address with a 5-bit unsigned offset") \ | |
| 4737 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB, \ | |
| 4738 | F(FLD_SVE_Zn), \ | |
| 4739 | "an address with a 5-bit unsigned offset, multiplied by 2") \ | |
| 4740 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB, \ | |
| 4741 | F(FLD_SVE_Zn), \ | |
| 4742 | "an address with a 5-bit unsigned offset, multiplied by 4") \ | |
| 4743 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB, \ | |
| 4744 | F(FLD_SVE_Zn), \ | |
| 4745 | "an address with a 5-bit unsigned offset, multiplied by 8") \ | |
| 4746 | Y(ADDRESS, sve_addr_zz_lsl, "SVE_ADDR_ZZ_LSL", 0, \ | |
| 4747 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
| 4748 | "an address with a vector register offset") \ | |
| 4749 | Y(ADDRESS, sve_addr_zz_sxtw, "SVE_ADDR_ZZ_SXTW", 0, \ | |
| 4750 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
| 4751 | "an address with a vector register offset") \ | |
| 4752 | Y(ADDRESS, sve_addr_zz_uxtw, "SVE_ADDR_ZZ_UXTW", 0, \ | |
| 4753 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
| 4754 | "an address with a vector register offset") \ | |
| e950b345 RS |
4755 | Y(IMMEDIATE, sve_aimm, "SVE_AIMM", 0, F(FLD_SVE_imm9), \ |
| 4756 | "a 9-bit unsigned arithmetic operand") \ | |
| 4757 | Y(IMMEDIATE, sve_asimm, "SVE_ASIMM", 0, F(FLD_SVE_imm9), \ | |
| 4758 | "a 9-bit signed arithmetic operand") \ | |
| 165d4950 RS |
4759 | Y(IMMEDIATE, fpimm, "SVE_FPIMM8", 0, F(FLD_SVE_imm8), \ |
| 4760 | "an 8-bit floating-point immediate") \ | |
| 4761 | Y(IMMEDIATE, sve_float_half_one, "SVE_I1_HALF_ONE", 0, \ | |
| 4762 | F(FLD_SVE_i1), "either 0.5 or 1.0") \ | |
| 4763 | Y(IMMEDIATE, sve_float_half_two, "SVE_I1_HALF_TWO", 0, \ | |
| 4764 | F(FLD_SVE_i1), "either 0.5 or 2.0") \ | |
| 4765 | Y(IMMEDIATE, sve_float_zero_one, "SVE_I1_ZERO_ONE", 0, \ | |
| 4766 | F(FLD_SVE_i1), "either 0.0 or 1.0") \ | |
| 582e12bf RS |
4767 | Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD_SVE_rot1), \ |
| 4768 | "a 1-bit rotation specifier for complex arithmetic operations") \ | |
| 4769 | Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \ | |
| 4770 | "a 2-bit rotation specifier for complex arithmetic operations") \ | |
| e950b345 RS |
4771 | Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \ |
| 4772 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
| 4773 | "an inverted 13-bit logical immediate") \ | |
| 4774 | Y(IMMEDIATE, limm, "SVE_LIMM", 0, \ | |
| 4775 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
| 4776 | "a 13-bit logical immediate") \ | |
| 4777 | Y(IMMEDIATE, sve_limm_mov, "SVE_LIMM_MOV", 0, \ | |
| 4778 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
| 4779 | "a 13-bit logical move immediate") \ | |
| 245d2e3f RS |
4780 | Y(IMMEDIATE, imm, "SVE_PATTERN", 0, F(FLD_SVE_pattern), \ |
| 4781 | "an enumeration value such as POW2") \ | |
| 2442d846 RS |
4782 | Y(IMMEDIATE, sve_scale, "SVE_PATTERN_SCALED", 0, \ |
| 4783 | F(FLD_SVE_pattern), "an enumeration value such as POW2") \ | |
| 245d2e3f RS |
4784 | Y(IMMEDIATE, imm, "SVE_PRFOP", 0, F(FLD_SVE_prfop), \ |
| 4785 | "an enumeration value such as PLDL1KEEP") \ | |
| f11ad6bc RS |
4786 | Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD_SVE_Pd), \ |
| 4787 | "an SVE predicate register") \ | |
| 4788 | Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD_SVE_Pg3), \ | |
| 4789 | "an SVE predicate register") \ | |
| 4790 | Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD_SVE_Pg4_5), \ | |
| 4791 | "an SVE predicate register") \ | |
| 4792 | Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD_SVE_Pg4_10), \ | |
| 4793 | "an SVE predicate register") \ | |
| 4794 | Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD_SVE_Pg4_16), \ | |
| 4795 | "an SVE predicate register") \ | |
| 4796 | Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD_SVE_Pm), \ | |
| 4797 | "an SVE predicate register") \ | |
| 4798 | Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD_SVE_Pn), \ | |
| 4799 | "an SVE predicate register") \ | |
| 4800 | Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ | |
| 4801 | "an SVE predicate register") \ | |
| 047cd301 RS |
4802 | Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \ |
| 4803 | "an integer register or zero") \ | |
| 4804 | Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \ | |
| 4805 | "an integer register or SP") \ | |
| e950b345 RS |
4806 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \ |
| 4807 | F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ | |
| 4808 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ | |
| 4809 | F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ | |
| 4810 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0, \ | |
| 4811 | F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ | |
| 4812 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0, \ | |
| 4813 | F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ | |
| 4814 | Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ | |
| 4815 | "a 5-bit signed immediate") \ | |
| 4816 | Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ | |
| 4817 | "a 5-bit signed immediate") \ | |
| 4818 | Y(IMMEDIATE, imm, "SVE_SIMM6", OPD_F_SEXT, F(FLD_SVE_imms), \ | |
| 4819 | "a 6-bit signed immediate") \ | |
| 4820 | Y(IMMEDIATE, imm, "SVE_SIMM8", OPD_F_SEXT, F(FLD_SVE_imm8), \ | |
| 4821 | "an 8-bit signed immediate") \ | |
| 4822 | Y(IMMEDIATE, imm, "SVE_UIMM3", 0, F(FLD_SVE_imm3), \ | |
| 4823 | "a 3-bit unsigned immediate") \ | |
| 4824 | Y(IMMEDIATE, imm, "SVE_UIMM7", 0, F(FLD_SVE_imm7), \ | |
| 4825 | "a 7-bit unsigned immediate") \ | |
| 4826 | Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ | |
| 4827 | "an 8-bit unsigned immediate") \ | |
| 4828 | Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \ | |
| 4829 | "an 8-bit unsigned immediate") \ | |
| 047cd301 RS |
4830 | Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ |
| 4831 | Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ | |
| 4832 | Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \ | |
| 4833 | Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \ | |
| f11ad6bc RS |
4834 | Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ |
| 4835 | "an SVE vector register") \ | |
| 4836 | Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ | |
| 4837 | "an SVE vector register") \ | |
| 4838 | Y(SVE_REG, regno, "SVE_Zd", 0, F(FLD_SVE_Zd), \ | |
| 4839 | "an SVE vector register") \ | |
| 4840 | Y(SVE_REG, regno, "SVE_Zm_5", 0, F(FLD_SVE_Zm_5), \ | |
| 4841 | "an SVE vector register") \ | |
| 4842 | Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ | |
| 4843 | "an SVE vector register") \ | |
| 582e12bf RS |
4844 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \ |
| 4845 | 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ | |
| 4846 | "an indexed SVE vector register") \ | |
| 4847 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ | |
| 4848 | 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ | |
| 4849 | "an indexed SVE vector register") \ | |
| 4850 | Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \ | |
| 4851 | 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ | |
| 4852 | "an indexed SVE vector register") \ | |
| f11ad6bc RS |
4853 | Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ |
| 4854 | "an SVE vector register") \ | |
| 4855 | Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ | |
| 4856 | "an indexed SVE vector register") \ | |
| 4857 | Y(SVE_REG, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ | |
| 4858 | "a list of SVE vector registers") \ | |
| 4859 | Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ | |
| 4860 | "an SVE vector register") \ | |
| 4861 | Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ | |
| f42f1a1d TC |
4862 | "a list of SVE vector registers") \ |
| 4863 | Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ | |
| 4864 | "an indexed SM3 vector immediate") |