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Remove redundant init of config.make_executable to true.
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
01c7f630 2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6This file is part of libopcodes.
7
8This program is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2 of the License, or (at your option)
11any later version.
12
13This program is distributed in the hope that it will be useful, but WITHOUT
14ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16more details.
17
18You should have received a copy of the GNU General Public License
19along with this program; if not, write to the Free Software
20Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
cb6a5892 22#include "sysdep.h"
252b5132
RH		 23#include "dis-asm.h"
24#define DEFINE_TABLE
25#include "arm-opc.h"
26#include "coff/internal.h"
27#include "libcoff.h"
28#include "opintl.h"
29
30/* FIXME: This shouldn't be done here */
31#include "elf-bfd.h"
32#include "elf/internal.h"
33#include "elf/arm.h"
34
01c7f630 35#ifndef streq
58efb6c0 36#define streq(a,b) (strcmp ((a), (b)) == 0)
01c7f630 37#endif
58efb6c0 38
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
5876e06d 47static char * arm_conditional[] =
252b5132
RH		 48{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
50
58efb6c0
NC		 51typedef struct
52{
53 const char * name;
54 const char * description;
55 const char * reg_names[16];
56}
57arm_regname;
dd92f639 58
58efb6c0
NC		 59static arm_regname regnames[] =
60{
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
7c03c75e
SB		 63 { "gcc", "Select register names used by GCC",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
58efb6c0
NC		 65 { "std", "Select register names used in ARM's ISA documentation",
66 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
67 { "apcs", "Select register names used in the APCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
69 { "atpcs", "Select register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
a7f8487e 71 { "special-atpcs", "Select special register names used in the ATPCS",
58efb6c0
NC		 72 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
73};
74
7c03c75e 75/* Default to GCC register name set. */
58efb6c0
NC		 76static unsigned int regname_selected = 1;
77
78#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
79#define arm_regnames regnames[regname_selected].reg_names
252b5132 80
01c7f630
NC		 81static boolean force_thumb = false;
82
5876e06d 83static char * arm_fp_const[] =
252b5132
RH		 84{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
85
5876e06d 86static char * arm_shift[] =
252b5132 87{"lsl", "lsr", "asr", "ror"};
01c7f630
NC		 88\f
89/* Forward declarations. */
90static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
91static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
92static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
01c7f630 93static void parse_disassembler_options PARAMS ((char *));
58efb6c0 94static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
a7f8487e
FN		 95int get_arm_regname_num_options (void);
96int set_arm_regname_option (int option);
97int get_arm_regnames (int option, const char **setname,
98 const char **setdescription,
99 const char ***register_names);
01c7f630
NC		 100\f
101/* Functions. */
a7f8487e
FN		 102int
103get_arm_regname_num_options (void)
104{
105 return NUM_ARM_REGNAMES;
106}
107
108int
109set_arm_regname_option (int option)
110{
111 int old = regname_selected;
112 regname_selected = option;
113 return old;
114}
115
116int
117get_arm_regnames (int option, const char **setname,
118 const char **setdescription,
119 const char ***register_names)
120{
121 *setname = regnames[option].name;
122 *setdescription = regnames[option].description;
123 *register_names = regnames[option].reg_names;
124 return 16;
125}
126
252b5132
RH		 127static void
128arm_decode_shift (given, func, stream)
129 long given;
130 fprintf_ftype func;
5876e06d 131 void * stream;
252b5132
RH		 132{
133 func (stream, "%s", arm_regnames[given & 0xf]);
5876e06d 134
252b5132
RH		 135 if ((given & 0xff0) != 0)
136 {
137 if ((given & 0x10) == 0)
138 {
139 int amount = (given & 0xf80) >> 7;
140 int shift = (given & 0x60) >> 5;
5876e06d 141
252b5132
RH		 142 if (amount == 0)
143 {
144 if (shift == 3)
145 {
146 func (stream, ", rrx");
147 return;
148 }
5876e06d 149
252b5132
RH		 150 amount = 32;
151 }
5876e06d 152
252b5132
RH		 153 func (stream, ", %s #%d", arm_shift[shift], amount);
154 }
155 else
156 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
157 arm_regnames[(given & 0xf00) >> 8]);
158 }
159}
160
161/* Print one instruction from PC on INFO->STREAM.
162 Return the size of the instruction (always 4 on ARM). */
252b5132
RH		 163static int
164print_insn_arm (pc, info, given)
5876e06d
NC		 165 bfd_vma pc;
166 struct disassemble_info * info;
167 long given;
252b5132
RH		 168{
169 struct arm_opcode * insn;
170 void * stream = info->stream;
171 fprintf_ftype func = info->fprintf_func;
172
173 for (insn = arm_opcodes; insn->assembler; insn++)
174 {
175 if ((given & insn->mask) == insn->value)
176 {
177 char * c;
178
179 for (c = insn->assembler; *c; c++)
180 {
181 if (*c == '%')
182 {
183 switch (*++c)
184 {
185 case '%':
186 func (stream, "%%");
187 break;
188
189 case 'a':
190 if (((given & 0x000f0000) == 0x000f0000)
191 && ((given & 0x02000000) == 0))
192 {
193 int offset = given & 0xfff;
194
195 func (stream, "[pc");
196
197 if (given & 0x01000000)
198 {
199 if ((given & 0x00800000) == 0)
200 offset = - offset;
201
202 /* pre-indexed */
203 func (stream, ", #%x]", offset);
204
205 offset += pc + 8;
206
58efb6c0
NC		 207 /* Cope with the possibility of write-back
208 being used. Probably a very dangerous thing
209 for the programmer to do, but who are we to
210 argue ? */
252b5132
RH		 211 if (given & 0x00200000)
212 func (stream, "!");
213 }
214 else
215 {
58efb6c0 216 /* Post indexed. */
252b5132
RH		 217 func (stream, "], #%x", offset);
218
58efb6c0 219 offset = pc + 8; /* ie ignore the offset. */
252b5132
RH		 220 }
221
222 func (stream, "\t; ");
223 info->print_address_func (offset, info);
224 }
225 else
226 {
227 func (stream, "[%s",
228 arm_regnames[(given >> 16) & 0xf]);
229 if ((given & 0x01000000) != 0)
230 {
231 if ((given & 0x02000000) == 0)
232 {
233 int offset = given & 0xfff;
234 if (offset)
235 func (stream, ", %s#%d",
236 (((given & 0x00800000) == 0)
237 ? "-" : ""), offset);
238 }
239 else
240 {
241 func (stream, ", %s",
242 (((given & 0x00800000) == 0)
243 ? "-" : ""));
244 arm_decode_shift (given, func, stream);
245 }
246
247 func (stream, "]%s",
248 ((given & 0x00200000) != 0) ? "!" : "");
249 }
250 else
251 {
252 if ((given & 0x02000000) == 0)
253 {
254 int offset = given & 0xfff;
255 if (offset)
256 func (stream, "], %s#%d",
257 (((given & 0x00800000) == 0)
258 ? "-" : ""), offset);
259 else
260 func (stream, "]");
261 }
262 else
263 {
264 func (stream, "], %s",
265 (((given & 0x00800000) == 0)
266 ? "-" : ""));
267 arm_decode_shift (given, func, stream);
268 }
269 }
270 }
271 break;
272
273 case 's':
274 if ((given & 0x004f0000) == 0x004f0000)
275 {
58efb6c0 276 /* PC relative with immediate offset. */
252b5132 277 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
886796f9 278
252b5132
RH		 279 if ((given & 0x00800000) == 0)
280 offset = -offset;
886796f9
NC		 281
282 func (stream, "[pc, #%x]\t; ", offset);
283
252b5132
RH		 284 (*info->print_address_func)
285 (offset + pc + 8, info);
286 }
287 else
288 {
289 func (stream, "[%s",
290 arm_regnames[(given >> 16) & 0xf]);
291 if ((given & 0x01000000) != 0)
292 {
58efb6c0 293 /* Pre-indexed. */
252b5132
RH		 294 if ((given & 0x00400000) == 0x00400000)
295 {
58efb6c0 296 /* Immediate. */
252b5132
RH		 297 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
298 if (offset)
299 func (stream, ", %s#%d",
300 (((given & 0x00800000) == 0)
301 ? "-" : ""), offset);
302 }
303 else
304 {
58efb6c0 305 /* Register. */
252b5132
RH		 306 func (stream, ", %s%s",
307 (((given & 0x00800000) == 0)
308 ? "-" : ""),
309 arm_regnames[given & 0xf]);
310 }
311
312 func (stream, "]%s",
313 ((given & 0x00200000) != 0) ? "!" : "");
314 }
315 else
316 {
58efb6c0 317 /* Post-indexed. */
252b5132
RH		 318 if ((given & 0x00400000) == 0x00400000)
319 {
58efb6c0 320 /* Immediate. */
252b5132
RH		 321 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
322 if (offset)
323 func (stream, "], %s#%d",
324 (((given & 0x00800000) == 0)
325 ? "-" : ""), offset);
326 else
327 func (stream, "]");
328 }
329 else
330 {
58efb6c0 331 /* Register. */
252b5132
RH		 332 func (stream, "], %s%s",
333 (((given & 0x00800000) == 0)
334 ? "-" : ""),
335 arm_regnames[given & 0xf]);
336 }
337 }
338 }
339 break;
340
341 case 'b':
342 (*info->print_address_func)
343 (BDISP (given) * 4 + pc + 8, info);
344 break;
345
346 case 'c':
347 func (stream, "%s",
348 arm_conditional [(given >> 28) & 0xf]);
349 break;
350
351 case 'm':
352 {
353 int started = 0;
354 int reg;
355
356 func (stream, "{");
357 for (reg = 0; reg < 16; reg++)
358 if ((given & (1 << reg)) != 0)
359 {
360 if (started)
361 func (stream, ", ");
362 started = 1;
363 func (stream, "%s", arm_regnames[reg]);
364 }
365 func (stream, "}");
366 }
367 break;
368
369 case 'o':
370 if ((given & 0x02000000) != 0)
371 {
372 int rotate = (given & 0xf00) >> 7;
373 int immed = (given & 0xff);
9f20bbfd
NC		 374 immed = (((immed << (32 - rotate))
375 | (immed >> rotate)) & 0xffffffff);
376 func (stream, "#%d\t; 0x%x", immed, immed);
252b5132
RH		 377 }
378 else
379 arm_decode_shift (given, func, stream);
380 break;
381
382 case 'p':
383 if ((given & 0x0000f000) == 0x0000f000)
384 func (stream, "p");
385 break;
386
387 case 't':
388 if ((given & 0x01200000) == 0x00200000)
389 func (stream, "t");
390 break;
391
392 case 'h':
393 if ((given & 0x00000020) == 0x00000020)
394 func (stream, "h");
395 else
396 func (stream, "b");
397 break;
398
399 case 'A':
400 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
401 if ((given & 0x01000000) != 0)
402 {
403 int offset = given & 0xff;
404 if (offset)
405 func (stream, ", %s#%d]%s",
406 ((given & 0x00800000) == 0 ? "-" : ""),
407 offset * 4,
408 ((given & 0x00200000) != 0 ? "!" : ""));
409 else
410 func (stream, "]");
411 }
412 else
413 {
414 int offset = given & 0xff;
415 if (offset)
416 func (stream, "], %s#%d",
417 ((given & 0x00800000) == 0 ? "-" : ""),
418 offset * 4);
419 else
420 func (stream, "]");
421 }
422 break;
423
424 case 'C':
6eeeb4b4
AO		 425 func (stream, "_");
426 if (given & 0x80000)
427 func (stream, "f");
428 if (given & 0x40000)
429 func (stream, "s");
430 if (given & 0x20000)
431 func (stream, "x");
432 if (given & 0x10000)
433 func (stream, "c");
252b5132
RH		 434 break;
435
436 case 'F':
437 switch (given & 0x00408000)
438 {
439 case 0:
440 func (stream, "4");
441 break;
442 case 0x8000:
443 func (stream, "1");
444 break;
445 case 0x00400000:
446 func (stream, "2");
447 break;
448 default:
449 func (stream, "3");
450 }
451 break;
452
453 case 'P':
454 switch (given & 0x00080080)
455 {
456 case 0:
457 func (stream, "s");
458 break;
459 case 0x80:
460 func (stream, "d");
461 break;
462 case 0x00080000:
463 func (stream, "e");
464 break;
465 default:
466 func (stream, _("<illegal precision>"));
467 break;
468 }
469 break;
470 case 'Q':
471 switch (given & 0x00408000)
472 {
473 case 0:
474 func (stream, "s");
475 break;
476 case 0x8000:
477 func (stream, "d");
478 break;
479 case 0x00400000:
480 func (stream, "e");
481 break;
482 default:
483 func (stream, "p");
484 break;
485 }
486 break;
487 case 'R':
488 switch (given & 0x60)
489 {
490 case 0:
491 break;
492 case 0x20:
493 func (stream, "p");
494 break;
495 case 0x40:
496 func (stream, "m");
497 break;
498 default:
499 func (stream, "z");
500 break;
501 }
502 break;
503
504 case '0': case '1': case '2': case '3': case '4':
505 case '5': case '6': case '7': case '8': case '9':
506 {
507 int bitstart = *c++ - '0';
508 int bitend = 0;
509 while (*c >= '0' && *c <= '9')
510 bitstart = (bitstart * 10) + *c++ - '0';
511
512 switch (*c)
513 {
514 case '-':
515 c++;
58efb6c0 516
252b5132
RH		 517 while (*c >= '0' && *c <= '9')
518 bitend = (bitend * 10) + *c++ - '0';
58efb6c0 519
252b5132
RH		 520 if (!bitend)
521 abort ();
58efb6c0 522
252b5132
RH		 523 switch (*c)
524 {
525 case 'r':
526 {
527 long reg;
58efb6c0 528
252b5132
RH		 529 reg = given >> bitstart;
530 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 531
252b5132
RH		 532 func (stream, "%s", arm_regnames[reg]);
533 }
534 break;
535 case 'd':
536 {
537 long reg;
58efb6c0 538
252b5132
RH		 539 reg = given >> bitstart;
540 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 541
252b5132
RH		 542 func (stream, "%d", reg);
543 }
544 break;
545 case 'x':
546 {
547 long reg;
58efb6c0 548
252b5132
RH		 549 reg = given >> bitstart;
550 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 551
252b5132 552 func (stream, "0x%08x", reg);
5876e06d 553
58efb6c0
NC		 554 /* Some SWI instructions have special
555 meanings. */
5876e06d
NC		 556 if ((given & 0x0fffffff) == 0x0FF00000)
557 func (stream, "\t; IMB");
558 else if ((given & 0x0fffffff) == 0x0FF00001)
559 func (stream, "\t; IMBRange");
252b5132
RH		 560 }
561 break;
cfbd315c
DL		 562 case 'X':
563 {
564 long reg;
58efb6c0 565
cfbd315c
DL		 566 reg = given >> bitstart;
567 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 568
cfbd315c
DL		 569 func (stream, "%01x", reg & 0xf);
570 }
571 break;
252b5132
RH		 572 case 'f':
573 {
574 long reg;
58efb6c0 575
252b5132
RH		 576 reg = given >> bitstart;
577 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 578
252b5132
RH		 579 if (reg > 7)
580 func (stream, "#%s",
581 arm_fp_const[reg & 7]);
582 else
583 func (stream, "f%d", reg);
584 }
585 break;
586 default:
587 abort ();
588 }
589 break;
58efb6c0 590
252b5132
RH		 591 case '`':
592 c++;
593 if ((given & (1 << bitstart)) == 0)
594 func (stream, "%c", *c);
595 break;
596 case '\'':
597 c++;
598 if ((given & (1 << bitstart)) != 0)
599 func (stream, "%c", *c);
600 break;
601 case '?':
602 ++c;
603 if ((given & (1 << bitstart)) != 0)
604 func (stream, "%c", *c++);
605 else
606 func (stream, "%c", *++c);
607 break;
608 default:
609 abort ();
610 }
611 break;
612
613 default:
614 abort ();
615 }
616 }
617 }
618 else
619 func (stream, "%c", *c);
620 }
621 return 4;
622 }
623 }
624 abort ();
625}
626
627/* Print one instruction from PC on INFO->STREAM.
628 Return the size of the instruction. */
252b5132
RH		 629static int
630print_insn_thumb (pc, info, given)
5876e06d
NC		 631 bfd_vma pc;
632 struct disassemble_info * info;
633 long given;
252b5132 634{
5876e06d
NC		 635 struct thumb_opcode * insn;
636 void * stream = info->stream;
637 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 638
639 for (insn = thumb_opcodes; insn->assembler; insn++)
640 {
641 if ((given & insn->mask) == insn->value)
642 {
5876e06d 643 char * c = insn->assembler;
252b5132 644
58efb6c0
NC		 645 /* Special processing for Thumb 2 instruction BL sequence: */
646 if (!*c) /* Check for empty (not NULL) assembler string. */
252b5132
RH		 647 {
648 info->bytes_per_chunk = 4;
649 info->bytes_per_line = 4;
650
a3d9c82d
NC		 651 func (stream, "bl\t");
652
58efb6c0 653 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
252b5132
RH		 654 return 4;
655 }
656 else
657 {
658 info->bytes_per_chunk = 2;
659 info->bytes_per_line = 4;
660
661 given &= 0xffff;
58efb6c0 662
252b5132
RH		 663 for (; *c; c++)
664 {
665 if (*c == '%')
666 {
667 int domaskpc = 0;
668 int domasklr = 0;
5876e06d 669
252b5132
RH		 670 switch (*++c)
671 {
672 case '%':
673 func (stream, "%%");
674 break;
675
676 case 'S':
677 {
678 long reg;
58efb6c0 679
252b5132
RH		 680 reg = (given >> 3) & 0x7;
681 if (given & (1 << 6))
682 reg += 8;
58efb6c0 683
252b5132
RH		 684 func (stream, "%s", arm_regnames[reg]);
685 }
686 break;
687
688 case 'D':
689 {
690 long reg;
5876e06d 691
252b5132
RH		 692 reg = given & 0x7;
693 if (given & (1 << 7))
694 reg += 8;
58efb6c0 695
252b5132
RH		 696 func (stream, "%s", arm_regnames[reg]);
697 }
698 break;
699
700 case 'T':
701 func (stream, "%s",
702 arm_conditional [(given >> 8) & 0xf]);
703 break;
704
705 case 'N':
706 if (given & (1 << 8))
707 domasklr = 1;
58efb6c0 708 /* Fall through. */
252b5132
RH		 709 case 'O':
710 if (*c == 'O' && (given & (1 << 8)))
711 domaskpc = 1;
58efb6c0 712 /* Fall through. */
252b5132
RH		 713 case 'M':
714 {
715 int started = 0;
716 int reg;
5876e06d 717
252b5132 718 func (stream, "{");
58efb6c0 719
252b5132
RH		 720 /* It would be nice if we could spot
721 ranges, and generate the rS-rE format: */
722 for (reg = 0; (reg < 8); reg++)
723 if ((given & (1 << reg)) != 0)
724 {
725 if (started)
726 func (stream, ", ");
727 started = 1;
728 func (stream, "%s", arm_regnames[reg]);
729 }
730
731 if (domasklr)
732 {
733 if (started)
734 func (stream, ", ");
735 started = 1;
a7f8487e 736 func (stream, arm_regnames[14] /* "lr" */);
252b5132
RH		 737 }
738
739 if (domaskpc)
740 {
741 if (started)
742 func (stream, ", ");
a7f8487e 743 func (stream, arm_regnames[15] /* "pc" */);
252b5132
RH		 744 }
745
746 func (stream, "}");
747 }
748 break;
749
750
751 case '0': case '1': case '2': case '3': case '4':
752 case '5': case '6': case '7': case '8': case '9':
753 {
754 int bitstart = *c++ - '0';
755 int bitend = 0;
5876e06d 756
252b5132
RH		 757 while (*c >= '0' && *c <= '9')
758 bitstart = (bitstart * 10) + *c++ - '0';
759
760 switch (*c)
761 {
762 case '-':
763 {
764 long reg;
5876e06d 765
252b5132
RH		 766 c++;
767 while (*c >= '0' && *c <= '9')
768 bitend = (bitend * 10) + *c++ - '0';
769 if (!bitend)
770 abort ();
771 reg = given >> bitstart;
772 reg &= (2 << (bitend - bitstart)) - 1;
773 switch (*c)
774 {
775 case 'r':
776 func (stream, "%s", arm_regnames[reg]);
777 break;
778
779 case 'd':
780 func (stream, "%d", reg);
781 break;
782
783 case 'H':
784 func (stream, "%d", reg << 1);
785 break;
786
787 case 'W':
788 func (stream, "%d", reg << 2);
789 break;
790
791 case 'a':
792 /* PC-relative address -- the bottom two
58efb6c0
NC		 793 bits of the address are dropped
794 before the calculation. */
252b5132
RH		 795 info->print_address_func
796 (((pc + 4) & ~3) + (reg << 2), info);
797 break;
798
799 case 'x':
800 func (stream, "0x%04x", reg);
801 break;
802
803 case 'I':
804 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
805 func (stream, "%d", reg);
806 break;
807
808 case 'B':
809 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
810 (*info->print_address_func)
811 (reg * 2 + pc + 4, info);
812 break;
813
814 default:
5876e06d 815 abort ();
252b5132
RH		 816 }
817 }
818 break;
819
820 case '\'':
821 c++;
822 if ((given & (1 << bitstart)) != 0)
823 func (stream, "%c", *c);
824 break;
825
826 case '?':
827 ++c;
828 if ((given & (1 << bitstart)) != 0)
829 func (stream, "%c", *c++);
830 else
831 func (stream, "%c", *++c);
832 break;
833
834 default:
5876e06d 835 abort ();
252b5132
RH		 836 }
837 }
838 break;
839
840 default:
841 abort ();
842 }
843 }
844 else
845 func (stream, "%c", *c);
846 }
847 }
848 return 2;
849 }
850 }
851
58efb6c0 852 /* No match. */
252b5132
RH		 853 abort ();
854}
855
58efb6c0 856/* Parse an individual disassembler option. */
a3d9c82d
NC		 857void
858parse_arm_disassembler_option (option)
01c7f630 859 char * option;
dd92f639 860{
01c7f630 861 if (option == NULL)
dd92f639
NC		 862 return;
863
01c7f630 864 if (strneq (option, "reg-names-", 10))
dd92f639 865 {
58efb6c0
NC		 866 int i;
867
01c7f630 868 option += 10;
58efb6c0
NC		 869
870 for (i = NUM_ARM_REGNAMES; i--;)
871 if (streq (option, regnames[i].name))
872 {
873 regname_selected = i;
874 break;
875 }
dd92f639 876
58efb6c0
NC		 877 if (i < 0)
878 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 879 }
01c7f630
NC		 880 else if (streq (option, "force-thumb"))
881 force_thumb = 1;
882 else if (streq (option, "no-force-thumb"))
883 force_thumb = 0;
dd92f639 884 else
58efb6c0 885 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
dd92f639
NC		 886
887 return;
888}
889
58efb6c0 890/* Parse the string of disassembler options, spliting it at whitespaces. */
01c7f630
NC		 891static void
892parse_disassembler_options (options)
893 char * options;
894{
895 char * space;
896
897 if (options == NULL)
898 return;
899
900 do
901 {
902 space = strchr (options, ' ');
903
904 if (space)
905 {
906 * space = '\0';
a3d9c82d 907 parse_arm_disassembler_option (options);
01c7f630
NC		 908 * space = ' ';
909 options = space + 1;
910 }
911 else
a3d9c82d 912 parse_arm_disassembler_option (options);
01c7f630
NC		 913 }
914 while (space);
915}
916
58efb6c0
NC		 917/* NOTE: There are no checks in these routines that
918 the relevant number of data bytes exist. */
919static int
920print_insn (pc, info, little)
252b5132 921 bfd_vma pc;
5876e06d 922 struct disassemble_info * info;
58efb6c0 923 boolean little;
252b5132
RH		 924{
925 unsigned char b[4];
926 long given;
927 int status;
252b5132 928 int is_thumb;
58efb6c0 929
dd92f639
NC		 930 if (info->disassembler_options)
931 {
932 parse_disassembler_options (info->disassembler_options);
933
58efb6c0 934 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 935 info->disassembler_options = NULL;
936 }
937
01c7f630
NC		 938 is_thumb = force_thumb;
939
940 if (!is_thumb && info->symbols != NULL)
252b5132 941 {
5876e06d
NC		 942 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
943 {
2f0ca46a
NC		 944 coff_symbol_type * cs;
945
5876e06d
NC		 946 cs = coffsymbol (*info->symbols);
947 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
948 || cs->native->u.syment.n_sclass == C_THUMBSTAT
949 || cs->native->u.syment.n_sclass == C_THUMBLABEL
950 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
951 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
952 }
953 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
954 {
2f0ca46a 955 elf_symbol_type * es;
58efb6c0 956 unsigned int type;
2f0ca46a 957
5876e06d 958 es = *(elf_symbol_type **)(info->symbols);
58efb6c0
NC		 959 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
960
961 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
5876e06d
NC		 962 }
963 }
58efb6c0 964
252b5132 965 info->bytes_per_chunk = 4;
58efb6c0 966 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
252b5132 967
58efb6c0 968 if (little)
252b5132 969 {
58efb6c0
NC		 970 status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
971 if (status != 0 && is_thumb)
972 {
973 info->bytes_per_chunk = 2;
974
975 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
976 b[3] = b[2] = 0;
977 }
978
979 if (status != 0)
980 {
981 info->memory_error_func (status, pc, info);
982 return -1;
983 }
984
985 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
252b5132 986 }
58efb6c0 987 else
252b5132 988 {
58efb6c0
NC		 989 status = info->read_memory_func
990 (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
991 if (status != 0)
252b5132 992 {
58efb6c0
NC		 993 info->memory_error_func (status, pc, info);
994 return -1;
995 }
996
997 if (is_thumb)
998 {
999 if (pc & 0x2)
252b5132 1000 {
58efb6c0
NC		 1001 given = (b[2] << 8) | b[3];
1002
1003 status = info->read_memory_func
1004 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
1005 if (status != 0)
1006 {
1007 info->memory_error_func (status, pc + 4, info);
1008 return -1;
1009 }
1010
1011 given |= (b[0] << 24) | (b[1] << 16);
252b5132 1012 }
58efb6c0
NC		 1013 else
1014 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
252b5132
RH		 1015 }
1016 else
58efb6c0 1017 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
252b5132 1018 }
58efb6c0 1019
252b5132 1020 if (is_thumb)
5876e06d 1021 status = print_insn_thumb (pc, info, given);
252b5132 1022 else
5876e06d 1023 status = print_insn_arm (pc, info, given);
252b5132
RH		 1024
1025 return status;
1026}
1027
1028int
58efb6c0 1029print_insn_big_arm (pc, info)
252b5132
RH		 1030 bfd_vma pc;
1031 struct disassemble_info * info;
1032{
58efb6c0
NC		 1033 return print_insn (pc, info, false);
1034}
01c7f630 1035
58efb6c0
NC		 1036int
1037print_insn_little_arm (pc, info)
1038 bfd_vma pc;
1039 struct disassemble_info * info;
1040{
1041 return print_insn (pc, info, true);
1042}
252b5132 1043
58efb6c0
NC		 1044void
1045print_arm_disassembler_options (FILE * stream)
1046{
1047 int i;
252b5132 1048
58efb6c0
NC		 1049 fprintf (stream, _("\n\
1050The following ARM specific disassembler options are supported for use with\n\
1051the -M switch:\n"));
01c7f630 1052
58efb6c0
NC		 1053 for (i = NUM_ARM_REGNAMES; i--;)
1054 fprintf (stream, " reg-names-%s %*c%s\n",
1055 regnames[i].name,
1056 14 - strlen (regnames[i].name), ' ',
1057 regnames[i].description);
1058
1059 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
1060 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
252b5132 1061}
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