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aarch64: Fix the hyphenated disassembly comment.
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
fd67aa11 2 Copyright (C) 1994-2024 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
1fbaefec
PB		 42/* Cached mapping symbol state. */
43enum map_type
44{
45 MAP_ARM,
46 MAP_THUMB,
47 MAP_DATA
48};
49
b0e28b39
DJ		 50struct arm_private_data
51{
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features;
54
1fbaefec
PB		 55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type;
57
58 /* Tracking symbol table information */
59 int last_mapping_sym;
796d6298
TC		 60
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset;
1fbaefec 63 bfd_vma last_mapping_addr;
b0e28b39
DJ		 64};
65
73cd51e5
AV		 66enum mve_instructions
67{
143275ea
AV		 68 MVE_VPST,
69 MVE_VPT_FP_T1,
70 MVE_VPT_FP_T2,
71 MVE_VPT_VEC_T1,
72 MVE_VPT_VEC_T2,
73 MVE_VPT_VEC_T3,
74 MVE_VPT_VEC_T4,
75 MVE_VPT_VEC_T5,
76 MVE_VPT_VEC_T6,
77 MVE_VCMP_FP_T1,
78 MVE_VCMP_FP_T2,
79 MVE_VCMP_VEC_T1,
80 MVE_VCMP_VEC_T2,
81 MVE_VCMP_VEC_T3,
82 MVE_VCMP_VEC_T4,
83 MVE_VCMP_VEC_T5,
84 MVE_VCMP_VEC_T6,
9743db03
AV		 85 MVE_VDUP,
86 MVE_VEOR,
87 MVE_VFMAS_FP_SCALAR,
88 MVE_VFMA_FP_SCALAR,
89 MVE_VFMA_FP,
90 MVE_VFMS_FP,
91 MVE_VHADD_T1,
92 MVE_VHADD_T2,
93 MVE_VHSUB_T1,
94 MVE_VHSUB_T2,
95 MVE_VRHADD,
04d54ace
AV		 96 MVE_VLD2,
97 MVE_VLD4,
98 MVE_VST2,
99 MVE_VST4,
aef6d006
AV		 100 MVE_VLDRB_T1,
101 MVE_VLDRH_T2,
102 MVE_VLDRB_T5,
103 MVE_VLDRH_T6,
104 MVE_VLDRW_T7,
105 MVE_VSTRB_T1,
106 MVE_VSTRH_T2,
107 MVE_VSTRB_T5,
108 MVE_VSTRH_T6,
109 MVE_VSTRW_T7,
ef1576a1
AV		 110 MVE_VLDRB_GATHER_T1,
111 MVE_VLDRH_GATHER_T2,
112 MVE_VLDRW_GATHER_T3,
113 MVE_VLDRD_GATHER_T4,
114 MVE_VLDRW_GATHER_T5,
115 MVE_VLDRD_GATHER_T6,
116 MVE_VSTRB_SCATTER_T1,
117 MVE_VSTRH_SCATTER_T2,
118 MVE_VSTRW_SCATTER_T3,
119 MVE_VSTRD_SCATTER_T4,
120 MVE_VSTRW_SCATTER_T5,
121 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 122 MVE_VCVT_FP_FIX_VEC,
123 MVE_VCVT_BETWEEN_FP_INT,
124 MVE_VCVT_FP_HALF_FP,
125 MVE_VCVT_FROM_FP_TO_INT,
126 MVE_VRINT_FP,
c507f10b
AV		 127 MVE_VMOV_HFP_TO_GP,
128 MVE_VMOV_GP_TO_VEC_LANE,
129 MVE_VMOV_IMM_TO_VEC,
130 MVE_VMOV_VEC_TO_VEC,
131 MVE_VMOV2_VEC_LANE_TO_GP,
132 MVE_VMOV2_GP_TO_VEC_LANE,
133 MVE_VMOV_VEC_LANE_TO_GP,
134 MVE_VMVN_IMM,
135 MVE_VMVN_REG,
136 MVE_VORR_IMM,
137 MVE_VORR_REG,
138 MVE_VORN,
139 MVE_VBIC_IMM,
140 MVE_VBIC_REG,
141 MVE_VMOVX,
14925797
AV		 142 MVE_VMOVL,
143 MVE_VMOVN,
144 MVE_VMULL_INT,
145 MVE_VMULL_POLY,
146 MVE_VQDMULL_T1,
147 MVE_VQDMULL_T2,
148 MVE_VQMOVN,
149 MVE_VQMOVUN,
d3b63143
AV		 150 MVE_VADDV,
151 MVE_VMLADAV_T1,
152 MVE_VMLADAV_T2,
153 MVE_VMLALDAV,
154 MVE_VMLAS,
155 MVE_VADDLV,
156 MVE_VMLSDAV_T1,
157 MVE_VMLSDAV_T2,
158 MVE_VMLSLDAV,
159 MVE_VRMLALDAVH,
160 MVE_VRMLSLDAVH,
161 MVE_VQDMLADH,
162 MVE_VQRDMLADH,
163 MVE_VQDMLAH,
164 MVE_VQRDMLAH,
165 MVE_VQDMLASH,
166 MVE_VQRDMLASH,
167 MVE_VQDMLSDH,
168 MVE_VQRDMLSDH,
169 MVE_VQDMULH_T1,
170 MVE_VQRDMULH_T2,
171 MVE_VQDMULH_T3,
172 MVE_VQRDMULH_T4,
1c8f2df8
AV		 173 MVE_VDDUP,
174 MVE_VDWDUP,
175 MVE_VIWDUP,
176 MVE_VIDUP,
897b9bbc
AV		 177 MVE_VCADD_FP,
178 MVE_VCADD_VEC,
179 MVE_VHCADD,
180 MVE_VCMLA_FP,
181 MVE_VCMUL_FP,
ed63aa17
AV		 182 MVE_VQRSHL_T1,
183 MVE_VQRSHL_T2,
184 MVE_VQRSHRN,
185 MVE_VQRSHRUN,
186 MVE_VQSHL_T1,
187 MVE_VQSHL_T2,
188 MVE_VQSHLU_T3,
189 MVE_VQSHL_T4,
190 MVE_VQSHRN,
191 MVE_VQSHRUN,
192 MVE_VRSHL_T1,
193 MVE_VRSHL_T2,
194 MVE_VRSHR,
195 MVE_VRSHRN,
196 MVE_VSHL_T1,
197 MVE_VSHL_T2,
198 MVE_VSHL_T3,
199 MVE_VSHLC,
200 MVE_VSHLL_T1,
201 MVE_VSHLL_T2,
202 MVE_VSHR,
203 MVE_VSHRN,
204 MVE_VSLI,
205 MVE_VSRI,
66dcaa5d
AV		 206 MVE_VADC,
207 MVE_VABAV,
208 MVE_VABD_FP,
209 MVE_VABD_VEC,
210 MVE_VABS_FP,
211 MVE_VABS_VEC,
212 MVE_VADD_FP_T1,
213 MVE_VADD_FP_T2,
214 MVE_VADD_VEC_T1,
215 MVE_VADD_VEC_T2,
216 MVE_VSBC,
217 MVE_VSUB_FP_T1,
218 MVE_VSUB_FP_T2,
219 MVE_VSUB_VEC_T1,
220 MVE_VSUB_VEC_T2,
e523f101
AV		 221 MVE_VAND,
222 MVE_VBRSR,
223 MVE_VCLS,
224 MVE_VCLZ,
225 MVE_VCTP,
56858bea
AV		 226 MVE_VMAX,
227 MVE_VMAXA,
228 MVE_VMAXNM_FP,
229 MVE_VMAXNMA_FP,
230 MVE_VMAXNMV_FP,
231 MVE_VMAXNMAV_FP,
232 MVE_VMAXV,
233 MVE_VMAXAV,
234 MVE_VMIN,
235 MVE_VMINA,
236 MVE_VMINNM_FP,
237 MVE_VMINNMA_FP,
238 MVE_VMINNMV_FP,
239 MVE_VMINNMAV_FP,
240 MVE_VMINV,
241 MVE_VMINAV,
242 MVE_VMLA,
f49bb598
AV		 243 MVE_VMUL_FP_T1,
244 MVE_VMUL_FP_T2,
245 MVE_VMUL_VEC_T1,
246 MVE_VMUL_VEC_T2,
247 MVE_VMULH,
248 MVE_VRMULH,
249 MVE_VNEG_FP,
250 MVE_VNEG_VEC,
14b456f2
AV		 251 MVE_VPNOT,
252 MVE_VPSEL,
253 MVE_VQABS,
254 MVE_VQADD_T1,
255 MVE_VQADD_T2,
256 MVE_VQSUB_T1,
257 MVE_VQSUB_T2,
258 MVE_VQNEG,
259 MVE_VREV16,
260 MVE_VREV32,
261 MVE_VREV64,
23d00a41
SD		 262 MVE_LSLL,
263 MVE_LSLLI,
264 MVE_LSRL,
265 MVE_ASRL,
266 MVE_ASRLI,
267 MVE_SQRSHRL,
268 MVE_SQRSHR,
269 MVE_UQRSHL,
270 MVE_UQRSHLL,
271 MVE_UQSHL,
272 MVE_UQSHLL,
273 MVE_URSHRL,
274 MVE_URSHR,
275 MVE_SRSHRL,
276 MVE_SRSHR,
277 MVE_SQSHLL,
278 MVE_SQSHL,
e39c1607
SD		 279 MVE_CINC,
280 MVE_CINV,
281 MVE_CNEG,
282 MVE_CSINC,
283 MVE_CSINV,
284 MVE_CSET,
285 MVE_CSETM,
286 MVE_CSNEG,
287 MVE_CSEL,
73cd51e5
AV		 288 MVE_NONE
289};
290
291enum mve_unpredictable
292{
293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
294 */
143275ea
AV		 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
296 fcB = 1 (vpt). */
297 UNPRED_R13, /* Unpredictable because r13 (sp) or
298 r15 (sp) used. */
9743db03 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 300 UNPRED_Q_GT_4, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
305 and WB bit = 1. */
ef1576a1
AV		 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
307 equal. */
308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
310 same. */
c507f10b
AV		 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
312 size = 1. */
313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
314 size = 2. */
73cd51e5
AV		 315 UNPRED_NONE /* No unpredictable behavior. */
316};
317
318enum mve_undefined
319{
ed63aa17 320 UNDEF_SIZE, /* undefined size. */
bf0b396d 321 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 322 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 323 UNDEF_SIZE_3, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
329 size == 0. */
330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
331 size == 1. */
332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
336 op1 == (0 or 1). */
337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
340 in {0xx1, x0x1}. */
d3b63143 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 342 UNDEF_NONE /* no undefined behavior. */
343};
344
6b5d3a4d
ZW		 345struct opcode32
346{
823d2571
TG		 347 arm_feature_set arch; /* Architecture defining this insn. */
348 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 350 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 351};
352
4934a27c
MM		 353struct cdeopcode32
354{
355 arm_feature_set arch; /* Architecture defining this insn. */
356 uint8_t coproc_shift; /* coproc is this far into op. */
357 uint16_t coproc_mask; /* Length of coproc field in op. */
358 unsigned long value; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask; /* Recognise insn if (op & mask) == value. */
360 const char * assembler; /* How to disassemble this insn. */
361};
362
73cd51e5
AV		 363/* MVE opcodes. */
364
365struct mopcode32
366{
367 arm_feature_set arch; /* Architecture defining this insn. */
368 enum mve_instructions mve_op; /* Specific mve instruction for faster
369 decoding. */
370 unsigned long value; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask; /* Recognise insn if (op & mask) == value. */
372 const char * assembler; /* How to disassemble this insn. */
373};
374
6b0dd094
AV		 375enum isa {
376 ANY,
377 T32,
378 ARM
379};
380
381
382/* Shared (between Arm and Thumb mode) opcode. */
383struct sopcode32
384{
385 enum isa isa; /* Execution mode instruction availability. */
386 arm_feature_set arch; /* Architecture defining this insn. */
387 unsigned long value; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask; /* Recognise insn if (op & mask) == value. */
389 const char * assembler; /* How to disassemble this insn. */
390};
391
6b5d3a4d
ZW		 392struct opcode16
393{
823d2571 394 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 396 const char *assembler; /* How to disassemble this insn. */
397};
b7693d02 398
8f06b2d8 399/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 400
2fbad815 401 %% %
4a5329c6 402
c22aaad1 403 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 404 %b print condition code allowing cp_num == 9
37b37b2d 405 %q print shifter argument
e2efe87d
MGD		 406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
4a5329c6 408 %A print address for ldc/stc/ldf/stf instruction
16980d0b 409 %B print vstm/vldm register list
efd6b359 410 %C print vscclrm register list
4a5329c6 411 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
4a5329c6
ZW		 414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
418
33399f07 419 %<bitfield>c print as a condition code (for vsel)
4a5329c6 420 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 423 %<bitfield>d print the bitfield in decimal
16980d0b 424 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
4a5329c6
ZW		 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
c28eeff2 434 %<bitfield>V print as a NEON D or Q register
6f1c2142 435 %<bitfield>E print a quarter-float immediate value
4a5329c6 436
16980d0b 437 %y<code> print a single precision VFP reg.
2fbad815 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 439 %z<code> print a double precision VFP reg
2fbad815 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 441
16980d0b
JB		 442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
43e65147 445
2fbad815 446 %L print as an iWMMXt N/M width field.
4a5329c6 447 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 448 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 449 versions.
450 %i print 5-bit immediate in bits 8,3..0
451 (print "32" when 0)
fe56b6ce 452 %r print register offset address for wldt/wstr instruction. */
2fbad815 453
21d799b5 454enum opcode_sentinel_enum
05413229
NC		 455{
456 SENTINEL_IWMMXT_START = 1,
457 SENTINEL_IWMMXT_END,
458 SENTINEL_GENERIC_START
459} opcode_sentinels;
460
8cb6e175
AB		 461#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
462#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
463#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
464#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
05413229 465
8f06b2d8 466/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 467
4934a27c
MM		 468/* print_insn_cde recognizes the following format control codes:
469
470 %% %
471
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
483
484/* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488static const struct cdeopcode32 cde_opcodes[] =
489{
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492 0xee000000, 0xefc00840,
6576bffe 493 "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495 0xee000040, 0xefc00840,
6576bffe 496 "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 497
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499 0xee400000, 0xefc00840,
6576bffe 500 "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502 0xee400040, 0xefc00840,
6576bffe 503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 504
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506 0xee800000, 0xef800840,
6576bffe 507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c
MM		 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509 0xee800040, 0xef800840,
6576bffe 510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c 511
5aae9ae9
MM		 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513 0xec200000, 0xeeb00840,
6576bffe 514 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
5aae9ae9
MM		 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516 0xec200040, 0xeeb00840,
6576bffe 517 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
5aae9ae9
MM		 518
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520 0xec300000, 0xeeb00840,
6576bffe 521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
5aae9ae9
MM		 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523 0xec300040, 0xeeb00840,
6576bffe 524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
5aae9ae9
MM		 525
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527 0xec800000, 0xee800840,
6576bffe 528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
5aae9ae9
MM		 529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530 0xec800040, 0xee800840,
6576bffe 531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
5aae9ae9 532
4934a27c
MM		 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535};
536
6b0dd094 537static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 538{
2fbad815 539 /* XScale instructions. */
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 541 0x0e200010, 0x0fff0ff0,
6576bffe 542 "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e280010, 0x0fff0ff0,
6576bffe 545 "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 549 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
05413229 552
2fbad815 553 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 707 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 708 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 709
fe56b6ce 710 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 797
efd6b359
AV		 798 /* Armv8.1-M Mainline instructions. */
799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
16a1fa25 804 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
fe56b6ce 810 /* Register load/store. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 847
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
16980d0b 856
fe56b6ce 857 /* Data transfer between ARM and NEON registers. */
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
8e79c3df 874 /* Half-precision conversion instructions. */
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 883
fe56b6ce 884 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
2da2eaf4 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
ba6cd17f 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 890 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
2da2eaf4 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
2da2eaf4 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
ba6cd17f 907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 908 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
ba6cd17f 909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 910 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
2da2eaf4 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
ba6cd17f 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
2da2eaf4 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
2da2eaf4 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
ba6cd17f 935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
ba6cd17f 937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815 1043
62f3b8c8 1044 /* VFP Fused multiply add instructions. */
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1046 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1048 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1050 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1052 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1054 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1056 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1058 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1060 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1061
33399f07 1062 /* FP v5. */
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1064 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1066 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1068 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1070 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1072 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1074 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1076 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1078 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1080 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1082 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1084 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1086 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1087
6b0dd094 1088 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1089 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1090 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1091 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 1092 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1093 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 1094 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1095 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1096 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1097 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1098 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1099 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1100 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1101 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1102 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1103 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
6b0dd094 1104 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1105 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
6b0dd094 1106 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1107 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
6b0dd094 1108 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1109 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
c28eeff2 1110
aab2c27d
MM		 1111 /* BFloat16 instructions. */
1112 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1113 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1114
c604a79a 1115 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1117 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
6576bffe 1119 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
c604a79a 1120
dec41383 1121 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1122 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1123 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1124 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1125 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1126 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1127 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1128 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1129 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1130 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1131 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1132 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1133 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1134 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1135 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
6b0dd094 1136 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1137 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
dec41383 1138
b0c11777
RL		 1139 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1140 cp_num: bit <11:8> == 0b1001.
1141 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1142 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1143 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1144 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1145 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1146 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1147 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1148 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1149 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
6b0dd094 1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1151 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1152 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1153 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1155 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1157 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1158 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1159 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1161 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1163 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1165 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1167 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1169 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1171 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1173 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1175 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1176 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1177 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1178 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1179 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1181 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1183 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1185 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1187 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1189 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1191 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1193 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1195 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1197 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1199 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1201 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1203 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1205 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1207 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1209 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1211 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1212
49e8a725 1213 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1215 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1216
6b0dd094 1217 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1218};
1219
33593eaf
MM		 1220/* Generic coprocessor instructions. These are only matched if a more specific
1221 SIMD or co-processor instruction does not match first. */
1222
1223static const struct sopcode32 generic_coprocessor_opcodes[] =
1224{
1225 /* Generic coprocessor instructions. */
1226 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
6576bffe 1227 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
33593eaf
MM		 1228 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1229 0x0c500000, 0x0ff00000,
6576bffe 1230 "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1231 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1232 0x0e000000, 0x0f000010,
6576bffe 1233 "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1234 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1235 0x0e10f010, 0x0f10f010,
6576bffe 1236 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1237 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1238 0x0e100010, 0x0f100010,
6576bffe 1239 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1240 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1241 0x0e000010, 0x0f100010,
6576bffe 1242 "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf 1243 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1244 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1245 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1246 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1247
1248 /* V6 coprocessor instructions. */
1249 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1250 0xfc500000, 0xfff00000,
6576bffe 1251 "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1252 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1253 0xfc400000, 0xfff00000,
6576bffe 1254 "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
33593eaf
MM		 1255
1256 /* V5 coprocessor instructions. */
1257 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1258 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1259 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1260 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1261 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1262 0xfe000000, 0xff000010,
6576bffe 1263 "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1264 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1265 0xfe000010, 0xff100010,
6576bffe 1266 "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1267 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1268 0xfe100010, 0xff100010,
6576bffe 1269 "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1270
1271 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1272};
1273
16980d0b
JB		 1274/* Neon opcode table: This does not encode the top byte -- that is
1275 checked by the print_insn_neon routine, as it depends on whether we are
1276 doing thumb32 or arm32 disassembly. */
1277
1278/* print_insn_neon recognizes the following format control codes:
1279
1280 %% %
1281
c22aaad1 1282 %c print condition code
e2efe87d
MGD		 1283 %u print condition code (unconditional in ARM mode,
1284 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1285 %A print v{st,ld}[1234] operands
1286 %B print v{st,ld}[1234] any one operands
1287 %C print v{st,ld}[1234] single->all operands
1288 %D print scalar
1289 %E print vmov, vmvn, vorr, vbic encoded constant
1290 %F print vtbl,vtbx register list
1291
1292 %<bitfield>r print as an ARM register
1293 %<bitfield>d print the bitfield in decimal
1294 %<bitfield>e print the 2^N - bitfield in decimal
1295 %<bitfield>D print as a NEON D register
1296 %<bitfield>Q print as a NEON Q register
1297 %<bitfield>R print as a NEON D or Q register
1298 %<bitfield>Sn print byte scaled width limited by n
1299 %<bitfield>Tn print short scaled width limited by n
1300 %<bitfield>Un print long scaled width limited by n
43e65147 1301
16980d0b
JB		 1302 %<bitfield>'c print specified char iff bitfield is all ones
1303 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1304 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1305
1306static const struct opcode32 neon_opcodes[] =
1307{
fe56b6ce 1308 /* Extract. */
823d2571
TG		 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2b00840, 0xffb00850,
6576bffe 1311 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
823d2571
TG		 1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313 0xf2b00000, 0xffb00810,
6576bffe 1314 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
16980d0b 1315
9743db03
AV		 1316 /* Data transfer between ARM and NEON registers. */
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1318 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1320 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1322 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1324 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1326 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1328 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1329
fe56b6ce 1330 /* Move data element to all lanes. */
823d2571 1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1332 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
823d2571 1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1334 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
823d2571 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1336 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
16980d0b 1337
fe56b6ce 1338 /* Table lookup. */
823d2571
TG		 1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1343
8e79c3df 1344 /* Half-precision conversions. */
823d2571
TG		 1345 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1346 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1347 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1348 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1349
1350 /* NEON fused multiply add instructions. */
823d2571 1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1352 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1354 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1356 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1358 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1359
aab2c27d
MM		 1360 /* BFloat16 instructions. */
1361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1362 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1364 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
aab2c27d
MM		 1365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1366 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1368 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1369 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1370 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1372 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
aab2c27d 1373
616ce08e
MM		 1374 /* Matrix Multiply instructions. */
1375 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1376 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1378 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1380 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1382 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1384 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1386 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1387
fe56b6ce 1388 /* Two registers, miscellaneous. */
823d2571
TG		 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1390 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1392 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1394 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1396 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1397 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1398 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1399 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1400 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1401 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1402 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1403 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1404 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1405 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1406 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1407 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1408 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1409 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1410 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3b20300, 0xffb30fd0,
6576bffe 1433 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
823d2571
TG		 1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1436 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1437 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1441 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1463 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1465 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1467 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1469 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1471 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571
TG		 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1481 0xf3bb0600, 0xffbf0e10,
823d2571 1482 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1484 0xf3b70600, 0xffbf0e10,
1485 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1486
fe56b6ce 1487 /* Three registers of the same length. */
823d2571
TG		 1488 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1489 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1490 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1491 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1492 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1493 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1494 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1495 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1496 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1497 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1498 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1499 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1500 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1501 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1503 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1505 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1507 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1509 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1527 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1529 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1531 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1535 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1539 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1543 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1547 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1549 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1551 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1553 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1555 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1557 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1559 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1561 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1563 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1565 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1567 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1569 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1571 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1573 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1575 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1577 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1579 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1581 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1583 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1585 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1587 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1589 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1591 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1593 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1595 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1597 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf2000b00, 0xff800f10,
1606 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2000b10, 0xff800f10,
1609 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3000b00, 0xff800f10,
1618 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2000000, 0xfe800f10,
1621 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf2000010, 0xfe800f10,
1624 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2000100, 0xfe800f10,
1627 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf2000200, 0xfe800f10,
1630 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf2000210, 0xfe800f10,
1633 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf2000300, 0xfe800f10,
1636 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2000310, 0xfe800f10,
1639 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf2000400, 0xfe800f10,
1642 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2000410, 0xfe800f10,
1645 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf2000500, 0xfe800f10,
1648 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2000510, 0xfe800f10,
1651 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf2000600, 0xfe800f10,
1654 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2000610, 0xfe800f10,
1657 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf2000700, 0xfe800f10,
1660 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2000710, 0xfe800f10,
1663 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2000910, 0xfe800f10,
1666 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2000a00, 0xfe800f10,
1669 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2000a10, 0xfe800f10,
1672 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1674 0xf3000b10, 0xff800f10,
1675 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1677 0xf3000c10, 0xff800f10,
1678 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1679
fe56b6ce 1680 /* One register and an immediate value. */
823d2571
TG		 1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1707
fe56b6ce 1708 /* Two registers and a shift amount. */
823d2571 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1710 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1712 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1714 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1716 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1718 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571
TG		 1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf2880950, 0xfeb80fd0,
6576bffe 1721 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1723 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
823d2571 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1725 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1727 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1729 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1731 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1733 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1735 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1737 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1739 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1741 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571
TG		 1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2900950, 0xfeb00fd0,
6576bffe 1744 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1746 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
823d2571 1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1748 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1750 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1752 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1754 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1756 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1758 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1759 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1760 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1762 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1764 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1766 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1768 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1770 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
823d2571 1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1772 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1774 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1776 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1778 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1780 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1782 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1784 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1786 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571
TG		 1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2a00950, 0xfea00fd0,
6576bffe 1789 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1791 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1793 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1795 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1797 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1799 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1801 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1803 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1805 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1807 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1809 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1811 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1813 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1815 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1817 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1819 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1821 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1823 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1825 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571
TG		 1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2a00e10, 0xfea00e90,
6576bffe 1828 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
cc933301
JW		 1829 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1830 0xf2a00c10, 0xfea00e90,
6576bffe 1831 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
16980d0b 1832
fe56b6ce 1833 /* Three registers of different lengths. */
823d2571
TG		 1834 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1835 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2800400, 0xff800f50,
1840 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2800600, 0xff800f50,
1843 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2800900, 0xff800f50,
1846 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2800b00, 0xff800f50,
1849 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf2800d00, 0xff800f50,
1852 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3800400, 0xff800f50,
1855 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1857 0xf3800600, 0xff800f50,
1858 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800000, 0xfe800f50,
1861 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf2800100, 0xfe800f50,
1864 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2800200, 0xfe800f50,
1867 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf2800300, 0xfe800f50,
1870 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2800500, 0xfe800f50,
1873 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875 0xf2800700, 0xfe800f50,
1876 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800800, 0xfe800f50,
1879 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2800a00, 0xfe800f50,
1882 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800c00, 0xfe800f50,
1885 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1886
fe56b6ce 1887 /* Two registers and a scalar. */
823d2571
TG		 1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1891 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1892 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1893 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1899 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1900 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1901 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1907 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1908 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1909 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1919 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1920 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1921 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1925 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1926 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1927 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1931 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1932 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1933 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf2800240, 0xfe800f50,
1940 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf2800640, 0xfe800f50,
1943 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf2800a40, 0xfe800f50,
1946 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1948 0xf2800e40, 0xff800f50,
1949 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1951 0xf2800f40, 0xff800f50,
1952 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1954 0xf3800e40, 0xff800f50,
1955 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1957 0xf3800f40, 0xff800f50,
1958 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1959 },
16980d0b 1960
fe56b6ce 1961 /* Element and structure load/store. */
823d2571
TG		 1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2000
2001 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2002};
2003
73cd51e5
AV		 2004/* mve opcode table. */
2005
2006/* print_insn_mve recognizes the following format control codes:
2007
2008 %% %
2009
ef1576a1
AV		 2010 %a print '+' or '-' or imm offset in vldr[bhwd] and
2011 vstr[bhwd]
9743db03 2012 %c print condition code
aef6d006
AV		 2013 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2014 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2015 %i print MVE predicate(s) for vpt and vpst
23d00a41 2016 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2017 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2018 %m print rounding mode for vcvt and vrint
143275ea 2019 %n print vector comparison code for predicated instruction
bf0b396d 2020 %s print size for various vcvt instructions
143275ea
AV		 2021 %v print vector predicate for instruction in predicated
2022 block
ef1576a1 2023 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2024 %w print writeback mode for MVE v{st,ld}[24]
2025 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2026 %E print vmov, vmvn, vorr, vbic encoded constant
2027 %N print generic index for vmov
14925797 2028 %T print bottom ('b') or top ('t') of source register
d3b63143 2029 %X print exchange field in vmla* instructions
04d54ace 2030
9743db03 2031 %<bitfield>r print as an ARM register
04d54ace 2032 %<bitfield>d print the bitfield in decimal
d3b63143 2033 %<bitfield>A print accumulate or not
e39c1607
SD		 2034 %<bitfield>c print bitfield as a condition code
2035 %<bitfield>C print bitfield as an inverted condition code
143275ea 2036 %<bitfield>Q print as a MVE Q register
c507f10b 2037 %<bitfield>F print as a MVE S register
143275ea
AV		 2038 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2039 UNPREDICTABLE
23d00a41
SD		 2040
2041 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2042 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2043 %<bitfield>I print carry flag or not
ef1576a1 2044 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2045 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2046 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2047 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2048 %<bitfield>o print rotate value for vcmul
1c8f2df8 2049 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2050 %<bitfield>x print the bitfield in hex.
1c8f2df8 2051 */
73cd51e5
AV		 2052
2053static const struct mopcode32 mve_opcodes[] =
2054{
143275ea
AV		 2055 /* MVE. */
2056
2da2eaf4 2057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2058 MVE_VPST,
2059 0xfe310f4d, 0xffbf1fff,
2060 "vpst%i"
2061 },
2062
2063 /* Floating point VPT T1. */
2da2eaf4 2064 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2065 MVE_VPT_FP_T1,
2066 0xee310f00, 0xefb10f50,
2067 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2068 /* Floating point VPT T2. */
2da2eaf4 2069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2070 MVE_VPT_FP_T2,
2071 0xee310f40, 0xefb10f50,
2072 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2073
2074 /* Vector VPT T1. */
2da2eaf4 2075 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2076 MVE_VPT_VEC_T1,
2077 0xfe010f00, 0xff811f51,
2078 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2079 /* Vector VPT T2. */
2da2eaf4 2080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2081 MVE_VPT_VEC_T2,
2082 0xfe010f01, 0xff811f51,
2083 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2084 /* Vector VPT T3. */
2da2eaf4 2085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2086 MVE_VPT_VEC_T3,
2087 0xfe011f00, 0xff811f50,
2088 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2089 /* Vector VPT T4. */
2da2eaf4 2090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2091 MVE_VPT_VEC_T4,
2092 0xfe010f40, 0xff811f70,
2093 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2094 /* Vector VPT T5. */
2da2eaf4 2095 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2096 MVE_VPT_VEC_T5,
2097 0xfe010f60, 0xff811f70,
2098 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2099 /* Vector VPT T6. */
2da2eaf4 2100 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2101 MVE_VPT_VEC_T6,
2102 0xfe011f40, 0xff811f50,
2103 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2104
c507f10b 2105 /* Vector VBIC immediate. */
2da2eaf4 2106 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2107 MVE_VBIC_IMM,
2108 0xef800070, 0xefb81070,
2109 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2110
2111 /* Vector VBIC register. */
2da2eaf4 2112 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2113 MVE_VBIC_REG,
2114 0xef100150, 0xffb11f51,
2115 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2116
66dcaa5d 2117 /* Vector VABAV. */
2da2eaf4 2118 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2119 MVE_VABAV,
2120 0xee800f01, 0xefc10f51,
2121 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2122
2123 /* Vector VABD floating point. */
2da2eaf4 2124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2125 MVE_VABD_FP,
2126 0xff200d40, 0xffa11f51,
2127 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2128
2129 /* Vector VABD. */
2da2eaf4 2130 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2131 MVE_VABD_VEC,
2132 0xef000740, 0xef811f51,
2133 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2134
2135 /* Vector VABS floating point. */
2da2eaf4 2136 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2137 MVE_VABS_FP,
2138 0xFFB10740, 0xFFB31FD1,
2139 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2140 /* Vector VABS. */
2da2eaf4 2141 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2142 MVE_VABS_VEC,
2143 0xffb10340, 0xffb31fd1,
2144 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2145
2146 /* Vector VADD floating point T1. */
2da2eaf4 2147 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2148 MVE_VADD_FP_T1,
2149 0xef000d40, 0xffa11f51,
2150 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2151 /* Vector VADD floating point T2. */
2da2eaf4 2152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2153 MVE_VADD_FP_T2,
2154 0xee300f40, 0xefb11f70,
2155 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2156 /* Vector VADD T1. */
2da2eaf4 2157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2158 MVE_VADD_VEC_T1,
2159 0xef000840, 0xff811f51,
2160 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2161 /* Vector VADD T2. */
2da2eaf4 2162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2163 MVE_VADD_VEC_T2,
2164 0xee010f40, 0xff811f70,
2165 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2166
d3b63143 2167 /* Vector VADDLV. */
2da2eaf4 2168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2169 MVE_VADDLV,
2170 0xee890f00, 0xef8f1fd1,
2171 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2172
2173 /* Vector VADDV. */
2da2eaf4 2174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2175 MVE_VADDV,
2176 0xeef10f00, 0xeff31fd1,
2177 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2178
66dcaa5d 2179 /* Vector VADC. */
2da2eaf4 2180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2181 MVE_VADC,
2182 0xee300f00, 0xffb10f51,
2183 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2184
e523f101 2185 /* Vector VAND. */
2da2eaf4 2186 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2187 MVE_VAND,
2188 0xef000150, 0xffb11f51,
2189 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2190
2191 /* Vector VBRSR register. */
2da2eaf4 2192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2193 MVE_VBRSR,
2194 0xfe011e60, 0xff811f70,
2195 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2196
897b9bbc 2197 /* Vector VCADD floating point. */
2da2eaf4 2198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2199 MVE_VCADD_FP,
2200 0xfc800840, 0xfea11f51,
6576bffe 2201 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
897b9bbc
AV		 2202
2203 /* Vector VCADD. */
2da2eaf4 2204 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2205 MVE_VCADD_VEC,
2206 0xfe000f00, 0xff810f51,
6576bffe 2207 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2208
e523f101 2209 /* Vector VCLS. */
2da2eaf4 2210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2211 MVE_VCLS,
2212 0xffb00440, 0xffb31fd1,
2213 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2214
2215 /* Vector VCLZ. */
2da2eaf4 2216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2217 MVE_VCLZ,
2218 0xffb004c0, 0xffb31fd1,
2219 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2220
897b9bbc 2221 /* Vector VCMLA. */
2da2eaf4 2222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2223 MVE_VCMLA_FP,
2224 0xfc200840, 0xfe211f51,
6576bffe 2225 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
897b9bbc 2226
143275ea 2227 /* Vector VCMP floating point T1. */
2da2eaf4 2228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2229 MVE_VCMP_FP_T1,
2230 0xee310f00, 0xeff1ef50,
2231 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2232
2233 /* Vector VCMP floating point T2. */
2da2eaf4 2234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2235 MVE_VCMP_FP_T2,
2236 0xee310f40, 0xeff1ef50,
2237 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2238
2239 /* Vector VCMP T1. */
2da2eaf4 2240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2241 MVE_VCMP_VEC_T1,
2242 0xfe010f00, 0xffc1ff51,
2243 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2244 /* Vector VCMP T2. */
2da2eaf4 2245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2246 MVE_VCMP_VEC_T2,
2247 0xfe010f01, 0xffc1ff51,
2248 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2249 /* Vector VCMP T3. */
2da2eaf4 2250 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2251 MVE_VCMP_VEC_T3,
2252 0xfe011f00, 0xffc1ff50,
2253 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2254 /* Vector VCMP T4. */
2da2eaf4 2255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2256 MVE_VCMP_VEC_T4,
2257 0xfe010f40, 0xffc1ff70,
2258 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2259 /* Vector VCMP T5. */
2da2eaf4 2260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2261 MVE_VCMP_VEC_T5,
2262 0xfe010f60, 0xffc1ff70,
2263 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2264 /* Vector VCMP T6. */
2da2eaf4 2265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2266 MVE_VCMP_VEC_T6,
2267 0xfe011f40, 0xffc1ff50,
2268 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2269
9743db03 2270 /* Vector VDUP. */
2da2eaf4 2271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2272 MVE_VDUP,
2273 0xeea00b10, 0xffb10f5f,
2274 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2275
2276 /* Vector VEOR. */
2da2eaf4 2277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2278 MVE_VEOR,
2279 0xff000150, 0xffd11f51,
2280 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2281
2282 /* Vector VFMA, vector * scalar. */
2da2eaf4 2283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2284 MVE_VFMA_FP_SCALAR,
2285 0xee310e40, 0xefb11f70,
2286 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2287
2288 /* Vector VFMA floating point. */
2da2eaf4 2289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2290 MVE_VFMA_FP,
2291 0xef000c50, 0xffa11f51,
2292 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2293
2294 /* Vector VFMS floating point. */
2da2eaf4 2295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2296 MVE_VFMS_FP,
2297 0xef200c50, 0xffa11f51,
2298 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2299
2300 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2302 MVE_VFMAS_FP_SCALAR,
2303 0xee311e40, 0xefb11f70,
2304 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2305
2306 /* Vector VHADD T1. */
2da2eaf4 2307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2308 MVE_VHADD_T1,
2309 0xef000040, 0xef811f51,
2310 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2311
2312 /* Vector VHADD T2. */
2da2eaf4 2313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2314 MVE_VHADD_T2,
2315 0xee000f40, 0xef811f70,
2316 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2317
2318 /* Vector VHSUB T1. */
2da2eaf4 2319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2320 MVE_VHSUB_T1,
2321 0xef000240, 0xef811f51,
2322 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2323
2324 /* Vector VHSUB T2. */
2da2eaf4 2325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2326 MVE_VHSUB_T2,
2327 0xee001f40, 0xef811f70,
2328 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2329
897b9bbc 2330 /* Vector VCMUL. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2332 MVE_VCMUL_FP,
2333 0xee300e00, 0xefb10f50,
6576bffe 2334 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
897b9bbc 2335
e523f101 2336 /* Vector VCTP. */
2da2eaf4 2337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2338 MVE_VCTP,
2339 0xf000e801, 0xffc0ffff,
2340 "vctp%v.%20-21s\t%16-19r"},
2341
9743db03 2342 /* Vector VDUP. */
2da2eaf4 2343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2344 MVE_VDUP,
2345 0xeea00b10, 0xffb10f5f,
2346 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2347
2348 /* Vector VRHADD. */
2da2eaf4 2349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2350 MVE_VRHADD,
2351 0xef000140, 0xef811f51,
2352 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2353
bf0b396d 2354 /* Vector VCVT. */
2da2eaf4 2355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2356 MVE_VCVT_FP_FIX_VEC,
2357 0xef800c50, 0xef801cd1,
6576bffe 2358 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
bf0b396d
AV		 2359
2360 /* Vector VCVT. */
2da2eaf4 2361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2362 MVE_VCVT_BETWEEN_FP_INT,
2363 0xffb30640, 0xffb31e51,
2364 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2365
2366 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2368 MVE_VCVT_FP_HALF_FP,
2369 0xee3f0e01, 0xefbf1fd1,
2370 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2371
2372 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2374 MVE_VCVT_FP_HALF_FP,
2375 0xee3f1e01, 0xefbf1fd1,
2376 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2377
2378 /* Vector VCVT. */
2da2eaf4 2379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2380 MVE_VCVT_FROM_FP_TO_INT,
2381 0xffb30040, 0xffb31c51,
2382 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2383
1c8f2df8 2384 /* Vector VDDUP. */
2da2eaf4 2385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2386 MVE_VDDUP,
2387 0xee011f6e, 0xff811f7e,
6576bffe 2388 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8
AV		 2389
2390 /* Vector VDWDUP. */
2da2eaf4 2391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2392 MVE_VDWDUP,
2393 0xee011f60, 0xff811f70,
6576bffe 2394 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8 2395
897b9bbc 2396 /* Vector VHCADD. */
2da2eaf4 2397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2398 MVE_VHCADD,
2399 0xee000f00, 0xff810f51,
6576bffe 2400 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2401
1c8f2df8 2402 /* Vector VIWDUP. */
2da2eaf4 2403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2404 MVE_VIWDUP,
2405 0xee010f60, 0xff811f70,
6576bffe 2406 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8
AV		 2407
2408 /* Vector VIDUP. */
2da2eaf4 2409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2410 MVE_VIDUP,
2411 0xee010f6e, 0xff811f7e,
6576bffe 2412 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8 2413
04d54ace 2414 /* Vector VLD2. */
2da2eaf4 2415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2416 MVE_VLD2,
2417 0xfc901e00, 0xff901e5f,
2418 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2419
2420 /* Vector VLD4. */
2da2eaf4 2421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2422 MVE_VLD4,
2423 0xfc901e01, 0xff901e1f,
2424 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2425
ef1576a1 2426 /* Vector VLDRB gather load. */
2da2eaf4 2427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2428 MVE_VLDRB_GATHER_T1,
2429 0xec900e00, 0xefb01e50,
2430 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2431
2432 /* Vector VLDRH gather load. */
2da2eaf4 2433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2434 MVE_VLDRH_GATHER_T2,
2435 0xec900e10, 0xefb01e50,
2436 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2437
2438 /* Vector VLDRW gather load. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2440 MVE_VLDRW_GATHER_T3,
2441 0xfc900f40, 0xffb01fd0,
2442 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2443
2444 /* Vector VLDRD gather load. */
2da2eaf4 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2446 MVE_VLDRD_GATHER_T4,
2447 0xec900fd0, 0xefb01fd0,
2448 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2449
2450 /* Vector VLDRW gather load. */
2da2eaf4 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2452 MVE_VLDRW_GATHER_T5,
2453 0xfd101e00, 0xff111f00,
6576bffe 2454 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 2455
2456 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2458 MVE_VLDRD_GATHER_T6,
2459 0xfd101f00, 0xff111f00,
6576bffe 2460 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 2461
aef6d006 2462 /* Vector VLDRB. */
2da2eaf4 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2464 MVE_VLDRB_T1,
2465 0xec100e00, 0xee581e00,
2466 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2467
2468 /* Vector VLDRH. */
2da2eaf4 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2470 MVE_VLDRH_T2,
2471 0xec180e00, 0xee581e00,
2472 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2473
2474 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2476 MVE_VLDRB_T5,
2477 0xec101e00, 0xfe101f80,
2478 "vldrb%v.u8\t%13-15,22Q, %d"},
2479
2480 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2482 MVE_VLDRH_T6,
2483 0xec101e80, 0xfe101f80,
2484 "vldrh%v.u16\t%13-15,22Q, %d"},
2485
2486 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2488 MVE_VLDRW_T7,
2489 0xec101f00, 0xfe101f80,
2490 "vldrw%v.u32\t%13-15,22Q, %d"},
2491
56858bea 2492 /* Vector VMAX. */
2da2eaf4 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2494 MVE_VMAX,
2495 0xef000640, 0xef811f51,
2496 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498 /* Vector VMAXA. */
2da2eaf4 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2500 MVE_VMAXA,
2501 0xee330e81, 0xffb31fd1,
2502 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2503
2504 /* Vector VMAXNM floating point. */
2da2eaf4 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2506 MVE_VMAXNM_FP,
2507 0xff000f50, 0xffa11f51,
2508 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2509
2510 /* Vector VMAXNMA floating point. */
2da2eaf4 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2512 MVE_VMAXNMA_FP,
2513 0xee3f0e81, 0xefbf1fd1,
2514 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2515
2516 /* Vector VMAXNMV floating point. */
2da2eaf4 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2518 MVE_VMAXNMV_FP,
2519 0xeeee0f00, 0xefff0fd1,
2520 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2521
2522 /* Vector VMAXNMAV floating point. */
2da2eaf4 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2524 MVE_VMAXNMAV_FP,
2525 0xeeec0f00, 0xefff0fd1,
2526 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2527
2528 /* Vector VMAXV. */
2da2eaf4 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2530 MVE_VMAXV,
2531 0xeee20f00, 0xeff30fd1,
2532 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2533
2534 /* Vector VMAXAV. */
2da2eaf4 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2536 MVE_VMAXAV,
2537 0xeee00f00, 0xfff30fd1,
2538 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2539
2540 /* Vector VMIN. */
2da2eaf4 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2542 MVE_VMIN,
2543 0xef000650, 0xef811f51,
2544 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2545
2546 /* Vector VMINA. */
2da2eaf4 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2548 MVE_VMINA,
2549 0xee331e81, 0xffb31fd1,
2550 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2551
2552 /* Vector VMINNM floating point. */
2da2eaf4 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2554 MVE_VMINNM_FP,
2555 0xff200f50, 0xffa11f51,
2556 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2557
2558 /* Vector VMINNMA floating point. */
2da2eaf4 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2560 MVE_VMINNMA_FP,
2561 0xee3f1e81, 0xefbf1fd1,
2562 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2563
2564 /* Vector VMINNMV floating point. */
2da2eaf4 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2566 MVE_VMINNMV_FP,
2567 0xeeee0f80, 0xefff0fd1,
2568 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2569
2570 /* Vector VMINNMAV floating point. */
2da2eaf4 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2572 MVE_VMINNMAV_FP,
2573 0xeeec0f80, 0xefff0fd1,
2574 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2575
2576 /* Vector VMINV. */
2da2eaf4 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2578 MVE_VMINV,
2579 0xeee20f80, 0xeff30fd1,
2580 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2581
2582 /* Vector VMINAV. */
2da2eaf4 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2584 MVE_VMINAV,
2585 0xeee00f80, 0xfff30fd1,
2586 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2587
2588 /* Vector VMLA. */
2da2eaf4 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2590 MVE_VMLA,
2591 0xee010e40, 0xef811f70,
3e562e4b 2592 "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
56858bea 2593
d3b63143
AV		 2594 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2595 opcode aliasing. */
2da2eaf4 2596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2597 MVE_VMLALDAV,
2598 0xee801e00, 0xef801f51,
2599 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2600
2da2eaf4 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2602 MVE_VMLALDAV,
2603 0xee800e00, 0xef801f51,
2604 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2605
2606 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2608 MVE_VMLADAV_T1,
2609 0xeef00e00, 0xeff01f51,
2610 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2611
2612 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2614 MVE_VMLADAV_T2,
2615 0xeef00f00, 0xeff11f51,
2616 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2617
2618 /* Vector VMLADAV T1 variant. */
2da2eaf4 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2620 MVE_VMLADAV_T1,
2621 0xeef01e00, 0xeff01f51,
2622 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2623
2624 /* Vector VMLADAV T2 variant. */
2da2eaf4 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2626 MVE_VMLADAV_T2,
2627 0xeef01f00, 0xeff11f51,
2628 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2629
2630 /* Vector VMLAS. */
2da2eaf4 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2632 MVE_VMLAS,
2633 0xee011e40, 0xef811f70,
2634 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2635
2636 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2637 opcode aliasing. */
2da2eaf4 2638 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2639 MVE_VRMLSLDAVH,
2640 0xfe800e01, 0xff810f51,
2641 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2642
2643 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2644 opcdoe aliasing. */
2da2eaf4 2645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2646 MVE_VMLSLDAV,
2647 0xee800e01, 0xff800f51,
2648 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2649
2650 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2652 MVE_VMLSDAV_T1,
2653 0xeef00e01, 0xfff00f51,
2654 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2655
2656 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2658 MVE_VMLSDAV_T2,
2659 0xfef00e01, 0xfff10f51,
2660 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2661
c507f10b 2662 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2664 MVE_VMOV_HFP_TO_GP,
2665 0xee000910, 0xfff00f7f,
2666 "vmov.f16\t%7,16-19F, %12-15r"},
2667
2668 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2670 MVE_VMOV_HFP_TO_GP,
2671 0xee100910, 0xfff00f7f,
2672 "vmov.f16\t%12-15r, %7,16-19F"},
2673
2da2eaf4 2674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2675 MVE_VMOV_GP_TO_VEC_LANE,
2676 0xee000b10, 0xff900f1f,
6576bffe 2677 "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
c507f10b
AV		 2678
2679 /* Vector VORR immediate to vector.
2680 NOTE: MVE_VORR_IMM must appear in the table
2681 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2683 MVE_VORR_IMM,
2684 0xef800050, 0xefb810f0,
2685 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2686
ed63aa17
AV		 2687 /* Vector VQSHL T2 Variant.
2688 NOTE: MVE_VQSHL_T2 must appear in the table before
2689 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2691 MVE_VQSHL_T2,
2692 0xef800750, 0xef801fd1,
6576bffe 2693 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2694
2695 /* Vector VQSHLU T3 Variant
2696 NOTE: MVE_VQSHL_T2 must appear in the table before
2697 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2698
2da2eaf4 2699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2700 MVE_VQSHLU_T3,
2701 0xff800650, 0xff801fd1,
6576bffe 2702 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2703
2704 /* Vector VRSHR
2705 NOTE: MVE_VRSHR must appear in the table before
2706 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2708 MVE_VRSHR,
2709 0xef800250, 0xef801fd1,
6576bffe 2710 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2711
2712 /* Vector VSHL.
2713 NOTE: MVE_VSHL must appear in the table before
2714 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2716 MVE_VSHL_T1,
2717 0xef800550, 0xff801fd1,
6576bffe 2718 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2719
2720 /* Vector VSHR
2721 NOTE: MVE_VSHR must appear in the table before
2722 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2724 MVE_VSHR,
2725 0xef800050, 0xef801fd1,
6576bffe 2726 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2727
2728 /* Vector VSLI
2729 NOTE: MVE_VSLI must appear in the table before
2730 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2732 MVE_VSLI,
2733 0xff800550, 0xff801fd1,
6576bffe 2734 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2735
2736 /* Vector VSRI
2737 NOTE: MVE_VSRI must appear in the table before
2738 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2740 MVE_VSRI,
2741 0xff800450, 0xff801fd1,
6576bffe 2742 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2743
c507f10b 2744 /* Vector VMOV immediate to vector,
ce760a76 2745 undefinded for cmode == 1111 */
2da2eaf4 2746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2747 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2748
2749 /* Vector VMOV immediate to vector,
2750 cmode == 1101 */
2da2eaf4 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2752 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2753 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2754
2755 /* Vector VMOV immediate to vector. */
2da2eaf4 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2757 MVE_VMOV_IMM_TO_VEC,
2758 0xef800050, 0xefb810d0,
2759 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2760
2761 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2763 MVE_VMOV2_VEC_LANE_TO_GP,
2764 0xec000f00, 0xffb01ff0,
6576bffe 2765 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
c507f10b
AV		 2766
2767 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2769 MVE_VMOV2_VEC_LANE_TO_GP,
2770 0xec000f10, 0xffb01ff0,
6576bffe 2771 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
c507f10b
AV		 2772
2773 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2774 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2775 MVE_VMOV2_GP_TO_VEC_LANE,
2776 0xec100f00, 0xffb01ff0,
6576bffe 2777 "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
c507f10b
AV		 2778
2779 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2781 MVE_VMOV2_GP_TO_VEC_LANE,
2782 0xec100f10, 0xffb01ff0,
6576bffe 2783 "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
c507f10b
AV		 2784
2785 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2787 MVE_VMOV_VEC_LANE_TO_GP,
2788 0xee100b10, 0xff100f1f,
6576bffe 2789 "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
c507f10b 2790
ed63aa17
AV		 2791 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2792 to instruction opcode aliasing. */
2da2eaf4 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2794 MVE_VSHLL_T1,
2795 0xeea00f40, 0xefa00fd1,
6576bffe 2796 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2797
14925797 2798 /* Vector VMOVL long. */
2da2eaf4 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2800 MVE_VMOVL,
2801 0xeea00f40, 0xefa70fd1,
2802 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2803
2804 /* Vector VMOV and narrow. */
2da2eaf4 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2806 MVE_VMOVN,
2807 0xfe310e81, 0xffb30fd1,
2808 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2809
c507f10b 2810 /* Floating point move extract. */
2da2eaf4 2811 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2812 MVE_VMOVX,
2813 0xfeb00a40, 0xffbf0fd0,
2814 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2815
f49bb598 2816 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2818 MVE_VMUL_FP_T1,
2819 0xff000d50, 0xffa11f51,
2820 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2821
2822 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2823 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2824 MVE_VMUL_FP_T2,
2825 0xee310e60, 0xefb11f70,
2826 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2827
2828 /* Vector VMUL T1 variant. */
2da2eaf4 2829 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2830 MVE_VMUL_VEC_T1,
2831 0xef000950, 0xff811f51,
2832 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2833
2834 /* Vector VMUL T2 variant. */
2da2eaf4 2835 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2836 MVE_VMUL_VEC_T2,
2837 0xee011e60, 0xff811f70,
2838 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2839
2840 /* Vector VMULH. */
2da2eaf4 2841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2842 MVE_VMULH,
2843 0xee010e01, 0xef811f51,
2844 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2845
2846 /* Vector VRMULH. */
2da2eaf4 2847 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2848 MVE_VRMULH,
2849 0xee011e01, 0xef811f51,
2850 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2851
14925797 2852 /* Vector VMULL integer. */
2da2eaf4 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2854 MVE_VMULL_INT,
2855 0xee010e00, 0xef810f51,
2856 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2857
2858 /* Vector VMULL polynomial. */
2da2eaf4 2859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2860 MVE_VMULL_POLY,
2861 0xee310e00, 0xefb10f51,
2862 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2863
c507f10b 2864 /* Vector VMVN immediate to vector. */
2da2eaf4 2865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2866 MVE_VMVN_IMM,
2867 0xef800070, 0xefb810f0,
2868 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2869
2870 /* Vector VMVN register. */
2da2eaf4 2871 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2872 MVE_VMVN_REG,
2873 0xffb005c0, 0xffbf1fd1,
2874 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2875
f49bb598 2876 /* Vector VNEG floating point. */
2da2eaf4 2877 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2878 MVE_VNEG_FP,
2879 0xffb107c0, 0xffb31fd1,
2880 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2881
2882 /* Vector VNEG. */
2da2eaf4 2883 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2884 MVE_VNEG_VEC,
2885 0xffb103c0, 0xffb31fd1,
2886 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2887
c507f10b 2888 /* Vector VORN, vector bitwise or not. */
2da2eaf4 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2890 MVE_VORN,
2891 0xef300150, 0xffb11f51,
2892 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2893
2894 /* Vector VORR register. */
2da2eaf4 2895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2896 MVE_VORR_REG,
2897 0xef200150, 0xffb11f51,
2898 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2899
c4a23bf8
SP		 2900 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2901 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2902 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2903 array. */
2904
2da2eaf4 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 2906 MVE_VMOV_VEC_TO_VEC,
2907 0xef200150, 0xffb11f51,
2908 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2909
14925797 2910 /* Vector VQDMULL T1 variant. */
2da2eaf4 2911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2912 MVE_VQDMULL_T1,
2913 0xee300f01, 0xefb10f51,
2914 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2915
14b456f2 2916 /* Vector VPNOT. */
2da2eaf4 2917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2918 MVE_VPNOT,
2919 0xfe310f4d, 0xffffffff,
2920 "vpnot%v"},
2921
2922 /* Vector VPSEL. */
2da2eaf4 2923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2924 MVE_VPSEL,
2925 0xfe310f01, 0xffb11f51,
2926 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2927
2928 /* Vector VQABS. */
2da2eaf4 2929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2930 MVE_VQABS,
2931 0xffb00740, 0xffb31fd1,
2932 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2933
2934 /* Vector VQADD T1 variant. */
2da2eaf4 2935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2936 MVE_VQADD_T1,
2937 0xef000050, 0xef811f51,
2938 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2939
2940 /* Vector VQADD T2 variant. */
2da2eaf4 2941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2942 MVE_VQADD_T2,
2943 0xee000f60, 0xef811f70,
2944 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2945
14925797 2946 /* Vector VQDMULL T2 variant. */
2da2eaf4 2947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2948 MVE_VQDMULL_T2,
2949 0xee300f60, 0xefb10f70,
2950 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2951
2952 /* Vector VQMOVN. */
2da2eaf4 2953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2954 MVE_VQMOVN,
2955 0xee330e01, 0xefb30fd1,
2956 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2957
2958 /* Vector VQMOVUN. */
2da2eaf4 2959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2960 MVE_VQMOVUN,
2961 0xee310e81, 0xffb30fd1,
2962 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2963
d3b63143 2964 /* Vector VQDMLADH. */
2da2eaf4 2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2966 MVE_VQDMLADH,
2967 0xee000e00, 0xff810f51,
2968 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2969
2970 /* Vector VQRDMLADH. */
2da2eaf4 2971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2972 MVE_VQRDMLADH,
2973 0xee000e01, 0xff810f51,
2974 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2975
2976 /* Vector VQDMLAH. */
2da2eaf4 2977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2978 MVE_VQDMLAH,
23d188c7 2979 0xee000e60, 0xff811f70,
d3b63143
AV		 2980 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2981
2982 /* Vector VQRDMLAH. */
2da2eaf4 2983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2984 MVE_VQRDMLAH,
23d188c7 2985 0xee000e40, 0xff811f70,
d3b63143
AV		 2986 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2987
2988 /* Vector VQDMLASH. */
2da2eaf4 2989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2990 MVE_VQDMLASH,
23d188c7 2991 0xee001e60, 0xff811f70,
d3b63143
AV		 2992 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2993
2994 /* Vector VQRDMLASH. */
2da2eaf4 2995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2996 MVE_VQRDMLASH,
23d188c7 2997 0xee001e40, 0xff811f70,
d3b63143
AV		 2998 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2999
3000 /* Vector VQDMLSDH. */
2da2eaf4 3001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3002 MVE_VQDMLSDH,
3003 0xfe000e00, 0xff810f51,
3004 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3005
3006 /* Vector VQRDMLSDH. */
2da2eaf4 3007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3008 MVE_VQRDMLSDH,
3009 0xfe000e01, 0xff810f51,
3010 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3011
3012 /* Vector VQDMULH T1 variant. */
2da2eaf4 3013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3014 MVE_VQDMULH_T1,
3015 0xef000b40, 0xff811f51,
3016 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3017
3018 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3020 MVE_VQRDMULH_T2,
3021 0xff000b40, 0xff811f51,
3022 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3023
3024 /* Vector VQDMULH T3 variant. */
2da2eaf4 3025 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3026 MVE_VQDMULH_T3,
3027 0xee010e60, 0xff811f70,
3028 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3029
3030 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3031 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3032 MVE_VQRDMULH_T4,
3033 0xfe010e60, 0xff811f70,
3034 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3035
14b456f2 3036 /* Vector VQNEG. */
2da2eaf4 3037 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3038 MVE_VQNEG,
3039 0xffb007c0, 0xffb31fd1,
3040 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3041
ed63aa17 3042 /* Vector VQRSHL T1 variant. */
2da2eaf4 3043 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3044 MVE_VQRSHL_T1,
3045 0xef000550, 0xef811f51,
3046 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3047
3048 /* Vector VQRSHL T2 variant. */
2da2eaf4 3049 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3050 MVE_VQRSHL_T2,
3051 0xee331ee0, 0xefb31ff0,
3052 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3053
3054 /* Vector VQRSHRN. */
2da2eaf4 3055 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3056 MVE_VQRSHRN,
3057 0xee800f41, 0xefa00fd1,
6576bffe 3058 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3059
3060 /* Vector VQRSHRUN. */
2da2eaf4 3061 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3062 MVE_VQRSHRUN,
3063 0xfe800fc0, 0xffa00fd1,
6576bffe 3064 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3065
3066 /* Vector VQSHL T1 Variant. */
2da2eaf4 3067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3068 MVE_VQSHL_T1,
3069 0xee311ee0, 0xefb31ff0,
3070 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3071
3072 /* Vector VQSHL T4 Variant. */
2da2eaf4 3073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3074 MVE_VQSHL_T4,
3075 0xef000450, 0xef811f51,
3076 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3077
3078 /* Vector VQSHRN. */
2da2eaf4 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3080 MVE_VQSHRN,
3081 0xee800f40, 0xefa00fd1,
6576bffe 3082 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3083
3084 /* Vector VQSHRUN. */
2da2eaf4 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3086 MVE_VQSHRUN,
3087 0xee800fc0, 0xffa00fd1,
6576bffe 3088 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3089
14b456f2 3090 /* Vector VQSUB T1 Variant. */
2da2eaf4 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3092 MVE_VQSUB_T1,
3093 0xef000250, 0xef811f51,
3094 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3095
3096 /* Vector VQSUB T2 Variant. */
2da2eaf4 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3098 MVE_VQSUB_T2,
3099 0xee001f60, 0xef811f70,
3100 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3101
3102 /* Vector VREV16. */
2da2eaf4 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3104 MVE_VREV16,
3105 0xffb00140, 0xffb31fd1,
3106 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3107
3108 /* Vector VREV32. */
2da2eaf4 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3110 MVE_VREV32,
3111 0xffb000c0, 0xffb31fd1,
3112 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3113
3114 /* Vector VREV64. */
2da2eaf4 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3116 MVE_VREV64,
3117 0xffb00040, 0xffb31fd1,
3118 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3119
bf0b396d 3120 /* Vector VRINT floating point. */
2da2eaf4 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3122 MVE_VRINT_FP,
3123 0xffb20440, 0xffb31c51,
3124 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3125
d3b63143 3126 /* Vector VRMLALDAVH. */
2da2eaf4 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3128 MVE_VRMLALDAVH,
3129 0xee800f00, 0xef811f51,
3130 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3131
3132 /* Vector VRMLALDAVH. */
2da2eaf4 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3134 MVE_VRMLALDAVH,
3135 0xee801f00, 0xef811f51,
3136 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3137
ed63aa17 3138 /* Vector VRSHL T1 Variant. */
2da2eaf4 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3140 MVE_VRSHL_T1,
3141 0xef000540, 0xef811f51,
3142 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3143
3144 /* Vector VRSHL T2 Variant. */
2da2eaf4 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3146 MVE_VRSHL_T2,
3147 0xee331e60, 0xefb31ff0,
3148 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3149
3150 /* Vector VRSHRN. */
2da2eaf4 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3152 MVE_VRSHRN,
3153 0xfe800fc1, 0xffa00fd1,
6576bffe 3154 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3155
66dcaa5d 3156 /* Vector VSBC. */
2da2eaf4 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3158 MVE_VSBC,
3159 0xfe300f00, 0xffb10f51,
3160 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3161
ed63aa17 3162 /* Vector VSHL T2 Variant. */
2da2eaf4 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3164 MVE_VSHL_T2,
3165 0xee311e60, 0xefb31ff0,
3166 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3167
3168 /* Vector VSHL T3 Variant. */
2da2eaf4 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3170 MVE_VSHL_T3,
3171 0xef000440, 0xef811f51,
3172 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3173
3174 /* Vector VSHLC. */
2da2eaf4 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3176 MVE_VSHLC,
3177 0xeea00fc0, 0xffa01ff0,
6576bffe 3178 "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
ed63aa17
AV		 3179
3180 /* Vector VSHLL T2 Variant. */
2da2eaf4 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3182 MVE_VSHLL_T2,
3183 0xee310e01, 0xefb30fd1,
6576bffe 3184 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
ed63aa17
AV		 3185
3186 /* Vector VSHRN. */
2da2eaf4 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3188 MVE_VSHRN,
3189 0xee800fc1, 0xffa00fd1,
6576bffe 3190 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3191
04d54ace 3192 /* Vector VST2 no writeback. */
2da2eaf4 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3194 MVE_VST2,
3195 0xfc801e00, 0xffb01e5f,
3196 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3197
3198 /* Vector VST2 writeback. */
2da2eaf4 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3200 MVE_VST2,
3201 0xfca01e00, 0xffb01e5f,
3202 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3203
3204 /* Vector VST4 no writeback. */
2da2eaf4 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3206 MVE_VST4,
3207 0xfc801e01, 0xffb01e1f,
3208 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3209
3210 /* Vector VST4 writeback. */
2da2eaf4 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3212 MVE_VST4,
3213 0xfca01e01, 0xffb01e1f,
3214 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3215
ef1576a1 3216 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3218 MVE_VSTRB_SCATTER_T1,
3219 0xec800e00, 0xffb01e50,
3220 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3221
3222 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3224 MVE_VSTRH_SCATTER_T2,
3225 0xec800e10, 0xffb01e50,
3226 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3227
3228 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3230 MVE_VSTRW_SCATTER_T3,
3231 0xec800e40, 0xffb01e50,
3232 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3233
3234 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3236 MVE_VSTRD_SCATTER_T4,
3237 0xec800fd0, 0xffb01fd0,
3238 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3239
3240 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3242 MVE_VSTRW_SCATTER_T5,
3243 0xfd001e00, 0xff111f00,
6576bffe 3244 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 3245
3246 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3248 MVE_VSTRD_SCATTER_T6,
3249 0xfd001f00, 0xff111f00,
6576bffe 3250 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 3251
aef6d006 3252 /* Vector VSTRB. */
2da2eaf4 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3254 MVE_VSTRB_T1,
3255 0xec000e00, 0xfe581e00,
3256 "vstrb%v.%7-8s\t%13-15Q, %d"},
3257
3258 /* Vector VSTRH. */
2da2eaf4 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3260 MVE_VSTRH_T2,
3261 0xec080e00, 0xfe581e00,
3262 "vstrh%v.%7-8s\t%13-15Q, %d"},
3263
3264 /* Vector VSTRB variant T5. */
2da2eaf4 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3266 MVE_VSTRB_T5,
3267 0xec001e00, 0xfe101f80,
3268 "vstrb%v.8\t%13-15,22Q, %d"},
3269
3270 /* Vector VSTRH variant T6. */
2da2eaf4 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3272 MVE_VSTRH_T6,
3273 0xec001e80, 0xfe101f80,
3274 "vstrh%v.16\t%13-15,22Q, %d"},
3275
3276 /* Vector VSTRW variant T7. */
2da2eaf4 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3278 MVE_VSTRW_T7,
3279 0xec001f00, 0xfe101f80,
3280 "vstrw%v.32\t%13-15,22Q, %d"},
3281
66dcaa5d 3282 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3284 MVE_VSUB_FP_T1,
3285 0xef200d40, 0xffa11f51,
3286 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3287
3288 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3290 MVE_VSUB_FP_T2,
3291 0xee301f40, 0xefb11f70,
3292 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3293
3294 /* Vector VSUB T1 variant. */
2da2eaf4 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3296 MVE_VSUB_VEC_T1,
3297 0xff000840, 0xff811f51,
3298 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3299
3300 /* Vector VSUB T2 variant. */
2da2eaf4 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3302 MVE_VSUB_VEC_T2,
3303 0xee011f40, 0xff811f70,
3304 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3305
2da2eaf4 3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3307 MVE_ASRLI,
3308 0xea50012f, 0xfff1813f,
3309 "asrl%c\t%17-19l, %9-11h, %j"},
3310
2da2eaf4 3311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3312 MVE_ASRL,
3313 0xea50012d, 0xfff101ff,
3314 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3315
2da2eaf4 3316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3317 MVE_LSLLI,
3318 0xea50010f, 0xfff1813f,
3319 "lsll%c\t%17-19l, %9-11h, %j"},
3320
2da2eaf4 3321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3322 MVE_LSLL,
3323 0xea50010d, 0xfff101ff,
3324 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3325
2da2eaf4 3326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3327 MVE_LSRL,
3328 0xea50011f, 0xfff1813f,
3329 "lsrl%c\t%17-19l, %9-11h, %j"},
3330
2da2eaf4 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3332 MVE_SQRSHRL,
08132bdd
SP		 3333 0xea51012d, 0xfff1017f,
3334 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3335
2da2eaf4 3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3337 MVE_SQRSHR,
3338 0xea500f2d, 0xfff00fff,
3339 "sqrshr%c\t%16-19S, %12-15S"},
3340
2da2eaf4 3341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3342 MVE_SQSHLL,
3343 0xea51013f, 0xfff1813f,
3344 "sqshll%c\t%17-19l, %9-11h, %j"},
3345
2da2eaf4 3346 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3347 MVE_SQSHL,
3348 0xea500f3f, 0xfff08f3f,
3349 "sqshl%c\t%16-19S, %j"},
3350
2da2eaf4 3351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3352 MVE_SRSHRL,
3353 0xea51012f, 0xfff1813f,
3354 "srshrl%c\t%17-19l, %9-11h, %j"},
3355
2da2eaf4 3356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3357 MVE_SRSHR,
3358 0xea500f2f, 0xfff08f3f,
3359 "srshr%c\t%16-19S, %j"},
3360
2da2eaf4 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3362 MVE_UQRSHLL,
08132bdd
SP		 3363 0xea51010d, 0xfff1017f,
3364 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3365
2da2eaf4 3366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3367 MVE_UQRSHL,
3368 0xea500f0d, 0xfff00fff,
3369 "uqrshl%c\t%16-19S, %12-15S"},
3370
2da2eaf4 3371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3372 MVE_UQSHLL,
3373 0xea51010f, 0xfff1813f,
3374 "uqshll%c\t%17-19l, %9-11h, %j"},
3375
2da2eaf4 3376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3377 MVE_UQSHL,
3378 0xea500f0f, 0xfff08f3f,
3379 "uqshl%c\t%16-19S, %j"},
3380
2da2eaf4 3381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3382 MVE_URSHRL,
3383 0xea51011f, 0xfff1813f,
3384 "urshrl%c\t%17-19l, %9-11h, %j"},
3385
2da2eaf4 3386 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3387 MVE_URSHR,
3388 0xea500f1f, 0xfff08f3f,
3389 "urshr%c\t%16-19S, %j"},
3390
e39c1607
SD		 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3392 MVE_CSINC,
3393 0xea509000, 0xfff0f000,
3394 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3395
3396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3397 MVE_CSINV,
3398 0xea50a000, 0xfff0f000,
3399 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3400
3401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3402 MVE_CSET,
3403 0xea5f900f, 0xfffff00f,
3404 "cset\t%8-11S, %4-7C"},
3405
3406 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3407 MVE_CSETM,
3408 0xea5fa00f, 0xfffff00f,
3409 "csetm\t%8-11S, %4-7C"},
3410
3411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3412 MVE_CSEL,
3413 0xea508000, 0xfff0f000,
3414 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3415
3416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3417 MVE_CSNEG,
3418 0xea50b000, 0xfff0f000,
3419 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3420
3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3422 MVE_CINC,
3423 0xea509000, 0xfff0f000,
3424 "cinc\t%8-11S, %16-19Z, %4-7C"},
3425
3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3427 MVE_CINV,
3428 0xea50a000, 0xfff0f000,
3429 "cinv\t%8-11S, %16-19Z, %4-7C"},
3430
3431 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3432 MVE_CNEG,
3433 0xea50b000, 0xfff0f000,
3434 "cneg\t%8-11S, %16-19Z, %4-7C"},
3435
143275ea
AV		 3436 {ARM_FEATURE_CORE_LOW (0),
3437 MVE_NONE,
3438 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3439};
3440
8f06b2d8
PB		 3441/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3442 ordered: they must be searched linearly from the top to obtain a correct
3443 match. */
3444
3445/* print_insn_arm recognizes the following format control codes:
3446
3447 %% %
3448
3449 %a print address for ldr/str instruction
3450 %s print address for ldr/str halfword/signextend instruction
c1e26897 3451 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3452 %b print branch destination
3453 %c print condition code (always bits 28-31)
3454 %m print register mask for ldm/stm instruction
3455 %o print operand2 (immediate or register + shift)
3456 %p print 'p' iff bits 12-15 are 15
3457 %t print 't' iff bit 21 set and bit 24 clear
3458 %B print arm BLX(1) destination
3459 %C print the PSR sub type.
62b3e311
PB		 3460 %U print barrier type.
3461 %P print address for pli instruction.
8f06b2d8
PB		 3462
3463 %<bitfield>r print as an ARM register
9eb6c0f1 3464 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3465 %<bitfield>R as %r but r15 is UNPREDICTABLE
3466 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3467 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3468 %<bitfield>d print the bitfield in decimal
43e65147 3469 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3470 %<bitfield>x print the bitfield in hex
3471 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3472
16980d0b
JB		 3473 %<bitfield>'c print specified char iff bitfield is all ones
3474 %<bitfield>`c print specified char iff bitfield is all zeroes
3475 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3476
8f06b2d8
PB		 3477 %e print arm SMI operand (bits 0..7,8..19).
3478 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3479 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3480 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3481
8f06b2d8
PB		 3482static const struct opcode32 arm_opcodes[] =
3483{
3484 /* ARM instructions. */
823d2571 3485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 3486 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
823d2571 3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3488 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
823d2571
TG		 3489
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3491 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3493 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3495 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3497 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3499 0x00800090, 0x0fa000f0,
3500 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3502 0x00a00090, 0x0fa000f0,
3503 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3504
105bde57 3505 /* V8.2 RAS extension instructions. */
4d1464f2 3506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3507 0xe320f010, 0xffffffff, "esb"},
3508
26417f19
AC		 3509 /* V8-R instructions. */
3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3511 0xf57ff04c, 0xffffffff, "dfb"},
3512
53c4b28b 3513 /* V8 instructions. */
823d2571
TG		 3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3515 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3516 /* Defined in V8 but is in NOP space so available to all arch. */
3517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3518 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
4ed7ed8d 3519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3520 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3521 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3522 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3524 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3526 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3527 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3528 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3529 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3530 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3531 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3532 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3533 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3534 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3535 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3536 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3537 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3538 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3539 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3540 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3541 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3542 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3543 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3544 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3545 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3546 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3547 /* CRC32 instructions. */
8b301fbb 3548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3549 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3551 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3553 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3555 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3557 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3559 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3560
ddfded2f
MW		 3561 /* Privileged Access Never extension instructions. */
3562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
6576bffe 3563 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
ddfded2f 3564
90ec0d68 3565 /* Virtualization Extension instructions. */
823d2571
TG		 3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3568
eea54501 3569 /* Integer Divide Extension instructions. */
823d2571
TG		 3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3571 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3573 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3574
60e5ef9f 3575 /* MP Extension instructions. */
823d2571 3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3577
c597cc3d
SD		 3578 /* Speculation Barriers. */
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3582
62b3e311 3583 /* V7 instructions. */
823d2571 3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
6576bffe 3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a 3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 3592 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
62b3e311 3593
c19d1205 3594 /* ARM V6T2 instructions. */
823d2571
TG		 3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3596 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3598 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3600 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3602 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3603
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3605 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3607 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3608
ff8646ee 3609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3610 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3612 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3614 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 3616 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
885fc257 3617
f4c65163 3618 /* ARM Security extension instructions. */
823d2571
TG		 3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3620 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3621
8f06b2d8 3622 /* ARM V6K instructions. */
823d2571
TG		 3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3624 0xf57ff01f, 0xffffffff, "clrex"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3626 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3628 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3630 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3632 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3634 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3636 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3637
7fadb25d
SD		 3638 /* ARMv8.5-A instructions. */
3639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3640
8f06b2d8 3641 /* ARM V6K NOP hints. */
823d2571
TG		 3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3643 0x0320f001, 0x0fffffff, "yield%c"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3645 0x0320f002, 0x0fffffff, "wfe%c"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3647 0x0320f003, 0x0fffffff, "wfi%c"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3649 0x0320f004, 0x0fffffff, "sev%c"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
6576bffe 3651 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
c19d1205 3652
fe56b6ce 3653 /* ARM V6 instructions. */
823d2571 3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3655 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
823d2571 3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3657 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3659 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
823d2571 3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3661 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3663 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
823d2571
TG		 3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3665 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3667 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3669 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
823d2571 3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3671 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3673 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
823d2571
TG		 3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3675 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3677 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3679 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3681 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3683 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3685 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3687 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3689 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3691 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3693 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3695 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3697 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3699 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3701 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3703 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3705 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3707 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3709 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3711 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3713 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3715 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3717 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3719 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3721 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3723 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3725 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3727 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3729 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3731 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3733 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3735 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3737 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3739 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3741 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3743 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3745 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3747 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3749 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3757 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3759 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3761 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3763 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3765 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3767 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3769 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3771 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3773 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3775 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3777 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3779 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3781 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3783 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3785 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3787 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3789 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3791 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3793 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3795 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3797 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3799 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3801 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3803 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3805 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3807 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3809 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3813 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3815 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3817 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3821 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3823 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3825 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3829 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3831 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3833 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3837 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3839 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3841 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
823d2571
TG		 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3845 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3847 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3849 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3853 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
823d2571
TG		 3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3873 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3875 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
823d2571 3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3877 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3879 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3881 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
823d2571
TG		 3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3891 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
823d2571 3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3893 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3895 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3897 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
c19d1205 3898
8f06b2d8 3899 /* V5J instruction. */
823d2571
TG		 3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3901 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3902
8f06b2d8 3903 /* V5 Instructions. */
823d2571
TG		 3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3905 0xe1200070, 0xfff000f0,
6576bffe 3906 "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
823d2571
TG		 3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3908 0xfa000000, 0xfe000000, "blx\t%B"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3910 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3912 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3913
3914 /* V5E "El Segundo" Instructions. */
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3916 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3918 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3920 0xf450f000, 0xfc70f000, "pld\t%a"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3922 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3924 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3926 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3928 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3929
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3931 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3933 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3934
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3936 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3938 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3940 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3942 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3943
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3945 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3947 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3949 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3951 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3952
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3954 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3956 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3957
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3959 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3961 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3963 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3965 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3966
8f06b2d8 3967 /* ARM Instructions. */
823d2571 3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 3969 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
823d2571
TG		 3970
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3972 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3974 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3976 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3978 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3980 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3982 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3983
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3985 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3987 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3989 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3991 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3992
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3994 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3998 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4000 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4001
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4005 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4007 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4008
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4014 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4015
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4017 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4021 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4022
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4024 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4026 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4028 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4029
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4031 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4033 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4035 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4036
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4038 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4042 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4043
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4049 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4050
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4057
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4059 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4061 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4063 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4064
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4071
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4073 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4075 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4077 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4078
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4085
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4092
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4098 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4099
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4109 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4111 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4114
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4116 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4118 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4121
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4125 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4127 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4128
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 4132 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
823d2571
TG		 4133
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4135 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4136
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4140 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4141
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4167 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4169 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x092d0000, 0x0fff0000, "push%c\t%m"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4180
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4204 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4206 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4208 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4210 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4218 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4219
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4224
4225 /* The rest. */
4ab90a7a 4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 4227 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4230 {ARM_FEATURE_CORE_LOW (0),
4231 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4232};
4233
4234/* print_insn_thumb16 recognizes the following format control codes:
4235
4236 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4237 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4238 %<bitfield>I print bitfield as a signed decimal
4239 (top bit of range being the sign bit)
4240 %N print Thumb register mask (with LR)
4241 %O print Thumb register mask (with PC)
4242 %M print Thumb register mask
4243 %b print CZB's 6-bit unsigned branch destination
4244 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4245 %c print the condition code
4246 %C print the condition code, or "s" if not conditional
4247 %x print warning if conditional an not at end of IT block"
8cb6e175 4248 %X print "\t@ unpredictable <IT:code>" if conditional
c22aaad1 4249 %I print IT instruction suffix and operands
4547cb56 4250 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4251 %<bitfield>r print bitfield as an ARM register
4252 %<bitfield>d print bitfield as a decimal
4253 %<bitfield>H print (bitfield * 2) as a decimal
4254 %<bitfield>W print (bitfield * 4) as a decimal
4255 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4256 %<bitfield>B print Thumb branch destination (signed displacement)
4257 %<bitfield>c print bitfield as a condition code
4258 %<bitnum>'c print specified char iff bit is one
4259 %<bitnum>?ab print a if bit is one else print b. */
4260
4261static const struct opcode16 thumb_opcodes[] =
4262{
4263 /* Thumb instructions. */
4264
16a1fa25
TP		 4265 /* ARMv8-M Security Extensions instructions. */
4266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4268
53c4b28b 4269 /* ARM V8 instructions. */
823d2571
TG		 4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
6576bffe 4272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
53c4b28b 4273
8f06b2d8 4274 /* ARM V6K no-argument instructions. */
823d2571
TG		 4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4281
4282 /* ARM V6T2 instructions. */
ff8646ee
TP		 4283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4284 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4286 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4288
4289 /* ARM V6. */
6576bffe
AB		 4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
823d2571
TG		 4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
6576bffe 4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
823d2571
TG		 4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4301
4302 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4304 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4305 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4307 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4308 /* ARM V4T ISA (Thumb v1). */
823d2571 4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
8cb6e175 4310 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
8f06b2d8 4311 /* Format 4. */
823d2571
TG		 4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4328 /* format 13 */
6576bffe
AB		 4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
8f06b2d8 4331 /* format 5 */
823d2571
TG		 4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4336 /* format 14 */
823d2571
TG		 4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4339 /* format 2 */
823d2571
TG		 4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4341 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4343 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4345 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
823d2571 4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4347 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
8f06b2d8 4348 /* format 8 */
823d2571
TG		 4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4350 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4352 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4354 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4355 /* format 7 */
823d2571
TG		 4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4357 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4359 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4360 /* format 1 */
823d2571
TG		 4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4363 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
823d2571
TG		 4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4366 /* format 3 */
6576bffe
AB		 4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
8f06b2d8 4371 /* format 6 */
823d2571
TG		 4372 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4374 0x4800, 0xF800,
6576bffe 4375 "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
8f06b2d8 4376 /* format 9 */
823d2571 4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4378 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4380 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4382 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
823d2571 4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4384 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
8f06b2d8 4385 /* format 10 */
823d2571 4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4387 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
823d2571 4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4389 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
8f06b2d8 4390 /* format 11 */
823d2571 4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4392 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
823d2571 4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4394 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
8f06b2d8 4395 /* format 12 */
823d2571 4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4397 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
823d2571 4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4399 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
8f06b2d8 4400 /* format 15 */
823d2571
TG		 4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4403 /* format 17 */
823d2571 4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4405 /* format 16 */
6576bffe 4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
823d2571
TG		 4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4409 /* format 18 */
823d2571 4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4411
4412 /* The E800 .. FFFF range is unconditionally redirected to the
4413 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4414 are processed via that table. Thus, we can never encounter a
4415 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4417 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4418};
4419
4420/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4421 We adopt the convention that hw1 is the high 16 bits of .value and
4422 .mask, hw2 the low 16 bits.
4423
4424 print_insn_thumb32 recognizes the following format control codes:
4425
4426 %% %
4427
4428 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4429 %M print a modified 12-bit immediate (same location)
4430 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4431 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4432 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4433 %S print a possibly-shifted Rm
4434
32a94698 4435 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4436 %a print the address of a plain load/store
4437 %w print the width and signedness of a core load/store
4438 %m print register mask for ldm/stm
4b5a202f 4439 %n print register mask for clrm
8f06b2d8
PB		 4440
4441 %E print the lsb and width fields of a bfc/bfi instruction
4442 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4443 %G print a fallback offset for Branch Future instructions
e5d6e09e 4444 %W print an offset for BF instruction
1caf72a5 4445 %Y print an offset for BFL instruction
1889da70 4446 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4447 %Q print an offset for Low Overhead Loop instructions
4448 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4449 %b print a conditional branch offset
4450 %B print an unconditional branch offset
4451 %s print the shift field of an SSAT instruction
4452 %R print the rotation field of an SXT instruction
62b3e311
PB		 4453 %U print barrier type.
4454 %P print address for pli instruction.
c22aaad1
PB		 4455 %c print the condition code
4456 %x print warning if conditional an not at end of IT block"
8cb6e175 4457 %X print "\t@ unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4458
4459 %<bitfield>d print bitfield in decimal
f0fba320 4460 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4461 %<bitfield>W print bitfield*4 in decimal
4462 %<bitfield>r print bitfield as an ARM register
dd5181d5 4463 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4464 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4465 %<bitfield>c print bitfield as a condition code
4466
16980d0b
JB		 4467 %<bitfield>'c print specified char iff bitfield is all ones
4468 %<bitfield>`c print specified char iff bitfield is all zeroes
4469 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4470
4471 With one exception at the bottom (done because BL and BLX(1) need
4472 to come dead last), this table was machine-sorted first in
4473 decreasing order of number of bits set in the mask, then in
4474 increasing numeric order of mask, then in increasing numeric order
4475 of opcode. This order is not the clearest for a human reader, but
4476 is guaranteed never to catch a special-case bit pattern with a more
4477 general mask, which is important, because this instruction encoding
4478 makes heavy use of special-case bit patterns. */
4479static const struct opcode32 thumb32_opcodes[] =
4480{
3751264c
AC		 4481 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4482 Identification Extension. */
e43ca2cb 4483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4484 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
be05908c
AC		 4485 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4486 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
3751264c
AC		 4487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4488 0xf3af800f, 0xffffffff, "bti"},
e07352fa
AC		 4489 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4490 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
ce537a7d 4491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4492 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
f1e1d7f3 4493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4494 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
5c43020d
AC		 4495 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4496 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
3751264c 4497
4b5a202f
AV		 4498 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4499 instructions. */
60f993ce 4500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4501 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4503 0xf02fc001, 0xfffff001, "le\t%P"},
4504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4505 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
d052b9b7 4506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4507 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
d052b9b7 4508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4509 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4511 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4513 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
d052b9b7 4514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4515 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
60f993ce 4516
4389b29a
AV		 4517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4518 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4520 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4522 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4524 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d 4525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4526 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4389b29a 4527
4b5a202f
AV		 4528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4529 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4530
16a1fa25
TP		 4531 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4534 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4536 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4538 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4540 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4541
105bde57 4542 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4544 0xf3af8010, 0xffffffff, "esb"},
4545
53c4b28b 4546 /* V8 instructions. */
823d2571
TG		 4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4548 0xf3af8005, 0xffffffff, "sevl%c.w"},
4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4550 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4552 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4554 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4556 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4558 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4560 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4562 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4564 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4566 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4568 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4570 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4572 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4574 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4576 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4578 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4579
26417f19
AC		 4580 /* V8-R instructions. */
4581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4582 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4583
dd5181d5 4584 /* CRC32 instructions. */
8b301fbb 4585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4586 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4588 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4590 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4592 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4594 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4596 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4597
c597cc3d
SD		 4598 /* Speculation Barriers. */
4599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4602
62b3e311 4603 /* V7 instructions. */
823d2571 4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
6576bffe 4605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4611 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4612 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4613 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4614 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4615
90ec0d68 4616 /* Virtualization Extension instructions. */
823d2571 4617 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4618 /* We skip ERET as that is SUBS pc, lr, #0. */
4619
60e5ef9f 4620 /* MP Extension instructions. */
823d2571 4621 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4622
f4c65163 4623 /* Security extension instructions. */
823d2571 4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4625
7fadb25d
SD		 4626 /* ARMv8.5-A instructions. */
4627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4628
8f06b2d8 4629 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4636 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
823d2571
TG		 4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4638
ff8646ee 4639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4640 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4642 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571 4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4644 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571
TG		 4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4646 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4648 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4650 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4652 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4654 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
823d2571
TG		 4655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4656 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4658 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
823d2571 4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4660 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4662 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4664 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
823d2571
TG		 4665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4666 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4668 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4670 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4672 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 4673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4674 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571
TG		 4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4676 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4678 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4680 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4682 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4684 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4686 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4688 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4690 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4692 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4694 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4696 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4698 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4700 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4702 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4704 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4706 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4708 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4710 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4724 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4726 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4738 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4744 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4758 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4794 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4795 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4796 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4798 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
823d2571 4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4800 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
823d2571
TG		 4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4863 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 4864 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xf810f000, 0xff70f000, "pld%c\t%a"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xfb100000, 0xfff000c0,
4897 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xfbc00080, 0xfff000c0,
4900 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4906 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
823d2571 4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4908 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
823d2571
TG		 4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4912 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4916 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 4938 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972 0xe9400000, 0xff500000,
6576bffe 4973 "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975 0xe9500000, 0xff500000,
6576bffe 4976 "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xe8600000, 0xff700000,
6576bffe 4979 "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xe8700000, 0xff700000,
6576bffe 4982 "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4987
4988 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4997
8f06b2d8 4998 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5000 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5002 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5003
5004 /* Fallback. */
823d2571
TG		 5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5006 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5007 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5008};
ff4a8d2b 5009
8f06b2d8
PB		 5010static const char *const arm_conditional[] =
5011{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5012 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5013
5014static const char *const arm_fp_const[] =
5015{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5016
5017static const char *const arm_shift[] =
5018{"lsl", "lsr", "asr", "ror"};
5019
5020typedef struct
5021{
5022 const char *name;
5023 const char *description;
5024 const char *reg_names[16];
5025}
5026arm_regname;
5027
5028static const arm_regname regnames[] =
5029{
65b48a81 5030 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5031 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5032 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5033 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5034 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5035 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5036 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5037 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5038 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5039 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5040 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5041 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5042 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5043 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5044 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5045};
5046
5047static const char *const iwmmxt_wwnames[] =
5048{"b", "h", "w", "d"};
5049
5050static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5051{"b", "bus", "bc", "bss",
5052 "h", "hus", "hc", "hss",
5053 "w", "wus", "wc", "wss",
5054 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5055};
5056
5057static const char *const iwmmxt_regnames[] =
5058{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5059 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5060};
5061
5062static const char *const iwmmxt_cregnames[] =
5063{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5064 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5065};
5066
143275ea
AV		 5067static const char *const vec_condnames[] =
5068{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5069};
5070
5071static const char *const mve_predicatenames[] =
5072{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5073 "eee", "ee", "eet", "e", "ett", "et", "ete"
5074};
5075
5076/* Names for 2-bit size field for mve vector isntructions. */
5077static const char *const mve_vec_sizename[] =
5078 { "8", "16", "32", "64"};
5079
5080/* Indicates whether we are processing a then predicate,
5081 else predicate or none at all. */
5082enum vpt_pred_state
5083{
5084 PRED_NONE,
5085 PRED_THEN,
5086 PRED_ELSE
5087};
5088
5089/* Information used to process a vpt block and subsequent instructions. */
5090struct vpt_block
5091{
5092 /* Are we in a vpt block. */
78933a4a 5093 bool in_vpt_block;
143275ea
AV		 5094
5095 /* Next predicate state if in vpt block. */
5096 enum vpt_pred_state next_pred_state;
5097
5098 /* Mask from vpt/vpst instruction. */
5099 long predicate_mask;
5100
5101 /* Instruction number in vpt block. */
5102 long current_insn_num;
5103
5104 /* Number of instructions in vpt block.. */
5105 long num_pred_insn;
5106};
5107
5108static struct vpt_block vpt_block_state =
5109{
78933a4a 5110 false,
143275ea
AV		 5111 PRED_NONE,
5112 0,
5113 0,
5114 0
5115};
5116
8f06b2d8
PB		 5117/* Default to GCC register name set. */
5118static unsigned int regname_selected = 1;
5119
65b48a81 5120#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5121#define arm_regnames regnames[regname_selected].reg_names
5122
78933a4a 5123static bool force_thumb = false;
4934a27c 5124static uint16_t cde_coprocs = 0;
8f06b2d8 5125
c22aaad1
PB		 5126/* Current IT instruction state. This contains the same state as the IT
5127 bits in the CPSR. */
5128static unsigned int ifthen_state;
5129/* IT state for the next instruction. */
5130static unsigned int ifthen_next_state;
5131/* The address of the insn for which the IT state is valid. */
5132static bfd_vma ifthen_address;
5133#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5134/* Indicates that the current Conditional state is unconditional or outside
5135 an IT block. */
5136#define COND_UNCOND 16
c22aaad1 5137
8f06b2d8
PB		 5138\f
5139/* Functions. */
143275ea
AV		 5140/* Extract the predicate mask for a VPT or VPST instruction.
5141 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5142
5143static long
5144mve_extract_pred_mask (long given)
5145{
5146 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5147}
5148
5149/* Return the number of instructions in a MVE predicate block. */
5150static long
5151num_instructions_vpt_block (long given)
5152{
5153 long mask = mve_extract_pred_mask (given);
5154 if (mask == 0)
5155 return 0;
5156
5157 if (mask == 8)
5158 return 1;
5159
5160 if ((mask & 7) == 4)
5161 return 2;
5162
5163 if ((mask & 3) == 2)
5164 return 3;
5165
5166 if ((mask & 1) == 1)
5167 return 4;
5168
5169 return 0;
5170}
5171
5172static void
5173mark_outside_vpt_block (void)
5174{
78933a4a 5175 vpt_block_state.in_vpt_block = false;
143275ea
AV		 5176 vpt_block_state.next_pred_state = PRED_NONE;
5177 vpt_block_state.predicate_mask = 0;
5178 vpt_block_state.current_insn_num = 0;
5179 vpt_block_state.num_pred_insn = 0;
5180}
5181
5182static void
5183mark_inside_vpt_block (long given)
5184{
78933a4a 5185 vpt_block_state.in_vpt_block = true;
143275ea
AV		 5186 vpt_block_state.next_pred_state = PRED_THEN;
5187 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5188 vpt_block_state.current_insn_num = 0;
5189 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5190 assert (vpt_block_state.num_pred_insn >= 1);
5191}
5192
5193static enum vpt_pred_state
5194invert_next_predicate_state (enum vpt_pred_state astate)
5195{
5196 if (astate == PRED_THEN)
5197 return PRED_ELSE;
5198 else if (astate == PRED_ELSE)
5199 return PRED_THEN;
5200 else
5201 return PRED_NONE;
5202}
5203
5204static enum vpt_pred_state
5205update_next_predicate_state (void)
5206{
5207 long pred_mask = vpt_block_state.predicate_mask;
5208 long mask_for_insn = 0;
5209
5210 switch (vpt_block_state.current_insn_num)
5211 {
5212 case 1:
5213 mask_for_insn = 8;
5214 break;
5215
5216 case 2:
5217 mask_for_insn = 4;
5218 break;
5219
5220 case 3:
5221 mask_for_insn = 2;
5222 break;
5223
5224 case 4:
5225 return PRED_NONE;
5226 }
5227
5228 if (pred_mask & mask_for_insn)
5229 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5230 else
5231 return vpt_block_state.next_pred_state;
5232}
5233
5234static void
5235update_vpt_block_state (void)
5236{
5237 vpt_block_state.current_insn_num++;
5238 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5239 {
5240 /* No more instructions to process in vpt block. */
5241 mark_outside_vpt_block ();
5242 return;
5243 }
5244
5245 vpt_block_state.next_pred_state = update_next_predicate_state ();
5246}
8f06b2d8 5247
16980d0b
JB		 5248/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5249 Returns pointer to following character of the format string and
5250 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5251 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5252
5253static const char *
fe56b6ce
NC		 5254arm_decode_bitfield (const char *ptr,
5255 unsigned long insn,
5256 unsigned long *valuep,
5257 int *widthp)
16980d0b
JB		 5258{
5259 unsigned long value = 0;
5260 int width = 0;
43e65147
L		 5261
5262 do
16980d0b
JB		 5263 {
5264 int start, end;
5265 int bits;
5266
5267 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5268 start = start * 10 + *ptr - '0';
5269 if (*ptr == '-')
5270 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5271 end = end * 10 + *ptr - '0';
5272 else
5273 end = start;
5274 bits = end - start;
5275 if (bits < 0)
5276 abort ();
5277 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5278 width += bits + 1;
5279 }
5280 while (*ptr++ == ',');
5281 *valuep = value;
5282 if (widthp)
5283 *widthp = width;
5284 return ptr - 1;
5285}
5286
8f06b2d8 5287static void
6576bffe 5288arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
78933a4a 5289 bool print_shift)
8f06b2d8 5290{
6576bffe 5291 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
8f06b2d8
PB		 5292
5293 if ((given & 0xff0) != 0)
5294 {
5295 if ((given & 0x10) == 0)
5296 {
5297 int amount = (given & 0xf80) >> 7;
5298 int shift = (given & 0x60) >> 5;
5299
5300 if (amount == 0)
5301 {
5302 if (shift == 3)
5303 {
6576bffe
AB		 5304 func (stream, dis_style_text, ", ");
5305 func (stream, dis_style_sub_mnemonic, "rrx");
8f06b2d8
PB		 5306 return;
5307 }
5308
5309 amount = 32;
5310 }
5311
37b37b2d 5312 if (print_shift)
6576bffe
AB		 5313 {
5314 func (stream, dis_style_text, ", ");
5315 func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5316 func (stream, dis_style_immediate, "#%d", amount);
5317 }
37b37b2d 5318 else
6576bffe
AB		 5319 {
5320 func (stream, dis_style_text, ", ");
5321 func (stream, dis_style_immediate, "#%d", amount);
5322 }
8f06b2d8 5323 }
74bdfecf 5324 else if ((given & 0x80) == 0x80)
6576bffe
AB		 5325 func (stream, dis_style_comment_start,
5326 "\t@ <illegal shifter operand>");
37b37b2d 5327 else if (print_shift)
6576bffe
AB		 5328 {
5329 func (stream, dis_style_text, ", ");
5330 func (stream, dis_style_sub_mnemonic, "%s ",
5331 arm_shift[(given & 0x60) >> 5]);
5332 func (stream, dis_style_register, "%s",
5333 arm_regnames[(given & 0xf00) >> 8]);
5334 }
37b37b2d 5335 else
6576bffe
AB		 5336 {
5337 func (stream, dis_style_text, ", ");
5338 func (stream, dis_style_register, "%s",
5339 arm_regnames[(given & 0xf00) >> 8]);
5340 }
8f06b2d8
PB		 5341 }
5342}
5343
73cd51e5
AV		 5344/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5345
78933a4a 5346static bool
73cd51e5
AV		 5347is_mve_okay_in_it (enum mve_instructions matched_insn)
5348{
c507f10b
AV		 5349 switch (matched_insn)
5350 {
5351 case MVE_VMOV_GP_TO_VEC_LANE:
5352 case MVE_VMOV2_VEC_LANE_TO_GP:
5353 case MVE_VMOV2_GP_TO_VEC_LANE:
5354 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5355 case MVE_LSLL:
5356 case MVE_LSLLI:
5357 case MVE_LSRL:
5358 case MVE_ASRL:
5359 case MVE_ASRLI:
5360 case MVE_SQRSHRL:
5361 case MVE_SQRSHR:
5362 case MVE_UQRSHL:
5363 case MVE_UQRSHLL:
5364 case MVE_UQSHL:
5365 case MVE_UQSHLL:
5366 case MVE_URSHRL:
5367 case MVE_URSHR:
5368 case MVE_SRSHRL:
5369 case MVE_SRSHR:
5370 case MVE_SQSHLL:
5371 case MVE_SQSHL:
78933a4a 5372 return true;
c507f10b 5373 default:
78933a4a 5374 return false;
c507f10b 5375 }
73cd51e5
AV		 5376}
5377
78933a4a 5378static bool
73cd51e5
AV		 5379is_mve_architecture (struct disassemble_info *info)
5380{
5381 struct arm_private_data *private_data = info->private_data;
5382 arm_feature_set allowed_arches = private_data->features;
5383
5384 arm_feature_set arm_ext_v8_1m_main
5385 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5386
5387 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5388 && !ARM_CPU_IS_ANY (allowed_arches))
78933a4a 5389 return true;
73cd51e5 5390 else
78933a4a 5391 return false;
73cd51e5
AV		 5392}
5393
78933a4a 5394static bool
143275ea
AV		 5395is_vpt_instruction (long given)
5396{
5397
5398 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5399 if ((given & 0x0040e000) == 0)
78933a4a 5400 return false;
143275ea
AV		 5401
5402 /* VPT floating point T1 variant. */
5403 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5404 /* VPT floating point T2 variant. */
5405 || ((given & 0xefb10f50) == 0xee310f40)
5406 /* VPT vector T1 variant. */
5407 || ((given & 0xff811f51) == 0xfe010f00)
5408 /* VPT vector T2 variant. */
5409 || ((given & 0xff811f51) == 0xfe010f01
5410 && ((given & 0x300000) != 0x300000))
5411 /* VPT vector T3 variant. */
5412 || ((given & 0xff811f50) == 0xfe011f00)
5413 /* VPT vector T4 variant. */
5414 || ((given & 0xff811f70) == 0xfe010f40)
5415 /* VPT vector T5 variant. */
5416 || ((given & 0xff811f70) == 0xfe010f60)
5417 /* VPT vector T6 variant. */
5418 || ((given & 0xff811f50) == 0xfe011f40)
5419 /* VPST vector T variant. */
5420 || ((given & 0xffbf1fff) == 0xfe310f4d))
78933a4a 5421 return true;
143275ea 5422 else
78933a4a 5423 return false;
143275ea
AV		 5424}
5425
73cd51e5
AV		 5426/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5427 and ending bitfield = END. END must be greater than START. */
5428
5429static unsigned long
5430arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5431{
5432 int bits = end - start;
5433
5434 if (bits < 0)
5435 abort ();
5436
5437 return ((given >> start) & ((2ul << bits) - 1));
5438}
5439
5440/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5441 START:END and START2:END2. END/END2 must be greater than
5442 START/START2. */
5443
5444static unsigned long
5445arm_decode_field_multiple (unsigned long given, unsigned int start,
5446 unsigned int end, unsigned int start2,
5447 unsigned int end2)
5448{
5449 int bits = end - start;
5450 int bits2 = end2 - start2;
5451 unsigned long value = 0;
5452 int width = 0;
5453
5454 if (bits2 < 0)
5455 abort ();
5456
5457 value = arm_decode_field (given, start, end);
5458 width += bits + 1;
5459
5460 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5461 return value;
5462}
5463
5464/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5465 This helps us decode instructions that change mnemonic depending on specific
5466 operand values/encodings. */
5467
78933a4a 5468static bool
73cd51e5
AV		 5469is_mve_encoding_conflict (unsigned long given,
5470 enum mve_instructions matched_insn)
5471{
143275ea
AV		 5472 switch (matched_insn)
5473 {
5474 case MVE_VPST:
5475 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5476 return true;
143275ea 5477 else
78933a4a 5478 return false;
143275ea
AV		 5479
5480 case MVE_VPT_FP_T1:
5481 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5482 return true;
143275ea
AV		 5483 if ((arm_decode_field (given, 12, 12) == 0)
5484 && (arm_decode_field (given, 0, 0) == 1))
78933a4a
AM		 5485 return true;
5486 return false;
143275ea
AV		 5487
5488 case MVE_VPT_FP_T2:
5489 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5490 return true;
143275ea 5491 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a
AM		 5492 return true;
5493 return false;
143275ea
AV		 5494
5495 case MVE_VPT_VEC_T1:
5496 case MVE_VPT_VEC_T2:
5497 case MVE_VPT_VEC_T3:
5498 case MVE_VPT_VEC_T4:
5499 case MVE_VPT_VEC_T5:
5500 case MVE_VPT_VEC_T6:
5501 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5502 return true;
143275ea 5503 if (arm_decode_field (given, 20, 21) == 3)
78933a4a
AM		 5504 return true;
5505 return false;
143275ea
AV		 5506
5507 case MVE_VCMP_FP_T1:
5508 if ((arm_decode_field (given, 12, 12) == 0)
5509 && (arm_decode_field (given, 0, 0) == 1))
78933a4a 5510 return true;
143275ea 5511 else
78933a4a 5512 return false;
143275ea
AV		 5513
5514 case MVE_VCMP_FP_T2:
5515 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5516 return true;
143275ea 5517 else
78933a4a 5518 return false;
143275ea 5519
14b456f2
AV		 5520 case MVE_VQADD_T2:
5521 case MVE_VQSUB_T2:
f49bb598
AV		 5522 case MVE_VMUL_VEC_T2:
5523 case MVE_VMULH:
5524 case MVE_VRMULH:
56858bea
AV		 5525 case MVE_VMLA:
5526 case MVE_VMAX:
5527 case MVE_VMIN:
e523f101 5528 case MVE_VBRSR:
66dcaa5d
AV		 5529 case MVE_VADD_VEC_T2:
5530 case MVE_VSUB_VEC_T2:
5531 case MVE_VABAV:
ed63aa17
AV		 5532 case MVE_VQRSHL_T1:
5533 case MVE_VQSHL_T4:
5534 case MVE_VRSHL_T1:
5535 case MVE_VSHL_T3:
897b9bbc
AV		 5536 case MVE_VCADD_VEC:
5537 case MVE_VHCADD:
1c8f2df8
AV		 5538 case MVE_VDDUP:
5539 case MVE_VIDUP:
d3b63143
AV		 5540 case MVE_VQRDMLADH:
5541 case MVE_VQDMLAH:
5542 case MVE_VQRDMLAH:
5543 case MVE_VQDMLASH:
5544 case MVE_VQRDMLASH:
5545 case MVE_VQDMLSDH:
5546 case MVE_VQRDMLSDH:
5547 case MVE_VQDMULH_T3:
5548 case MVE_VQRDMULH_T4:
5549 case MVE_VQDMLADH:
5550 case MVE_VMLAS:
14925797 5551 case MVE_VMULL_INT:
9743db03
AV		 5552 case MVE_VHADD_T2:
5553 case MVE_VHSUB_T2:
143275ea
AV		 5554 case MVE_VCMP_VEC_T1:
5555 case MVE_VCMP_VEC_T2:
5556 case MVE_VCMP_VEC_T3:
5557 case MVE_VCMP_VEC_T4:
5558 case MVE_VCMP_VEC_T5:
5559 case MVE_VCMP_VEC_T6:
5560 if (arm_decode_field (given, 20, 21) == 3)
78933a4a 5561 return true;
143275ea 5562 else
78933a4a 5563 return false;
143275ea 5564
04d54ace
AV		 5565 case MVE_VLD2:
5566 case MVE_VLD4:
5567 case MVE_VST2:
5568 case MVE_VST4:
5569 if (arm_decode_field (given, 7, 8) == 3)
78933a4a 5570 return true;
04d54ace 5571 else
78933a4a 5572 return false;
04d54ace 5573
aef6d006
AV		 5574 case MVE_VSTRB_T1:
5575 case MVE_VSTRH_T2:
5576 if ((arm_decode_field (given, 24, 24) == 0)
5577 && (arm_decode_field (given, 21, 21) == 0))
5578 {
78933a4a 5579 return true;
aef6d006
AV		 5580 }
5581 else if ((arm_decode_field (given, 7, 8) == 3))
78933a4a 5582 return true;
aef6d006 5583 else
78933a4a 5584 return false;
aef6d006 5585
e683cb41
AC		 5586 case MVE_VLDRB_T1:
5587 case MVE_VLDRH_T2:
5588 case MVE_VLDRW_T7:
aef6d006
AV		 5589 case MVE_VSTRB_T5:
5590 case MVE_VSTRH_T6:
5591 case MVE_VSTRW_T7:
5592 if ((arm_decode_field (given, 24, 24) == 0)
5593 && (arm_decode_field (given, 21, 21) == 0))
5594 {
78933a4a 5595 return true;
aef6d006
AV		 5596 }
5597 else
78933a4a 5598 return false;
aef6d006 5599
bf0b396d
AV		 5600 case MVE_VCVT_FP_FIX_VEC:
5601 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5602
c507f10b
AV		 5603 case MVE_VBIC_IMM:
5604 case MVE_VORR_IMM:
5605 {
5606 unsigned long cmode = arm_decode_field (given, 8, 11);
5607
5608 if ((cmode & 1) == 0)
78933a4a 5609 return true;
c507f10b 5610 else if ((cmode & 0xc) == 0xc)
78933a4a 5611 return true;
c507f10b 5612 else
78933a4a 5613 return false;
c507f10b
AV		 5614 }
5615
5616 case MVE_VMVN_IMM:
5617 {
5618 unsigned long cmode = arm_decode_field (given, 8, 11);
5619
ce760a76 5620 if (cmode == 0xe)
78933a4a 5621 return true;
ce760a76 5622 else if ((cmode & 0x9) == 1)
78933a4a 5623 return true;
ce760a76 5624 else if ((cmode & 0xd) == 9)
78933a4a 5625 return true;
c507f10b 5626 else
78933a4a 5627 return false;
c507f10b
AV		 5628 }
5629
5630 case MVE_VMOV_IMM_TO_VEC:
5631 if ((arm_decode_field (given, 5, 5) == 1)
5632 && (arm_decode_field (given, 8, 11) != 0xe))
78933a4a 5633 return true;
c507f10b 5634 else
78933a4a 5635 return false;
c507f10b 5636
14925797
AV		 5637 case MVE_VMOVL:
5638 {
5639 unsigned long size = arm_decode_field (given, 19, 20);
5640 if ((size == 0) || (size == 3))
78933a4a 5641 return true;
14925797 5642 else
78933a4a 5643 return false;
14925797
AV		 5644 }
5645
56858bea
AV		 5646 case MVE_VMAXA:
5647 case MVE_VMINA:
5648 case MVE_VMAXV:
5649 case MVE_VMAXAV:
5650 case MVE_VMINV:
5651 case MVE_VMINAV:
ed63aa17
AV		 5652 case MVE_VQRSHL_T2:
5653 case MVE_VQSHL_T1:
5654 case MVE_VRSHL_T2:
5655 case MVE_VSHL_T2:
5656 case MVE_VSHLL_T2:
d3b63143 5657 case MVE_VADDV:
14925797
AV		 5658 case MVE_VMOVN:
5659 case MVE_VQMOVUN:
5660 case MVE_VQMOVN:
5661 if (arm_decode_field (given, 18, 19) == 3)
78933a4a 5662 return true;
14925797 5663 else
78933a4a 5664 return false;
14925797 5665
d3b63143
AV		 5666 case MVE_VMLSLDAV:
5667 case MVE_VRMLSLDAVH:
5668 case MVE_VMLALDAV:
5669 case MVE_VADDLV:
5670 if (arm_decode_field (given, 20, 22) == 7)
78933a4a 5671 return true;
d3b63143 5672 else
78933a4a 5673 return false;
d3b63143
AV		 5674
5675 case MVE_VRMLALDAVH:
5676 if ((arm_decode_field (given, 20, 22) & 6) == 6)
78933a4a 5677 return true;
d3b63143 5678 else
78933a4a 5679 return false;
d3b63143 5680
1c8f2df8
AV		 5681 case MVE_VDWDUP:
5682 case MVE_VIWDUP:
5683 if ((arm_decode_field (given, 20, 21) == 3)
5684 || (arm_decode_field (given, 1, 3) == 7))
78933a4a 5685 return true;
1c8f2df8 5686 else
78933a4a 5687 return false;
1c8f2df8 5688
ed63aa17
AV		 5689
5690 case MVE_VSHLL_T1:
5691 if (arm_decode_field (given, 16, 18) == 0)
5692 {
5693 unsigned long sz = arm_decode_field (given, 19, 20);
5694
5695 if ((sz == 1) || (sz == 2))
78933a4a 5696 return true;
ed63aa17 5697 else
78933a4a 5698 return false;
ed63aa17
AV		 5699 }
5700 else
78933a4a 5701 return false;
ed63aa17
AV		 5702
5703 case MVE_VQSHL_T2:
5704 case MVE_VQSHLU_T3:
5705 case MVE_VRSHR:
5706 case MVE_VSHL_T1:
5707 case MVE_VSHR:
5708 case MVE_VSLI:
5709 case MVE_VSRI:
5710 if (arm_decode_field (given, 19, 21) == 0)
78933a4a 5711 return true;
ed63aa17 5712 else
78933a4a 5713 return false;
ed63aa17 5714
e523f101
AV		 5715 case MVE_VCTP:
5716 if (arm_decode_field (given, 16, 19) == 0xf)
78933a4a 5717 return true;
e523f101 5718 else
78933a4a 5719 return false;
e523f101 5720
23d00a41
SD		 5721 case MVE_ASRLI:
5722 case MVE_ASRL:
5723 case MVE_LSLLI:
5724 case MVE_LSLL:
5725 case MVE_LSRL:
5726 case MVE_SQRSHRL:
5727 case MVE_SQSHLL:
5728 case MVE_SRSHRL:
5729 case MVE_UQRSHLL:
5730 case MVE_UQSHLL:
5731 case MVE_URSHRL:
5732 if (arm_decode_field (given, 9, 11) == 0x7)
78933a4a 5733 return true;
23d00a41 5734 else
78933a4a 5735 return false;
23d00a41 5736
e39c1607
SD		 5737 case MVE_CSINC:
5738 case MVE_CSINV:
5739 {
5740 unsigned long rm, rn;
5741 rm = arm_decode_field (given, 0, 3);
5742 rn = arm_decode_field (given, 16, 19);
5743 /* CSET/CSETM. */
5744 if (rm == 0xf && rn == 0xf)
78933a4a 5745 return true;
e39c1607
SD		 5746 /* CINC/CINV. */
5747 else if (rn == rm && rn != 0xf)
78933a4a 5748 return true;
e39c1607
SD		 5749 }
5750 /* Fall through. */
5751 case MVE_CSEL:
5752 case MVE_CSNEG:
5753 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5754 return true;
e39c1607
SD		 5755 /* CNEG. */
5756 else if (matched_insn == MVE_CSNEG)
5757 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
78933a4a
AM		 5758 return true;
5759 return false;
e39c1607 5760
143275ea 5761 default:
66dcaa5d
AV		 5762 case MVE_VADD_FP_T1:
5763 case MVE_VADD_FP_T2:
5764 case MVE_VADD_VEC_T1:
78933a4a 5765 return false;
143275ea
AV		 5766
5767 }
73cd51e5
AV		 5768}
5769
aef6d006
AV		 5770static void
5771print_mve_vld_str_addr (struct disassemble_info *info,
5772 unsigned long given,
5773 enum mve_instructions matched_insn)
5774{
5775 void *stream = info->stream;
6576bffe 5776 fprintf_styled_ftype func = info->fprintf_styled_func;
aef6d006
AV		 5777
5778 unsigned long p, w, gpr, imm, add, mod_imm;
5779
5780 imm = arm_decode_field (given, 0, 6);
5781 mod_imm = imm;
5782
5783 switch (matched_insn)
5784 {
5785 case MVE_VLDRB_T1:
5786 case MVE_VSTRB_T1:
5787 gpr = arm_decode_field (given, 16, 18);
5788 break;
5789
5790 case MVE_VLDRH_T2:
5791 case MVE_VSTRH_T2:
5792 gpr = arm_decode_field (given, 16, 18);
5793 mod_imm = imm << 1;
5794 break;
5795
5796 case MVE_VLDRH_T6:
5797 case MVE_VSTRH_T6:
5798 gpr = arm_decode_field (given, 16, 19);
5799 mod_imm = imm << 1;
5800 break;
5801
5802 case MVE_VLDRW_T7:
5803 case MVE_VSTRW_T7:
5804 gpr = arm_decode_field (given, 16, 19);
5805 mod_imm = imm << 2;
5806 break;
5807
5808 case MVE_VLDRB_T5:
5809 case MVE_VSTRB_T5:
5810 gpr = arm_decode_field (given, 16, 19);
5811 break;
5812
5813 default:
5814 return;
5815 }
5816
5817 p = arm_decode_field (given, 24, 24);
5818 w = arm_decode_field (given, 21, 21);
5819
5820 add = arm_decode_field (given, 23, 23);
5821
5822 char * add_sub;
5823
5824 /* Don't print anything for '+' as it is implied. */
5825 if (add == 1)
5826 add_sub = "";
5827 else
5828 add_sub = "-";
5829
6576bffe 5830 func (stream, dis_style_text, "[");
4575eafb 5831 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
aef6d006
AV		 5832 if (p == 1)
5833 {
6576bffe
AB		 5834 func (stream, dis_style_text, ", ");
5835 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
aef6d006
AV		 5836 /* Offset mode. */
5837 if (w == 0)
6576bffe 5838 func (stream, dis_style_text, "]");
aef6d006
AV		 5839 /* Pre-indexed mode. */
5840 else
6576bffe 5841 func (stream, dis_style_text, "]!");
aef6d006
AV		 5842 }
5843 else if ((p == 0) && (w == 1))
6576bffe
AB		 5844 {
5845 /* Post-index mode. */
5846 func (stream, dis_style_text, "], ");
5847 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5848 }
aef6d006
AV		 5849}
5850
73cd51e5
AV		 5851/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5852 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5853 this encoding is undefined. */
5854
78933a4a 5855static bool
73cd51e5
AV		 5856is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5857 enum mve_undefined *undefined_code)
5858{
5859 *undefined_code = UNDEF_NONE;
5860
9743db03
AV		 5861 switch (matched_insn)
5862 {
5863 case MVE_VDUP:
5864 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5865 {
5866 *undefined_code = UNDEF_SIZE_3;
78933a4a 5867 return true;
9743db03
AV		 5868 }
5869 else
78933a4a 5870 return false;
9743db03 5871
14b456f2
AV		 5872 case MVE_VQADD_T1:
5873 case MVE_VQSUB_T1:
f49bb598 5874 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5875 case MVE_VABD_VEC:
5876 case MVE_VADD_VEC_T1:
5877 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5878 case MVE_VQDMULH_T1:
5879 case MVE_VQRDMULH_T2:
9743db03
AV		 5880 case MVE_VRHADD:
5881 case MVE_VHADD_T1:
5882 case MVE_VHSUB_T1:
5883 if (arm_decode_field (given, 20, 21) == 3)
5884 {
5885 *undefined_code = UNDEF_SIZE_3;
78933a4a 5886 return true;
9743db03
AV		 5887 }
5888 else
78933a4a 5889 return false;
9743db03 5890
aef6d006
AV		 5891 case MVE_VLDRB_T1:
5892 if (arm_decode_field (given, 7, 8) == 3)
5893 {
5894 *undefined_code = UNDEF_SIZE_3;
78933a4a 5895 return true;
aef6d006
AV		 5896 }
5897 else
78933a4a 5898 return false;
aef6d006
AV		 5899
5900 case MVE_VLDRH_T2:
5901 if (arm_decode_field (given, 7, 8) <= 1)
5902 {
5903 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 5904 return true;
aef6d006
AV		 5905 }
5906 else
78933a4a 5907 return false;
aef6d006
AV		 5908
5909 case MVE_VSTRB_T1:
5910 if ((arm_decode_field (given, 7, 8) == 0))
5911 {
5912 *undefined_code = UNDEF_SIZE_0;
78933a4a 5913 return true;
aef6d006
AV		 5914 }
5915 else
78933a4a 5916 return false;
aef6d006
AV		 5917
5918 case MVE_VSTRH_T2:
5919 if ((arm_decode_field (given, 7, 8) <= 1))
5920 {
5921 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 5922 return true;
aef6d006
AV		 5923 }
5924 else
78933a4a 5925 return false;
aef6d006 5926
ef1576a1
AV		 5927 case MVE_VLDRB_GATHER_T1:
5928 if (arm_decode_field (given, 7, 8) == 3)
5929 {
5930 *undefined_code = UNDEF_SIZE_3;
78933a4a 5931 return true;
ef1576a1
AV		 5932 }
5933 else if ((arm_decode_field (given, 28, 28) == 0)
5934 && (arm_decode_field (given, 7, 8) == 0))
5935 {
5936 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
78933a4a 5937 return true;
ef1576a1
AV		 5938 }
5939 else
78933a4a 5940 return false;
ef1576a1
AV		 5941
5942 case MVE_VLDRH_GATHER_T2:
5943 if (arm_decode_field (given, 7, 8) == 3)
5944 {
5945 *undefined_code = UNDEF_SIZE_3;
78933a4a 5946 return true;
ef1576a1
AV		 5947 }
5948 else if ((arm_decode_field (given, 28, 28) == 0)
5949 && (arm_decode_field (given, 7, 8) == 1))
5950 {
5951 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
78933a4a 5952 return true;
ef1576a1
AV		 5953 }
5954 else if (arm_decode_field (given, 7, 8) == 0)
5955 {
5956 *undefined_code = UNDEF_SIZE_0;
78933a4a 5957 return true;
ef1576a1
AV		 5958 }
5959 else
78933a4a 5960 return false;
ef1576a1
AV		 5961
5962 case MVE_VLDRW_GATHER_T3:
5963 if (arm_decode_field (given, 7, 8) != 2)
5964 {
5965 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 5966 return true;
ef1576a1
AV		 5967 }
5968 else if (arm_decode_field (given, 28, 28) == 0)
5969 {
5970 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 5971 return true;
ef1576a1
AV		 5972 }
5973 else
78933a4a 5974 return false;
ef1576a1
AV		 5975
5976 case MVE_VLDRD_GATHER_T4:
5977 if (arm_decode_field (given, 7, 8) != 3)
5978 {
5979 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 5980 return true;
ef1576a1
AV		 5981 }
5982 else if (arm_decode_field (given, 28, 28) == 0)
5983 {
5984 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 5985 return true;
ef1576a1
AV		 5986 }
5987 else
78933a4a 5988 return false;
ef1576a1
AV		 5989
5990 case MVE_VSTRB_SCATTER_T1:
5991 if (arm_decode_field (given, 7, 8) == 3)
5992 {
5993 *undefined_code = UNDEF_SIZE_3;
78933a4a 5994 return true;
ef1576a1
AV		 5995 }
5996 else
78933a4a 5997 return false;
ef1576a1
AV		 5998
5999 case MVE_VSTRH_SCATTER_T2:
6000 {
6001 unsigned long size = arm_decode_field (given, 7, 8);
6002 if (size == 3)
6003 {
6004 *undefined_code = UNDEF_SIZE_3;
78933a4a 6005 return true;
ef1576a1
AV		 6006 }
6007 else if (size == 0)
6008 {
6009 *undefined_code = UNDEF_SIZE_0;
78933a4a 6010 return true;
ef1576a1
AV		 6011 }
6012 else
78933a4a 6013 return false;
ef1576a1
AV		 6014 }
6015
6016 case MVE_VSTRW_SCATTER_T3:
6017 if (arm_decode_field (given, 7, 8) != 2)
6018 {
6019 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6020 return true;
ef1576a1
AV		 6021 }
6022 else
78933a4a 6023 return false;
ef1576a1
AV		 6024
6025 case MVE_VSTRD_SCATTER_T4:
6026 if (arm_decode_field (given, 7, 8) != 3)
6027 {
6028 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6029 return true;
ef1576a1
AV		 6030 }
6031 else
78933a4a 6032 return false;
ef1576a1 6033
bf0b396d
AV		 6034 case MVE_VCVT_FP_FIX_VEC:
6035 {
6036 unsigned long imm6 = arm_decode_field (given, 16, 21);
6037 if ((imm6 & 0x20) == 0)
6038 {
6039 *undefined_code = UNDEF_VCVT_IMM6;
78933a4a 6040 return true;
bf0b396d
AV		 6041 }
6042
6043 if ((arm_decode_field (given, 9, 9) == 0)
6044 && ((imm6 & 0x30) == 0x20))
6045 {
6046 *undefined_code = UNDEF_VCVT_FSI_IMM6;
78933a4a 6047 return true;
bf0b396d
AV		 6048 }
6049
78933a4a 6050 return false;
bf0b396d
AV		 6051 }
6052
f49bb598 6053 case MVE_VNEG_FP:
66dcaa5d 6054 case MVE_VABS_FP:
bf0b396d
AV		 6055 case MVE_VCVT_BETWEEN_FP_INT:
6056 case MVE_VCVT_FROM_FP_TO_INT:
6057 {
6058 unsigned long size = arm_decode_field (given, 18, 19);
6059 if (size == 0)
6060 {
6061 *undefined_code = UNDEF_SIZE_0;
78933a4a 6062 return true;
bf0b396d
AV		 6063 }
6064 else if (size == 3)
6065 {
6066 *undefined_code = UNDEF_SIZE_3;
78933a4a 6067 return true;
bf0b396d
AV		 6068 }
6069 else
78933a4a 6070 return false;
bf0b396d
AV		 6071 }
6072
c507f10b
AV		 6073 case MVE_VMOV_VEC_LANE_TO_GP:
6074 {
6075 unsigned long op1 = arm_decode_field (given, 21, 22);
6076 unsigned long op2 = arm_decode_field (given, 5, 6);
6077 unsigned long u = arm_decode_field (given, 23, 23);
6078
6079 if ((op2 == 0) && (u == 1))
6080 {
6081 if ((op1 == 0) || (op1 == 1))
6082 {
6083 *undefined_code = UNDEF_BAD_U_OP1_OP2;
78933a4a 6084 return true;
c507f10b
AV		 6085 }
6086 else
78933a4a 6087 return false;
c507f10b
AV		 6088 }
6089 else if (op2 == 2)
6090 {
6091 if ((op1 == 0) || (op1 == 1))
6092 {
6093 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6094 return true;
c507f10b
AV		 6095 }
6096 else
78933a4a 6097 return false;
c507f10b
AV		 6098 }
6099
78933a4a 6100 return false;
c507f10b
AV		 6101 }
6102
6103 case MVE_VMOV_GP_TO_VEC_LANE:
6104 if (arm_decode_field (given, 5, 6) == 2)
6105 {
6106 unsigned long op1 = arm_decode_field (given, 21, 22);
6107 if ((op1 == 0) || (op1 == 1))
6108 {
6109 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6110 return true;
c507f10b
AV		 6111 }
6112 else
78933a4a 6113 return false;
c507f10b
AV		 6114 }
6115 else
78933a4a 6116 return false;
c507f10b 6117
c4a23bf8
SP		 6118 case MVE_VMOV_VEC_TO_VEC:
6119 if ((arm_decode_field (given, 5, 5) == 1)
6120 || (arm_decode_field (given, 22, 22) == 1))
78933a4a
AM		 6121 return true;
6122 return false;
c4a23bf8 6123
c507f10b
AV		 6124 case MVE_VMOV_IMM_TO_VEC:
6125 if (arm_decode_field (given, 5, 5) == 0)
6126 {
6127 unsigned long cmode = arm_decode_field (given, 8, 11);
6128
6129 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6130 {
6131 *undefined_code = UNDEF_OP_0_BAD_CMODE;
78933a4a 6132 return true;
c507f10b
AV		 6133 }
6134 else
78933a4a 6135 return false;
c507f10b
AV		 6136 }
6137 else
78933a4a 6138 return false;
c507f10b 6139
ed63aa17 6140 case MVE_VSHLL_T2:
14925797
AV		 6141 case MVE_VMOVN:
6142 if (arm_decode_field (given, 18, 19) == 2)
6143 {
6144 *undefined_code = UNDEF_SIZE_2;
78933a4a 6145 return true;
14925797
AV		 6146 }
6147 else
78933a4a 6148 return false;
14925797 6149
d3b63143
AV		 6150 case MVE_VRMLALDAVH:
6151 case MVE_VMLADAV_T1:
6152 case MVE_VMLADAV_T2:
6153 case MVE_VMLALDAV:
6154 if ((arm_decode_field (given, 28, 28) == 1)
6155 && (arm_decode_field (given, 12, 12) == 1))
6156 {
6157 *undefined_code = UNDEF_XCHG_UNS;
78933a4a 6158 return true;
d3b63143
AV		 6159 }
6160 else
78933a4a 6161 return false;
d3b63143 6162
ed63aa17
AV		 6163 case MVE_VQSHRN:
6164 case MVE_VQSHRUN:
6165 case MVE_VSHLL_T1:
6166 case MVE_VSHRN:
6167 {
6168 unsigned long sz = arm_decode_field (given, 19, 20);
6169 if (sz == 1)
78933a4a 6170 return false;
ed63aa17 6171 else if ((sz & 2) == 2)
78933a4a 6172 return false;
ed63aa17
AV		 6173 else
6174 {
6175 *undefined_code = UNDEF_SIZE;
78933a4a 6176 return true;
ed63aa17
AV		 6177 }
6178 }
6179 break;
6180
6181 case MVE_VQSHL_T2:
6182 case MVE_VQSHLU_T3:
6183 case MVE_VRSHR:
6184 case MVE_VSHL_T1:
6185 case MVE_VSHR:
6186 case MVE_VSLI:
6187 case MVE_VSRI:
6188 {
6189 unsigned long sz = arm_decode_field (given, 19, 21);
6190 if ((sz & 7) == 1)
78933a4a 6191 return false;
ed63aa17 6192 else if ((sz & 6) == 2)
78933a4a 6193 return false;
ed63aa17 6194 else if ((sz & 4) == 4)
78933a4a 6195 return false;
ed63aa17
AV		 6196 else
6197 {
6198 *undefined_code = UNDEF_SIZE;
78933a4a 6199 return true;
ed63aa17
AV		 6200 }
6201 }
6202
6203 case MVE_VQRSHRN:
6204 case MVE_VQRSHRUN:
6205 if (arm_decode_field (given, 19, 20) == 0)
6206 {
6207 *undefined_code = UNDEF_SIZE_0;
78933a4a 6208 return true;
ed63aa17
AV		 6209 }
6210 else
78933a4a 6211 return false;
ed63aa17 6212
66dcaa5d
AV		 6213 case MVE_VABS_VEC:
6214 if (arm_decode_field (given, 18, 19) == 3)
6215 {
6216 *undefined_code = UNDEF_SIZE_3;
78933a4a 6217 return true;
66dcaa5d
AV		 6218 }
6219 else
78933a4a 6220 return false;
66dcaa5d 6221
14b456f2
AV		 6222 case MVE_VQNEG:
6223 case MVE_VQABS:
f49bb598 6224 case MVE_VNEG_VEC:
e523f101
AV		 6225 case MVE_VCLS:
6226 case MVE_VCLZ:
6227 if (arm_decode_field (given, 18, 19) == 3)
6228 {
6229 *undefined_code = UNDEF_SIZE_3;
78933a4a 6230 return true;
e523f101
AV		 6231 }
6232 else
78933a4a 6233 return false;
e523f101 6234
14b456f2
AV		 6235 case MVE_VREV16:
6236 if (arm_decode_field (given, 18, 19) == 0)
78933a4a 6237 return false;
14b456f2
AV		 6238 else
6239 {
6240 *undefined_code = UNDEF_SIZE_NOT_0;
78933a4a 6241 return true;
14b456f2
AV		 6242 }
6243
6244 case MVE_VREV32:
6245 {
6246 unsigned long size = arm_decode_field (given, 18, 19);
6247 if ((size & 2) == 2)
6248 {
6249 *undefined_code = UNDEF_SIZE_2;
78933a4a 6250 return true;
14b456f2
AV		 6251 }
6252 else
78933a4a 6253 return false;
14b456f2
AV		 6254 }
6255
6256 case MVE_VREV64:
6257 if (arm_decode_field (given, 18, 19) != 3)
78933a4a 6258 return false;
14b456f2
AV		 6259 else
6260 {
6261 *undefined_code = UNDEF_SIZE_3;
78933a4a 6262 return true;
14b456f2
AV		 6263 }
6264
9743db03 6265 default:
78933a4a 6266 return false;
9743db03 6267 }
73cd51e5
AV		 6268}
6269
6270/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6271 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6272 why this encoding is unpredictable. */
6273
78933a4a 6274static bool
73cd51e5
AV		 6275is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6276 enum mve_unpredictable *unpredictable_code)
6277{
6278 *unpredictable_code = UNPRED_NONE;
6279
143275ea
AV		 6280 switch (matched_insn)
6281 {
6282 case MVE_VCMP_FP_T2:
6283 case MVE_VPT_FP_T2:
6284 if ((arm_decode_field (given, 12, 12) == 0)
6285 && (arm_decode_field (given, 5, 5) == 1))
6286 {
6287 *unpredictable_code = UNPRED_FCA_0_FCB_1;
78933a4a 6288 return true;
143275ea
AV		 6289 }
6290 else
78933a4a 6291 return false;
73cd51e5 6292
143275ea
AV		 6293 case MVE_VPT_VEC_T4:
6294 case MVE_VPT_VEC_T5:
6295 case MVE_VPT_VEC_T6:
6296 case MVE_VCMP_VEC_T4:
6297 case MVE_VCMP_VEC_T5:
6298 case MVE_VCMP_VEC_T6:
6299 if (arm_decode_field (given, 0, 3) == 0xd)
6300 {
6301 *unpredictable_code = UNPRED_R13;
78933a4a 6302 return true;
143275ea
AV		 6303 }
6304 else
78933a4a 6305 return false;
c1e26897 6306
9743db03
AV		 6307 case MVE_VDUP:
6308 {
6309 unsigned long gpr = arm_decode_field (given, 12, 15);
6310 if (gpr == 0xd)
6311 {
6312 *unpredictable_code = UNPRED_R13;
78933a4a 6313 return true;
9743db03
AV		 6314 }
6315 else if (gpr == 0xf)
6316 {
6317 *unpredictable_code = UNPRED_R15;
78933a4a 6318 return true;
9743db03
AV		 6319 }
6320
78933a4a 6321 return false;
9743db03
AV		 6322 }
6323
14b456f2
AV		 6324 case MVE_VQADD_T2:
6325 case MVE_VQSUB_T2:
f49bb598
AV		 6326 case MVE_VMUL_FP_T2:
6327 case MVE_VMUL_VEC_T2:
56858bea 6328 case MVE_VMLA:
e523f101 6329 case MVE_VBRSR:
66dcaa5d
AV		 6330 case MVE_VADD_FP_T2:
6331 case MVE_VSUB_FP_T2:
6332 case MVE_VADD_VEC_T2:
6333 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6334 case MVE_VQRSHL_T2:
6335 case MVE_VQSHL_T1:
6336 case MVE_VRSHL_T2:
6337 case MVE_VSHL_T2:
6338 case MVE_VSHLC:
d3b63143
AV		 6339 case MVE_VQDMLAH:
6340 case MVE_VQRDMLAH:
6341 case MVE_VQDMLASH:
6342 case MVE_VQRDMLASH:
6343 case MVE_VQDMULH_T3:
6344 case MVE_VQRDMULH_T4:
6345 case MVE_VMLAS:
9743db03
AV		 6346 case MVE_VFMA_FP_SCALAR:
6347 case MVE_VFMAS_FP_SCALAR:
6348 case MVE_VHADD_T2:
6349 case MVE_VHSUB_T2:
6350 {
6351 unsigned long gpr = arm_decode_field (given, 0, 3);
6352 if (gpr == 0xd)
6353 {
6354 *unpredictable_code = UNPRED_R13;
78933a4a 6355 return true;
9743db03
AV		 6356 }
6357 else if (gpr == 0xf)
6358 {
6359 *unpredictable_code = UNPRED_R15;
78933a4a 6360 return true;
9743db03
AV		 6361 }
6362
78933a4a 6363 return false;
9743db03
AV		 6364 }
6365
04d54ace
AV		 6366 case MVE_VLD2:
6367 case MVE_VST2:
6368 {
6369 unsigned long rn = arm_decode_field (given, 16, 19);
6370
6371 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6372 {
6373 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6374 return true;
04d54ace
AV		 6375 }
6376
6377 if (rn == 0xf)
6378 {
6379 *unpredictable_code = UNPRED_R15;
78933a4a 6380 return true;
04d54ace
AV		 6381 }
6382
6383 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6384 {
6385 *unpredictable_code = UNPRED_Q_GT_6;
78933a4a 6386 return true;
04d54ace
AV		 6387 }
6388 else
78933a4a 6389 return false;
04d54ace
AV		 6390 }
6391
6392 case MVE_VLD4:
6393 case MVE_VST4:
6394 {
6395 unsigned long rn = arm_decode_field (given, 16, 19);
6396
6397 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6398 {
6399 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6400 return true;
04d54ace
AV		 6401 }
6402
6403 if (rn == 0xf)
6404 {
6405 *unpredictable_code = UNPRED_R15;
78933a4a 6406 return true;
04d54ace
AV		 6407 }
6408
6409 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6410 {
6411 *unpredictable_code = UNPRED_Q_GT_4;
78933a4a 6412 return true;
04d54ace
AV		 6413 }
6414 else
78933a4a 6415 return false;
04d54ace
AV		 6416 }
6417
aef6d006
AV		 6418 case MVE_VLDRB_T5:
6419 case MVE_VLDRH_T6:
6420 case MVE_VLDRW_T7:
6421 case MVE_VSTRB_T5:
6422 case MVE_VSTRH_T6:
6423 case MVE_VSTRW_T7:
6424 {
6425 unsigned long rn = arm_decode_field (given, 16, 19);
6426
6427 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6428 {
6429 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6430 return true;
aef6d006
AV		 6431 }
6432 else if (rn == 0xf)
6433 {
6434 *unpredictable_code = UNPRED_R15;
78933a4a 6435 return true;
aef6d006
AV		 6436 }
6437 else
78933a4a 6438 return false;
aef6d006
AV		 6439 }
6440
ef1576a1
AV		 6441 case MVE_VLDRB_GATHER_T1:
6442 if (arm_decode_field (given, 0, 0) == 1)
6443 {
6444 *unpredictable_code = UNPRED_OS;
78933a4a 6445 return true;
ef1576a1
AV		 6446 }
6447
6448 /* fall through. */
6449 /* To handle common code with T2-T4 variants. */
6450 case MVE_VLDRH_GATHER_T2:
6451 case MVE_VLDRW_GATHER_T3:
6452 case MVE_VLDRD_GATHER_T4:
6453 {
6454 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6455 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6456
6457 if (qd == qm)
6458 {
6459 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6460 return true;
ef1576a1
AV		 6461 }
6462
6463 if (arm_decode_field (given, 16, 19) == 0xf)
6464 {
6465 *unpredictable_code = UNPRED_R15;
78933a4a 6466 return true;
ef1576a1
AV		 6467 }
6468
78933a4a 6469 return false;
ef1576a1
AV		 6470 }
6471
6472 case MVE_VLDRW_GATHER_T5:
6473 case MVE_VLDRD_GATHER_T6:
6474 {
6475 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6476 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6477
6478 if (qd == qm)
6479 {
6480 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6481 return true;
ef1576a1
AV		 6482 }
6483 else
78933a4a 6484 return false;
ef1576a1
AV		 6485 }
6486
6487 case MVE_VSTRB_SCATTER_T1:
6488 if (arm_decode_field (given, 16, 19) == 0xf)
6489 {
6490 *unpredictable_code = UNPRED_R15;
78933a4a 6491 return true;
ef1576a1
AV		 6492 }
6493 else if (arm_decode_field (given, 0, 0) == 1)
6494 {
6495 *unpredictable_code = UNPRED_OS;
78933a4a 6496 return true;
ef1576a1
AV		 6497 }
6498 else
78933a4a 6499 return false;
ef1576a1
AV		 6500
6501 case MVE_VSTRH_SCATTER_T2:
6502 case MVE_VSTRW_SCATTER_T3:
6503 case MVE_VSTRD_SCATTER_T4:
6504 if (arm_decode_field (given, 16, 19) == 0xf)
6505 {
6506 *unpredictable_code = UNPRED_R15;
78933a4a 6507 return true;
ef1576a1
AV		 6508 }
6509 else
78933a4a 6510 return false;
ef1576a1 6511
c507f10b
AV		 6512 case MVE_VMOV2_VEC_LANE_TO_GP:
6513 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6514 case MVE_VCVT_BETWEEN_FP_INT:
6515 case MVE_VCVT_FROM_FP_TO_INT:
6516 {
6517 unsigned long rt = arm_decode_field (given, 0, 3);
6518 unsigned long rt2 = arm_decode_field (given, 16, 19);
6519
6520 if ((rt == 0xd) || (rt2 == 0xd))
6521 {
6522 *unpredictable_code = UNPRED_R13;
78933a4a 6523 return true;
bf0b396d
AV		 6524 }
6525 else if ((rt == 0xf) || (rt2 == 0xf))
6526 {
6527 *unpredictable_code = UNPRED_R15;
78933a4a 6528 return true;
bf0b396d 6529 }
e683cb41 6530 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
bf0b396d
AV		 6531 {
6532 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
78933a4a 6533 return true;
bf0b396d
AV		 6534 }
6535
78933a4a 6536 return false;
bf0b396d
AV		 6537 }
6538
56858bea
AV		 6539 case MVE_VMAXV:
6540 case MVE_VMAXAV:
6541 case MVE_VMAXNMV_FP:
6542 case MVE_VMAXNMAV_FP:
6543 case MVE_VMINNMV_FP:
6544 case MVE_VMINNMAV_FP:
6545 case MVE_VMINV:
6546 case MVE_VMINAV:
66dcaa5d 6547 case MVE_VABAV:
c507f10b
AV		 6548 case MVE_VMOV_HFP_TO_GP:
6549 case MVE_VMOV_GP_TO_VEC_LANE:
6550 case MVE_VMOV_VEC_LANE_TO_GP:
6551 {
6552 unsigned long rda = arm_decode_field (given, 12, 15);
6553 if (rda == 0xd)
6554 {
6555 *unpredictable_code = UNPRED_R13;
78933a4a 6556 return true;
c507f10b
AV		 6557 }
6558 else if (rda == 0xf)
6559 {
6560 *unpredictable_code = UNPRED_R15;
78933a4a 6561 return true;
c507f10b
AV		 6562 }
6563
78933a4a 6564 return false;
c507f10b
AV		 6565 }
6566
14925797
AV		 6567 case MVE_VMULL_INT:
6568 {
6569 unsigned long Qd;
6570 unsigned long Qm;
6571 unsigned long Qn;
6572
6573 if (arm_decode_field (given, 20, 21) == 2)
6574 {
6575 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6576 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6577 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6578
6579 if ((Qd == Qn) || (Qd == Qm))
6580 {
6581 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6582 return true;
14925797
AV		 6583 }
6584 else
78933a4a 6585 return false;
14925797
AV		 6586 }
6587 else
78933a4a 6588 return false;
14925797
AV		 6589 }
6590
897b9bbc 6591 case MVE_VCMUL_FP:
14925797
AV		 6592 case MVE_VQDMULL_T1:
6593 {
6594 unsigned long Qd;
6595 unsigned long Qm;
6596 unsigned long Qn;
6597
6598 if (arm_decode_field (given, 28, 28) == 1)
6599 {
6600 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6601 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6602 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6603
6604 if ((Qd == Qn) || (Qd == Qm))
6605 {
6606 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6607 return true;
14925797
AV		 6608 }
6609 else
78933a4a 6610 return false;
14925797
AV		 6611 }
6612 else
78933a4a 6613 return false;
14925797
AV		 6614 }
6615
6616 case MVE_VQDMULL_T2:
6617 {
6618 unsigned long gpr = arm_decode_field (given, 0, 3);
6619 if (gpr == 0xd)
6620 {
6621 *unpredictable_code = UNPRED_R13;
78933a4a 6622 return true;
14925797
AV		 6623 }
6624 else if (gpr == 0xf)
6625 {
6626 *unpredictable_code = UNPRED_R15;
78933a4a 6627 return true;
14925797
AV		 6628 }
6629
6630 if (arm_decode_field (given, 28, 28) == 1)
6631 {
6632 unsigned long Qd
6633 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6634 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6635
a9d96ab9 6636 if (Qd == Qn)
14925797
AV		 6637 {
6638 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6639 return true;
14925797
AV		 6640 }
6641 else
78933a4a 6642 return false;
14925797
AV		 6643 }
6644
78933a4a 6645 return false;
14925797
AV		 6646 }
6647
d3b63143
AV		 6648 case MVE_VMLSLDAV:
6649 case MVE_VRMLSLDAVH:
6650 case MVE_VMLALDAV:
6651 case MVE_VADDLV:
6652 if (arm_decode_field (given, 20, 22) == 6)
6653 {
6654 *unpredictable_code = UNPRED_R13;
78933a4a 6655 return true;
d3b63143
AV		 6656 }
6657 else
78933a4a 6658 return false;
d3b63143 6659
1c8f2df8
AV		 6660 case MVE_VDWDUP:
6661 case MVE_VIWDUP:
6662 if (arm_decode_field (given, 1, 3) == 6)
6663 {
6664 *unpredictable_code = UNPRED_R13;
78933a4a 6665 return true;
1c8f2df8
AV		 6666 }
6667 else
78933a4a 6668 return false;
1c8f2df8 6669
897b9bbc
AV		 6670 case MVE_VCADD_VEC:
6671 case MVE_VHCADD:
6672 {
6673 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6674 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6675 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6676 {
6677 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6678 return true;
897b9bbc
AV		 6679 }
6680 else
78933a4a 6681 return false;
897b9bbc
AV		 6682 }
6683
6684 case MVE_VCADD_FP:
6685 {
6686 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6687 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6688 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6689 {
6690 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6691 return true;
897b9bbc
AV		 6692 }
6693 else
78933a4a 6694 return false;
897b9bbc
AV		 6695 }
6696
6697 case MVE_VCMLA_FP:
6698 {
6699 unsigned long Qda;
6700 unsigned long Qm;
6701 unsigned long Qn;
6702
6703 if (arm_decode_field (given, 20, 20) == 1)
6704 {
6705 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6706 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6707 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6708
6709 if ((Qda == Qn) || (Qda == Qm))
6710 {
6711 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6712 return true;
897b9bbc
AV		 6713 }
6714 else
78933a4a 6715 return false;
897b9bbc
AV		 6716 }
6717 else
78933a4a 6718 return false;
897b9bbc
AV		 6719
6720 }
6721
e523f101
AV		 6722 case MVE_VCTP:
6723 if (arm_decode_field (given, 16, 19) == 0xd)
6724 {
6725 *unpredictable_code = UNPRED_R13;
78933a4a 6726 return true;
e523f101
AV		 6727 }
6728 else
78933a4a 6729 return false;
e523f101 6730
14b456f2
AV		 6731 case MVE_VREV64:
6732 {
6733 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6734 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6735
6736 if (qd == qm)
6737 {
6738 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6739 return true;
14b456f2
AV		 6740 }
6741 else
78933a4a 6742 return false;
14b456f2
AV		 6743 }
6744
23d00a41
SD		 6745 case MVE_LSLL:
6746 case MVE_LSLLI:
6747 case MVE_LSRL:
6748 case MVE_ASRL:
6749 case MVE_ASRLI:
6750 case MVE_UQSHLL:
6751 case MVE_UQRSHLL:
6752 case MVE_URSHRL:
6753 case MVE_SRSHRL:
6754 case MVE_SQSHLL:
6755 case MVE_SQRSHRL:
6756 {
6757 unsigned long gpr = arm_decode_field (given, 9, 11);
6758 gpr = ((gpr << 1) | 1);
6759 if (gpr == 0xd)
6760 {
6761 *unpredictable_code = UNPRED_R13;
78933a4a 6762 return true;
23d00a41
SD		 6763 }
6764 else if (gpr == 0xf)
6765 {
6766 *unpredictable_code = UNPRED_R15;
78933a4a 6767 return true;
23d00a41
SD		 6768 }
6769
78933a4a 6770 return false;
23d00a41
SD		 6771 }
6772
143275ea 6773 default:
78933a4a 6774 return false;
143275ea
AV		 6775 }
6776}
c1e26897 6777
c507f10b
AV		 6778static void
6779print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6780{
6781 unsigned long op1 = arm_decode_field (given, 21, 22);
6782 unsigned long op2 = arm_decode_field (given, 5, 6);
6783 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6784 unsigned long index_operand, esize, targetBeat, idx;
c507f10b 6785 void *stream = info->stream;
6576bffe 6786 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 6787
6788 if ((op1 & 0x2) == 0x2)
6789 {
43dd7626 6790 index_operand = op2;
c507f10b
AV		 6791 esize = 8;
6792 }
6793 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6794 {
43dd7626 6795 index_operand = op2 >> 1;
c507f10b
AV		 6796 esize = 16;
6797 }
6798 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6799 {
43dd7626 6800 index_operand = 0;
c507f10b
AV		 6801 esize = 32;
6802 }
6803 else
6804 {
6576bffe 6805 func (stream, dis_style_text, "<undefined index>");
c507f10b
AV		 6806 return;
6807 }
6808
6809 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6810 idx = index_operand + targetBeat * (32/esize);
c507f10b 6811
6576bffe 6812 func (stream, dis_style_immediate, "%lu", idx);
c507f10b
AV		 6813}
6814
6815/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6816 in length and integer of floating-point type. */
6817static void
6818print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6819 unsigned int ibit_loc, const struct mopcode32 *insn)
6820{
6821 int bits = 0;
6822 int cmode = (given >> 8) & 0xf;
6823 int op = (given >> 5) & 0x1;
6824 unsigned long value = 0, hival = 0;
6825 unsigned shift;
6826 int size = 0;
6827 int isfloat = 0;
6828 void *stream = info->stream;
6576bffe 6829 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 6830
6831 /* On Neon the 'i' bit is at bit 24, on mve it is
6832 at bit 28. */
6833 bits |= ((given >> ibit_loc) & 1) << 7;
6834 bits |= ((given >> 16) & 7) << 4;
6835 bits |= ((given >> 0) & 15) << 0;
6836
6837 if (cmode < 8)
6838 {
6839 shift = (cmode >> 1) & 3;
6840 value = (unsigned long) bits << (8 * shift);
6841 size = 32;
6842 }
6843 else if (cmode < 12)
6844 {
6845 shift = (cmode >> 1) & 1;
6846 value = (unsigned long) bits << (8 * shift);
6847 size = 16;
6848 }
6849 else if (cmode < 14)
6850 {
6851 shift = (cmode & 1) + 1;
6852 value = (unsigned long) bits << (8 * shift);
6853 value |= (1ul << (8 * shift)) - 1;
6854 size = 32;
6855 }
6856 else if (cmode == 14)
6857 {
6858 if (op)
6859 {
6860 /* Bit replication into bytes. */
6861 int ix;
6862 unsigned long mask;
6863
6864 value = 0;
6865 hival = 0;
6866 for (ix = 7; ix >= 0; ix--)
6867 {
6868 mask = ((bits >> ix) & 1) ? 0xff : 0;
6869 if (ix <= 3)
6870 value = (value << 8) | mask;
6871 else
6872 hival = (hival << 8) | mask;
6873 }
6874 size = 64;
6875 }
6876 else
6877 {
6878 /* Byte replication. */
6879 value = (unsigned long) bits;
6880 size = 8;
6881 }
6882 }
6883 else if (!op)
6884 {
6885 /* Floating point encoding. */
6886 int tmp;
6887
6888 value = (unsigned long) (bits & 0x7f) << 19;
6889 value |= (unsigned long) (bits & 0x80) << 24;
6890 tmp = bits & 0x40 ? 0x3c : 0x40;
6891 value |= (unsigned long) tmp << 24;
6892 size = 32;
6893 isfloat = 1;
6894 }
6895 else
6896 {
6576bffe 6897 func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
c507f10b
AV		 6898 bits, cmode, op);
6899 size = 32;
6900 return;
6901 }
6902
279edac5
AM		 6903 /* printU determines whether the immediate value should be printed as
6904 unsigned. */
c507f10b
AV		 6905 unsigned printU = 0;
6906 switch (insn->mve_op)
6907 {
6908 default:
6909 break;
279edac5 6910 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 6911 case MVE_VBIC_IMM:
6912 case MVE_VORR_IMM:
6913 case MVE_VMVN_IMM:
6914 case MVE_VMOV_IMM_TO_VEC:
6915 printU = 1;
6916 break;
6917 }
6918 switch (size)
6919 {
6920 case 8:
6576bffe
AB		 6921 func (stream, dis_style_immediate, "#%ld", value);
6922 func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
c507f10b
AV		 6923 break;
6924
6925 case 16:
6576bffe
AB		 6926 func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
6927 func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
c507f10b
AV		 6928 break;
6929
6930 case 32:
6931 if (isfloat)
6932 {
6933 unsigned char valbytes[4];
6934 double fvalue;
6935
6936 /* Do this a byte at a time so we don't have to
6937 worry about the host's endianness. */
6938 valbytes[0] = value & 0xff;
6939 valbytes[1] = (value >> 8) & 0xff;
6940 valbytes[2] = (value >> 16) & 0xff;
6941 valbytes[3] = (value >> 24) & 0xff;
6942
6943 floatformat_to_double
6944 (& floatformat_ieee_single_little, valbytes,
6945 & fvalue);
6946
6576bffe
AB		 6947 func (stream, dis_style_immediate, "#%.7g", fvalue);
6948 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
c507f10b
AV		 6949 }
6950 else
6576bffe
AB		 6951 {
6952 func (stream, dis_style_immediate,
6953 printU ? "#%lu" : "#%ld",
6954 (long) (((value & 0x80000000L) != 0)
6955 && !printU
6956 ? value | ~0xffffffffL : value));
6957 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6958 }
c507f10b
AV		 6959 break;
6960
6961 case 64:
6576bffe 6962 func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
c507f10b
AV		 6963 break;
6964
6965 default:
6966 abort ();
6967 }
6968
6969}
6970
73cd51e5
AV		 6971static void
6972print_mve_undefined (struct disassemble_info *info,
6973 enum mve_undefined undefined_code)
6974{
6975 void *stream = info->stream;
6576bffe 6976 fprintf_styled_ftype func = info->fprintf_styled_func;
d8521074
AB		 6977 /* Initialize REASON to avoid compiler warning about uninitialized
6978 usage, though such usage should be impossible. */
6979 const char *reason = "??";
73cd51e5
AV		 6980
6981 switch (undefined_code)
6982 {
ed63aa17 6983 case UNDEF_SIZE:
6576bffe 6984 reason = "illegal size";
ed63aa17
AV		 6985 break;
6986
aef6d006 6987 case UNDEF_SIZE_0:
6576bffe 6988 reason = "size equals zero";
aef6d006
AV		 6989 break;
6990
c507f10b 6991 case UNDEF_SIZE_2:
6576bffe 6992 reason = "size equals two";
c507f10b
AV		 6993 break;
6994
9743db03 6995 case UNDEF_SIZE_3:
6576bffe 6996 reason = "size equals three";
9743db03
AV		 6997 break;
6998
aef6d006 6999 case UNDEF_SIZE_LE_1:
6576bffe 7000 reason = "size <= 1";
aef6d006
AV		 7001 break;
7002
14b456f2 7003 case UNDEF_SIZE_NOT_0:
6576bffe 7004 reason = "size not equal to 0";
14b456f2
AV		 7005 break;
7006
ef1576a1 7007 case UNDEF_SIZE_NOT_2:
6576bffe 7008 reason = "size not equal to 2";
ef1576a1
AV		 7009 break;
7010
7011 case UNDEF_SIZE_NOT_3:
6576bffe 7012 reason = "size not equal to 3";
ef1576a1
AV		 7013 break;
7014
7015 case UNDEF_NOT_UNS_SIZE_0:
6576bffe 7016 reason = "not unsigned and size = zero";
ef1576a1
AV		 7017 break;
7018
7019 case UNDEF_NOT_UNS_SIZE_1:
6576bffe 7020 reason = "not unsigned and size = one";
ef1576a1
AV		 7021 break;
7022
7023 case UNDEF_NOT_UNSIGNED:
6576bffe 7024 reason = "not unsigned";
ef1576a1
AV		 7025 break;
7026
bf0b396d 7027 case UNDEF_VCVT_IMM6:
6576bffe 7028 reason = "invalid imm6";
bf0b396d
AV		 7029 break;
7030
7031 case UNDEF_VCVT_FSI_IMM6:
6576bffe 7032 reason = "fsi = 0 and invalid imm6";
bf0b396d
AV		 7033 break;
7034
c507f10b 7035 case UNDEF_BAD_OP1_OP2:
6576bffe 7036 reason = "bad size with op2 = 2 and op1 = 0 or 1";
c507f10b
AV		 7037 break;
7038
7039 case UNDEF_BAD_U_OP1_OP2:
6576bffe 7040 reason = "unsigned with op2 = 0 and op1 = 0 or 1";
c507f10b
AV		 7041 break;
7042
7043 case UNDEF_OP_0_BAD_CMODE:
6576bffe 7044 reason = "op field equal 0 and bad cmode";
c507f10b
AV		 7045 break;
7046
d3b63143 7047 case UNDEF_XCHG_UNS:
6576bffe 7048 reason = "exchange and unsigned together";
d3b63143
AV		 7049 break;
7050
73cd51e5 7051 case UNDEF_NONE:
6576bffe 7052 reason = "";
73cd51e5
AV		 7053 break;
7054 }
7055
6576bffe 7056 func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
73cd51e5
AV		 7057}
7058
7059static void
7060print_mve_unpredictable (struct disassemble_info *info,
7061 enum mve_unpredictable unpredict_code)
7062{
7063 void *stream = info->stream;
6576bffe 7064 fprintf_styled_ftype func = info->fprintf_styled_func;
2df82cd4
AB		 7065 /* Initialize REASON to avoid compiler warning about uninitialized
7066 usage, though such usage should be impossible. */
7067 const char *reason = "??";
73cd51e5
AV		 7068
7069 switch (unpredict_code)
7070 {
7071 case UNPRED_IT_BLOCK:
6576bffe 7072 reason = "mve instruction in it block";
73cd51e5
AV		 7073 break;
7074
143275ea 7075 case UNPRED_FCA_0_FCB_1:
6576bffe 7076 reason = "condition bits, fca = 0 and fcb = 1";
143275ea
AV		 7077 break;
7078
7079 case UNPRED_R13:
6576bffe 7080 reason = "use of r13 (sp)";
143275ea
AV		 7081 break;
7082
9743db03 7083 case UNPRED_R15:
6576bffe 7084 reason = "use of r15 (pc)";
9743db03
AV		 7085 break;
7086
04d54ace 7087 case UNPRED_Q_GT_4:
6576bffe 7088 reason = "start register block > r4";
04d54ace
AV		 7089 break;
7090
7091 case UNPRED_Q_GT_6:
6576bffe 7092 reason = "start register block > r6";
04d54ace
AV		 7093 break;
7094
7095 case UNPRED_R13_AND_WB:
6576bffe 7096 reason = "use of r13 and write back";
04d54ace
AV		 7097 break;
7098
ef1576a1 7099 case UNPRED_Q_REGS_EQUAL:
6576bffe 7100 reason = "same vector register used for destination and other operand";
ef1576a1
AV		 7101 break;
7102
7103 case UNPRED_OS:
6576bffe 7104 reason = "use of offset scaled";
ef1576a1
AV		 7105 break;
7106
bf0b396d 7107 case UNPRED_GP_REGS_EQUAL:
6576bffe 7108 reason = "same general-purpose register used for both operands";
bf0b396d
AV		 7109 break;
7110
c507f10b 7111 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6576bffe 7112 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7113 break;
7114
7115 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6576bffe 7116 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7117 break;
7118
73cd51e5 7119 case UNPRED_NONE:
6576bffe 7120 reason = "";
73cd51e5
AV		 7121 break;
7122 }
6576bffe
AB		 7123
7124 func (stream, dis_style_comment_start, "%s: %s",
7125 UNPREDICTABLE_INSTRUCTION, reason);
73cd51e5
AV		 7126}
7127
04d54ace
AV		 7128/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7129
7130static void
7131print_mve_register_blocks (struct disassemble_info *info,
7132 unsigned long given,
7133 enum mve_instructions matched_insn)
7134{
7135 void *stream = info->stream;
6576bffe 7136 fprintf_styled_ftype func = info->fprintf_styled_func;
04d54ace
AV		 7137
7138 unsigned long q_reg_start = arm_decode_field_multiple (given,
7139 13, 15,
7140 22, 22);
7141 switch (matched_insn)
7142 {
7143 case MVE_VLD2:
7144 case MVE_VST2:
7145 if (q_reg_start <= 6)
6576bffe
AB		 7146 {
7147 func (stream, dis_style_text, "{");
7148 func (stream, dis_style_register, "q%ld", q_reg_start);
7149 func (stream, dis_style_text, ", ");
7150 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7151 func (stream, dis_style_text, "}");
7152 }
04d54ace 7153 else
6576bffe 7154 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7155 break;
7156
7157 case MVE_VLD4:
7158 case MVE_VST4:
7159 if (q_reg_start <= 4)
6576bffe
AB		 7160 {
7161 func (stream, dis_style_text, "{");
7162 func (stream, dis_style_register, "q%ld", q_reg_start);
7163 func (stream, dis_style_text, ", ");
7164 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7165 func (stream, dis_style_text, ", ");
7166 func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7167 func (stream, dis_style_text, ", ");
7168 func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7169 func (stream, dis_style_text, "}");
7170 }
04d54ace 7171 else
6576bffe 7172 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7173 break;
7174
7175 default:
7176 break;
7177 }
7178}
7179
bf0b396d
AV		 7180static void
7181print_mve_rounding_mode (struct disassemble_info *info,
7182 unsigned long given,
7183 enum mve_instructions matched_insn)
7184{
7185 void *stream = info->stream;
6576bffe 7186 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7187
7188 switch (matched_insn)
7189 {
7190 case MVE_VCVT_FROM_FP_TO_INT:
7191 {
7192 switch (arm_decode_field (given, 8, 9))
7193 {
7194 case 0:
6576bffe 7195 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7196 break;
7197
7198 case 1:
6576bffe 7199 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7200 break;
7201
7202 case 2:
6576bffe 7203 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7204 break;
7205
7206 case 3:
6576bffe 7207 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7208 break;
7209
7210 default:
7211 break;
7212 }
7213 }
7214 break;
7215
7216 case MVE_VRINT_FP:
7217 {
7218 switch (arm_decode_field (given, 7, 9))
7219 {
7220 case 0:
6576bffe 7221 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7222 break;
7223
7224 case 1:
6576bffe 7225 func (stream, dis_style_mnemonic, "x");
bf0b396d
AV		 7226 break;
7227
7228 case 2:
6576bffe 7229 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7230 break;
7231
7232 case 3:
6576bffe 7233 func (stream, dis_style_mnemonic, "z");
bf0b396d
AV		 7234 break;
7235
7236 case 5:
6576bffe 7237 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7238 break;
7239
7240 case 7:
6576bffe 7241 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7242
7243 case 4:
7244 case 6:
7245 default:
7246 break;
7247 }
7248 }
7249 break;
7250
7251 default:
7252 break;
7253 }
7254}
7255
7256static void
7257print_mve_vcvt_size (struct disassemble_info *info,
7258 unsigned long given,
7259 enum mve_instructions matched_insn)
7260{
7261 unsigned long mode = 0;
7262 void *stream = info->stream;
6576bffe 7263 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7264
7265 switch (matched_insn)
7266 {
7267 case MVE_VCVT_FP_FIX_VEC:
7268 {
7269 mode = (((given & 0x200) >> 7)
7270 | ((given & 0x10000000) >> 27)
7271 | ((given & 0x100) >> 8));
7272
7273 switch (mode)
7274 {
7275 case 0:
6576bffe 7276 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7277 break;
7278
7279 case 1:
6576bffe 7280 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7281 break;
7282
7283 case 2:
6576bffe 7284 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7285 break;
7286
7287 case 3:
6576bffe 7288 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7289 break;
7290
7291 case 4:
6576bffe 7292 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7293 break;
7294
7295 case 5:
6576bffe 7296 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7297 break;
7298
7299 case 6:
6576bffe 7300 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7301 break;
7302
7303 case 7:
6576bffe 7304 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7305 break;
7306
7307 default:
7308 break;
7309 }
7310 break;
7311 }
7312 case MVE_VCVT_BETWEEN_FP_INT:
7313 {
7314 unsigned long size = arm_decode_field (given, 18, 19);
7315 unsigned long op = arm_decode_field (given, 7, 8);
7316
7317 if (size == 1)
7318 {
7319 switch (op)
7320 {
7321 case 0:
6576bffe 7322 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7323 break;
7324
7325 case 1:
6576bffe 7326 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7327 break;
7328
7329 case 2:
6576bffe 7330 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7331 break;
7332
7333 case 3:
6576bffe 7334 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7335 break;
7336
7337 default:
7338 break;
7339 }
7340 }
7341 else if (size == 2)
7342 {
7343 switch (op)
7344 {
7345 case 0:
6576bffe 7346 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7347 break;
7348
7349 case 1:
6576bffe 7350 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7351 break;
7352
7353 case 2:
6576bffe 7354 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7355 break;
7356
7357 case 3:
6576bffe 7358 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7359 break;
7360 }
7361 }
7362 }
7363 break;
7364
7365 case MVE_VCVT_FP_HALF_FP:
7366 {
7367 unsigned long op = arm_decode_field (given, 28, 28);
7368 if (op == 0)
6576bffe 7369 func (stream, dis_style_mnemonic, "f16.f32");
bf0b396d 7370 else if (op == 1)
6576bffe 7371 func (stream, dis_style_mnemonic, "f32.f16");
bf0b396d
AV		 7372 }
7373 break;
7374
7375 case MVE_VCVT_FROM_FP_TO_INT:
7376 {
7377 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7378
7379 switch (size)
7380 {
7381 case 2:
6576bffe 7382 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7383 break;
7384
7385 case 3:
6576bffe 7386 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7387 break;
7388
7389 case 4:
6576bffe 7390 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7391 break;
7392
7393 case 5:
6576bffe 7394 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7395 break;
7396
7397 default:
7398 break;
7399 }
7400 }
7401 break;
7402
7403 default:
7404 break;
7405 }
7406}
7407
897b9bbc
AV		 7408static void
7409print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7410 unsigned long rot_width)
7411{
7412 void *stream = info->stream;
6576bffe 7413 fprintf_styled_ftype func = info->fprintf_styled_func;
897b9bbc
AV		 7414
7415 if (rot_width == 1)
7416 {
7417 switch (rot)
7418 {
7419 case 0:
6576bffe 7420 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7421 break;
7422 case 1:
6576bffe 7423 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7424 break;
7425 default:
7426 break;
7427 }
7428 }
7429 else if (rot_width == 2)
7430 {
7431 switch (rot)
7432 {
7433 case 0:
6576bffe 7434 func (stream, dis_style_immediate, "0");
897b9bbc
AV		 7435 break;
7436 case 1:
6576bffe 7437 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7438 break;
7439 case 2:
6576bffe 7440 func (stream, dis_style_immediate, "180");
897b9bbc
AV		 7441 break;
7442 case 3:
6576bffe 7443 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7444 break;
7445 default:
7446 break;
7447 }
7448 }
7449}
7450
143275ea
AV		 7451static void
7452print_instruction_predicate (struct disassemble_info *info)
7453{
7454 void *stream = info->stream;
6576bffe 7455 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7456
7457 if (vpt_block_state.next_pred_state == PRED_THEN)
6576bffe 7458 func (stream, dis_style_mnemonic, "t");
143275ea 7459 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6576bffe 7460 func (stream, dis_style_mnemonic, "e");
143275ea
AV		 7461}
7462
7463static void
7464print_mve_size (struct disassemble_info *info,
7465 unsigned long size,
7466 enum mve_instructions matched_insn)
7467{
7468 void *stream = info->stream;
6576bffe 7469 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7470
7471 switch (matched_insn)
7472 {
66dcaa5d
AV		 7473 case MVE_VABAV:
7474 case MVE_VABD_VEC:
7475 case MVE_VABS_FP:
7476 case MVE_VABS_VEC:
7477 case MVE_VADD_VEC_T1:
7478 case MVE_VADD_VEC_T2:
d3b63143 7479 case MVE_VADDV:
e523f101 7480 case MVE_VBRSR:
897b9bbc 7481 case MVE_VCADD_VEC:
e523f101
AV		 7482 case MVE_VCLS:
7483 case MVE_VCLZ:
143275ea
AV		 7484 case MVE_VCMP_VEC_T1:
7485 case MVE_VCMP_VEC_T2:
7486 case MVE_VCMP_VEC_T3:
7487 case MVE_VCMP_VEC_T4:
7488 case MVE_VCMP_VEC_T5:
7489 case MVE_VCMP_VEC_T6:
e523f101 7490 case MVE_VCTP:
1c8f2df8
AV		 7491 case MVE_VDDUP:
7492 case MVE_VDWDUP:
9743db03
AV		 7493 case MVE_VHADD_T1:
7494 case MVE_VHADD_T2:
897b9bbc 7495 case MVE_VHCADD:
9743db03
AV		 7496 case MVE_VHSUB_T1:
7497 case MVE_VHSUB_T2:
1c8f2df8
AV		 7498 case MVE_VIDUP:
7499 case MVE_VIWDUP:
04d54ace
AV		 7500 case MVE_VLD2:
7501 case MVE_VLD4:
ef1576a1
AV		 7502 case MVE_VLDRB_GATHER_T1:
7503 case MVE_VLDRH_GATHER_T2:
7504 case MVE_VLDRW_GATHER_T3:
7505 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7506 case MVE_VLDRB_T1:
7507 case MVE_VLDRH_T2:
56858bea
AV		 7508 case MVE_VMAX:
7509 case MVE_VMAXA:
7510 case MVE_VMAXV:
7511 case MVE_VMAXAV:
7512 case MVE_VMIN:
7513 case MVE_VMINA:
7514 case MVE_VMINV:
7515 case MVE_VMINAV:
7516 case MVE_VMLA:
d3b63143 7517 case MVE_VMLAS:
f49bb598
AV		 7518 case MVE_VMUL_VEC_T1:
7519 case MVE_VMUL_VEC_T2:
7520 case MVE_VMULH:
7521 case MVE_VRMULH:
7522 case MVE_VMULL_INT:
7523 case MVE_VNEG_FP:
7524 case MVE_VNEG_VEC:
143275ea
AV		 7525 case MVE_VPT_VEC_T1:
7526 case MVE_VPT_VEC_T2:
7527 case MVE_VPT_VEC_T3:
7528 case MVE_VPT_VEC_T4:
7529 case MVE_VPT_VEC_T5:
7530 case MVE_VPT_VEC_T6:
14b456f2
AV		 7531 case MVE_VQABS:
7532 case MVE_VQADD_T1:
7533 case MVE_VQADD_T2:
d3b63143
AV		 7534 case MVE_VQDMLADH:
7535 case MVE_VQRDMLADH:
7536 case MVE_VQDMLAH:
7537 case MVE_VQRDMLAH:
7538 case MVE_VQDMLASH:
7539 case MVE_VQRDMLASH:
7540 case MVE_VQDMLSDH:
7541 case MVE_VQRDMLSDH:
7542 case MVE_VQDMULH_T1:
7543 case MVE_VQRDMULH_T2:
7544 case MVE_VQDMULH_T3:
7545 case MVE_VQRDMULH_T4:
14b456f2 7546 case MVE_VQNEG:
ed63aa17
AV		 7547 case MVE_VQRSHL_T1:
7548 case MVE_VQRSHL_T2:
7549 case MVE_VQSHL_T1:
7550 case MVE_VQSHL_T4:
14b456f2
AV		 7551 case MVE_VQSUB_T1:
7552 case MVE_VQSUB_T2:
7553 case MVE_VREV32:
7554 case MVE_VREV64:
9743db03 7555 case MVE_VRHADD:
bf0b396d 7556 case MVE_VRINT_FP:
ed63aa17
AV		 7557 case MVE_VRSHL_T1:
7558 case MVE_VRSHL_T2:
7559 case MVE_VSHL_T2:
7560 case MVE_VSHL_T3:
7561 case MVE_VSHLL_T2:
04d54ace
AV		 7562 case MVE_VST2:
7563 case MVE_VST4:
ef1576a1
AV		 7564 case MVE_VSTRB_SCATTER_T1:
7565 case MVE_VSTRH_SCATTER_T2:
7566 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7567 case MVE_VSTRB_T1:
7568 case MVE_VSTRH_T2:
66dcaa5d
AV		 7569 case MVE_VSUB_VEC_T1:
7570 case MVE_VSUB_VEC_T2:
143275ea 7571 if (size <= 3)
6576bffe 7572 func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
143275ea 7573 else
6576bffe 7574 func (stream, dis_style_text, "<undef size>");
143275ea
AV		 7575 break;
7576
66dcaa5d
AV		 7577 case MVE_VABD_FP:
7578 case MVE_VADD_FP_T1:
7579 case MVE_VADD_FP_T2:
7580 case MVE_VSUB_FP_T1:
7581 case MVE_VSUB_FP_T2:
143275ea
AV		 7582 case MVE_VCMP_FP_T1:
7583 case MVE_VCMP_FP_T2:
9743db03
AV		 7584 case MVE_VFMA_FP_SCALAR:
7585 case MVE_VFMA_FP:
7586 case MVE_VFMS_FP:
7587 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7588 case MVE_VMAXNM_FP:
7589 case MVE_VMAXNMA_FP:
7590 case MVE_VMAXNMV_FP:
7591 case MVE_VMAXNMAV_FP:
7592 case MVE_VMINNM_FP:
7593 case MVE_VMINNMA_FP:
7594 case MVE_VMINNMV_FP:
7595 case MVE_VMINNMAV_FP:
f49bb598
AV		 7596 case MVE_VMUL_FP_T1:
7597 case MVE_VMUL_FP_T2:
143275ea
AV		 7598 case MVE_VPT_FP_T1:
7599 case MVE_VPT_FP_T2:
7600 if (size == 0)
6576bffe 7601 func (stream, dis_style_mnemonic, "32");
143275ea 7602 else if (size == 1)
6576bffe 7603 func (stream, dis_style_mnemonic, "16");
143275ea
AV		 7604 break;
7605
897b9bbc
AV		 7606 case MVE_VCADD_FP:
7607 case MVE_VCMLA_FP:
7608 case MVE_VCMUL_FP:
d3b63143
AV		 7609 case MVE_VMLADAV_T1:
7610 case MVE_VMLALDAV:
7611 case MVE_VMLSDAV_T1:
7612 case MVE_VMLSLDAV:
14925797
AV		 7613 case MVE_VMOVN:
7614 case MVE_VQDMULL_T1:
7615 case MVE_VQDMULL_T2:
7616 case MVE_VQMOVN:
7617 case MVE_VQMOVUN:
7618 if (size == 0)
6576bffe 7619 func (stream, dis_style_mnemonic, "16");
14925797 7620 else if (size == 1)
6576bffe 7621 func (stream, dis_style_mnemonic, "32");
14925797
AV		 7622 break;
7623
7624 case MVE_VMOVL:
7625 if (size == 1)
6576bffe 7626 func (stream, dis_style_mnemonic, "8");
14925797 7627 else if (size == 2)
6576bffe 7628 func (stream, dis_style_mnemonic, "16");
14925797
AV		 7629 break;
7630
9743db03
AV		 7631 case MVE_VDUP:
7632 switch (size)
7633 {
7634 case 0:
6576bffe 7635 func (stream, dis_style_mnemonic, "32");
9743db03
AV		 7636 break;
7637 case 1:
6576bffe 7638 func (stream, dis_style_mnemonic, "16");
9743db03
AV		 7639 break;
7640 case 2:
6576bffe 7641 func (stream, dis_style_mnemonic, "8");
9743db03
AV		 7642 break;
7643 default:
7644 break;
7645 }
7646 break;
7647
c507f10b
AV		 7648 case MVE_VMOV_GP_TO_VEC_LANE:
7649 case MVE_VMOV_VEC_LANE_TO_GP:
7650 switch (size)
7651 {
7652 case 0: case 4:
6576bffe 7653 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7654 break;
7655
7656 case 1: case 3:
7657 case 5: case 7:
6576bffe 7658 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7659 break;
7660
7661 case 8: case 9: case 10: case 11:
7662 case 12: case 13: case 14: case 15:
6576bffe 7663 func (stream, dis_style_mnemonic, "8");
c507f10b
AV		 7664 break;
7665
7666 default:
7667 break;
7668 }
7669 break;
7670
7671 case MVE_VMOV_IMM_TO_VEC:
7672 switch (size)
7673 {
7674 case 0: case 4: case 8:
7675 case 12: case 24: case 26:
6576bffe 7676 func (stream, dis_style_mnemonic, "i32");
c507f10b
AV		 7677 break;
7678 case 16: case 20:
6576bffe 7679 func (stream, dis_style_mnemonic, "i16");
c507f10b
AV		 7680 break;
7681 case 28:
6576bffe 7682 func (stream, dis_style_mnemonic, "i8");
c507f10b
AV		 7683 break;
7684 case 29:
6576bffe 7685 func (stream, dis_style_mnemonic, "i64");
c507f10b
AV		 7686 break;
7687 case 30:
6576bffe 7688 func (stream, dis_style_mnemonic, "f32");
c507f10b
AV		 7689 break;
7690 default:
7691 break;
7692 }
7693 break;
7694
14925797
AV		 7695 case MVE_VMULL_POLY:
7696 if (size == 0)
6576bffe 7697 func (stream, dis_style_mnemonic, "p8");
14925797 7698 else if (size == 1)
6576bffe 7699 func (stream, dis_style_mnemonic, "p16");
14925797
AV		 7700 break;
7701
c507f10b
AV		 7702 case MVE_VMVN_IMM:
7703 switch (size)
7704 {
7705 case 0: case 2: case 4:
7706 case 6: case 12: case 13:
6576bffe 7707 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7708 break;
7709
7710 case 8: case 10:
6576bffe 7711 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7712 break;
7713
7714 default:
7715 break;
7716 }
7717 break;
7718
7719 case MVE_VBIC_IMM:
7720 case MVE_VORR_IMM:
7721 switch (size)
7722 {
7723 case 1: case 3:
7724 case 5: case 7:
6576bffe 7725 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7726 break;
7727
7728 case 9: case 11:
6576bffe 7729 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7730 break;
7731
7732 default:
7733 break;
7734 }
7735 break;
7736
ed63aa17
AV		 7737 case MVE_VQSHRN:
7738 case MVE_VQSHRUN:
7739 case MVE_VQRSHRN:
7740 case MVE_VQRSHRUN:
7741 case MVE_VRSHRN:
7742 case MVE_VSHRN:
7743 {
7744 switch (size)
7745 {
7746 case 1:
6576bffe 7747 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7748 break;
7749
7750 case 2: case 3:
6576bffe 7751 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7752 break;
7753
7754 default:
7755 break;
7756 }
7757 }
7758 break;
7759
7760 case MVE_VQSHL_T2:
7761 case MVE_VQSHLU_T3:
7762 case MVE_VRSHR:
7763 case MVE_VSHL_T1:
7764 case MVE_VSHLL_T1:
7765 case MVE_VSHR:
7766 case MVE_VSLI:
7767 case MVE_VSRI:
7768 {
7769 switch (size)
7770 {
7771 case 1:
6576bffe 7772 func (stream, dis_style_mnemonic, "8");
ed63aa17
AV		 7773 break;
7774
7775 case 2: case 3:
6576bffe 7776 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7777 break;
7778
7779 case 4: case 5: case 6: case 7:
6576bffe 7780 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7781 break;
7782
7783 default:
7784 break;
7785 }
7786 }
7787 break;
7788
143275ea
AV		 7789 default:
7790 break;
7791 }
7792}
7793
f9d6cf2e
AC		 7794/* Return true if INSN is a shift insn with an immediate shift amount
7795 which needs decoding as per print_mve_shift_n. */
7796
7797static bool
7798mve_shift_insn_p (enum mve_instructions insn)
7799{
7800 switch (insn)
7801 {
7802 case MVE_VQSHL_T2:
7803 case MVE_VQSHLU_T3:
cd714ac0
AC		 7804 case MVE_VQSHRN:
7805 case MVE_VQSHRUN:
7806 case MVE_VQRSHRN:
7807 case MVE_VQRSHRUN:
f9d6cf2e
AC		 7808 case MVE_VRSHR:
7809 case MVE_VRSHRN:
7810 case MVE_VSHL_T1:
7811 case MVE_VSHLL_T1:
7812 case MVE_VSHR:
7813 case MVE_VSHRN:
7814 case MVE_VSLI:
7815 case MVE_VSRI:
7816 return true;
7817 default:
7818 return false;
7819 }
7820}
7821
ed63aa17
AV		 7822static void
7823print_mve_shift_n (struct disassemble_info *info, long given,
7824 enum mve_instructions matched_insn)
7825{
7826 void *stream = info->stream;
6576bffe 7827 fprintf_styled_ftype func = info->fprintf_styled_func;
ed63aa17
AV		 7828
7829 int startAt0
7830 = matched_insn == MVE_VQSHL_T2
7831 || matched_insn == MVE_VQSHLU_T3
7832 || matched_insn == MVE_VSHL_T1
7833 || matched_insn == MVE_VSHLL_T1
7834 || matched_insn == MVE_VSLI;
7835
7836 unsigned imm6 = (given & 0x3f0000) >> 16;
7837
7838 if (matched_insn == MVE_VSHLL_T1)
7839 imm6 &= 0x1f;
7840
7841 unsigned shiftAmount = 0;
7842 if ((imm6 & 0x20) != 0)
7843 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7844 else if ((imm6 & 0x10) != 0)
7845 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7846 else if ((imm6 & 0x08) != 0)
7847 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7848 else
7849 print_mve_undefined (info, UNDEF_SIZE_0);
7850
6576bffe 7851 func (stream, dis_style_immediate, "%u", shiftAmount);
ed63aa17
AV		 7852}
7853
143275ea
AV		 7854static void
7855print_vec_condition (struct disassemble_info *info, long given,
7856 enum mve_instructions matched_insn)
7857{
7858 void *stream = info->stream;
6576bffe 7859 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7860 long vec_cond = 0;
7861
7862 switch (matched_insn)
7863 {
7864 case MVE_VPT_FP_T1:
7865 case MVE_VCMP_FP_T1:
7866 vec_cond = (((given & 0x1000) >> 10)
7867 | ((given & 1) << 1)
7868 | ((given & 0x0080) >> 7));
6576bffe 7869 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7870 break;
7871
7872 case MVE_VPT_FP_T2:
7873 case MVE_VCMP_FP_T2:
7874 vec_cond = (((given & 0x1000) >> 10)
7875 | ((given & 0x0020) >> 4)
7876 | ((given & 0x0080) >> 7));
6576bffe 7877 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7878 break;
7879
7880 case MVE_VPT_VEC_T1:
7881 case MVE_VCMP_VEC_T1:
7882 vec_cond = (given & 0x0080) >> 7;
6576bffe 7883 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7884 break;
7885
7886 case MVE_VPT_VEC_T2:
7887 case MVE_VCMP_VEC_T2:
7888 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 7889 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7890 break;
7891
7892 case MVE_VPT_VEC_T3:
7893 case MVE_VCMP_VEC_T3:
7894 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6576bffe 7895 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7896 break;
7897
7898 case MVE_VPT_VEC_T4:
7899 case MVE_VCMP_VEC_T4:
7900 vec_cond = (given & 0x0080) >> 7;
6576bffe 7901 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7902 break;
7903
7904 case MVE_VPT_VEC_T5:
7905 case MVE_VCMP_VEC_T5:
7906 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 7907 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7908 break;
7909
7910 case MVE_VPT_VEC_T6:
7911 case MVE_VCMP_VEC_T6:
7912 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6576bffe 7913 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7914 break;
7915
7916 case MVE_NONE:
7917 case MVE_VPST:
7918 default:
7919 break;
7920 }
7921}
7922
7923#define W_BIT 21
7924#define I_BIT 22
7925#define U_BIT 23
7926#define P_BIT 24
7927
7928#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7929#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7930#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7931#define PRE_BIT_SET (given & (1 << P_BIT))
7932
6576bffe
AB		 7933/* The assembler string for an instruction can include %{X:...%} patterns,
7934 where the 'X' is one of the characters understood by this function.
7935
7936 This function takes the X character, and returns a new style. This new
7937 style will be used by the caller to temporarily change the current base
7938 style. */
7939
7940static enum disassembler_style
7941decode_base_style (const char x)
7942{
7943 switch (x)
7944 {
7945 case 'A': return dis_style_address;
7946 case 'B': return dis_style_sub_mnemonic;
7947 case 'C': return dis_style_comment_start;
7948 case 'D': return dis_style_assembler_directive;
7949 case 'I': return dis_style_immediate;
7950 case 'M': return dis_style_mnemonic;
7951 case 'O': return dis_style_address_offset;
7952 case 'R': return dis_style_register;
7953 case 'S': return dis_style_symbol;
7954 case 'T': return dis_style_text;
7955 default:
7956 abort ();
7957 }
7958}
143275ea 7959
8f06b2d8
PB		 7960/* Print one coprocessor instruction on INFO->STREAM.
7961 Return TRUE if the instuction matched, FALSE if this is not a
7962 recognised coprocessor instruction. */
7963
78933a4a 7964static bool
33593eaf
MM		 7965print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7966 bfd_vma pc,
7967 struct disassemble_info *info,
7968 long given,
78933a4a 7969 bool thumb)
8f06b2d8 7970{
6b0dd094 7971 const struct sopcode32 *insn;
8f06b2d8 7972 void *stream = info->stream;
6576bffe 7973 fprintf_styled_ftype func = info->fprintf_styled_func;
8f06b2d8 7974 unsigned long mask;
2edcd244 7975 unsigned long value = 0;
c22aaad1 7976 int cond;
8afc7bea 7977 int cp_num;
823d2571
TG		 7978 struct arm_private_data *private_data = info->private_data;
7979 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7980 arm_feature_set arm_ext_v8_1m_main =
7981 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
6576bffe
AB		 7982 enum disassembler_style base_style = dis_style_mnemonic;
7983 enum disassembler_style old_base_style = base_style;
823d2571 7984
5b616bef 7985 allowed_arches = private_data->features;
8f06b2d8 7986
33593eaf 7987 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 7988 {
ff4a8d2b 7989 unsigned long u_reg = 16;
78933a4a 7990 bool is_unpredictable = false;
05413229 7991 signed long value_in_comment = 0;
0313a2b8
NC		 7992 const char *c;
7993
823d2571 7994 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7995 switch (insn->value)
7996 {
7997 case SENTINEL_IWMMXT_START:
7998 if (info->mach != bfd_mach_arm_XScale
7999 && info->mach != bfd_mach_arm_iWMMXt
8000 && info->mach != bfd_mach_arm_iWMMXt2)
8001 do
8002 insn++;
823d2571
TG		 8003 while ((! ARM_FEATURE_ZERO (insn->arch))
8004 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8005 continue;
8006
8007 case SENTINEL_IWMMXT_END:
8008 continue;
8009
8010 case SENTINEL_GENERIC_START:
5b616bef 8011 allowed_arches = private_data->features;
05413229
NC		 8012 continue;
8013
8014 default:
8015 abort ();
8016 }
8f06b2d8
PB		 8017
8018 mask = insn->mask;
8019 value = insn->value;
8afc7bea
RL		 8020 cp_num = (given >> 8) & 0xf;
8021
8f06b2d8
PB		 8022 if (thumb)
8023 {
8024 /* The high 4 bits are 0xe for Arm conditional instructions, and
8025 0xe for arm unconditional instructions. The rest of the
8026 encoding is the same. */
8027 mask |= 0xf0000000;
8028 value |= 0xe0000000;
c22aaad1
PB		 8029 if (ifthen_state)
8030 cond = IFTHEN_COND;
8031 else
e2efe87d 8032 cond = COND_UNCOND;
8f06b2d8
PB		 8033 }
8034 else
8035 {
8036 /* Only match unconditional instuctions against unconditional
8037 patterns. */
8038 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8039 {
8040 mask |= 0xf0000000;
e2efe87d 8041 cond = COND_UNCOND;
c22aaad1
PB		 8042 }
8043 else
8044 {
8045 cond = (given >> 28) & 0xf;
8046 if (cond == 0xe)
e2efe87d 8047 cond = COND_UNCOND;
c22aaad1 8048 }
8f06b2d8 8049 }
823d2571 8050
6b0dd094
AV		 8051 if ((insn->isa == T32 && !thumb)
8052 || (insn->isa == ARM && thumb))
8053 continue;
8054
0313a2b8
NC		 8055 if ((given & mask) != value)
8056 continue;
8f06b2d8 8057
823d2571 8058 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8059 continue;
8060
8afc7bea
RL		 8061 if (insn->value == 0xfe000010 /* mcr2 */
8062 || insn->value == 0xfe100010 /* mrc2 */
8063 || insn->value == 0xfc100000 /* ldc2 */
8064 || insn->value == 0xfc000000) /* stc2 */
8065 {
b0c11777 8066 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
78933a4a 8067 is_unpredictable = true;
f08d8ce3
AV		 8068
8069 /* Armv8.1-M Mainline FP & MVE instructions. */
8070 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8071 && !ARM_CPU_IS_ANY (allowed_arches)
8072 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8073 continue;
8074
8afc7bea
RL		 8075 }
8076 else if (insn->value == 0x0e000000 /* cdp */
8077 || insn->value == 0xfe000000 /* cdp2 */
8078 || insn->value == 0x0e000010 /* mcr */
8079 || insn->value == 0x0e100010 /* mrc */
8080 || insn->value == 0x0c100000 /* ldc */
8081 || insn->value == 0x0c000000) /* stc */
8082 {
8083 /* Floating-point instructions. */
b0c11777 8084 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8085 continue;
32c36c3c
AV		 8086
8087 /* Armv8.1-M Mainline FP & MVE instructions. */
8088 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8089 && !ARM_CPU_IS_ANY (allowed_arches)
8090 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8091 continue;
8afc7bea 8092 }
aef6d006
AV		 8093 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8094 || insn->value == 0xec000f80) /* vstr (system register) */
8095 && arm_decode_field (given, 24, 24) == 0
8096 && arm_decode_field (given, 21, 21) == 0)
8097 /* If the P and W bits are both 0 then these encodings match the MVE
8098 VLDR and VSTR instructions, these are in a different table, so we
8099 don't let it match here. */
8100 continue;
8101
0313a2b8
NC		 8102 for (c = insn->assembler; *c; c++)
8103 {
8104 if (*c == '%')
8f06b2d8 8105 {
32c36c3c 8106 const char mod = *++c;
6576bffe 8107
32c36c3c 8108 switch (mod)
8f06b2d8 8109 {
6576bffe
AB		 8110 case '{':
8111 ++c;
8112 if (*c == '\0')
8113 abort ();
8114 old_base_style = base_style;
8115 base_style = decode_base_style (*c);
8116 ++c;
8117 if (*c != ':')
8118 abort ();
8119 break;
8120
8121 case '}':
8122 base_style = old_base_style;
8123 break;
8124
0313a2b8 8125 case '%':
6576bffe 8126 func (stream, base_style, "%%");
0313a2b8
NC		 8127 break;
8128
8129 case 'A':
32c36c3c 8130 case 'K':
05413229 8131 {
79862e45 8132 int rn = (given >> 16) & 0xf;
b0c11777 8133 bfd_vma offset = given & 0xff;
0313a2b8 8134
32c36c3c
AV		 8135 if (mod == 'K')
8136 offset = given & 0x7f;
8137
6576bffe
AB		 8138 func (stream, dis_style_text, "[");
8139 func (stream, dis_style_register, "%s",
8140 arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8141
79862e45
DJ		 8142 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8143 {
8144 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8145 if (cp_num == 9)
8146 /* vldr.16/vstr.16 will shift the address
8147 left by 1 bit only. */
8148 offset = offset * 2;
8149 else
8150 offset = offset * 4;
8151
79862e45
DJ		 8152 if (NEGATIVE_BIT_SET)
8153 offset = - offset;
8154 if (rn != 15)
8155 value_in_comment = offset;
8156 }
8157
c1e26897 8158 if (PRE_BIT_SET)
05413229
NC		 8159 {
8160 if (offset)
6576bffe
AB		 8161 {
8162 func (stream, dis_style_text, ", ");
8163 func (stream, dis_style_immediate, "#%d",
8164 (int) offset);
8165 func (stream, dis_style_text, "]%s",
8166 WRITEBACK_BIT_SET ? "!" : "");
8167 }
26d97720 8168 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8169 {
8170 func (stream, dis_style_text, ", ");
8171 func (stream, dis_style_immediate, "#-0");
8172 func (stream, dis_style_text, "]");
8173 }
05413229 8174 else
6576bffe 8175 func (stream, dis_style_text, "]");
05413229
NC		 8176 }
8177 else
8178 {
6576bffe 8179 func (stream, dis_style_text, "]");
8f06b2d8 8180
c1e26897 8181 if (WRITEBACK_BIT_SET)
05413229
NC		 8182 {
8183 if (offset)
6576bffe
AB		 8184 {
8185 func (stream, dis_style_text, ", ");
8186 func (stream, dis_style_immediate,
8187 "#%d", (int) offset);
8188 }
26d97720 8189 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8190 {
8191 func (stream, dis_style_text, ", ");
8192 func (stream, dis_style_immediate, "#-0");
8193 }
05413229
NC		 8194 }
8195 else
fe56b6ce 8196 {
6576bffe
AB		 8197 func (stream, dis_style_text, ", {");
8198 func (stream, dis_style_immediate, "%s%d",
26d97720 8199 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8200 (int) offset);
6576bffe 8201 func (stream, dis_style_text, "}");
fe56b6ce
NC		 8202 value_in_comment = offset;
8203 }
05413229 8204 }
79862e45
DJ		 8205 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8206 {
6576bffe 8207 func (stream, dis_style_comment_start, "\t@ ");
6844b2c2
MGD		 8208 /* For unaligned PCs, apply off-by-alignment
8209 correction. */
43e65147 8210 info->print_address_func (offset + pc
6844b2c2
MGD		 8211 + info->bytes_per_chunk * 2
8212 - (pc & 3),
dffaa15c 8213 info);
79862e45 8214 }
05413229 8215 }
0313a2b8 8216 break;
8f06b2d8 8217
0313a2b8
NC		 8218 case 'B':
8219 {
8220 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8221 int offset = (given >> 1) & 0x3f;
8222
6576bffe 8223 func (stream, dis_style_text, "{");
0313a2b8 8224 if (offset == 1)
6576bffe 8225 func (stream, dis_style_register, "d%d", regno);
0313a2b8 8226 else if (regno + offset > 32)
6576bffe
AB		 8227 {
8228 func (stream, dis_style_register, "d%d", regno);
8229 func (stream, dis_style_text, "-<overflow reg d%d>",
8230 regno + offset - 1);
8231 }
0313a2b8 8232 else
6576bffe
AB		 8233 {
8234 func (stream, dis_style_register, "d%d", regno);
8235 func (stream, dis_style_text, "-");
8236 func (stream, dis_style_register, "d%d",
8237 regno + offset - 1);
8238 }
8239 func (stream, dis_style_text, "}");
0313a2b8
NC		 8240 }
8241 break;
8f06b2d8 8242
efd6b359
AV		 8243 case 'C':
8244 {
78933a4a 8245 bool single = ((given >> 8) & 1) == 0;
efd6b359
AV		 8246 char reg_prefix = single ? 's' : 'd';
8247 int Dreg = (given >> 22) & 0x1;
8248 int Vdreg = (given >> 12) & 0xf;
8249 int reg = single ? ((Vdreg << 1) | Dreg)
8250 : ((Dreg << 4) | Vdreg);
8251 int num = (given >> (single ? 0 : 1)) & 0x7f;
8252 int maxreg = single ? 31 : 15;
8253 int topreg = reg + num - 1;
8254
6576bffe 8255 func (stream, dis_style_text, "{");
efd6b359 8256 if (!num)
6576bffe
AB		 8257 {
8258 /* Nothing. */
8259 }
efd6b359 8260 else if (num == 1)
6576bffe
AB		 8261 {
8262 func (stream, dis_style_register,
8263 "%c%d", reg_prefix, reg);
8264 func (stream, dis_style_text, ", ");
8265 }
efd6b359 8266 else if (topreg > maxreg)
6576bffe
AB		 8267 {
8268 func (stream, dis_style_register, "%c%d",
8269 reg_prefix, reg);
8270 func (stream, dis_style_text, "-<overflow reg d%d, ",
8271 single ? topreg >> 1 : topreg);
8272 }
efd6b359 8273 else
6576bffe
AB		 8274 {
8275 func (stream, dis_style_register,
8276 "%c%d", reg_prefix, reg);
8277 func (stream, dis_style_text, "-");
8278 func (stream, dis_style_register, "%c%d",
8279 reg_prefix, topreg);
8280 func (stream, dis_style_text, ", ");
8281 }
8282 func (stream, dis_style_register, "VPR");
8283 func (stream, dis_style_text, "}");
efd6b359
AV		 8284 }
8285 break;
8286
e2efe87d
MGD		 8287 case 'u':
8288 if (cond != COND_UNCOND)
78933a4a 8289 is_unpredictable = true;
e2efe87d
MGD		 8290
8291 /* Fall through. */
0313a2b8 8292 case 'c':
b0c11777 8293 if (cond != COND_UNCOND && cp_num == 9)
78933a4a 8294 is_unpredictable = true;
b0c11777 8295
aab2c27d
MM		 8296 /* Fall through. */
8297 case 'b':
6576bffe
AB		 8298 func (stream, dis_style_mnemonic, "%s",
8299 arm_conditional[cond]);
0313a2b8 8300 break;
8f06b2d8 8301
0313a2b8
NC		 8302 case 'I':
8303 /* Print a Cirrus/DSP shift immediate. */
8304 /* Immediates are 7bit signed ints with bits 0..3 in
8305 bits 0..3 of opcode and bits 4..6 in bits 5..7
8306 of opcode. */
8307 {
8308 int imm;
8f06b2d8 8309
0313a2b8 8310 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8311
0313a2b8
NC		 8312 /* Is ``imm'' a negative number? */
8313 if (imm & 0x40)
24b4cf66 8314 imm -= 0x80;
8f06b2d8 8315
6576bffe 8316 func (stream, dis_style_immediate, "%d", imm);
0313a2b8
NC		 8317 }
8318
8319 break;
8f06b2d8 8320
32c36c3c
AV		 8321 case 'J':
8322 {
73cd51e5
AV		 8323 unsigned long regno
8324 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8325
8326 switch (regno)
8327 {
8328 case 0x1:
6576bffe 8329 func (stream, dis_style_register, "FPSCR");
32c36c3c
AV		 8330 break;
8331 case 0x2:
6576bffe 8332 func (stream, dis_style_register, "FPSCR_nzcvqc");
32c36c3c
AV		 8333 break;
8334 case 0xc:
6576bffe 8335 func (stream, dis_style_register, "VPR");
32c36c3c
AV		 8336 break;
8337 case 0xd:
6576bffe 8338 func (stream, dis_style_register, "P0");
32c36c3c
AV		 8339 break;
8340 case 0xe:
6576bffe 8341 func (stream, dis_style_register, "FPCXTNS");
32c36c3c
AV		 8342 break;
8343 case 0xf:
6576bffe 8344 func (stream, dis_style_register, "FPCXTS");
32c36c3c
AV		 8345 break;
8346 default:
6576bffe
AB		 8347 func (stream, dis_style_text, "<invalid reg %lu>",
8348 regno);
32c36c3c
AV		 8349 break;
8350 }
8351 }
8352 break;
8353
0313a2b8
NC		 8354 case 'F':
8355 switch (given & 0x00408000)
8356 {
8357 case 0:
6576bffe 8358 func (stream, dis_style_immediate, "4");
0313a2b8
NC		 8359 break;
8360 case 0x8000:
6576bffe 8361 func (stream, dis_style_immediate, "1");
0313a2b8
NC		 8362 break;
8363 case 0x00400000:
6576bffe 8364 func (stream, dis_style_immediate, "2");
8f06b2d8 8365 break;
0313a2b8 8366 default:
6576bffe 8367 func (stream, dis_style_immediate, "3");
0313a2b8
NC		 8368 }
8369 break;
8f06b2d8 8370
0313a2b8
NC		 8371 case 'P':
8372 switch (given & 0x00080080)
8373 {
8374 case 0:
6576bffe 8375 func (stream, dis_style_mnemonic, "s");
0313a2b8
NC		 8376 break;
8377 case 0x80:
6576bffe 8378 func (stream, dis_style_mnemonic, "d");
0313a2b8
NC		 8379 break;
8380 case 0x00080000:
6576bffe 8381 func (stream, dis_style_mnemonic, "e");
0313a2b8
NC		 8382 break;
8383 default:
6576bffe 8384 func (stream, dis_style_text, _("<illegal precision>"));
8f06b2d8 8385 break;
0313a2b8
NC		 8386 }
8387 break;
8f06b2d8 8388
0313a2b8
NC		 8389 case 'Q':
8390 switch (given & 0x00408000)
8391 {
8392 case 0:
6576bffe 8393 func (stream, dis_style_mnemonic, "s");
8f06b2d8 8394 break;
0313a2b8 8395 case 0x8000:
6576bffe 8396 func (stream, dis_style_mnemonic, "d");
8f06b2d8 8397 break;
0313a2b8 8398 case 0x00400000:
6576bffe 8399 func (stream, dis_style_mnemonic, "e");
0313a2b8
NC		 8400 break;
8401 default:
6576bffe 8402 func (stream, dis_style_mnemonic, "p");
8f06b2d8 8403 break;
0313a2b8
NC		 8404 }
8405 break;
8f06b2d8 8406
0313a2b8
NC		 8407 case 'R':
8408 switch (given & 0x60)
8409 {
8410 case 0:
8411 break;
8412 case 0x20:
6576bffe 8413 func (stream, dis_style_mnemonic, "p");
0313a2b8
NC		 8414 break;
8415 case 0x40:
6576bffe 8416 func (stream, dis_style_mnemonic, "m");
0313a2b8
NC		 8417 break;
8418 default:
6576bffe 8419 func (stream, dis_style_mnemonic, "z");
0313a2b8
NC		 8420 break;
8421 }
8422 break;
16980d0b 8423
0313a2b8
NC		 8424 case '0': case '1': case '2': case '3': case '4':
8425 case '5': case '6': case '7': case '8': case '9':
8426 {
8427 int width;
8f06b2d8 8428
0313a2b8 8429 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8430
0313a2b8
NC		 8431 switch (*c)
8432 {
ff4a8d2b
NC		 8433 case 'R':
8434 if (value == 15)
78933a4a 8435 is_unpredictable = true;
ff4a8d2b 8436 /* Fall through. */
0313a2b8 8437 case 'r':
ff4a8d2b
NC		 8438 if (c[1] == 'u')
8439 {
8440 /* Eat the 'u' character. */
8441 ++ c;
8442
8443 if (u_reg == value)
78933a4a 8444 is_unpredictable = true;
ff4a8d2b
NC		 8445 u_reg = value;
8446 }
4575eafb
AB		 8447 func (stream, dis_style_register, "%s",
8448 arm_regnames[value]);
0313a2b8 8449 break;
c28eeff2
SN		 8450 case 'V':
8451 if (given & (1 << 6))
8452 goto Q;
8453 /* FALLTHROUGH */
0313a2b8 8454 case 'D':
6576bffe 8455 func (stream, dis_style_register, "d%ld", value);
0313a2b8
NC		 8456 break;
8457 case 'Q':
c28eeff2 8458 Q:
0313a2b8 8459 if (value & 1)
6576bffe
AB		 8460 func (stream, dis_style_text,
8461 "<illegal reg q%ld.5>", value >> 1);
0313a2b8 8462 else
6576bffe
AB		 8463 func (stream, dis_style_register,
8464 "q%ld", value >> 1);
0313a2b8
NC		 8465 break;
8466 case 'd':
6576bffe 8467 func (stream, base_style, "%ld", value);
05413229 8468 value_in_comment = value;
0313a2b8 8469 break;
6f1c2142
AM		 8470 case 'E':
8471 {
8472 /* Converts immediate 8 bit back to float value. */
8473 unsigned floatVal = (value & 0x80) << 24
8474 | (value & 0x3F) << 19
8475 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8476
8477 /* Quarter float have a maximum value of 31.0.
8478 Get floating point value multiplied by 1e7.
8479 The maximum value stays in limit of a 32-bit int. */
8480 unsigned decVal =
8481 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8482 (16 + (value & 0xF));
8483
8484 if (!(decVal % 1000000))
6576bffe
AB		 8485 {
8486 func (stream, dis_style_immediate, "%ld", value);
8487 func (stream, dis_style_comment_start,
8488 "\t@ 0x%08x %c%u.%01u",
8489 floatVal, value & 0x80 ? '-' : ' ',
8490 decVal / 10000000,
8491 decVal % 10000000 / 1000000);
8492 }
6f1c2142 8493 else if (!(decVal % 10000))
6576bffe
AB		 8494 {
8495 func (stream, dis_style_immediate, "%ld", value);
8496 func (stream, dis_style_comment_start,
8497 "\t@ 0x%08x %c%u.%03u",
8498 floatVal, value & 0x80 ? '-' : ' ',
8499 decVal / 10000000,
8500 decVal % 10000000 / 10000);
8501 }
6f1c2142 8502 else
6576bffe
AB		 8503 {
8504 func (stream, dis_style_immediate, "%ld", value);
8505 func (stream, dis_style_comment_start,
8506 "\t@ 0x%08x %c%u.%07u",
8507 floatVal, value & 0x80 ? '-' : ' ',
8508 decVal / 10000000, decVal % 10000000);
8509 }
6f1c2142
AM		 8510 break;
8511 }
0313a2b8
NC		 8512 case 'k':
8513 {
8514 int from = (given & (1 << 7)) ? 32 : 16;
6576bffe
AB		 8515 func (stream, dis_style_immediate, "%ld",
8516 from - value);
0313a2b8
NC		 8517 }
8518 break;
8f06b2d8 8519
0313a2b8
NC		 8520 case 'f':
8521 if (value > 7)
6576bffe
AB		 8522 func (stream, dis_style_immediate, "#%s",
8523 arm_fp_const[value & 7]);
0313a2b8 8524 else
6576bffe 8525 func (stream, dis_style_register, "f%ld", value);
0313a2b8 8526 break;
4146fd53 8527
0313a2b8
NC		 8528 case 'w':
8529 if (width == 2)
6576bffe
AB		 8530 func (stream, dis_style_mnemonic, "%s",
8531 iwmmxt_wwnames[value]);
0313a2b8 8532 else
6576bffe
AB		 8533 func (stream, dis_style_mnemonic, "%s",
8534 iwmmxt_wwssnames[value]);
0313a2b8 8535 break;
4146fd53 8536
0313a2b8 8537 case 'g':
6576bffe
AB		 8538 func (stream, dis_style_register, "%s",
8539 iwmmxt_regnames[value]);
0313a2b8
NC		 8540 break;
8541 case 'G':
6576bffe
AB		 8542 func (stream, dis_style_register, "%s",
8543 iwmmxt_cregnames[value]);
16980d0b 8544 break;
8f06b2d8 8545
0313a2b8 8546 case 'x':
6576bffe
AB		 8547 func (stream, dis_style_immediate, "0x%lx",
8548 (value & 0xffffffffUL));
0313a2b8 8549 break;
8f06b2d8 8550
33399f07
MGD		 8551 case 'c':
8552 switch (value)
8553 {
8554 case 0:
6576bffe 8555 func (stream, dis_style_mnemonic, "eq");
33399f07
MGD		 8556 break;
8557
8558 case 1:
6576bffe 8559 func (stream, dis_style_mnemonic, "vs");
33399f07
MGD		 8560 break;
8561
8562 case 2:
6576bffe 8563 func (stream, dis_style_mnemonic, "ge");
33399f07
MGD		 8564 break;
8565
8566 case 3:
6576bffe 8567 func (stream, dis_style_mnemonic, "gt");
33399f07
MGD		 8568 break;
8569
8570 default:
6576bffe 8571 func (stream, dis_style_text, "??");
33399f07
MGD		 8572 break;
8573 }
8574 break;
8575
0313a2b8
NC		 8576 case '`':
8577 c++;
8578 if (value == 0)
6576bffe 8579 func (stream, dis_style_mnemonic, "%c", *c);
0313a2b8
NC		 8580 break;
8581 case '\'':
8582 c++;
8583 if (value == ((1ul << width) - 1))
6576bffe 8584 func (stream, base_style, "%c", *c);
0313a2b8
NC		 8585 break;
8586 case '?':
6576bffe
AB		 8587 func (stream, base_style, "%c",
8588 c[(1 << width) - (int) value]);
0313a2b8
NC		 8589 c += 1 << width;
8590 break;
8591 default:
8592 abort ();
8593 }
dffaa15c
AM		 8594 }
8595 break;
0313a2b8 8596
dffaa15c
AM		 8597 case 'y':
8598 case 'z':
8599 {
8600 int single = *c++ == 'y';
8601 int regno;
8f06b2d8 8602
dffaa15c
AM		 8603 switch (*c)
8604 {
8605 case '4': /* Sm pair */
8606 case '0': /* Sm, Dm */
8607 regno = given & 0x0000000f;
8608 if (single)
8609 {
8610 regno <<= 1;
8611 regno += (given >> 5) & 1;
8612 }
8613 else
8614 regno += ((given >> 5) & 1) << 4;
8615 break;
8f06b2d8 8616
dffaa15c
AM		 8617 case '1': /* Sd, Dd */
8618 regno = (given >> 12) & 0x0000000f;
8619 if (single)
8620 {
8621 regno <<= 1;
8622 regno += (given >> 22) & 1;
8623 }
8624 else
8625 regno += ((given >> 22) & 1) << 4;
8626 break;
7df76b80 8627
dffaa15c
AM		 8628 case '2': /* Sn, Dn */
8629 regno = (given >> 16) & 0x0000000f;
8630 if (single)
8631 {
8632 regno <<= 1;
8633 regno += (given >> 7) & 1;
8634 }
8635 else
8636 regno += ((given >> 7) & 1) << 4;
8637 break;
a7f8487e 8638
dffaa15c 8639 case '3': /* List */
6576bffe 8640 func (stream, dis_style_text, "{");
dffaa15c
AM		 8641 regno = (given >> 12) & 0x0000000f;
8642 if (single)
8643 {
8644 regno <<= 1;
8645 regno += (given >> 22) & 1;
8646 }
8647 else
8648 regno += ((given >> 22) & 1) << 4;
8649 break;
a7f8487e 8650
dffaa15c
AM		 8651 default:
8652 abort ();
8653 }
0313a2b8 8654
6576bffe
AB		 8655 func (stream, dis_style_register, "%c%d",
8656 single ? 's' : 'd', regno);
a7f8487e 8657
dffaa15c
AM		 8658 if (*c == '3')
8659 {
8660 int count = given & 0xff;
b34976b6 8661
dffaa15c
AM		 8662 if (single == 0)
8663 count >>= 1;
0313a2b8 8664
dffaa15c
AM		 8665 if (--count)
8666 {
6576bffe
AB		 8667 func (stream, dis_style_text, "-");
8668 func (stream, dis_style_register, "%c%d",
dffaa15c
AM		 8669 single ? 's' : 'd',
8670 regno + count);
8671 }
0313a2b8 8672
6576bffe 8673 func (stream, dis_style_text, "}");
0313a2b8 8674 }
dffaa15c 8675 else if (*c == '4')
6576bffe
AB		 8676 {
8677 func (stream, dis_style_text, ", ");
8678 func (stream, dis_style_register, "%c%d",
8679 single ? 's' : 'd', regno + 1);
8680 }
dffaa15c
AM		 8681 }
8682 break;
b34976b6 8683
dffaa15c
AM		 8684 case 'L':
8685 switch (given & 0x00400100)
0313a2b8 8686 {
6576bffe
AB		 8687 case 0x00000000:
8688 func (stream, dis_style_mnemonic, "b");
8689 break;
8690 case 0x00400000:
8691 func (stream, dis_style_mnemonic, "h");
8692 break;
8693 case 0x00000100:
8694 func (stream, dis_style_mnemonic, "w");
8695 break;
8696 case 0x00400100:
8697 func (stream, dis_style_mnemonic, "d");
8698 break;
dffaa15c
AM		 8699 default:
8700 break;
0313a2b8 8701 }
dffaa15c 8702 break;
2d447fca 8703
dffaa15c
AM		 8704 case 'Z':
8705 {
8706 /* given (20, 23) | given (0, 3) */
8707 value = ((given >> 16) & 0xf0) | (given & 0xf);
6576bffe 8708 func (stream, dis_style_immediate, "%d", (int) value);
dffaa15c
AM		 8709 }
8710 break;
0313a2b8 8711
dffaa15c
AM		 8712 case 'l':
8713 /* This is like the 'A' operator, except that if
8714 the width field "M" is zero, then the offset is
8715 *not* multiplied by four. */
8716 {
8717 int offset = given & 0xff;
8718 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8719
6576bffe
AB		 8720 func (stream, dis_style_text, "[");
8721 func (stream, dis_style_register, "%s",
8722 arm_regnames [(given >> 16) & 0xf]);
05413229 8723
dffaa15c
AM		 8724 if (multiplier > 1)
8725 {
8726 value_in_comment = offset * multiplier;
8727 if (NEGATIVE_BIT_SET)
8728 value_in_comment = - value_in_comment;
8729 }
0313a2b8 8730
dffaa15c
AM		 8731 if (offset)
8732 {
8733 if (PRE_BIT_SET)
6576bffe
AB		 8734 {
8735 func (stream, dis_style_text, ", ");
8736 func (stream, dis_style_immediate, "#%s%d",
8737 NEGATIVE_BIT_SET ? "-" : "",
8738 offset * multiplier);
8739 func (stream, dis_style_text, "]%s",
8740 WRITEBACK_BIT_SET ? "!" : "");
8741 }
dffaa15c 8742 else
6576bffe
AB		 8743 {
8744 func (stream, dis_style_text, "], ");
8745 func (stream, dis_style_immediate, "#%s%d",
8746 NEGATIVE_BIT_SET ? "-" : "",
8747 offset * multiplier);
8748 }
dffaa15c
AM		 8749 }
8750 else
6576bffe 8751 func (stream, dis_style_text, "]");
dffaa15c
AM		 8752 }
8753 break;
2d447fca 8754
dffaa15c
AM		 8755 case 'r':
8756 {
8757 int imm4 = (given >> 4) & 0xf;
8758 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8759 int ubit = ! NEGATIVE_BIT_SET;
8760 const char *rm = arm_regnames [given & 0xf];
8761 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8762
dffaa15c
AM		 8763 switch (puw_bits)
8764 {
8765 case 1:
8766 case 3:
6576bffe
AB		 8767 func (stream, dis_style_text, "[");
8768 func (stream, dis_style_register, "%s", rn);
8769 func (stream, dis_style_text, "], ");
8770 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8771 func (stream, dis_style_register, "%s", rm);
dffaa15c 8772 if (imm4)
6576bffe
AB		 8773 {
8774 func (stream, dis_style_text, ", ");
8775 func (stream, dis_style_sub_mnemonic, "lsl ");
8776 func (stream, dis_style_immediate, "#%d", imm4);
8777 }
dffaa15c 8778 break;
0313a2b8 8779
dffaa15c
AM		 8780 case 4:
8781 case 5:
8782 case 6:
8783 case 7:
6576bffe
AB		 8784 func (stream, dis_style_text, "[");
8785 func (stream, dis_style_register, "%s", rn);
8786 func (stream, dis_style_text, ", ");
8787 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8788 func (stream, dis_style_register, "%s", rm);
dffaa15c 8789 if (imm4 > 0)
6576bffe
AB		 8790 {
8791 func (stream, dis_style_text, ", ");
8792 func (stream, dis_style_sub_mnemonic, "lsl ");
8793 func (stream, dis_style_immediate, "#%d", imm4);
8794 }
8795 func (stream, dis_style_text, "]");
dffaa15c 8796 if (puw_bits == 5 || puw_bits == 7)
6576bffe 8797 func (stream, dis_style_text, "!");
dffaa15c 8798 break;
2d447fca 8799
dffaa15c 8800 default:
6576bffe 8801 func (stream, dis_style_text, "INVALID");
dffaa15c
AM		 8802 }
8803 }
8804 break;
0313a2b8 8805
dffaa15c
AM		 8806 case 'i':
8807 {
8808 long imm5;
8809 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
6576bffe
AB		 8810 func (stream, dis_style_immediate, "%ld",
8811 (imm5 == 0) ? 32 : imm5);
0313a2b8 8812 }
dffaa15c
AM		 8813 break;
8814
8815 default:
8816 abort ();
252b5132 8817 }
252b5132 8818 }
0313a2b8 8819 else
6576bffe
AB		 8820 {
8821 if (*c == '@')
8822 base_style = dis_style_comment_start;
8823
8824 if (*c == '\t')
8825 base_style = dis_style_text;
8826
8827 func (stream, base_style, "%c", *c);
8828 }
252b5132 8829 }
05413229
NC		 8830
8831 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 8832 func (stream, dis_style_comment_start, "\t@ 0x%lx",
8833 (value_in_comment & 0xffffffffUL));
05413229 8834
ff4a8d2b 8835 if (is_unpredictable)
6576bffe 8836 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8837
78933a4a 8838 return true;
252b5132 8839 }
78933a4a 8840 return false;
252b5132
RH		 8841}
8842
78933a4a 8843static bool
33593eaf
MM		 8844print_insn_coprocessor (bfd_vma pc,
8845 struct disassemble_info *info,
8846 long given,
78933a4a 8847 bool thumb)
33593eaf
MM		 8848{
8849 return print_insn_coprocessor_1 (coprocessor_opcodes,
8850 pc, info, given, thumb);
8851}
8852
78933a4a 8853static bool
33593eaf
MM		 8854print_insn_generic_coprocessor (bfd_vma pc,
8855 struct disassemble_info *info,
8856 long given,
78933a4a 8857 bool thumb)
33593eaf
MM		 8858{
8859 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8860 pc, info, given, thumb);
8861}
8862
05413229
NC		 8863/* Decodes and prints ARM addressing modes. Returns the offset
8864 used in the address, if any, if it is worthwhile printing the
8865 offset as a hexadecimal value in a comment at the end of the
8866 line of disassembly. */
8867
8868static signed long
62b3e311
PB		 8869print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8870{
8871 void *stream = info->stream;
6576bffe 8872 fprintf_styled_ftype func = info->fprintf_styled_func;
f8b960bc 8873 bfd_vma offset = 0;
62b3e311
PB		 8874
8875 if (((given & 0x000f0000) == 0x000f0000)
8876 && ((given & 0x02000000) == 0))
8877 {
05413229 8878 offset = given & 0xfff;
62b3e311 8879
6576bffe
AB		 8880 func (stream, dis_style_text, "[");
8881 func (stream, dis_style_register, "pc");
62b3e311 8882
c1e26897 8883 if (PRE_BIT_SET)
62b3e311 8884 {
26d97720
NS		 8885 /* Pre-indexed. Elide offset of positive zero when
8886 non-writeback. */
8887 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 8888 {
8889 func (stream, dis_style_text, ", ");
8890 func (stream, dis_style_immediate, "#%s%d",
8891 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8892 }
26d97720
NS		 8893
8894 if (NEGATIVE_BIT_SET)
8895 offset = -offset;
62b3e311
PB		 8896
8897 offset += pc + 8;
8898
8899 /* Cope with the possibility of write-back
8900 being used. Probably a very dangerous thing
8901 for the programmer to do, but who are we to
8902 argue ? */
6576bffe 8903 func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8904 }
c1e26897 8905 else /* Post indexed. */
62b3e311 8906 {
6576bffe
AB		 8907 func (stream, dis_style_text, "], ");
8908 func (stream, dis_style_immediate, "#%s%d",
8909 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8910
c1e26897 8911 /* Ie ignore the offset. */
62b3e311
PB		 8912 offset = pc + 8;
8913 }
8914
6576bffe 8915 func (stream, dis_style_comment_start, "\t@ ");
62b3e311 8916 info->print_address_func (offset, info);
05413229 8917 offset = 0;
62b3e311
PB		 8918 }
8919 else
8920 {
6576bffe
AB		 8921 func (stream, dis_style_text, "[");
8922 func (stream, dis_style_register, "%s",
62b3e311 8923 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8924
8925 if (PRE_BIT_SET)
62b3e311
PB		 8926 {
8927 if ((given & 0x02000000) == 0)
8928 {
26d97720 8929 /* Elide offset of positive zero when non-writeback. */
05413229 8930 offset = given & 0xfff;
26d97720 8931 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 8932 {
8933 func (stream, dis_style_text, ", ");
8934 func (stream, dis_style_immediate, "#%s%d",
8935 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8936 }
62b3e311
PB		 8937 }
8938 else
8939 {
6576bffe
AB		 8940 func (stream, dis_style_text, ", %s",
8941 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8942 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8943 }
8944
6576bffe 8945 func (stream, dis_style_text, "]%s",
c1e26897 8946 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8947 }
8948 else
8949 {
8950 if ((given & 0x02000000) == 0)
8951 {
26d97720 8952 /* Always show offset. */
05413229 8953 offset = given & 0xfff;
6576bffe
AB		 8954 func (stream, dis_style_text, "], ");
8955 func (stream, dis_style_immediate, "#%s%d",
d908c8af 8956 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8957 }
8958 else
8959 {
6576bffe 8960 func (stream, dis_style_text, "], %s",
c1e26897 8961 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8962 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8963 }
8964 }
84919466
MR		 8965 if (NEGATIVE_BIT_SET)
8966 offset = -offset;
62b3e311 8967 }
05413229
NC		 8968
8969 return (signed long) offset;
62b3e311
PB		 8970}
8971
4934a27c
MM		 8972
8973/* Print one cde instruction on INFO->STREAM.
8974 Return TRUE if the instuction matched, FALSE if this is not a
8975 recognised cde instruction. */
78933a4a
AM		 8976static bool
8977print_insn_cde (struct disassemble_info *info, long given, bool thumb)
4934a27c
MM		 8978{
8979 const struct cdeopcode32 *insn;
8980 void *stream = info->stream;
6576bffe
AB		 8981 fprintf_styled_ftype func = info->fprintf_styled_func;
8982 enum disassembler_style base_style = dis_style_mnemonic;
8983 enum disassembler_style old_base_style = base_style;
4934a27c
MM		 8984
8985 if (thumb)
8986 {
8987 /* Manually extract the coprocessor code from a known point.
8988 This position is the same across all CDE instructions. */
8989 for (insn = cde_opcodes; insn->assembler; insn++)
8990 {
8991 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8992 uint16_t coproc_mask = 1 << coproc;
8993 if (! (coproc_mask & cde_coprocs))
8994 continue;
8995
8996 if ((given & insn->mask) == insn->value)
8997 {
78933a4a 8998 bool is_unpredictable = false;
4934a27c
MM		 8999 const char *c;
9000
9001 for (c = insn->assembler; *c; c++)
9002 {
9003 if (*c == '%')
9004 {
9005 switch (*++c)
9006 {
6576bffe
AB		 9007 case '{':
9008 ++c;
9009 if (*c == '\0')
9010 abort ();
9011 old_base_style = base_style;
9012 base_style = decode_base_style (*c);
9013 ++c;
9014 if (*c != ':')
9015 abort ();
9016 break;
9017
9018 case '}':
9019 base_style = old_base_style;
9020 break;
9021
4934a27c 9022 case '%':
6576bffe 9023 func (stream, base_style, "%%");
4934a27c
MM		 9024 break;
9025
9026 case '0': case '1': case '2': case '3': case '4':
9027 case '5': case '6': case '7': case '8': case '9':
9028 {
9029 int width;
9030 unsigned long value;
9031
9032 c = arm_decode_bitfield (c, given, &value, &width);
9033
9034 switch (*c)
9035 {
9036 case 'S':
9037 if (value > 10)
78933a4a 9038 is_unpredictable = true;
4934a27c
MM		 9039 /* Fall through. */
9040 case 'R':
9041 if (value == 13)
78933a4a 9042 is_unpredictable = true;
4934a27c
MM		 9043 /* Fall through. */
9044 case 'r':
6576bffe
AB		 9045 func (stream, dis_style_register, "%s",
9046 arm_regnames[value]);
4934a27c
MM		 9047 break;
9048
9049 case 'n':
9050 if (value == 15)
6576bffe 9051 func (stream, dis_style_register, "%s", "APSR_nzcv");
4934a27c 9052 else
6576bffe
AB		 9053 func (stream, dis_style_register, "%s",
9054 arm_regnames[value]);
4934a27c
MM		 9055 break;
9056
9057 case 'T':
6576bffe
AB		 9058 func (stream, dis_style_register, "%s",
9059 arm_regnames[(value + 1) & 15]);
4934a27c
MM		 9060 break;
9061
9062 case 'd':
6576bffe 9063 func (stream, dis_style_immediate, "%ld", value);
4934a27c
MM		 9064 break;
9065
5aae9ae9
MM		 9066 case 'V':
9067 if (given & (1 << 6))
6576bffe 9068 func (stream, dis_style_register, "q%ld", value >> 1);
5aae9ae9 9069 else if (given & (1 << 24))
6576bffe 9070 func (stream, dis_style_register, "d%ld", value);
5aae9ae9
MM		 9071 else
9072 {
9073 /* Encoding for S register is different than for D and
9074 Q registers. S registers are encoded using the top
9075 single bit in position 22 as the lowest bit of the
9076 register number, while for Q and D it represents the
9077 highest bit of the register number. */
9078 uint8_t top_bit = (value >> 4) & 1;
9079 uint8_t tmp = (value << 1) & 0x1e;
9080 uint8_t res = tmp | top_bit;
6576bffe 9081 func (stream, dis_style_register, "s%u", res);
5aae9ae9
MM		 9082 }
9083 break;
9084
4934a27c
MM		 9085 default:
9086 abort ();
9087 }
9088 }
9089 break;
9090
9091 case 'p':
9092 {
9093 uint8_t proc_number = (given >> 8) & 0x7;
6576bffe 9094 func (stream, dis_style_register, "p%u", proc_number);
4934a27c
MM		 9095 break;
9096 }
9097
9098 case 'a':
9099 {
9100 uint8_t a_offset = 28;
9101 if (given & (1 << a_offset))
6576bffe 9102 func (stream, dis_style_mnemonic, "a");
4934a27c
MM		 9103 break;
9104 }
9105 default:
9106 abort ();
9107 }
9108 }
9109 else
6576bffe
AB		 9110 {
9111 if (*c == '@')
9112 base_style = dis_style_comment_start;
9113 if (*c == '\t')
9114 base_style = dis_style_text;
9115
9116 func (stream, base_style, "%c", *c);
9117 }
4934a27c
MM		 9118 }
9119
9120 if (is_unpredictable)
6576bffe 9121 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
4934a27c 9122
78933a4a 9123 return true;
4934a27c
MM		 9124 }
9125 }
78933a4a 9126 return false;
4934a27c
MM		 9127 }
9128 else
78933a4a 9129 return false;
4934a27c
MM		 9130}
9131
9132
16980d0b
JB		 9133/* Print one neon instruction on INFO->STREAM.
9134 Return TRUE if the instuction matched, FALSE if this is not a
9135 recognised neon instruction. */
9136
78933a4a
AM		 9137static bool
9138print_insn_neon (struct disassemble_info *info, long given, bool thumb)
16980d0b
JB		 9139{
9140 const struct opcode32 *insn;
9141 void *stream = info->stream;
6576bffe
AB		 9142 fprintf_styled_ftype func = info->fprintf_styled_func;
9143 enum disassembler_style base_style = dis_style_mnemonic;
9144 enum disassembler_style old_base_style = base_style;
16980d0b
JB		 9145
9146 if (thumb)
9147 {
9148 if ((given & 0xef000000) == 0xef000000)
9149 {
0313a2b8 9150 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9151 unsigned long bit28 = given & (1 << 28);
9152
9153 given &= 0x00ffffff;
9154 if (bit28)
9155 given |= 0xf3000000;
9156 else
9157 given |= 0xf2000000;
9158 }
9159 else if ((given & 0xff000000) == 0xf9000000)
9160 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9161 /* BFloat16 neon instructions without special top byte handling. */
9162 else if ((given & 0xff000000) == 0xfe000000
9163 || (given & 0xff000000) == 0xfc000000)
9164 ;
9743db03 9165 /* vdup is also a valid neon instruction. */
e409955d 9166 else if ((given & 0xff900f5f) != 0xee800b10)
78933a4a 9167 return false;
16980d0b 9168 }
43e65147 9169
16980d0b
JB		 9170 for (insn = neon_opcodes; insn->assembler; insn++)
9171 {
e409955d
FS		 9172 unsigned long cond_mask = insn->mask;
9173 unsigned long cond_value = insn->value;
9174 int cond;
9175
9176 if (thumb)
9177 {
9178 if ((cond_mask & 0xf0000000) == 0) {
9179 /* For the entries in neon_opcodes, an opcode mask/value with
9180 the high 4 bits equal to 0 indicates a conditional
9181 instruction. For thumb however, we need to include those
9182 bits in the instruction matching. */
9183 cond_mask |= 0xf0000000;
9184 /* Furthermore, the thumb encoding of a conditional instruction
9185 will have the high 4 bits equal to 0xe. */
9186 cond_value |= 0xe0000000;
9187 }
9188 if (ifthen_state)
9189 cond = IFTHEN_COND;
9190 else
9191 cond = COND_UNCOND;
9192 }
9193 else
9194 {
9195 if ((given & 0xf0000000) == 0xf0000000)
9196 {
9197 /* If the instruction is unconditional, update the mask to only
9198 match against unconditional opcode values. */
9199 cond_mask |= 0xf0000000;
9200 cond = COND_UNCOND;
9201 }
9202 else
9203 {
9204 cond = (given >> 28) & 0xf;
9205 if (cond == 0xe)
9206 cond = COND_UNCOND;
9207 }
9208 }
9209
9210 if ((given & cond_mask) == cond_value)
16980d0b 9211 {
05413229 9212 signed long value_in_comment = 0;
78933a4a 9213 bool is_unpredictable = false;
16980d0b
JB		 9214 const char *c;
9215
9216 for (c = insn->assembler; *c; c++)
9217 {
9218 if (*c == '%')
9219 {
9220 switch (*++c)
9221 {
6576bffe
AB		 9222 case '{':
9223 ++c;
9224 if (*c == '\0')
9225 abort ();
9226 old_base_style = base_style;
9227 base_style = decode_base_style (*c);
9228 ++c;
9229 if (*c != ':')
9230 abort ();
9231 break;
9232
9233 case '}':
9234 base_style = old_base_style;
9235 break;
9236
16980d0b 9237 case '%':
6576bffe 9238 func (stream, base_style, "%%");
16980d0b
JB		 9239 break;
9240
e2efe87d
MGD		 9241 case 'u':
9242 if (thumb && ifthen_state)
78933a4a 9243 is_unpredictable = true;
e2efe87d
MGD		 9244
9245 /* Fall through. */
c22aaad1 9246 case 'c':
6576bffe
AB		 9247 func (stream, dis_style_mnemonic, "%s",
9248 arm_conditional[cond]);
c22aaad1
PB		 9249 break;
9250
16980d0b
JB		 9251 case 'A':
9252 {
43e65147 9253 static const unsigned char enc[16] =
16980d0b
JB		 9254 {
9255 0x4, 0x14, /* st4 0,1 */
9256 0x4, /* st1 2 */
9257 0x4, /* st2 3 */
9258 0x3, /* st3 4 */
9259 0x13, /* st3 5 */
9260 0x3, /* st1 6 */
9261 0x1, /* st1 7 */
9262 0x2, /* st2 8 */
9263 0x12, /* st2 9 */
9264 0x2, /* st1 10 */
9265 0, 0, 0, 0, 0
9266 };
9267 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9268 int rn = ((given >> 16) & 0xf);
9269 int rm = ((given >> 0) & 0xf);
9270 int align = ((given >> 4) & 0x3);
9271 int type = ((given >> 8) & 0xf);
9272 int n = enc[type] & 0xf;
9273 int stride = (enc[type] >> 4) + 1;
9274 int ix;
43e65147 9275
6576bffe 9276 func (stream, dis_style_text, "{");
16980d0b
JB		 9277 if (stride > 1)
9278 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9279 {
9280 if (ix > 0)
9281 func (stream, dis_style_text, ",");
9282 func (stream, dis_style_register, "d%d",
9283 rd + ix * stride);
9284 }
16980d0b 9285 else if (n == 1)
6576bffe 9286 func (stream, dis_style_register, "d%d", rd);
16980d0b 9287 else
6576bffe
AB		 9288 {
9289 func (stream, dis_style_register, "d%d", rd);
9290 func (stream, dis_style_text, "-");
9291 func (stream, dis_style_register, "d%d",
9292 rd + n - 1);
9293 }
9294 func (stream, dis_style_text, "}, [");
9295 func (stream, dis_style_register, "%s",
9296 arm_regnames[rn]);
16980d0b 9297 if (align)
6576bffe
AB		 9298 {
9299 func (stream, dis_style_text, " :");
9300 func (stream, dis_style_immediate, "%d",
9301 32 << align);
9302 }
9303 func (stream, dis_style_text, "]");
16980d0b 9304 if (rm == 0xd)
6576bffe 9305 func (stream, dis_style_text, "!");
16980d0b 9306 else if (rm != 0xf)
6576bffe
AB		 9307 {
9308 func (stream, dis_style_text, ", ");
9309 func (stream, dis_style_register, "%s",
9310 arm_regnames[rm]);
9311 }
16980d0b
JB		 9312 }
9313 break;
43e65147 9314
16980d0b
JB		 9315 case 'B':
9316 {
9317 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9318 int rn = ((given >> 16) & 0xf);
9319 int rm = ((given >> 0) & 0xf);
9320 int idx_align = ((given >> 4) & 0xf);
9321 int align = 0;
9322 int size = ((given >> 10) & 0x3);
9323 int idx = idx_align >> (size + 1);
9324 int length = ((given >> 8) & 3) + 1;
9325 int stride = 1;
9326 int i;
9327
9328 if (length > 1 && size > 0)
9329 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9330
16980d0b
JB		 9331 switch (length)
9332 {
9333 case 1:
9334 {
9335 int amask = (1 << size) - 1;
9336 if ((idx_align & (1 << size)) != 0)
78933a4a 9337 return false;
16980d0b
JB		 9338 if (size > 0)
9339 {
9340 if ((idx_align & amask) == amask)
9341 align = 8 << size;
9342 else if ((idx_align & amask) != 0)
78933a4a 9343 return false;
16980d0b
JB		 9344 }
9345 }
9346 break;
43e65147 9347
16980d0b
JB		 9348 case 2:
9349 if (size == 2 && (idx_align & 2) != 0)
78933a4a 9350 return false;
16980d0b
JB		 9351 align = (idx_align & 1) ? 16 << size : 0;
9352 break;
43e65147 9353
16980d0b
JB		 9354 case 3:
9355 if ((size == 2 && (idx_align & 3) != 0)
9356 || (idx_align & 1) != 0)
78933a4a 9357 return false;
16980d0b 9358 break;
43e65147 9359
16980d0b
JB		 9360 case 4:
9361 if (size == 2)
9362 {
9363 if ((idx_align & 3) == 3)
78933a4a 9364 return false;
16980d0b
JB		 9365 align = (idx_align & 3) * 64;
9366 }
9367 else
9368 align = (idx_align & 1) ? 32 << size : 0;
9369 break;
43e65147 9370
16980d0b
JB		 9371 default:
9372 abort ();
9373 }
43e65147 9374
6576bffe 9375 func (stream, dis_style_text, "{");
16980d0b 9376 for (i = 0; i < length; i++)
6576bffe
AB		 9377 {
9378 if (i > 0)
9379 func (stream, dis_style_text, ",");
9380 func (stream, dis_style_register, "d%d[%d]",
9381 rd + i * stride, idx);
9382 }
9383 func (stream, dis_style_text, "}, [");
9384 func (stream, dis_style_register, "%s",
9385 arm_regnames[rn]);
16980d0b 9386 if (align)
6576bffe
AB		 9387 {
9388 func (stream, dis_style_text, " :");
9389 func (stream, dis_style_immediate, "%d", align);
9390 }
9391 func (stream, dis_style_text, "]");
16980d0b 9392 if (rm == 0xd)
6576bffe 9393 func (stream, dis_style_text, "!");
16980d0b 9394 else if (rm != 0xf)
6576bffe
AB		 9395 {
9396 func (stream, dis_style_text, ", ");
9397 func (stream, dis_style_register, "%s",
9398 arm_regnames[rm]);
9399 }
16980d0b
JB		 9400 }
9401 break;
43e65147 9402
16980d0b
JB		 9403 case 'C':
9404 {
9405 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9406 int rn = ((given >> 16) & 0xf);
9407 int rm = ((given >> 0) & 0xf);
9408 int align = ((given >> 4) & 0x1);
9409 int size = ((given >> 6) & 0x3);
9410 int type = ((given >> 8) & 0x3);
9411 int n = type + 1;
9412 int stride = ((given >> 5) & 0x1);
9413 int ix;
43e65147 9414
16980d0b
JB		 9415 if (stride && (n == 1))
9416 n++;
9417 else
9418 stride++;
43e65147 9419
6576bffe 9420 func (stream, dis_style_text, "{");
16980d0b
JB		 9421 if (stride > 1)
9422 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9423 {
9424 if (ix > 0)
9425 func (stream, dis_style_text, ",");
9426 func (stream, dis_style_register, "d%d[]",
9427 rd + ix * stride);
9428 }
16980d0b 9429 else if (n == 1)
6576bffe 9430 func (stream, dis_style_register, "d%d[]", rd);
16980d0b 9431 else
6576bffe
AB		 9432 {
9433 func (stream, dis_style_register, "d%d[]", rd);
9434 func (stream, dis_style_text, "-");
9435 func (stream, dis_style_register, "d%d[]",
9436 rd + n - 1);
9437 }
9438 func (stream, dis_style_text, "}, [");
9439 func (stream, dis_style_register, "%s",
9440 arm_regnames[rn]);
16980d0b
JB		 9441 if (align)
9442 {
91d6fa6a 9443 align = (8 * (type + 1)) << size;
16980d0b
JB		 9444 if (type == 3)
9445 align = (size > 1) ? align >> 1 : align;
9446 if (type == 2 || (type == 0 && !size))
6576bffe
AB		 9447 func (stream, dis_style_text,
9448 " :<bad align %d>", align);
16980d0b 9449 else
6576bffe
AB		 9450 {
9451 func (stream, dis_style_text, " :");
9452 func (stream, dis_style_immediate,
9453 "%d", align);
9454 }
16980d0b 9455 }
6576bffe 9456 func (stream, dis_style_text, "]");
16980d0b 9457 if (rm == 0xd)
6576bffe 9458 func (stream, dis_style_text, "!");
16980d0b 9459 else if (rm != 0xf)
6576bffe
AB		 9460 {
9461 func (stream, dis_style_text, ", ");
9462 func (stream, dis_style_register, "%s",
9463 arm_regnames[rm]);
9464 }
16980d0b
JB		 9465 }
9466 break;
43e65147 9467
16980d0b
JB		 9468 case 'D':
9469 {
9470 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9471 int size = (given >> 20) & 3;
9472 int reg = raw_reg & ((4 << size) - 1);
9473 int ix = raw_reg >> size >> 2;
43e65147 9474
6576bffe 9475 func (stream, dis_style_register, "d%d[%d]", reg, ix);
16980d0b
JB		 9476 }
9477 break;
43e65147 9478
16980d0b 9479 case 'E':
fe56b6ce 9480 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9481 {
9482 int bits = 0;
9483 int cmode = (given >> 8) & 0xf;
9484 int op = (given >> 5) & 0x1;
9485 unsigned long value = 0, hival = 0;
9486 unsigned shift;
9487 int size = 0;
0dbde4cf 9488 int isfloat = 0;
43e65147 9489
16980d0b
JB		 9490 bits |= ((given >> 24) & 1) << 7;
9491 bits |= ((given >> 16) & 7) << 4;
9492 bits |= ((given >> 0) & 15) << 0;
43e65147 9493
16980d0b
JB		 9494 if (cmode < 8)
9495 {
9496 shift = (cmode >> 1) & 3;
fe56b6ce 9497 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9498 size = 32;
9499 }
9500 else if (cmode < 12)
9501 {
9502 shift = (cmode >> 1) & 1;
fe56b6ce 9503 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9504 size = 16;
9505 }
9506 else if (cmode < 14)
9507 {
9508 shift = (cmode & 1) + 1;
fe56b6ce 9509 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9510 value |= (1ul << (8 * shift)) - 1;
9511 size = 32;
9512 }
9513 else if (cmode == 14)
9514 {
9515 if (op)
9516 {
fe56b6ce 9517 /* Bit replication into bytes. */
16980d0b
JB		 9518 int ix;
9519 unsigned long mask;
43e65147 9520
16980d0b
JB		 9521 value = 0;
9522 hival = 0;
9523 for (ix = 7; ix >= 0; ix--)
9524 {
9525 mask = ((bits >> ix) & 1) ? 0xff : 0;
9526 if (ix <= 3)
9527 value = (value << 8) | mask;
9528 else
9529 hival = (hival << 8) | mask;
9530 }
9531 size = 64;
9532 }
9533 else
9534 {
fe56b6ce
NC		 9535 /* Byte replication. */
9536 value = (unsigned long) bits;
16980d0b
JB		 9537 size = 8;
9538 }
9539 }
9540 else if (!op)
9541 {
fe56b6ce 9542 /* Floating point encoding. */
16980d0b 9543 int tmp;
43e65147 9544
fe56b6ce
NC		 9545 value = (unsigned long) (bits & 0x7f) << 19;
9546 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9547 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9548 value |= (unsigned long) tmp << 24;
16980d0b 9549 size = 32;
0dbde4cf 9550 isfloat = 1;
16980d0b
JB		 9551 }
9552 else
9553 {
6576bffe
AB		 9554 func (stream, dis_style_text,
9555 "<illegal constant %.8x:%x:%x>",
16980d0b
JB		 9556 bits, cmode, op);
9557 size = 32;
9558 break;
9559 }
9560 switch (size)
9561 {
9562 case 8:
6576bffe
AB		 9563 func (stream, dis_style_immediate, "#%ld", value);
9564 func (stream, dis_style_comment_start,
9565 "\t@ 0x%.2lx", value);
16980d0b 9566 break;
43e65147 9567
16980d0b 9568 case 16:
6576bffe
AB		 9569 func (stream, dis_style_immediate, "#%ld", value);
9570 func (stream, dis_style_comment_start,
9571 "\t@ 0x%.4lx", value);
16980d0b
JB		 9572 break;
9573
9574 case 32:
0dbde4cf
JB		 9575 if (isfloat)
9576 {
9577 unsigned char valbytes[4];
9578 double fvalue;
43e65147 9579
0dbde4cf
JB		 9580 /* Do this a byte at a time so we don't have to
9581 worry about the host's endianness. */
9582 valbytes[0] = value & 0xff;
9583 valbytes[1] = (value >> 8) & 0xff;
9584 valbytes[2] = (value >> 16) & 0xff;
9585 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9586
9587 floatformat_to_double
c1e26897
NC		 9588 (& floatformat_ieee_single_little, valbytes,
9589 & fvalue);
43e65147 9590
6576bffe
AB		 9591 func (stream, dis_style_immediate,
9592 "#%.7g", fvalue);
9593 func (stream, dis_style_comment_start,
9594 "\t@ 0x%.8lx", value);
0dbde4cf
JB		 9595 }
9596 else
6576bffe
AB		 9597 {
9598 func (stream, dis_style_immediate, "#%ld",
9599 (long) (((value & 0x80000000L) != 0)
9600 ? value | ~0xffffffffL : value));
9601 func (stream, dis_style_comment_start,
9602 "\t@ 0x%.8lx", value);
9603 }
16980d0b
JB		 9604 break;
9605
9606 case 64:
6576bffe
AB		 9607 func (stream, dis_style_immediate,
9608 "#0x%.8lx%.8lx", hival, value);
16980d0b 9609 break;
43e65147 9610
16980d0b
JB		 9611 default:
9612 abort ();
9613 }
9614 }
9615 break;
43e65147 9616
16980d0b
JB		 9617 case 'F':
9618 {
9619 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9620 int num = (given >> 8) & 0x3;
43e65147 9621
6576bffe 9622 func (stream, dis_style_text, "{");
16980d0b 9623 if (!num)
6576bffe 9624 func (stream, dis_style_register, "d%d", regno);
16980d0b 9625 else if (num + regno >= 32)
6576bffe
AB		 9626 {
9627 func (stream, dis_style_register, "d%d", regno);
9628 func (stream, dis_style_text, "-<overflow reg d%d",
9629 regno + num);
9630 }
16980d0b 9631 else
6576bffe
AB		 9632 {
9633 func (stream, dis_style_register, "d%d", regno);
9634 func (stream, dis_style_text, "-");
9635 func (stream, dis_style_register, "d%d",
9636 regno + num);
9637 }
9638 func (stream, dis_style_text, "}");
16980d0b
JB		 9639 }
9640 break;
7e8e6784 9641
16980d0b
JB		 9642
9643 case '0': case '1': case '2': case '3': case '4':
9644 case '5': case '6': case '7': case '8': case '9':
9645 {
9646 int width;
9647 unsigned long value;
9648
9649 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9650
16980d0b
JB		 9651 switch (*c)
9652 {
9653 case 'r':
6576bffe
AB		 9654 func (stream, dis_style_register, "%s",
9655 arm_regnames[value]);
16980d0b
JB		 9656 break;
9657 case 'd':
6576bffe 9658 func (stream, base_style, "%ld", value);
05413229 9659 value_in_comment = value;
16980d0b
JB		 9660 break;
9661 case 'e':
6576bffe
AB		 9662 func (stream, dis_style_immediate, "%ld",
9663 (1ul << width) - value);
16980d0b 9664 break;
43e65147 9665
16980d0b
JB		 9666 case 'S':
9667 case 'T':
9668 case 'U':
05413229 9669 /* Various width encodings. */
16980d0b
JB		 9670 {
9671 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9672 int limit;
9673 unsigned low, high;
9674
9675 c++;
9676 if (*c >= '0' && *c <= '9')
9677 limit = *c - '0';
9678 else if (*c >= 'a' && *c <= 'f')
9679 limit = *c - 'a' + 10;
9680 else
9681 abort ();
9682 low = limit >> 2;
9683 high = limit & 3;
9684
9685 if (value < low || value > high)
6576bffe
AB		 9686 func (stream, dis_style_text,
9687 "<illegal width %d>", base << value);
16980d0b 9688 else
6576bffe
AB		 9689 func (stream, base_style, "%d",
9690 base << value);
16980d0b
JB		 9691 }
9692 break;
9693 case 'R':
9694 if (given & (1 << 6))
9695 goto Q;
9696 /* FALLTHROUGH */
9697 case 'D':
6576bffe 9698 func (stream, dis_style_register, "d%ld", value);
16980d0b
JB		 9699 break;
9700 case 'Q':
9701 Q:
9702 if (value & 1)
6576bffe
AB		 9703 func (stream, dis_style_text,
9704 "<illegal reg q%ld.5>", value >> 1);
16980d0b 9705 else
6576bffe
AB		 9706 func (stream, dis_style_register,
9707 "q%ld", value >> 1);
16980d0b 9708 break;
43e65147 9709
16980d0b
JB		 9710 case '`':
9711 c++;
9712 if (value == 0)
6576bffe 9713 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9714 break;
9715 case '\'':
9716 c++;
9717 if (value == ((1ul << width) - 1))
6576bffe 9718 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9719 break;
9720 case '?':
6576bffe
AB		 9721 func (stream, dis_style_mnemonic, "%c",
9722 c[(1 << width) - (int) value]);
16980d0b
JB		 9723 c += 1 << width;
9724 break;
9725 default:
9726 abort ();
9727 }
16980d0b 9728 }
dffaa15c
AM		 9729 break;
9730
9731 default:
9732 abort ();
16980d0b
JB		 9733 }
9734 }
9735 else
6576bffe
AB		 9736 {
9737 if (*c == '@')
9738 base_style = dis_style_comment_start;
9739
9740 if (*c == '\t')
9741 base_style = dis_style_text;
9742
9743 func (stream, base_style, "%c", *c);
9744
9745 }
16980d0b 9746 }
05413229
NC		 9747
9748 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 9749 func (stream, dis_style_comment_start, "\t@ 0x%lx",
9750 value_in_comment);
05413229 9751
e2efe87d 9752 if (is_unpredictable)
6576bffe 9753 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
e2efe87d 9754
78933a4a 9755 return true;
16980d0b
JB		 9756 }
9757 }
78933a4a 9758 return false;
16980d0b
JB		 9759}
9760
73cd51e5
AV		 9761/* Print one mve instruction on INFO->STREAM.
9762 Return TRUE if the instuction matched, FALSE if this is not a
9763 recognised mve instruction. */
9764
78933a4a 9765static bool
73cd51e5
AV		 9766print_insn_mve (struct disassemble_info *info, long given)
9767{
9768 const struct mopcode32 *insn;
9769 void *stream = info->stream;
6576bffe
AB		 9770 fprintf_styled_ftype func = info->fprintf_styled_func;
9771 enum disassembler_style base_style = dis_style_mnemonic;
9772 enum disassembler_style old_base_style = base_style;
73cd51e5
AV		 9773
9774 for (insn = mve_opcodes; insn->assembler; insn++)
9775 {
9776 if (((given & insn->mask) == insn->value)
9777 && !is_mve_encoding_conflict (given, insn->mve_op))
9778 {
9779 signed long value_in_comment = 0;
78933a4a
AM		 9780 bool is_unpredictable = false;
9781 bool is_undefined = false;
73cd51e5
AV		 9782 const char *c;
9783 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9784 enum mve_undefined undefined_cond = UNDEF_NONE;
9785
9786 /* Most vector mve instruction are illegal in a it block.
9787 There are a few exceptions; check for them. */
9788 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9789 {
78933a4a 9790 is_unpredictable = true;
73cd51e5
AV		 9791 unpredictable_cond = UNPRED_IT_BLOCK;
9792 }
9793 else if (is_mve_unpredictable (given, insn->mve_op,
9794 &unpredictable_cond))
78933a4a 9795 is_unpredictable = true;
73cd51e5
AV		 9796
9797 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
78933a4a 9798 is_undefined = true;
73cd51e5 9799
c4a23bf8
SP		 9800 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9801 i.e "VMOV Qd, Qm". */
9802 if ((insn->mve_op == MVE_VORR_REG)
9803 && (arm_decode_field (given, 1, 3)
9804 == arm_decode_field (given, 17, 19)))
9805 continue;
9806
73cd51e5
AV		 9807 for (c = insn->assembler; *c; c++)
9808 {
9809 if (*c == '%')
9810 {
9811 switch (*++c)
9812 {
6576bffe
AB		 9813 case '{':
9814 ++c;
9815 if (*c == '\0')
9816 abort ();
9817 old_base_style = base_style;
9818 base_style = decode_base_style (*c);
9819 ++c;
9820 if (*c != ':')
9821 abort ();
9822 break;
9823
9824 case '}':
9825 base_style = old_base_style;
9826 break;
9827
73cd51e5 9828 case '%':
6576bffe 9829 func (stream, base_style, "%%");
73cd51e5
AV		 9830 break;
9831
ef1576a1
AV		 9832 case 'a':
9833 /* Don't print anything for '+' as it is implied. */
9834 if (arm_decode_field (given, 23, 23) == 0)
6576bffe 9835 func (stream, dis_style_immediate, "-");
ef1576a1
AV		 9836 break;
9837
143275ea
AV		 9838 case 'c':
9839 if (ifthen_state)
6576bffe
AB		 9840 func (stream, dis_style_mnemonic, "%s",
9841 arm_conditional[IFTHEN_COND]);
143275ea
AV		 9842 break;
9843
aef6d006
AV		 9844 case 'd':
9845 print_mve_vld_str_addr (info, given, insn->mve_op);
9846 break;
9847
143275ea
AV		 9848 case 'i':
9849 {
9850 long mve_mask = mve_extract_pred_mask (given);
6576bffe
AB		 9851 func (stream, dis_style_mnemonic, "%s",
9852 mve_predicatenames[mve_mask]);
143275ea
AV		 9853 }
9854 break;
9855
23d00a41
SD		 9856 case 'j':
9857 {
9858 unsigned int imm5 = 0;
9859 imm5 |= arm_decode_field (given, 6, 7);
9860 imm5 |= (arm_decode_field (given, 12, 14) << 2);
6576bffe
AB		 9861 func (stream, dis_style_immediate, "#%u",
9862 (imm5 == 0) ? 32 : imm5);
23d00a41
SD		 9863 }
9864 break;
9865
08132bdd 9866 case 'k':
6576bffe 9867 func (stream, dis_style_immediate, "#%u",
08132bdd
SP		 9868 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9869 break;
9870
143275ea
AV		 9871 case 'n':
9872 print_vec_condition (info, given, insn->mve_op);
9873 break;
9874
ef1576a1
AV		 9875 case 'o':
9876 if (arm_decode_field (given, 0, 0) == 1)
9877 {
9878 unsigned long size
9879 = arm_decode_field (given, 4, 4)
9880 | (arm_decode_field (given, 6, 6) << 1);
9881
6576bffe
AB		 9882 func (stream, dis_style_text, ", ");
9883 func (stream, dis_style_sub_mnemonic, "uxtw ");
9884 func (stream, dis_style_immediate, "#%lu", size);
ef1576a1
AV		 9885 }
9886 break;
9887
bf0b396d
AV		 9888 case 'm':
9889 print_mve_rounding_mode (info, given, insn->mve_op);
9890 break;
9891
9892 case 's':
9893 print_mve_vcvt_size (info, given, insn->mve_op);
9894 break;
9895
aef6d006
AV		 9896 case 'u':
9897 {
c507f10b
AV		 9898 unsigned long op1 = arm_decode_field (given, 21, 22);
9899
9900 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9901 {
9902 /* Check for signed. */
9903 if (arm_decode_field (given, 23, 23) == 0)
9904 {
9905 /* We don't print 's' for S32. */
9906 if ((arm_decode_field (given, 5, 6) == 0)
9907 && ((op1 == 0) || (op1 == 1)))
9908 ;
9909 else
6576bffe 9910 func (stream, dis_style_mnemonic, "s");
c507f10b
AV		 9911 }
9912 else
6576bffe 9913 func (stream, dis_style_mnemonic, "u");
c507f10b 9914 }
aef6d006 9915 else
c507f10b
AV		 9916 {
9917 if (arm_decode_field (given, 28, 28) == 0)
6576bffe 9918 func (stream, dis_style_mnemonic, "s");
c507f10b 9919 else
6576bffe 9920 func (stream, dis_style_mnemonic, "u");
c507f10b 9921 }
aef6d006 9922 }
ef1576a1 9923 break;
aef6d006 9924
143275ea
AV		 9925 case 'v':
9926 print_instruction_predicate (info);
9927 break;
9928
04d54ace
AV		 9929 case 'w':
9930 if (arm_decode_field (given, 21, 21) == 1)
6576bffe 9931 func (stream, dis_style_text, "!");
04d54ace
AV		 9932 break;
9933
9934 case 'B':
9935 print_mve_register_blocks (info, given, insn->mve_op);
9936 break;
9937
c507f10b
AV		 9938 case 'E':
9939 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9940
9941 print_simd_imm8 (info, given, 28, insn);
9942 break;
9943
9944 case 'N':
9945 print_mve_vmov_index (info, given);
9946 break;
9947
14925797
AV		 9948 case 'T':
9949 if (arm_decode_field (given, 12, 12) == 0)
6576bffe 9950 func (stream, dis_style_mnemonic, "b");
14925797 9951 else
6576bffe 9952 func (stream, dis_style_mnemonic, "t");
14925797
AV		 9953 break;
9954
d3b63143
AV		 9955 case 'X':
9956 if (arm_decode_field (given, 12, 12) == 1)
6576bffe 9957 func (stream, dis_style_mnemonic, "x");
d3b63143
AV		 9958 break;
9959
143275ea
AV		 9960 case '0': case '1': case '2': case '3': case '4':
9961 case '5': case '6': case '7': case '8': case '9':
9962 {
9963 int width;
9964 unsigned long value;
9965
9966 c = arm_decode_bitfield (c, given, &value, &width);
9967
9968 switch (*c)
9969 {
9970 case 'Z':
9971 if (value == 13)
78933a4a 9972 is_unpredictable = true;
143275ea 9973 else if (value == 15)
6576bffe 9974 func (stream, dis_style_register, "zr");
143275ea 9975 else
6576bffe
AB		 9976 func (stream, dis_style_register, "%s",
9977 arm_regnames[value]);
143275ea 9978 break;
23d00a41 9979
e39c1607 9980 case 'c':
6576bffe
AB		 9981 func (stream, dis_style_sub_mnemonic, "%s",
9982 arm_conditional[value]);
e39c1607
SD		 9983 break;
9984
9985 case 'C':
9986 value ^= 1;
6576bffe
AB		 9987 func (stream, dis_style_sub_mnemonic, "%s",
9988 arm_conditional[value]);
e39c1607
SD		 9989 break;
9990
23d00a41
SD		 9991 case 'S':
9992 if (value == 13 || value == 15)
78933a4a 9993 is_unpredictable = true;
23d00a41 9994 else
6576bffe
AB		 9995 func (stream, dis_style_register, "%s",
9996 arm_regnames[value]);
23d00a41
SD		 9997 break;
9998
143275ea
AV		 9999 case 's':
10000 print_mve_size (info,
10001 value,
10002 insn->mve_op);
10003 break;
66dcaa5d
AV		 10004 case 'I':
10005 if (value == 1)
6576bffe 10006 func (stream, dis_style_mnemonic, "i");
66dcaa5d 10007 break;
d3b63143
AV		 10008 case 'A':
10009 if (value == 1)
6576bffe 10010 func (stream, dis_style_mnemonic, "a");
d3b63143 10011 break;
1c8f2df8
AV		 10012 case 'h':
10013 {
10014 unsigned int odd_reg = (value << 1) | 1;
6576bffe
AB		 10015 func (stream, dis_style_register, "%s",
10016 arm_regnames[odd_reg]);
1c8f2df8
AV		 10017 }
10018 break;
ef1576a1
AV		 10019 case 'i':
10020 {
10021 unsigned long imm
10022 = arm_decode_field (given, 0, 6);
10023 unsigned long mod_imm = imm;
10024
10025 switch (insn->mve_op)
10026 {
10027 case MVE_VLDRW_GATHER_T5:
10028 case MVE_VSTRW_SCATTER_T5:
10029 mod_imm = mod_imm << 2;
10030 break;
10031 case MVE_VSTRD_SCATTER_T6:
10032 case MVE_VLDRD_GATHER_T6:
10033 mod_imm = mod_imm << 3;
10034 break;
10035
10036 default:
10037 break;
10038 }
10039
6576bffe
AB		 10040 func (stream, dis_style_immediate, "%lu",
10041 mod_imm);
ef1576a1
AV		 10042 }
10043 break;
bf0b396d 10044 case 'k':
6576bffe
AB		 10045 func (stream, dis_style_immediate, "%lu",
10046 64 - value);
bf0b396d 10047 break;
1c8f2df8
AV		 10048 case 'l':
10049 {
10050 unsigned int even_reg = value << 1;
6576bffe
AB		 10051 func (stream, dis_style_register, "%s",
10052 arm_regnames[even_reg]);
1c8f2df8
AV		 10053 }
10054 break;
10055 case 'u':
10056 switch (value)
10057 {
10058 case 0:
6576bffe 10059 func (stream, dis_style_immediate, "1");
1c8f2df8
AV		 10060 break;
10061 case 1:
6576bffe 10062 func (stream, dis_style_immediate, "2");
1c8f2df8
AV		 10063 break;
10064 case 2:
6576bffe 10065 func (stream, dis_style_immediate, "4");
1c8f2df8
AV		 10066 break;
10067 case 3:
6576bffe 10068 func (stream, dis_style_immediate, "8");
1c8f2df8
AV		 10069 break;
10070 default:
10071 break;
10072 }
10073 break;
897b9bbc
AV		 10074 case 'o':
10075 print_mve_rotate (info, value, width);
10076 break;
9743db03 10077 case 'r':
6576bffe
AB		 10078 func (stream, dis_style_register, "%s",
10079 arm_regnames[value]);
9743db03 10080 break;
04d54ace 10081 case 'd':
f9d6cf2e 10082 if (mve_shift_insn_p (insn->mve_op))
ed63aa17
AV		 10083 print_mve_shift_n (info, given, insn->mve_op);
10084 else if (insn->mve_op == MVE_VSHLL_T2)
10085 {
10086 switch (value)
10087 {
10088 case 0x00:
6576bffe 10089 func (stream, dis_style_immediate, "8");
ed63aa17
AV		 10090 break;
10091 case 0x01:
6576bffe 10092 func (stream, dis_style_immediate, "16");
ed63aa17
AV		 10093 break;
10094 case 0x10:
10095 print_mve_undefined (info, UNDEF_SIZE_0);
10096 break;
10097 default:
10098 assert (0);
10099 break;
10100 }
10101 }
10102 else
10103 {
10104 if (insn->mve_op == MVE_VSHLC && value == 0)
10105 value = 32;
6576bffe 10106 func (stream, base_style, "%ld", value);
ed63aa17
AV		 10107 value_in_comment = value;
10108 }
04d54ace 10109 break;
c507f10b 10110 case 'F':
6576bffe 10111 func (stream, dis_style_register, "s%ld", value);
c507f10b 10112 break;
143275ea
AV		 10113 case 'Q':
10114 if (value & 0x8)
6576bffe
AB		 10115 func (stream, dis_style_text,
10116 "<illegal reg q%ld.5>", value);
143275ea 10117 else
6576bffe 10118 func (stream, dis_style_register, "q%ld", value);
143275ea 10119 break;
c507f10b 10120 case 'x':
6576bffe
AB		 10121 func (stream, dis_style_immediate,
10122 "0x%08lx", value);
c507f10b 10123 break;
143275ea
AV		 10124 default:
10125 abort ();
10126 }
10127 break;
10128 default:
10129 abort ();
10130 }
73cd51e5
AV		 10131 }
10132 }
10133 else
6576bffe
AB		 10134 {
10135 if (*c == '@')
10136 base_style = dis_style_comment_start;
10137
10138 if (*c == '\t')
10139 base_style = dis_style_text;
10140
10141 func (stream, base_style, "%c", *c);
10142 }
73cd51e5
AV		 10143 }
10144
10145 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10146 func (stream, dis_style_comment_start, "\t@ 0x%lx",
10147 value_in_comment);
73cd51e5
AV		 10148
10149 if (is_unpredictable)
10150 print_mve_unpredictable (info, unpredictable_cond);
10151
10152 if (is_undefined)
10153 print_mve_undefined (info, undefined_cond);
10154
63b4cc53 10155 if (!vpt_block_state.in_vpt_block
143275ea 10156 && !ifthen_state
63b4cc53 10157 && is_vpt_instruction (given))
143275ea 10158 mark_inside_vpt_block (given);
63b4cc53 10159 else if (vpt_block_state.in_vpt_block)
143275ea
AV		 10160 update_vpt_block_state ();
10161
78933a4a 10162 return true;
73cd51e5
AV		 10163 }
10164 }
78933a4a 10165 return false;
73cd51e5
AV		 10166}
10167
10168
90ec0d68
MGD		 10169/* Return the name of a v7A special register. */
10170
43e65147 10171static const char *
90ec0d68
MGD		 10172banked_regname (unsigned reg)
10173{
10174 switch (reg)
10175 {
10176 case 15: return "CPSR";
43e65147 10177 case 32: return "R8_usr";
90ec0d68
MGD		 10178 case 33: return "R9_usr";
10179 case 34: return "R10_usr";
10180 case 35: return "R11_usr";
10181 case 36: return "R12_usr";
10182 case 37: return "SP_usr";
10183 case 38: return "LR_usr";
43e65147 10184 case 40: return "R8_fiq";
90ec0d68
MGD		 10185 case 41: return "R9_fiq";
10186 case 42: return "R10_fiq";
10187 case 43: return "R11_fiq";
10188 case 44: return "R12_fiq";
10189 case 45: return "SP_fiq";
10190 case 46: return "LR_fiq";
10191 case 48: return "LR_irq";
10192 case 49: return "SP_irq";
10193 case 50: return "LR_svc";
10194 case 51: return "SP_svc";
10195 case 52: return "LR_abt";
10196 case 53: return "SP_abt";
10197 case 54: return "LR_und";
10198 case 55: return "SP_und";
10199 case 60: return "LR_mon";
10200 case 61: return "SP_mon";
10201 case 62: return "ELR_hyp";
10202 case 63: return "SP_hyp";
10203 case 79: return "SPSR";
10204 case 110: return "SPSR_fiq";
10205 case 112: return "SPSR_irq";
10206 case 114: return "SPSR_svc";
10207 case 116: return "SPSR_abt";
10208 case 118: return "SPSR_und";
10209 case 124: return "SPSR_mon";
10210 case 126: return "SPSR_hyp";
10211 default: return NULL;
10212 }
10213}
10214
e797f7e0
MGD		 10215/* Return the name of the DMB/DSB option. */
10216static const char *
10217data_barrier_option (unsigned option)
10218{
10219 switch (option & 0xf)
10220 {
10221 case 0xf: return "sy";
10222 case 0xe: return "st";
10223 case 0xd: return "ld";
10224 case 0xb: return "ish";
10225 case 0xa: return "ishst";
10226 case 0x9: return "ishld";
10227 case 0x7: return "un";
10228 case 0x6: return "unst";
10229 case 0x5: return "nshld";
10230 case 0x3: return "osh";
10231 case 0x2: return "oshst";
10232 case 0x1: return "oshld";
10233 default: return NULL;
10234 }
10235}
10236
4a5329c6
ZW		 10237/* Print one ARM instruction from PC on INFO->STREAM. */
10238
10239static void
10240print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10241{
6b5d3a4d 10242 const struct opcode32 *insn;
6a51a8a8 10243 void *stream = info->stream;
6576bffe 10244 fprintf_styled_ftype func = info->fprintf_styled_func;
b0e28b39 10245 struct arm_private_data *private_data = info->private_data;
6576bffe
AB		 10246 enum disassembler_style base_style = dis_style_mnemonic;
10247 enum disassembler_style old_base_style = base_style;
252b5132 10248
78933a4a 10249 if (print_insn_coprocessor (pc, info, given, false))
16980d0b
JB		 10250 return;
10251
78933a4a 10252 if (print_insn_neon (info, given, false))
8f06b2d8
PB		 10253 return;
10254
78933a4a 10255 if (print_insn_generic_coprocessor (pc, info, given, false))
33593eaf
MM		 10256 return;
10257
252b5132
RH		 10258 for (insn = arm_opcodes; insn->assembler; insn++)
10259 {
0313a2b8
NC		 10260 if ((given & insn->mask) != insn->value)
10261 continue;
823d2571
TG		 10262
10263 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 10264 continue;
10265
10266 /* Special case: an instruction with all bits set in the condition field
10267 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10268 or by the catchall at the end of the table. */
10269 if ((given & 0xF0000000) != 0xF0000000
10270 || (insn->mask & 0xF0000000) == 0xF0000000
10271 || (insn->mask == 0 && insn->value == 0))
252b5132 10272 {
ff4a8d2b
NC		 10273 unsigned long u_reg = 16;
10274 unsigned long U_reg = 16;
78933a4a 10275 bool is_unpredictable = false;
05413229 10276 signed long value_in_comment = 0;
6b5d3a4d 10277 const char *c;
b34976b6 10278
252b5132
RH		 10279 for (c = insn->assembler; *c; c++)
10280 {
10281 if (*c == '%')
10282 {
78933a4a 10283 bool allow_unpredictable = false;
c1e26897 10284
252b5132
RH		 10285 switch (*++c)
10286 {
6576bffe
AB		 10287 case '{':
10288 ++c;
10289 if (*c == '\0')
10290 abort ();
10291 old_base_style = base_style;
10292 base_style = decode_base_style (*c);
10293 ++c;
10294 if (*c != ':')
10295 abort ();
10296 break;
10297
10298 case '}':
10299 base_style = old_base_style;
10300 break;
10301
252b5132 10302 case '%':
6576bffe 10303 func (stream, base_style, "%%");
252b5132
RH		 10304 break;
10305
10306 case 'a':
05413229 10307 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10308 break;
252b5132 10309
62b3e311
PB		 10310 case 'P':
10311 /* Set P address bit and use normal address
10312 printing routine. */
c1e26897 10313 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10314 break;
10315
c1e26897 10316 case 'S':
78933a4a 10317 allow_unpredictable = true;
1a0670f3 10318 /* Fall through. */
252b5132
RH		 10319 case 's':
10320 if ((given & 0x004f0000) == 0x004f0000)
10321 {
58efb6c0 10322 /* PC relative with immediate offset. */
f8b960bc 10323 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10324
aefd8a40
NC		 10325 if (PRE_BIT_SET)
10326 {
26d97720
NS		 10327 /* Elide positive zero offset. */
10328 if (offset || NEGATIVE_BIT_SET)
6576bffe
AB		 10329 {
10330 func (stream, dis_style_text, "[");
10331 func (stream, dis_style_register, "pc");
10332 func (stream, dis_style_text, ", ");
10333 func (stream, dis_style_immediate, "#%s%d",
10334 (NEGATIVE_BIT_SET ? "-" : ""),
10335 (int) offset);
10336 func (stream, dis_style_text, "]");
10337 }
945ee430 10338 else
6576bffe
AB		 10339 {
10340 func (stream, dis_style_text, "[");
10341 func (stream, dis_style_register, "pc");
10342 func (stream, dis_style_text, "]");
10343 }
26d97720
NS		 10344 if (NEGATIVE_BIT_SET)
10345 offset = -offset;
6576bffe 10346 func (stream, dis_style_comment_start, "\t@ ");
aefd8a40
NC		 10347 info->print_address_func (offset + pc + 8, info);
10348 }
10349 else
10350 {
26d97720 10351 /* Always show the offset. */
6576bffe
AB		 10352 func (stream, dis_style_text, "[");
10353 func (stream, dis_style_register, "pc");
10354 func (stream, dis_style_text, "], ");
10355 func (stream, dis_style_immediate, "#%s%d",
d908c8af 10356 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b 10357 if (! allow_unpredictable)
78933a4a 10358 is_unpredictable = true;
aefd8a40 10359 }
252b5132
RH		 10360 }
10361 else
10362 {
fe56b6ce
NC		 10363 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10364
6576bffe
AB		 10365 func (stream, dis_style_text, "[");
10366 func (stream, dis_style_register, "%s",
252b5132 10367 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10368
c1e26897 10369 if (PRE_BIT_SET)
252b5132 10370 {
c1e26897 10371 if (IMMEDIATE_BIT_SET)
252b5132 10372 {
26d97720
NS		 10373 /* Elide offset for non-writeback
10374 positive zero. */
10375 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10376 || offset)
6576bffe
AB		 10377 {
10378 func (stream, dis_style_text, ", ");
10379 func (stream, dis_style_immediate,
10380 "#%s%d",
10381 (NEGATIVE_BIT_SET ? "-" : ""),
10382 offset);
10383 }
26d97720
NS		 10384
10385 if (NEGATIVE_BIT_SET)
10386 offset = -offset;
945ee430 10387
fe56b6ce 10388 value_in_comment = offset;
252b5132 10389 }
945ee430 10390 else
ff4a8d2b
NC		 10391 {
10392 /* Register Offset or Register Pre-Indexed. */
6576bffe
AB		 10393 func (stream, dis_style_text, ", %s",
10394 NEGATIVE_BIT_SET ? "-" : "");
10395 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10396 arm_regnames[given & 0xf]);
10397
10398 /* Writing back to the register that is the source/
10399 destination of the load/store is unpredictable. */
10400 if (! allow_unpredictable
10401 && WRITEBACK_BIT_SET
10402 && ((given & 0xf) == ((given >> 12) & 0xf)))
78933a4a 10403 is_unpredictable = true;
ff4a8d2b 10404 }
252b5132 10405
6576bffe 10406 func (stream, dis_style_text, "]%s",
c1e26897 10407 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10408 }
945ee430 10409 else
252b5132 10410 {
c1e26897 10411 if (IMMEDIATE_BIT_SET)
252b5132 10412 {
945ee430 10413 /* Immediate Post-indexed. */
aefd8a40 10414 /* PR 10924: Offset must be printed, even if it is zero. */
6576bffe
AB		 10415 func (stream, dis_style_text, "], ");
10416 func (stream, dis_style_immediate, "#%s%d",
26d97720
NS		 10417 NEGATIVE_BIT_SET ? "-" : "", offset);
10418 if (NEGATIVE_BIT_SET)
10419 offset = -offset;
fe56b6ce 10420 value_in_comment = offset;
252b5132 10421 }
945ee430 10422 else
ff4a8d2b
NC		 10423 {
10424 /* Register Post-indexed. */
6576bffe
AB		 10425 func (stream, dis_style_text, "], %s",
10426 NEGATIVE_BIT_SET ? "-" : "");
10427 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10428 arm_regnames[given & 0xf]);
10429
10430 /* Writing back to the register that is the source/
10431 destination of the load/store is unpredictable. */
10432 if (! allow_unpredictable
10433 && (given & 0xf) == ((given >> 12) & 0xf))
78933a4a 10434 is_unpredictable = true;
ff4a8d2b 10435 }
c1e26897 10436
07a28fab
NC		 10437 if (! allow_unpredictable)
10438 {
10439 /* Writeback is automatically implied by post- addressing.
10440 Setting the W bit is unnecessary and ARM specify it as
10441 being unpredictable. */
10442 if (WRITEBACK_BIT_SET
10443 /* Specifying the PC register as the post-indexed
10444 registers is also unpredictable. */
ab8e2090 10445 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
78933a4a 10446 is_unpredictable = true;
07a28fab 10447 }
252b5132
RH		 10448 }
10449 }
10450 break;
b34976b6 10451
252b5132 10452 case 'b':
6b5d3a4d 10453 {
f8b960bc 10454 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10455 bfd_vma target = disp * 4 + pc + 8;
10456 info->print_address_func (target, info);
10457
10458 /* Fill in instruction information. */
10459 info->insn_info_valid = 1;
10460 info->insn_type = dis_branch;
10461 info->target = target;
6b5d3a4d 10462 }
252b5132
RH		 10463 break;
10464
10465 case 'c':
c22aaad1 10466 if (((given >> 28) & 0xf) != 0xe)
6576bffe 10467 func (stream, dis_style_mnemonic, "%s",
c22aaad1 10468 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10469 break;
10470
10471 case 'm':
10472 {
10473 int started = 0;
10474 int reg;
10475
6576bffe 10476 func (stream, dis_style_text, "{");
252b5132
RH		 10477 for (reg = 0; reg < 16; reg++)
10478 if ((given & (1 << reg)) != 0)
10479 {
10480 if (started)
6576bffe 10481 func (stream, dis_style_text, ", ");
252b5132 10482 started = 1;
6576bffe
AB		 10483 func (stream, dis_style_register, "%s",
10484 arm_regnames[reg]);
252b5132 10485 }
6576bffe 10486 func (stream, dis_style_text, "}");
ab8e2090 10487 if (! started)
78933a4a 10488 is_unpredictable = true;
252b5132
RH		 10489 }
10490 break;
10491
37b37b2d 10492 case 'q':
78933a4a 10493 arm_decode_shift (given, func, stream, false);
37b37b2d
RE		 10494 break;
10495
252b5132
RH		 10496 case 'o':
10497 if ((given & 0x02000000) != 0)
10498 {
a415b1cd
JB		 10499 unsigned int rotate = (given & 0xf00) >> 7;
10500 unsigned int immed = (given & 0xff);
10501 unsigned int a, i;
10502
ebd1c6d1
AM		 10503 a = (immed << ((32 - rotate) & 31)
10504 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10505 /* If there is another encoding with smaller rotate,
10506 the rotate should be specified directly. */
10507 for (i = 0; i < 32; i += 2)
ebd1c6d1 10508 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10509 break;
10510
10511 if (i != rotate)
6576bffe
AB		 10512 {
10513 func (stream, dis_style_immediate, "#%d", immed);
10514 func (stream, dis_style_text, ", ");
10515 func (stream, dis_style_immediate, "%d", rotate);
10516 }
a415b1cd 10517 else
6576bffe 10518 func (stream, dis_style_immediate, "#%d", a);
a415b1cd 10519 value_in_comment = a;
252b5132
RH		 10520 }
10521 else
78933a4a 10522 arm_decode_shift (given, func, stream, true);
252b5132
RH		 10523 break;
10524
10525 case 'p':
10526 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10527 {
823d2571
TG		 10528 arm_feature_set arm_ext_v6 =
10529 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10530
aefd8a40
NC		 10531 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10532 mechanism for setting PSR flag bits. They are
10533 obsolete in V6 onwards. */
823d2571
TG		 10534 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10535 arm_ext_v6))
6576bffe 10536 func (stream, dis_style_mnemonic, "p");
4ab90a7a 10537 else
78933a4a 10538 is_unpredictable = true;
aefd8a40 10539 }
252b5132
RH		 10540 break;
10541
10542 case 't':
10543 if ((given & 0x01200000) == 0x00200000)
6576bffe 10544 func (stream, dis_style_mnemonic, "t");
252b5132
RH		 10545 break;
10546
252b5132 10547 case 'A':
05413229
NC		 10548 {
10549 int offset = given & 0xff;
f02232aa 10550
05413229 10551 value_in_comment = offset * 4;
c1e26897 10552 if (NEGATIVE_BIT_SET)
05413229 10553 value_in_comment = - value_in_comment;
f02232aa 10554
6576bffe
AB		 10555 func (stream, dis_style_text, "[%s",
10556 arm_regnames [(given >> 16) & 0xf]);
f02232aa 10557
c1e26897 10558 if (PRE_BIT_SET)
05413229
NC		 10559 {
10560 if (offset)
6576bffe 10561 func (stream, dis_style_text, ", #%d]%s",
d908c8af 10562 (int) value_in_comment,
c1e26897 10563 WRITEBACK_BIT_SET ? "!" : "");
05413229 10564 else
6576bffe 10565 func (stream, dis_style_text, "]");
05413229
NC		 10566 }
10567 else
10568 {
6576bffe 10569 func (stream, dis_style_text, "]");
f02232aa 10570
c1e26897 10571 if (WRITEBACK_BIT_SET)
05413229
NC		 10572 {
10573 if (offset)
6576bffe
AB		 10574 func (stream, dis_style_text,
10575 ", #%d", (int) value_in_comment);
05413229
NC		 10576 }
10577 else
fe56b6ce 10578 {
6576bffe
AB		 10579 func (stream, dis_style_text,
10580 ", {%d}", (int) offset);
fe56b6ce
NC		 10581 value_in_comment = offset;
10582 }
05413229
NC		 10583 }
10584 }
252b5132
RH		 10585 break;
10586
077b8428
NC		 10587 case 'B':
10588 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10589 {
10590 bfd_vma address;
10591 bfd_vma offset = 0;
b34976b6 10592
c1e26897 10593 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10594 /* Is signed, hi bits should be ones. */
10595 offset = (-1) ^ 0x00ffffff;
10596
10597 /* Offset is (SignExtend(offset field)<<2). */
10598 offset += given & 0x00ffffff;
10599 offset <<= 2;
10600 address = offset + pc + 8;
b34976b6 10601
8f06b2d8
PB		 10602 if (given & 0x01000000)
10603 /* H bit allows addressing to 2-byte boundaries. */
10604 address += 2;
b1ee46c5 10605
8f06b2d8 10606 info->print_address_func (address, info);
1d67fe3b
TT		 10607
10608 /* Fill in instruction information. */
10609 info->insn_info_valid = 1;
10610 info->insn_type = dis_branch;
10611 info->target = address;
b1ee46c5 10612 }
b1ee46c5
AH		 10613 break;
10614
252b5132 10615 case 'C':
90ec0d68
MGD		 10616 if ((given & 0x02000200) == 0x200)
10617 {
10618 const char * name;
10619 unsigned sysm = (given & 0x004f0000) >> 16;
10620
10621 sysm |= (given & 0x300) >> 4;
10622 name = banked_regname (sysm);
10623
10624 if (name != NULL)
6576bffe 10625 func (stream, dis_style_register, "%s", name);
90ec0d68 10626 else
6576bffe
AB		 10627 func (stream, dis_style_text,
10628 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10629 }
10630 else
10631 {
6576bffe 10632 func (stream, dis_style_register, "%cPSR_",
90ec0d68 10633 (given & 0x00400000) ? 'S' : 'C');
6576bffe 10634
90ec0d68 10635 if (given & 0x80000)
6576bffe 10636 func (stream, dis_style_register, "f");
90ec0d68 10637 if (given & 0x40000)
6576bffe 10638 func (stream, dis_style_register, "s");
90ec0d68 10639 if (given & 0x20000)
6576bffe 10640 func (stream, dis_style_register, "x");
90ec0d68 10641 if (given & 0x10000)
6576bffe 10642 func (stream, dis_style_register, "c");
90ec0d68 10643 }
252b5132
RH		 10644 break;
10645
62b3e311 10646 case 'U':
43e65147 10647 if ((given & 0xf0) == 0x60)
62b3e311 10648 {
52e7f43d
RE		 10649 switch (given & 0xf)
10650 {
6576bffe
AB		 10651 case 0xf:
10652 func (stream, dis_style_sub_mnemonic, "sy");
10653 break;
52e7f43d 10654 default:
6576bffe
AB		 10655 func (stream, dis_style_immediate, "#%d",
10656 (int) given & 0xf);
52e7f43d
RE		 10657 break;
10658 }
43e65147
L		 10659 }
10660 else
52e7f43d 10661 {
e797f7e0
MGD		 10662 const char * opt = data_barrier_option (given & 0xf);
10663 if (opt != NULL)
6576bffe 10664 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 10665 else
6576bffe
AB		 10666 func (stream, dis_style_immediate,
10667 "#%d", (int) given & 0xf);
62b3e311
PB		 10668 }
10669 break;
10670
b34976b6 10671 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10672 case '5': case '6': case '7': case '8': case '9':
10673 {
16980d0b
JB		 10674 int width;
10675 unsigned long value;
252b5132 10676
16980d0b 10677 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10678
252b5132
RH		 10679 switch (*c)
10680 {
ab8e2090
NC		 10681 case 'R':
10682 if (value == 15)
78933a4a 10683 is_unpredictable = true;
ab8e2090 10684 /* Fall through. */
16980d0b 10685 case 'r':
9eb6c0f1
MGD		 10686 case 'T':
10687 /* We want register + 1 when decoding T. */
10688 if (*c == 'T')
2bddb71a 10689 value = (value + 1) & 0xf;
9eb6c0f1 10690
ff4a8d2b
NC		 10691 if (c[1] == 'u')
10692 {
10693 /* Eat the 'u' character. */
10694 ++ c;
10695
10696 if (u_reg == value)
78933a4a 10697 is_unpredictable = true;
ff4a8d2b
NC		 10698 u_reg = value;
10699 }
10700 if (c[1] == 'U')
10701 {
10702 /* Eat the 'U' character. */
10703 ++ c;
10704
10705 if (U_reg == value)
78933a4a 10706 is_unpredictable = true;
ff4a8d2b
NC		 10707 U_reg = value;
10708 }
6576bffe
AB		 10709 func (stream, dis_style_register, "%s",
10710 arm_regnames[value]);
16980d0b
JB		 10711 break;
10712 case 'd':
6576bffe 10713 func (stream, base_style, "%ld", value);
05413229 10714 value_in_comment = value;
16980d0b
JB		 10715 break;
10716 case 'b':
6576bffe
AB		 10717 func (stream, dis_style_immediate,
10718 "%ld", value * 8);
05413229 10719 value_in_comment = value * 8;
16980d0b
JB		 10720 break;
10721 case 'W':
6576bffe
AB		 10722 func (stream, dis_style_immediate,
10723 "%ld", value + 1);
05413229 10724 value_in_comment = value + 1;
16980d0b
JB		 10725 break;
10726 case 'x':
6576bffe
AB		 10727 func (stream, dis_style_immediate,
10728 "0x%08lx", value);
16980d0b
JB		 10729
10730 /* Some SWI instructions have special
10731 meanings. */
10732 if ((given & 0x0fffffff) == 0x0FF00000)
6576bffe
AB		 10733 func (stream, dis_style_comment_start,
10734 "\t@ IMB");
16980d0b 10735 else if ((given & 0x0fffffff) == 0x0FF00001)
6576bffe
AB		 10736 func (stream, dis_style_comment_start,
10737 "\t@ IMBRange");
16980d0b
JB		 10738 break;
10739 case 'X':
6576bffe
AB		 10740 func (stream, dis_style_immediate,
10741 "%01lx", value & 0xf);
05413229 10742 value_in_comment = value;
252b5132
RH		 10743 break;
10744 case '`':
10745 c++;
16980d0b 10746 if (value == 0)
6576bffe 10747 func (stream, dis_style_text, "%c", *c);
252b5132
RH		 10748 break;
10749 case '\'':
10750 c++;
16980d0b 10751 if (value == ((1ul << width) - 1))
6576bffe 10752 func (stream, base_style, "%c", *c);
252b5132
RH		 10753 break;
10754 case '?':
6576bffe
AB		 10755 func (stream, base_style, "%c",
10756 c[(1 << width) - (int) value]);
16980d0b 10757 c += 1 << width;
252b5132
RH		 10758 break;
10759 default:
10760 abort ();
10761 }
dffaa15c
AM		 10762 }
10763 break;
0dd132b6 10764
dffaa15c
AM		 10765 case 'e':
10766 {
10767 int imm;
0dd132b6 10768
dffaa15c 10769 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6576bffe 10770 func (stream, dis_style_immediate, "%d", imm);
dffaa15c
AM		 10771 value_in_comment = imm;
10772 }
10773 break;
fe56b6ce 10774
dffaa15c
AM		 10775 case 'E':
10776 /* LSB and WIDTH fields of BFI or BFC. The machine-
10777 language instruction encodes LSB and MSB. */
10778 {
10779 long msb = (given & 0x001f0000) >> 16;
10780 long lsb = (given & 0x00000f80) >> 7;
10781 long w = msb - lsb + 1;
0a003adc 10782
dffaa15c 10783 if (w > 0)
6576bffe
AB		 10784 {
10785 func (stream, dis_style_immediate, "#%lu", lsb);
10786 func (stream, dis_style_text, ", ");
10787 func (stream, dis_style_immediate, "#%lu", w);
10788 }
dffaa15c 10789 else
6576bffe
AB		 10790 func (stream, dis_style_text,
10791 "(invalid: %lu:%lu)", lsb, msb);
dffaa15c
AM		 10792 }
10793 break;
90ec0d68 10794
dffaa15c
AM		 10795 case 'R':
10796 /* Get the PSR/banked register name. */
10797 {
10798 const char * name;
10799 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10800
dffaa15c
AM		 10801 sysm |= (given & 0x300) >> 4;
10802 name = banked_regname (sysm);
90ec0d68 10803
dffaa15c 10804 if (name != NULL)
6576bffe 10805 func (stream, dis_style_register, "%s", name);
dffaa15c 10806 else
6576bffe
AB		 10807 func (stream, dis_style_text,
10808 "(UNDEF: %lu)", (unsigned long) sysm);
dffaa15c
AM		 10809 }
10810 break;
fe56b6ce 10811
dffaa15c
AM		 10812 case 'V':
10813 /* 16-bit unsigned immediate from a MOVT or MOVW
10814 instruction, encoded in bits 0:11 and 15:19. */
10815 {
10816 long hi = (given & 0x000f0000) >> 4;
10817 long lo = (given & 0x00000fff);
10818 long imm16 = hi | lo;
0a003adc 10819
6576bffe 10820 func (stream, dis_style_immediate, "#%lu", imm16);
dffaa15c 10821 value_in_comment = imm16;
252b5132 10822 }
dffaa15c
AM		 10823 break;
10824
10825 default:
10826 abort ();
252b5132
RH		 10827 }
10828 }
10829 else
6576bffe
AB		 10830 {
10831
10832 if (*c == '@')
10833 base_style = dis_style_comment_start;
10834
10835 if (*c == '\t')
10836 base_style = dis_style_text;
10837
10838 func (stream, base_style, "%c", *c);
10839 }
252b5132 10840 }
05413229
NC		 10841
10842 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10843 func (stream, dis_style_comment_start, "\t@ 0x%lx",
10844 (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10845
10846 if (is_unpredictable)
6576bffe 10847 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10848
4a5329c6 10849 return;
252b5132
RH		 10850 }
10851 }
6576bffe
AB		 10852 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
10853 (unsigned) given);
0b347048 10854 return;
252b5132
RH		 10855}
10856
4a5329c6 10857/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10858
4a5329c6
ZW		 10859static void
10860print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10861{
6b5d3a4d 10862 const struct opcode16 *insn;
6a51a8a8 10863 void *stream = info->stream;
6576bffe
AB		 10864 fprintf_styled_ftype func = info->fprintf_styled_func;
10865 enum disassembler_style base_style = dis_style_mnemonic;
10866 enum disassembler_style old_base_style = base_style;
252b5132
RH		 10867
10868 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10869 if ((given & insn->mask) == insn->value)
10870 {
05413229 10871 signed long value_in_comment = 0;
6b5d3a4d 10872 const char *c = insn->assembler;
05413229 10873
c19d1205
ZW		 10874 for (; *c; c++)
10875 {
10876 int domaskpc = 0;
10877 int domasklr = 0;
10878
10879 if (*c != '%')
10880 {
6576bffe
AB		 10881 if (*c == '@')
10882 base_style = dis_style_comment_start;
10883
10884 if (*c == '\t')
10885 base_style = dis_style_text;
10886
10887 func (stream, base_style, "%c", *c);
10888
c19d1205
ZW		 10889 continue;
10890 }
252b5132 10891
c19d1205
ZW		 10892 switch (*++c)
10893 {
6576bffe
AB		 10894 case '{':
10895 ++c;
10896 if (*c == '\0')
10897 abort ();
10898 old_base_style = base_style;
10899 base_style = decode_base_style (*c);
10900 ++c;
10901 if (*c != ':')
10902 abort ();
10903 break;
10904
10905 case '}':
10906 base_style = old_base_style;
10907 break;
10908
c19d1205 10909 case '%':
6576bffe 10910 func (stream, base_style, "%%");
c19d1205 10911 break;
b34976b6 10912
c22aaad1
PB		 10913 case 'c':
10914 if (ifthen_state)
6576bffe
AB		 10915 func (stream, dis_style_mnemonic, "%s",
10916 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 10917 break;
10918
10919 case 'C':
10920 if (ifthen_state)
6576bffe
AB		 10921 func (stream, dis_style_mnemonic, "%s",
10922 arm_conditional[IFTHEN_COND]);
c22aaad1 10923 else
6576bffe 10924 func (stream, dis_style_mnemonic, "s");
c22aaad1
PB		 10925 break;
10926
10927 case 'I':
10928 {
10929 unsigned int tmp;
10930
10931 ifthen_next_state = given & 0xff;
10932 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6576bffe
AB		 10933 func (stream, dis_style_mnemonic,
10934 ((given ^ tmp) & 0x10) ? "e" : "t");
10935 func (stream, dis_style_text, "\t");
10936 func (stream, dis_style_sub_mnemonic, "%s",
10937 arm_conditional[(given >> 4) & 0xf]);
c22aaad1
PB		 10938 }
10939 break;
10940
10941 case 'x':
10942 if (ifthen_next_state)
6576bffe
AB		 10943 func (stream, dis_style_comment_start,
10944 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 10945 break;
10946
10947 case 'X':
10948 if (ifthen_state)
6576bffe
AB		 10949 func (stream, dis_style_comment_start,
10950 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 10951 arm_conditional[IFTHEN_COND]);
10952 break;
10953
c19d1205
ZW		 10954 case 'S':
10955 {
10956 long reg;
10957
10958 reg = (given >> 3) & 0x7;
10959 if (given & (1 << 6))
10960 reg += 8;
4f3c3dbb 10961
6576bffe 10962 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 10963 }
10964 break;
baf0cc5e 10965
c19d1205 10966 case 'D':
4f3c3dbb 10967 {
c19d1205
ZW		 10968 long reg;
10969
10970 reg = given & 0x7;
10971 if (given & (1 << 7))
10972 reg += 8;
10973
6576bffe 10974 func (stream, dis_style_register, "%s", arm_regnames[reg]);
4f3c3dbb 10975 }
c19d1205
ZW		 10976 break;
10977
10978 case 'N':
10979 if (given & (1 << 8))
10980 domasklr = 1;
10981 /* Fall through. */
10982 case 'O':
10983 if (*c == 'O' && (given & (1 << 8)))
10984 domaskpc = 1;
10985 /* Fall through. */
10986 case 'M':
10987 {
10988 int started = 0;
10989 int reg;
10990
6576bffe 10991 func (stream, dis_style_text, "{");
c19d1205
ZW		 10992
10993 /* It would be nice if we could spot
10994 ranges, and generate the rS-rE format: */
10995 for (reg = 0; (reg < 8); reg++)
10996 if ((given & (1 << reg)) != 0)
10997 {
10998 if (started)
6576bffe 10999 func (stream, dis_style_text, ", ");
c19d1205 11000 started = 1;
6576bffe
AB		 11001 func (stream, dis_style_register, "%s",
11002 arm_regnames[reg]);
c19d1205
ZW		 11003 }
11004
11005 if (domasklr)
11006 {
11007 if (started)
6576bffe 11008 func (stream, dis_style_text, ", ");
c19d1205 11009 started = 1;
6576bffe
AB		 11010 func (stream, dis_style_register, "%s",
11011 arm_regnames[14] /* "lr" */);
c19d1205
ZW		 11012 }
11013
11014 if (domaskpc)
11015 {
11016 if (started)
6576bffe
AB		 11017 func (stream, dis_style_text, ", ");
11018 func (stream, dis_style_register, "%s",
11019 arm_regnames[15] /* "pc" */);
c19d1205
ZW		 11020 }
11021
6576bffe 11022 func (stream, dis_style_text, "}");
c19d1205
ZW		 11023 }
11024 break;
11025
4547cb56
NC		 11026 case 'W':
11027 /* Print writeback indicator for a LDMIA. We are doing a
11028 writeback if the base register is not in the register
11029 mask. */
11030 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6576bffe 11031 func (stream, dis_style_text, "!");
dffaa15c 11032 break;
4547cb56 11033
c19d1205
ZW		 11034 case 'b':
11035 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
11036 {
11037 bfd_vma address = (pc + 4
11038 + ((given & 0x00f8) >> 2)
11039 + ((given & 0x0200) >> 3));
11040 info->print_address_func (address, info);
1d67fe3b
TT		 11041
11042 /* Fill in instruction information. */
11043 info->insn_info_valid = 1;
11044 info->insn_type = dis_branch;
11045 info->target = address;
c19d1205
ZW		 11046 }
11047 break;
11048
11049 case 's':
11050 /* Right shift immediate -- bits 6..10; 1-31 print
11051 as themselves, 0 prints as 32. */
11052 {
11053 long imm = (given & 0x07c0) >> 6;
11054 if (imm == 0)
11055 imm = 32;
6576bffe 11056 func (stream, dis_style_immediate, "#%ld", imm);
c19d1205
ZW		 11057 }
11058 break;
11059
11060 case '0': case '1': case '2': case '3': case '4':
11061 case '5': case '6': case '7': case '8': case '9':
11062 {
11063 int bitstart = *c++ - '0';
11064 int bitend = 0;
11065
11066 while (*c >= '0' && *c <= '9')
11067 bitstart = (bitstart * 10) + *c++ - '0';
11068
11069 switch (*c)
11070 {
11071 case '-':
11072 {
f8b960bc 11073 bfd_vma reg;
c19d1205
ZW		 11074
11075 c++;
11076 while (*c >= '0' && *c <= '9')
11077 bitend = (bitend * 10) + *c++ - '0';
11078 if (!bitend)
11079 abort ();
11080 reg = given >> bitstart;
459cde81 11081 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
ff4a8d2b 11082
c19d1205
ZW		 11083 switch (*c)
11084 {
11085 case 'r':
6576bffe
AB		 11086 func (stream, dis_style_register, "%s",
11087 arm_regnames[reg]);
c19d1205
ZW		 11088 break;
11089
11090 case 'd':
6576bffe
AB		 11091 func (stream, dis_style_immediate, "%ld",
11092 (long) reg);
05413229 11093 value_in_comment = reg;
c19d1205
ZW		 11094 break;
11095
11096 case 'H':
6576bffe
AB		 11097 func (stream, dis_style_immediate, "%ld",
11098 (long) (reg << 1));
05413229 11099 value_in_comment = reg << 1;
c19d1205
ZW		 11100 break;
11101
11102 case 'W':
6576bffe
AB		 11103 func (stream, dis_style_immediate, "%ld",
11104 (long) (reg << 2));
05413229 11105 value_in_comment = reg << 2;
c19d1205
ZW		 11106 break;
11107
11108 case 'a':
11109 /* PC-relative address -- the bottom two
11110 bits of the address are dropped
11111 before the calculation. */
11112 info->print_address_func
11113 (((pc + 4) & ~3) + (reg << 2), info);
05413229 11114 value_in_comment = 0;
c19d1205
ZW		 11115 break;
11116
11117 case 'x':
6576bffe
AB		 11118 func (stream, dis_style_immediate, "0x%04lx",
11119 (long) reg);
c19d1205
ZW		 11120 break;
11121
c19d1205
ZW		 11122 case 'B':
11123 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 11124 bfd_vma target = reg * 2 + pc + 4;
11125 info->print_address_func (target, info);
05413229 11126 value_in_comment = 0;
1d67fe3b
TT		 11127
11128 /* Fill in instruction information. */
11129 info->insn_info_valid = 1;
11130 info->insn_type = dis_branch;
11131 info->target = target;
c19d1205
ZW		 11132 break;
11133
11134 case 'c':
6576bffe
AB		 11135 func (stream, dis_style_mnemonic, "%s",
11136 arm_conditional [reg]);
c19d1205
ZW		 11137 break;
11138
11139 default:
11140 abort ();
11141 }
11142 }
11143 break;
11144
11145 case '\'':
11146 c++;
11147 if ((given & (1 << bitstart)) != 0)
6576bffe 11148 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11149 break;
11150
11151 case '?':
11152 ++c;
11153 if ((given & (1 << bitstart)) != 0)
6576bffe 11154 func (stream, base_style, "%c", *c++);
c19d1205 11155 else
6576bffe 11156 func (stream, base_style, "%c", *++c);
c19d1205
ZW		 11157 break;
11158
11159 default:
11160 abort ();
11161 }
11162 }
11163 break;
11164
11165 default:
11166 abort ();
11167 }
11168 }
05413229
NC		 11169
11170 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 11171 func (stream, dis_style_comment_start,
11172 "\t@ 0x%lx", value_in_comment);
4a5329c6 11173 return;
c19d1205
ZW		 11174 }
11175
11176 /* No match. */
6576bffe
AB		 11177 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
11178 (unsigned) given);
0b347048 11179 return;
c19d1205
ZW		 11180}
11181
62b3e311 11182/* Return the name of an V7M special register. */
fe56b6ce 11183
62b3e311
PB		 11184static const char *
11185psr_name (int regno)
11186{
11187 switch (regno)
11188 {
1a336194
TP		 11189 case 0x0: return "APSR";
11190 case 0x1: return "IAPSR";
11191 case 0x2: return "EAPSR";
11192 case 0x3: return "PSR";
11193 case 0x5: return "IPSR";
11194 case 0x6: return "EPSR";
11195 case 0x7: return "IEPSR";
11196 case 0x8: return "MSP";
11197 case 0x9: return "PSP";
11198 case 0xa: return "MSPLIM";
11199 case 0xb: return "PSPLIM";
11200 case 0x10: return "PRIMASK";
11201 case 0x11: return "BASEPRI";
11202 case 0x12: return "BASEPRI_MAX";
11203 case 0x13: return "FAULTMASK";
11204 case 0x14: return "CONTROL";
16a1fa25
TP		 11205 case 0x88: return "MSP_NS";
11206 case 0x89: return "PSP_NS";
1a336194
TP		 11207 case 0x8a: return "MSPLIM_NS";
11208 case 0x8b: return "PSPLIM_NS";
11209 case 0x90: return "PRIMASK_NS";
11210 case 0x91: return "BASEPRI_NS";
11211 case 0x93: return "FAULTMASK_NS";
11212 case 0x94: return "CONTROL_NS";
11213 case 0x98: return "SP_NS";
62b3e311
PB		 11214 default: return "<unknown>";
11215 }
11216}
11217
4a5329c6
ZW		 11218/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
11219
11220static void
11221print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 11222{
6b5d3a4d 11223 const struct opcode32 *insn;
c19d1205 11224 void *stream = info->stream;
6576bffe 11225 fprintf_styled_ftype func = info->fprintf_styled_func;
78933a4a 11226 bool is_mve = is_mve_architecture (info);
6576bffe
AB		 11227 enum disassembler_style base_style = dis_style_mnemonic;
11228 enum disassembler_style old_base_style = base_style;
c19d1205 11229
78933a4a 11230 if (print_insn_coprocessor (pc, info, given, true))
16980d0b
JB		 11231 return;
11232
78933a4a 11233 if (!is_mve && print_insn_neon (info, given, true))
73cd51e5
AV		 11234 return;
11235
11236 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 11237 return;
11238
78933a4a 11239 if (print_insn_cde (info, given, true))
4934a27c
MM		 11240 return;
11241
78933a4a 11242 if (print_insn_generic_coprocessor (pc, info, given, true))
33593eaf
MM		 11243 return;
11244
c19d1205
ZW		 11245 for (insn = thumb32_opcodes; insn->assembler; insn++)
11246 if ((given & insn->mask) == insn->value)
11247 {
78933a4a
AM		 11248 bool is_clrm = false;
11249 bool is_unpredictable = false;
05413229 11250 signed long value_in_comment = 0;
6b5d3a4d 11251 const char *c = insn->assembler;
05413229 11252
c19d1205
ZW		 11253 for (; *c; c++)
11254 {
11255 if (*c != '%')
11256 {
6576bffe
AB		 11257 if (*c == '@')
11258 base_style = dis_style_comment_start;
11259 if (*c == '\t')
11260 base_style = dis_style_text;
11261 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11262 continue;
11263 }
11264
11265 switch (*++c)
11266 {
6576bffe
AB		 11267 case '{':
11268 ++c;
11269 if (*c == '\0')
11270 abort ();
11271 old_base_style = base_style;
11272 base_style = decode_base_style (*c);
11273 ++c;
11274 if (*c != ':')
11275 abort ();
11276 break;
11277
11278 case '}':
11279 base_style = old_base_style;
11280 break;
11281
c19d1205 11282 case '%':
6576bffe 11283 func (stream, base_style, "%%");
c19d1205
ZW		 11284 break;
11285
c22aaad1
PB		 11286 case 'c':
11287 if (ifthen_state)
6576bffe
AB		 11288 func (stream, dis_style_mnemonic, "%s",
11289 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 11290 break;
11291
11292 case 'x':
11293 if (ifthen_next_state)
6576bffe
AB		 11294 func (stream, dis_style_comment_start,
11295 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 11296 break;
11297
11298 case 'X':
11299 if (ifthen_state)
6576bffe
AB		 11300 func (stream, dis_style_comment_start,
11301 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 11302 arm_conditional[IFTHEN_COND]);
11303 break;
11304
c19d1205
ZW		 11305 case 'I':
11306 {
11307 unsigned int imm12 = 0;
fe56b6ce 11308
c19d1205
ZW		 11309 imm12 |= (given & 0x000000ffu);
11310 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 11311 imm12 |= (given & 0x04000000u) >> 15;
6576bffe 11312 func (stream, dis_style_immediate, "#%u", imm12);
fe56b6ce 11313 value_in_comment = imm12;
c19d1205
ZW		 11314 }
11315 break;
11316
11317 case 'M':
11318 {
11319 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 11320
c19d1205
ZW		 11321 bits |= (given & 0x000000ffu);
11322 bits |= (given & 0x00007000u) >> 4;
11323 bits |= (given & 0x04000000u) >> 15;
11324 imm8 = (bits & 0x0ff);
11325 mod = (bits & 0xf00) >> 8;
11326 switch (mod)
11327 {
11328 case 0: imm = imm8; break;
c1e26897
NC		 11329 case 1: imm = ((imm8 << 16) | imm8); break;
11330 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11331 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 11332 default:
11333 mod = (bits & 0xf80) >> 7;
11334 imm8 = (bits & 0x07f) | 0x80;
11335 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11336 }
6576bffe 11337 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11338 value_in_comment = imm;
c19d1205
ZW		 11339 }
11340 break;
43e65147 11341
c19d1205
ZW		 11342 case 'J':
11343 {
11344 unsigned int imm = 0;
fe56b6ce 11345
c19d1205
ZW		 11346 imm |= (given & 0x000000ffu);
11347 imm |= (given & 0x00007000u) >> 4;
11348 imm |= (given & 0x04000000u) >> 15;
11349 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11350 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11351 value_in_comment = imm;
c19d1205
ZW		 11352 }
11353 break;
11354
11355 case 'K':
11356 {
11357 unsigned int imm = 0;
fe56b6ce 11358
c19d1205
ZW		 11359 imm |= (given & 0x000f0000u) >> 16;
11360 imm |= (given & 0x00000ff0u) >> 0;
11361 imm |= (given & 0x0000000fu) << 12;
6576bffe 11362 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11363 value_in_comment = imm;
c19d1205
ZW		 11364 }
11365 break;
11366
74db7efb
NC		 11367 case 'H':
11368 {
11369 unsigned int imm = 0;
11370
11371 imm |= (given & 0x000f0000u) >> 4;
11372 imm |= (given & 0x00000fffu) >> 0;
6576bffe 11373 func (stream, dis_style_immediate, "#%u", imm);
74db7efb
NC		 11374 value_in_comment = imm;
11375 }
11376 break;
11377
90ec0d68
MGD		 11378 case 'V':
11379 {
11380 unsigned int imm = 0;
11381
11382 imm |= (given & 0x00000fffu);
11383 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11384 func (stream, dis_style_immediate, "#%u", imm);
90ec0d68
MGD		 11385 value_in_comment = imm;
11386 }
11387 break;
11388
c19d1205
ZW		 11389 case 'S':
11390 {
11391 unsigned int reg = (given & 0x0000000fu);
11392 unsigned int stp = (given & 0x00000030u) >> 4;
11393 unsigned int imm = 0;
11394 imm |= (given & 0x000000c0u) >> 6;
11395 imm |= (given & 0x00007000u) >> 10;
11396
6576bffe 11397 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 11398 switch (stp)
11399 {
11400 case 0:
11401 if (imm > 0)
6576bffe
AB		 11402 {
11403 func (stream, dis_style_text, ", ");
11404 func (stream, dis_style_sub_mnemonic, "lsl ");
11405 func (stream, dis_style_immediate, "#%u", imm);
11406 }
c19d1205
ZW		 11407 break;
11408
11409 case 1:
11410 if (imm == 0)
11411 imm = 32;
6576bffe
AB		 11412 func (stream, dis_style_text, ", ");
11413 func (stream, dis_style_sub_mnemonic, "lsr ");
11414 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11415 break;
11416
11417 case 2:
11418 if (imm == 0)
11419 imm = 32;
6576bffe
AB		 11420 func (stream, dis_style_text, ", ");
11421 func (stream, dis_style_sub_mnemonic, "asr ");
11422 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11423 break;
11424
11425 case 3:
11426 if (imm == 0)
6576bffe
AB		 11427 {
11428 func (stream, dis_style_text, ", ");
11429 func (stream, dis_style_sub_mnemonic, "rrx");
11430 }
c19d1205 11431 else
6576bffe
AB		 11432 {
11433 func (stream, dis_style_text, ", ");
11434 func (stream, dis_style_sub_mnemonic, "ror ");
11435 func (stream, dis_style_immediate, "#%u", imm);
11436 }
c19d1205
ZW		 11437 }
11438 }
11439 break;
11440
11441 case 'a':
11442 {
11443 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11444 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11445 unsigned int op = (given & 0x00000f00) >> 8;
11446 unsigned int i12 = (given & 0x00000fff);
11447 unsigned int i8 = (given & 0x000000ff);
78933a4a 11448 bool writeback = false, postind = false;
f8b960bc 11449 bfd_vma offset = 0;
c19d1205 11450
6576bffe
AB		 11451 func (stream, dis_style_text, "[");
11452 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
05413229
NC		 11453 if (U) /* 12-bit positive immediate offset. */
11454 {
11455 offset = i12;
11456 if (Rn != 15)
11457 value_in_comment = offset;
11458 }
11459 else if (Rn == 15) /* 12-bit negative immediate offset. */
11460 offset = - (int) i12;
11461 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11462 {
11463 unsigned int Rm = (i8 & 0x0f);
11464 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11465
6576bffe
AB		 11466 func (stream, dis_style_text, ", ");
11467 func (stream, dis_style_register, "%s",
11468 arm_regnames[Rm]);
c19d1205 11469 if (sh)
6576bffe
AB		 11470 {
11471 func (stream, dis_style_text, ", ");
11472 func (stream, dis_style_sub_mnemonic, "lsl ");
11473 func (stream, dis_style_immediate, "#%u", sh);
11474 }
11475 func (stream, dis_style_text, "]");
c19d1205
ZW		 11476 break;
11477 }
11478 else switch (op)
11479 {
05413229 11480 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11481 offset = i8;
11482 break;
11483
05413229 11484 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11485 offset = -i8;
11486 break;
11487
05413229 11488 case 0xF: /* 8-bit + preindex with wb. */
c19d1205 11489 offset = i8;
78933a4a 11490 writeback = true;
c19d1205
ZW		 11491 break;
11492
05413229 11493 case 0xD: /* 8-bit - preindex with wb. */
c19d1205 11494 offset = -i8;
78933a4a 11495 writeback = true;
c19d1205
ZW		 11496 break;
11497
05413229 11498 case 0xB: /* 8-bit + postindex. */
c19d1205 11499 offset = i8;
78933a4a 11500 postind = true;
c19d1205
ZW		 11501 break;
11502
05413229 11503 case 0x9: /* 8-bit - postindex. */
c19d1205 11504 offset = -i8;
78933a4a 11505 postind = true;
c19d1205
ZW		 11506 break;
11507
11508 default:
6576bffe 11509 func (stream, dis_style_text, ", <undefined>]");
c19d1205
ZW		 11510 goto skip;
11511 }
11512
11513 if (postind)
6576bffe
AB		 11514 {
11515 func (stream, dis_style_text, "], ");
11516 func (stream, dis_style_immediate, "#%d", (int) offset);
11517 }
c19d1205
ZW		 11518 else
11519 {
11520 if (offset)
6576bffe
AB		 11521 {
11522 func (stream, dis_style_text, ", ");
11523 func (stream, dis_style_immediate, "#%d",
11524 (int) offset);
11525 }
11526 func (stream, dis_style_text, writeback ? "]!" : "]");
c19d1205
ZW		 11527 }
11528
11529 if (Rn == 15)
11530 {
6576bffe 11531 func (stream, dis_style_comment_start, "\t@ ");
c19d1205
ZW		 11532 info->print_address_func (((pc + 4) & ~3) + offset, info);
11533 }
11534 }
11535 skip:
11536 break;
11537
11538 case 'A':
11539 {
c1e26897
NC		 11540 unsigned int U = ! NEGATIVE_BIT_SET;
11541 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11542 unsigned int Rn = (given & 0x000f0000) >> 16;
11543 unsigned int off = (given & 0x000000ff);
11544
6576bffe
AB		 11545 func (stream, dis_style_text, "[");
11546 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
c1e26897
NC		 11547
11548 if (PRE_BIT_SET)
c19d1205
ZW		 11549 {
11550 if (off || !U)
05413229 11551 {
6576bffe
AB		 11552 func (stream, dis_style_text, ", ");
11553 func (stream, dis_style_immediate, "#%c%u",
11554 U ? '+' : '-', off * 4);
fe50e98c 11555 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11556 }
6576bffe 11557 func (stream, dis_style_text, "]");
c19d1205 11558 if (W)
6576bffe 11559 func (stream, dis_style_text, "!");
c19d1205
ZW		 11560 }
11561 else
11562 {
6576bffe 11563 func (stream, dis_style_text, "], ");
c19d1205 11564 if (W)
05413229 11565 {
6576bffe
AB		 11566 func (stream, dis_style_immediate, "#%c%u",
11567 U ? '+' : '-', off * 4);
fe50e98c 11568 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11569 }
c19d1205 11570 else
fe56b6ce 11571 {
6576bffe
AB		 11572 func (stream, dis_style_text, "{");
11573 func (stream, dis_style_immediate, "%u", off);
11574 func (stream, dis_style_text, "}");
fe56b6ce
NC		 11575 value_in_comment = off;
11576 }
c19d1205
ZW		 11577 }
11578 }
11579 break;
11580
11581 case 'w':
11582 {
11583 unsigned int Sbit = (given & 0x01000000) >> 24;
11584 unsigned int type = (given & 0x00600000) >> 21;
05413229 11585
c19d1205
ZW		 11586 switch (type)
11587 {
6576bffe
AB		 11588 case 0:
11589 func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11590 break;
11591 case 1:
11592 func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11593 break;
c19d1205
ZW		 11594 case 2:
11595 if (Sbit)
6576bffe 11596 func (stream, dis_style_text, "??");
c19d1205
ZW		 11597 break;
11598 case 3:
6576bffe 11599 func (stream, dis_style_text, "??");
c19d1205
ZW		 11600 break;
11601 }
11602 }
11603 break;
11604
4b5a202f 11605 case 'n':
78933a4a 11606 is_clrm = true;
4b5a202f 11607 /* Fall through. */
c19d1205
ZW		 11608 case 'm':
11609 {
11610 int started = 0;
11611 int reg;
11612
6576bffe 11613 func (stream, dis_style_text, "{");
c19d1205
ZW		 11614 for (reg = 0; reg < 16; reg++)
11615 if ((given & (1 << reg)) != 0)
11616 {
11617 if (started)
6576bffe 11618 func (stream, dis_style_text, ", ");
c19d1205 11619 started = 1;
4b5a202f 11620 if (is_clrm && reg == 13)
6576bffe
AB		 11621 func (stream, dis_style_text, "(invalid: %s)",
11622 arm_regnames[reg]);
4b5a202f 11623 else if (is_clrm && reg == 15)
6576bffe 11624 func (stream, dis_style_register, "%s", "APSR");
4b5a202f 11625 else
6576bffe
AB		 11626 func (stream, dis_style_register, "%s",
11627 arm_regnames[reg]);
c19d1205 11628 }
6576bffe 11629 func (stream, dis_style_text, "}");
c19d1205
ZW		 11630 }
11631 break;
11632
11633 case 'E':
11634 {
11635 unsigned int msb = (given & 0x0000001f);
11636 unsigned int lsb = 0;
fe56b6ce 11637
c19d1205
ZW		 11638 lsb |= (given & 0x000000c0u) >> 6;
11639 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11640 func (stream, dis_style_immediate, "#%u", lsb);
11641 func (stream, dis_style_text, ", ");
11642 func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
c19d1205
ZW		 11643 }
11644 break;
11645
11646 case 'F':
11647 {
11648 unsigned int width = (given & 0x0000001f) + 1;
11649 unsigned int lsb = 0;
fe56b6ce 11650
c19d1205
ZW		 11651 lsb |= (given & 0x000000c0u) >> 6;
11652 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11653 func (stream, dis_style_immediate, "#%u", lsb);
11654 func (stream, dis_style_text, ", ");
11655 func (stream, dis_style_immediate, "#%u", width);
c19d1205
ZW		 11656 }
11657 break;
11658
e12437dc
AV		 11659 case 'G':
11660 {
11661 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
6576bffe 11662 func (stream, dis_style_immediate, "%x", boff);
e12437dc
AV		 11663 }
11664 break;
11665
e5d6e09e
AV		 11666 case 'W':
11667 {
11668 unsigned int immA = (given & 0x001f0000u) >> 16;
11669 unsigned int immB = (given & 0x000007feu) >> 1;
11670 unsigned int immC = (given & 0x00000800u) >> 11;
11671 bfd_vma offset = 0;
11672
11673 offset |= immA << 12;
11674 offset |= immB << 2;
11675 offset |= immC << 1;
11676 /* Sign extend. */
11677 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11678
11679 info->print_address_func (pc + 4 + offset, info);
11680 }
11681 break;
11682
1caf72a5
AV		 11683 case 'Y':
11684 {
11685 unsigned int immA = (given & 0x007f0000u) >> 16;
11686 unsigned int immB = (given & 0x000007feu) >> 1;
11687 unsigned int immC = (given & 0x00000800u) >> 11;
11688 bfd_vma offset = 0;
11689
11690 offset |= immA << 12;
11691 offset |= immB << 2;
11692 offset |= immC << 1;
11693 /* Sign extend. */
11694 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11695
11696 info->print_address_func (pc + 4 + offset, info);
11697 }
11698 break;
11699
1889da70
AV		 11700 case 'Z':
11701 {
11702 unsigned int immA = (given & 0x00010000u) >> 16;
11703 unsigned int immB = (given & 0x000007feu) >> 1;
11704 unsigned int immC = (given & 0x00000800u) >> 11;
11705 bfd_vma offset = 0;
11706
11707 offset |= immA << 12;
11708 offset |= immB << 2;
11709 offset |= immC << 1;
11710 /* Sign extend. */
11711 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11712
11713 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11714
11715 unsigned int T = (given & 0x00020000u) >> 17;
11716 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11717 unsigned int boffset = (T == 1) ? 4 : 2;
6576bffe
AB		 11718 func (stream, dis_style_text, ", ");
11719 func (stream, dis_style_immediate, "%x",
11720 endoffset + boffset);
1889da70
AV		 11721 }
11722 break;
11723
60f993ce
AV		 11724 case 'Q':
11725 {
11726 unsigned int immh = (given & 0x000007feu) >> 1;
11727 unsigned int imml = (given & 0x00000800u) >> 11;
11728 bfd_vma imm32 = 0;
11729
11730 imm32 |= immh << 2;
11731 imm32 |= imml << 1;
11732
11733 info->print_address_func (pc + 4 + imm32, info);
11734 }
11735 break;
11736
11737 case 'P':
11738 {
11739 unsigned int immh = (given & 0x000007feu) >> 1;
11740 unsigned int imml = (given & 0x00000800u) >> 11;
11741 bfd_vma imm32 = 0;
11742
11743 imm32 |= immh << 2;
11744 imm32 |= imml << 1;
11745
11746 info->print_address_func (pc + 4 - imm32, info);
11747 }
11748 break;
11749
c19d1205
ZW		 11750 case 'b':
11751 {
11752 unsigned int S = (given & 0x04000000u) >> 26;
11753 unsigned int J1 = (given & 0x00002000u) >> 13;
11754 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11755 bfd_vma offset = 0;
c19d1205
ZW		 11756
11757 offset |= !S << 20;
11758 offset |= J2 << 19;
11759 offset |= J1 << 18;
11760 offset |= (given & 0x003f0000) >> 4;
11761 offset |= (given & 0x000007ff) << 1;
11762 offset -= (1 << 20);
11763
1d67fe3b
TT		 11764 bfd_vma target = pc + 4 + offset;
11765 info->print_address_func (target, info);
11766
11767 /* Fill in instruction information. */
11768 info->insn_info_valid = 1;
11769 info->insn_type = dis_branch;
11770 info->target = target;
c19d1205
ZW		 11771 }
11772 break;
11773
11774 case 'B':
11775 {
11776 unsigned int S = (given & 0x04000000u) >> 26;
11777 unsigned int I1 = (given & 0x00002000u) >> 13;
11778 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11779 bfd_vma offset = 0;
c19d1205
ZW		 11780
11781 offset |= !S << 24;
11782 offset |= !(I1 ^ S) << 23;
11783 offset |= !(I2 ^ S) << 22;
11784 offset |= (given & 0x03ff0000u) >> 4;
11785 offset |= (given & 0x000007ffu) << 1;
11786 offset -= (1 << 24);
36b0c57d 11787 offset += pc + 4;
c19d1205 11788
36b0c57d
PB		 11789 /* BLX target addresses are always word aligned. */
11790 if ((given & 0x00001000u) == 0)
11791 offset &= ~2u;
11792
11793 info->print_address_func (offset, info);
1d67fe3b
TT		 11794
11795 /* Fill in instruction information. */
11796 info->insn_info_valid = 1;
11797 info->insn_type = dis_branch;
11798 info->target = offset;
c19d1205
ZW		 11799 }
11800 break;
11801
11802 case 's':
11803 {
11804 unsigned int shift = 0;
fe56b6ce 11805
c19d1205
ZW		 11806 shift |= (given & 0x000000c0u) >> 6;
11807 shift |= (given & 0x00007000u) >> 10;
c1e26897 11808 if (WRITEBACK_BIT_SET)
6576bffe
AB		 11809 {
11810 func (stream, dis_style_text, ", ");
11811 func (stream, dis_style_sub_mnemonic, "asr ");
11812 func (stream, dis_style_immediate, "#%u", shift);
11813 }
c19d1205 11814 else if (shift)
6576bffe
AB		 11815 {
11816 func (stream, dis_style_text, ", ");
11817 func (stream, dis_style_sub_mnemonic, "lsl ");
11818 func (stream, dis_style_immediate, "#%u", shift);
11819 }
c19d1205
ZW		 11820 /* else print nothing - lsl #0 */
11821 }
11822 break;
11823
11824 case 'R':
11825 {
11826 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11827
c19d1205 11828 if (rot)
6576bffe
AB		 11829 {
11830 func (stream, dis_style_text, ", ");
11831 func (stream, dis_style_sub_mnemonic, "ror ");
11832 func (stream, dis_style_immediate, "#%u", rot * 8);
11833 }
c19d1205
ZW		 11834 }
11835 break;
11836
62b3e311 11837 case 'U':
43e65147 11838 if ((given & 0xf0) == 0x60)
62b3e311 11839 {
52e7f43d
RE		 11840 switch (given & 0xf)
11841 {
6576bffe
AB		 11842 case 0xf:
11843 func (stream, dis_style_sub_mnemonic, "sy");
11844 break;
11845 default:
11846 func (stream, dis_style_immediate, "#%d",
11847 (int) given & 0xf);
11848 break;
52e7f43d 11849 }
62b3e311 11850 }
43e65147 11851 else
52e7f43d 11852 {
e797f7e0
MGD		 11853 const char * opt = data_barrier_option (given & 0xf);
11854 if (opt != NULL)
6576bffe 11855 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 11856 else
6576bffe
AB		 11857 func (stream, dis_style_immediate, "#%d",
11858 (int) given & 0xf);
52e7f43d 11859 }
62b3e311
PB		 11860 break;
11861
11862 case 'C':
11863 if ((given & 0xff) == 0)
11864 {
6576bffe
AB		 11865 func (stream, dis_style_register, "%cPSR_",
11866 (given & 0x100000) ? 'S' : 'C');
11867
62b3e311 11868 if (given & 0x800)
6576bffe 11869 func (stream, dis_style_register, "f");
62b3e311 11870 if (given & 0x400)
6576bffe 11871 func (stream, dis_style_register, "s");
62b3e311 11872 if (given & 0x200)
6576bffe 11873 func (stream, dis_style_register, "x");
62b3e311 11874 if (given & 0x100)
6576bffe 11875 func (stream, dis_style_register, "c");
62b3e311 11876 }
90ec0d68
MGD		 11877 else if ((given & 0x20) == 0x20)
11878 {
11879 char const* name;
11880 unsigned sysm = (given & 0xf00) >> 8;
11881
11882 sysm |= (given & 0x30);
11883 sysm |= (given & 0x00100000) >> 14;
11884 name = banked_regname (sysm);
43e65147 11885
90ec0d68 11886 if (name != NULL)
6576bffe 11887 func (stream, dis_style_register, "%s", name);
90ec0d68 11888 else
6576bffe
AB		 11889 func (stream, dis_style_text,
11890 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11891 }
62b3e311
PB		 11892 else
11893 {
6576bffe
AB		 11894 func (stream, dis_style_register, "%s",
11895 psr_name (given & 0xff));
62b3e311
PB		 11896 }
11897 break;
11898
11899 case 'D':
90ec0d68
MGD		 11900 if (((given & 0xff) == 0)
11901 || ((given & 0x20) == 0x20))
11902 {
11903 char const* name;
11904 unsigned sm = (given & 0xf0000) >> 16;
11905
11906 sm |= (given & 0x30);
11907 sm |= (given & 0x00100000) >> 14;
11908 name = banked_regname (sm);
11909
11910 if (name != NULL)
6576bffe 11911 func (stream, dis_style_register, "%s", name);
90ec0d68 11912 else
6576bffe
AB		 11913 func (stream, dis_style_text,
11914 "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11915 }
62b3e311 11916 else
6576bffe
AB		 11917 func (stream, dis_style_register, "%s",
11918 psr_name (given & 0xff));
62b3e311
PB		 11919 break;
11920
c19d1205
ZW		 11921 case '0': case '1': case '2': case '3': case '4':
11922 case '5': case '6': case '7': case '8': case '9':
11923 {
16980d0b
JB		 11924 int width;
11925 unsigned long val;
c19d1205 11926
16980d0b 11927 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11928
c19d1205
ZW		 11929 switch (*c)
11930 {
d052b9b7
AV		 11931 case 's':
11932 if (val <= 3)
6576bffe
AB		 11933 func (stream, dis_style_mnemonic, "%s",
11934 mve_vec_sizename[val]);
d052b9b7 11935 else
6576bffe 11936 func (stream, dis_style_text, "<undef size>");
d052b9b7
AV		 11937 break;
11938
05413229 11939 case 'd':
6576bffe 11940 func (stream, base_style, "%lu", val);
05413229
NC		 11941 value_in_comment = val;
11942 break;
ff4a8d2b 11943
f0fba320 11944 case 'D':
6576bffe 11945 func (stream, dis_style_immediate, "%lu", val + 1);
f0fba320
RL		 11946 value_in_comment = val + 1;
11947 break;
11948
05413229 11949 case 'W':
6576bffe 11950 func (stream, dis_style_immediate, "%lu", val * 4);
05413229
NC		 11951 value_in_comment = val * 4;
11952 break;
ff4a8d2b 11953
f1c7f421
AV		 11954 case 'S':
11955 if (val == 13)
78933a4a 11956 is_unpredictable = true;
f1c7f421 11957 /* Fall through. */
ff4a8d2b
NC		 11958 case 'R':
11959 if (val == 15)
78933a4a 11960 is_unpredictable = true;
ff4a8d2b
NC		 11961 /* Fall through. */
11962 case 'r':
6576bffe
AB		 11963 func (stream, dis_style_register, "%s",
11964 arm_regnames[val]);
ff4a8d2b 11965 break;
c19d1205
ZW		 11966
11967 case 'c':
6576bffe 11968 func (stream, base_style, "%s", arm_conditional[val]);
c19d1205
ZW		 11969 break;
11970
11971 case '\'':
c19d1205 11972 c++;
16980d0b 11973 if (val == ((1ul << width) - 1))
6576bffe 11974 func (stream, base_style, "%c", *c);
c19d1205 11975 break;
43e65147 11976
c19d1205 11977 case '`':
c19d1205 11978 c++;
16980d0b 11979 if (val == 0)
6576bffe 11980 func (stream, dis_style_immediate, "%c", *c);
c19d1205
ZW		 11981 break;
11982
11983 case '?':
6576bffe
AB		 11984 func (stream, dis_style_mnemonic, "%c",
11985 c[(1 << width) - (int) val]);
16980d0b 11986 c += 1 << width;
c19d1205 11987 break;
43e65147 11988
0bb027fd 11989 case 'x':
6576bffe
AB		 11990 func (stream, dis_style_immediate, "0x%lx",
11991 val & 0xffffffffUL);
0bb027fd 11992 break;
c19d1205
ZW		 11993
11994 default:
11995 abort ();
11996 }
11997 }
11998 break;
11999
32a94698
NC		 12000 case 'L':
12001 /* PR binutils/12534
12002 If we have a PC relative offset in an LDRD or STRD
12003 instructions then display the decoded address. */
12004 if (((given >> 16) & 0xf) == 0xf)
12005 {
12006 bfd_vma offset = (given & 0xff) * 4;
12007
12008 if ((given & (1 << 23)) == 0)
12009 offset = - offset;
6576bffe 12010 func (stream, dis_style_comment_start, "\t@ ");
32a94698
NC		 12011 info->print_address_func ((pc & ~3) + 4 + offset, info);
12012 }
12013 break;
12014
c19d1205
ZW		 12015 default:
12016 abort ();
12017 }
12018 }
05413229
NC		 12019
12020 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 12021 func (stream, dis_style_comment_start, "\t@ 0x%lx",
12022 value_in_comment);
ff4a8d2b
NC		 12023
12024 if (is_unpredictable)
6576bffe 12025 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 12026
4a5329c6 12027 return;
c19d1205 12028 }
252b5132 12029
58efb6c0 12030 /* No match. */
6576bffe
AB		 12031 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
12032 (unsigned) given);
0b347048 12033 return;
252b5132
RH		 12034}
12035
e821645d
DJ		 12036/* Print data bytes on INFO->STREAM. */
12037
12038static void
fe56b6ce
NC		 12039print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
12040 struct disassemble_info *info,
e821645d
DJ		 12041 long given)
12042{
6576bffe
AB		 12043 fprintf_styled_ftype func = info->fprintf_styled_func;
12044
e821645d
DJ		 12045 switch (info->bytes_per_chunk)
12046 {
12047 case 1:
6576bffe
AB		 12048 func (info->stream, dis_style_assembler_directive, ".byte");
12049 func (info->stream, dis_style_text, "\t");
12050 func (info->stream, dis_style_immediate, "0x%02lx", given);
e821645d
DJ		 12051 break;
12052 case 2:
6576bffe
AB		 12053 func (info->stream, dis_style_assembler_directive, ".short");
12054 func (info->stream, dis_style_text, "\t");
12055 func (info->stream, dis_style_immediate, "0x%04lx", given);
e821645d
DJ		 12056 break;
12057 case 4:
6576bffe
AB		 12058 func (info->stream, dis_style_assembler_directive, ".word");
12059 func (info->stream, dis_style_text, "\t");
12060 func (info->stream, dis_style_immediate, "0x%08lx", given);
e821645d
DJ		 12061 break;
12062 default:
12063 abort ();
12064 }
12065}
12066
22a398e1 12067/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 12068 being displayed in symbol relative addresses.
12069
12070 Also disallow private symbol, with __tagsym$$ prefix,
12071 from ARM RVCT toolchain being displayed. */
22a398e1 12072
78933a4a 12073bool
22a398e1
NC		 12074arm_symbol_is_valid (asymbol * sym,
12075 struct disassemble_info * info ATTRIBUTE_UNUSED)
12076{
12077 const char * name;
43e65147 12078
22a398e1 12079 if (sym == NULL)
78933a4a 12080 return false;
22a398e1
NC		 12081
12082 name = bfd_asymbol_name (sym);
12083
d8282f0e 12084 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 12085}
12086
65b48a81 12087/* Parse the string of disassembler options. */
baf0cc5e 12088
65b48a81 12089static void
f995bbe8 12090parse_arm_disassembler_options (const char *options)
dd92f639 12091{
f995bbe8 12092 const char *opt;
b34976b6 12093
cad152f2 12094 force_thumb = false;
65b48a81 12095 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 12096 {
08dedd66 12097 if (startswith (opt, "reg-names-"))
65b48a81
PB		 12098 {
12099 unsigned int i;
12100 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12101 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
12102 {
12103 regname_selected = i;
12104 break;
12105 }
b34976b6 12106
65b48a81 12107 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 12108 /* xgettext: c-format */
12109 opcodes_error_handler (_("unrecognised register name set: %s"),
12110 opt);
65b48a81 12111 }
08dedd66 12112 else if (startswith (opt, "force-thumb"))
65b48a81 12113 force_thumb = 1;
08dedd66 12114 else if (startswith (opt, "no-force-thumb"))
65b48a81 12115 force_thumb = 0;
08dedd66 12116 else if (startswith (opt, "coproc"))
4934a27c
MM		 12117 {
12118 const char *procptr = opt + sizeof ("coproc") - 1;
12119 char *endptr;
12120 uint8_t coproc_number = strtol (procptr, &endptr, 10);
12121 if (endptr != procptr + 1 || coproc_number > 7)
12122 {
12123 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
12124 opt);
12125 continue;
12126 }
12127 if (*endptr != '=')
12128 {
12129 opcodes_error_handler (_("coproc must have an argument: %s"),
12130 opt);
12131 continue;
12132 }
12133 endptr += 1;
08dedd66 12134 if (startswith (endptr, "generic"))
4934a27c 12135 cde_coprocs &= ~(1 << coproc_number);
08dedd66
ML		 12136 else if (startswith (endptr, "cde")
12137 || startswith (endptr, "CDE"))
4934a27c
MM		 12138 cde_coprocs |= (1 << coproc_number);
12139 else
12140 {
12141 opcodes_error_handler (
12142 _("coprocN argument takes options \"generic\","
12143 " \"cde\", or \"CDE\": %s"), opt);
12144 }
12145 }
65b48a81 12146 else
a6743a54
AM		 12147 /* xgettext: c-format */
12148 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 12149 }
b34976b6 12150
dd92f639
NC		 12151 return;
12152}
12153
78933a4a 12154static bool
5bc5ae88
RL		 12155mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12156 enum map_type *map_symbol);
12157
c22aaad1
PB		 12158/* Search back through the insn stream to determine if this instruction is
12159 conditionally executed. */
fe56b6ce 12160
c22aaad1 12161static void
fe56b6ce
NC		 12162find_ifthen_state (bfd_vma pc,
12163 struct disassemble_info *info,
78933a4a 12164 bool little)
c22aaad1
PB		 12165{
12166 unsigned char b[2];
12167 unsigned int insn;
12168 int status;
12169 /* COUNT is twice the number of instructions seen. It will be odd if we
12170 just crossed an instruction boundary. */
12171 int count;
12172 int it_count;
12173 unsigned int seen_it;
12174 bfd_vma addr;
12175
12176 ifthen_address = pc;
12177 ifthen_state = 0;
12178
12179 addr = pc;
12180 count = 1;
12181 it_count = 0;
12182 seen_it = 0;
12183 /* Scan backwards looking for IT instructions, keeping track of where
12184 instruction boundaries are. We don't know if something is actually an
12185 IT instruction until we find a definite instruction boundary. */
12186 for (;;)
12187 {
fe56b6ce 12188 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 12189 {
12190 /* A symbol must be on an instruction boundary, and will not
12191 be within an IT block. */
12192 if (seen_it && (count & 1))
12193 break;
12194
12195 return;
12196 }
12197 addr -= 2;
fe56b6ce 12198 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 12199 if (status)
12200 return;
12201
12202 if (little)
12203 insn = (b[0]) | (b[1] << 8);
12204 else
12205 insn = (b[1]) | (b[0] << 8);
12206 if (seen_it)
12207 {
12208 if ((insn & 0xf800) < 0xe800)
12209 {
12210 /* Addr + 2 is an instruction boundary. See if this matches
12211 the expected boundary based on the position of the last
12212 IT candidate. */
12213 if (count & 1)
12214 break;
12215 seen_it = 0;
12216 }
12217 }
12218 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12219 {
5bc5ae88 12220 enum map_type type = MAP_ARM;
78933a4a 12221 bool found = mapping_symbol_for_insn (addr, info, &type);
5bc5ae88
RL		 12222
12223 if (!found || (found && type == MAP_THUMB))
12224 {
12225 /* This could be an IT instruction. */
12226 seen_it = insn;
12227 it_count = count >> 1;
12228 }
c22aaad1
PB		 12229 }
12230 if ((insn & 0xf800) >= 0xe800)
12231 count++;
12232 else
12233 count = (count + 2) | 1;
12234 /* IT blocks contain at most 4 instructions. */
12235 if (count >= 8 && !seen_it)
12236 return;
12237 }
12238 /* We found an IT instruction. */
12239 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12240 if ((ifthen_state & 0xf) == 0)
12241 ifthen_state = 0;
12242}
12243
b0e28b39
DJ		 12244/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12245 mapping symbol. */
12246
12247static int
77186045
NC		 12248is_mapping_symbol (struct disassemble_info *info,
12249 int n,
b0e28b39
DJ		 12250 enum map_type *map_type)
12251{
77186045 12252 const char *name = bfd_asymbol_name (info->symtab[n]);
b0e28b39 12253
77186045
NC		 12254 if (name[0] == '$'
12255 && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
b0e28b39
DJ		 12256 && (name[2] == 0 || name[2] == '.'))
12257 {
12258 *map_type = ((name[1] == 'a') ? MAP_ARM
12259 : (name[1] == 't') ? MAP_THUMB
12260 : MAP_DATA);
78933a4a 12261 return true;
b0e28b39
DJ		 12262 }
12263
78933a4a 12264 return false;
b0e28b39
DJ		 12265}
12266
12267/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12268 Returns nonzero if *MAP_TYPE was set. */
12269
12270static int
12271get_map_sym_type (struct disassemble_info *info,
12272 int n,
12273 enum map_type *map_type)
12274{
12275 /* If the symbol is in a different section, ignore it. */
12276 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12277 return false;
b0e28b39
DJ		 12278
12279 return is_mapping_symbol (info, n, map_type);
12280}
12281
12282/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 12283 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 12284
12285static int
fe56b6ce
NC		 12286get_sym_code_type (struct disassemble_info *info,
12287 int n,
e821645d 12288 enum map_type *map_type)
2087ad84
PB		 12289{
12290 elf_symbol_type *es;
12291 unsigned int type;
77186045 12292 asymbol * sym;
b0e28b39
DJ		 12293
12294 /* If the symbol is in a different section, ignore it. */
12295 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12296 return false;
2087ad84 12297
77186045
NC		 12298 /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */
12299 sym = info->symtab[n];
12300 if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12301 return false;
12302
12303 es = (elf_symbol_type *) sym;
2087ad84
PB		 12304 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12305
12306 /* If the symbol has function type then use that. */
34e77a92 12307 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 12308 {
39d911fc
TP		 12309 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12310 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 12311 *map_type = MAP_THUMB;
12312 else
12313 *map_type = MAP_ARM;
78933a4a 12314 return true;
2087ad84
PB		 12315 }
12316
78933a4a 12317 return false;
2087ad84
PB		 12318}
12319
5bc5ae88
RL		 12320/* Search the mapping symbol state for instruction at pc. This is only
12321 applicable for elf target.
12322
12323 There is an assumption Here, info->private_data contains the correct AND
12324 up-to-date information about current scan process. The information will be
12325 used to speed this search process.
12326
12327 Return TRUE if the mapping state can be determined, and map_symbol
12328 will be updated accordingly. Otherwise, return FALSE. */
12329
78933a4a 12330static bool
5bc5ae88
RL		 12331mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12332 enum map_type *map_symbol)
12333{
796d6298
TC		 12334 bfd_vma addr, section_vma = 0;
12335 int n, last_sym = -1;
78933a4a
AM		 12336 bool found = false;
12337 bool can_use_search_opt_p = false;
796d6298 12338
76a95fac
LM		 12339 /* Sanity check. */
12340 if (info == NULL)
12341 return false;
12342
796d6298
TC		 12343 /* Default to DATA. A text section is required by the ABI to contain an
12344 INSN mapping symbol at the start. A data section has no such
12345 requirement, hence if no mapping symbol is found the section must
12346 contain only data. This however isn't very useful if the user has
12347 fully stripped the binaries. If this is the case use the section
12348 attributes to determine the default. If we have no section default to
12349 INSN as well, as we may be disassembling some raw bytes on a baremetal
12350 HEX file or similar. */
12351 enum map_type type = MAP_DATA;
12352 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12353 type = MAP_ARM;
5bc5ae88
RL		 12354 struct arm_private_data *private_data;
12355
76a95fac 12356 if (info->private_data == NULL || info->symtab == NULL
4eeb0013 12357 || info->symtab_size == 0
5bc5ae88 12358 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
78933a4a 12359 return false;
5bc5ae88
RL		 12360
12361 private_data = info->private_data;
5bc5ae88 12362
796d6298 12363 /* First, look for mapping symbols. */
4eeb0013
AM		 12364 if (pc <= private_data->last_mapping_addr)
12365 private_data->last_mapping_sym = -1;
12366
12367 /* Start scanning at the start of the function, or wherever
12368 we finished last time. */
12369 n = info->symtab_pos + 1;
12370
12371 /* If the last stop offset is different from the current one it means we
12372 are disassembling a different glob of bytes. As such the optimization
12373 would not be safe and we should start over. */
12374 can_use_search_opt_p
12375 = (private_data->last_mapping_sym >= 0
12376 && info->stop_offset == private_data->last_stop_offset);
12377
12378 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12379 n = private_data->last_mapping_sym;
12380
12381 /* Look down while we haven't passed the location being disassembled.
12382 The reason for this is that there's no defined order between a symbol
12383 and an mapping symbol that may be at the same address. We may have to
12384 look at least one position ahead. */
12385 for (; n < info->symtab_size; n++)
12386 {
12387 addr = bfd_asymbol_value (info->symtab[n]);
12388 if (addr > pc)
12389 break;
12390 if (get_map_sym_type (info, n, &type))
12391 {
12392 last_sym = n;
12393 found = true;
12394 }
12395 }
5bc5ae88 12396
4eeb0013
AM		 12397 if (!found)
12398 {
12399 n = info->symtab_pos;
12400 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12401 n = private_data->last_mapping_sym;
12402
12403 /* No mapping symbol found at this address. Look backwards
12404 for a preceeding one, but don't go pass the section start
12405 otherwise a data section with no mapping symbol can pick up
12406 a text mapping symbol of a preceeding section. The documentation
12407 says section can be NULL, in which case we will seek up all the
12408 way to the top. */
12409 if (info->section)
12410 section_vma = info->section->vma;
12411
12412 for (; n >= 0; n--)
12413 {
12414 addr = bfd_asymbol_value (info->symtab[n]);
12415 if (addr < section_vma)
12416 break;
796d6298 12417
4eeb0013
AM		 12418 if (get_map_sym_type (info, n, &type))
12419 {
12420 last_sym = n;
12421 found = true;
12422 break;
12423 }
12424 }
12425 }
796d6298
TC		 12426
12427 /* If no mapping symbol was found, try looking up without a mapping
12428 symbol. This is done by walking up from the current PC to the nearest
12429 symbol. We don't actually have to loop here since symtab_pos will
12430 contain the nearest symbol already. */
12431 if (!found)
5bc5ae88 12432 {
796d6298
TC		 12433 n = info->symtab_pos;
12434 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 12435 {
796d6298 12436 last_sym = n;
78933a4a 12437 found = true;
5bc5ae88
RL		 12438 }
12439 }
12440
796d6298
TC		 12441 private_data->last_mapping_sym = last_sym;
12442 private_data->last_type = type;
12443 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 12444
12445 *map_symbol = type;
12446 return found;
12447}
12448
0313a2b8
NC		 12449/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12450 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 12451 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 12452
12453 FIXME: This could more efficiently implemented as a constant array,
12454 although it would also be less robust. */
12455
12456static void
12457select_arm_features (unsigned long mach,
12458 arm_feature_set * features)
12459{
c0c468d5
TP		 12460 arm_feature_set arch_fset;
12461 const arm_feature_set fpu_any = FPU_ANY;
12462
1af1dd51
MW		 12463#undef ARM_SET_FEATURES
12464#define ARM_SET_FEATURES(FSET) \
12465 { \
12466 const arm_feature_set fset = FSET; \
c0c468d5 12467 arch_fset = fset; \
1af1dd51 12468 }
823d2571 12469
c0c468d5
TP		 12470 /* When several architecture versions share the same bfd_mach_arm_XXX value
12471 the most featureful is chosen. */
0313a2b8
NC		 12472 switch (mach)
12473 {
c0c468d5
TP		 12474 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
12475 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12476 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
12477 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12478 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
ad5da6e6 12479 case bfd_mach_arm_ep9312:
c0c468d5
TP		 12480 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12481 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
12482 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12483 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12484 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
c0c468d5
TP		 12485 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12486 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12487 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12488 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
12489 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12490 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12491 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12492 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12493 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12494 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12495 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12496 case bfd_mach_arm_8:
12497 {
aab2c27d
MM		 12498 /* Add bits for extensions that Armv8.6-A recognizes. */
12499 arm_feature_set armv8_6_ext_fset
0632eeea 12500 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 12501 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12502 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 12503 break;
12504 }
12505 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12506 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12507 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12508 case bfd_mach_arm_8_1M_MAIN:
12509 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12510 arm_feature_set mve_all
12511 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12512 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12513 force_thumb = 1;
12514 break;
3197e593 12515 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
c0c468d5 12516 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12517 extensions, with the exception of MVE as that clashes with NEON. */
12518 case bfd_mach_arm_unknown:
3197e593 12519 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
2da2eaf4 12520 break;
0313a2b8
NC		 12521 default:
12522 abort ();
12523 }
1af1dd51 12524#undef ARM_SET_FEATURES
c0c468d5
TP		 12525
12526 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12527 and thus on bfd_mach_arm_XXX value. Therefore for a given
12528 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12529 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12530}
12531
12532
58efb6c0
NC		 12533/* NOTE: There are no checks in these routines that
12534 the relevant number of data bytes exist. */
baf0cc5e 12535
58efb6c0 12536static int
78933a4a 12537print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
252b5132 12538{
c19d1205 12539 unsigned char b[4];
2480b6fa 12540 unsigned long given;
78933a4a
AM		 12541 int status;
12542 int is_thumb = false;
12543 int is_data = false;
12544 int little_code;
e821645d 12545 unsigned int size = 4;
78933a4a
AM		 12546 void (*printer) (bfd_vma, struct disassemble_info *, long);
12547 bool found = false;
b0e28b39 12548 struct arm_private_data *private_data;
58efb6c0 12549
1d67fe3b
TT		 12550 /* Clear instruction information field. */
12551 info->insn_info_valid = 0;
12552 info->branch_delay_insns = 0;
12553 info->data_size = 0;
12554 info->insn_type = dis_noninsn;
12555 info->target = 0;
12556 info->target2 = 0;
12557
dd92f639
NC		 12558 if (info->disassembler_options)
12559 {
65b48a81 12560 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12561
58efb6c0 12562 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12563 info->disassembler_options = NULL;
12564 }
b34976b6 12565
0313a2b8
NC		 12566 /* PR 10288: Control which instructions will be disassembled. */
12567 if (info->private_data == NULL)
12568 {
b0e28b39 12569 static struct arm_private_data private;
0313a2b8
NC		 12570
12571 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12572 /* If the user did not use the -m command line switch then default to
12573 disassembling all types of ARM instruction.
43e65147 12574
0313a2b8
NC		 12575 The info->mach value has to be ignored as this will be based on
12576 the default archictecture for the target and/or hints in the notes
12577 section, but it will never be greater than the current largest arm
12578 machine value (iWMMXt2), which is only equivalent to the V5TE
12579 architecture. ARM architectures have advanced beyond the machine
12580 value encoding, and these newer architectures would be ignored if
12581 the machine value was used.
12582
12583 Ie the -m switch is used to restrict which instructions will be
12584 disassembled. If it is necessary to use the -m switch to tell
12585 objdump that an ARM binary is being disassembled, eg because the
12586 input is a raw binary file, but it is also desired to disassemble
12587 all ARM instructions then use "-marm". This will select the
12588 "unknown" arm architecture which is compatible with any ARM
12589 instruction. */
12590 info->mach = bfd_mach_arm_unknown;
12591
12592 /* Compute the architecture bitmask from the machine number.
12593 Note: This assumes that the machine number will not change
12594 during disassembly.... */
b0e28b39 12595 select_arm_features (info->mach, & private.features);
0313a2b8 12596
1fbaefec
PB		 12597 private.last_mapping_sym = -1;
12598 private.last_mapping_addr = 0;
796d6298 12599 private.last_stop_offset = 0;
b0e28b39
DJ		 12600
12601 info->private_data = & private;
0313a2b8 12602 }
b0e28b39
DJ		 12603
12604 private_data = info->private_data;
12605
bd2e2557
SS		 12606 /* Decide if our code is going to be little-endian, despite what the
12607 function argument might say. */
12608 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12609
b0e28b39
DJ		 12610 /* For ELF, consult the symbol table to determine what kind of code
12611 or data we have. */
8977d4b2 12612 if (info->symtab_size != 0
e821645d
DJ		 12613 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12614 {
12615 bfd_vma addr;
796d6298 12616 int n;
e821645d 12617 int last_sym = -1;
b0e28b39 12618 enum map_type type = MAP_ARM;
e821645d 12619
796d6298
TC		 12620 found = mapping_symbol_for_insn (pc, info, &type);
12621 last_sym = private_data->last_mapping_sym;
e821645d 12622
1fbaefec
PB		 12623 is_thumb = (private_data->last_type == MAP_THUMB);
12624 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12625
e821645d
DJ		 12626 /* Look a little bit ahead to see if we should print out
12627 two or four bytes of data. If there's a symbol,
12628 mapping or otherwise, after two bytes then don't
12629 print more. */
12630 if (is_data)
12631 {
12632 size = 4 - (pc & 3);
12633 for (n = last_sym + 1; n < info->symtab_size; n++)
12634 {
12635 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12636 if (addr > pc
12637 && (info->section == NULL
12638 || info->section == info->symtab[n]->section))
e821645d
DJ		 12639 {
12640 if (addr - pc < size)
12641 size = addr - pc;
12642 break;
12643 }
12644 }
12645 /* If the next symbol is after three bytes, we need to
12646 print only part of the data, so that we can use either
12647 .byte or .short. */
12648 if (size == 3)
12649 size = (pc & 1) ? 1 : 2;
12650 }
12651 }
12652
12653 if (info->symbols != NULL)
252b5132 12654 {
5876e06d
NC		 12655 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12656 {
2f0ca46a 12657 coff_symbol_type * cs;
b34976b6 12658
5876e06d
NC		 12659 cs = coffsymbol (*info->symbols);
12660 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12661 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12662 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12663 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12664 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12665 }
e821645d
DJ		 12666 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12667 && !found)
5876e06d 12668 {
2087ad84
PB		 12669 /* If no mapping symbol has been found then fall back to the type
12670 of the function symbol. */
e821645d
DJ		 12671 elf_symbol_type * es;
12672 unsigned int type;
2087ad84 12673
e821645d
DJ		 12674 es = *(elf_symbol_type **)(info->symbols);
12675 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12676
39d911fc
TP		 12677 is_thumb =
12678 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12679 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12680 }
e49d43ff
TG		 12681 else if (bfd_asymbol_flavour (*info->symbols)
12682 == bfd_target_mach_o_flavour)
12683 {
12684 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12685
12686 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12687 }
5876e06d 12688 }
b34976b6 12689
e821645d 12690 if (force_thumb)
78933a4a 12691 is_thumb = true;
e821645d 12692
b8f9ee44
CL		 12693 if (is_data)
12694 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12695 else
12696 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12697
c19d1205 12698 info->bytes_per_line = 4;
252b5132 12699
1316c8b3
NC		 12700 /* PR 10263: Disassemble data if requested to do so by the user. */
12701 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12702 {
12703 int i;
12704
1316c8b3 12705 /* Size was already set above. */
e821645d
DJ		 12706 info->bytes_per_chunk = size;
12707 printer = print_insn_data;
12708
fe56b6ce 12709 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12710 given = 0;
12711 if (little)
12712 for (i = size - 1; i >= 0; i--)
12713 given = b[i] | (given << 8);
12714 else
12715 for (i = 0; i < (int) size; i++)
12716 given = b[i] | (given << 8);
12717 }
12718 else if (!is_thumb)
252b5132 12719 {
c19d1205
ZW		 12720 /* In ARM mode endianness is a straightforward issue: the instruction
12721 is four bytes long and is either ordered 0123 or 3210. */
12722 printer = print_insn_arm;
12723 info->bytes_per_chunk = 4;
4a5329c6 12724 size = 4;
c19d1205 12725
0313a2b8 12726 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12727 if (little_code)
2480b6fa 12728 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12729 else
2480b6fa 12730 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12731 }
58efb6c0 12732 else
252b5132 12733 {
c19d1205
ZW		 12734 /* In Thumb mode we have the additional wrinkle of two
12735 instruction lengths. Fortunately, the bits that determine
12736 the length of the current instruction are always to be found
12737 in the first two bytes. */
4a5329c6 12738 printer = print_insn_thumb16;
c19d1205 12739 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12740 size = 2;
12741
fe56b6ce 12742 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12743 if (little_code)
9a2ff3f5
AM		 12744 given = (b[0]) | (b[1] << 8);
12745 else
12746 given = (b[1]) | (b[0] << 8);
12747
c19d1205 12748 if (!status)
252b5132 12749 {
c19d1205
ZW		 12750 /* These bit patterns signal a four-byte Thumb
12751 instruction. */
12752 if ((given & 0xF800) == 0xF800
12753 || (given & 0xF800) == 0xF000
12754 || (given & 0xF800) == 0xE800)
252b5132 12755 {
0313a2b8 12756 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12757 if (little_code)
c19d1205 12758 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12759 else
c19d1205
ZW		 12760 given = (b[1]) | (b[0] << 8) | (given << 16);
12761
12762 printer = print_insn_thumb32;
4a5329c6 12763 size = 4;
252b5132 12764 }
252b5132 12765 }
c22aaad1
PB		 12766
12767 if (ifthen_address != pc)
0313a2b8 12768 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12769
12770 if (ifthen_state)
12771 {
12772 if ((ifthen_state & 0xf) == 0x8)
12773 ifthen_next_state = 0;
12774 else
12775 ifthen_next_state = (ifthen_state & 0xe0)
12776 | ((ifthen_state & 0xf) << 1);
12777 }
252b5132 12778 }
b34976b6 12779
c19d1205
ZW		 12780 if (status)
12781 {
12782 info->memory_error_func (status, pc, info);
12783 return -1;
12784 }
6a56ec7e
NC		 12785 if (info->flags & INSN_HAS_RELOC)
12786 /* If the instruction has a reloc associated with it, then
12787 the offset field in the instruction will actually be the
12788 addend for the reloc. (We are using REL type relocs).
12789 In such cases, we can ignore the pc when computing
12790 addresses, since the addend is not currently pc-relative. */
12791 pc = 0;
b34976b6 12792
4a5329c6 12793 printer (pc, info, given);
c22aaad1
PB		 12794
12795 if (is_thumb)
12796 {
12797 ifthen_state = ifthen_next_state;
12798 ifthen_address += size;
12799 }
4a5329c6 12800 return size;
252b5132
RH		 12801}
12802
12803int
4a5329c6 12804print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12805{
bd2e2557
SS		 12806 /* Detect BE8-ness and record it in the disassembler info. */
12807 if (info->flavour == bfd_target_elf_flavour
12808 && info->section != NULL
12809 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12810 info->endian_code = BFD_ENDIAN_LITTLE;
12811
78933a4a 12812 return print_insn (pc, info, false);
58efb6c0 12813}
01c7f630 12814
58efb6c0 12815int
4a5329c6 12816print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12817{
78933a4a 12818 return print_insn (pc, info, true);
58efb6c0 12819}
252b5132 12820
471b9d15 12821const disasm_options_and_args_t *
65b48a81
PB		 12822disassembler_options_arm (void)
12823{
471b9d15 12824 static disasm_options_and_args_t *opts_and_args;
65b48a81 12825
471b9d15 12826 if (opts_and_args == NULL)
65b48a81 12827 {
471b9d15 12828 disasm_options_t *opts;
65b48a81 12829 unsigned int i;
471b9d15
MR		 12830
12831 opts_and_args = XNEW (disasm_options_and_args_t);
12832 opts_and_args->args = NULL;
12833
12834 opts = &opts_and_args->options;
65b48a81
PB		 12835 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12836 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12837 opts->arg = NULL;
65b48a81
PB		 12838 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12839 {
12840 opts->name[i] = regnames[i].name;
12841 if (regnames[i].description != NULL)
12842 opts->description[i] = _(regnames[i].description);
12843 else
12844 opts->description[i] = NULL;
12845 }
12846 /* The array we return must be NULL terminated. */
12847 opts->name[i] = NULL;
12848 opts->description[i] = NULL;
12849 }
12850
471b9d15 12851 return opts_and_args;
65b48a81
PB		 12852}
12853
58efb6c0 12854void
4a5329c6 12855print_arm_disassembler_options (FILE *stream)
58efb6c0 12856{
65b48a81 12857 unsigned int i, max_len = 0;
58efb6c0
NC		 12858 fprintf (stream, _("\n\
12859The following ARM specific disassembler options are supported for use with\n\
12860the -M switch:\n"));
b34976b6 12861
65b48a81
PB		 12862 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12863 {
12864 unsigned int len = strlen (regnames[i].name);
12865 if (max_len < len)
12866 max_len = len;
12867 }
58efb6c0 12868
65b48a81
PB		 12869 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12870 fprintf (stream, " %s%*c %s\n",
12871 regnames[i].name,
12872 (int)(max_len - strlen (regnames[i].name)), ' ',
12873 _(regnames[i].description));
252b5132 12874}
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