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[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
e8e7cf2a 2 Copyright (C) 1994-2025 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
1fbaefec
PB		 42/* Cached mapping symbol state. */
43enum map_type
44{
45 MAP_ARM,
46 MAP_THUMB,
47 MAP_DATA
48};
49
b0e28b39
DJ		 50struct arm_private_data
51{
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features;
54
1fbaefec
PB		 55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type;
57
58 /* Tracking symbol table information */
59 int last_mapping_sym;
796d6298
TC		 60
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset;
1fbaefec 63 bfd_vma last_mapping_addr;
b0e28b39
DJ		 64};
65
73cd51e5
AV		 66enum mve_instructions
67{
143275ea
AV		 68 MVE_VPST,
69 MVE_VPT_FP_T1,
70 MVE_VPT_FP_T2,
71 MVE_VPT_VEC_T1,
72 MVE_VPT_VEC_T2,
73 MVE_VPT_VEC_T3,
74 MVE_VPT_VEC_T4,
75 MVE_VPT_VEC_T5,
76 MVE_VPT_VEC_T6,
77 MVE_VCMP_FP_T1,
78 MVE_VCMP_FP_T2,
79 MVE_VCMP_VEC_T1,
80 MVE_VCMP_VEC_T2,
81 MVE_VCMP_VEC_T3,
82 MVE_VCMP_VEC_T4,
83 MVE_VCMP_VEC_T5,
84 MVE_VCMP_VEC_T6,
9743db03
AV		 85 MVE_VDUP,
86 MVE_VEOR,
87 MVE_VFMAS_FP_SCALAR,
88 MVE_VFMA_FP_SCALAR,
89 MVE_VFMA_FP,
90 MVE_VFMS_FP,
91 MVE_VHADD_T1,
92 MVE_VHADD_T2,
93 MVE_VHSUB_T1,
94 MVE_VHSUB_T2,
95 MVE_VRHADD,
04d54ace
AV		 96 MVE_VLD2,
97 MVE_VLD4,
98 MVE_VST2,
99 MVE_VST4,
aef6d006
AV		 100 MVE_VLDRB_T1,
101 MVE_VLDRH_T2,
102 MVE_VLDRB_T5,
103 MVE_VLDRH_T6,
104 MVE_VLDRW_T7,
105 MVE_VSTRB_T1,
106 MVE_VSTRH_T2,
107 MVE_VSTRB_T5,
108 MVE_VSTRH_T6,
109 MVE_VSTRW_T7,
ef1576a1
AV		 110 MVE_VLDRB_GATHER_T1,
111 MVE_VLDRH_GATHER_T2,
112 MVE_VLDRW_GATHER_T3,
113 MVE_VLDRD_GATHER_T4,
114 MVE_VLDRW_GATHER_T5,
115 MVE_VLDRD_GATHER_T6,
116 MVE_VSTRB_SCATTER_T1,
117 MVE_VSTRH_SCATTER_T2,
118 MVE_VSTRW_SCATTER_T3,
119 MVE_VSTRD_SCATTER_T4,
120 MVE_VSTRW_SCATTER_T5,
121 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 122 MVE_VCVT_FP_FIX_VEC,
123 MVE_VCVT_BETWEEN_FP_INT,
124 MVE_VCVT_FP_HALF_FP,
125 MVE_VCVT_FROM_FP_TO_INT,
126 MVE_VRINT_FP,
c507f10b
AV		 127 MVE_VMOV_HFP_TO_GP,
128 MVE_VMOV_GP_TO_VEC_LANE,
129 MVE_VMOV_IMM_TO_VEC,
130 MVE_VMOV_VEC_TO_VEC,
131 MVE_VMOV2_VEC_LANE_TO_GP,
132 MVE_VMOV2_GP_TO_VEC_LANE,
133 MVE_VMOV_VEC_LANE_TO_GP,
134 MVE_VMVN_IMM,
135 MVE_VMVN_REG,
136 MVE_VORR_IMM,
137 MVE_VORR_REG,
138 MVE_VORN,
139 MVE_VBIC_IMM,
140 MVE_VBIC_REG,
141 MVE_VMOVX,
14925797
AV		 142 MVE_VMOVL,
143 MVE_VMOVN,
144 MVE_VMULL_INT,
145 MVE_VMULL_POLY,
146 MVE_VQDMULL_T1,
147 MVE_VQDMULL_T2,
148 MVE_VQMOVN,
149 MVE_VQMOVUN,
d3b63143
AV		 150 MVE_VADDV,
151 MVE_VMLADAV_T1,
152 MVE_VMLADAV_T2,
153 MVE_VMLALDAV,
154 MVE_VMLAS,
155 MVE_VADDLV,
156 MVE_VMLSDAV_T1,
157 MVE_VMLSDAV_T2,
158 MVE_VMLSLDAV,
159 MVE_VRMLALDAVH,
160 MVE_VRMLSLDAVH,
161 MVE_VQDMLADH,
162 MVE_VQRDMLADH,
163 MVE_VQDMLAH,
164 MVE_VQRDMLAH,
165 MVE_VQDMLASH,
166 MVE_VQRDMLASH,
167 MVE_VQDMLSDH,
168 MVE_VQRDMLSDH,
169 MVE_VQDMULH_T1,
170 MVE_VQRDMULH_T2,
171 MVE_VQDMULH_T3,
172 MVE_VQRDMULH_T4,
1c8f2df8
AV		 173 MVE_VDDUP,
174 MVE_VDWDUP,
175 MVE_VIWDUP,
176 MVE_VIDUP,
897b9bbc
AV		 177 MVE_VCADD_FP,
178 MVE_VCADD_VEC,
179 MVE_VHCADD,
180 MVE_VCMLA_FP,
181 MVE_VCMUL_FP,
ed63aa17
AV		 182 MVE_VQRSHL_T1,
183 MVE_VQRSHL_T2,
184 MVE_VQRSHRN,
185 MVE_VQRSHRUN,
186 MVE_VQSHL_T1,
187 MVE_VQSHL_T2,
188 MVE_VQSHLU_T3,
189 MVE_VQSHL_T4,
190 MVE_VQSHRN,
191 MVE_VQSHRUN,
192 MVE_VRSHL_T1,
193 MVE_VRSHL_T2,
194 MVE_VRSHR,
195 MVE_VRSHRN,
196 MVE_VSHL_T1,
197 MVE_VSHL_T2,
198 MVE_VSHL_T3,
199 MVE_VSHLC,
200 MVE_VSHLL_T1,
201 MVE_VSHLL_T2,
202 MVE_VSHR,
203 MVE_VSHRN,
204 MVE_VSLI,
205 MVE_VSRI,
66dcaa5d
AV		 206 MVE_VADC,
207 MVE_VABAV,
208 MVE_VABD_FP,
209 MVE_VABD_VEC,
210 MVE_VABS_FP,
211 MVE_VABS_VEC,
212 MVE_VADD_FP_T1,
213 MVE_VADD_FP_T2,
214 MVE_VADD_VEC_T1,
215 MVE_VADD_VEC_T2,
216 MVE_VSBC,
217 MVE_VSUB_FP_T1,
218 MVE_VSUB_FP_T2,
219 MVE_VSUB_VEC_T1,
220 MVE_VSUB_VEC_T2,
e523f101
AV		 221 MVE_VAND,
222 MVE_VBRSR,
223 MVE_VCLS,
224 MVE_VCLZ,
225 MVE_VCTP,
56858bea
AV		 226 MVE_VMAX,
227 MVE_VMAXA,
228 MVE_VMAXNM_FP,
229 MVE_VMAXNMA_FP,
230 MVE_VMAXNMV_FP,
231 MVE_VMAXNMAV_FP,
232 MVE_VMAXV,
233 MVE_VMAXAV,
234 MVE_VMIN,
235 MVE_VMINA,
236 MVE_VMINNM_FP,
237 MVE_VMINNMA_FP,
238 MVE_VMINNMV_FP,
239 MVE_VMINNMAV_FP,
240 MVE_VMINV,
241 MVE_VMINAV,
242 MVE_VMLA,
f49bb598
AV		 243 MVE_VMUL_FP_T1,
244 MVE_VMUL_FP_T2,
245 MVE_VMUL_VEC_T1,
246 MVE_VMUL_VEC_T2,
247 MVE_VMULH,
248 MVE_VRMULH,
249 MVE_VNEG_FP,
250 MVE_VNEG_VEC,
14b456f2
AV		 251 MVE_VPNOT,
252 MVE_VPSEL,
253 MVE_VQABS,
254 MVE_VQADD_T1,
255 MVE_VQADD_T2,
256 MVE_VQSUB_T1,
257 MVE_VQSUB_T2,
258 MVE_VQNEG,
259 MVE_VREV16,
260 MVE_VREV32,
261 MVE_VREV64,
23d00a41
SD		 262 MVE_LSLL,
263 MVE_LSLLI,
264 MVE_LSRL,
265 MVE_ASRL,
266 MVE_ASRLI,
267 MVE_SQRSHRL,
268 MVE_SQRSHR,
269 MVE_UQRSHL,
270 MVE_UQRSHLL,
271 MVE_UQSHL,
272 MVE_UQSHLL,
273 MVE_URSHRL,
274 MVE_URSHR,
275 MVE_SRSHRL,
276 MVE_SRSHR,
277 MVE_SQSHLL,
278 MVE_SQSHL,
e39c1607
SD		 279 MVE_CINC,
280 MVE_CINV,
281 MVE_CNEG,
282 MVE_CSINC,
283 MVE_CSINV,
284 MVE_CSET,
285 MVE_CSETM,
286 MVE_CSNEG,
287 MVE_CSEL,
73cd51e5
AV		 288 MVE_NONE
289};
290
291enum mve_unpredictable
292{
293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
294 */
143275ea
AV		 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
296 fcB = 1 (vpt). */
297 UNPRED_R13, /* Unpredictable because r13 (sp) or
298 r15 (sp) used. */
9743db03 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 300 UNPRED_Q_GT_4, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
305 and WB bit = 1. */
ef1576a1
AV		 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
307 equal. */
308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
310 same. */
c507f10b
AV		 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
312 size = 1. */
313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
314 size = 2. */
73cd51e5
AV		 315 UNPRED_NONE /* No unpredictable behavior. */
316};
317
318enum mve_undefined
319{
ed63aa17 320 UNDEF_SIZE, /* undefined size. */
bf0b396d 321 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 322 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 323 UNDEF_SIZE_3, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
329 size == 0. */
330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
331 size == 1. */
332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
336 op1 == (0 or 1). */
337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
340 in {0xx1, x0x1}. */
d3b63143 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 342 UNDEF_NONE /* no undefined behavior. */
343};
344
6b5d3a4d
ZW		 345struct opcode32
346{
823d2571
TG		 347 arm_feature_set arch; /* Architecture defining this insn. */
348 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 350 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 351};
352
4934a27c
MM		 353struct cdeopcode32
354{
355 arm_feature_set arch; /* Architecture defining this insn. */
356 uint8_t coproc_shift; /* coproc is this far into op. */
357 uint16_t coproc_mask; /* Length of coproc field in op. */
358 unsigned long value; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask; /* Recognise insn if (op & mask) == value. */
360 const char * assembler; /* How to disassemble this insn. */
361};
362
73cd51e5
AV		 363/* MVE opcodes. */
364
365struct mopcode32
366{
367 arm_feature_set arch; /* Architecture defining this insn. */
368 enum mve_instructions mve_op; /* Specific mve instruction for faster
369 decoding. */
370 unsigned long value; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask; /* Recognise insn if (op & mask) == value. */
372 const char * assembler; /* How to disassemble this insn. */
373};
374
6b0dd094
AV		 375enum isa {
376 ANY,
377 T32,
378 ARM
379};
380
381
382/* Shared (between Arm and Thumb mode) opcode. */
383struct sopcode32
384{
385 enum isa isa; /* Execution mode instruction availability. */
386 arm_feature_set arch; /* Architecture defining this insn. */
387 unsigned long value; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask; /* Recognise insn if (op & mask) == value. */
389 const char * assembler; /* How to disassemble this insn. */
390};
391
6b5d3a4d
ZW		 392struct opcode16
393{
823d2571 394 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 396 const char *assembler; /* How to disassemble this insn. */
397};
b7693d02 398
8f06b2d8 399/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 400
2fbad815 401 %% %
4a5329c6 402
c22aaad1 403 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 404 %b print condition code allowing cp_num == 9
37b37b2d 405 %q print shifter argument
e2efe87d
MGD		 406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
79171565 408 %A print address for ldc/stc instruction
16980d0b 409 %B print vstm/vldm register list
efd6b359 410 %C print vscclrm register list
32c36c3c
AV		 411 %J print register for VLDR instruction
412 %K print address for VLDR instruction
4a5329c6 413
33399f07 414 %<bitfield>c print as a condition code (for vsel)
4a5329c6 415 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 416 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
417 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 418 %<bitfield>d print the bitfield in decimal
16980d0b 419 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 420 %<bitfield>x print the bitfield in hex
421 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
4a5329c6
ZW		 422 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
423 %<bitfield>g print as an iWMMXt 64-bit register
424 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 425 %<bitfield>D print as a NEON D register
426 %<bitfield>Q print as a NEON Q register
c28eeff2 427 %<bitfield>V print as a NEON D or Q register
6f1c2142 428 %<bitfield>E print a quarter-float immediate value
4a5329c6 429
16980d0b 430 %y<code> print a single precision VFP reg.
2fbad815 431 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 432 %z<code> print a double precision VFP reg
2fbad815 433 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 434
16980d0b
JB		 435 %<bitfield>'c print specified char iff bitfield is all ones
436 %<bitfield>`c print specified char iff bitfield is all zeroes
437 %<bitfield>?ab... select from array of values in big endian order
43e65147 438
2fbad815 439 %L print as an iWMMXt N/M width field.
4a5329c6 440 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 441 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 442 versions.
443 %i print 5-bit immediate in bits 8,3..0
444 (print "32" when 0)
fe56b6ce 445 %r print register offset address for wldt/wstr instruction. */
2fbad815 446
21d799b5 447enum opcode_sentinel_enum
05413229
NC		 448{
449 SENTINEL_IWMMXT_START = 1,
450 SENTINEL_IWMMXT_END,
451 SENTINEL_GENERIC_START
452} opcode_sentinels;
453
8cb6e175
AB		 454#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
455#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
456#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
457#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
05413229 458
8f06b2d8 459/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 460
4934a27c
MM		 461/* print_insn_cde recognizes the following format control codes:
462
463 %% %
464
465 %a print 'a' iff bit 28 is 1
466 %p print bits 8-10 as coprocessor
467 %<bitfield>d print as decimal
468 %<bitfield>r print as an ARM register
469 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
470 %<bitfield>T print as an ARM register + 1
471 %<bitfield>R as %r but r13 is UNPREDICTABLE
472 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
473 %j print immediate taken from bits (16..21,7,0..5)
474 %k print immediate taken from bits (20..21,7,0..5).
475 %l print immediate taken from bits (20..22,7,4..5). */
476
477/* At the moment there is only one valid position for the coprocessor number,
478 and hence that's encoded in the macro below. */
479#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
480 { ARCH, 8, 7, VALUE, MASK, ASM }
481static const struct cdeopcode32 cde_opcodes[] =
482{
483 /* Custom Datapath Extension instructions. */
484 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
485 0xee000000, 0xefc00840,
6576bffe 486 "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 487 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
488 0xee000040, 0xefc00840,
6576bffe 489 "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 490
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492 0xee400000, 0xefc00840,
6576bffe 493 "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495 0xee400040, 0xefc00840,
6576bffe 496 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 497
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499 0xee800000, 0xef800840,
6576bffe 500 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c
MM		 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502 0xee800040, 0xef800840,
6576bffe 503 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c 504
5aae9ae9
MM		 505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506 0xec200000, 0xeeb00840,
6576bffe 507 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
5aae9ae9
MM		 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509 0xec200040, 0xeeb00840,
6576bffe 510 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
5aae9ae9
MM		 511
512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513 0xec300000, 0xeeb00840,
6576bffe 514 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
5aae9ae9
MM		 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516 0xec300040, 0xeeb00840,
6576bffe 517 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
5aae9ae9
MM		 518
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520 0xec800000, 0xee800840,
6576bffe 521 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
5aae9ae9
MM		 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523 0xec800040, 0xee800840,
6576bffe 524 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
5aae9ae9 525
4934a27c
MM		 526 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
527
528};
529
6b0dd094 530static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 531{
2fbad815 532 /* XScale instructions. */
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 534 0x0e200010, 0x0fff0ff0,
6576bffe 535 "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 537 0x0e280010, 0x0fff0ff0,
6576bffe 538 "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 540 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 542 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 544 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
05413229 545
2fbad815 546 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 547 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 549 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 553 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
6b0dd094 554 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 555 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 557 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 559 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 561 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 563 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 565 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 567 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 569 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 589 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 607 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 609 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 611 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 613 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 617 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 621 0x0e800120, 0x0f800ff0,
622 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 624 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 628 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 630 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 632 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 634 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 636 0x0e8000a0, 0x0f800ff0,
637 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 639 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 641 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 643 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 645 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 647 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 649 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 651 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 653 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 655 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 657 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 659 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 661 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 663 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 665 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 667 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 669 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 671 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 673 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 675 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 677 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 679 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 681 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 683 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 685 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 687 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 689 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 691 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 693 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 695 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 697 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 699 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 700 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 701 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 702
efd6b359
AV		 703 /* Armv8.1-M Mainline instructions. */
704 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
705 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
706 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
707 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
708
16a1fa25 709 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 710 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 711 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 712 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 713 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
714
fe56b6ce 715 /* Register load/store. */
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 717 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 719 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 721 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 723 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 725 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 727 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 729 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 731 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 733 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 735 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 737 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 739 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 741 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 743 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 745 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 747 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 748 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
749 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
750 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
751 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 752
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 754 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 756 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 758 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 760 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
16980d0b 761
fe56b6ce 762 /* Data transfer between ARM and NEON registers. */
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 764 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 766 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 768 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 770 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 772 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 774 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 776 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 778 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
8e79c3df 779 /* Half-precision conversion instructions. */
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 781 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 782 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 783 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 785 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 787 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 788
fe56b6ce 789 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 791 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
2da2eaf4 792 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 793 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
ba6cd17f 794 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 795 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 797 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 799 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 801 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 803 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 805 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 807 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
2da2eaf4 808 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 809 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
2da2eaf4 810 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 811 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
ba6cd17f 812 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 813 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
ba6cd17f 814 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 815 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 817 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 819 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
2da2eaf4 820 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 821 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
ba6cd17f 822 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 823 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 825 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 827 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
6b0dd094 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 829 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 831 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 833 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 835 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
2da2eaf4 836 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 837 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
2da2eaf4 838 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 839 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
ba6cd17f 840 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 841 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
ba6cd17f 842 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 843 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 845 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 847 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 849 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 851 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 853 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 857 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 859 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 861 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 863 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 865 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 867 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 869 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 871 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 873 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 875 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 877 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 879 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 881 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 883 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 885 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 887 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 889 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 891 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 893 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 895 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 897 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 899 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 901 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 903 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 905 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 907 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 909 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 911 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 913 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 915 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 917 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 919 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 921 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 923 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 925 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 927 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 929 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 931 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 933 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 935 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 937 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 939 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 941 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 943 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 945 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 947 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815 948
62f3b8c8 949 /* VFP Fused multiply add instructions. */
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 951 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 953 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 955 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 957 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 959 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 961 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 963 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 965 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 966
33399f07 967 /* FP v5. */
6b0dd094 968 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 969 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 971 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 973 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 975 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 977 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 979 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 981 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 983 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 985 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 987 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 989 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 991 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 992
6b0dd094 993 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 994 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 995 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 996 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 997 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 998 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 999 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1000 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1001 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1002 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1003 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1004 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1005 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1006 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1007 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1008 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
6b0dd094 1009 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1010 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
6b0dd094 1011 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1012 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
6b0dd094 1013 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1014 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
c28eeff2 1015
aab2c27d
MM		 1016 /* BFloat16 instructions. */
1017 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1018 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1019
c604a79a 1020 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1022 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
6576bffe 1024 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
c604a79a 1025
dec41383 1026 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1027 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1028 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1029 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1030 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1031 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1032 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1033 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1034 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1035 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1036 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1037 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1038 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1039 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1040 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
6b0dd094 1041 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1042 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
dec41383 1043
b0c11777
RL		 1044 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1045 cp_num: bit <11:8> == 0b1001.
1046 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1047 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1048 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1049 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1050 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1051 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1052 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1053 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1054 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
6b0dd094 1055 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1056 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1057 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1058 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1059 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1060 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1061 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1062 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1063 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1064 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1065 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1066 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1067 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1068 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1069 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1070 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1071 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1072 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1073 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1074 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1075 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1076 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1077 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1078 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1079 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1080 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1081 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1082 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1083 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1084 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1085 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1086 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1088 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1089 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1090 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1091 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1092 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1093 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1094 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1095 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1096 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 1097 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1098 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1099 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1100 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1101 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1102 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1103 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1104 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1105 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1106 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1107 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1108 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1109 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1110 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1111 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1112 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1113 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1114 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1115 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1116 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1117
49e8a725 1118 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1120 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1121
6b0dd094 1122 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1123};
1124
33593eaf
MM		 1125/* Generic coprocessor instructions. These are only matched if a more specific
1126 SIMD or co-processor instruction does not match first. */
1127
1128static const struct sopcode32 generic_coprocessor_opcodes[] =
1129{
1130 /* Generic coprocessor instructions. */
1131 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
6576bffe 1132 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
33593eaf
MM		 1133 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1134 0x0c500000, 0x0ff00000,
6576bffe 1135 "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1136 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1137 0x0e000000, 0x0f000010,
6576bffe 1138 "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1139 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1140 0x0e10f010, 0x0f10f010,
6576bffe 1141 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1142 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1143 0x0e100010, 0x0f100010,
6576bffe 1144 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1145 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1146 0x0e000010, 0x0f100010,
6576bffe 1147 "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf 1148 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1149 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1150 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1151 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1152
1153 /* V6 coprocessor instructions. */
1154 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1155 0xfc500000, 0xfff00000,
6576bffe 1156 "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1157 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1158 0xfc400000, 0xfff00000,
6576bffe 1159 "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
33593eaf
MM		 1160
1161 /* V5 coprocessor instructions. */
1162 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1163 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1164 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1165 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1166 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1167 0xfe000000, 0xff000010,
6576bffe 1168 "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1169 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1170 0xfe000010, 0xff100010,
6576bffe 1171 "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1172 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1173 0xfe100010, 0xff100010,
6576bffe 1174 "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1175
1176 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1177};
1178
16980d0b
JB		 1179/* Neon opcode table: This does not encode the top byte -- that is
1180 checked by the print_insn_neon routine, as it depends on whether we are
1181 doing thumb32 or arm32 disassembly. */
1182
1183/* print_insn_neon recognizes the following format control codes:
1184
1185 %% %
1186
c22aaad1 1187 %c print condition code
e2efe87d
MGD		 1188 %u print condition code (unconditional in ARM mode,
1189 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1190 %A print v{st,ld}[1234] operands
1191 %B print v{st,ld}[1234] any one operands
1192 %C print v{st,ld}[1234] single->all operands
1193 %D print scalar
1194 %E print vmov, vmvn, vorr, vbic encoded constant
1195 %F print vtbl,vtbx register list
1196
1197 %<bitfield>r print as an ARM register
1198 %<bitfield>d print the bitfield in decimal
1199 %<bitfield>e print the 2^N - bitfield in decimal
1200 %<bitfield>D print as a NEON D register
1201 %<bitfield>Q print as a NEON Q register
1202 %<bitfield>R print as a NEON D or Q register
1203 %<bitfield>Sn print byte scaled width limited by n
1204 %<bitfield>Tn print short scaled width limited by n
1205 %<bitfield>Un print long scaled width limited by n
43e65147 1206
16980d0b
JB		 1207 %<bitfield>'c print specified char iff bitfield is all ones
1208 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1209 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1210
1211static const struct opcode32 neon_opcodes[] =
1212{
fe56b6ce 1213 /* Extract. */
823d2571
TG		 1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215 0xf2b00840, 0xffb00850,
6576bffe 1216 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
823d2571
TG		 1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2b00000, 0xffb00810,
6576bffe 1219 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
16980d0b 1220
9743db03
AV		 1221 /* Data transfer between ARM and NEON registers. */
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1223 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1224 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1225 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1227 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1229 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1231 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1233 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1234
fe56b6ce 1235 /* Move data element to all lanes. */
823d2571 1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1237 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
823d2571 1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1239 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
823d2571 1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1241 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
16980d0b 1242
fe56b6ce 1243 /* Table lookup. */
823d2571
TG		 1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1248
8e79c3df 1249 /* Half-precision conversions. */
823d2571
TG		 1250 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1251 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1252 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1253 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1254
1255 /* NEON fused multiply add instructions. */
823d2571 1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1257 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1259 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1261 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1263 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1264
aab2c27d
MM		 1265 /* BFloat16 instructions. */
1266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1267 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1269 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
aab2c27d
MM		 1270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1271 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1273 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1275 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1277 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
aab2c27d 1278
616ce08e
MM		 1279 /* Matrix Multiply instructions. */
1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1281 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1283 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1285 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1287 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1289 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1290 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1291 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1292
fe56b6ce 1293 /* Two registers, miscellaneous. */
823d2571
TG		 1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1295 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1297 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1299 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1302 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1303 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1304 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1305 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1306 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1307 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1308 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1309 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1310 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1311 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1312 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1313 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1314 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1315 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3b20300, 0xffb30fd0,
6576bffe 1338 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
823d2571
TG		 1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1345 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1346 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1363 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1368 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1370 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1372 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1374 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1376 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571
TG		 1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1386 0xf3bb0600, 0xffbf0e10,
823d2571 1387 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1388 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1389 0xf3b70600, 0xffbf0e10,
1390 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1391
fe56b6ce 1392 /* Three registers of the same length. */
823d2571
TG		 1393 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1394 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1395 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1396 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1397 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1398 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1399 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1400 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1401 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1402 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1403 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1404 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1405 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1406 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1408 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1410 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1412 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1414 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1432 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1434 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1436 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1438 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1440 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1442 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1444 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1446 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1448 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1450 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1452 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1456 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1458 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1460 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1462 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1464 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1466 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1468 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1470 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1472 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1473 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1474 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1476 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1478 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1480 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1482 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1484 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1486 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1488 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1490 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1492 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1494 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1496 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1498 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1500 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1502 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf2000b00, 0xff800f10,
1511 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf2000b10, 0xff800f10,
1514 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3000b00, 0xff800f10,
1523 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf2000000, 0xfe800f10,
1526 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf2000010, 0xfe800f10,
1529 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531 0xf2000100, 0xfe800f10,
1532 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2000200, 0xfe800f10,
1535 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf2000210, 0xfe800f10,
1538 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2000300, 0xfe800f10,
1541 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf2000310, 0xfe800f10,
1544 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2000400, 0xfe800f10,
1547 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf2000410, 0xfe800f10,
1550 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2000500, 0xfe800f10,
1553 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2000510, 0xfe800f10,
1556 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2000600, 0xfe800f10,
1559 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2000610, 0xfe800f10,
1562 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2000700, 0xfe800f10,
1565 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf2000710, 0xfe800f10,
1568 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000910, 0xfe800f10,
1571 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2000a00, 0xfe800f10,
1574 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2000a10, 0xfe800f10,
1577 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1579 0xf3000b10, 0xff800f10,
1580 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1582 0xf3000c10, 0xff800f10,
1583 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1584
fe56b6ce 1585 /* One register and an immediate value. */
823d2571
TG		 1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1612
fe56b6ce 1613 /* Two registers and a shift amount. */
823d2571 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1615 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1617 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1619 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1621 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1623 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571
TG		 1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf2880950, 0xfeb80fd0,
6576bffe 1626 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1628 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
823d2571 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1630 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1632 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1634 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1636 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1638 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1640 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1642 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1644 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1646 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571
TG		 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf2900950, 0xfeb00fd0,
6576bffe 1649 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1651 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
823d2571 1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1653 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1655 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1657 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1659 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1661 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1663 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1665 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1667 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1669 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1671 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1673 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1675 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
823d2571 1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1677 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1679 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1681 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1683 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1685 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1687 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1689 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1691 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571
TG		 1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2a00950, 0xfea00fd0,
6576bffe 1694 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1696 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1698 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1700 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1702 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1704 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1706 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1708 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1710 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1712 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1714 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1716 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1718 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1720 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1722 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1724 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1726 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1728 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1730 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571
TG		 1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2a00e10, 0xfea00e90,
6576bffe 1733 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
cc933301
JW		 1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735 0xf2a00c10, 0xfea00e90,
6576bffe 1736 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
16980d0b 1737
fe56b6ce 1738 /* Three registers of different lengths. */
823d2571
TG		 1739 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1740 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2800400, 0xff800f50,
1745 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2800600, 0xff800f50,
1748 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2800900, 0xff800f50,
1751 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2800b00, 0xff800f50,
1754 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf2800d00, 0xff800f50,
1757 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf3800400, 0xff800f50,
1760 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf3800600, 0xff800f50,
1763 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800000, 0xfe800f50,
1766 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2800100, 0xfe800f50,
1769 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2800200, 0xfe800f50,
1772 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774 0xf2800300, 0xfe800f50,
1775 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2800500, 0xfe800f50,
1778 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2800700, 0xfe800f50,
1781 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf2800800, 0xfe800f50,
1784 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2800a00, 0xfe800f50,
1787 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf2800c00, 0xfe800f50,
1790 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1791
fe56b6ce 1792 /* Two registers and a scalar. */
823d2571
TG		 1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1796 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1797 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1798 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1804 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1805 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1806 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1812 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1813 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1814 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1824 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1825 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1826 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1830 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1831 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1832 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1836 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1837 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1838 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2800240, 0xfe800f50,
1845 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2800640, 0xfe800f50,
1848 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2800a40, 0xfe800f50,
1851 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1853 0xf2800e40, 0xff800f50,
1854 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1856 0xf2800f40, 0xff800f50,
1857 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1859 0xf3800e40, 0xff800f50,
1860 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1862 0xf3800f40, 0xff800f50,
1863 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1864 },
16980d0b 1865
fe56b6ce 1866 /* Element and structure load/store. */
823d2571
TG		 1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1905
1906 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1907};
1908
73cd51e5
AV		 1909/* mve opcode table. */
1910
1911/* print_insn_mve recognizes the following format control codes:
1912
1913 %% %
1914
ef1576a1
AV		 1915 %a print '+' or '-' or imm offset in vldr[bhwd] and
1916 vstr[bhwd]
9743db03 1917 %c print condition code
aef6d006
AV		 1918 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1919 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1920 %i print MVE predicate(s) for vpt and vpst
23d00a41 1921 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 1922 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 1923 %m print rounding mode for vcvt and vrint
143275ea 1924 %n print vector comparison code for predicated instruction
bf0b396d 1925 %s print size for various vcvt instructions
143275ea
AV		 1926 %v print vector predicate for instruction in predicated
1927 block
ef1576a1 1928 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1929 %w print writeback mode for MVE v{st,ld}[24]
1930 %B print v{st,ld}[24] any one operands
c507f10b
AV		 1931 %E print vmov, vmvn, vorr, vbic encoded constant
1932 %N print generic index for vmov
14925797 1933 %T print bottom ('b') or top ('t') of source register
d3b63143 1934 %X print exchange field in vmla* instructions
04d54ace 1935
9743db03 1936 %<bitfield>r print as an ARM register
04d54ace 1937 %<bitfield>d print the bitfield in decimal
d3b63143 1938 %<bitfield>A print accumulate or not
e39c1607
SD		 1939 %<bitfield>c print bitfield as a condition code
1940 %<bitfield>C print bitfield as an inverted condition code
143275ea 1941 %<bitfield>Q print as a MVE Q register
c507f10b 1942 %<bitfield>F print as a MVE S register
143275ea
AV		 1943 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1944 UNPREDICTABLE
23d00a41
SD		 1945
1946 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 1947 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 1948 %<bitfield>I print carry flag or not
ef1576a1 1949 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 1950 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 1951 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 1952 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 1953 %<bitfield>o print rotate value for vcmul
1c8f2df8 1954 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 1955 %<bitfield>x print the bitfield in hex.
1c8f2df8 1956 */
73cd51e5
AV		 1957
1958static const struct mopcode32 mve_opcodes[] =
1959{
143275ea
AV		 1960 /* MVE. */
1961
2da2eaf4 1962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 1963 MVE_VPST,
1964 0xfe310f4d, 0xffbf1fff,
1965 "vpst%i"
1966 },
1967
1968 /* Floating point VPT T1. */
2da2eaf4 1969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 1970 MVE_VPT_FP_T1,
1971 0xee310f00, 0xefb10f50,
1972 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1973 /* Floating point VPT T2. */
2da2eaf4 1974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 1975 MVE_VPT_FP_T2,
1976 0xee310f40, 0xefb10f50,
1977 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1978
1979 /* Vector VPT T1. */
2da2eaf4 1980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 1981 MVE_VPT_VEC_T1,
1982 0xfe010f00, 0xff811f51,
1983 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1984 /* Vector VPT T2. */
2da2eaf4 1985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 1986 MVE_VPT_VEC_T2,
1987 0xfe010f01, 0xff811f51,
1988 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1989 /* Vector VPT T3. */
2da2eaf4 1990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 1991 MVE_VPT_VEC_T3,
1992 0xfe011f00, 0xff811f50,
1993 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1994 /* Vector VPT T4. */
2da2eaf4 1995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 1996 MVE_VPT_VEC_T4,
1997 0xfe010f40, 0xff811f70,
1998 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1999 /* Vector VPT T5. */
2da2eaf4 2000 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2001 MVE_VPT_VEC_T5,
2002 0xfe010f60, 0xff811f70,
2003 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2004 /* Vector VPT T6. */
2da2eaf4 2005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2006 MVE_VPT_VEC_T6,
2007 0xfe011f40, 0xff811f50,
2008 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2009
c507f10b 2010 /* Vector VBIC immediate. */
2da2eaf4 2011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2012 MVE_VBIC_IMM,
2013 0xef800070, 0xefb81070,
2014 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2015
2016 /* Vector VBIC register. */
2da2eaf4 2017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2018 MVE_VBIC_REG,
2019 0xef100150, 0xffb11f51,
2020 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2021
66dcaa5d 2022 /* Vector VABAV. */
2da2eaf4 2023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2024 MVE_VABAV,
2025 0xee800f01, 0xefc10f51,
2026 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2027
2028 /* Vector VABD floating point. */
2da2eaf4 2029 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2030 MVE_VABD_FP,
2031 0xff200d40, 0xffa11f51,
2032 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2033
2034 /* Vector VABD. */
2da2eaf4 2035 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2036 MVE_VABD_VEC,
2037 0xef000740, 0xef811f51,
2038 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2039
2040 /* Vector VABS floating point. */
2da2eaf4 2041 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2042 MVE_VABS_FP,
2043 0xFFB10740, 0xFFB31FD1,
2044 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2045 /* Vector VABS. */
2da2eaf4 2046 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2047 MVE_VABS_VEC,
2048 0xffb10340, 0xffb31fd1,
2049 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2050
2051 /* Vector VADD floating point T1. */
2da2eaf4 2052 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2053 MVE_VADD_FP_T1,
2054 0xef000d40, 0xffa11f51,
2055 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2056 /* Vector VADD floating point T2. */
2da2eaf4 2057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2058 MVE_VADD_FP_T2,
2059 0xee300f40, 0xefb11f70,
2060 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2061 /* Vector VADD T1. */
2da2eaf4 2062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2063 MVE_VADD_VEC_T1,
2064 0xef000840, 0xff811f51,
2065 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2066 /* Vector VADD T2. */
2da2eaf4 2067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2068 MVE_VADD_VEC_T2,
2069 0xee010f40, 0xff811f70,
2070 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2071
d3b63143 2072 /* Vector VADDLV. */
2da2eaf4 2073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2074 MVE_VADDLV,
2075 0xee890f00, 0xef8f1fd1,
2076 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2077
2078 /* Vector VADDV. */
2da2eaf4 2079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2080 MVE_VADDV,
2081 0xeef10f00, 0xeff31fd1,
2082 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2083
66dcaa5d 2084 /* Vector VADC. */
2da2eaf4 2085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2086 MVE_VADC,
2087 0xee300f00, 0xffb10f51,
2088 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2089
e523f101 2090 /* Vector VAND. */
2da2eaf4 2091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2092 MVE_VAND,
2093 0xef000150, 0xffb11f51,
2094 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2095
2096 /* Vector VBRSR register. */
2da2eaf4 2097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2098 MVE_VBRSR,
2099 0xfe011e60, 0xff811f70,
2100 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2101
897b9bbc 2102 /* Vector VCADD floating point. */
2da2eaf4 2103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2104 MVE_VCADD_FP,
2105 0xfc800840, 0xfea11f51,
6576bffe 2106 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
897b9bbc
AV		 2107
2108 /* Vector VCADD. */
2da2eaf4 2109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2110 MVE_VCADD_VEC,
2111 0xfe000f00, 0xff810f51,
6576bffe 2112 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2113
e523f101 2114 /* Vector VCLS. */
2da2eaf4 2115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2116 MVE_VCLS,
2117 0xffb00440, 0xffb31fd1,
2118 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2119
2120 /* Vector VCLZ. */
2da2eaf4 2121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2122 MVE_VCLZ,
2123 0xffb004c0, 0xffb31fd1,
2124 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2125
897b9bbc 2126 /* Vector VCMLA. */
2da2eaf4 2127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2128 MVE_VCMLA_FP,
2129 0xfc200840, 0xfe211f51,
6576bffe 2130 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
897b9bbc 2131
143275ea 2132 /* Vector VCMP floating point T1. */
2da2eaf4 2133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2134 MVE_VCMP_FP_T1,
2135 0xee310f00, 0xeff1ef50,
2136 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2137
2138 /* Vector VCMP floating point T2. */
2da2eaf4 2139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2140 MVE_VCMP_FP_T2,
2141 0xee310f40, 0xeff1ef50,
2142 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2143
2144 /* Vector VCMP T1. */
2da2eaf4 2145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2146 MVE_VCMP_VEC_T1,
2147 0xfe010f00, 0xffc1ff51,
2148 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2149 /* Vector VCMP T2. */
2da2eaf4 2150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2151 MVE_VCMP_VEC_T2,
2152 0xfe010f01, 0xffc1ff51,
2153 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2154 /* Vector VCMP T3. */
2da2eaf4 2155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2156 MVE_VCMP_VEC_T3,
2157 0xfe011f00, 0xffc1ff50,
2158 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2159 /* Vector VCMP T4. */
2da2eaf4 2160 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2161 MVE_VCMP_VEC_T4,
2162 0xfe010f40, 0xffc1ff70,
2163 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2164 /* Vector VCMP T5. */
2da2eaf4 2165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2166 MVE_VCMP_VEC_T5,
2167 0xfe010f60, 0xffc1ff70,
2168 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2169 /* Vector VCMP T6. */
2da2eaf4 2170 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2171 MVE_VCMP_VEC_T6,
2172 0xfe011f40, 0xffc1ff50,
2173 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2174
9743db03 2175 /* Vector VDUP. */
2da2eaf4 2176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2177 MVE_VDUP,
2178 0xeea00b10, 0xffb10f5f,
2179 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2180
2181 /* Vector VEOR. */
2da2eaf4 2182 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2183 MVE_VEOR,
2184 0xff000150, 0xffd11f51,
2185 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2186
2187 /* Vector VFMA, vector * scalar. */
2da2eaf4 2188 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2189 MVE_VFMA_FP_SCALAR,
2190 0xee310e40, 0xefb11f70,
2191 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2192
2193 /* Vector VFMA floating point. */
2da2eaf4 2194 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2195 MVE_VFMA_FP,
2196 0xef000c50, 0xffa11f51,
2197 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2198
2199 /* Vector VFMS floating point. */
2da2eaf4 2200 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2201 MVE_VFMS_FP,
2202 0xef200c50, 0xffa11f51,
2203 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2204
2205 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2206 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2207 MVE_VFMAS_FP_SCALAR,
2208 0xee311e40, 0xefb11f70,
2209 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2210
2211 /* Vector VHADD T1. */
2da2eaf4 2212 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2213 MVE_VHADD_T1,
2214 0xef000040, 0xef811f51,
2215 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
2217 /* Vector VHADD T2. */
2da2eaf4 2218 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2219 MVE_VHADD_T2,
2220 0xee000f40, 0xef811f70,
2221 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2222
2223 /* Vector VHSUB T1. */
2da2eaf4 2224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2225 MVE_VHSUB_T1,
2226 0xef000240, 0xef811f51,
2227 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228
2229 /* Vector VHSUB T2. */
2da2eaf4 2230 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2231 MVE_VHSUB_T2,
2232 0xee001f40, 0xef811f70,
2233 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2234
897b9bbc 2235 /* Vector VCMUL. */
2da2eaf4 2236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2237 MVE_VCMUL_FP,
2238 0xee300e00, 0xefb10f50,
6576bffe 2239 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
897b9bbc 2240
e523f101 2241 /* Vector VCTP. */
2da2eaf4 2242 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2243 MVE_VCTP,
2244 0xf000e801, 0xffc0ffff,
2245 "vctp%v.%20-21s\t%16-19r"},
2246
9743db03 2247 /* Vector VDUP. */
2da2eaf4 2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2249 MVE_VDUP,
2250 0xeea00b10, 0xffb10f5f,
2251 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2252
2253 /* Vector VRHADD. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2255 MVE_VRHADD,
2256 0xef000140, 0xef811f51,
2257 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2258
bf0b396d 2259 /* Vector VCVT. */
2da2eaf4 2260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2261 MVE_VCVT_FP_FIX_VEC,
2262 0xef800c50, 0xef801cd1,
6576bffe 2263 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
bf0b396d
AV		 2264
2265 /* Vector VCVT. */
2da2eaf4 2266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2267 MVE_VCVT_BETWEEN_FP_INT,
2268 0xffb30640, 0xffb31e51,
2269 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2270
2271 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2273 MVE_VCVT_FP_HALF_FP,
2274 0xee3f0e01, 0xefbf1fd1,
2275 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2276
2277 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2278 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2279 MVE_VCVT_FP_HALF_FP,
2280 0xee3f1e01, 0xefbf1fd1,
2281 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2282
2283 /* Vector VCVT. */
2da2eaf4 2284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2285 MVE_VCVT_FROM_FP_TO_INT,
2286 0xffb30040, 0xffb31c51,
2287 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2288
1c8f2df8 2289 /* Vector VDDUP. */
2da2eaf4 2290 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2291 MVE_VDDUP,
2292 0xee011f6e, 0xff811f7e,
6576bffe 2293 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8
AV		 2294
2295 /* Vector VDWDUP. */
2da2eaf4 2296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2297 MVE_VDWDUP,
2298 0xee011f60, 0xff811f70,
6576bffe 2299 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8 2300
897b9bbc 2301 /* Vector VHCADD. */
2da2eaf4 2302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2303 MVE_VHCADD,
2304 0xee000f00, 0xff810f51,
6576bffe 2305 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2306
1c8f2df8 2307 /* Vector VIWDUP. */
2da2eaf4 2308 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2309 MVE_VIWDUP,
2310 0xee010f60, 0xff811f70,
6576bffe 2311 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8
AV		 2312
2313 /* Vector VIDUP. */
2da2eaf4 2314 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2315 MVE_VIDUP,
2316 0xee010f6e, 0xff811f7e,
6576bffe 2317 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8 2318
04d54ace 2319 /* Vector VLD2. */
2da2eaf4 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2321 MVE_VLD2,
2322 0xfc901e00, 0xff901e5f,
2323 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2324
2325 /* Vector VLD4. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2327 MVE_VLD4,
2328 0xfc901e01, 0xff901e1f,
2329 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2330
ef1576a1 2331 /* Vector VLDRB gather load. */
2da2eaf4 2332 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2333 MVE_VLDRB_GATHER_T1,
2334 0xec900e00, 0xefb01e50,
2335 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2336
2337 /* Vector VLDRH gather load. */
2da2eaf4 2338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2339 MVE_VLDRH_GATHER_T2,
2340 0xec900e10, 0xefb01e50,
2341 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2342
2343 /* Vector VLDRW gather load. */
2da2eaf4 2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2345 MVE_VLDRW_GATHER_T3,
2346 0xfc900f40, 0xffb01fd0,
2347 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2348
2349 /* Vector VLDRD gather load. */
2da2eaf4 2350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2351 MVE_VLDRD_GATHER_T4,
2352 0xec900fd0, 0xefb01fd0,
2353 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2354
2355 /* Vector VLDRW gather load. */
2da2eaf4 2356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2357 MVE_VLDRW_GATHER_T5,
2358 0xfd101e00, 0xff111f00,
6576bffe 2359 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 2360
2361 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2363 MVE_VLDRD_GATHER_T6,
2364 0xfd101f00, 0xff111f00,
6576bffe 2365 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 2366
aef6d006 2367 /* Vector VLDRB. */
2da2eaf4 2368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2369 MVE_VLDRB_T1,
2370 0xec100e00, 0xee581e00,
2371 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2372
2373 /* Vector VLDRH. */
2da2eaf4 2374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2375 MVE_VLDRH_T2,
2376 0xec180e00, 0xee581e00,
2377 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2378
2379 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2381 MVE_VLDRB_T5,
2382 0xec101e00, 0xfe101f80,
2383 "vldrb%v.u8\t%13-15,22Q, %d"},
2384
2385 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2386 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2387 MVE_VLDRH_T6,
2388 0xec101e80, 0xfe101f80,
2389 "vldrh%v.u16\t%13-15,22Q, %d"},
2390
2391 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2393 MVE_VLDRW_T7,
2394 0xec101f00, 0xfe101f80,
2395 "vldrw%v.u32\t%13-15,22Q, %d"},
2396
56858bea 2397 /* Vector VMAX. */
2da2eaf4 2398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2399 MVE_VMAX,
2400 0xef000640, 0xef811f51,
2401 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2402
2403 /* Vector VMAXA. */
2da2eaf4 2404 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2405 MVE_VMAXA,
2406 0xee330e81, 0xffb31fd1,
2407 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2408
2409 /* Vector VMAXNM floating point. */
2da2eaf4 2410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2411 MVE_VMAXNM_FP,
2412 0xff000f50, 0xffa11f51,
2413 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2414
2415 /* Vector VMAXNMA floating point. */
2da2eaf4 2416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2417 MVE_VMAXNMA_FP,
2418 0xee3f0e81, 0xefbf1fd1,
2419 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2420
2421 /* Vector VMAXNMV floating point. */
2da2eaf4 2422 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2423 MVE_VMAXNMV_FP,
2424 0xeeee0f00, 0xefff0fd1,
2425 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2426
2427 /* Vector VMAXNMAV floating point. */
2da2eaf4 2428 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2429 MVE_VMAXNMAV_FP,
2430 0xeeec0f00, 0xefff0fd1,
2431 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2432
2433 /* Vector VMAXV. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2435 MVE_VMAXV,
2436 0xeee20f00, 0xeff30fd1,
2437 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2438
2439 /* Vector VMAXAV. */
2da2eaf4 2440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2441 MVE_VMAXAV,
2442 0xeee00f00, 0xfff30fd1,
2443 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2444
2445 /* Vector VMIN. */
2da2eaf4 2446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2447 MVE_VMIN,
2448 0xef000650, 0xef811f51,
2449 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2450
2451 /* Vector VMINA. */
2da2eaf4 2452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2453 MVE_VMINA,
2454 0xee331e81, 0xffb31fd1,
2455 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2456
2457 /* Vector VMINNM floating point. */
2da2eaf4 2458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2459 MVE_VMINNM_FP,
2460 0xff200f50, 0xffa11f51,
2461 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2462
2463 /* Vector VMINNMA floating point. */
2da2eaf4 2464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2465 MVE_VMINNMA_FP,
2466 0xee3f1e81, 0xefbf1fd1,
2467 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2468
2469 /* Vector VMINNMV floating point. */
2da2eaf4 2470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2471 MVE_VMINNMV_FP,
2472 0xeeee0f80, 0xefff0fd1,
2473 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2474
2475 /* Vector VMINNMAV floating point. */
2da2eaf4 2476 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2477 MVE_VMINNMAV_FP,
2478 0xeeec0f80, 0xefff0fd1,
2479 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2480
2481 /* Vector VMINV. */
2da2eaf4 2482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2483 MVE_VMINV,
2484 0xeee20f80, 0xeff30fd1,
2485 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2486
2487 /* Vector VMINAV. */
2da2eaf4 2488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2489 MVE_VMINAV,
2490 0xeee00f80, 0xfff30fd1,
2491 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2492
2493 /* Vector VMLA. */
2da2eaf4 2494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2495 MVE_VMLA,
2496 0xee010e40, 0xef811f70,
3e562e4b 2497 "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
56858bea 2498
d3b63143
AV		 2499 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2500 opcode aliasing. */
2da2eaf4 2501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2502 MVE_VMLALDAV,
2503 0xee801e00, 0xef801f51,
2504 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2505
2da2eaf4 2506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2507 MVE_VMLALDAV,
2508 0xee800e00, 0xef801f51,
2509 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2510
2511 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2513 MVE_VMLADAV_T1,
2514 0xeef00e00, 0xeff01f51,
2515 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2516
2517 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2519 MVE_VMLADAV_T2,
2520 0xeef00f00, 0xeff11f51,
2521 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2522
2523 /* Vector VMLADAV T1 variant. */
2da2eaf4 2524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2525 MVE_VMLADAV_T1,
2526 0xeef01e00, 0xeff01f51,
2527 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2528
2529 /* Vector VMLADAV T2 variant. */
2da2eaf4 2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2531 MVE_VMLADAV_T2,
2532 0xeef01f00, 0xeff11f51,
2533 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2534
2535 /* Vector VMLAS. */
2da2eaf4 2536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2537 MVE_VMLAS,
2538 0xee011e40, 0xef811f70,
2539 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2540
2541 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2542 opcode aliasing. */
2da2eaf4 2543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2544 MVE_VRMLSLDAVH,
2545 0xfe800e01, 0xff810f51,
2546 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2547
2548 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2549 opcdoe aliasing. */
2da2eaf4 2550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2551 MVE_VMLSLDAV,
2552 0xee800e01, 0xff800f51,
2553 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2554
2555 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2557 MVE_VMLSDAV_T1,
2558 0xeef00e01, 0xfff00f51,
2559 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2560
2561 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2563 MVE_VMLSDAV_T2,
2564 0xfef00e01, 0xfff10f51,
2565 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2566
c507f10b 2567 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2569 MVE_VMOV_HFP_TO_GP,
2570 0xee000910, 0xfff00f7f,
2571 "vmov.f16\t%7,16-19F, %12-15r"},
2572
2573 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2575 MVE_VMOV_HFP_TO_GP,
2576 0xee100910, 0xfff00f7f,
2577 "vmov.f16\t%12-15r, %7,16-19F"},
2578
2da2eaf4 2579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2580 MVE_VMOV_GP_TO_VEC_LANE,
2581 0xee000b10, 0xff900f1f,
6576bffe 2582 "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
c507f10b
AV		 2583
2584 /* Vector VORR immediate to vector.
2585 NOTE: MVE_VORR_IMM must appear in the table
2586 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2588 MVE_VORR_IMM,
2589 0xef800050, 0xefb810f0,
2590 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2591
ed63aa17
AV		 2592 /* Vector VQSHL T2 Variant.
2593 NOTE: MVE_VQSHL_T2 must appear in the table before
2594 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2596 MVE_VQSHL_T2,
2597 0xef800750, 0xef801fd1,
6576bffe 2598 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2599
2600 /* Vector VQSHLU T3 Variant
2601 NOTE: MVE_VQSHL_T2 must appear in the table before
2602 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2603
2da2eaf4 2604 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2605 MVE_VQSHLU_T3,
2606 0xff800650, 0xff801fd1,
6576bffe 2607 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2608
2609 /* Vector VRSHR
2610 NOTE: MVE_VRSHR must appear in the table before
2611 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2613 MVE_VRSHR,
2614 0xef800250, 0xef801fd1,
6576bffe 2615 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2616
2617 /* Vector VSHL.
2618 NOTE: MVE_VSHL must appear in the table before
2619 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2620 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2621 MVE_VSHL_T1,
2622 0xef800550, 0xff801fd1,
6576bffe 2623 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2624
2625 /* Vector VSHR
2626 NOTE: MVE_VSHR must appear in the table before
2627 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2629 MVE_VSHR,
2630 0xef800050, 0xef801fd1,
6576bffe 2631 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2632
2633 /* Vector VSLI
2634 NOTE: MVE_VSLI must appear in the table before
2635 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2637 MVE_VSLI,
2638 0xff800550, 0xff801fd1,
6576bffe 2639 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2640
2641 /* Vector VSRI
2642 NOTE: MVE_VSRI must appear in the table before
2643 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2645 MVE_VSRI,
2646 0xff800450, 0xff801fd1,
6576bffe 2647 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2648
c507f10b 2649 /* Vector VMOV immediate to vector,
ce760a76 2650 undefinded for cmode == 1111 */
2da2eaf4 2651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2652 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2653
2654 /* Vector VMOV immediate to vector,
2655 cmode == 1101 */
2da2eaf4 2656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2657 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2658 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2659
2660 /* Vector VMOV immediate to vector. */
2da2eaf4 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2662 MVE_VMOV_IMM_TO_VEC,
2663 0xef800050, 0xefb810d0,
2664 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2665
2666 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2668 MVE_VMOV2_VEC_LANE_TO_GP,
2669 0xec000f00, 0xffb01ff0,
6576bffe 2670 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
c507f10b
AV		 2671
2672 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2674 MVE_VMOV2_VEC_LANE_TO_GP,
2675 0xec000f10, 0xffb01ff0,
6576bffe 2676 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
c507f10b
AV		 2677
2678 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2680 MVE_VMOV2_GP_TO_VEC_LANE,
2681 0xec100f00, 0xffb01ff0,
6576bffe 2682 "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
c507f10b
AV		 2683
2684 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2686 MVE_VMOV2_GP_TO_VEC_LANE,
2687 0xec100f10, 0xffb01ff0,
6576bffe 2688 "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
c507f10b
AV		 2689
2690 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2692 MVE_VMOV_VEC_LANE_TO_GP,
2693 0xee100b10, 0xff100f1f,
6576bffe 2694 "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
c507f10b 2695
ed63aa17
AV		 2696 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2697 to instruction opcode aliasing. */
2da2eaf4 2698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2699 MVE_VSHLL_T1,
2700 0xeea00f40, 0xefa00fd1,
6576bffe 2701 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2702
14925797 2703 /* Vector VMOVL long. */
2da2eaf4 2704 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2705 MVE_VMOVL,
2706 0xeea00f40, 0xefa70fd1,
2707 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2708
2709 /* Vector VMOV and narrow. */
2da2eaf4 2710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2711 MVE_VMOVN,
2712 0xfe310e81, 0xffb30fd1,
2713 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2714
c507f10b 2715 /* Floating point move extract. */
2da2eaf4 2716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2717 MVE_VMOVX,
2718 0xfeb00a40, 0xffbf0fd0,
2719 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2720
f49bb598 2721 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2723 MVE_VMUL_FP_T1,
2724 0xff000d50, 0xffa11f51,
2725 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2726
2727 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2729 MVE_VMUL_FP_T2,
2730 0xee310e60, 0xefb11f70,
2731 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2732
2733 /* Vector VMUL T1 variant. */
2da2eaf4 2734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2735 MVE_VMUL_VEC_T1,
2736 0xef000950, 0xff811f51,
2737 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2738
2739 /* Vector VMUL T2 variant. */
2da2eaf4 2740 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2741 MVE_VMUL_VEC_T2,
2742 0xee011e60, 0xff811f70,
2743 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2744
2745 /* Vector VMULH. */
2da2eaf4 2746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2747 MVE_VMULH,
2748 0xee010e01, 0xef811f51,
2749 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2750
2751 /* Vector VRMULH. */
2da2eaf4 2752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2753 MVE_VRMULH,
2754 0xee011e01, 0xef811f51,
2755 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2756
14925797 2757 /* Vector VMULL integer. */
2da2eaf4 2758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2759 MVE_VMULL_INT,
2760 0xee010e00, 0xef810f51,
2761 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2762
2763 /* Vector VMULL polynomial. */
2da2eaf4 2764 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2765 MVE_VMULL_POLY,
2766 0xee310e00, 0xefb10f51,
2767 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2768
c507f10b 2769 /* Vector VMVN immediate to vector. */
2da2eaf4 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2771 MVE_VMVN_IMM,
2772 0xef800070, 0xefb810f0,
2773 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2774
2775 /* Vector VMVN register. */
2da2eaf4 2776 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2777 MVE_VMVN_REG,
2778 0xffb005c0, 0xffbf1fd1,
2779 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2780
f49bb598 2781 /* Vector VNEG floating point. */
2da2eaf4 2782 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2783 MVE_VNEG_FP,
2784 0xffb107c0, 0xffb31fd1,
2785 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2786
2787 /* Vector VNEG. */
2da2eaf4 2788 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2789 MVE_VNEG_VEC,
2790 0xffb103c0, 0xffb31fd1,
2791 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2792
c507f10b 2793 /* Vector VORN, vector bitwise or not. */
2da2eaf4 2794 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2795 MVE_VORN,
2796 0xef300150, 0xffb11f51,
2797 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2798
2799 /* Vector VORR register. */
2da2eaf4 2800 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2801 MVE_VORR_REG,
2802 0xef200150, 0xffb11f51,
2803 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2804
c4a23bf8
SP		 2805 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2806 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2807 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2808 array. */
2809
2da2eaf4 2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 2811 MVE_VMOV_VEC_TO_VEC,
2812 0xef200150, 0xffb11f51,
2813 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2814
14925797 2815 /* Vector VQDMULL T1 variant. */
2da2eaf4 2816 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2817 MVE_VQDMULL_T1,
2818 0xee300f01, 0xefb10f51,
2819 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2820
14b456f2 2821 /* Vector VPNOT. */
2da2eaf4 2822 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2823 MVE_VPNOT,
2824 0xfe310f4d, 0xffffffff,
2825 "vpnot%v"},
2826
2827 /* Vector VPSEL. */
2da2eaf4 2828 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2829 MVE_VPSEL,
2830 0xfe310f01, 0xffb11f51,
2831 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2832
2833 /* Vector VQABS. */
2da2eaf4 2834 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2835 MVE_VQABS,
2836 0xffb00740, 0xffb31fd1,
2837 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2838
2839 /* Vector VQADD T1 variant. */
2da2eaf4 2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2841 MVE_VQADD_T1,
2842 0xef000050, 0xef811f51,
2843 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2844
2845 /* Vector VQADD T2 variant. */
2da2eaf4 2846 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2847 MVE_VQADD_T2,
2848 0xee000f60, 0xef811f70,
2849 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2850
14925797 2851 /* Vector VQDMULL T2 variant. */
2da2eaf4 2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2853 MVE_VQDMULL_T2,
2854 0xee300f60, 0xefb10f70,
2855 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2856
2857 /* Vector VQMOVN. */
2da2eaf4 2858 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2859 MVE_VQMOVN,
2860 0xee330e01, 0xefb30fd1,
2861 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2862
2863 /* Vector VQMOVUN. */
2da2eaf4 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2865 MVE_VQMOVUN,
2866 0xee310e81, 0xffb30fd1,
2867 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2868
d3b63143 2869 /* Vector VQDMLADH. */
2da2eaf4 2870 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2871 MVE_VQDMLADH,
2872 0xee000e00, 0xff810f51,
2873 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2874
2875 /* Vector VQRDMLADH. */
2da2eaf4 2876 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2877 MVE_VQRDMLADH,
2878 0xee000e01, 0xff810f51,
2879 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2880
2881 /* Vector VQDMLAH. */
2da2eaf4 2882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2883 MVE_VQDMLAH,
23d188c7 2884 0xee000e60, 0xff811f70,
d3b63143
AV		 2885 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2886
2887 /* Vector VQRDMLAH. */
2da2eaf4 2888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2889 MVE_VQRDMLAH,
23d188c7 2890 0xee000e40, 0xff811f70,
d3b63143
AV		 2891 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2892
2893 /* Vector VQDMLASH. */
2da2eaf4 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2895 MVE_VQDMLASH,
23d188c7 2896 0xee001e60, 0xff811f70,
d3b63143
AV		 2897 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2898
2899 /* Vector VQRDMLASH. */
2da2eaf4 2900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 2901 MVE_VQRDMLASH,
23d188c7 2902 0xee001e40, 0xff811f70,
d3b63143
AV		 2903 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2904
2905 /* Vector VQDMLSDH. */
2da2eaf4 2906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2907 MVE_VQDMLSDH,
2908 0xfe000e00, 0xff810f51,
2909 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2910
2911 /* Vector VQRDMLSDH. */
2da2eaf4 2912 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2913 MVE_VQRDMLSDH,
2914 0xfe000e01, 0xff810f51,
2915 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2916
2917 /* Vector VQDMULH T1 variant. */
2da2eaf4 2918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2919 MVE_VQDMULH_T1,
2920 0xef000b40, 0xff811f51,
2921 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2922
2923 /* Vector VQRDMULH T2 variant. */
2da2eaf4 2924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2925 MVE_VQRDMULH_T2,
2926 0xff000b40, 0xff811f51,
2927 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2928
2929 /* Vector VQDMULH T3 variant. */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2931 MVE_VQDMULH_T3,
2932 0xee010e60, 0xff811f70,
2933 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2934
2935 /* Vector VQRDMULH T4 variant. */
2da2eaf4 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2937 MVE_VQRDMULH_T4,
2938 0xfe010e60, 0xff811f70,
2939 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2940
14b456f2 2941 /* Vector VQNEG. */
2da2eaf4 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2943 MVE_VQNEG,
2944 0xffb007c0, 0xffb31fd1,
2945 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2946
ed63aa17 2947 /* Vector VQRSHL T1 variant. */
2da2eaf4 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2949 MVE_VQRSHL_T1,
2950 0xef000550, 0xef811f51,
2951 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2952
2953 /* Vector VQRSHL T2 variant. */
2da2eaf4 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2955 MVE_VQRSHL_T2,
2956 0xee331ee0, 0xefb31ff0,
2957 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2958
2959 /* Vector VQRSHRN. */
2da2eaf4 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2961 MVE_VQRSHRN,
2962 0xee800f41, 0xefa00fd1,
6576bffe 2963 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2964
2965 /* Vector VQRSHRUN. */
2da2eaf4 2966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2967 MVE_VQRSHRUN,
2968 0xfe800fc0, 0xffa00fd1,
6576bffe 2969 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2970
2971 /* Vector VQSHL T1 Variant. */
2da2eaf4 2972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2973 MVE_VQSHL_T1,
2974 0xee311ee0, 0xefb31ff0,
2975 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2976
2977 /* Vector VQSHL T4 Variant. */
2da2eaf4 2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2979 MVE_VQSHL_T4,
2980 0xef000450, 0xef811f51,
2981 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2982
2983 /* Vector VQSHRN. */
2da2eaf4 2984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2985 MVE_VQSHRN,
2986 0xee800f40, 0xefa00fd1,
6576bffe 2987 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2988
2989 /* Vector VQSHRUN. */
2da2eaf4 2990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2991 MVE_VQSHRUN,
2992 0xee800fc0, 0xffa00fd1,
6576bffe 2993 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2994
14b456f2 2995 /* Vector VQSUB T1 Variant. */
2da2eaf4 2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 2997 MVE_VQSUB_T1,
2998 0xef000250, 0xef811f51,
2999 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3000
3001 /* Vector VQSUB T2 Variant. */
2da2eaf4 3002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3003 MVE_VQSUB_T2,
3004 0xee001f60, 0xef811f70,
3005 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3006
3007 /* Vector VREV16. */
2da2eaf4 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3009 MVE_VREV16,
3010 0xffb00140, 0xffb31fd1,
3011 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3012
3013 /* Vector VREV32. */
2da2eaf4 3014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3015 MVE_VREV32,
3016 0xffb000c0, 0xffb31fd1,
3017 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3018
3019 /* Vector VREV64. */
2da2eaf4 3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3021 MVE_VREV64,
3022 0xffb00040, 0xffb31fd1,
3023 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3024
bf0b396d 3025 /* Vector VRINT floating point. */
2da2eaf4 3026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3027 MVE_VRINT_FP,
3028 0xffb20440, 0xffb31c51,
3029 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3030
d3b63143 3031 /* Vector VRMLALDAVH. */
2da2eaf4 3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3033 MVE_VRMLALDAVH,
3034 0xee800f00, 0xef811f51,
3035 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3036
3037 /* Vector VRMLALDAVH. */
2da2eaf4 3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3039 MVE_VRMLALDAVH,
3040 0xee801f00, 0xef811f51,
3041 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3042
ed63aa17 3043 /* Vector VRSHL T1 Variant. */
2da2eaf4 3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3045 MVE_VRSHL_T1,
3046 0xef000540, 0xef811f51,
3047 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3048
3049 /* Vector VRSHL T2 Variant. */
2da2eaf4 3050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3051 MVE_VRSHL_T2,
3052 0xee331e60, 0xefb31ff0,
3053 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3054
3055 /* Vector VRSHRN. */
2da2eaf4 3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3057 MVE_VRSHRN,
3058 0xfe800fc1, 0xffa00fd1,
6576bffe 3059 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3060
66dcaa5d 3061 /* Vector VSBC. */
2da2eaf4 3062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3063 MVE_VSBC,
3064 0xfe300f00, 0xffb10f51,
3065 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3066
ed63aa17 3067 /* Vector VSHL T2 Variant. */
2da2eaf4 3068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3069 MVE_VSHL_T2,
3070 0xee311e60, 0xefb31ff0,
3071 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3072
3073 /* Vector VSHL T3 Variant. */
2da2eaf4 3074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3075 MVE_VSHL_T3,
3076 0xef000440, 0xef811f51,
3077 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3078
3079 /* Vector VSHLC. */
2da2eaf4 3080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3081 MVE_VSHLC,
3082 0xeea00fc0, 0xffa01ff0,
6576bffe 3083 "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
ed63aa17
AV		 3084
3085 /* Vector VSHLL T2 Variant. */
2da2eaf4 3086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3087 MVE_VSHLL_T2,
3088 0xee310e01, 0xefb30fd1,
6576bffe 3089 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
ed63aa17
AV		 3090
3091 /* Vector VSHRN. */
2da2eaf4 3092 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3093 MVE_VSHRN,
3094 0xee800fc1, 0xffa00fd1,
6576bffe 3095 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3096
04d54ace 3097 /* Vector VST2 no writeback. */
2da2eaf4 3098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3099 MVE_VST2,
3100 0xfc801e00, 0xffb01e5f,
3101 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3102
3103 /* Vector VST2 writeback. */
2da2eaf4 3104 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3105 MVE_VST2,
3106 0xfca01e00, 0xffb01e5f,
3107 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3108
3109 /* Vector VST4 no writeback. */
2da2eaf4 3110 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3111 MVE_VST4,
3112 0xfc801e01, 0xffb01e1f,
3113 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3114
3115 /* Vector VST4 writeback. */
2da2eaf4 3116 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3117 MVE_VST4,
3118 0xfca01e01, 0xffb01e1f,
3119 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3120
ef1576a1 3121 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3122 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3123 MVE_VSTRB_SCATTER_T1,
3124 0xec800e00, 0xffb01e50,
3125 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3126
3127 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3128 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3129 MVE_VSTRH_SCATTER_T2,
3130 0xec800e10, 0xffb01e50,
3131 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3132
3133 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3134 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3135 MVE_VSTRW_SCATTER_T3,
3136 0xec800e40, 0xffb01e50,
3137 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3138
3139 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3140 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3141 MVE_VSTRD_SCATTER_T4,
3142 0xec800fd0, 0xffb01fd0,
3143 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3144
3145 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3146 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3147 MVE_VSTRW_SCATTER_T5,
3148 0xfd001e00, 0xff111f00,
6576bffe 3149 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 3150
3151 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3153 MVE_VSTRD_SCATTER_T6,
3154 0xfd001f00, 0xff111f00,
6576bffe 3155 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 3156
aef6d006 3157 /* Vector VSTRB. */
2da2eaf4 3158 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3159 MVE_VSTRB_T1,
3160 0xec000e00, 0xfe581e00,
3161 "vstrb%v.%7-8s\t%13-15Q, %d"},
3162
3163 /* Vector VSTRH. */
2da2eaf4 3164 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3165 MVE_VSTRH_T2,
3166 0xec080e00, 0xfe581e00,
3167 "vstrh%v.%7-8s\t%13-15Q, %d"},
3168
3169 /* Vector VSTRB variant T5. */
2da2eaf4 3170 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3171 MVE_VSTRB_T5,
3172 0xec001e00, 0xfe101f80,
3173 "vstrb%v.8\t%13-15,22Q, %d"},
3174
3175 /* Vector VSTRH variant T6. */
2da2eaf4 3176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3177 MVE_VSTRH_T6,
3178 0xec001e80, 0xfe101f80,
3179 "vstrh%v.16\t%13-15,22Q, %d"},
3180
3181 /* Vector VSTRW variant T7. */
2da2eaf4 3182 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3183 MVE_VSTRW_T7,
3184 0xec001f00, 0xfe101f80,
3185 "vstrw%v.32\t%13-15,22Q, %d"},
3186
66dcaa5d 3187 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3188 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3189 MVE_VSUB_FP_T1,
3190 0xef200d40, 0xffa11f51,
3191 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3192
3193 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3194 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3195 MVE_VSUB_FP_T2,
3196 0xee301f40, 0xefb11f70,
3197 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3198
3199 /* Vector VSUB T1 variant. */
2da2eaf4 3200 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3201 MVE_VSUB_VEC_T1,
3202 0xff000840, 0xff811f51,
3203 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3204
3205 /* Vector VSUB T2 variant. */
2da2eaf4 3206 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3207 MVE_VSUB_VEC_T2,
3208 0xee011f40, 0xff811f70,
3209 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3210
2da2eaf4 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3212 MVE_ASRLI,
3213 0xea50012f, 0xfff1813f,
3214 "asrl%c\t%17-19l, %9-11h, %j"},
3215
2da2eaf4 3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3217 MVE_ASRL,
3218 0xea50012d, 0xfff101ff,
3219 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3220
2da2eaf4 3221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3222 MVE_LSLLI,
3223 0xea50010f, 0xfff1813f,
3224 "lsll%c\t%17-19l, %9-11h, %j"},
3225
2da2eaf4 3226 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3227 MVE_LSLL,
3228 0xea50010d, 0xfff101ff,
3229 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3230
2da2eaf4 3231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3232 MVE_LSRL,
3233 0xea50011f, 0xfff1813f,
3234 "lsrl%c\t%17-19l, %9-11h, %j"},
3235
2da2eaf4 3236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3237 MVE_SQRSHRL,
08132bdd
SP		 3238 0xea51012d, 0xfff1017f,
3239 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3240
2da2eaf4 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3242 MVE_SQRSHR,
3243 0xea500f2d, 0xfff00fff,
3244 "sqrshr%c\t%16-19S, %12-15S"},
3245
2da2eaf4 3246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3247 MVE_SQSHLL,
3248 0xea51013f, 0xfff1813f,
3249 "sqshll%c\t%17-19l, %9-11h, %j"},
3250
2da2eaf4 3251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3252 MVE_SQSHL,
3253 0xea500f3f, 0xfff08f3f,
3254 "sqshl%c\t%16-19S, %j"},
3255
2da2eaf4 3256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3257 MVE_SRSHRL,
3258 0xea51012f, 0xfff1813f,
3259 "srshrl%c\t%17-19l, %9-11h, %j"},
3260
2da2eaf4 3261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3262 MVE_SRSHR,
3263 0xea500f2f, 0xfff08f3f,
3264 "srshr%c\t%16-19S, %j"},
3265
2da2eaf4 3266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3267 MVE_UQRSHLL,
08132bdd
SP		 3268 0xea51010d, 0xfff1017f,
3269 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3270
2da2eaf4 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3272 MVE_UQRSHL,
3273 0xea500f0d, 0xfff00fff,
3274 "uqrshl%c\t%16-19S, %12-15S"},
3275
2da2eaf4 3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3277 MVE_UQSHLL,
3278 0xea51010f, 0xfff1813f,
3279 "uqshll%c\t%17-19l, %9-11h, %j"},
3280
2da2eaf4 3281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3282 MVE_UQSHL,
3283 0xea500f0f, 0xfff08f3f,
3284 "uqshl%c\t%16-19S, %j"},
3285
2da2eaf4 3286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3287 MVE_URSHRL,
3288 0xea51011f, 0xfff1813f,
3289 "urshrl%c\t%17-19l, %9-11h, %j"},
3290
2da2eaf4 3291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3292 MVE_URSHR,
3293 0xea500f1f, 0xfff08f3f,
3294 "urshr%c\t%16-19S, %j"},
3295
e39c1607
SD		 3296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3297 MVE_CSINC,
3298 0xea509000, 0xfff0f000,
3299 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3300
3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3302 MVE_CSINV,
3303 0xea50a000, 0xfff0f000,
3304 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3305
3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3307 MVE_CSET,
3308 0xea5f900f, 0xfffff00f,
3309 "cset\t%8-11S, %4-7C"},
3310
3311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3312 MVE_CSETM,
3313 0xea5fa00f, 0xfffff00f,
3314 "csetm\t%8-11S, %4-7C"},
3315
3316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3317 MVE_CSEL,
3318 0xea508000, 0xfff0f000,
3319 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3320
3321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3322 MVE_CSNEG,
3323 0xea50b000, 0xfff0f000,
3324 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3325
3326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3327 MVE_CINC,
3328 0xea509000, 0xfff0f000,
3329 "cinc\t%8-11S, %16-19Z, %4-7C"},
3330
3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3332 MVE_CINV,
3333 0xea50a000, 0xfff0f000,
3334 "cinv\t%8-11S, %16-19Z, %4-7C"},
3335
3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3337 MVE_CNEG,
3338 0xea50b000, 0xfff0f000,
3339 "cneg\t%8-11S, %16-19Z, %4-7C"},
3340
143275ea
AV		 3341 {ARM_FEATURE_CORE_LOW (0),
3342 MVE_NONE,
3343 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3344};
3345
8f06b2d8
PB		 3346/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3347 ordered: they must be searched linearly from the top to obtain a correct
3348 match. */
3349
3350/* print_insn_arm recognizes the following format control codes:
3351
3352 %% %
3353
3354 %a print address for ldr/str instruction
3355 %s print address for ldr/str halfword/signextend instruction
c1e26897 3356 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3357 %b print branch destination
3358 %c print condition code (always bits 28-31)
3359 %m print register mask for ldm/stm instruction
3360 %o print operand2 (immediate or register + shift)
3361 %p print 'p' iff bits 12-15 are 15
cfbbd403 3362 %O print 'OBSOLETE' iff bits 12-15 are 15
8f06b2d8
PB		 3363 %t print 't' iff bit 21 set and bit 24 clear
3364 %B print arm BLX(1) destination
3365 %C print the PSR sub type.
62b3e311
PB		 3366 %U print barrier type.
3367 %P print address for pli instruction.
2c9d089c 3368 %T print 'from Armv4T onwards'
8f06b2d8
PB		 3369
3370 %<bitfield>r print as an ARM register
9eb6c0f1 3371 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3372 %<bitfield>R as %r but r15 is UNPREDICTABLE
3373 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3374 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3375 %<bitfield>d print the bitfield in decimal
43e65147 3376 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3377 %<bitfield>x print the bitfield in hex
3378 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3379
16980d0b
JB		 3380 %<bitfield>'c print specified char iff bitfield is all ones
3381 %<bitfield>`c print specified char iff bitfield is all zeroes
3382 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3383
8f06b2d8
PB		 3384 %e print arm SMI operand (bits 0..7,8..19).
3385 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3386 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3387 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3388
8f06b2d8
PB		 3389static const struct opcode32 arm_opcodes[] =
3390{
3391 /* ARM instructions. */
823d2571 3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 3393 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
823d2571 3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3395 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
823d2571 3396
2c9d089c
AV		 3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4),
3398 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r%T"},
823d2571
TG		 3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3400 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3402 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3404 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3406 0x00800090, 0x0fa000f0,
3407 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3409 0x00a00090, 0x0fa000f0,
3410 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3411
105bde57 3412 /* V8.2 RAS extension instructions. */
4d1464f2 3413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3414 0xe320f010, 0xffffffff, "esb"},
3415
26417f19
AC		 3416 /* V8-R instructions. */
3417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3418 0xf57ff04c, 0xffffffff, "dfb"},
3419
53c4b28b 3420 /* V8 instructions. */
823d2571
TG		 3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3422 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3423 /* Defined in V8 but is in NOP space so available to all arch. */
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3425 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
4ed7ed8d 3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3427 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3428 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3429 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3431 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3433 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3434 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3435 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3436 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3437 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3438 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3439 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3440 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3441 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3442 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3443 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3444 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3445 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3446 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3447 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3448 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3449 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3450 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3451 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3452 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3453 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3454 /* CRC32 instructions. */
8b301fbb 3455 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3456 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3458 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3460 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3462 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3464 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3466 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3467
ddfded2f
MW		 3468 /* Privileged Access Never extension instructions. */
3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
6576bffe 3470 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
ddfded2f 3471
90ec0d68 3472 /* Virtualization Extension instructions. */
823d2571
TG		 3473 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3475
eea54501 3476 /* Integer Divide Extension instructions. */
823d2571
TG		 3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3478 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3480 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3481
60e5ef9f 3482 /* MP Extension instructions. */
823d2571 3483 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3484
c597cc3d
SD		 3485 /* Speculation Barriers. */
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3489
62b3e311 3490 /* V7 instructions. */
823d2571 3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
6576bffe 3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a 3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 3499 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
62b3e311 3500
c19d1205 3501 /* ARM V6T2 instructions. */
823d2571
TG		 3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3505 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3507 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3509 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3510
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3512 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3514 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3515
ff8646ee 3516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3517 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3519 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 3523 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
885fc257 3524
f4c65163 3525 /* ARM Security extension instructions. */
823d2571
TG		 3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3527 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3528
8f06b2d8 3529 /* ARM V6K instructions. */
823d2571
TG		 3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3531 0xf57ff01f, 0xffffffff, "clrex"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3533 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3535 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3537 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3539 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3541 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3543 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3544
7fadb25d
SD		 3545 /* ARMv8.5-A instructions. */
3546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3547
8f06b2d8 3548 /* ARM V6K NOP hints. */
823d2571
TG		 3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3550 0x0320f001, 0x0fffffff, "yield%c"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3552 0x0320f002, 0x0fffffff, "wfe%c"},
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3554 0x0320f003, 0x0fffffff, "wfi%c"},
3555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3556 0x0320f004, 0x0fffffff, "sev%c"},
3557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
6576bffe 3558 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
c19d1205 3559
fe56b6ce 3560 /* ARM V6 instructions. */
823d2571 3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3562 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
823d2571 3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3564 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3566 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
823d2571 3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3568 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3570 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
823d2571
TG		 3571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3572 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3574 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3576 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
823d2571 3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3578 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3580 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
823d2571
TG		 3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3582 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3584 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3586 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3588 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3590 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3592 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3594 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3596 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3598 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3600 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3602 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3604 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3606 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3608 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3610 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3612 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3614 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3616 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3618 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3620 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3622 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3624 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3626 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3628 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3630 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3632 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3634 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3636 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3638 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3640 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3642 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3644 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3646 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3648 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3650 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3652 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3654 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3656 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3658 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3660 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3662 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3664 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3666 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3668 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3670 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3672 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3674 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3676 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3678 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3680 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3682 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3684 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3686 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3688 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3690 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3692 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3694 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3696 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3698 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3700 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3702 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3704 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3706 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3708 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3710 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3712 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3714 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3716 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3718 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3720 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3722 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3724 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3726 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3728 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3730 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3732 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3736 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3738 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3740 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3744 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3746 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3748 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
823d2571
TG		 3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3752 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3754 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3756 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3760 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
823d2571
TG		 3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3780 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3782 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
823d2571 3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3784 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3786 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3788 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
823d2571
TG		 3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3798 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
823d2571 3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3800 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3802 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3804 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
c19d1205 3805
8f06b2d8 3806 /* V5J instruction. */
823d2571
TG		 3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3808 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3809
8f06b2d8 3810 /* V5 Instructions. */
823d2571
TG		 3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3812 0xe1200070, 0xfff000f0,
6576bffe 3813 "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
823d2571
TG		 3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3815 0xfa000000, 0xfe000000, "blx\t%B"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3817 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3819 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3820
3821 /* V5E "El Segundo" Instructions. */
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3823 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3825 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3827 0xf450f000, 0xfc70f000, "pld\t%a"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3829 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3831 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3833 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3835 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3836
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3838 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3840 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3841
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3843 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3845 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3847 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3849 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3850
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3852 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3854 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3856 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3858 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3859
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3861 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3863 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3864
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3866 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3868 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3870 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3872 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3873
8f06b2d8 3874 /* ARM Instructions. */
823d2571 3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 3876 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
823d2571
TG		 3877
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3879 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3881 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3883 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3885 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3887 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3889 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3890
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3892 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3894 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3896 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3898 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3899
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3901 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3903 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3905 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3907 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3908
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3910 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3912 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3914 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3915
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3917 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3919 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3921 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3922
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3924 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3926 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3928 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3929
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3931 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3933 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3935 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3936
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3938 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3940 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3942 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3943
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3947 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3949 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3950
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3952 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3954 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3956 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3957
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3959 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3961 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3963 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3964
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3966 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3968 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3970 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3971
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3973 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o%O"},
823d2571 3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3975 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o%O"},
823d2571 3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3977 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o%O"},
823d2571
TG		 3978
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3980 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o%O"},
823d2571 3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3982 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o%O"},
823d2571 3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3984 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o%O"},
823d2571
TG		 3985
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3987 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o%O"},
823d2571 3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3989 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o%O"},
823d2571 3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3991 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o%O"},
823d2571
TG		 3992
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3994 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o%O"},
823d2571 3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3996 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o%O"},
823d2571 3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
cfbbd403 3998 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o%O"},
823d2571
TG		 3999
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4005 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4006
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4008 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4014 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4016 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4018 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4020 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4021
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4023 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4025 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4027 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4028
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4030 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4032 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4034 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4035
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4037 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 4039 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
823d2571
TG		 4040
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4042 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4043
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4048
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4058 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4062 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082 0x092d0000, 0x0fff0000, "push%c\t%m"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4086 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4087
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4093 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4095 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4097 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4099 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4109 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4111 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4119 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4121 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4125 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4126
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4131
4132 /* The rest. */
4ab90a7a 4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 4134 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4137 {ARM_FEATURE_CORE_LOW (0),
4138 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4139};
4140
4141/* print_insn_thumb16 recognizes the following format control codes:
4142
4143 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4144 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4145 %<bitfield>I print bitfield as a signed decimal
4146 (top bit of range being the sign bit)
4147 %N print Thumb register mask (with LR)
4148 %O print Thumb register mask (with PC)
4149 %M print Thumb register mask
4150 %b print CZB's 6-bit unsigned branch destination
4151 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4152 %c print the condition code
4153 %C print the condition code, or "s" if not conditional
4154 %x print warning if conditional an not at end of IT block"
8cb6e175 4155 %X print "\t@ unpredictable <IT:code>" if conditional
c22aaad1 4156 %I print IT instruction suffix and operands
4547cb56 4157 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4158 %<bitfield>r print bitfield as an ARM register
4159 %<bitfield>d print bitfield as a decimal
4160 %<bitfield>H print (bitfield * 2) as a decimal
4161 %<bitfield>W print (bitfield * 4) as a decimal
4162 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4163 %<bitfield>B print Thumb branch destination (signed displacement)
4164 %<bitfield>c print bitfield as a condition code
4165 %<bitnum>'c print specified char iff bit is one
4166 %<bitnum>?ab print a if bit is one else print b. */
4167
4168static const struct opcode16 thumb_opcodes[] =
4169{
4170 /* Thumb instructions. */
4171
16a1fa25
TP		 4172 /* ARMv8-M Security Extensions instructions. */
4173 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4175
53c4b28b 4176 /* ARM V8 instructions. */
823d2571
TG		 4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
6576bffe 4179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
53c4b28b 4180
8f06b2d8 4181 /* ARM V6K no-argument instructions. */
823d2571
TG		 4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4188
4189 /* ARM V6T2 instructions. */
ff8646ee
TP		 4190 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4191 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4193 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4195
4196 /* ARM V6. */
6576bffe
AB		 4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
823d2571
TG		 4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
6576bffe 4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
823d2571
TG		 4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4208
4209 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4211 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4212 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4214 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4215 /* ARM V4T ISA (Thumb v1). */
823d2571 4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
8cb6e175 4217 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
8f06b2d8 4218 /* Format 4. */
823d2571
TG		 4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4235 /* format 13 */
6576bffe
AB		 4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
8f06b2d8 4238 /* format 5 */
823d2571
TG		 4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4243 /* format 14 */
823d2571
TG		 4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4246 /* format 2 */
823d2571
TG		 4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4248 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4250 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4252 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
823d2571 4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4254 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
8f06b2d8 4255 /* format 8 */
823d2571
TG		 4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4257 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4259 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4261 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4262 /* format 7 */
823d2571
TG		 4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4264 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4266 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4267 /* format 1 */
823d2571
TG		 4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4270 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
823d2571
TG		 4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4273 /* format 3 */
6576bffe
AB		 4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
8f06b2d8 4278 /* format 6 */
823d2571
TG		 4279 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4281 0x4800, 0xF800,
6576bffe 4282 "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
8f06b2d8 4283 /* format 9 */
823d2571 4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4285 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4287 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4289 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
823d2571 4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4291 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
8f06b2d8 4292 /* format 10 */
823d2571 4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4294 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
823d2571 4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4296 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
8f06b2d8 4297 /* format 11 */
823d2571 4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4299 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
823d2571 4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4301 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
8f06b2d8 4302 /* format 12 */
823d2571 4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4304 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
823d2571 4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4306 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
8f06b2d8 4307 /* format 15 */
823d2571
TG		 4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4310 /* format 17 */
823d2571 4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4312 /* format 16 */
6576bffe 4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
823d2571
TG		 4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4316 /* format 18 */
823d2571 4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4318
4319 /* The E800 .. FFFF range is unconditionally redirected to the
4320 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4321 are processed via that table. Thus, we can never encounter a
4322 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4324 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4325};
4326
4327/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4328 We adopt the convention that hw1 is the high 16 bits of .value and
4329 .mask, hw2 the low 16 bits.
4330
4331 print_insn_thumb32 recognizes the following format control codes:
4332
4333 %% %
4334
4335 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4336 %M print a modified 12-bit immediate (same location)
4337 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4338 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4339 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4340 %S print a possibly-shifted Rm
4341
32a94698 4342 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4343 %a print the address of a plain load/store
4344 %w print the width and signedness of a core load/store
4345 %m print register mask for ldm/stm
4b5a202f 4346 %n print register mask for clrm
8f06b2d8
PB		 4347
4348 %E print the lsb and width fields of a bfc/bfi instruction
4349 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4350 %G print a fallback offset for Branch Future instructions
e5d6e09e 4351 %W print an offset for BF instruction
1caf72a5 4352 %Y print an offset for BFL instruction
1889da70 4353 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4354 %Q print an offset for Low Overhead Loop instructions
4355 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4356 %b print a conditional branch offset
4357 %B print an unconditional branch offset
4358 %s print the shift field of an SSAT instruction
4359 %R print the rotation field of an SXT instruction
62b3e311
PB		 4360 %U print barrier type.
4361 %P print address for pli instruction.
c22aaad1
PB		 4362 %c print the condition code
4363 %x print warning if conditional an not at end of IT block"
8cb6e175 4364 %X print "\t@ unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4365
4366 %<bitfield>d print bitfield in decimal
f0fba320 4367 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4368 %<bitfield>W print bitfield*4 in decimal
4369 %<bitfield>r print bitfield as an ARM register
dd5181d5 4370 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4371 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4372 %<bitfield>c print bitfield as a condition code
4373
16980d0b
JB		 4374 %<bitfield>'c print specified char iff bitfield is all ones
4375 %<bitfield>`c print specified char iff bitfield is all zeroes
4376 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4377
4378 With one exception at the bottom (done because BL and BLX(1) need
4379 to come dead last), this table was machine-sorted first in
4380 decreasing order of number of bits set in the mask, then in
4381 increasing numeric order of mask, then in increasing numeric order
4382 of opcode. This order is not the clearest for a human reader, but
4383 is guaranteed never to catch a special-case bit pattern with a more
4384 general mask, which is important, because this instruction encoding
4385 makes heavy use of special-case bit patterns. */
4386static const struct opcode32 thumb32_opcodes[] =
4387{
3751264c
AC		 4388 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4389 Identification Extension. */
e43ca2cb 4390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4391 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
be05908c
AC		 4392 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4393 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
3751264c
AC		 4394 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4395 0xf3af800f, 0xffffffff, "bti"},
e07352fa
AC		 4396 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4397 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
ce537a7d 4398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4399 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
f1e1d7f3 4400 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4401 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
5c43020d
AC		 4402 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4403 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
3751264c 4404
4b5a202f
AV		 4405 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4406 instructions. */
60f993ce 4407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4408 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4410 0xf02fc001, 0xfffff001, "le\t%P"},
4411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4412 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
d052b9b7 4413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4414 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
d052b9b7 4415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4416 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4418 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4420 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
d052b9b7 4421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4422 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
60f993ce 4423
4389b29a
AV		 4424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4425 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4427 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4428 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4429 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4431 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d 4432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4433 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4389b29a 4434
4b5a202f
AV		 4435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4436 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4437
16a1fa25
TP		 4438 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4441 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4442 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4443 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4445 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4447 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4448
105bde57 4449 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4451 0xf3af8010, 0xffffffff, "esb"},
4452
53c4b28b 4453 /* V8 instructions. */
823d2571
TG		 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4455 0xf3af8005, 0xffffffff, "sevl%c.w"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4457 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4459 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4461 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4463 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4465 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4467 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4469 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4471 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4473 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4475 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4477 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4479 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4481 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4483 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4485 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4486
26417f19
AC		 4487 /* V8-R instructions. */
4488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4489 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4490
dd5181d5 4491 /* CRC32 instructions. */
8b301fbb 4492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4493 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4495 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4497 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4499 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4501 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4503 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4504
c597cc3d
SD		 4505 /* Speculation Barriers. */
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4509
62b3e311 4510 /* V7 instructions. */
823d2571 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
6576bffe 4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4519 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4521 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4522
90ec0d68 4523 /* Virtualization Extension instructions. */
823d2571 4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4525 /* We skip ERET as that is SUBS pc, lr, #0. */
4526
60e5ef9f 4527 /* MP Extension instructions. */
823d2571 4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4529
f4c65163 4530 /* Security extension instructions. */
823d2571 4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4532
7fadb25d
SD		 4533 /* ARMv8.5-A instructions. */
4534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4535
8f06b2d8 4536 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4543 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
823d2571
TG		 4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4545
ff8646ee 4546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4547 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4549 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571 4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4551 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571
TG		 4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4553 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4555 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4557 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4561 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
823d2571
TG		 4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4563 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4565 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
823d2571 4566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4567 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4569 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4571 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
823d2571
TG		 4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4573 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4575 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4577 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4579 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4581 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571
TG		 4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4583 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4585 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4587 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4589 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4591 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4593 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4595 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4597 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4599 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4601 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4603 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4605 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4607 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4609 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4611 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4613 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4615 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4617 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4619 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4621 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4623 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4625 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4627 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4629 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4631 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4633 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4635 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4637 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4639 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4641 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4643 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4645 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4647 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4649 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4651 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4653 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4657 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4659 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4701 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4703 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4705 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
823d2571 4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4707 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
823d2571
TG		 4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 4771 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xf810f000, 0xff70f000, "pld%c\t%a"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xfb100000, 0xfff000c0,
4804 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xfbc00080, 0xfff000c0,
4807 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4813 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
823d2571 4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4815 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
823d2571
TG		 4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4818 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4819 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4822 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4823 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4844 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 4845 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xe9400000, 0xff500000,
6576bffe 4880 "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xe9500000, 0xff500000,
6576bffe 4883 "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xe8600000, 0xff700000,
6576bffe 4886 "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xe8700000, 0xff700000,
6576bffe 4889 "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4894
4895 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4904
8f06b2d8 4905 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4907 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4909 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4910
4911 /* Fallback. */
823d2571
TG		 4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4913 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4914 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4915};
ff4a8d2b 4916
8f06b2d8
PB		 4917static const char *const arm_conditional[] =
4918{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4919 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8 4920
8f06b2d8
PB		 4921static const char *const arm_shift[] =
4922{"lsl", "lsr", "asr", "ror"};
4923
4924typedef struct
4925{
4926 const char *name;
4927 const char *description;
4928 const char *reg_names[16];
4929}
4930arm_regname;
4931
4932static const arm_regname regnames[] =
4933{
65b48a81 4934 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4935 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4936 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4937 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4938 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4939 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4940 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4941 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4942 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4943 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4944 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4945 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 4946 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 4947 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
4948 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 4949};
4950
4951static const char *const iwmmxt_wwnames[] =
4952{"b", "h", "w", "d"};
4953
4954static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4955{"b", "bus", "bc", "bss",
4956 "h", "hus", "hc", "hss",
4957 "w", "wus", "wc", "wss",
4958 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4959};
4960
4961static const char *const iwmmxt_regnames[] =
4962{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4963 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4964};
4965
4966static const char *const iwmmxt_cregnames[] =
4967{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4968 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4969};
4970
143275ea
AV		 4971static const char *const vec_condnames[] =
4972{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4973};
4974
4975static const char *const mve_predicatenames[] =
4976{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4977 "eee", "ee", "eet", "e", "ett", "et", "ete"
4978};
4979
4980/* Names for 2-bit size field for mve vector isntructions. */
4981static const char *const mve_vec_sizename[] =
4982 { "8", "16", "32", "64"};
4983
4984/* Indicates whether we are processing a then predicate,
4985 else predicate or none at all. */
4986enum vpt_pred_state
4987{
4988 PRED_NONE,
4989 PRED_THEN,
4990 PRED_ELSE
4991};
4992
4993/* Information used to process a vpt block and subsequent instructions. */
4994struct vpt_block
4995{
4996 /* Are we in a vpt block. */
78933a4a 4997 bool in_vpt_block;
143275ea
AV		 4998
4999 /* Next predicate state if in vpt block. */
5000 enum vpt_pred_state next_pred_state;
5001
5002 /* Mask from vpt/vpst instruction. */
5003 long predicate_mask;
5004
5005 /* Instruction number in vpt block. */
5006 long current_insn_num;
5007
5008 /* Number of instructions in vpt block.. */
5009 long num_pred_insn;
5010};
5011
5012static struct vpt_block vpt_block_state =
5013{
78933a4a 5014 false,
143275ea
AV		 5015 PRED_NONE,
5016 0,
5017 0,
5018 0
5019};
5020
8f06b2d8
PB		 5021/* Default to GCC register name set. */
5022static unsigned int regname_selected = 1;
5023
65b48a81 5024#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5025#define arm_regnames regnames[regname_selected].reg_names
5026
78933a4a 5027static bool force_thumb = false;
4934a27c 5028static uint16_t cde_coprocs = 0;
8f06b2d8 5029
c22aaad1
PB		 5030/* Current IT instruction state. This contains the same state as the IT
5031 bits in the CPSR. */
5032static unsigned int ifthen_state;
5033/* IT state for the next instruction. */
5034static unsigned int ifthen_next_state;
5035/* The address of the insn for which the IT state is valid. */
5036static bfd_vma ifthen_address;
5037#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5038/* Indicates that the current Conditional state is unconditional or outside
5039 an IT block. */
5040#define COND_UNCOND 16
c22aaad1 5041
8f06b2d8
PB		 5042\f
5043/* Functions. */
143275ea
AV		 5044/* Extract the predicate mask for a VPT or VPST instruction.
5045 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5046
5047static long
5048mve_extract_pred_mask (long given)
5049{
5050 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5051}
5052
5053/* Return the number of instructions in a MVE predicate block. */
5054static long
5055num_instructions_vpt_block (long given)
5056{
5057 long mask = mve_extract_pred_mask (given);
5058 if (mask == 0)
5059 return 0;
5060
5061 if (mask == 8)
5062 return 1;
5063
5064 if ((mask & 7) == 4)
5065 return 2;
5066
5067 if ((mask & 3) == 2)
5068 return 3;
5069
5070 if ((mask & 1) == 1)
5071 return 4;
5072
5073 return 0;
5074}
5075
5076static void
5077mark_outside_vpt_block (void)
5078{
78933a4a 5079 vpt_block_state.in_vpt_block = false;
143275ea
AV		 5080 vpt_block_state.next_pred_state = PRED_NONE;
5081 vpt_block_state.predicate_mask = 0;
5082 vpt_block_state.current_insn_num = 0;
5083 vpt_block_state.num_pred_insn = 0;
5084}
5085
5086static void
5087mark_inside_vpt_block (long given)
5088{
78933a4a 5089 vpt_block_state.in_vpt_block = true;
143275ea
AV		 5090 vpt_block_state.next_pred_state = PRED_THEN;
5091 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5092 vpt_block_state.current_insn_num = 0;
5093 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5094 assert (vpt_block_state.num_pred_insn >= 1);
5095}
5096
5097static enum vpt_pred_state
5098invert_next_predicate_state (enum vpt_pred_state astate)
5099{
5100 if (astate == PRED_THEN)
5101 return PRED_ELSE;
5102 else if (astate == PRED_ELSE)
5103 return PRED_THEN;
5104 else
5105 return PRED_NONE;
5106}
5107
5108static enum vpt_pred_state
5109update_next_predicate_state (void)
5110{
5111 long pred_mask = vpt_block_state.predicate_mask;
5112 long mask_for_insn = 0;
5113
5114 switch (vpt_block_state.current_insn_num)
5115 {
5116 case 1:
5117 mask_for_insn = 8;
5118 break;
5119
5120 case 2:
5121 mask_for_insn = 4;
5122 break;
5123
5124 case 3:
5125 mask_for_insn = 2;
5126 break;
5127
5128 case 4:
5129 return PRED_NONE;
5130 }
5131
5132 if (pred_mask & mask_for_insn)
5133 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5134 else
5135 return vpt_block_state.next_pred_state;
5136}
5137
5138static void
5139update_vpt_block_state (void)
5140{
5141 vpt_block_state.current_insn_num++;
5142 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5143 {
5144 /* No more instructions to process in vpt block. */
5145 mark_outside_vpt_block ();
5146 return;
5147 }
5148
5149 vpt_block_state.next_pred_state = update_next_predicate_state ();
5150}
8f06b2d8 5151
16980d0b
JB		 5152/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5153 Returns pointer to following character of the format string and
5154 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5155 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5156
5157static const char *
fe56b6ce
NC		 5158arm_decode_bitfield (const char *ptr,
5159 unsigned long insn,
5160 unsigned long *valuep,
5161 int *widthp)
16980d0b
JB		 5162{
5163 unsigned long value = 0;
5164 int width = 0;
43e65147
L		 5165
5166 do
16980d0b
JB		 5167 {
5168 int start, end;
5169 int bits;
5170
5171 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5172 start = start * 10 + *ptr - '0';
5173 if (*ptr == '-')
5174 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5175 end = end * 10 + *ptr - '0';
5176 else
5177 end = start;
5178 bits = end - start;
5179 if (bits < 0)
5180 abort ();
5181 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5182 width += bits + 1;
5183 }
5184 while (*ptr++ == ',');
5185 *valuep = value;
5186 if (widthp)
5187 *widthp = width;
5188 return ptr - 1;
5189}
5190
8f06b2d8 5191static void
6576bffe 5192arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
78933a4a 5193 bool print_shift)
8f06b2d8 5194{
6576bffe 5195 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
8f06b2d8
PB		 5196
5197 if ((given & 0xff0) != 0)
5198 {
5199 if ((given & 0x10) == 0)
5200 {
5201 int amount = (given & 0xf80) >> 7;
5202 int shift = (given & 0x60) >> 5;
5203
5204 if (amount == 0)
5205 {
5206 if (shift == 3)
5207 {
6576bffe
AB		 5208 func (stream, dis_style_text, ", ");
5209 func (stream, dis_style_sub_mnemonic, "rrx");
8f06b2d8
PB		 5210 return;
5211 }
5212
5213 amount = 32;
5214 }
5215
37b37b2d 5216 if (print_shift)
6576bffe
AB		 5217 {
5218 func (stream, dis_style_text, ", ");
5219 func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5220 func (stream, dis_style_immediate, "#%d", amount);
5221 }
37b37b2d 5222 else
6576bffe
AB		 5223 {
5224 func (stream, dis_style_text, ", ");
5225 func (stream, dis_style_immediate, "#%d", amount);
5226 }
8f06b2d8 5227 }
74bdfecf 5228 else if ((given & 0x80) == 0x80)
6576bffe
AB		 5229 func (stream, dis_style_comment_start,
5230 "\t@ <illegal shifter operand>");
37b37b2d 5231 else if (print_shift)
6576bffe
AB		 5232 {
5233 func (stream, dis_style_text, ", ");
5234 func (stream, dis_style_sub_mnemonic, "%s ",
5235 arm_shift[(given & 0x60) >> 5]);
5236 func (stream, dis_style_register, "%s",
5237 arm_regnames[(given & 0xf00) >> 8]);
5238 }
37b37b2d 5239 else
6576bffe
AB		 5240 {
5241 func (stream, dis_style_text, ", ");
5242 func (stream, dis_style_register, "%s",
5243 arm_regnames[(given & 0xf00) >> 8]);
5244 }
8f06b2d8
PB		 5245 }
5246}
5247
73cd51e5
AV		 5248/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5249
78933a4a 5250static bool
73cd51e5
AV		 5251is_mve_okay_in_it (enum mve_instructions matched_insn)
5252{
c507f10b
AV		 5253 switch (matched_insn)
5254 {
5255 case MVE_VMOV_GP_TO_VEC_LANE:
5256 case MVE_VMOV2_VEC_LANE_TO_GP:
5257 case MVE_VMOV2_GP_TO_VEC_LANE:
5258 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5259 case MVE_LSLL:
5260 case MVE_LSLLI:
5261 case MVE_LSRL:
5262 case MVE_ASRL:
5263 case MVE_ASRLI:
5264 case MVE_SQRSHRL:
5265 case MVE_SQRSHR:
5266 case MVE_UQRSHL:
5267 case MVE_UQRSHLL:
5268 case MVE_UQSHL:
5269 case MVE_UQSHLL:
5270 case MVE_URSHRL:
5271 case MVE_URSHR:
5272 case MVE_SRSHRL:
5273 case MVE_SRSHR:
5274 case MVE_SQSHLL:
5275 case MVE_SQSHL:
78933a4a 5276 return true;
c507f10b 5277 default:
78933a4a 5278 return false;
c507f10b 5279 }
73cd51e5
AV		 5280}
5281
78933a4a 5282static bool
1fb5ccd6 5283is_v81m_architecture (struct disassemble_info *info)
73cd51e5
AV		 5284{
5285 struct arm_private_data *private_data = info->private_data;
5286 arm_feature_set allowed_arches = private_data->features;
5287
5288 arm_feature_set arm_ext_v8_1m_main
5289 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5290
5291 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5292 && !ARM_CPU_IS_ANY (allowed_arches))
78933a4a 5293 return true;
73cd51e5 5294 else
78933a4a 5295 return false;
73cd51e5
AV		 5296}
5297
78933a4a 5298static bool
143275ea
AV		 5299is_vpt_instruction (long given)
5300{
5301
5302 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5303 if ((given & 0x0040e000) == 0)
78933a4a 5304 return false;
143275ea
AV		 5305
5306 /* VPT floating point T1 variant. */
5307 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5308 /* VPT floating point T2 variant. */
5309 || ((given & 0xefb10f50) == 0xee310f40)
5310 /* VPT vector T1 variant. */
5311 || ((given & 0xff811f51) == 0xfe010f00)
5312 /* VPT vector T2 variant. */
5313 || ((given & 0xff811f51) == 0xfe010f01
5314 && ((given & 0x300000) != 0x300000))
5315 /* VPT vector T3 variant. */
5316 || ((given & 0xff811f50) == 0xfe011f00)
5317 /* VPT vector T4 variant. */
5318 || ((given & 0xff811f70) == 0xfe010f40)
5319 /* VPT vector T5 variant. */
5320 || ((given & 0xff811f70) == 0xfe010f60)
5321 /* VPT vector T6 variant. */
5322 || ((given & 0xff811f50) == 0xfe011f40)
5323 /* VPST vector T variant. */
5324 || ((given & 0xffbf1fff) == 0xfe310f4d))
78933a4a 5325 return true;
143275ea 5326 else
78933a4a 5327 return false;
143275ea
AV		 5328}
5329
73cd51e5
AV		 5330/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5331 and ending bitfield = END. END must be greater than START. */
5332
5333static unsigned long
5334arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5335{
5336 int bits = end - start;
5337
5338 if (bits < 0)
5339 abort ();
5340
5341 return ((given >> start) & ((2ul << bits) - 1));
5342}
5343
5344/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5345 START:END and START2:END2. END/END2 must be greater than
5346 START/START2. */
5347
5348static unsigned long
5349arm_decode_field_multiple (unsigned long given, unsigned int start,
5350 unsigned int end, unsigned int start2,
5351 unsigned int end2)
5352{
5353 int bits = end - start;
5354 int bits2 = end2 - start2;
5355 unsigned long value = 0;
5356 int width = 0;
5357
5358 if (bits2 < 0)
5359 abort ();
5360
5361 value = arm_decode_field (given, start, end);
5362 width += bits + 1;
5363
5364 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5365 return value;
5366}
5367
5368/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5369 This helps us decode instructions that change mnemonic depending on specific
5370 operand values/encodings. */
5371
78933a4a 5372static bool
73cd51e5
AV		 5373is_mve_encoding_conflict (unsigned long given,
5374 enum mve_instructions matched_insn)
5375{
143275ea
AV		 5376 switch (matched_insn)
5377 {
5378 case MVE_VPST:
5379 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5380 return true;
143275ea 5381 else
78933a4a 5382 return false;
143275ea
AV		 5383
5384 case MVE_VPT_FP_T1:
5385 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5386 return true;
143275ea
AV		 5387 if ((arm_decode_field (given, 12, 12) == 0)
5388 && (arm_decode_field (given, 0, 0) == 1))
78933a4a
AM		 5389 return true;
5390 return false;
143275ea
AV		 5391
5392 case MVE_VPT_FP_T2:
5393 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5394 return true;
143275ea 5395 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a
AM		 5396 return true;
5397 return false;
143275ea
AV		 5398
5399 case MVE_VPT_VEC_T1:
5400 case MVE_VPT_VEC_T2:
5401 case MVE_VPT_VEC_T3:
5402 case MVE_VPT_VEC_T4:
5403 case MVE_VPT_VEC_T5:
5404 case MVE_VPT_VEC_T6:
5405 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5406 return true;
143275ea 5407 if (arm_decode_field (given, 20, 21) == 3)
78933a4a
AM		 5408 return true;
5409 return false;
143275ea
AV		 5410
5411 case MVE_VCMP_FP_T1:
5412 if ((arm_decode_field (given, 12, 12) == 0)
5413 && (arm_decode_field (given, 0, 0) == 1))
78933a4a 5414 return true;
143275ea 5415 else
78933a4a 5416 return false;
143275ea
AV		 5417
5418 case MVE_VCMP_FP_T2:
5419 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5420 return true;
143275ea 5421 else
78933a4a 5422 return false;
143275ea 5423
14b456f2
AV		 5424 case MVE_VQADD_T2:
5425 case MVE_VQSUB_T2:
f49bb598
AV		 5426 case MVE_VMUL_VEC_T2:
5427 case MVE_VMULH:
5428 case MVE_VRMULH:
56858bea
AV		 5429 case MVE_VMLA:
5430 case MVE_VMAX:
5431 case MVE_VMIN:
e523f101 5432 case MVE_VBRSR:
66dcaa5d
AV		 5433 case MVE_VADD_VEC_T2:
5434 case MVE_VSUB_VEC_T2:
5435 case MVE_VABAV:
ed63aa17
AV		 5436 case MVE_VQRSHL_T1:
5437 case MVE_VQSHL_T4:
5438 case MVE_VRSHL_T1:
5439 case MVE_VSHL_T3:
897b9bbc
AV		 5440 case MVE_VCADD_VEC:
5441 case MVE_VHCADD:
1c8f2df8
AV		 5442 case MVE_VDDUP:
5443 case MVE_VIDUP:
d3b63143
AV		 5444 case MVE_VQRDMLADH:
5445 case MVE_VQDMLAH:
5446 case MVE_VQRDMLAH:
5447 case MVE_VQDMLASH:
5448 case MVE_VQRDMLASH:
5449 case MVE_VQDMLSDH:
5450 case MVE_VQRDMLSDH:
5451 case MVE_VQDMULH_T3:
5452 case MVE_VQRDMULH_T4:
5453 case MVE_VQDMLADH:
5454 case MVE_VMLAS:
14925797 5455 case MVE_VMULL_INT:
9743db03
AV		 5456 case MVE_VHADD_T2:
5457 case MVE_VHSUB_T2:
143275ea
AV		 5458 case MVE_VCMP_VEC_T1:
5459 case MVE_VCMP_VEC_T2:
5460 case MVE_VCMP_VEC_T3:
5461 case MVE_VCMP_VEC_T4:
5462 case MVE_VCMP_VEC_T5:
5463 case MVE_VCMP_VEC_T6:
5464 if (arm_decode_field (given, 20, 21) == 3)
78933a4a 5465 return true;
143275ea 5466 else
78933a4a 5467 return false;
143275ea 5468
04d54ace
AV		 5469 case MVE_VLD2:
5470 case MVE_VLD4:
5471 case MVE_VST2:
5472 case MVE_VST4:
5473 if (arm_decode_field (given, 7, 8) == 3)
78933a4a 5474 return true;
04d54ace 5475 else
78933a4a 5476 return false;
04d54ace 5477
aef6d006
AV		 5478 case MVE_VSTRB_T1:
5479 case MVE_VSTRH_T2:
5480 if ((arm_decode_field (given, 24, 24) == 0)
5481 && (arm_decode_field (given, 21, 21) == 0))
5482 {
78933a4a 5483 return true;
aef6d006
AV		 5484 }
5485 else if ((arm_decode_field (given, 7, 8) == 3))
78933a4a 5486 return true;
aef6d006 5487 else
78933a4a 5488 return false;
aef6d006 5489
e683cb41
AC		 5490 case MVE_VLDRB_T1:
5491 case MVE_VLDRH_T2:
5492 case MVE_VLDRW_T7:
aef6d006
AV		 5493 case MVE_VSTRB_T5:
5494 case MVE_VSTRH_T6:
5495 case MVE_VSTRW_T7:
5496 if ((arm_decode_field (given, 24, 24) == 0)
5497 && (arm_decode_field (given, 21, 21) == 0))
5498 {
78933a4a 5499 return true;
aef6d006
AV		 5500 }
5501 else
78933a4a 5502 return false;
aef6d006 5503
bf0b396d
AV		 5504 case MVE_VCVT_FP_FIX_VEC:
5505 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5506
c507f10b
AV		 5507 case MVE_VBIC_IMM:
5508 case MVE_VORR_IMM:
5509 {
5510 unsigned long cmode = arm_decode_field (given, 8, 11);
5511
5512 if ((cmode & 1) == 0)
78933a4a 5513 return true;
c507f10b 5514 else if ((cmode & 0xc) == 0xc)
78933a4a 5515 return true;
c507f10b 5516 else
78933a4a 5517 return false;
c507f10b
AV		 5518 }
5519
5520 case MVE_VMVN_IMM:
5521 {
5522 unsigned long cmode = arm_decode_field (given, 8, 11);
5523
ce760a76 5524 if (cmode == 0xe)
78933a4a 5525 return true;
ce760a76 5526 else if ((cmode & 0x9) == 1)
78933a4a 5527 return true;
ce760a76 5528 else if ((cmode & 0xd) == 9)
78933a4a 5529 return true;
c507f10b 5530 else
78933a4a 5531 return false;
c507f10b
AV		 5532 }
5533
5534 case MVE_VMOV_IMM_TO_VEC:
5535 if ((arm_decode_field (given, 5, 5) == 1)
5536 && (arm_decode_field (given, 8, 11) != 0xe))
78933a4a 5537 return true;
c507f10b 5538 else
78933a4a 5539 return false;
c507f10b 5540
14925797
AV		 5541 case MVE_VMOVL:
5542 {
5543 unsigned long size = arm_decode_field (given, 19, 20);
5544 if ((size == 0) || (size == 3))
78933a4a 5545 return true;
14925797 5546 else
78933a4a 5547 return false;
14925797
AV		 5548 }
5549
56858bea
AV		 5550 case MVE_VMAXA:
5551 case MVE_VMINA:
5552 case MVE_VMAXV:
5553 case MVE_VMAXAV:
5554 case MVE_VMINV:
5555 case MVE_VMINAV:
ed63aa17
AV		 5556 case MVE_VQRSHL_T2:
5557 case MVE_VQSHL_T1:
5558 case MVE_VRSHL_T2:
5559 case MVE_VSHL_T2:
5560 case MVE_VSHLL_T2:
d3b63143 5561 case MVE_VADDV:
14925797
AV		 5562 case MVE_VMOVN:
5563 case MVE_VQMOVUN:
5564 case MVE_VQMOVN:
5565 if (arm_decode_field (given, 18, 19) == 3)
78933a4a 5566 return true;
14925797 5567 else
78933a4a 5568 return false;
14925797 5569
d3b63143
AV		 5570 case MVE_VMLSLDAV:
5571 case MVE_VRMLSLDAVH:
5572 case MVE_VMLALDAV:
5573 case MVE_VADDLV:
5574 if (arm_decode_field (given, 20, 22) == 7)
78933a4a 5575 return true;
d3b63143 5576 else
78933a4a 5577 return false;
d3b63143
AV		 5578
5579 case MVE_VRMLALDAVH:
5580 if ((arm_decode_field (given, 20, 22) & 6) == 6)
78933a4a 5581 return true;
d3b63143 5582 else
78933a4a 5583 return false;
d3b63143 5584
1c8f2df8
AV		 5585 case MVE_VDWDUP:
5586 case MVE_VIWDUP:
5587 if ((arm_decode_field (given, 20, 21) == 3)
5588 || (arm_decode_field (given, 1, 3) == 7))
78933a4a 5589 return true;
1c8f2df8 5590 else
78933a4a 5591 return false;
1c8f2df8 5592
ed63aa17
AV		 5593
5594 case MVE_VSHLL_T1:
5595 if (arm_decode_field (given, 16, 18) == 0)
5596 {
5597 unsigned long sz = arm_decode_field (given, 19, 20);
5598
5599 if ((sz == 1) || (sz == 2))
78933a4a 5600 return true;
ed63aa17 5601 else
78933a4a 5602 return false;
ed63aa17
AV		 5603 }
5604 else
78933a4a 5605 return false;
ed63aa17
AV		 5606
5607 case MVE_VQSHL_T2:
5608 case MVE_VQSHLU_T3:
5609 case MVE_VRSHR:
5610 case MVE_VSHL_T1:
5611 case MVE_VSHR:
5612 case MVE_VSLI:
5613 case MVE_VSRI:
5614 if (arm_decode_field (given, 19, 21) == 0)
78933a4a 5615 return true;
ed63aa17 5616 else
78933a4a 5617 return false;
ed63aa17 5618
e523f101
AV		 5619 case MVE_VCTP:
5620 if (arm_decode_field (given, 16, 19) == 0xf)
78933a4a 5621 return true;
e523f101 5622 else
78933a4a 5623 return false;
e523f101 5624
23d00a41
SD		 5625 case MVE_ASRLI:
5626 case MVE_ASRL:
5627 case MVE_LSLLI:
5628 case MVE_LSLL:
5629 case MVE_LSRL:
5630 case MVE_SQRSHRL:
5631 case MVE_SQSHLL:
5632 case MVE_SRSHRL:
5633 case MVE_UQRSHLL:
5634 case MVE_UQSHLL:
5635 case MVE_URSHRL:
5636 if (arm_decode_field (given, 9, 11) == 0x7)
78933a4a 5637 return true;
23d00a41 5638 else
78933a4a 5639 return false;
23d00a41 5640
e39c1607
SD		 5641 case MVE_CSINC:
5642 case MVE_CSINV:
5643 {
5644 unsigned long rm, rn;
5645 rm = arm_decode_field (given, 0, 3);
5646 rn = arm_decode_field (given, 16, 19);
5647 /* CSET/CSETM. */
5648 if (rm == 0xf && rn == 0xf)
78933a4a 5649 return true;
e39c1607
SD		 5650 /* CINC/CINV. */
5651 else if (rn == rm && rn != 0xf)
78933a4a 5652 return true;
e39c1607
SD		 5653 }
5654 /* Fall through. */
5655 case MVE_CSEL:
5656 case MVE_CSNEG:
5657 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5658 return true;
e39c1607
SD		 5659 /* CNEG. */
5660 else if (matched_insn == MVE_CSNEG)
5661 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
78933a4a
AM		 5662 return true;
5663 return false;
e39c1607 5664
143275ea 5665 default:
66dcaa5d
AV		 5666 case MVE_VADD_FP_T1:
5667 case MVE_VADD_FP_T2:
5668 case MVE_VADD_VEC_T1:
78933a4a 5669 return false;
143275ea
AV		 5670
5671 }
73cd51e5
AV		 5672}
5673
aef6d006
AV		 5674static void
5675print_mve_vld_str_addr (struct disassemble_info *info,
5676 unsigned long given,
5677 enum mve_instructions matched_insn)
5678{
5679 void *stream = info->stream;
6576bffe 5680 fprintf_styled_ftype func = info->fprintf_styled_func;
aef6d006
AV		 5681
5682 unsigned long p, w, gpr, imm, add, mod_imm;
5683
5684 imm = arm_decode_field (given, 0, 6);
5685 mod_imm = imm;
5686
5687 switch (matched_insn)
5688 {
5689 case MVE_VLDRB_T1:
5690 case MVE_VSTRB_T1:
5691 gpr = arm_decode_field (given, 16, 18);
5692 break;
5693
5694 case MVE_VLDRH_T2:
5695 case MVE_VSTRH_T2:
5696 gpr = arm_decode_field (given, 16, 18);
5697 mod_imm = imm << 1;
5698 break;
5699
5700 case MVE_VLDRH_T6:
5701 case MVE_VSTRH_T6:
5702 gpr = arm_decode_field (given, 16, 19);
5703 mod_imm = imm << 1;
5704 break;
5705
5706 case MVE_VLDRW_T7:
5707 case MVE_VSTRW_T7:
5708 gpr = arm_decode_field (given, 16, 19);
5709 mod_imm = imm << 2;
5710 break;
5711
5712 case MVE_VLDRB_T5:
5713 case MVE_VSTRB_T5:
5714 gpr = arm_decode_field (given, 16, 19);
5715 break;
5716
5717 default:
5718 return;
5719 }
5720
5721 p = arm_decode_field (given, 24, 24);
5722 w = arm_decode_field (given, 21, 21);
5723
5724 add = arm_decode_field (given, 23, 23);
5725
5726 char * add_sub;
5727
5728 /* Don't print anything for '+' as it is implied. */
5729 if (add == 1)
5730 add_sub = "";
5731 else
5732 add_sub = "-";
5733
6576bffe 5734 func (stream, dis_style_text, "[");
4575eafb 5735 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
aef6d006
AV		 5736 if (p == 1)
5737 {
6576bffe
AB		 5738 func (stream, dis_style_text, ", ");
5739 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
aef6d006
AV		 5740 /* Offset mode. */
5741 if (w == 0)
6576bffe 5742 func (stream, dis_style_text, "]");
aef6d006
AV		 5743 /* Pre-indexed mode. */
5744 else
6576bffe 5745 func (stream, dis_style_text, "]!");
aef6d006
AV		 5746 }
5747 else if ((p == 0) && (w == 1))
6576bffe
AB		 5748 {
5749 /* Post-index mode. */
5750 func (stream, dis_style_text, "], ");
5751 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5752 }
aef6d006
AV		 5753}
5754
73cd51e5
AV		 5755/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5756 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5757 this encoding is undefined. */
5758
78933a4a 5759static bool
73cd51e5
AV		 5760is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5761 enum mve_undefined *undefined_code)
5762{
5763 *undefined_code = UNDEF_NONE;
5764
9743db03
AV		 5765 switch (matched_insn)
5766 {
5767 case MVE_VDUP:
5768 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5769 {
5770 *undefined_code = UNDEF_SIZE_3;
78933a4a 5771 return true;
9743db03
AV		 5772 }
5773 else
78933a4a 5774 return false;
9743db03 5775
14b456f2
AV		 5776 case MVE_VQADD_T1:
5777 case MVE_VQSUB_T1:
f49bb598 5778 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5779 case MVE_VABD_VEC:
5780 case MVE_VADD_VEC_T1:
5781 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5782 case MVE_VQDMULH_T1:
5783 case MVE_VQRDMULH_T2:
9743db03
AV		 5784 case MVE_VRHADD:
5785 case MVE_VHADD_T1:
5786 case MVE_VHSUB_T1:
5787 if (arm_decode_field (given, 20, 21) == 3)
5788 {
5789 *undefined_code = UNDEF_SIZE_3;
78933a4a 5790 return true;
9743db03
AV		 5791 }
5792 else
78933a4a 5793 return false;
9743db03 5794
aef6d006
AV		 5795 case MVE_VLDRB_T1:
5796 if (arm_decode_field (given, 7, 8) == 3)
5797 {
5798 *undefined_code = UNDEF_SIZE_3;
78933a4a 5799 return true;
aef6d006
AV		 5800 }
5801 else
78933a4a 5802 return false;
aef6d006
AV		 5803
5804 case MVE_VLDRH_T2:
5805 if (arm_decode_field (given, 7, 8) <= 1)
5806 {
5807 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 5808 return true;
aef6d006
AV		 5809 }
5810 else
78933a4a 5811 return false;
aef6d006
AV		 5812
5813 case MVE_VSTRB_T1:
5814 if ((arm_decode_field (given, 7, 8) == 0))
5815 {
5816 *undefined_code = UNDEF_SIZE_0;
78933a4a 5817 return true;
aef6d006
AV		 5818 }
5819 else
78933a4a 5820 return false;
aef6d006
AV		 5821
5822 case MVE_VSTRH_T2:
5823 if ((arm_decode_field (given, 7, 8) <= 1))
5824 {
5825 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 5826 return true;
aef6d006
AV		 5827 }
5828 else
78933a4a 5829 return false;
aef6d006 5830
ef1576a1
AV		 5831 case MVE_VLDRB_GATHER_T1:
5832 if (arm_decode_field (given, 7, 8) == 3)
5833 {
5834 *undefined_code = UNDEF_SIZE_3;
78933a4a 5835 return true;
ef1576a1
AV		 5836 }
5837 else if ((arm_decode_field (given, 28, 28) == 0)
5838 && (arm_decode_field (given, 7, 8) == 0))
5839 {
5840 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
78933a4a 5841 return true;
ef1576a1
AV		 5842 }
5843 else
78933a4a 5844 return false;
ef1576a1
AV		 5845
5846 case MVE_VLDRH_GATHER_T2:
5847 if (arm_decode_field (given, 7, 8) == 3)
5848 {
5849 *undefined_code = UNDEF_SIZE_3;
78933a4a 5850 return true;
ef1576a1
AV		 5851 }
5852 else if ((arm_decode_field (given, 28, 28) == 0)
5853 && (arm_decode_field (given, 7, 8) == 1))
5854 {
5855 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
78933a4a 5856 return true;
ef1576a1
AV		 5857 }
5858 else if (arm_decode_field (given, 7, 8) == 0)
5859 {
5860 *undefined_code = UNDEF_SIZE_0;
78933a4a 5861 return true;
ef1576a1
AV		 5862 }
5863 else
78933a4a 5864 return false;
ef1576a1
AV		 5865
5866 case MVE_VLDRW_GATHER_T3:
5867 if (arm_decode_field (given, 7, 8) != 2)
5868 {
5869 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 5870 return true;
ef1576a1
AV		 5871 }
5872 else if (arm_decode_field (given, 28, 28) == 0)
5873 {
5874 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 5875 return true;
ef1576a1
AV		 5876 }
5877 else
78933a4a 5878 return false;
ef1576a1
AV		 5879
5880 case MVE_VLDRD_GATHER_T4:
5881 if (arm_decode_field (given, 7, 8) != 3)
5882 {
5883 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 5884 return true;
ef1576a1
AV		 5885 }
5886 else if (arm_decode_field (given, 28, 28) == 0)
5887 {
5888 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 5889 return true;
ef1576a1
AV		 5890 }
5891 else
78933a4a 5892 return false;
ef1576a1
AV		 5893
5894 case MVE_VSTRB_SCATTER_T1:
5895 if (arm_decode_field (given, 7, 8) == 3)
5896 {
5897 *undefined_code = UNDEF_SIZE_3;
78933a4a 5898 return true;
ef1576a1
AV		 5899 }
5900 else
78933a4a 5901 return false;
ef1576a1
AV		 5902
5903 case MVE_VSTRH_SCATTER_T2:
5904 {
5905 unsigned long size = arm_decode_field (given, 7, 8);
5906 if (size == 3)
5907 {
5908 *undefined_code = UNDEF_SIZE_3;
78933a4a 5909 return true;
ef1576a1
AV		 5910 }
5911 else if (size == 0)
5912 {
5913 *undefined_code = UNDEF_SIZE_0;
78933a4a 5914 return true;
ef1576a1
AV		 5915 }
5916 else
78933a4a 5917 return false;
ef1576a1
AV		 5918 }
5919
5920 case MVE_VSTRW_SCATTER_T3:
5921 if (arm_decode_field (given, 7, 8) != 2)
5922 {
5923 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 5924 return true;
ef1576a1
AV		 5925 }
5926 else
78933a4a 5927 return false;
ef1576a1
AV		 5928
5929 case MVE_VSTRD_SCATTER_T4:
5930 if (arm_decode_field (given, 7, 8) != 3)
5931 {
5932 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 5933 return true;
ef1576a1
AV		 5934 }
5935 else
78933a4a 5936 return false;
ef1576a1 5937
bf0b396d
AV		 5938 case MVE_VCVT_FP_FIX_VEC:
5939 {
5940 unsigned long imm6 = arm_decode_field (given, 16, 21);
5941 if ((imm6 & 0x20) == 0)
5942 {
5943 *undefined_code = UNDEF_VCVT_IMM6;
78933a4a 5944 return true;
bf0b396d
AV		 5945 }
5946
5947 if ((arm_decode_field (given, 9, 9) == 0)
5948 && ((imm6 & 0x30) == 0x20))
5949 {
5950 *undefined_code = UNDEF_VCVT_FSI_IMM6;
78933a4a 5951 return true;
bf0b396d
AV		 5952 }
5953
78933a4a 5954 return false;
bf0b396d
AV		 5955 }
5956
f49bb598 5957 case MVE_VNEG_FP:
66dcaa5d 5958 case MVE_VABS_FP:
bf0b396d
AV		 5959 case MVE_VCVT_BETWEEN_FP_INT:
5960 case MVE_VCVT_FROM_FP_TO_INT:
5961 {
5962 unsigned long size = arm_decode_field (given, 18, 19);
5963 if (size == 0)
5964 {
5965 *undefined_code = UNDEF_SIZE_0;
78933a4a 5966 return true;
bf0b396d
AV		 5967 }
5968 else if (size == 3)
5969 {
5970 *undefined_code = UNDEF_SIZE_3;
78933a4a 5971 return true;
bf0b396d
AV		 5972 }
5973 else
78933a4a 5974 return false;
bf0b396d
AV		 5975 }
5976
c507f10b
AV		 5977 case MVE_VMOV_VEC_LANE_TO_GP:
5978 {
5979 unsigned long op1 = arm_decode_field (given, 21, 22);
5980 unsigned long op2 = arm_decode_field (given, 5, 6);
5981 unsigned long u = arm_decode_field (given, 23, 23);
5982
5983 if ((op2 == 0) && (u == 1))
5984 {
5985 if ((op1 == 0) || (op1 == 1))
5986 {
5987 *undefined_code = UNDEF_BAD_U_OP1_OP2;
78933a4a 5988 return true;
c507f10b
AV		 5989 }
5990 else
78933a4a 5991 return false;
c507f10b
AV		 5992 }
5993 else if (op2 == 2)
5994 {
5995 if ((op1 == 0) || (op1 == 1))
5996 {
5997 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 5998 return true;
c507f10b
AV		 5999 }
6000 else
78933a4a 6001 return false;
c507f10b
AV		 6002 }
6003
78933a4a 6004 return false;
c507f10b
AV		 6005 }
6006
6007 case MVE_VMOV_GP_TO_VEC_LANE:
6008 if (arm_decode_field (given, 5, 6) == 2)
6009 {
6010 unsigned long op1 = arm_decode_field (given, 21, 22);
6011 if ((op1 == 0) || (op1 == 1))
6012 {
6013 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6014 return true;
c507f10b
AV		 6015 }
6016 else
78933a4a 6017 return false;
c507f10b
AV		 6018 }
6019 else
78933a4a 6020 return false;
c507f10b 6021
c4a23bf8
SP		 6022 case MVE_VMOV_VEC_TO_VEC:
6023 if ((arm_decode_field (given, 5, 5) == 1)
6024 || (arm_decode_field (given, 22, 22) == 1))
78933a4a
AM		 6025 return true;
6026 return false;
c4a23bf8 6027
c507f10b
AV		 6028 case MVE_VMOV_IMM_TO_VEC:
6029 if (arm_decode_field (given, 5, 5) == 0)
6030 {
6031 unsigned long cmode = arm_decode_field (given, 8, 11);
6032
6033 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6034 {
6035 *undefined_code = UNDEF_OP_0_BAD_CMODE;
78933a4a 6036 return true;
c507f10b
AV		 6037 }
6038 else
78933a4a 6039 return false;
c507f10b
AV		 6040 }
6041 else
78933a4a 6042 return false;
c507f10b 6043
ed63aa17 6044 case MVE_VSHLL_T2:
14925797
AV		 6045 case MVE_VMOVN:
6046 if (arm_decode_field (given, 18, 19) == 2)
6047 {
6048 *undefined_code = UNDEF_SIZE_2;
78933a4a 6049 return true;
14925797
AV		 6050 }
6051 else
78933a4a 6052 return false;
14925797 6053
d3b63143
AV		 6054 case MVE_VRMLALDAVH:
6055 case MVE_VMLADAV_T1:
6056 case MVE_VMLADAV_T2:
6057 case MVE_VMLALDAV:
6058 if ((arm_decode_field (given, 28, 28) == 1)
6059 && (arm_decode_field (given, 12, 12) == 1))
6060 {
6061 *undefined_code = UNDEF_XCHG_UNS;
78933a4a 6062 return true;
d3b63143
AV		 6063 }
6064 else
78933a4a 6065 return false;
d3b63143 6066
ed63aa17
AV		 6067 case MVE_VQSHRN:
6068 case MVE_VQSHRUN:
6069 case MVE_VSHLL_T1:
6070 case MVE_VSHRN:
6071 {
6072 unsigned long sz = arm_decode_field (given, 19, 20);
6073 if (sz == 1)
78933a4a 6074 return false;
ed63aa17 6075 else if ((sz & 2) == 2)
78933a4a 6076 return false;
ed63aa17
AV		 6077 else
6078 {
6079 *undefined_code = UNDEF_SIZE;
78933a4a 6080 return true;
ed63aa17
AV		 6081 }
6082 }
6083 break;
6084
6085 case MVE_VQSHL_T2:
6086 case MVE_VQSHLU_T3:
6087 case MVE_VRSHR:
6088 case MVE_VSHL_T1:
6089 case MVE_VSHR:
6090 case MVE_VSLI:
6091 case MVE_VSRI:
6092 {
6093 unsigned long sz = arm_decode_field (given, 19, 21);
6094 if ((sz & 7) == 1)
78933a4a 6095 return false;
ed63aa17 6096 else if ((sz & 6) == 2)
78933a4a 6097 return false;
ed63aa17 6098 else if ((sz & 4) == 4)
78933a4a 6099 return false;
ed63aa17
AV		 6100 else
6101 {
6102 *undefined_code = UNDEF_SIZE;
78933a4a 6103 return true;
ed63aa17
AV		 6104 }
6105 }
6106
6107 case MVE_VQRSHRN:
6108 case MVE_VQRSHRUN:
6109 if (arm_decode_field (given, 19, 20) == 0)
6110 {
6111 *undefined_code = UNDEF_SIZE_0;
78933a4a 6112 return true;
ed63aa17
AV		 6113 }
6114 else
78933a4a 6115 return false;
ed63aa17 6116
66dcaa5d
AV		 6117 case MVE_VABS_VEC:
6118 if (arm_decode_field (given, 18, 19) == 3)
6119 {
6120 *undefined_code = UNDEF_SIZE_3;
78933a4a 6121 return true;
66dcaa5d
AV		 6122 }
6123 else
78933a4a 6124 return false;
66dcaa5d 6125
14b456f2
AV		 6126 case MVE_VQNEG:
6127 case MVE_VQABS:
f49bb598 6128 case MVE_VNEG_VEC:
e523f101
AV		 6129 case MVE_VCLS:
6130 case MVE_VCLZ:
6131 if (arm_decode_field (given, 18, 19) == 3)
6132 {
6133 *undefined_code = UNDEF_SIZE_3;
78933a4a 6134 return true;
e523f101
AV		 6135 }
6136 else
78933a4a 6137 return false;
e523f101 6138
14b456f2
AV		 6139 case MVE_VREV16:
6140 if (arm_decode_field (given, 18, 19) == 0)
78933a4a 6141 return false;
14b456f2
AV		 6142 else
6143 {
6144 *undefined_code = UNDEF_SIZE_NOT_0;
78933a4a 6145 return true;
14b456f2
AV		 6146 }
6147
6148 case MVE_VREV32:
6149 {
6150 unsigned long size = arm_decode_field (given, 18, 19);
6151 if ((size & 2) == 2)
6152 {
6153 *undefined_code = UNDEF_SIZE_2;
78933a4a 6154 return true;
14b456f2
AV		 6155 }
6156 else
78933a4a 6157 return false;
14b456f2
AV		 6158 }
6159
6160 case MVE_VREV64:
6161 if (arm_decode_field (given, 18, 19) != 3)
78933a4a 6162 return false;
14b456f2
AV		 6163 else
6164 {
6165 *undefined_code = UNDEF_SIZE_3;
78933a4a 6166 return true;
14b456f2
AV		 6167 }
6168
9743db03 6169 default:
78933a4a 6170 return false;
9743db03 6171 }
73cd51e5
AV		 6172}
6173
6174/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6175 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6176 why this encoding is unpredictable. */
6177
78933a4a 6178static bool
73cd51e5
AV		 6179is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6180 enum mve_unpredictable *unpredictable_code)
6181{
6182 *unpredictable_code = UNPRED_NONE;
6183
143275ea
AV		 6184 switch (matched_insn)
6185 {
6186 case MVE_VCMP_FP_T2:
6187 case MVE_VPT_FP_T2:
6188 if ((arm_decode_field (given, 12, 12) == 0)
6189 && (arm_decode_field (given, 5, 5) == 1))
6190 {
6191 *unpredictable_code = UNPRED_FCA_0_FCB_1;
78933a4a 6192 return true;
143275ea
AV		 6193 }
6194 else
78933a4a 6195 return false;
73cd51e5 6196
143275ea
AV		 6197 case MVE_VPT_VEC_T4:
6198 case MVE_VPT_VEC_T5:
6199 case MVE_VPT_VEC_T6:
6200 case MVE_VCMP_VEC_T4:
6201 case MVE_VCMP_VEC_T5:
6202 case MVE_VCMP_VEC_T6:
6203 if (arm_decode_field (given, 0, 3) == 0xd)
6204 {
6205 *unpredictable_code = UNPRED_R13;
78933a4a 6206 return true;
143275ea
AV		 6207 }
6208 else
78933a4a 6209 return false;
c1e26897 6210
9743db03
AV		 6211 case MVE_VDUP:
6212 {
6213 unsigned long gpr = arm_decode_field (given, 12, 15);
6214 if (gpr == 0xd)
6215 {
6216 *unpredictable_code = UNPRED_R13;
78933a4a 6217 return true;
9743db03
AV		 6218 }
6219 else if (gpr == 0xf)
6220 {
6221 *unpredictable_code = UNPRED_R15;
78933a4a 6222 return true;
9743db03
AV		 6223 }
6224
78933a4a 6225 return false;
9743db03
AV		 6226 }
6227
14b456f2
AV		 6228 case MVE_VQADD_T2:
6229 case MVE_VQSUB_T2:
f49bb598
AV		 6230 case MVE_VMUL_FP_T2:
6231 case MVE_VMUL_VEC_T2:
56858bea 6232 case MVE_VMLA:
e523f101 6233 case MVE_VBRSR:
66dcaa5d
AV		 6234 case MVE_VADD_FP_T2:
6235 case MVE_VSUB_FP_T2:
6236 case MVE_VADD_VEC_T2:
6237 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6238 case MVE_VQRSHL_T2:
6239 case MVE_VQSHL_T1:
6240 case MVE_VRSHL_T2:
6241 case MVE_VSHL_T2:
6242 case MVE_VSHLC:
d3b63143
AV		 6243 case MVE_VQDMLAH:
6244 case MVE_VQRDMLAH:
6245 case MVE_VQDMLASH:
6246 case MVE_VQRDMLASH:
6247 case MVE_VQDMULH_T3:
6248 case MVE_VQRDMULH_T4:
6249 case MVE_VMLAS:
9743db03
AV		 6250 case MVE_VFMA_FP_SCALAR:
6251 case MVE_VFMAS_FP_SCALAR:
6252 case MVE_VHADD_T2:
6253 case MVE_VHSUB_T2:
6254 {
6255 unsigned long gpr = arm_decode_field (given, 0, 3);
6256 if (gpr == 0xd)
6257 {
6258 *unpredictable_code = UNPRED_R13;
78933a4a 6259 return true;
9743db03
AV		 6260 }
6261 else if (gpr == 0xf)
6262 {
6263 *unpredictable_code = UNPRED_R15;
78933a4a 6264 return true;
9743db03
AV		 6265 }
6266
78933a4a 6267 return false;
9743db03
AV		 6268 }
6269
04d54ace
AV		 6270 case MVE_VLD2:
6271 case MVE_VST2:
6272 {
6273 unsigned long rn = arm_decode_field (given, 16, 19);
6274
6275 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6276 {
6277 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6278 return true;
04d54ace
AV		 6279 }
6280
6281 if (rn == 0xf)
6282 {
6283 *unpredictable_code = UNPRED_R15;
78933a4a 6284 return true;
04d54ace
AV		 6285 }
6286
6287 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6288 {
6289 *unpredictable_code = UNPRED_Q_GT_6;
78933a4a 6290 return true;
04d54ace
AV		 6291 }
6292 else
78933a4a 6293 return false;
04d54ace
AV		 6294 }
6295
6296 case MVE_VLD4:
6297 case MVE_VST4:
6298 {
6299 unsigned long rn = arm_decode_field (given, 16, 19);
6300
6301 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6302 {
6303 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6304 return true;
04d54ace
AV		 6305 }
6306
6307 if (rn == 0xf)
6308 {
6309 *unpredictable_code = UNPRED_R15;
78933a4a 6310 return true;
04d54ace
AV		 6311 }
6312
6313 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6314 {
6315 *unpredictable_code = UNPRED_Q_GT_4;
78933a4a 6316 return true;
04d54ace
AV		 6317 }
6318 else
78933a4a 6319 return false;
04d54ace
AV		 6320 }
6321
aef6d006
AV		 6322 case MVE_VLDRB_T5:
6323 case MVE_VLDRH_T6:
6324 case MVE_VLDRW_T7:
6325 case MVE_VSTRB_T5:
6326 case MVE_VSTRH_T6:
6327 case MVE_VSTRW_T7:
6328 {
6329 unsigned long rn = arm_decode_field (given, 16, 19);
6330
6331 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6332 {
6333 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6334 return true;
aef6d006
AV		 6335 }
6336 else if (rn == 0xf)
6337 {
6338 *unpredictable_code = UNPRED_R15;
78933a4a 6339 return true;
aef6d006
AV		 6340 }
6341 else
78933a4a 6342 return false;
aef6d006
AV		 6343 }
6344
ef1576a1
AV		 6345 case MVE_VLDRB_GATHER_T1:
6346 if (arm_decode_field (given, 0, 0) == 1)
6347 {
6348 *unpredictable_code = UNPRED_OS;
78933a4a 6349 return true;
ef1576a1
AV		 6350 }
6351
6352 /* fall through. */
6353 /* To handle common code with T2-T4 variants. */
6354 case MVE_VLDRH_GATHER_T2:
6355 case MVE_VLDRW_GATHER_T3:
6356 case MVE_VLDRD_GATHER_T4:
6357 {
6358 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6359 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6360
6361 if (qd == qm)
6362 {
6363 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6364 return true;
ef1576a1
AV		 6365 }
6366
6367 if (arm_decode_field (given, 16, 19) == 0xf)
6368 {
6369 *unpredictable_code = UNPRED_R15;
78933a4a 6370 return true;
ef1576a1
AV		 6371 }
6372
78933a4a 6373 return false;
ef1576a1
AV		 6374 }
6375
6376 case MVE_VLDRW_GATHER_T5:
6377 case MVE_VLDRD_GATHER_T6:
6378 {
6379 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6380 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6381
6382 if (qd == qm)
6383 {
6384 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6385 return true;
ef1576a1
AV		 6386 }
6387 else
78933a4a 6388 return false;
ef1576a1
AV		 6389 }
6390
6391 case MVE_VSTRB_SCATTER_T1:
6392 if (arm_decode_field (given, 16, 19) == 0xf)
6393 {
6394 *unpredictable_code = UNPRED_R15;
78933a4a 6395 return true;
ef1576a1
AV		 6396 }
6397 else if (arm_decode_field (given, 0, 0) == 1)
6398 {
6399 *unpredictable_code = UNPRED_OS;
78933a4a 6400 return true;
ef1576a1
AV		 6401 }
6402 else
78933a4a 6403 return false;
ef1576a1
AV		 6404
6405 case MVE_VSTRH_SCATTER_T2:
6406 case MVE_VSTRW_SCATTER_T3:
6407 case MVE_VSTRD_SCATTER_T4:
6408 if (arm_decode_field (given, 16, 19) == 0xf)
6409 {
6410 *unpredictable_code = UNPRED_R15;
78933a4a 6411 return true;
ef1576a1
AV		 6412 }
6413 else
78933a4a 6414 return false;
ef1576a1 6415
c507f10b
AV		 6416 case MVE_VMOV2_VEC_LANE_TO_GP:
6417 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6418 case MVE_VCVT_BETWEEN_FP_INT:
6419 case MVE_VCVT_FROM_FP_TO_INT:
6420 {
6421 unsigned long rt = arm_decode_field (given, 0, 3);
6422 unsigned long rt2 = arm_decode_field (given, 16, 19);
6423
6424 if ((rt == 0xd) || (rt2 == 0xd))
6425 {
6426 *unpredictable_code = UNPRED_R13;
78933a4a 6427 return true;
bf0b396d
AV		 6428 }
6429 else if ((rt == 0xf) || (rt2 == 0xf))
6430 {
6431 *unpredictable_code = UNPRED_R15;
78933a4a 6432 return true;
bf0b396d 6433 }
e683cb41 6434 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
bf0b396d
AV		 6435 {
6436 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
78933a4a 6437 return true;
bf0b396d
AV		 6438 }
6439
78933a4a 6440 return false;
bf0b396d
AV		 6441 }
6442
56858bea
AV		 6443 case MVE_VMAXV:
6444 case MVE_VMAXAV:
6445 case MVE_VMAXNMV_FP:
6446 case MVE_VMAXNMAV_FP:
6447 case MVE_VMINNMV_FP:
6448 case MVE_VMINNMAV_FP:
6449 case MVE_VMINV:
6450 case MVE_VMINAV:
66dcaa5d 6451 case MVE_VABAV:
c507f10b
AV		 6452 case MVE_VMOV_HFP_TO_GP:
6453 case MVE_VMOV_GP_TO_VEC_LANE:
6454 case MVE_VMOV_VEC_LANE_TO_GP:
6455 {
6456 unsigned long rda = arm_decode_field (given, 12, 15);
6457 if (rda == 0xd)
6458 {
6459 *unpredictable_code = UNPRED_R13;
78933a4a 6460 return true;
c507f10b
AV		 6461 }
6462 else if (rda == 0xf)
6463 {
6464 *unpredictable_code = UNPRED_R15;
78933a4a 6465 return true;
c507f10b
AV		 6466 }
6467
78933a4a 6468 return false;
c507f10b
AV		 6469 }
6470
14925797
AV		 6471 case MVE_VMULL_INT:
6472 {
6473 unsigned long Qd;
6474 unsigned long Qm;
6475 unsigned long Qn;
6476
6477 if (arm_decode_field (given, 20, 21) == 2)
6478 {
6479 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6480 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6481 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6482
6483 if ((Qd == Qn) || (Qd == Qm))
6484 {
6485 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6486 return true;
14925797
AV		 6487 }
6488 else
78933a4a 6489 return false;
14925797
AV		 6490 }
6491 else
78933a4a 6492 return false;
14925797
AV		 6493 }
6494
897b9bbc 6495 case MVE_VCMUL_FP:
14925797
AV		 6496 case MVE_VQDMULL_T1:
6497 {
6498 unsigned long Qd;
6499 unsigned long Qm;
6500 unsigned long Qn;
6501
6502 if (arm_decode_field (given, 28, 28) == 1)
6503 {
6504 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6505 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6506 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6507
6508 if ((Qd == Qn) || (Qd == Qm))
6509 {
6510 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6511 return true;
14925797
AV		 6512 }
6513 else
78933a4a 6514 return false;
14925797
AV		 6515 }
6516 else
78933a4a 6517 return false;
14925797
AV		 6518 }
6519
6520 case MVE_VQDMULL_T2:
6521 {
6522 unsigned long gpr = arm_decode_field (given, 0, 3);
6523 if (gpr == 0xd)
6524 {
6525 *unpredictable_code = UNPRED_R13;
78933a4a 6526 return true;
14925797
AV		 6527 }
6528 else if (gpr == 0xf)
6529 {
6530 *unpredictable_code = UNPRED_R15;
78933a4a 6531 return true;
14925797
AV		 6532 }
6533
6534 if (arm_decode_field (given, 28, 28) == 1)
6535 {
6536 unsigned long Qd
6537 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6538 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6539
a9d96ab9 6540 if (Qd == Qn)
14925797
AV		 6541 {
6542 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6543 return true;
14925797
AV		 6544 }
6545 else
78933a4a 6546 return false;
14925797
AV		 6547 }
6548
78933a4a 6549 return false;
14925797
AV		 6550 }
6551
d3b63143
AV		 6552 case MVE_VMLSLDAV:
6553 case MVE_VRMLSLDAVH:
6554 case MVE_VMLALDAV:
6555 case MVE_VADDLV:
6556 if (arm_decode_field (given, 20, 22) == 6)
6557 {
6558 *unpredictable_code = UNPRED_R13;
78933a4a 6559 return true;
d3b63143
AV		 6560 }
6561 else
78933a4a 6562 return false;
d3b63143 6563
1c8f2df8
AV		 6564 case MVE_VDWDUP:
6565 case MVE_VIWDUP:
6566 if (arm_decode_field (given, 1, 3) == 6)
6567 {
6568 *unpredictable_code = UNPRED_R13;
78933a4a 6569 return true;
1c8f2df8
AV		 6570 }
6571 else
78933a4a 6572 return false;
1c8f2df8 6573
897b9bbc
AV		 6574 case MVE_VCADD_VEC:
6575 case MVE_VHCADD:
6576 {
6577 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6578 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6579 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6580 {
6581 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6582 return true;
897b9bbc
AV		 6583 }
6584 else
78933a4a 6585 return false;
897b9bbc
AV		 6586 }
6587
6588 case MVE_VCADD_FP:
6589 {
6590 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6591 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6592 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6593 {
6594 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6595 return true;
897b9bbc
AV		 6596 }
6597 else
78933a4a 6598 return false;
897b9bbc
AV		 6599 }
6600
6601 case MVE_VCMLA_FP:
6602 {
6603 unsigned long Qda;
6604 unsigned long Qm;
6605 unsigned long Qn;
6606
6607 if (arm_decode_field (given, 20, 20) == 1)
6608 {
6609 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6610 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6611 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6612
6613 if ((Qda == Qn) || (Qda == Qm))
6614 {
6615 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6616 return true;
897b9bbc
AV		 6617 }
6618 else
78933a4a 6619 return false;
897b9bbc
AV		 6620 }
6621 else
78933a4a 6622 return false;
897b9bbc
AV		 6623
6624 }
6625
e523f101
AV		 6626 case MVE_VCTP:
6627 if (arm_decode_field (given, 16, 19) == 0xd)
6628 {
6629 *unpredictable_code = UNPRED_R13;
78933a4a 6630 return true;
e523f101
AV		 6631 }
6632 else
78933a4a 6633 return false;
e523f101 6634
14b456f2
AV		 6635 case MVE_VREV64:
6636 {
6637 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6638 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6639
6640 if (qd == qm)
6641 {
6642 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6643 return true;
14b456f2
AV		 6644 }
6645 else
78933a4a 6646 return false;
14b456f2
AV		 6647 }
6648
23d00a41
SD		 6649 case MVE_LSLL:
6650 case MVE_LSLLI:
6651 case MVE_LSRL:
6652 case MVE_ASRL:
6653 case MVE_ASRLI:
6654 case MVE_UQSHLL:
6655 case MVE_UQRSHLL:
6656 case MVE_URSHRL:
6657 case MVE_SRSHRL:
6658 case MVE_SQSHLL:
6659 case MVE_SQRSHRL:
6660 {
6661 unsigned long gpr = arm_decode_field (given, 9, 11);
6662 gpr = ((gpr << 1) | 1);
6663 if (gpr == 0xd)
6664 {
6665 *unpredictable_code = UNPRED_R13;
78933a4a 6666 return true;
23d00a41
SD		 6667 }
6668 else if (gpr == 0xf)
6669 {
6670 *unpredictable_code = UNPRED_R15;
78933a4a 6671 return true;
23d00a41
SD		 6672 }
6673
78933a4a 6674 return false;
23d00a41
SD		 6675 }
6676
143275ea 6677 default:
78933a4a 6678 return false;
143275ea
AV		 6679 }
6680}
c1e26897 6681
c507f10b
AV		 6682static void
6683print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6684{
6685 unsigned long op1 = arm_decode_field (given, 21, 22);
6686 unsigned long op2 = arm_decode_field (given, 5, 6);
6687 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6688 unsigned long index_operand, esize, targetBeat, idx;
c507f10b 6689 void *stream = info->stream;
6576bffe 6690 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 6691
6692 if ((op1 & 0x2) == 0x2)
6693 {
43dd7626 6694 index_operand = op2;
c507f10b
AV		 6695 esize = 8;
6696 }
6697 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6698 {
43dd7626 6699 index_operand = op2 >> 1;
c507f10b
AV		 6700 esize = 16;
6701 }
6702 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6703 {
43dd7626 6704 index_operand = 0;
c507f10b
AV		 6705 esize = 32;
6706 }
6707 else
6708 {
6576bffe 6709 func (stream, dis_style_text, "<undefined index>");
c507f10b
AV		 6710 return;
6711 }
6712
6713 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6714 idx = index_operand + targetBeat * (32/esize);
c507f10b 6715
6576bffe 6716 func (stream, dis_style_immediate, "%lu", idx);
c507f10b
AV		 6717}
6718
6719/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6720 in length and integer of floating-point type. */
6721static void
6722print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6723 unsigned int ibit_loc, const struct mopcode32 *insn)
6724{
6725 int bits = 0;
6726 int cmode = (given >> 8) & 0xf;
6727 int op = (given >> 5) & 0x1;
6728 unsigned long value = 0, hival = 0;
6729 unsigned shift;
6730 int size = 0;
6731 int isfloat = 0;
6732 void *stream = info->stream;
6576bffe 6733 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 6734
6735 /* On Neon the 'i' bit is at bit 24, on mve it is
6736 at bit 28. */
6737 bits |= ((given >> ibit_loc) & 1) << 7;
6738 bits |= ((given >> 16) & 7) << 4;
6739 bits |= ((given >> 0) & 15) << 0;
6740
6741 if (cmode < 8)
6742 {
6743 shift = (cmode >> 1) & 3;
6744 value = (unsigned long) bits << (8 * shift);
6745 size = 32;
6746 }
6747 else if (cmode < 12)
6748 {
6749 shift = (cmode >> 1) & 1;
6750 value = (unsigned long) bits << (8 * shift);
6751 size = 16;
6752 }
6753 else if (cmode < 14)
6754 {
6755 shift = (cmode & 1) + 1;
6756 value = (unsigned long) bits << (8 * shift);
6757 value |= (1ul << (8 * shift)) - 1;
6758 size = 32;
6759 }
6760 else if (cmode == 14)
6761 {
6762 if (op)
6763 {
6764 /* Bit replication into bytes. */
6765 int ix;
6766 unsigned long mask;
6767
6768 value = 0;
6769 hival = 0;
6770 for (ix = 7; ix >= 0; ix--)
6771 {
6772 mask = ((bits >> ix) & 1) ? 0xff : 0;
6773 if (ix <= 3)
6774 value = (value << 8) | mask;
6775 else
6776 hival = (hival << 8) | mask;
6777 }
6778 size = 64;
6779 }
6780 else
6781 {
6782 /* Byte replication. */
6783 value = (unsigned long) bits;
6784 size = 8;
6785 }
6786 }
6787 else if (!op)
6788 {
6789 /* Floating point encoding. */
6790 int tmp;
6791
6792 value = (unsigned long) (bits & 0x7f) << 19;
6793 value |= (unsigned long) (bits & 0x80) << 24;
6794 tmp = bits & 0x40 ? 0x3c : 0x40;
6795 value |= (unsigned long) tmp << 24;
6796 size = 32;
6797 isfloat = 1;
6798 }
6799 else
6800 {
6576bffe 6801 func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
c507f10b
AV		 6802 bits, cmode, op);
6803 size = 32;
6804 return;
6805 }
6806
279edac5
AM		 6807 /* printU determines whether the immediate value should be printed as
6808 unsigned. */
c507f10b
AV		 6809 unsigned printU = 0;
6810 switch (insn->mve_op)
6811 {
6812 default:
6813 break;
279edac5 6814 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 6815 case MVE_VBIC_IMM:
6816 case MVE_VORR_IMM:
6817 case MVE_VMVN_IMM:
6818 case MVE_VMOV_IMM_TO_VEC:
6819 printU = 1;
6820 break;
6821 }
6822 switch (size)
6823 {
6824 case 8:
6576bffe
AB		 6825 func (stream, dis_style_immediate, "#%ld", value);
6826 func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
c507f10b
AV		 6827 break;
6828
6829 case 16:
6576bffe
AB		 6830 func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
6831 func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
c507f10b
AV		 6832 break;
6833
6834 case 32:
6835 if (isfloat)
6836 {
6837 unsigned char valbytes[4];
6838 double fvalue;
6839
6840 /* Do this a byte at a time so we don't have to
6841 worry about the host's endianness. */
6842 valbytes[0] = value & 0xff;
6843 valbytes[1] = (value >> 8) & 0xff;
6844 valbytes[2] = (value >> 16) & 0xff;
6845 valbytes[3] = (value >> 24) & 0xff;
6846
6847 floatformat_to_double
6848 (& floatformat_ieee_single_little, valbytes,
6849 & fvalue);
6850
6576bffe
AB		 6851 func (stream, dis_style_immediate, "#%.7g", fvalue);
6852 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
c507f10b
AV		 6853 }
6854 else
6576bffe
AB		 6855 {
6856 func (stream, dis_style_immediate,
6857 printU ? "#%lu" : "#%ld",
6858 (long) (((value & 0x80000000L) != 0)
6859 && !printU
6860 ? value | ~0xffffffffL : value));
6861 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6862 }
c507f10b
AV		 6863 break;
6864
6865 case 64:
6576bffe 6866 func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
c507f10b
AV		 6867 break;
6868
6869 default:
6870 abort ();
6871 }
6872
6873}
6874
73cd51e5
AV		 6875static void
6876print_mve_undefined (struct disassemble_info *info,
6877 enum mve_undefined undefined_code)
6878{
6879 void *stream = info->stream;
6576bffe 6880 fprintf_styled_ftype func = info->fprintf_styled_func;
d8521074
AB		 6881 /* Initialize REASON to avoid compiler warning about uninitialized
6882 usage, though such usage should be impossible. */
6883 const char *reason = "??";
73cd51e5
AV		 6884
6885 switch (undefined_code)
6886 {
ed63aa17 6887 case UNDEF_SIZE:
6576bffe 6888 reason = "illegal size";
ed63aa17
AV		 6889 break;
6890
aef6d006 6891 case UNDEF_SIZE_0:
6576bffe 6892 reason = "size equals zero";
aef6d006
AV		 6893 break;
6894
c507f10b 6895 case UNDEF_SIZE_2:
6576bffe 6896 reason = "size equals two";
c507f10b
AV		 6897 break;
6898
9743db03 6899 case UNDEF_SIZE_3:
6576bffe 6900 reason = "size equals three";
9743db03
AV		 6901 break;
6902
aef6d006 6903 case UNDEF_SIZE_LE_1:
6576bffe 6904 reason = "size <= 1";
aef6d006
AV		 6905 break;
6906
14b456f2 6907 case UNDEF_SIZE_NOT_0:
6576bffe 6908 reason = "size not equal to 0";
14b456f2
AV		 6909 break;
6910
ef1576a1 6911 case UNDEF_SIZE_NOT_2:
6576bffe 6912 reason = "size not equal to 2";
ef1576a1
AV		 6913 break;
6914
6915 case UNDEF_SIZE_NOT_3:
6576bffe 6916 reason = "size not equal to 3";
ef1576a1
AV		 6917 break;
6918
6919 case UNDEF_NOT_UNS_SIZE_0:
6576bffe 6920 reason = "not unsigned and size = zero";
ef1576a1
AV		 6921 break;
6922
6923 case UNDEF_NOT_UNS_SIZE_1:
6576bffe 6924 reason = "not unsigned and size = one";
ef1576a1
AV		 6925 break;
6926
6927 case UNDEF_NOT_UNSIGNED:
6576bffe 6928 reason = "not unsigned";
ef1576a1
AV		 6929 break;
6930
bf0b396d 6931 case UNDEF_VCVT_IMM6:
6576bffe 6932 reason = "invalid imm6";
bf0b396d
AV		 6933 break;
6934
6935 case UNDEF_VCVT_FSI_IMM6:
6576bffe 6936 reason = "fsi = 0 and invalid imm6";
bf0b396d
AV		 6937 break;
6938
c507f10b 6939 case UNDEF_BAD_OP1_OP2:
6576bffe 6940 reason = "bad size with op2 = 2 and op1 = 0 or 1";
c507f10b
AV		 6941 break;
6942
6943 case UNDEF_BAD_U_OP1_OP2:
6576bffe 6944 reason = "unsigned with op2 = 0 and op1 = 0 or 1";
c507f10b
AV		 6945 break;
6946
6947 case UNDEF_OP_0_BAD_CMODE:
6576bffe 6948 reason = "op field equal 0 and bad cmode";
c507f10b
AV		 6949 break;
6950
d3b63143 6951 case UNDEF_XCHG_UNS:
6576bffe 6952 reason = "exchange and unsigned together";
d3b63143
AV		 6953 break;
6954
73cd51e5 6955 case UNDEF_NONE:
6576bffe 6956 reason = "";
73cd51e5
AV		 6957 break;
6958 }
6959
6576bffe 6960 func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
73cd51e5
AV		 6961}
6962
6963static void
6964print_mve_unpredictable (struct disassemble_info *info,
6965 enum mve_unpredictable unpredict_code)
6966{
6967 void *stream = info->stream;
6576bffe 6968 fprintf_styled_ftype func = info->fprintf_styled_func;
2df82cd4
AB		 6969 /* Initialize REASON to avoid compiler warning about uninitialized
6970 usage, though such usage should be impossible. */
6971 const char *reason = "??";
73cd51e5
AV		 6972
6973 switch (unpredict_code)
6974 {
6975 case UNPRED_IT_BLOCK:
6576bffe 6976 reason = "mve instruction in it block";
73cd51e5
AV		 6977 break;
6978
143275ea 6979 case UNPRED_FCA_0_FCB_1:
6576bffe 6980 reason = "condition bits, fca = 0 and fcb = 1";
143275ea
AV		 6981 break;
6982
6983 case UNPRED_R13:
6576bffe 6984 reason = "use of r13 (sp)";
143275ea
AV		 6985 break;
6986
9743db03 6987 case UNPRED_R15:
6576bffe 6988 reason = "use of r15 (pc)";
9743db03
AV		 6989 break;
6990
04d54ace 6991 case UNPRED_Q_GT_4:
6576bffe 6992 reason = "start register block > r4";
04d54ace
AV		 6993 break;
6994
6995 case UNPRED_Q_GT_6:
6576bffe 6996 reason = "start register block > r6";
04d54ace
AV		 6997 break;
6998
6999 case UNPRED_R13_AND_WB:
6576bffe 7000 reason = "use of r13 and write back";
04d54ace
AV		 7001 break;
7002
ef1576a1 7003 case UNPRED_Q_REGS_EQUAL:
6576bffe 7004 reason = "same vector register used for destination and other operand";
ef1576a1
AV		 7005 break;
7006
7007 case UNPRED_OS:
6576bffe 7008 reason = "use of offset scaled";
ef1576a1
AV		 7009 break;
7010
bf0b396d 7011 case UNPRED_GP_REGS_EQUAL:
6576bffe 7012 reason = "same general-purpose register used for both operands";
bf0b396d
AV		 7013 break;
7014
c507f10b 7015 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6576bffe 7016 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7017 break;
7018
7019 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6576bffe 7020 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7021 break;
7022
73cd51e5 7023 case UNPRED_NONE:
6576bffe 7024 reason = "";
73cd51e5
AV		 7025 break;
7026 }
6576bffe
AB		 7027
7028 func (stream, dis_style_comment_start, "%s: %s",
7029 UNPREDICTABLE_INSTRUCTION, reason);
73cd51e5
AV		 7030}
7031
04d54ace
AV		 7032/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7033
7034static void
7035print_mve_register_blocks (struct disassemble_info *info,
7036 unsigned long given,
7037 enum mve_instructions matched_insn)
7038{
7039 void *stream = info->stream;
6576bffe 7040 fprintf_styled_ftype func = info->fprintf_styled_func;
04d54ace
AV		 7041
7042 unsigned long q_reg_start = arm_decode_field_multiple (given,
7043 13, 15,
7044 22, 22);
7045 switch (matched_insn)
7046 {
7047 case MVE_VLD2:
7048 case MVE_VST2:
7049 if (q_reg_start <= 6)
6576bffe
AB		 7050 {
7051 func (stream, dis_style_text, "{");
7052 func (stream, dis_style_register, "q%ld", q_reg_start);
7053 func (stream, dis_style_text, ", ");
7054 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7055 func (stream, dis_style_text, "}");
7056 }
04d54ace 7057 else
6576bffe 7058 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7059 break;
7060
7061 case MVE_VLD4:
7062 case MVE_VST4:
7063 if (q_reg_start <= 4)
6576bffe
AB		 7064 {
7065 func (stream, dis_style_text, "{");
7066 func (stream, dis_style_register, "q%ld", q_reg_start);
7067 func (stream, dis_style_text, ", ");
7068 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7069 func (stream, dis_style_text, ", ");
7070 func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7071 func (stream, dis_style_text, ", ");
7072 func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7073 func (stream, dis_style_text, "}");
7074 }
04d54ace 7075 else
6576bffe 7076 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7077 break;
7078
7079 default:
7080 break;
7081 }
7082}
7083
bf0b396d
AV		 7084static void
7085print_mve_rounding_mode (struct disassemble_info *info,
7086 unsigned long given,
7087 enum mve_instructions matched_insn)
7088{
7089 void *stream = info->stream;
6576bffe 7090 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7091
7092 switch (matched_insn)
7093 {
7094 case MVE_VCVT_FROM_FP_TO_INT:
7095 {
7096 switch (arm_decode_field (given, 8, 9))
7097 {
7098 case 0:
6576bffe 7099 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7100 break;
7101
7102 case 1:
6576bffe 7103 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7104 break;
7105
7106 case 2:
6576bffe 7107 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7108 break;
7109
7110 case 3:
6576bffe 7111 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7112 break;
7113
7114 default:
7115 break;
7116 }
7117 }
7118 break;
7119
7120 case MVE_VRINT_FP:
7121 {
7122 switch (arm_decode_field (given, 7, 9))
7123 {
7124 case 0:
6576bffe 7125 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7126 break;
7127
7128 case 1:
6576bffe 7129 func (stream, dis_style_mnemonic, "x");
bf0b396d
AV		 7130 break;
7131
7132 case 2:
6576bffe 7133 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7134 break;
7135
7136 case 3:
6576bffe 7137 func (stream, dis_style_mnemonic, "z");
bf0b396d
AV		 7138 break;
7139
7140 case 5:
6576bffe 7141 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7142 break;
7143
7144 case 7:
6576bffe 7145 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7146
7147 case 4:
7148 case 6:
7149 default:
7150 break;
7151 }
7152 }
7153 break;
7154
7155 default:
7156 break;
7157 }
7158}
7159
7160static void
7161print_mve_vcvt_size (struct disassemble_info *info,
7162 unsigned long given,
7163 enum mve_instructions matched_insn)
7164{
7165 unsigned long mode = 0;
7166 void *stream = info->stream;
6576bffe 7167 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7168
7169 switch (matched_insn)
7170 {
7171 case MVE_VCVT_FP_FIX_VEC:
7172 {
7173 mode = (((given & 0x200) >> 7)
7174 | ((given & 0x10000000) >> 27)
7175 | ((given & 0x100) >> 8));
7176
7177 switch (mode)
7178 {
7179 case 0:
6576bffe 7180 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7181 break;
7182
7183 case 1:
6576bffe 7184 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7185 break;
7186
7187 case 2:
6576bffe 7188 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7189 break;
7190
7191 case 3:
6576bffe 7192 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7193 break;
7194
7195 case 4:
6576bffe 7196 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7197 break;
7198
7199 case 5:
6576bffe 7200 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7201 break;
7202
7203 case 6:
6576bffe 7204 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7205 break;
7206
7207 case 7:
6576bffe 7208 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7209 break;
7210
7211 default:
7212 break;
7213 }
7214 break;
7215 }
7216 case MVE_VCVT_BETWEEN_FP_INT:
7217 {
7218 unsigned long size = arm_decode_field (given, 18, 19);
7219 unsigned long op = arm_decode_field (given, 7, 8);
7220
7221 if (size == 1)
7222 {
7223 switch (op)
7224 {
7225 case 0:
6576bffe 7226 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7227 break;
7228
7229 case 1:
6576bffe 7230 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7231 break;
7232
7233 case 2:
6576bffe 7234 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7235 break;
7236
7237 case 3:
6576bffe 7238 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7239 break;
7240
7241 default:
7242 break;
7243 }
7244 }
7245 else if (size == 2)
7246 {
7247 switch (op)
7248 {
7249 case 0:
6576bffe 7250 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7251 break;
7252
7253 case 1:
6576bffe 7254 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7255 break;
7256
7257 case 2:
6576bffe 7258 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7259 break;
7260
7261 case 3:
6576bffe 7262 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7263 break;
7264 }
7265 }
7266 }
7267 break;
7268
7269 case MVE_VCVT_FP_HALF_FP:
7270 {
7271 unsigned long op = arm_decode_field (given, 28, 28);
7272 if (op == 0)
6576bffe 7273 func (stream, dis_style_mnemonic, "f16.f32");
bf0b396d 7274 else if (op == 1)
6576bffe 7275 func (stream, dis_style_mnemonic, "f32.f16");
bf0b396d
AV		 7276 }
7277 break;
7278
7279 case MVE_VCVT_FROM_FP_TO_INT:
7280 {
7281 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7282
7283 switch (size)
7284 {
7285 case 2:
6576bffe 7286 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7287 break;
7288
7289 case 3:
6576bffe 7290 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7291 break;
7292
7293 case 4:
6576bffe 7294 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7295 break;
7296
7297 case 5:
6576bffe 7298 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7299 break;
7300
7301 default:
7302 break;
7303 }
7304 }
7305 break;
7306
7307 default:
7308 break;
7309 }
7310}
7311
897b9bbc
AV		 7312static void
7313print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7314 unsigned long rot_width)
7315{
7316 void *stream = info->stream;
6576bffe 7317 fprintf_styled_ftype func = info->fprintf_styled_func;
897b9bbc
AV		 7318
7319 if (rot_width == 1)
7320 {
7321 switch (rot)
7322 {
7323 case 0:
6576bffe 7324 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7325 break;
7326 case 1:
6576bffe 7327 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7328 break;
7329 default:
7330 break;
7331 }
7332 }
7333 else if (rot_width == 2)
7334 {
7335 switch (rot)
7336 {
7337 case 0:
6576bffe 7338 func (stream, dis_style_immediate, "0");
897b9bbc
AV		 7339 break;
7340 case 1:
6576bffe 7341 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7342 break;
7343 case 2:
6576bffe 7344 func (stream, dis_style_immediate, "180");
897b9bbc
AV		 7345 break;
7346 case 3:
6576bffe 7347 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7348 break;
7349 default:
7350 break;
7351 }
7352 }
7353}
7354
143275ea
AV		 7355static void
7356print_instruction_predicate (struct disassemble_info *info)
7357{
7358 void *stream = info->stream;
6576bffe 7359 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7360
7361 if (vpt_block_state.next_pred_state == PRED_THEN)
6576bffe 7362 func (stream, dis_style_mnemonic, "t");
143275ea 7363 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6576bffe 7364 func (stream, dis_style_mnemonic, "e");
143275ea
AV		 7365}
7366
7367static void
7368print_mve_size (struct disassemble_info *info,
7369 unsigned long size,
7370 enum mve_instructions matched_insn)
7371{
7372 void *stream = info->stream;
6576bffe 7373 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7374
7375 switch (matched_insn)
7376 {
66dcaa5d
AV		 7377 case MVE_VABAV:
7378 case MVE_VABD_VEC:
7379 case MVE_VABS_FP:
7380 case MVE_VABS_VEC:
7381 case MVE_VADD_VEC_T1:
7382 case MVE_VADD_VEC_T2:
d3b63143 7383 case MVE_VADDV:
e523f101 7384 case MVE_VBRSR:
897b9bbc 7385 case MVE_VCADD_VEC:
e523f101
AV		 7386 case MVE_VCLS:
7387 case MVE_VCLZ:
143275ea
AV		 7388 case MVE_VCMP_VEC_T1:
7389 case MVE_VCMP_VEC_T2:
7390 case MVE_VCMP_VEC_T3:
7391 case MVE_VCMP_VEC_T4:
7392 case MVE_VCMP_VEC_T5:
7393 case MVE_VCMP_VEC_T6:
e523f101 7394 case MVE_VCTP:
1c8f2df8
AV		 7395 case MVE_VDDUP:
7396 case MVE_VDWDUP:
9743db03
AV		 7397 case MVE_VHADD_T1:
7398 case MVE_VHADD_T2:
897b9bbc 7399 case MVE_VHCADD:
9743db03
AV		 7400 case MVE_VHSUB_T1:
7401 case MVE_VHSUB_T2:
1c8f2df8
AV		 7402 case MVE_VIDUP:
7403 case MVE_VIWDUP:
04d54ace
AV		 7404 case MVE_VLD2:
7405 case MVE_VLD4:
ef1576a1
AV		 7406 case MVE_VLDRB_GATHER_T1:
7407 case MVE_VLDRH_GATHER_T2:
7408 case MVE_VLDRW_GATHER_T3:
7409 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7410 case MVE_VLDRB_T1:
7411 case MVE_VLDRH_T2:
56858bea
AV		 7412 case MVE_VMAX:
7413 case MVE_VMAXA:
7414 case MVE_VMAXV:
7415 case MVE_VMAXAV:
7416 case MVE_VMIN:
7417 case MVE_VMINA:
7418 case MVE_VMINV:
7419 case MVE_VMINAV:
7420 case MVE_VMLA:
d3b63143 7421 case MVE_VMLAS:
f49bb598
AV		 7422 case MVE_VMUL_VEC_T1:
7423 case MVE_VMUL_VEC_T2:
7424 case MVE_VMULH:
7425 case MVE_VRMULH:
7426 case MVE_VMULL_INT:
7427 case MVE_VNEG_FP:
7428 case MVE_VNEG_VEC:
143275ea
AV		 7429 case MVE_VPT_VEC_T1:
7430 case MVE_VPT_VEC_T2:
7431 case MVE_VPT_VEC_T3:
7432 case MVE_VPT_VEC_T4:
7433 case MVE_VPT_VEC_T5:
7434 case MVE_VPT_VEC_T6:
14b456f2
AV		 7435 case MVE_VQABS:
7436 case MVE_VQADD_T1:
7437 case MVE_VQADD_T2:
d3b63143
AV		 7438 case MVE_VQDMLADH:
7439 case MVE_VQRDMLADH:
7440 case MVE_VQDMLAH:
7441 case MVE_VQRDMLAH:
7442 case MVE_VQDMLASH:
7443 case MVE_VQRDMLASH:
7444 case MVE_VQDMLSDH:
7445 case MVE_VQRDMLSDH:
7446 case MVE_VQDMULH_T1:
7447 case MVE_VQRDMULH_T2:
7448 case MVE_VQDMULH_T3:
7449 case MVE_VQRDMULH_T4:
14b456f2 7450 case MVE_VQNEG:
ed63aa17
AV		 7451 case MVE_VQRSHL_T1:
7452 case MVE_VQRSHL_T2:
7453 case MVE_VQSHL_T1:
7454 case MVE_VQSHL_T4:
14b456f2
AV		 7455 case MVE_VQSUB_T1:
7456 case MVE_VQSUB_T2:
7457 case MVE_VREV32:
7458 case MVE_VREV64:
9743db03 7459 case MVE_VRHADD:
bf0b396d 7460 case MVE_VRINT_FP:
ed63aa17
AV		 7461 case MVE_VRSHL_T1:
7462 case MVE_VRSHL_T2:
7463 case MVE_VSHL_T2:
7464 case MVE_VSHL_T3:
7465 case MVE_VSHLL_T2:
04d54ace
AV		 7466 case MVE_VST2:
7467 case MVE_VST4:
ef1576a1
AV		 7468 case MVE_VSTRB_SCATTER_T1:
7469 case MVE_VSTRH_SCATTER_T2:
7470 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7471 case MVE_VSTRB_T1:
7472 case MVE_VSTRH_T2:
66dcaa5d
AV		 7473 case MVE_VSUB_VEC_T1:
7474 case MVE_VSUB_VEC_T2:
143275ea 7475 if (size <= 3)
6576bffe 7476 func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
143275ea 7477 else
6576bffe 7478 func (stream, dis_style_text, "<undef size>");
143275ea
AV		 7479 break;
7480
66dcaa5d
AV		 7481 case MVE_VABD_FP:
7482 case MVE_VADD_FP_T1:
7483 case MVE_VADD_FP_T2:
7484 case MVE_VSUB_FP_T1:
7485 case MVE_VSUB_FP_T2:
143275ea
AV		 7486 case MVE_VCMP_FP_T1:
7487 case MVE_VCMP_FP_T2:
9743db03
AV		 7488 case MVE_VFMA_FP_SCALAR:
7489 case MVE_VFMA_FP:
7490 case MVE_VFMS_FP:
7491 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7492 case MVE_VMAXNM_FP:
7493 case MVE_VMAXNMA_FP:
7494 case MVE_VMAXNMV_FP:
7495 case MVE_VMAXNMAV_FP:
7496 case MVE_VMINNM_FP:
7497 case MVE_VMINNMA_FP:
7498 case MVE_VMINNMV_FP:
7499 case MVE_VMINNMAV_FP:
f49bb598
AV		 7500 case MVE_VMUL_FP_T1:
7501 case MVE_VMUL_FP_T2:
143275ea
AV		 7502 case MVE_VPT_FP_T1:
7503 case MVE_VPT_FP_T2:
7504 if (size == 0)
6576bffe 7505 func (stream, dis_style_mnemonic, "32");
143275ea 7506 else if (size == 1)
6576bffe 7507 func (stream, dis_style_mnemonic, "16");
143275ea
AV		 7508 break;
7509
897b9bbc
AV		 7510 case MVE_VCADD_FP:
7511 case MVE_VCMLA_FP:
7512 case MVE_VCMUL_FP:
d3b63143
AV		 7513 case MVE_VMLADAV_T1:
7514 case MVE_VMLALDAV:
7515 case MVE_VMLSDAV_T1:
7516 case MVE_VMLSLDAV:
14925797
AV		 7517 case MVE_VMOVN:
7518 case MVE_VQDMULL_T1:
7519 case MVE_VQDMULL_T2:
7520 case MVE_VQMOVN:
7521 case MVE_VQMOVUN:
7522 if (size == 0)
6576bffe 7523 func (stream, dis_style_mnemonic, "16");
14925797 7524 else if (size == 1)
6576bffe 7525 func (stream, dis_style_mnemonic, "32");
14925797
AV		 7526 break;
7527
7528 case MVE_VMOVL:
7529 if (size == 1)
6576bffe 7530 func (stream, dis_style_mnemonic, "8");
14925797 7531 else if (size == 2)
6576bffe 7532 func (stream, dis_style_mnemonic, "16");
14925797
AV		 7533 break;
7534
9743db03
AV		 7535 case MVE_VDUP:
7536 switch (size)
7537 {
7538 case 0:
6576bffe 7539 func (stream, dis_style_mnemonic, "32");
9743db03
AV		 7540 break;
7541 case 1:
6576bffe 7542 func (stream, dis_style_mnemonic, "16");
9743db03
AV		 7543 break;
7544 case 2:
6576bffe 7545 func (stream, dis_style_mnemonic, "8");
9743db03
AV		 7546 break;
7547 default:
7548 break;
7549 }
7550 break;
7551
c507f10b
AV		 7552 case MVE_VMOV_GP_TO_VEC_LANE:
7553 case MVE_VMOV_VEC_LANE_TO_GP:
7554 switch (size)
7555 {
7556 case 0: case 4:
6576bffe 7557 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7558 break;
7559
7560 case 1: case 3:
7561 case 5: case 7:
6576bffe 7562 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7563 break;
7564
7565 case 8: case 9: case 10: case 11:
7566 case 12: case 13: case 14: case 15:
6576bffe 7567 func (stream, dis_style_mnemonic, "8");
c507f10b
AV		 7568 break;
7569
7570 default:
7571 break;
7572 }
7573 break;
7574
7575 case MVE_VMOV_IMM_TO_VEC:
7576 switch (size)
7577 {
7578 case 0: case 4: case 8:
7579 case 12: case 24: case 26:
6576bffe 7580 func (stream, dis_style_mnemonic, "i32");
c507f10b
AV		 7581 break;
7582 case 16: case 20:
6576bffe 7583 func (stream, dis_style_mnemonic, "i16");
c507f10b
AV		 7584 break;
7585 case 28:
6576bffe 7586 func (stream, dis_style_mnemonic, "i8");
c507f10b
AV		 7587 break;
7588 case 29:
6576bffe 7589 func (stream, dis_style_mnemonic, "i64");
c507f10b
AV		 7590 break;
7591 case 30:
6576bffe 7592 func (stream, dis_style_mnemonic, "f32");
c507f10b
AV		 7593 break;
7594 default:
7595 break;
7596 }
7597 break;
7598
14925797
AV		 7599 case MVE_VMULL_POLY:
7600 if (size == 0)
6576bffe 7601 func (stream, dis_style_mnemonic, "p8");
14925797 7602 else if (size == 1)
6576bffe 7603 func (stream, dis_style_mnemonic, "p16");
14925797
AV		 7604 break;
7605
c507f10b
AV		 7606 case MVE_VMVN_IMM:
7607 switch (size)
7608 {
7609 case 0: case 2: case 4:
7610 case 6: case 12: case 13:
6576bffe 7611 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7612 break;
7613
7614 case 8: case 10:
6576bffe 7615 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7616 break;
7617
7618 default:
7619 break;
7620 }
7621 break;
7622
7623 case MVE_VBIC_IMM:
7624 case MVE_VORR_IMM:
7625 switch (size)
7626 {
7627 case 1: case 3:
7628 case 5: case 7:
6576bffe 7629 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7630 break;
7631
7632 case 9: case 11:
6576bffe 7633 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7634 break;
7635
7636 default:
7637 break;
7638 }
7639 break;
7640
ed63aa17
AV		 7641 case MVE_VQSHRN:
7642 case MVE_VQSHRUN:
7643 case MVE_VQRSHRN:
7644 case MVE_VQRSHRUN:
7645 case MVE_VRSHRN:
7646 case MVE_VSHRN:
7647 {
7648 switch (size)
7649 {
7650 case 1:
6576bffe 7651 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7652 break;
7653
7654 case 2: case 3:
6576bffe 7655 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7656 break;
7657
7658 default:
7659 break;
7660 }
7661 }
7662 break;
7663
7664 case MVE_VQSHL_T2:
7665 case MVE_VQSHLU_T3:
7666 case MVE_VRSHR:
7667 case MVE_VSHL_T1:
7668 case MVE_VSHLL_T1:
7669 case MVE_VSHR:
7670 case MVE_VSLI:
7671 case MVE_VSRI:
7672 {
7673 switch (size)
7674 {
7675 case 1:
6576bffe 7676 func (stream, dis_style_mnemonic, "8");
ed63aa17
AV		 7677 break;
7678
7679 case 2: case 3:
6576bffe 7680 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7681 break;
7682
7683 case 4: case 5: case 6: case 7:
6576bffe 7684 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7685 break;
7686
7687 default:
7688 break;
7689 }
7690 }
7691 break;
7692
143275ea
AV		 7693 default:
7694 break;
7695 }
7696}
7697
f9d6cf2e
AC		 7698/* Return true if INSN is a shift insn with an immediate shift amount
7699 which needs decoding as per print_mve_shift_n. */
7700
7701static bool
7702mve_shift_insn_p (enum mve_instructions insn)
7703{
7704 switch (insn)
7705 {
7706 case MVE_VQSHL_T2:
7707 case MVE_VQSHLU_T3:
cd714ac0
AC		 7708 case MVE_VQSHRN:
7709 case MVE_VQSHRUN:
7710 case MVE_VQRSHRN:
7711 case MVE_VQRSHRUN:
f9d6cf2e
AC		 7712 case MVE_VRSHR:
7713 case MVE_VRSHRN:
7714 case MVE_VSHL_T1:
7715 case MVE_VSHLL_T1:
7716 case MVE_VSHR:
7717 case MVE_VSHRN:
7718 case MVE_VSLI:
7719 case MVE_VSRI:
7720 return true;
7721 default:
7722 return false;
7723 }
7724}
7725
ed63aa17
AV		 7726static void
7727print_mve_shift_n (struct disassemble_info *info, long given,
7728 enum mve_instructions matched_insn)
7729{
7730 void *stream = info->stream;
6576bffe 7731 fprintf_styled_ftype func = info->fprintf_styled_func;
ed63aa17
AV		 7732
7733 int startAt0
7734 = matched_insn == MVE_VQSHL_T2
7735 || matched_insn == MVE_VQSHLU_T3
7736 || matched_insn == MVE_VSHL_T1
7737 || matched_insn == MVE_VSHLL_T1
7738 || matched_insn == MVE_VSLI;
7739
7740 unsigned imm6 = (given & 0x3f0000) >> 16;
7741
7742 if (matched_insn == MVE_VSHLL_T1)
7743 imm6 &= 0x1f;
7744
7745 unsigned shiftAmount = 0;
7746 if ((imm6 & 0x20) != 0)
7747 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7748 else if ((imm6 & 0x10) != 0)
7749 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7750 else if ((imm6 & 0x08) != 0)
7751 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7752 else
7753 print_mve_undefined (info, UNDEF_SIZE_0);
7754
6576bffe 7755 func (stream, dis_style_immediate, "%u", shiftAmount);
ed63aa17
AV		 7756}
7757
143275ea
AV		 7758static void
7759print_vec_condition (struct disassemble_info *info, long given,
7760 enum mve_instructions matched_insn)
7761{
7762 void *stream = info->stream;
6576bffe 7763 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7764 long vec_cond = 0;
7765
7766 switch (matched_insn)
7767 {
7768 case MVE_VPT_FP_T1:
7769 case MVE_VCMP_FP_T1:
7770 vec_cond = (((given & 0x1000) >> 10)
7771 | ((given & 1) << 1)
7772 | ((given & 0x0080) >> 7));
6576bffe 7773 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7774 break;
7775
7776 case MVE_VPT_FP_T2:
7777 case MVE_VCMP_FP_T2:
7778 vec_cond = (((given & 0x1000) >> 10)
7779 | ((given & 0x0020) >> 4)
7780 | ((given & 0x0080) >> 7));
6576bffe 7781 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7782 break;
7783
7784 case MVE_VPT_VEC_T1:
7785 case MVE_VCMP_VEC_T1:
7786 vec_cond = (given & 0x0080) >> 7;
6576bffe 7787 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7788 break;
7789
7790 case MVE_VPT_VEC_T2:
7791 case MVE_VCMP_VEC_T2:
7792 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 7793 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7794 break;
7795
7796 case MVE_VPT_VEC_T3:
7797 case MVE_VCMP_VEC_T3:
7798 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6576bffe 7799 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7800 break;
7801
7802 case MVE_VPT_VEC_T4:
7803 case MVE_VCMP_VEC_T4:
7804 vec_cond = (given & 0x0080) >> 7;
6576bffe 7805 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7806 break;
7807
7808 case MVE_VPT_VEC_T5:
7809 case MVE_VCMP_VEC_T5:
7810 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 7811 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7812 break;
7813
7814 case MVE_VPT_VEC_T6:
7815 case MVE_VCMP_VEC_T6:
7816 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6576bffe 7817 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 7818 break;
7819
7820 case MVE_NONE:
7821 case MVE_VPST:
7822 default:
7823 break;
7824 }
7825}
7826
7827#define W_BIT 21
7828#define I_BIT 22
7829#define U_BIT 23
7830#define P_BIT 24
7831
7832#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7833#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7834#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7835#define PRE_BIT_SET (given & (1 << P_BIT))
7836
6576bffe
AB		 7837/* The assembler string for an instruction can include %{X:...%} patterns,
7838 where the 'X' is one of the characters understood by this function.
7839
7840 This function takes the X character, and returns a new style. This new
7841 style will be used by the caller to temporarily change the current base
7842 style. */
7843
7844static enum disassembler_style
7845decode_base_style (const char x)
7846{
7847 switch (x)
7848 {
7849 case 'A': return dis_style_address;
7850 case 'B': return dis_style_sub_mnemonic;
7851 case 'C': return dis_style_comment_start;
7852 case 'D': return dis_style_assembler_directive;
7853 case 'I': return dis_style_immediate;
7854 case 'M': return dis_style_mnemonic;
7855 case 'O': return dis_style_address_offset;
7856 case 'R': return dis_style_register;
7857 case 'S': return dis_style_symbol;
7858 case 'T': return dis_style_text;
7859 default:
7860 abort ();
7861 }
7862}
143275ea 7863
8f06b2d8
PB		 7864/* Print one coprocessor instruction on INFO->STREAM.
7865 Return TRUE if the instuction matched, FALSE if this is not a
7866 recognised coprocessor instruction. */
7867
78933a4a 7868static bool
33593eaf
MM		 7869print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7870 bfd_vma pc,
7871 struct disassemble_info *info,
7872 long given,
78933a4a 7873 bool thumb)
8f06b2d8 7874{
6b0dd094 7875 const struct sopcode32 *insn;
8f06b2d8 7876 void *stream = info->stream;
6576bffe 7877 fprintf_styled_ftype func = info->fprintf_styled_func;
8f06b2d8 7878 unsigned long mask;
2edcd244 7879 unsigned long value = 0;
c22aaad1 7880 int cond;
8afc7bea 7881 int cp_num;
823d2571
TG		 7882 struct arm_private_data *private_data = info->private_data;
7883 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7884 arm_feature_set arm_ext_v8_1m_main =
7885 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
6576bffe
AB		 7886 enum disassembler_style base_style = dis_style_mnemonic;
7887 enum disassembler_style old_base_style = base_style;
823d2571 7888
5b616bef 7889 allowed_arches = private_data->features;
8f06b2d8 7890
33593eaf 7891 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 7892 {
ff4a8d2b 7893 unsigned long u_reg = 16;
78933a4a 7894 bool is_unpredictable = false;
05413229 7895 signed long value_in_comment = 0;
0313a2b8
NC		 7896 const char *c;
7897
823d2571 7898 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7899 switch (insn->value)
7900 {
7901 case SENTINEL_IWMMXT_START:
7902 if (info->mach != bfd_mach_arm_XScale
7903 && info->mach != bfd_mach_arm_iWMMXt
7904 && info->mach != bfd_mach_arm_iWMMXt2)
7905 do
7906 insn++;
823d2571
TG		 7907 while ((! ARM_FEATURE_ZERO (insn->arch))
7908 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7909 continue;
7910
7911 case SENTINEL_IWMMXT_END:
7912 continue;
7913
7914 case SENTINEL_GENERIC_START:
5b616bef 7915 allowed_arches = private_data->features;
05413229
NC		 7916 continue;
7917
7918 default:
7919 abort ();
7920 }
8f06b2d8
PB		 7921
7922 mask = insn->mask;
7923 value = insn->value;
8afc7bea
RL		 7924 cp_num = (given >> 8) & 0xf;
7925
8f06b2d8
PB		 7926 if (thumb)
7927 {
7928 /* The high 4 bits are 0xe for Arm conditional instructions, and
7929 0xe for arm unconditional instructions. The rest of the
7930 encoding is the same. */
7931 mask |= 0xf0000000;
7932 value |= 0xe0000000;
c22aaad1
PB		 7933 if (ifthen_state)
7934 cond = IFTHEN_COND;
7935 else
e2efe87d 7936 cond = COND_UNCOND;
8f06b2d8
PB		 7937 }
7938 else
7939 {
7940 /* Only match unconditional instuctions against unconditional
7941 patterns. */
7942 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7943 {
7944 mask |= 0xf0000000;
e2efe87d 7945 cond = COND_UNCOND;
c22aaad1
PB		 7946 }
7947 else
7948 {
7949 cond = (given >> 28) & 0xf;
7950 if (cond == 0xe)
e2efe87d 7951 cond = COND_UNCOND;
c22aaad1 7952 }
8f06b2d8 7953 }
823d2571 7954
6b0dd094
AV		 7955 if ((insn->isa == T32 && !thumb)
7956 || (insn->isa == ARM && thumb))
7957 continue;
7958
0313a2b8
NC		 7959 if ((given & mask) != value)
7960 continue;
8f06b2d8 7961
823d2571 7962 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7963 continue;
7964
8afc7bea
RL		 7965 if (insn->value == 0xfe000010 /* mcr2 */
7966 || insn->value == 0xfe100010 /* mrc2 */
7967 || insn->value == 0xfc100000 /* ldc2 */
7968 || insn->value == 0xfc000000) /* stc2 */
7969 {
b0c11777 7970 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
78933a4a 7971 is_unpredictable = true;
f08d8ce3
AV		 7972
7973 /* Armv8.1-M Mainline FP & MVE instructions. */
7974 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7975 && !ARM_CPU_IS_ANY (allowed_arches)
7976 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7977 continue;
7978
8afc7bea
RL		 7979 }
7980 else if (insn->value == 0x0e000000 /* cdp */
7981 || insn->value == 0xfe000000 /* cdp2 */
7982 || insn->value == 0x0e000010 /* mcr */
7983 || insn->value == 0x0e100010 /* mrc */
7984 || insn->value == 0x0c100000 /* ldc */
7985 || insn->value == 0x0c000000) /* stc */
7986 {
7987 /* Floating-point instructions. */
b0c11777 7988 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7989 continue;
32c36c3c
AV		 7990
7991 /* Armv8.1-M Mainline FP & MVE instructions. */
7992 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7993 && !ARM_CPU_IS_ANY (allowed_arches)
7994 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7995 continue;
8afc7bea 7996 }
aef6d006
AV		 7997 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7998 || insn->value == 0xec000f80) /* vstr (system register) */
7999 && arm_decode_field (given, 24, 24) == 0
8000 && arm_decode_field (given, 21, 21) == 0)
8001 /* If the P and W bits are both 0 then these encodings match the MVE
8002 VLDR and VSTR instructions, these are in a different table, so we
8003 don't let it match here. */
8004 continue;
8005
0313a2b8
NC		 8006 for (c = insn->assembler; *c; c++)
8007 {
8008 if (*c == '%')
8f06b2d8 8009 {
32c36c3c 8010 const char mod = *++c;
6576bffe 8011
32c36c3c 8012 switch (mod)
8f06b2d8 8013 {
6576bffe
AB		 8014 case '{':
8015 ++c;
8016 if (*c == '\0')
8017 abort ();
8018 old_base_style = base_style;
8019 base_style = decode_base_style (*c);
8020 ++c;
8021 if (*c != ':')
8022 abort ();
8023 break;
8024
8025 case '}':
8026 base_style = old_base_style;
8027 break;
8028
0313a2b8 8029 case '%':
6576bffe 8030 func (stream, base_style, "%%");
0313a2b8
NC		 8031 break;
8032
8033 case 'A':
32c36c3c 8034 case 'K':
05413229 8035 {
79862e45 8036 int rn = (given >> 16) & 0xf;
b0c11777 8037 bfd_vma offset = given & 0xff;
0313a2b8 8038
32c36c3c
AV		 8039 if (mod == 'K')
8040 offset = given & 0x7f;
8041
6576bffe
AB		 8042 func (stream, dis_style_text, "[");
8043 func (stream, dis_style_register, "%s",
8044 arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8045
79862e45
DJ		 8046 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8047 {
8048 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8049 if (cp_num == 9)
8050 /* vldr.16/vstr.16 will shift the address
8051 left by 1 bit only. */
8052 offset = offset * 2;
8053 else
8054 offset = offset * 4;
8055
79862e45
DJ		 8056 if (NEGATIVE_BIT_SET)
8057 offset = - offset;
8058 if (rn != 15)
8059 value_in_comment = offset;
8060 }
8061
c1e26897 8062 if (PRE_BIT_SET)
05413229
NC		 8063 {
8064 if (offset)
6576bffe
AB		 8065 {
8066 func (stream, dis_style_text, ", ");
8067 func (stream, dis_style_immediate, "#%d",
8068 (int) offset);
8069 func (stream, dis_style_text, "]%s",
8070 WRITEBACK_BIT_SET ? "!" : "");
8071 }
26d97720 8072 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8073 {
8074 func (stream, dis_style_text, ", ");
8075 func (stream, dis_style_immediate, "#-0");
8076 func (stream, dis_style_text, "]");
8077 }
05413229 8078 else
6576bffe 8079 func (stream, dis_style_text, "]");
05413229
NC		 8080 }
8081 else
8082 {
6576bffe 8083 func (stream, dis_style_text, "]");
8f06b2d8 8084
c1e26897 8085 if (WRITEBACK_BIT_SET)
05413229
NC		 8086 {
8087 if (offset)
6576bffe
AB		 8088 {
8089 func (stream, dis_style_text, ", ");
8090 func (stream, dis_style_immediate,
8091 "#%d", (int) offset);
8092 }
26d97720 8093 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8094 {
8095 func (stream, dis_style_text, ", ");
8096 func (stream, dis_style_immediate, "#-0");
8097 }
05413229
NC		 8098 }
8099 else
fe56b6ce 8100 {
6576bffe
AB		 8101 func (stream, dis_style_text, ", {");
8102 func (stream, dis_style_immediate, "%s%d",
26d97720 8103 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8104 (int) offset);
6576bffe 8105 func (stream, dis_style_text, "}");
fe56b6ce
NC		 8106 value_in_comment = offset;
8107 }
05413229 8108 }
79862e45
DJ		 8109 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8110 {
6576bffe 8111 func (stream, dis_style_comment_start, "\t@ ");
6844b2c2
MGD		 8112 /* For unaligned PCs, apply off-by-alignment
8113 correction. */
43e65147 8114 info->print_address_func (offset + pc
6844b2c2
MGD		 8115 + info->bytes_per_chunk * 2
8116 - (pc & 3),
dffaa15c 8117 info);
79862e45 8118 }
05413229 8119 }
0313a2b8 8120 break;
8f06b2d8 8121
0313a2b8
NC		 8122 case 'B':
8123 {
8124 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8125 int offset = (given >> 1) & 0x3f;
8126
6576bffe 8127 func (stream, dis_style_text, "{");
0313a2b8 8128 if (offset == 1)
6576bffe 8129 func (stream, dis_style_register, "d%d", regno);
0313a2b8 8130 else if (regno + offset > 32)
6576bffe
AB		 8131 {
8132 func (stream, dis_style_register, "d%d", regno);
8133 func (stream, dis_style_text, "-<overflow reg d%d>",
8134 regno + offset - 1);
8135 }
0313a2b8 8136 else
6576bffe
AB		 8137 {
8138 func (stream, dis_style_register, "d%d", regno);
8139 func (stream, dis_style_text, "-");
8140 func (stream, dis_style_register, "d%d",
8141 regno + offset - 1);
8142 }
8143 func (stream, dis_style_text, "}");
0313a2b8
NC		 8144 }
8145 break;
8f06b2d8 8146
efd6b359
AV		 8147 case 'C':
8148 {
78933a4a 8149 bool single = ((given >> 8) & 1) == 0;
efd6b359
AV		 8150 char reg_prefix = single ? 's' : 'd';
8151 int Dreg = (given >> 22) & 0x1;
8152 int Vdreg = (given >> 12) & 0xf;
8153 int reg = single ? ((Vdreg << 1) | Dreg)
8154 : ((Dreg << 4) | Vdreg);
8155 int num = (given >> (single ? 0 : 1)) & 0x7f;
8156 int maxreg = single ? 31 : 15;
8157 int topreg = reg + num - 1;
8158
6576bffe 8159 func (stream, dis_style_text, "{");
efd6b359 8160 if (!num)
6576bffe
AB		 8161 {
8162 /* Nothing. */
8163 }
efd6b359 8164 else if (num == 1)
6576bffe
AB		 8165 {
8166 func (stream, dis_style_register,
8167 "%c%d", reg_prefix, reg);
8168 func (stream, dis_style_text, ", ");
8169 }
efd6b359 8170 else if (topreg > maxreg)
6576bffe
AB		 8171 {
8172 func (stream, dis_style_register, "%c%d",
8173 reg_prefix, reg);
8174 func (stream, dis_style_text, "-<overflow reg d%d, ",
8175 single ? topreg >> 1 : topreg);
8176 }
efd6b359 8177 else
6576bffe
AB		 8178 {
8179 func (stream, dis_style_register,
8180 "%c%d", reg_prefix, reg);
8181 func (stream, dis_style_text, "-");
8182 func (stream, dis_style_register, "%c%d",
8183 reg_prefix, topreg);
8184 func (stream, dis_style_text, ", ");
8185 }
8186 func (stream, dis_style_register, "VPR");
8187 func (stream, dis_style_text, "}");
efd6b359
AV		 8188 }
8189 break;
8190
e2efe87d
MGD		 8191 case 'u':
8192 if (cond != COND_UNCOND)
78933a4a 8193 is_unpredictable = true;
e2efe87d
MGD		 8194
8195 /* Fall through. */
0313a2b8 8196 case 'c':
b0c11777 8197 if (cond != COND_UNCOND && cp_num == 9)
78933a4a 8198 is_unpredictable = true;
b0c11777 8199
aab2c27d
MM		 8200 /* Fall through. */
8201 case 'b':
6576bffe
AB		 8202 func (stream, dis_style_mnemonic, "%s",
8203 arm_conditional[cond]);
0313a2b8 8204 break;
8f06b2d8 8205
32c36c3c
AV		 8206 case 'J':
8207 {
73cd51e5
AV		 8208 unsigned long regno
8209 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8210
8211 switch (regno)
8212 {
8213 case 0x1:
6576bffe 8214 func (stream, dis_style_register, "FPSCR");
32c36c3c
AV		 8215 break;
8216 case 0x2:
6576bffe 8217 func (stream, dis_style_register, "FPSCR_nzcvqc");
32c36c3c
AV		 8218 break;
8219 case 0xc:
6576bffe 8220 func (stream, dis_style_register, "VPR");
32c36c3c
AV		 8221 break;
8222 case 0xd:
6576bffe 8223 func (stream, dis_style_register, "P0");
32c36c3c
AV		 8224 break;
8225 case 0xe:
6576bffe 8226 func (stream, dis_style_register, "FPCXTNS");
32c36c3c
AV		 8227 break;
8228 case 0xf:
6576bffe 8229 func (stream, dis_style_register, "FPCXTS");
32c36c3c
AV		 8230 break;
8231 default:
6576bffe
AB		 8232 func (stream, dis_style_text, "<invalid reg %lu>",
8233 regno);
32c36c3c
AV		 8234 break;
8235 }
8236 }
8237 break;
8238
0313a2b8
NC		 8239 case '0': case '1': case '2': case '3': case '4':
8240 case '5': case '6': case '7': case '8': case '9':
8241 {
8242 int width;
8f06b2d8 8243
0313a2b8 8244 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8245
0313a2b8
NC		 8246 switch (*c)
8247 {
ff4a8d2b
NC		 8248 case 'R':
8249 if (value == 15)
78933a4a 8250 is_unpredictable = true;
ff4a8d2b 8251 /* Fall through. */
0313a2b8 8252 case 'r':
ff4a8d2b
NC		 8253 if (c[1] == 'u')
8254 {
8255 /* Eat the 'u' character. */
8256 ++ c;
8257
8258 if (u_reg == value)
78933a4a 8259 is_unpredictable = true;
ff4a8d2b
NC		 8260 u_reg = value;
8261 }
4575eafb
AB		 8262 func (stream, dis_style_register, "%s",
8263 arm_regnames[value]);
0313a2b8 8264 break;
c28eeff2
SN		 8265 case 'V':
8266 if (given & (1 << 6))
8267 goto Q;
8268 /* FALLTHROUGH */
0313a2b8 8269 case 'D':
6576bffe 8270 func (stream, dis_style_register, "d%ld", value);
0313a2b8
NC		 8271 break;
8272 case 'Q':
c28eeff2 8273 Q:
0313a2b8 8274 if (value & 1)
6576bffe
AB		 8275 func (stream, dis_style_text,
8276 "<illegal reg q%ld.5>", value >> 1);
0313a2b8 8277 else
6576bffe
AB		 8278 func (stream, dis_style_register,
8279 "q%ld", value >> 1);
0313a2b8
NC		 8280 break;
8281 case 'd':
6576bffe 8282 func (stream, base_style, "%ld", value);
05413229 8283 value_in_comment = value;
0313a2b8 8284 break;
6f1c2142
AM		 8285 case 'E':
8286 {
8287 /* Converts immediate 8 bit back to float value. */
8288 unsigned floatVal = (value & 0x80) << 24
8289 | (value & 0x3F) << 19
8290 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8291
8292 /* Quarter float have a maximum value of 31.0.
8293 Get floating point value multiplied by 1e7.
8294 The maximum value stays in limit of a 32-bit int. */
8295 unsigned decVal =
8296 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8297 (16 + (value & 0xF));
8298
8299 if (!(decVal % 1000000))
6576bffe
AB		 8300 {
8301 func (stream, dis_style_immediate, "%ld", value);
8302 func (stream, dis_style_comment_start,
8303 "\t@ 0x%08x %c%u.%01u",
8304 floatVal, value & 0x80 ? '-' : ' ',
8305 decVal / 10000000,
8306 decVal % 10000000 / 1000000);
8307 }
6f1c2142 8308 else if (!(decVal % 10000))
6576bffe
AB		 8309 {
8310 func (stream, dis_style_immediate, "%ld", value);
8311 func (stream, dis_style_comment_start,
8312 "\t@ 0x%08x %c%u.%03u",
8313 floatVal, value & 0x80 ? '-' : ' ',
8314 decVal / 10000000,
8315 decVal % 10000000 / 10000);
8316 }
6f1c2142 8317 else
6576bffe
AB		 8318 {
8319 func (stream, dis_style_immediate, "%ld", value);
8320 func (stream, dis_style_comment_start,
8321 "\t@ 0x%08x %c%u.%07u",
8322 floatVal, value & 0x80 ? '-' : ' ',
8323 decVal / 10000000, decVal % 10000000);
8324 }
6f1c2142
AM		 8325 break;
8326 }
0313a2b8
NC		 8327 case 'k':
8328 {
8329 int from = (given & (1 << 7)) ? 32 : 16;
6576bffe
AB		 8330 func (stream, dis_style_immediate, "%ld",
8331 from - value);
0313a2b8
NC		 8332 }
8333 break;
8f06b2d8 8334
0313a2b8
NC		 8335 case 'w':
8336 if (width == 2)
6576bffe
AB		 8337 func (stream, dis_style_mnemonic, "%s",
8338 iwmmxt_wwnames[value]);
0313a2b8 8339 else
6576bffe
AB		 8340 func (stream, dis_style_mnemonic, "%s",
8341 iwmmxt_wwssnames[value]);
0313a2b8 8342 break;
4146fd53 8343
0313a2b8 8344 case 'g':
6576bffe
AB		 8345 func (stream, dis_style_register, "%s",
8346 iwmmxt_regnames[value]);
0313a2b8
NC		 8347 break;
8348 case 'G':
6576bffe
AB		 8349 func (stream, dis_style_register, "%s",
8350 iwmmxt_cregnames[value]);
16980d0b 8351 break;
8f06b2d8 8352
0313a2b8 8353 case 'x':
6576bffe
AB		 8354 func (stream, dis_style_immediate, "0x%lx",
8355 (value & 0xffffffffUL));
0313a2b8 8356 break;
8f06b2d8 8357
33399f07
MGD		 8358 case 'c':
8359 switch (value)
8360 {
8361 case 0:
6576bffe 8362 func (stream, dis_style_mnemonic, "eq");
33399f07
MGD		 8363 break;
8364
8365 case 1:
6576bffe 8366 func (stream, dis_style_mnemonic, "vs");
33399f07
MGD		 8367 break;
8368
8369 case 2:
6576bffe 8370 func (stream, dis_style_mnemonic, "ge");
33399f07
MGD		 8371 break;
8372
8373 case 3:
6576bffe 8374 func (stream, dis_style_mnemonic, "gt");
33399f07
MGD		 8375 break;
8376
8377 default:
6576bffe 8378 func (stream, dis_style_text, "??");
33399f07
MGD		 8379 break;
8380 }
8381 break;
8382
0313a2b8
NC		 8383 case '`':
8384 c++;
8385 if (value == 0)
6576bffe 8386 func (stream, dis_style_mnemonic, "%c", *c);
0313a2b8
NC		 8387 break;
8388 case '\'':
8389 c++;
8390 if (value == ((1ul << width) - 1))
6576bffe 8391 func (stream, base_style, "%c", *c);
0313a2b8
NC		 8392 break;
8393 case '?':
6576bffe
AB		 8394 func (stream, base_style, "%c",
8395 c[(1 << width) - (int) value]);
0313a2b8
NC		 8396 c += 1 << width;
8397 break;
8398 default:
8399 abort ();
8400 }
dffaa15c
AM		 8401 }
8402 break;
0313a2b8 8403
dffaa15c
AM		 8404 case 'y':
8405 case 'z':
8406 {
8407 int single = *c++ == 'y';
8408 int regno;
8f06b2d8 8409
dffaa15c
AM		 8410 switch (*c)
8411 {
8412 case '4': /* Sm pair */
8413 case '0': /* Sm, Dm */
8414 regno = given & 0x0000000f;
8415 if (single)
8416 {
8417 regno <<= 1;
8418 regno += (given >> 5) & 1;
8419 }
8420 else
8421 regno += ((given >> 5) & 1) << 4;
8422 break;
8f06b2d8 8423
dffaa15c
AM		 8424 case '1': /* Sd, Dd */
8425 regno = (given >> 12) & 0x0000000f;
8426 if (single)
8427 {
8428 regno <<= 1;
8429 regno += (given >> 22) & 1;
8430 }
8431 else
8432 regno += ((given >> 22) & 1) << 4;
8433 break;
7df76b80 8434
dffaa15c
AM		 8435 case '2': /* Sn, Dn */
8436 regno = (given >> 16) & 0x0000000f;
8437 if (single)
8438 {
8439 regno <<= 1;
8440 regno += (given >> 7) & 1;
8441 }
8442 else
8443 regno += ((given >> 7) & 1) << 4;
8444 break;
a7f8487e 8445
dffaa15c 8446 case '3': /* List */
6576bffe 8447 func (stream, dis_style_text, "{");
dffaa15c
AM		 8448 regno = (given >> 12) & 0x0000000f;
8449 if (single)
8450 {
8451 regno <<= 1;
8452 regno += (given >> 22) & 1;
8453 }
8454 else
8455 regno += ((given >> 22) & 1) << 4;
8456 break;
a7f8487e 8457
dffaa15c
AM		 8458 default:
8459 abort ();
8460 }
0313a2b8 8461
6576bffe
AB		 8462 func (stream, dis_style_register, "%c%d",
8463 single ? 's' : 'd', regno);
a7f8487e 8464
dffaa15c
AM		 8465 if (*c == '3')
8466 {
8467 int count = given & 0xff;
b34976b6 8468
dffaa15c
AM		 8469 if (single == 0)
8470 count >>= 1;
0313a2b8 8471
dffaa15c
AM		 8472 if (--count)
8473 {
6576bffe
AB		 8474 func (stream, dis_style_text, "-");
8475 func (stream, dis_style_register, "%c%d",
dffaa15c
AM		 8476 single ? 's' : 'd',
8477 regno + count);
8478 }
0313a2b8 8479
6576bffe 8480 func (stream, dis_style_text, "}");
0313a2b8 8481 }
dffaa15c 8482 else if (*c == '4')
6576bffe
AB		 8483 {
8484 func (stream, dis_style_text, ", ");
8485 func (stream, dis_style_register, "%c%d",
8486 single ? 's' : 'd', regno + 1);
8487 }
dffaa15c
AM		 8488 }
8489 break;
b34976b6 8490
dffaa15c
AM		 8491 case 'L':
8492 switch (given & 0x00400100)
0313a2b8 8493 {
6576bffe
AB		 8494 case 0x00000000:
8495 func (stream, dis_style_mnemonic, "b");
8496 break;
8497 case 0x00400000:
8498 func (stream, dis_style_mnemonic, "h");
8499 break;
8500 case 0x00000100:
8501 func (stream, dis_style_mnemonic, "w");
8502 break;
8503 case 0x00400100:
8504 func (stream, dis_style_mnemonic, "d");
8505 break;
dffaa15c
AM		 8506 default:
8507 break;
0313a2b8 8508 }
dffaa15c 8509 break;
2d447fca 8510
dffaa15c
AM		 8511 case 'Z':
8512 {
8513 /* given (20, 23) | given (0, 3) */
8514 value = ((given >> 16) & 0xf0) | (given & 0xf);
6576bffe 8515 func (stream, dis_style_immediate, "%d", (int) value);
dffaa15c
AM		 8516 }
8517 break;
0313a2b8 8518
dffaa15c
AM		 8519 case 'l':
8520 /* This is like the 'A' operator, except that if
8521 the width field "M" is zero, then the offset is
8522 *not* multiplied by four. */
8523 {
8524 int offset = given & 0xff;
8525 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8526
6576bffe
AB		 8527 func (stream, dis_style_text, "[");
8528 func (stream, dis_style_register, "%s",
8529 arm_regnames [(given >> 16) & 0xf]);
05413229 8530
dffaa15c
AM		 8531 if (multiplier > 1)
8532 {
8533 value_in_comment = offset * multiplier;
8534 if (NEGATIVE_BIT_SET)
8535 value_in_comment = - value_in_comment;
8536 }
0313a2b8 8537
dffaa15c
AM		 8538 if (offset)
8539 {
8540 if (PRE_BIT_SET)
6576bffe
AB		 8541 {
8542 func (stream, dis_style_text, ", ");
8543 func (stream, dis_style_immediate, "#%s%d",
8544 NEGATIVE_BIT_SET ? "-" : "",
8545 offset * multiplier);
8546 func (stream, dis_style_text, "]%s",
8547 WRITEBACK_BIT_SET ? "!" : "");
8548 }
dffaa15c 8549 else
6576bffe
AB		 8550 {
8551 func (stream, dis_style_text, "], ");
8552 func (stream, dis_style_immediate, "#%s%d",
8553 NEGATIVE_BIT_SET ? "-" : "",
8554 offset * multiplier);
8555 }
dffaa15c
AM		 8556 }
8557 else
6576bffe 8558 func (stream, dis_style_text, "]");
dffaa15c
AM		 8559 }
8560 break;
2d447fca 8561
dffaa15c
AM		 8562 case 'r':
8563 {
8564 int imm4 = (given >> 4) & 0xf;
8565 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8566 int ubit = ! NEGATIVE_BIT_SET;
8567 const char *rm = arm_regnames [given & 0xf];
8568 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8569
dffaa15c
AM		 8570 switch (puw_bits)
8571 {
8572 case 1:
8573 case 3:
6576bffe
AB		 8574 func (stream, dis_style_text, "[");
8575 func (stream, dis_style_register, "%s", rn);
8576 func (stream, dis_style_text, "], ");
8577 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8578 func (stream, dis_style_register, "%s", rm);
dffaa15c 8579 if (imm4)
6576bffe
AB		 8580 {
8581 func (stream, dis_style_text, ", ");
8582 func (stream, dis_style_sub_mnemonic, "lsl ");
8583 func (stream, dis_style_immediate, "#%d", imm4);
8584 }
dffaa15c 8585 break;
0313a2b8 8586
dffaa15c
AM		 8587 case 4:
8588 case 5:
8589 case 6:
8590 case 7:
6576bffe
AB		 8591 func (stream, dis_style_text, "[");
8592 func (stream, dis_style_register, "%s", rn);
8593 func (stream, dis_style_text, ", ");
8594 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8595 func (stream, dis_style_register, "%s", rm);
dffaa15c 8596 if (imm4 > 0)
6576bffe
AB		 8597 {
8598 func (stream, dis_style_text, ", ");
8599 func (stream, dis_style_sub_mnemonic, "lsl ");
8600 func (stream, dis_style_immediate, "#%d", imm4);
8601 }
8602 func (stream, dis_style_text, "]");
dffaa15c 8603 if (puw_bits == 5 || puw_bits == 7)
6576bffe 8604 func (stream, dis_style_text, "!");
dffaa15c 8605 break;
2d447fca 8606
dffaa15c 8607 default:
6576bffe 8608 func (stream, dis_style_text, "INVALID");
dffaa15c
AM		 8609 }
8610 }
8611 break;
0313a2b8 8612
dffaa15c
AM		 8613 case 'i':
8614 {
8615 long imm5;
8616 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
6576bffe
AB		 8617 func (stream, dis_style_immediate, "%ld",
8618 (imm5 == 0) ? 32 : imm5);
0313a2b8 8619 }
dffaa15c
AM		 8620 break;
8621
8622 default:
8623 abort ();
252b5132 8624 }
252b5132 8625 }
0313a2b8 8626 else
6576bffe
AB		 8627 {
8628 if (*c == '@')
8629 base_style = dis_style_comment_start;
8630
8631 if (*c == '\t')
8632 base_style = dis_style_text;
8633
8634 func (stream, base_style, "%c", *c);
8635 }
252b5132 8636 }
05413229
NC		 8637
8638 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 8639 func (stream, dis_style_comment_start, "\t@ 0x%lx",
8640 (value_in_comment & 0xffffffffUL));
05413229 8641
ff4a8d2b 8642 if (is_unpredictable)
6576bffe 8643 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8644
78933a4a 8645 return true;
252b5132 8646 }
78933a4a 8647 return false;
252b5132
RH		 8648}
8649
78933a4a 8650static bool
33593eaf
MM		 8651print_insn_coprocessor (bfd_vma pc,
8652 struct disassemble_info *info,
8653 long given,
78933a4a 8654 bool thumb)
33593eaf
MM		 8655{
8656 return print_insn_coprocessor_1 (coprocessor_opcodes,
8657 pc, info, given, thumb);
8658}
8659
78933a4a 8660static bool
33593eaf
MM		 8661print_insn_generic_coprocessor (bfd_vma pc,
8662 struct disassemble_info *info,
8663 long given,
78933a4a 8664 bool thumb)
33593eaf
MM		 8665{
8666 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8667 pc, info, given, thumb);
8668}
8669
05413229
NC		 8670/* Decodes and prints ARM addressing modes. Returns the offset
8671 used in the address, if any, if it is worthwhile printing the
8672 offset as a hexadecimal value in a comment at the end of the
8673 line of disassembly. */
8674
8675static signed long
62b3e311
PB		 8676print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8677{
8678 void *stream = info->stream;
6576bffe 8679 fprintf_styled_ftype func = info->fprintf_styled_func;
f8b960bc 8680 bfd_vma offset = 0;
62b3e311
PB		 8681
8682 if (((given & 0x000f0000) == 0x000f0000)
8683 && ((given & 0x02000000) == 0))
8684 {
05413229 8685 offset = given & 0xfff;
62b3e311 8686
6576bffe
AB		 8687 func (stream, dis_style_text, "[");
8688 func (stream, dis_style_register, "pc");
62b3e311 8689
c1e26897 8690 if (PRE_BIT_SET)
62b3e311 8691 {
26d97720
NS		 8692 /* Pre-indexed. Elide offset of positive zero when
8693 non-writeback. */
8694 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 8695 {
8696 func (stream, dis_style_text, ", ");
8697 func (stream, dis_style_immediate, "#%s%d",
8698 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8699 }
26d97720
NS		 8700
8701 if (NEGATIVE_BIT_SET)
8702 offset = -offset;
62b3e311
PB		 8703
8704 offset += pc + 8;
8705
8706 /* Cope with the possibility of write-back
8707 being used. Probably a very dangerous thing
8708 for the programmer to do, but who are we to
8709 argue ? */
6576bffe 8710 func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8711 }
c1e26897 8712 else /* Post indexed. */
62b3e311 8713 {
6576bffe
AB		 8714 func (stream, dis_style_text, "], ");
8715 func (stream, dis_style_immediate, "#%s%d",
8716 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8717
c1e26897 8718 /* Ie ignore the offset. */
62b3e311
PB		 8719 offset = pc + 8;
8720 }
8721
6576bffe 8722 func (stream, dis_style_comment_start, "\t@ ");
62b3e311 8723 info->print_address_func (offset, info);
05413229 8724 offset = 0;
62b3e311
PB		 8725 }
8726 else
8727 {
6576bffe
AB		 8728 func (stream, dis_style_text, "[");
8729 func (stream, dis_style_register, "%s",
62b3e311 8730 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8731
8732 if (PRE_BIT_SET)
62b3e311
PB		 8733 {
8734 if ((given & 0x02000000) == 0)
8735 {
26d97720 8736 /* Elide offset of positive zero when non-writeback. */
05413229 8737 offset = given & 0xfff;
26d97720 8738 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 8739 {
8740 func (stream, dis_style_text, ", ");
8741 func (stream, dis_style_immediate, "#%s%d",
8742 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8743 }
62b3e311
PB		 8744 }
8745 else
8746 {
6576bffe
AB		 8747 func (stream, dis_style_text, ", %s",
8748 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8749 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8750 }
8751
6576bffe 8752 func (stream, dis_style_text, "]%s",
c1e26897 8753 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8754 }
8755 else
8756 {
8757 if ((given & 0x02000000) == 0)
8758 {
26d97720 8759 /* Always show offset. */
05413229 8760 offset = given & 0xfff;
6576bffe
AB		 8761 func (stream, dis_style_text, "], ");
8762 func (stream, dis_style_immediate, "#%s%d",
d908c8af 8763 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8764 }
8765 else
8766 {
6576bffe 8767 func (stream, dis_style_text, "], %s",
c1e26897 8768 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8769 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8770 }
8771 }
84919466
MR		 8772 if (NEGATIVE_BIT_SET)
8773 offset = -offset;
62b3e311 8774 }
05413229
NC		 8775
8776 return (signed long) offset;
62b3e311
PB		 8777}
8778
4934a27c
MM		 8779
8780/* Print one cde instruction on INFO->STREAM.
8781 Return TRUE if the instuction matched, FALSE if this is not a
8782 recognised cde instruction. */
78933a4a
AM		 8783static bool
8784print_insn_cde (struct disassemble_info *info, long given, bool thumb)
4934a27c
MM		 8785{
8786 const struct cdeopcode32 *insn;
8787 void *stream = info->stream;
6576bffe
AB		 8788 fprintf_styled_ftype func = info->fprintf_styled_func;
8789 enum disassembler_style base_style = dis_style_mnemonic;
8790 enum disassembler_style old_base_style = base_style;
4934a27c
MM		 8791
8792 if (thumb)
8793 {
8794 /* Manually extract the coprocessor code from a known point.
8795 This position is the same across all CDE instructions. */
8796 for (insn = cde_opcodes; insn->assembler; insn++)
8797 {
8798 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8799 uint16_t coproc_mask = 1 << coproc;
8800 if (! (coproc_mask & cde_coprocs))
8801 continue;
8802
8803 if ((given & insn->mask) == insn->value)
8804 {
78933a4a 8805 bool is_unpredictable = false;
4934a27c
MM		 8806 const char *c;
8807
8808 for (c = insn->assembler; *c; c++)
8809 {
8810 if (*c == '%')
8811 {
8812 switch (*++c)
8813 {
6576bffe
AB		 8814 case '{':
8815 ++c;
8816 if (*c == '\0')
8817 abort ();
8818 old_base_style = base_style;
8819 base_style = decode_base_style (*c);
8820 ++c;
8821 if (*c != ':')
8822 abort ();
8823 break;
8824
8825 case '}':
8826 base_style = old_base_style;
8827 break;
8828
4934a27c 8829 case '%':
6576bffe 8830 func (stream, base_style, "%%");
4934a27c
MM		 8831 break;
8832
8833 case '0': case '1': case '2': case '3': case '4':
8834 case '5': case '6': case '7': case '8': case '9':
8835 {
8836 int width;
8837 unsigned long value;
8838
8839 c = arm_decode_bitfield (c, given, &value, &width);
8840
8841 switch (*c)
8842 {
8843 case 'S':
8844 if (value > 10)
78933a4a 8845 is_unpredictable = true;
4934a27c
MM		 8846 /* Fall through. */
8847 case 'R':
8848 if (value == 13)
78933a4a 8849 is_unpredictable = true;
4934a27c
MM		 8850 /* Fall through. */
8851 case 'r':
6576bffe
AB		 8852 func (stream, dis_style_register, "%s",
8853 arm_regnames[value]);
4934a27c
MM		 8854 break;
8855
8856 case 'n':
8857 if (value == 15)
6576bffe 8858 func (stream, dis_style_register, "%s", "APSR_nzcv");
4934a27c 8859 else
6576bffe
AB		 8860 func (stream, dis_style_register, "%s",
8861 arm_regnames[value]);
4934a27c
MM		 8862 break;
8863
8864 case 'T':
6576bffe
AB		 8865 func (stream, dis_style_register, "%s",
8866 arm_regnames[(value + 1) & 15]);
4934a27c
MM		 8867 break;
8868
8869 case 'd':
6576bffe 8870 func (stream, dis_style_immediate, "%ld", value);
4934a27c
MM		 8871 break;
8872
5aae9ae9
MM		 8873 case 'V':
8874 if (given & (1 << 6))
6576bffe 8875 func (stream, dis_style_register, "q%ld", value >> 1);
5aae9ae9 8876 else if (given & (1 << 24))
6576bffe 8877 func (stream, dis_style_register, "d%ld", value);
5aae9ae9
MM		 8878 else
8879 {
8880 /* Encoding for S register is different than for D and
8881 Q registers. S registers are encoded using the top
8882 single bit in position 22 as the lowest bit of the
8883 register number, while for Q and D it represents the
8884 highest bit of the register number. */
8885 uint8_t top_bit = (value >> 4) & 1;
8886 uint8_t tmp = (value << 1) & 0x1e;
8887 uint8_t res = tmp | top_bit;
6576bffe 8888 func (stream, dis_style_register, "s%u", res);
5aae9ae9
MM		 8889 }
8890 break;
8891
4934a27c
MM		 8892 default:
8893 abort ();
8894 }
8895 }
8896 break;
8897
8898 case 'p':
8899 {
8900 uint8_t proc_number = (given >> 8) & 0x7;
6576bffe 8901 func (stream, dis_style_register, "p%u", proc_number);
4934a27c
MM		 8902 break;
8903 }
8904
8905 case 'a':
8906 {
8907 uint8_t a_offset = 28;
8908 if (given & (1 << a_offset))
6576bffe 8909 func (stream, dis_style_mnemonic, "a");
4934a27c
MM		 8910 break;
8911 }
8912 default:
8913 abort ();
8914 }
8915 }
8916 else
6576bffe
AB		 8917 {
8918 if (*c == '@')
8919 base_style = dis_style_comment_start;
8920 if (*c == '\t')
8921 base_style = dis_style_text;
8922
8923 func (stream, base_style, "%c", *c);
8924 }
4934a27c
MM		 8925 }
8926
8927 if (is_unpredictable)
6576bffe 8928 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
4934a27c 8929
78933a4a 8930 return true;
4934a27c
MM		 8931 }
8932 }
78933a4a 8933 return false;
4934a27c
MM		 8934 }
8935 else
78933a4a 8936 return false;
4934a27c
MM		 8937}
8938
8939
16980d0b
JB		 8940/* Print one neon instruction on INFO->STREAM.
8941 Return TRUE if the instuction matched, FALSE if this is not a
8942 recognised neon instruction. */
8943
78933a4a
AM		 8944static bool
8945print_insn_neon (struct disassemble_info *info, long given, bool thumb)
16980d0b
JB		 8946{
8947 const struct opcode32 *insn;
8948 void *stream = info->stream;
6576bffe
AB		 8949 fprintf_styled_ftype func = info->fprintf_styled_func;
8950 enum disassembler_style base_style = dis_style_mnemonic;
8951 enum disassembler_style old_base_style = base_style;
16980d0b
JB		 8952
8953 if (thumb)
8954 {
8955 if ((given & 0xef000000) == 0xef000000)
8956 {
0313a2b8 8957 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8958 unsigned long bit28 = given & (1 << 28);
8959
8960 given &= 0x00ffffff;
8961 if (bit28)
8962 given |= 0xf3000000;
8963 else
8964 given |= 0xf2000000;
8965 }
8966 else if ((given & 0xff000000) == 0xf9000000)
8967 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 8968 /* BFloat16 neon instructions without special top byte handling. */
8969 else if ((given & 0xff000000) == 0xfe000000
8970 || (given & 0xff000000) == 0xfc000000)
8971 ;
9743db03 8972 /* vdup is also a valid neon instruction. */
e409955d 8973 else if ((given & 0xff900f5f) != 0xee800b10)
78933a4a 8974 return false;
16980d0b 8975 }
43e65147 8976
16980d0b
JB		 8977 for (insn = neon_opcodes; insn->assembler; insn++)
8978 {
e409955d
FS		 8979 unsigned long cond_mask = insn->mask;
8980 unsigned long cond_value = insn->value;
8981 int cond;
8982
8983 if (thumb)
8984 {
8985 if ((cond_mask & 0xf0000000) == 0) {
8986 /* For the entries in neon_opcodes, an opcode mask/value with
8987 the high 4 bits equal to 0 indicates a conditional
8988 instruction. For thumb however, we need to include those
8989 bits in the instruction matching. */
8990 cond_mask |= 0xf0000000;
8991 /* Furthermore, the thumb encoding of a conditional instruction
8992 will have the high 4 bits equal to 0xe. */
8993 cond_value |= 0xe0000000;
8994 }
8995 if (ifthen_state)
8996 cond = IFTHEN_COND;
8997 else
8998 cond = COND_UNCOND;
8999 }
9000 else
9001 {
9002 if ((given & 0xf0000000) == 0xf0000000)
9003 {
9004 /* If the instruction is unconditional, update the mask to only
9005 match against unconditional opcode values. */
9006 cond_mask |= 0xf0000000;
9007 cond = COND_UNCOND;
9008 }
9009 else
9010 {
9011 cond = (given >> 28) & 0xf;
9012 if (cond == 0xe)
9013 cond = COND_UNCOND;
9014 }
9015 }
9016
9017 if ((given & cond_mask) == cond_value)
16980d0b 9018 {
05413229 9019 signed long value_in_comment = 0;
78933a4a 9020 bool is_unpredictable = false;
16980d0b
JB		 9021 const char *c;
9022
9023 for (c = insn->assembler; *c; c++)
9024 {
9025 if (*c == '%')
9026 {
9027 switch (*++c)
9028 {
6576bffe
AB		 9029 case '{':
9030 ++c;
9031 if (*c == '\0')
9032 abort ();
9033 old_base_style = base_style;
9034 base_style = decode_base_style (*c);
9035 ++c;
9036 if (*c != ':')
9037 abort ();
9038 break;
9039
9040 case '}':
9041 base_style = old_base_style;
9042 break;
9043
16980d0b 9044 case '%':
6576bffe 9045 func (stream, base_style, "%%");
16980d0b
JB		 9046 break;
9047
e2efe87d
MGD		 9048 case 'u':
9049 if (thumb && ifthen_state)
78933a4a 9050 is_unpredictable = true;
e2efe87d
MGD		 9051
9052 /* Fall through. */
c22aaad1 9053 case 'c':
6576bffe
AB		 9054 func (stream, dis_style_mnemonic, "%s",
9055 arm_conditional[cond]);
c22aaad1
PB		 9056 break;
9057
16980d0b
JB		 9058 case 'A':
9059 {
43e65147 9060 static const unsigned char enc[16] =
16980d0b
JB		 9061 {
9062 0x4, 0x14, /* st4 0,1 */
9063 0x4, /* st1 2 */
9064 0x4, /* st2 3 */
9065 0x3, /* st3 4 */
9066 0x13, /* st3 5 */
9067 0x3, /* st1 6 */
9068 0x1, /* st1 7 */
9069 0x2, /* st2 8 */
9070 0x12, /* st2 9 */
9071 0x2, /* st1 10 */
9072 0, 0, 0, 0, 0
9073 };
9074 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9075 int rn = ((given >> 16) & 0xf);
9076 int rm = ((given >> 0) & 0xf);
9077 int align = ((given >> 4) & 0x3);
9078 int type = ((given >> 8) & 0xf);
9079 int n = enc[type] & 0xf;
9080 int stride = (enc[type] >> 4) + 1;
9081 int ix;
43e65147 9082
6576bffe 9083 func (stream, dis_style_text, "{");
16980d0b
JB		 9084 if (stride > 1)
9085 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9086 {
9087 if (ix > 0)
9088 func (stream, dis_style_text, ",");
9089 func (stream, dis_style_register, "d%d",
9090 rd + ix * stride);
9091 }
16980d0b 9092 else if (n == 1)
6576bffe 9093 func (stream, dis_style_register, "d%d", rd);
16980d0b 9094 else
6576bffe
AB		 9095 {
9096 func (stream, dis_style_register, "d%d", rd);
9097 func (stream, dis_style_text, "-");
9098 func (stream, dis_style_register, "d%d",
9099 rd + n - 1);
9100 }
9101 func (stream, dis_style_text, "}, [");
9102 func (stream, dis_style_register, "%s",
9103 arm_regnames[rn]);
16980d0b 9104 if (align)
6576bffe
AB		 9105 {
9106 func (stream, dis_style_text, " :");
9107 func (stream, dis_style_immediate, "%d",
9108 32 << align);
9109 }
9110 func (stream, dis_style_text, "]");
16980d0b 9111 if (rm == 0xd)
6576bffe 9112 func (stream, dis_style_text, "!");
16980d0b 9113 else if (rm != 0xf)
6576bffe
AB		 9114 {
9115 func (stream, dis_style_text, ", ");
9116 func (stream, dis_style_register, "%s",
9117 arm_regnames[rm]);
9118 }
16980d0b
JB		 9119 }
9120 break;
43e65147 9121
16980d0b
JB		 9122 case 'B':
9123 {
9124 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9125 int rn = ((given >> 16) & 0xf);
9126 int rm = ((given >> 0) & 0xf);
9127 int idx_align = ((given >> 4) & 0xf);
9128 int align = 0;
9129 int size = ((given >> 10) & 0x3);
9130 int idx = idx_align >> (size + 1);
9131 int length = ((given >> 8) & 3) + 1;
9132 int stride = 1;
9133 int i;
9134
9135 if (length > 1 && size > 0)
9136 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9137
16980d0b
JB		 9138 switch (length)
9139 {
9140 case 1:
9141 {
9142 int amask = (1 << size) - 1;
9143 if ((idx_align & (1 << size)) != 0)
78933a4a 9144 return false;
16980d0b
JB		 9145 if (size > 0)
9146 {
9147 if ((idx_align & amask) == amask)
9148 align = 8 << size;
9149 else if ((idx_align & amask) != 0)
78933a4a 9150 return false;
16980d0b
JB		 9151 }
9152 }
9153 break;
43e65147 9154
16980d0b
JB		 9155 case 2:
9156 if (size == 2 && (idx_align & 2) != 0)
78933a4a 9157 return false;
16980d0b
JB		 9158 align = (idx_align & 1) ? 16 << size : 0;
9159 break;
43e65147 9160
16980d0b
JB		 9161 case 3:
9162 if ((size == 2 && (idx_align & 3) != 0)
9163 || (idx_align & 1) != 0)
78933a4a 9164 return false;
16980d0b 9165 break;
43e65147 9166
16980d0b
JB		 9167 case 4:
9168 if (size == 2)
9169 {
9170 if ((idx_align & 3) == 3)
78933a4a 9171 return false;
16980d0b
JB		 9172 align = (idx_align & 3) * 64;
9173 }
9174 else
9175 align = (idx_align & 1) ? 32 << size : 0;
9176 break;
43e65147 9177
16980d0b
JB		 9178 default:
9179 abort ();
9180 }
43e65147 9181
6576bffe 9182 func (stream, dis_style_text, "{");
16980d0b 9183 for (i = 0; i < length; i++)
6576bffe
AB		 9184 {
9185 if (i > 0)
9186 func (stream, dis_style_text, ",");
9187 func (stream, dis_style_register, "d%d[%d]",
9188 rd + i * stride, idx);
9189 }
9190 func (stream, dis_style_text, "}, [");
9191 func (stream, dis_style_register, "%s",
9192 arm_regnames[rn]);
16980d0b 9193 if (align)
6576bffe
AB		 9194 {
9195 func (stream, dis_style_text, " :");
9196 func (stream, dis_style_immediate, "%d", align);
9197 }
9198 func (stream, dis_style_text, "]");
16980d0b 9199 if (rm == 0xd)
6576bffe 9200 func (stream, dis_style_text, "!");
16980d0b 9201 else if (rm != 0xf)
6576bffe
AB		 9202 {
9203 func (stream, dis_style_text, ", ");
9204 func (stream, dis_style_register, "%s",
9205 arm_regnames[rm]);
9206 }
16980d0b
JB		 9207 }
9208 break;
43e65147 9209
16980d0b
JB		 9210 case 'C':
9211 {
9212 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9213 int rn = ((given >> 16) & 0xf);
9214 int rm = ((given >> 0) & 0xf);
9215 int align = ((given >> 4) & 0x1);
9216 int size = ((given >> 6) & 0x3);
9217 int type = ((given >> 8) & 0x3);
9218 int n = type + 1;
9219 int stride = ((given >> 5) & 0x1);
9220 int ix;
43e65147 9221
16980d0b
JB		 9222 if (stride && (n == 1))
9223 n++;
9224 else
9225 stride++;
43e65147 9226
6576bffe 9227 func (stream, dis_style_text, "{");
16980d0b
JB		 9228 if (stride > 1)
9229 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9230 {
9231 if (ix > 0)
9232 func (stream, dis_style_text, ",");
9233 func (stream, dis_style_register, "d%d[]",
9234 rd + ix * stride);
9235 }
16980d0b 9236 else if (n == 1)
6576bffe 9237 func (stream, dis_style_register, "d%d[]", rd);
16980d0b 9238 else
6576bffe
AB		 9239 {
9240 func (stream, dis_style_register, "d%d[]", rd);
9241 func (stream, dis_style_text, "-");
9242 func (stream, dis_style_register, "d%d[]",
9243 rd + n - 1);
9244 }
9245 func (stream, dis_style_text, "}, [");
9246 func (stream, dis_style_register, "%s",
9247 arm_regnames[rn]);
16980d0b
JB		 9248 if (align)
9249 {
91d6fa6a 9250 align = (8 * (type + 1)) << size;
16980d0b
JB		 9251 if (type == 3)
9252 align = (size > 1) ? align >> 1 : align;
9253 if (type == 2 || (type == 0 && !size))
6576bffe
AB		 9254 func (stream, dis_style_text,
9255 " :<bad align %d>", align);
16980d0b 9256 else
6576bffe
AB		 9257 {
9258 func (stream, dis_style_text, " :");
9259 func (stream, dis_style_immediate,
9260 "%d", align);
9261 }
16980d0b 9262 }
6576bffe 9263 func (stream, dis_style_text, "]");
16980d0b 9264 if (rm == 0xd)
6576bffe 9265 func (stream, dis_style_text, "!");
16980d0b 9266 else if (rm != 0xf)
6576bffe
AB		 9267 {
9268 func (stream, dis_style_text, ", ");
9269 func (stream, dis_style_register, "%s",
9270 arm_regnames[rm]);
9271 }
16980d0b
JB		 9272 }
9273 break;
43e65147 9274
16980d0b
JB		 9275 case 'D':
9276 {
9277 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9278 int size = (given >> 20) & 3;
9279 int reg = raw_reg & ((4 << size) - 1);
9280 int ix = raw_reg >> size >> 2;
43e65147 9281
6576bffe 9282 func (stream, dis_style_register, "d%d[%d]", reg, ix);
16980d0b
JB		 9283 }
9284 break;
43e65147 9285
16980d0b 9286 case 'E':
fe56b6ce 9287 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9288 {
9289 int bits = 0;
9290 int cmode = (given >> 8) & 0xf;
9291 int op = (given >> 5) & 0x1;
9292 unsigned long value = 0, hival = 0;
9293 unsigned shift;
9294 int size = 0;
0dbde4cf 9295 int isfloat = 0;
43e65147 9296
16980d0b
JB		 9297 bits |= ((given >> 24) & 1) << 7;
9298 bits |= ((given >> 16) & 7) << 4;
9299 bits |= ((given >> 0) & 15) << 0;
43e65147 9300
16980d0b
JB		 9301 if (cmode < 8)
9302 {
9303 shift = (cmode >> 1) & 3;
fe56b6ce 9304 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9305 size = 32;
9306 }
9307 else if (cmode < 12)
9308 {
9309 shift = (cmode >> 1) & 1;
fe56b6ce 9310 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9311 size = 16;
9312 }
9313 else if (cmode < 14)
9314 {
9315 shift = (cmode & 1) + 1;
fe56b6ce 9316 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9317 value |= (1ul << (8 * shift)) - 1;
9318 size = 32;
9319 }
9320 else if (cmode == 14)
9321 {
9322 if (op)
9323 {
fe56b6ce 9324 /* Bit replication into bytes. */
16980d0b
JB		 9325 int ix;
9326 unsigned long mask;
43e65147 9327
16980d0b
JB		 9328 value = 0;
9329 hival = 0;
9330 for (ix = 7; ix >= 0; ix--)
9331 {
9332 mask = ((bits >> ix) & 1) ? 0xff : 0;
9333 if (ix <= 3)
9334 value = (value << 8) | mask;
9335 else
9336 hival = (hival << 8) | mask;
9337 }
9338 size = 64;
9339 }
9340 else
9341 {
fe56b6ce
NC		 9342 /* Byte replication. */
9343 value = (unsigned long) bits;
16980d0b
JB		 9344 size = 8;
9345 }
9346 }
9347 else if (!op)
9348 {
fe56b6ce 9349 /* Floating point encoding. */
16980d0b 9350 int tmp;
43e65147 9351
fe56b6ce
NC		 9352 value = (unsigned long) (bits & 0x7f) << 19;
9353 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9354 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9355 value |= (unsigned long) tmp << 24;
16980d0b 9356 size = 32;
0dbde4cf 9357 isfloat = 1;
16980d0b
JB		 9358 }
9359 else
9360 {
6576bffe
AB		 9361 func (stream, dis_style_text,
9362 "<illegal constant %.8x:%x:%x>",
16980d0b
JB		 9363 bits, cmode, op);
9364 size = 32;
9365 break;
9366 }
9367 switch (size)
9368 {
9369 case 8:
6576bffe
AB		 9370 func (stream, dis_style_immediate, "#%ld", value);
9371 func (stream, dis_style_comment_start,
9372 "\t@ 0x%.2lx", value);
16980d0b 9373 break;
43e65147 9374
16980d0b 9375 case 16:
6576bffe
AB		 9376 func (stream, dis_style_immediate, "#%ld", value);
9377 func (stream, dis_style_comment_start,
9378 "\t@ 0x%.4lx", value);
16980d0b
JB		 9379 break;
9380
9381 case 32:
0dbde4cf
JB		 9382 if (isfloat)
9383 {
9384 unsigned char valbytes[4];
9385 double fvalue;
43e65147 9386
0dbde4cf
JB		 9387 /* Do this a byte at a time so we don't have to
9388 worry about the host's endianness. */
9389 valbytes[0] = value & 0xff;
9390 valbytes[1] = (value >> 8) & 0xff;
9391 valbytes[2] = (value >> 16) & 0xff;
9392 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9393
9394 floatformat_to_double
c1e26897
NC		 9395 (& floatformat_ieee_single_little, valbytes,
9396 & fvalue);
43e65147 9397
6576bffe
AB		 9398 func (stream, dis_style_immediate,
9399 "#%.7g", fvalue);
9400 func (stream, dis_style_comment_start,
9401 "\t@ 0x%.8lx", value);
0dbde4cf
JB		 9402 }
9403 else
6576bffe
AB		 9404 {
9405 func (stream, dis_style_immediate, "#%ld",
9406 (long) (((value & 0x80000000L) != 0)
9407 ? value | ~0xffffffffL : value));
9408 func (stream, dis_style_comment_start,
9409 "\t@ 0x%.8lx", value);
9410 }
16980d0b
JB		 9411 break;
9412
9413 case 64:
6576bffe
AB		 9414 func (stream, dis_style_immediate,
9415 "#0x%.8lx%.8lx", hival, value);
16980d0b 9416 break;
43e65147 9417
16980d0b
JB		 9418 default:
9419 abort ();
9420 }
9421 }
9422 break;
43e65147 9423
16980d0b
JB		 9424 case 'F':
9425 {
9426 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9427 int num = (given >> 8) & 0x3;
43e65147 9428
6576bffe 9429 func (stream, dis_style_text, "{");
16980d0b 9430 if (!num)
6576bffe 9431 func (stream, dis_style_register, "d%d", regno);
16980d0b 9432 else if (num + regno >= 32)
6576bffe
AB		 9433 {
9434 func (stream, dis_style_register, "d%d", regno);
9435 func (stream, dis_style_text, "-<overflow reg d%d",
9436 regno + num);
9437 }
16980d0b 9438 else
6576bffe
AB		 9439 {
9440 func (stream, dis_style_register, "d%d", regno);
9441 func (stream, dis_style_text, "-");
9442 func (stream, dis_style_register, "d%d",
9443 regno + num);
9444 }
9445 func (stream, dis_style_text, "}");
16980d0b
JB		 9446 }
9447 break;
7e8e6784 9448
16980d0b
JB		 9449
9450 case '0': case '1': case '2': case '3': case '4':
9451 case '5': case '6': case '7': case '8': case '9':
9452 {
9453 int width;
9454 unsigned long value;
9455
9456 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9457
16980d0b
JB		 9458 switch (*c)
9459 {
9460 case 'r':
6576bffe
AB		 9461 func (stream, dis_style_register, "%s",
9462 arm_regnames[value]);
16980d0b
JB		 9463 break;
9464 case 'd':
6576bffe 9465 func (stream, base_style, "%ld", value);
05413229 9466 value_in_comment = value;
16980d0b
JB		 9467 break;
9468 case 'e':
6576bffe
AB		 9469 func (stream, dis_style_immediate, "%ld",
9470 (1ul << width) - value);
16980d0b 9471 break;
43e65147 9472
16980d0b
JB		 9473 case 'S':
9474 case 'T':
9475 case 'U':
05413229 9476 /* Various width encodings. */
16980d0b
JB		 9477 {
9478 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9479 int limit;
9480 unsigned low, high;
9481
9482 c++;
9483 if (*c >= '0' && *c <= '9')
9484 limit = *c - '0';
9485 else if (*c >= 'a' && *c <= 'f')
9486 limit = *c - 'a' + 10;
9487 else
9488 abort ();
9489 low = limit >> 2;
9490 high = limit & 3;
9491
9492 if (value < low || value > high)
6576bffe
AB		 9493 func (stream, dis_style_text,
9494 "<illegal width %d>", base << value);
16980d0b 9495 else
6576bffe
AB		 9496 func (stream, base_style, "%d",
9497 base << value);
16980d0b
JB		 9498 }
9499 break;
9500 case 'R':
9501 if (given & (1 << 6))
9502 goto Q;
9503 /* FALLTHROUGH */
9504 case 'D':
6576bffe 9505 func (stream, dis_style_register, "d%ld", value);
16980d0b
JB		 9506 break;
9507 case 'Q':
9508 Q:
9509 if (value & 1)
6576bffe
AB		 9510 func (stream, dis_style_text,
9511 "<illegal reg q%ld.5>", value >> 1);
16980d0b 9512 else
6576bffe
AB		 9513 func (stream, dis_style_register,
9514 "q%ld", value >> 1);
16980d0b 9515 break;
43e65147 9516
16980d0b
JB		 9517 case '`':
9518 c++;
9519 if (value == 0)
6576bffe 9520 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9521 break;
9522 case '\'':
9523 c++;
9524 if (value == ((1ul << width) - 1))
6576bffe 9525 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9526 break;
9527 case '?':
6576bffe
AB		 9528 func (stream, dis_style_mnemonic, "%c",
9529 c[(1 << width) - (int) value]);
16980d0b
JB		 9530 c += 1 << width;
9531 break;
9532 default:
9533 abort ();
9534 }
16980d0b 9535 }
dffaa15c
AM		 9536 break;
9537
9538 default:
9539 abort ();
16980d0b
JB		 9540 }
9541 }
9542 else
6576bffe
AB		 9543 {
9544 if (*c == '@')
9545 base_style = dis_style_comment_start;
9546
9547 if (*c == '\t')
9548 base_style = dis_style_text;
9549
9550 func (stream, base_style, "%c", *c);
9551
9552 }
16980d0b 9553 }
05413229
NC		 9554
9555 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 9556 func (stream, dis_style_comment_start, "\t@ 0x%lx",
9557 value_in_comment);
05413229 9558
e2efe87d 9559 if (is_unpredictable)
6576bffe 9560 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
e2efe87d 9561
78933a4a 9562 return true;
16980d0b
JB		 9563 }
9564 }
78933a4a 9565 return false;
16980d0b
JB		 9566}
9567
73cd51e5
AV		 9568/* Print one mve instruction on INFO->STREAM.
9569 Return TRUE if the instuction matched, FALSE if this is not a
9570 recognised mve instruction. */
9571
78933a4a 9572static bool
73cd51e5
AV		 9573print_insn_mve (struct disassemble_info *info, long given)
9574{
9575 const struct mopcode32 *insn;
9576 void *stream = info->stream;
6576bffe
AB		 9577 fprintf_styled_ftype func = info->fprintf_styled_func;
9578 enum disassembler_style base_style = dis_style_mnemonic;
9579 enum disassembler_style old_base_style = base_style;
73cd51e5
AV		 9580
9581 for (insn = mve_opcodes; insn->assembler; insn++)
9582 {
9583 if (((given & insn->mask) == insn->value)
9584 && !is_mve_encoding_conflict (given, insn->mve_op))
9585 {
9586 signed long value_in_comment = 0;
78933a4a
AM		 9587 bool is_unpredictable = false;
9588 bool is_undefined = false;
73cd51e5
AV		 9589 const char *c;
9590 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9591 enum mve_undefined undefined_cond = UNDEF_NONE;
9592
9593 /* Most vector mve instruction are illegal in a it block.
9594 There are a few exceptions; check for them. */
9595 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9596 {
78933a4a 9597 is_unpredictable = true;
73cd51e5
AV		 9598 unpredictable_cond = UNPRED_IT_BLOCK;
9599 }
9600 else if (is_mve_unpredictable (given, insn->mve_op,
9601 &unpredictable_cond))
78933a4a 9602 is_unpredictable = true;
73cd51e5
AV		 9603
9604 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
78933a4a 9605 is_undefined = true;
73cd51e5 9606
c4a23bf8
SP		 9607 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9608 i.e "VMOV Qd, Qm". */
9609 if ((insn->mve_op == MVE_VORR_REG)
9610 && (arm_decode_field (given, 1, 3)
9611 == arm_decode_field (given, 17, 19)))
9612 continue;
9613
73cd51e5
AV		 9614 for (c = insn->assembler; *c; c++)
9615 {
9616 if (*c == '%')
9617 {
9618 switch (*++c)
9619 {
6576bffe
AB		 9620 case '{':
9621 ++c;
9622 if (*c == '\0')
9623 abort ();
9624 old_base_style = base_style;
9625 base_style = decode_base_style (*c);
9626 ++c;
9627 if (*c != ':')
9628 abort ();
9629 break;
9630
9631 case '}':
9632 base_style = old_base_style;
9633 break;
9634
73cd51e5 9635 case '%':
6576bffe 9636 func (stream, base_style, "%%");
73cd51e5
AV		 9637 break;
9638
ef1576a1
AV		 9639 case 'a':
9640 /* Don't print anything for '+' as it is implied. */
9641 if (arm_decode_field (given, 23, 23) == 0)
6576bffe 9642 func (stream, dis_style_immediate, "-");
ef1576a1
AV		 9643 break;
9644
143275ea
AV		 9645 case 'c':
9646 if (ifthen_state)
6576bffe
AB		 9647 func (stream, dis_style_mnemonic, "%s",
9648 arm_conditional[IFTHEN_COND]);
143275ea
AV		 9649 break;
9650
aef6d006
AV		 9651 case 'd':
9652 print_mve_vld_str_addr (info, given, insn->mve_op);
9653 break;
9654
143275ea
AV		 9655 case 'i':
9656 {
9657 long mve_mask = mve_extract_pred_mask (given);
6576bffe
AB		 9658 func (stream, dis_style_mnemonic, "%s",
9659 mve_predicatenames[mve_mask]);
143275ea
AV		 9660 }
9661 break;
9662
23d00a41
SD		 9663 case 'j':
9664 {
9665 unsigned int imm5 = 0;
9666 imm5 |= arm_decode_field (given, 6, 7);
9667 imm5 |= (arm_decode_field (given, 12, 14) << 2);
6576bffe
AB		 9668 func (stream, dis_style_immediate, "#%u",
9669 (imm5 == 0) ? 32 : imm5);
23d00a41
SD		 9670 }
9671 break;
9672
08132bdd 9673 case 'k':
6576bffe 9674 func (stream, dis_style_immediate, "#%u",
08132bdd
SP		 9675 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9676 break;
9677
143275ea
AV		 9678 case 'n':
9679 print_vec_condition (info, given, insn->mve_op);
9680 break;
9681
ef1576a1
AV		 9682 case 'o':
9683 if (arm_decode_field (given, 0, 0) == 1)
9684 {
9685 unsigned long size
9686 = arm_decode_field (given, 4, 4)
9687 | (arm_decode_field (given, 6, 6) << 1);
9688
6576bffe
AB		 9689 func (stream, dis_style_text, ", ");
9690 func (stream, dis_style_sub_mnemonic, "uxtw ");
9691 func (stream, dis_style_immediate, "#%lu", size);
ef1576a1
AV		 9692 }
9693 break;
9694
bf0b396d
AV		 9695 case 'm':
9696 print_mve_rounding_mode (info, given, insn->mve_op);
9697 break;
9698
9699 case 's':
9700 print_mve_vcvt_size (info, given, insn->mve_op);
9701 break;
9702
aef6d006
AV		 9703 case 'u':
9704 {
c507f10b
AV		 9705 unsigned long op1 = arm_decode_field (given, 21, 22);
9706
9707 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9708 {
9709 /* Check for signed. */
9710 if (arm_decode_field (given, 23, 23) == 0)
9711 {
9712 /* We don't print 's' for S32. */
9713 if ((arm_decode_field (given, 5, 6) == 0)
9714 && ((op1 == 0) || (op1 == 1)))
9715 ;
9716 else
6576bffe 9717 func (stream, dis_style_mnemonic, "s");
c507f10b
AV		 9718 }
9719 else
6576bffe 9720 func (stream, dis_style_mnemonic, "u");
c507f10b 9721 }
aef6d006 9722 else
c507f10b
AV		 9723 {
9724 if (arm_decode_field (given, 28, 28) == 0)
6576bffe 9725 func (stream, dis_style_mnemonic, "s");
c507f10b 9726 else
6576bffe 9727 func (stream, dis_style_mnemonic, "u");
c507f10b 9728 }
aef6d006 9729 }
ef1576a1 9730 break;
aef6d006 9731
143275ea
AV		 9732 case 'v':
9733 print_instruction_predicate (info);
9734 break;
9735
04d54ace
AV		 9736 case 'w':
9737 if (arm_decode_field (given, 21, 21) == 1)
6576bffe 9738 func (stream, dis_style_text, "!");
04d54ace
AV		 9739 break;
9740
9741 case 'B':
9742 print_mve_register_blocks (info, given, insn->mve_op);
9743 break;
9744
c507f10b
AV		 9745 case 'E':
9746 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9747
9748 print_simd_imm8 (info, given, 28, insn);
9749 break;
9750
9751 case 'N':
9752 print_mve_vmov_index (info, given);
9753 break;
9754
14925797
AV		 9755 case 'T':
9756 if (arm_decode_field (given, 12, 12) == 0)
6576bffe 9757 func (stream, dis_style_mnemonic, "b");
14925797 9758 else
6576bffe 9759 func (stream, dis_style_mnemonic, "t");
14925797
AV		 9760 break;
9761
d3b63143
AV		 9762 case 'X':
9763 if (arm_decode_field (given, 12, 12) == 1)
6576bffe 9764 func (stream, dis_style_mnemonic, "x");
d3b63143
AV		 9765 break;
9766
143275ea
AV		 9767 case '0': case '1': case '2': case '3': case '4':
9768 case '5': case '6': case '7': case '8': case '9':
9769 {
9770 int width;
9771 unsigned long value;
9772
9773 c = arm_decode_bitfield (c, given, &value, &width);
9774
9775 switch (*c)
9776 {
9777 case 'Z':
9778 if (value == 13)
78933a4a 9779 is_unpredictable = true;
143275ea 9780 else if (value == 15)
6576bffe 9781 func (stream, dis_style_register, "zr");
143275ea 9782 else
6576bffe
AB		 9783 func (stream, dis_style_register, "%s",
9784 arm_regnames[value]);
143275ea 9785 break;
23d00a41 9786
e39c1607 9787 case 'c':
6576bffe
AB		 9788 func (stream, dis_style_sub_mnemonic, "%s",
9789 arm_conditional[value]);
e39c1607
SD		 9790 break;
9791
9792 case 'C':
9793 value ^= 1;
6576bffe
AB		 9794 func (stream, dis_style_sub_mnemonic, "%s",
9795 arm_conditional[value]);
e39c1607
SD		 9796 break;
9797
23d00a41
SD		 9798 case 'S':
9799 if (value == 13 || value == 15)
78933a4a 9800 is_unpredictable = true;
23d00a41 9801 else
6576bffe
AB		 9802 func (stream, dis_style_register, "%s",
9803 arm_regnames[value]);
23d00a41
SD		 9804 break;
9805
143275ea
AV		 9806 case 's':
9807 print_mve_size (info,
9808 value,
9809 insn->mve_op);
9810 break;
66dcaa5d
AV		 9811 case 'I':
9812 if (value == 1)
6576bffe 9813 func (stream, dis_style_mnemonic, "i");
66dcaa5d 9814 break;
d3b63143
AV		 9815 case 'A':
9816 if (value == 1)
6576bffe 9817 func (stream, dis_style_mnemonic, "a");
d3b63143 9818 break;
1c8f2df8
AV		 9819 case 'h':
9820 {
9821 unsigned int odd_reg = (value << 1) | 1;
6576bffe
AB		 9822 func (stream, dis_style_register, "%s",
9823 arm_regnames[odd_reg]);
1c8f2df8
AV		 9824 }
9825 break;
ef1576a1
AV		 9826 case 'i':
9827 {
9828 unsigned long imm
9829 = arm_decode_field (given, 0, 6);
9830 unsigned long mod_imm = imm;
9831
9832 switch (insn->mve_op)
9833 {
9834 case MVE_VLDRW_GATHER_T5:
9835 case MVE_VSTRW_SCATTER_T5:
9836 mod_imm = mod_imm << 2;
9837 break;
9838 case MVE_VSTRD_SCATTER_T6:
9839 case MVE_VLDRD_GATHER_T6:
9840 mod_imm = mod_imm << 3;
9841 break;
9842
9843 default:
9844 break;
9845 }
9846
6576bffe
AB		 9847 func (stream, dis_style_immediate, "%lu",
9848 mod_imm);
ef1576a1
AV		 9849 }
9850 break;
bf0b396d 9851 case 'k':
6576bffe
AB		 9852 func (stream, dis_style_immediate, "%lu",
9853 64 - value);
bf0b396d 9854 break;
1c8f2df8
AV		 9855 case 'l':
9856 {
9857 unsigned int even_reg = value << 1;
6576bffe
AB		 9858 func (stream, dis_style_register, "%s",
9859 arm_regnames[even_reg]);
1c8f2df8
AV		 9860 }
9861 break;
9862 case 'u':
9863 switch (value)
9864 {
9865 case 0:
6576bffe 9866 func (stream, dis_style_immediate, "1");
1c8f2df8
AV		 9867 break;
9868 case 1:
6576bffe 9869 func (stream, dis_style_immediate, "2");
1c8f2df8
AV		 9870 break;
9871 case 2:
6576bffe 9872 func (stream, dis_style_immediate, "4");
1c8f2df8
AV		 9873 break;
9874 case 3:
6576bffe 9875 func (stream, dis_style_immediate, "8");
1c8f2df8
AV		 9876 break;
9877 default:
9878 break;
9879 }
9880 break;
897b9bbc
AV		 9881 case 'o':
9882 print_mve_rotate (info, value, width);
9883 break;
9743db03 9884 case 'r':
6576bffe
AB		 9885 func (stream, dis_style_register, "%s",
9886 arm_regnames[value]);
9743db03 9887 break;
04d54ace 9888 case 'd':
f9d6cf2e 9889 if (mve_shift_insn_p (insn->mve_op))
ed63aa17
AV		 9890 print_mve_shift_n (info, given, insn->mve_op);
9891 else if (insn->mve_op == MVE_VSHLL_T2)
e26ff6c4
AM		 9892 func (stream, dis_style_immediate, "%s",
9893 mve_vec_sizename[value]);
ed63aa17
AV		 9894 else
9895 {
9896 if (insn->mve_op == MVE_VSHLC && value == 0)
9897 value = 32;
6576bffe 9898 func (stream, base_style, "%ld", value);
ed63aa17
AV		 9899 value_in_comment = value;
9900 }
04d54ace 9901 break;
c507f10b 9902 case 'F':
6576bffe 9903 func (stream, dis_style_register, "s%ld", value);
c507f10b 9904 break;
143275ea
AV		 9905 case 'Q':
9906 if (value & 0x8)
6576bffe
AB		 9907 func (stream, dis_style_text,
9908 "<illegal reg q%ld.5>", value);
143275ea 9909 else
6576bffe 9910 func (stream, dis_style_register, "q%ld", value);
143275ea 9911 break;
c507f10b 9912 case 'x':
6576bffe
AB		 9913 func (stream, dis_style_immediate,
9914 "0x%08lx", value);
c507f10b 9915 break;
143275ea
AV		 9916 default:
9917 abort ();
9918 }
9919 break;
9920 default:
9921 abort ();
9922 }
73cd51e5
AV		 9923 }
9924 }
9925 else
6576bffe
AB		 9926 {
9927 if (*c == '@')
9928 base_style = dis_style_comment_start;
9929
9930 if (*c == '\t')
9931 base_style = dis_style_text;
9932
9933 func (stream, base_style, "%c", *c);
9934 }
73cd51e5
AV		 9935 }
9936
9937 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 9938 func (stream, dis_style_comment_start, "\t@ 0x%lx",
9939 value_in_comment);
73cd51e5
AV		 9940
9941 if (is_unpredictable)
9942 print_mve_unpredictable (info, unpredictable_cond);
9943
9944 if (is_undefined)
9945 print_mve_undefined (info, undefined_cond);
9946
63b4cc53 9947 if (!vpt_block_state.in_vpt_block
143275ea 9948 && !ifthen_state
63b4cc53 9949 && is_vpt_instruction (given))
143275ea 9950 mark_inside_vpt_block (given);
63b4cc53 9951 else if (vpt_block_state.in_vpt_block)
143275ea
AV		 9952 update_vpt_block_state ();
9953
78933a4a 9954 return true;
73cd51e5
AV		 9955 }
9956 }
78933a4a 9957 return false;
73cd51e5
AV		 9958}
9959
9960
90ec0d68
MGD		 9961/* Return the name of a v7A special register. */
9962
43e65147 9963static const char *
90ec0d68
MGD		 9964banked_regname (unsigned reg)
9965{
9966 switch (reg)
9967 {
9968 case 15: return "CPSR";
43e65147 9969 case 32: return "R8_usr";
90ec0d68
MGD		 9970 case 33: return "R9_usr";
9971 case 34: return "R10_usr";
9972 case 35: return "R11_usr";
9973 case 36: return "R12_usr";
9974 case 37: return "SP_usr";
9975 case 38: return "LR_usr";
43e65147 9976 case 40: return "R8_fiq";
90ec0d68
MGD		 9977 case 41: return "R9_fiq";
9978 case 42: return "R10_fiq";
9979 case 43: return "R11_fiq";
9980 case 44: return "R12_fiq";
9981 case 45: return "SP_fiq";
9982 case 46: return "LR_fiq";
9983 case 48: return "LR_irq";
9984 case 49: return "SP_irq";
9985 case 50: return "LR_svc";
9986 case 51: return "SP_svc";
9987 case 52: return "LR_abt";
9988 case 53: return "SP_abt";
9989 case 54: return "LR_und";
9990 case 55: return "SP_und";
9991 case 60: return "LR_mon";
9992 case 61: return "SP_mon";
9993 case 62: return "ELR_hyp";
9994 case 63: return "SP_hyp";
9995 case 79: return "SPSR";
9996 case 110: return "SPSR_fiq";
9997 case 112: return "SPSR_irq";
9998 case 114: return "SPSR_svc";
9999 case 116: return "SPSR_abt";
10000 case 118: return "SPSR_und";
10001 case 124: return "SPSR_mon";
10002 case 126: return "SPSR_hyp";
10003 default: return NULL;
10004 }
10005}
10006
e797f7e0
MGD		 10007/* Return the name of the DMB/DSB option. */
10008static const char *
10009data_barrier_option (unsigned option)
10010{
10011 switch (option & 0xf)
10012 {
10013 case 0xf: return "sy";
10014 case 0xe: return "st";
10015 case 0xd: return "ld";
10016 case 0xb: return "ish";
10017 case 0xa: return "ishst";
10018 case 0x9: return "ishld";
10019 case 0x7: return "un";
10020 case 0x6: return "unst";
10021 case 0x5: return "nshld";
10022 case 0x3: return "osh";
10023 case 0x2: return "oshst";
10024 case 0x1: return "oshld";
10025 default: return NULL;
10026 }
10027}
10028
4a5329c6
ZW		 10029/* Print one ARM instruction from PC on INFO->STREAM. */
10030
10031static void
10032print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10033{
6b5d3a4d 10034 const struct opcode32 *insn;
6a51a8a8 10035 void *stream = info->stream;
6576bffe 10036 fprintf_styled_ftype func = info->fprintf_styled_func;
b0e28b39 10037 struct arm_private_data *private_data = info->private_data;
6576bffe
AB		 10038 enum disassembler_style base_style = dis_style_mnemonic;
10039 enum disassembler_style old_base_style = base_style;
252b5132 10040
78933a4a 10041 if (print_insn_coprocessor (pc, info, given, false))
16980d0b
JB		 10042 return;
10043
78933a4a 10044 if (print_insn_neon (info, given, false))
8f06b2d8
PB		 10045 return;
10046
78933a4a 10047 if (print_insn_generic_coprocessor (pc, info, given, false))
33593eaf
MM		 10048 return;
10049
252b5132
RH		 10050 for (insn = arm_opcodes; insn->assembler; insn++)
10051 {
0313a2b8
NC		 10052 if ((given & insn->mask) != insn->value)
10053 continue;
823d2571
TG		 10054
10055 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 10056 continue;
10057
10058 /* Special case: an instruction with all bits set in the condition field
10059 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10060 or by the catchall at the end of the table. */
10061 if ((given & 0xF0000000) != 0xF0000000
10062 || (insn->mask & 0xF0000000) == 0xF0000000
10063 || (insn->mask == 0 && insn->value == 0))
252b5132 10064 {
ff4a8d2b
NC		 10065 unsigned long u_reg = 16;
10066 unsigned long U_reg = 16;
78933a4a 10067 bool is_unpredictable = false;
05413229 10068 signed long value_in_comment = 0;
6b5d3a4d 10069 const char *c;
b34976b6 10070
252b5132
RH		 10071 for (c = insn->assembler; *c; c++)
10072 {
10073 if (*c == '%')
10074 {
78933a4a 10075 bool allow_unpredictable = false;
c1e26897 10076
252b5132
RH		 10077 switch (*++c)
10078 {
6576bffe
AB		 10079 case '{':
10080 ++c;
10081 if (*c == '\0')
10082 abort ();
10083 old_base_style = base_style;
10084 base_style = decode_base_style (*c);
10085 ++c;
10086 if (*c != ':')
10087 abort ();
10088 break;
10089
10090 case '}':
10091 base_style = old_base_style;
10092 break;
10093
252b5132 10094 case '%':
6576bffe 10095 func (stream, base_style, "%%");
252b5132
RH		 10096 break;
10097
10098 case 'a':
05413229 10099 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10100 break;
252b5132 10101
62b3e311
PB		 10102 case 'P':
10103 /* Set P address bit and use normal address
10104 printing routine. */
c1e26897 10105 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10106 break;
10107
2c9d089c
AV		 10108 case 'T':
10109 /* Armv4 does not have a BX instruction, however, when
10110 assembled with the --fix-v4bx option GAS will accept
10111 and assemble a BX instruction when assembling for
10112 Armv4. When disassembling we also disassemble it as a
10113 BX instruction, but do make the user aware that this
10114 instruction is only supported on HW from Armv4T
10115 onwards. */
10116 if (info->mach == bfd_mach_arm_4)
10117 func (stream, dis_style_text, "\t@ from Armv4T onwards");
10118 break;
10119
c1e26897 10120 case 'S':
78933a4a 10121 allow_unpredictable = true;
1a0670f3 10122 /* Fall through. */
252b5132
RH		 10123 case 's':
10124 if ((given & 0x004f0000) == 0x004f0000)
10125 {
58efb6c0 10126 /* PC relative with immediate offset. */
f8b960bc 10127 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10128
aefd8a40
NC		 10129 if (PRE_BIT_SET)
10130 {
26d97720
NS		 10131 /* Elide positive zero offset. */
10132 if (offset || NEGATIVE_BIT_SET)
6576bffe
AB		 10133 {
10134 func (stream, dis_style_text, "[");
10135 func (stream, dis_style_register, "pc");
10136 func (stream, dis_style_text, ", ");
10137 func (stream, dis_style_immediate, "#%s%d",
10138 (NEGATIVE_BIT_SET ? "-" : ""),
10139 (int) offset);
10140 func (stream, dis_style_text, "]");
10141 }
945ee430 10142 else
6576bffe
AB		 10143 {
10144 func (stream, dis_style_text, "[");
10145 func (stream, dis_style_register, "pc");
10146 func (stream, dis_style_text, "]");
10147 }
26d97720
NS		 10148 if (NEGATIVE_BIT_SET)
10149 offset = -offset;
6576bffe 10150 func (stream, dis_style_comment_start, "\t@ ");
aefd8a40
NC		 10151 info->print_address_func (offset + pc + 8, info);
10152 }
10153 else
10154 {
26d97720 10155 /* Always show the offset. */
6576bffe
AB		 10156 func (stream, dis_style_text, "[");
10157 func (stream, dis_style_register, "pc");
10158 func (stream, dis_style_text, "], ");
10159 func (stream, dis_style_immediate, "#%s%d",
d908c8af 10160 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b 10161 if (! allow_unpredictable)
78933a4a 10162 is_unpredictable = true;
aefd8a40 10163 }
252b5132
RH		 10164 }
10165 else
10166 {
fe56b6ce
NC		 10167 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10168
6576bffe
AB		 10169 func (stream, dis_style_text, "[");
10170 func (stream, dis_style_register, "%s",
252b5132 10171 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10172
c1e26897 10173 if (PRE_BIT_SET)
252b5132 10174 {
c1e26897 10175 if (IMMEDIATE_BIT_SET)
252b5132 10176 {
26d97720
NS		 10177 /* Elide offset for non-writeback
10178 positive zero. */
10179 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10180 || offset)
6576bffe
AB		 10181 {
10182 func (stream, dis_style_text, ", ");
10183 func (stream, dis_style_immediate,
10184 "#%s%d",
10185 (NEGATIVE_BIT_SET ? "-" : ""),
10186 offset);
10187 }
26d97720
NS		 10188
10189 if (NEGATIVE_BIT_SET)
10190 offset = -offset;
945ee430 10191
fe56b6ce 10192 value_in_comment = offset;
252b5132 10193 }
945ee430 10194 else
ff4a8d2b
NC		 10195 {
10196 /* Register Offset or Register Pre-Indexed. */
6576bffe
AB		 10197 func (stream, dis_style_text, ", %s",
10198 NEGATIVE_BIT_SET ? "-" : "");
10199 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10200 arm_regnames[given & 0xf]);
10201
10202 /* Writing back to the register that is the source/
10203 destination of the load/store is unpredictable. */
10204 if (! allow_unpredictable
10205 && WRITEBACK_BIT_SET
10206 && ((given & 0xf) == ((given >> 12) & 0xf)))
78933a4a 10207 is_unpredictable = true;
ff4a8d2b 10208 }
252b5132 10209
6576bffe 10210 func (stream, dis_style_text, "]%s",
c1e26897 10211 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10212 }
945ee430 10213 else
252b5132 10214 {
c1e26897 10215 if (IMMEDIATE_BIT_SET)
252b5132 10216 {
945ee430 10217 /* Immediate Post-indexed. */
aefd8a40 10218 /* PR 10924: Offset must be printed, even if it is zero. */
6576bffe
AB		 10219 func (stream, dis_style_text, "], ");
10220 func (stream, dis_style_immediate, "#%s%d",
26d97720
NS		 10221 NEGATIVE_BIT_SET ? "-" : "", offset);
10222 if (NEGATIVE_BIT_SET)
10223 offset = -offset;
fe56b6ce 10224 value_in_comment = offset;
252b5132 10225 }
945ee430 10226 else
ff4a8d2b
NC		 10227 {
10228 /* Register Post-indexed. */
6576bffe
AB		 10229 func (stream, dis_style_text, "], %s",
10230 NEGATIVE_BIT_SET ? "-" : "");
10231 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10232 arm_regnames[given & 0xf]);
10233
10234 /* Writing back to the register that is the source/
10235 destination of the load/store is unpredictable. */
10236 if (! allow_unpredictable
10237 && (given & 0xf) == ((given >> 12) & 0xf))
78933a4a 10238 is_unpredictable = true;
ff4a8d2b 10239 }
c1e26897 10240
07a28fab
NC		 10241 if (! allow_unpredictable)
10242 {
10243 /* Writeback is automatically implied by post- addressing.
10244 Setting the W bit is unnecessary and ARM specify it as
10245 being unpredictable. */
10246 if (WRITEBACK_BIT_SET
10247 /* Specifying the PC register as the post-indexed
10248 registers is also unpredictable. */
ab8e2090 10249 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
78933a4a 10250 is_unpredictable = true;
07a28fab 10251 }
252b5132
RH		 10252 }
10253 }
10254 break;
b34976b6 10255
252b5132 10256 case 'b':
6b5d3a4d 10257 {
f8b960bc 10258 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10259 bfd_vma target = disp * 4 + pc + 8;
10260 info->print_address_func (target, info);
10261
10262 /* Fill in instruction information. */
10263 info->insn_info_valid = 1;
10264 info->insn_type = dis_branch;
10265 info->target = target;
6b5d3a4d 10266 }
252b5132
RH		 10267 break;
10268
10269 case 'c':
c22aaad1 10270 if (((given >> 28) & 0xf) != 0xe)
6576bffe 10271 func (stream, dis_style_mnemonic, "%s",
c22aaad1 10272 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10273 break;
10274
10275 case 'm':
10276 {
10277 int started = 0;
10278 int reg;
10279
6576bffe 10280 func (stream, dis_style_text, "{");
252b5132
RH		 10281 for (reg = 0; reg < 16; reg++)
10282 if ((given & (1 << reg)) != 0)
10283 {
10284 if (started)
6576bffe 10285 func (stream, dis_style_text, ", ");
252b5132 10286 started = 1;
6576bffe
AB		 10287 func (stream, dis_style_register, "%s",
10288 arm_regnames[reg]);
252b5132 10289 }
6576bffe 10290 func (stream, dis_style_text, "}");
ab8e2090 10291 if (! started)
78933a4a 10292 is_unpredictable = true;
252b5132
RH		 10293 }
10294 break;
10295
37b37b2d 10296 case 'q':
78933a4a 10297 arm_decode_shift (given, func, stream, false);
37b37b2d
RE		 10298 break;
10299
252b5132
RH		 10300 case 'o':
10301 if ((given & 0x02000000) != 0)
10302 {
a415b1cd
JB		 10303 unsigned int rotate = (given & 0xf00) >> 7;
10304 unsigned int immed = (given & 0xff);
10305 unsigned int a, i;
10306
ebd1c6d1
AM		 10307 a = (immed << ((32 - rotate) & 31)
10308 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10309 /* If there is another encoding with smaller rotate,
10310 the rotate should be specified directly. */
10311 for (i = 0; i < 32; i += 2)
ebd1c6d1 10312 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10313 break;
10314
10315 if (i != rotate)
6576bffe
AB		 10316 {
10317 func (stream, dis_style_immediate, "#%d", immed);
10318 func (stream, dis_style_text, ", ");
10319 func (stream, dis_style_immediate, "%d", rotate);
10320 }
a415b1cd 10321 else
6576bffe 10322 func (stream, dis_style_immediate, "#%d", a);
a415b1cd 10323 value_in_comment = a;
252b5132
RH		 10324 }
10325 else
78933a4a 10326 arm_decode_shift (given, func, stream, true);
252b5132
RH		 10327 break;
10328
10329 case 'p':
10330 if ((given & 0x0000f000) == 0x0000f000)
cfbbd403
AV		 10331 func (stream, dis_style_mnemonic, "p");
10332 break;
10333 case 'O':
10334 if ((given & 0x0000f000) == 0x0000f000)
10335 func (stream, dis_style_text,
10336 "\t@ p-variant is OBSOLETE");
252b5132
RH		 10337 break;
10338
10339 case 't':
10340 if ((given & 0x01200000) == 0x00200000)
6576bffe 10341 func (stream, dis_style_mnemonic, "t");
252b5132
RH		 10342 break;
10343
252b5132 10344 case 'A':
05413229
NC		 10345 {
10346 int offset = given & 0xff;
f02232aa 10347
05413229 10348 value_in_comment = offset * 4;
c1e26897 10349 if (NEGATIVE_BIT_SET)
05413229 10350 value_in_comment = - value_in_comment;
f02232aa 10351
6576bffe
AB		 10352 func (stream, dis_style_text, "[%s",
10353 arm_regnames [(given >> 16) & 0xf]);
f02232aa 10354
c1e26897 10355 if (PRE_BIT_SET)
05413229
NC		 10356 {
10357 if (offset)
6576bffe 10358 func (stream, dis_style_text, ", #%d]%s",
d908c8af 10359 (int) value_in_comment,
c1e26897 10360 WRITEBACK_BIT_SET ? "!" : "");
05413229 10361 else
6576bffe 10362 func (stream, dis_style_text, "]");
05413229
NC		 10363 }
10364 else
10365 {
6576bffe 10366 func (stream, dis_style_text, "]");
f02232aa 10367
c1e26897 10368 if (WRITEBACK_BIT_SET)
05413229
NC		 10369 {
10370 if (offset)
6576bffe
AB		 10371 func (stream, dis_style_text,
10372 ", #%d", (int) value_in_comment);
05413229
NC		 10373 }
10374 else
fe56b6ce 10375 {
6576bffe
AB		 10376 func (stream, dis_style_text,
10377 ", {%d}", (int) offset);
fe56b6ce
NC		 10378 value_in_comment = offset;
10379 }
05413229
NC		 10380 }
10381 }
252b5132
RH		 10382 break;
10383
077b8428
NC		 10384 case 'B':
10385 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10386 {
10387 bfd_vma address;
10388 bfd_vma offset = 0;
b34976b6 10389
c1e26897 10390 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10391 /* Is signed, hi bits should be ones. */
10392 offset = (-1) ^ 0x00ffffff;
10393
10394 /* Offset is (SignExtend(offset field)<<2). */
10395 offset += given & 0x00ffffff;
10396 offset <<= 2;
10397 address = offset + pc + 8;
b34976b6 10398
8f06b2d8
PB		 10399 if (given & 0x01000000)
10400 /* H bit allows addressing to 2-byte boundaries. */
10401 address += 2;
b1ee46c5 10402
8f06b2d8 10403 info->print_address_func (address, info);
1d67fe3b
TT		 10404
10405 /* Fill in instruction information. */
10406 info->insn_info_valid = 1;
10407 info->insn_type = dis_branch;
10408 info->target = address;
b1ee46c5 10409 }
b1ee46c5
AH		 10410 break;
10411
252b5132 10412 case 'C':
90ec0d68
MGD		 10413 if ((given & 0x02000200) == 0x200)
10414 {
10415 const char * name;
10416 unsigned sysm = (given & 0x004f0000) >> 16;
10417
10418 sysm |= (given & 0x300) >> 4;
10419 name = banked_regname (sysm);
10420
10421 if (name != NULL)
6576bffe 10422 func (stream, dis_style_register, "%s", name);
90ec0d68 10423 else
6576bffe
AB		 10424 func (stream, dis_style_text,
10425 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10426 }
10427 else
10428 {
6576bffe 10429 func (stream, dis_style_register, "%cPSR_",
90ec0d68 10430 (given & 0x00400000) ? 'S' : 'C');
6576bffe 10431
90ec0d68 10432 if (given & 0x80000)
6576bffe 10433 func (stream, dis_style_register, "f");
90ec0d68 10434 if (given & 0x40000)
6576bffe 10435 func (stream, dis_style_register, "s");
90ec0d68 10436 if (given & 0x20000)
6576bffe 10437 func (stream, dis_style_register, "x");
90ec0d68 10438 if (given & 0x10000)
6576bffe 10439 func (stream, dis_style_register, "c");
90ec0d68 10440 }
252b5132
RH		 10441 break;
10442
62b3e311 10443 case 'U':
43e65147 10444 if ((given & 0xf0) == 0x60)
62b3e311 10445 {
52e7f43d
RE		 10446 switch (given & 0xf)
10447 {
6576bffe
AB		 10448 case 0xf:
10449 func (stream, dis_style_sub_mnemonic, "sy");
10450 break;
52e7f43d 10451 default:
6576bffe
AB		 10452 func (stream, dis_style_immediate, "#%d",
10453 (int) given & 0xf);
52e7f43d
RE		 10454 break;
10455 }
43e65147
L		 10456 }
10457 else
52e7f43d 10458 {
e797f7e0
MGD		 10459 const char * opt = data_barrier_option (given & 0xf);
10460 if (opt != NULL)
6576bffe 10461 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 10462 else
6576bffe
AB		 10463 func (stream, dis_style_immediate,
10464 "#%d", (int) given & 0xf);
62b3e311
PB		 10465 }
10466 break;
10467
b34976b6 10468 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10469 case '5': case '6': case '7': case '8': case '9':
10470 {
16980d0b
JB		 10471 int width;
10472 unsigned long value;
252b5132 10473
16980d0b 10474 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10475
252b5132
RH		 10476 switch (*c)
10477 {
ab8e2090
NC		 10478 case 'R':
10479 if (value == 15)
78933a4a 10480 is_unpredictable = true;
ab8e2090 10481 /* Fall through. */
16980d0b 10482 case 'r':
9eb6c0f1
MGD		 10483 case 'T':
10484 /* We want register + 1 when decoding T. */
10485 if (*c == 'T')
2bddb71a 10486 value = (value + 1) & 0xf;
9eb6c0f1 10487
ff4a8d2b
NC		 10488 if (c[1] == 'u')
10489 {
10490 /* Eat the 'u' character. */
10491 ++ c;
10492
10493 if (u_reg == value)
78933a4a 10494 is_unpredictable = true;
ff4a8d2b
NC		 10495 u_reg = value;
10496 }
10497 if (c[1] == 'U')
10498 {
10499 /* Eat the 'U' character. */
10500 ++ c;
10501
10502 if (U_reg == value)
78933a4a 10503 is_unpredictable = true;
ff4a8d2b
NC		 10504 U_reg = value;
10505 }
6576bffe
AB		 10506 func (stream, dis_style_register, "%s",
10507 arm_regnames[value]);
16980d0b
JB		 10508 break;
10509 case 'd':
6576bffe 10510 func (stream, base_style, "%ld", value);
05413229 10511 value_in_comment = value;
16980d0b
JB		 10512 break;
10513 case 'b':
6576bffe
AB		 10514 func (stream, dis_style_immediate,
10515 "%ld", value * 8);
05413229 10516 value_in_comment = value * 8;
16980d0b
JB		 10517 break;
10518 case 'W':
6576bffe
AB		 10519 func (stream, dis_style_immediate,
10520 "%ld", value + 1);
05413229 10521 value_in_comment = value + 1;
16980d0b
JB		 10522 break;
10523 case 'x':
6576bffe
AB		 10524 func (stream, dis_style_immediate,
10525 "0x%08lx", value);
16980d0b
JB		 10526
10527 /* Some SWI instructions have special
10528 meanings. */
10529 if ((given & 0x0fffffff) == 0x0FF00000)
6576bffe
AB		 10530 func (stream, dis_style_comment_start,
10531 "\t@ IMB");
16980d0b 10532 else if ((given & 0x0fffffff) == 0x0FF00001)
6576bffe
AB		 10533 func (stream, dis_style_comment_start,
10534 "\t@ IMBRange");
16980d0b
JB		 10535 break;
10536 case 'X':
6576bffe
AB		 10537 func (stream, dis_style_immediate,
10538 "%01lx", value & 0xf);
05413229 10539 value_in_comment = value;
252b5132
RH		 10540 break;
10541 case '`':
10542 c++;
16980d0b 10543 if (value == 0)
6576bffe 10544 func (stream, dis_style_text, "%c", *c);
252b5132
RH		 10545 break;
10546 case '\'':
10547 c++;
16980d0b 10548 if (value == ((1ul << width) - 1))
6576bffe 10549 func (stream, base_style, "%c", *c);
252b5132
RH		 10550 break;
10551 case '?':
6576bffe
AB		 10552 func (stream, base_style, "%c",
10553 c[(1 << width) - (int) value]);
16980d0b 10554 c += 1 << width;
252b5132
RH		 10555 break;
10556 default:
10557 abort ();
10558 }
dffaa15c
AM		 10559 }
10560 break;
0dd132b6 10561
dffaa15c
AM		 10562 case 'e':
10563 {
10564 int imm;
0dd132b6 10565
dffaa15c 10566 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6576bffe 10567 func (stream, dis_style_immediate, "%d", imm);
dffaa15c
AM		 10568 value_in_comment = imm;
10569 }
10570 break;
fe56b6ce 10571
dffaa15c
AM		 10572 case 'E':
10573 /* LSB and WIDTH fields of BFI or BFC. The machine-
10574 language instruction encodes LSB and MSB. */
10575 {
10576 long msb = (given & 0x001f0000) >> 16;
10577 long lsb = (given & 0x00000f80) >> 7;
10578 long w = msb - lsb + 1;
0a003adc 10579
dffaa15c 10580 if (w > 0)
6576bffe
AB		 10581 {
10582 func (stream, dis_style_immediate, "#%lu", lsb);
10583 func (stream, dis_style_text, ", ");
10584 func (stream, dis_style_immediate, "#%lu", w);
10585 }
dffaa15c 10586 else
6576bffe
AB		 10587 func (stream, dis_style_text,
10588 "(invalid: %lu:%lu)", lsb, msb);
dffaa15c
AM		 10589 }
10590 break;
90ec0d68 10591
dffaa15c
AM		 10592 case 'R':
10593 /* Get the PSR/banked register name. */
10594 {
10595 const char * name;
10596 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10597
dffaa15c
AM		 10598 sysm |= (given & 0x300) >> 4;
10599 name = banked_regname (sysm);
90ec0d68 10600
dffaa15c 10601 if (name != NULL)
6576bffe 10602 func (stream, dis_style_register, "%s", name);
dffaa15c 10603 else
6576bffe
AB		 10604 func (stream, dis_style_text,
10605 "(UNDEF: %lu)", (unsigned long) sysm);
dffaa15c
AM		 10606 }
10607 break;
fe56b6ce 10608
dffaa15c
AM		 10609 case 'V':
10610 /* 16-bit unsigned immediate from a MOVT or MOVW
10611 instruction, encoded in bits 0:11 and 15:19. */
10612 {
10613 long hi = (given & 0x000f0000) >> 4;
10614 long lo = (given & 0x00000fff);
10615 long imm16 = hi | lo;
0a003adc 10616
6576bffe 10617 func (stream, dis_style_immediate, "#%lu", imm16);
dffaa15c 10618 value_in_comment = imm16;
252b5132 10619 }
dffaa15c
AM		 10620 break;
10621
10622 default:
10623 abort ();
252b5132
RH		 10624 }
10625 }
10626 else
6576bffe
AB		 10627 {
10628
10629 if (*c == '@')
10630 base_style = dis_style_comment_start;
10631
10632 if (*c == '\t')
10633 base_style = dis_style_text;
10634
10635 func (stream, base_style, "%c", *c);
10636 }
252b5132 10637 }
05413229
NC		 10638
10639 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10640 func (stream, dis_style_comment_start, "\t@ 0x%lx",
10641 (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10642
10643 if (is_unpredictable)
6576bffe 10644 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10645
4a5329c6 10646 return;
252b5132
RH		 10647 }
10648 }
6576bffe
AB		 10649 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
10650 (unsigned) given);
0b347048 10651 return;
252b5132
RH		 10652}
10653
4a5329c6 10654/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10655
4a5329c6
ZW		 10656static void
10657print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10658{
6b5d3a4d 10659 const struct opcode16 *insn;
6a51a8a8 10660 void *stream = info->stream;
6576bffe
AB		 10661 fprintf_styled_ftype func = info->fprintf_styled_func;
10662 enum disassembler_style base_style = dis_style_mnemonic;
10663 enum disassembler_style old_base_style = base_style;
252b5132
RH		 10664
10665 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10666 if ((given & insn->mask) == insn->value)
10667 {
05413229 10668 signed long value_in_comment = 0;
6b5d3a4d 10669 const char *c = insn->assembler;
05413229 10670
c19d1205
ZW		 10671 for (; *c; c++)
10672 {
10673 int domaskpc = 0;
10674 int domasklr = 0;
10675
10676 if (*c != '%')
10677 {
6576bffe
AB		 10678 if (*c == '@')
10679 base_style = dis_style_comment_start;
10680
10681 if (*c == '\t')
10682 base_style = dis_style_text;
10683
10684 func (stream, base_style, "%c", *c);
10685
c19d1205
ZW		 10686 continue;
10687 }
252b5132 10688
c19d1205
ZW		 10689 switch (*++c)
10690 {
6576bffe
AB		 10691 case '{':
10692 ++c;
10693 if (*c == '\0')
10694 abort ();
10695 old_base_style = base_style;
10696 base_style = decode_base_style (*c);
10697 ++c;
10698 if (*c != ':')
10699 abort ();
10700 break;
10701
10702 case '}':
10703 base_style = old_base_style;
10704 break;
10705
c19d1205 10706 case '%':
6576bffe 10707 func (stream, base_style, "%%");
c19d1205 10708 break;
b34976b6 10709
c22aaad1
PB		 10710 case 'c':
10711 if (ifthen_state)
6576bffe
AB		 10712 func (stream, dis_style_mnemonic, "%s",
10713 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 10714 break;
10715
10716 case 'C':
10717 if (ifthen_state)
6576bffe
AB		 10718 func (stream, dis_style_mnemonic, "%s",
10719 arm_conditional[IFTHEN_COND]);
c22aaad1 10720 else
6576bffe 10721 func (stream, dis_style_mnemonic, "s");
c22aaad1
PB		 10722 break;
10723
10724 case 'I':
10725 {
10726 unsigned int tmp;
10727
10728 ifthen_next_state = given & 0xff;
10729 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6576bffe
AB		 10730 func (stream, dis_style_mnemonic,
10731 ((given ^ tmp) & 0x10) ? "e" : "t");
10732 func (stream, dis_style_text, "\t");
10733 func (stream, dis_style_sub_mnemonic, "%s",
10734 arm_conditional[(given >> 4) & 0xf]);
c22aaad1
PB		 10735 }
10736 break;
10737
10738 case 'x':
10739 if (ifthen_next_state)
6576bffe
AB		 10740 func (stream, dis_style_comment_start,
10741 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 10742 break;
10743
10744 case 'X':
10745 if (ifthen_state)
6576bffe
AB		 10746 func (stream, dis_style_comment_start,
10747 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 10748 arm_conditional[IFTHEN_COND]);
10749 break;
10750
c19d1205
ZW		 10751 case 'S':
10752 {
10753 long reg;
10754
10755 reg = (given >> 3) & 0x7;
10756 if (given & (1 << 6))
10757 reg += 8;
4f3c3dbb 10758
6576bffe 10759 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 10760 }
10761 break;
baf0cc5e 10762
c19d1205 10763 case 'D':
4f3c3dbb 10764 {
c19d1205
ZW		 10765 long reg;
10766
10767 reg = given & 0x7;
10768 if (given & (1 << 7))
10769 reg += 8;
10770
6576bffe 10771 func (stream, dis_style_register, "%s", arm_regnames[reg]);
4f3c3dbb 10772 }
c19d1205
ZW		 10773 break;
10774
10775 case 'N':
10776 if (given & (1 << 8))
10777 domasklr = 1;
10778 /* Fall through. */
10779 case 'O':
10780 if (*c == 'O' && (given & (1 << 8)))
10781 domaskpc = 1;
10782 /* Fall through. */
10783 case 'M':
10784 {
10785 int started = 0;
10786 int reg;
10787
6576bffe 10788 func (stream, dis_style_text, "{");
c19d1205
ZW		 10789
10790 /* It would be nice if we could spot
10791 ranges, and generate the rS-rE format: */
10792 for (reg = 0; (reg < 8); reg++)
10793 if ((given & (1 << reg)) != 0)
10794 {
10795 if (started)
6576bffe 10796 func (stream, dis_style_text, ", ");
c19d1205 10797 started = 1;
6576bffe
AB		 10798 func (stream, dis_style_register, "%s",
10799 arm_regnames[reg]);
c19d1205
ZW		 10800 }
10801
10802 if (domasklr)
10803 {
10804 if (started)
6576bffe 10805 func (stream, dis_style_text, ", ");
c19d1205 10806 started = 1;
6576bffe
AB		 10807 func (stream, dis_style_register, "%s",
10808 arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10809 }
10810
10811 if (domaskpc)
10812 {
10813 if (started)
6576bffe
AB		 10814 func (stream, dis_style_text, ", ");
10815 func (stream, dis_style_register, "%s",
10816 arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10817 }
10818
6576bffe 10819 func (stream, dis_style_text, "}");
c19d1205
ZW		 10820 }
10821 break;
10822
4547cb56
NC		 10823 case 'W':
10824 /* Print writeback indicator for a LDMIA. We are doing a
10825 writeback if the base register is not in the register
10826 mask. */
10827 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6576bffe 10828 func (stream, dis_style_text, "!");
dffaa15c 10829 break;
4547cb56 10830
c19d1205
ZW		 10831 case 'b':
10832 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10833 {
10834 bfd_vma address = (pc + 4
10835 + ((given & 0x00f8) >> 2)
10836 + ((given & 0x0200) >> 3));
10837 info->print_address_func (address, info);
1d67fe3b
TT		 10838
10839 /* Fill in instruction information. */
10840 info->insn_info_valid = 1;
10841 info->insn_type = dis_branch;
10842 info->target = address;
c19d1205
ZW		 10843 }
10844 break;
10845
10846 case 's':
10847 /* Right shift immediate -- bits 6..10; 1-31 print
10848 as themselves, 0 prints as 32. */
10849 {
10850 long imm = (given & 0x07c0) >> 6;
10851 if (imm == 0)
10852 imm = 32;
6576bffe 10853 func (stream, dis_style_immediate, "#%ld", imm);
c19d1205
ZW		 10854 }
10855 break;
10856
10857 case '0': case '1': case '2': case '3': case '4':
10858 case '5': case '6': case '7': case '8': case '9':
10859 {
10860 int bitstart = *c++ - '0';
10861 int bitend = 0;
10862
10863 while (*c >= '0' && *c <= '9')
10864 bitstart = (bitstart * 10) + *c++ - '0';
10865
10866 switch (*c)
10867 {
10868 case '-':
10869 {
f8b960bc 10870 bfd_vma reg;
c19d1205
ZW		 10871
10872 c++;
10873 while (*c >= '0' && *c <= '9')
10874 bitend = (bitend * 10) + *c++ - '0';
10875 if (!bitend)
10876 abort ();
10877 reg = given >> bitstart;
459cde81 10878 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
ff4a8d2b 10879
c19d1205
ZW		 10880 switch (*c)
10881 {
10882 case 'r':
6576bffe
AB		 10883 func (stream, dis_style_register, "%s",
10884 arm_regnames[reg]);
c19d1205
ZW		 10885 break;
10886
10887 case 'd':
6576bffe
AB		 10888 func (stream, dis_style_immediate, "%ld",
10889 (long) reg);
05413229 10890 value_in_comment = reg;
c19d1205
ZW		 10891 break;
10892
10893 case 'H':
6576bffe
AB		 10894 func (stream, dis_style_immediate, "%ld",
10895 (long) (reg << 1));
05413229 10896 value_in_comment = reg << 1;
c19d1205
ZW		 10897 break;
10898
10899 case 'W':
6576bffe
AB		 10900 func (stream, dis_style_immediate, "%ld",
10901 (long) (reg << 2));
05413229 10902 value_in_comment = reg << 2;
c19d1205
ZW		 10903 break;
10904
10905 case 'a':
10906 /* PC-relative address -- the bottom two
10907 bits of the address are dropped
10908 before the calculation. */
10909 info->print_address_func
10910 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10911 value_in_comment = 0;
c19d1205
ZW		 10912 break;
10913
10914 case 'x':
6576bffe
AB		 10915 func (stream, dis_style_immediate, "0x%04lx",
10916 (long) reg);
c19d1205
ZW		 10917 break;
10918
c19d1205
ZW		 10919 case 'B':
10920 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 10921 bfd_vma target = reg * 2 + pc + 4;
10922 info->print_address_func (target, info);
05413229 10923 value_in_comment = 0;
1d67fe3b
TT		 10924
10925 /* Fill in instruction information. */
10926 info->insn_info_valid = 1;
10927 info->insn_type = dis_branch;
10928 info->target = target;
c19d1205
ZW		 10929 break;
10930
10931 case 'c':
6576bffe
AB		 10932 func (stream, dis_style_mnemonic, "%s",
10933 arm_conditional [reg]);
c19d1205
ZW		 10934 break;
10935
10936 default:
10937 abort ();
10938 }
10939 }
10940 break;
10941
10942 case '\'':
10943 c++;
10944 if ((given & (1 << bitstart)) != 0)
6576bffe 10945 func (stream, base_style, "%c", *c);
c19d1205
ZW		 10946 break;
10947
10948 case '?':
10949 ++c;
10950 if ((given & (1 << bitstart)) != 0)
6576bffe 10951 func (stream, base_style, "%c", *c++);
c19d1205 10952 else
6576bffe 10953 func (stream, base_style, "%c", *++c);
c19d1205
ZW		 10954 break;
10955
10956 default:
10957 abort ();
10958 }
10959 }
10960 break;
10961
10962 default:
10963 abort ();
10964 }
10965 }
05413229
NC		 10966
10967 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10968 func (stream, dis_style_comment_start,
10969 "\t@ 0x%lx", value_in_comment);
4a5329c6 10970 return;
c19d1205
ZW		 10971 }
10972
10973 /* No match. */
6576bffe
AB		 10974 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
10975 (unsigned) given);
0b347048 10976 return;
c19d1205
ZW		 10977}
10978
62b3e311 10979/* Return the name of an V7M special register. */
fe56b6ce 10980
62b3e311
PB		 10981static const char *
10982psr_name (int regno)
10983{
10984 switch (regno)
10985 {
1a336194
TP		 10986 case 0x0: return "APSR";
10987 case 0x1: return "IAPSR";
10988 case 0x2: return "EAPSR";
10989 case 0x3: return "PSR";
10990 case 0x5: return "IPSR";
10991 case 0x6: return "EPSR";
10992 case 0x7: return "IEPSR";
10993 case 0x8: return "MSP";
10994 case 0x9: return "PSP";
10995 case 0xa: return "MSPLIM";
10996 case 0xb: return "PSPLIM";
10997 case 0x10: return "PRIMASK";
10998 case 0x11: return "BASEPRI";
10999 case 0x12: return "BASEPRI_MAX";
11000 case 0x13: return "FAULTMASK";
11001 case 0x14: return "CONTROL";
1fb5ccd6
AV		 11002 case 0x20: return "PAC_KEY_P_0";
11003 case 0x21: return "PAC_KEY_P_1";
11004 case 0x22: return "PAC_KEY_P_2";
11005 case 0x23: return "PAC_KEY_P_3";
11006 case 0x24: return "PAC_KEY_U_0";
11007 case 0x25: return "PAC_KEY_U_1";
11008 case 0x26: return "PAC_KEY_U_2";
11009 case 0x27: return "PAC_KEY_U_3";
16a1fa25
TP		 11010 case 0x88: return "MSP_NS";
11011 case 0x89: return "PSP_NS";
1a336194
TP		 11012 case 0x8a: return "MSPLIM_NS";
11013 case 0x8b: return "PSPLIM_NS";
11014 case 0x90: return "PRIMASK_NS";
11015 case 0x91: return "BASEPRI_NS";
11016 case 0x93: return "FAULTMASK_NS";
11017 case 0x94: return "CONTROL_NS";
11018 case 0x98: return "SP_NS";
1fb5ccd6
AV		 11019 case 0xa0: return "PAC_KEY_P_0_NS";
11020 case 0xa1: return "PAC_KEY_P_1_NS";
11021 case 0xa2: return "PAC_KEY_P_2_NS";
11022 case 0xa3: return "PAC_KEY_P_3_NS";
11023 case 0xa4: return "PAC_KEY_U_0_NS";
11024 case 0xa5: return "PAC_KEY_U_1_NS";
11025 case 0xa6: return "PAC_KEY_U_2_NS";
11026 case 0xa7: return "PAC_KEY_U_3_NS";
62b3e311
PB		 11027 default: return "<unknown>";
11028 }
11029}
11030
4a5329c6
ZW		 11031/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
11032
11033static void
11034print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 11035{
6b5d3a4d 11036 const struct opcode32 *insn;
c19d1205 11037 void *stream = info->stream;
6576bffe 11038 fprintf_styled_ftype func = info->fprintf_styled_func;
1fb5ccd6 11039 bool is_mve = is_v81m_architecture (info);
6576bffe
AB		 11040 enum disassembler_style base_style = dis_style_mnemonic;
11041 enum disassembler_style old_base_style = base_style;
c19d1205 11042
78933a4a 11043 if (print_insn_coprocessor (pc, info, given, true))
16980d0b
JB		 11044 return;
11045
78933a4a 11046 if (!is_mve && print_insn_neon (info, given, true))
73cd51e5
AV		 11047 return;
11048
11049 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 11050 return;
11051
78933a4a 11052 if (print_insn_cde (info, given, true))
4934a27c
MM		 11053 return;
11054
78933a4a 11055 if (print_insn_generic_coprocessor (pc, info, given, true))
33593eaf
MM		 11056 return;
11057
c19d1205
ZW		 11058 for (insn = thumb32_opcodes; insn->assembler; insn++)
11059 if ((given & insn->mask) == insn->value)
11060 {
78933a4a
AM		 11061 bool is_clrm = false;
11062 bool is_unpredictable = false;
05413229 11063 signed long value_in_comment = 0;
6b5d3a4d 11064 const char *c = insn->assembler;
05413229 11065
c19d1205
ZW		 11066 for (; *c; c++)
11067 {
11068 if (*c != '%')
11069 {
6576bffe
AB		 11070 if (*c == '@')
11071 base_style = dis_style_comment_start;
11072 if (*c == '\t')
11073 base_style = dis_style_text;
11074 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11075 continue;
11076 }
11077
11078 switch (*++c)
11079 {
6576bffe
AB		 11080 case '{':
11081 ++c;
11082 if (*c == '\0')
11083 abort ();
11084 old_base_style = base_style;
11085 base_style = decode_base_style (*c);
11086 ++c;
11087 if (*c != ':')
11088 abort ();
11089 break;
11090
11091 case '}':
11092 base_style = old_base_style;
11093 break;
11094
c19d1205 11095 case '%':
6576bffe 11096 func (stream, base_style, "%%");
c19d1205
ZW		 11097 break;
11098
c22aaad1
PB		 11099 case 'c':
11100 if (ifthen_state)
6576bffe
AB		 11101 func (stream, dis_style_mnemonic, "%s",
11102 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 11103 break;
11104
11105 case 'x':
11106 if (ifthen_next_state)
6576bffe
AB		 11107 func (stream, dis_style_comment_start,
11108 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 11109 break;
11110
11111 case 'X':
11112 if (ifthen_state)
6576bffe
AB		 11113 func (stream, dis_style_comment_start,
11114 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 11115 arm_conditional[IFTHEN_COND]);
11116 break;
11117
c19d1205
ZW		 11118 case 'I':
11119 {
11120 unsigned int imm12 = 0;
fe56b6ce 11121
c19d1205
ZW		 11122 imm12 |= (given & 0x000000ffu);
11123 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 11124 imm12 |= (given & 0x04000000u) >> 15;
6576bffe 11125 func (stream, dis_style_immediate, "#%u", imm12);
fe56b6ce 11126 value_in_comment = imm12;
c19d1205
ZW		 11127 }
11128 break;
11129
11130 case 'M':
11131 {
11132 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 11133
c19d1205
ZW		 11134 bits |= (given & 0x000000ffu);
11135 bits |= (given & 0x00007000u) >> 4;
11136 bits |= (given & 0x04000000u) >> 15;
11137 imm8 = (bits & 0x0ff);
11138 mod = (bits & 0xf00) >> 8;
11139 switch (mod)
11140 {
11141 case 0: imm = imm8; break;
c1e26897
NC		 11142 case 1: imm = ((imm8 << 16) | imm8); break;
11143 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11144 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 11145 default:
11146 mod = (bits & 0xf80) >> 7;
11147 imm8 = (bits & 0x07f) | 0x80;
11148 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11149 }
6576bffe 11150 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11151 value_in_comment = imm;
c19d1205
ZW		 11152 }
11153 break;
43e65147 11154
c19d1205
ZW		 11155 case 'J':
11156 {
11157 unsigned int imm = 0;
fe56b6ce 11158
c19d1205
ZW		 11159 imm |= (given & 0x000000ffu);
11160 imm |= (given & 0x00007000u) >> 4;
11161 imm |= (given & 0x04000000u) >> 15;
11162 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11163 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11164 value_in_comment = imm;
c19d1205
ZW		 11165 }
11166 break;
11167
11168 case 'K':
11169 {
11170 unsigned int imm = 0;
fe56b6ce 11171
c19d1205
ZW		 11172 imm |= (given & 0x000f0000u) >> 16;
11173 imm |= (given & 0x00000ff0u) >> 0;
11174 imm |= (given & 0x0000000fu) << 12;
6576bffe 11175 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11176 value_in_comment = imm;
c19d1205
ZW		 11177 }
11178 break;
11179
74db7efb
NC		 11180 case 'H':
11181 {
11182 unsigned int imm = 0;
11183
11184 imm |= (given & 0x000f0000u) >> 4;
11185 imm |= (given & 0x00000fffu) >> 0;
6576bffe 11186 func (stream, dis_style_immediate, "#%u", imm);
74db7efb
NC		 11187 value_in_comment = imm;
11188 }
11189 break;
11190
90ec0d68
MGD		 11191 case 'V':
11192 {
11193 unsigned int imm = 0;
11194
11195 imm |= (given & 0x00000fffu);
11196 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11197 func (stream, dis_style_immediate, "#%u", imm);
90ec0d68
MGD		 11198 value_in_comment = imm;
11199 }
11200 break;
11201
c19d1205
ZW		 11202 case 'S':
11203 {
11204 unsigned int reg = (given & 0x0000000fu);
11205 unsigned int stp = (given & 0x00000030u) >> 4;
11206 unsigned int imm = 0;
11207 imm |= (given & 0x000000c0u) >> 6;
11208 imm |= (given & 0x00007000u) >> 10;
11209
6576bffe 11210 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 11211 switch (stp)
11212 {
11213 case 0:
11214 if (imm > 0)
6576bffe
AB		 11215 {
11216 func (stream, dis_style_text, ", ");
11217 func (stream, dis_style_sub_mnemonic, "lsl ");
11218 func (stream, dis_style_immediate, "#%u", imm);
11219 }
c19d1205
ZW		 11220 break;
11221
11222 case 1:
11223 if (imm == 0)
11224 imm = 32;
6576bffe
AB		 11225 func (stream, dis_style_text, ", ");
11226 func (stream, dis_style_sub_mnemonic, "lsr ");
11227 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11228 break;
11229
11230 case 2:
11231 if (imm == 0)
11232 imm = 32;
6576bffe
AB		 11233 func (stream, dis_style_text, ", ");
11234 func (stream, dis_style_sub_mnemonic, "asr ");
11235 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11236 break;
11237
11238 case 3:
11239 if (imm == 0)
6576bffe
AB		 11240 {
11241 func (stream, dis_style_text, ", ");
11242 func (stream, dis_style_sub_mnemonic, "rrx");
11243 }
c19d1205 11244 else
6576bffe
AB		 11245 {
11246 func (stream, dis_style_text, ", ");
11247 func (stream, dis_style_sub_mnemonic, "ror ");
11248 func (stream, dis_style_immediate, "#%u", imm);
11249 }
c19d1205
ZW		 11250 }
11251 }
11252 break;
11253
11254 case 'a':
11255 {
11256 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11257 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11258 unsigned int op = (given & 0x00000f00) >> 8;
11259 unsigned int i12 = (given & 0x00000fff);
11260 unsigned int i8 = (given & 0x000000ff);
78933a4a 11261 bool writeback = false, postind = false;
f8b960bc 11262 bfd_vma offset = 0;
c19d1205 11263
6576bffe
AB		 11264 func (stream, dis_style_text, "[");
11265 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
05413229
NC		 11266 if (U) /* 12-bit positive immediate offset. */
11267 {
11268 offset = i12;
11269 if (Rn != 15)
11270 value_in_comment = offset;
11271 }
11272 else if (Rn == 15) /* 12-bit negative immediate offset. */
11273 offset = - (int) i12;
11274 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11275 {
11276 unsigned int Rm = (i8 & 0x0f);
11277 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11278
6576bffe
AB		 11279 func (stream, dis_style_text, ", ");
11280 func (stream, dis_style_register, "%s",
11281 arm_regnames[Rm]);
c19d1205 11282 if (sh)
6576bffe
AB		 11283 {
11284 func (stream, dis_style_text, ", ");
11285 func (stream, dis_style_sub_mnemonic, "lsl ");
11286 func (stream, dis_style_immediate, "#%u", sh);
11287 }
11288 func (stream, dis_style_text, "]");
c19d1205
ZW		 11289 break;
11290 }
11291 else switch (op)
11292 {
05413229 11293 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11294 offset = i8;
11295 break;
11296
05413229 11297 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11298 offset = -i8;
11299 break;
11300
05413229 11301 case 0xF: /* 8-bit + preindex with wb. */
c19d1205 11302 offset = i8;
78933a4a 11303 writeback = true;
c19d1205
ZW		 11304 break;
11305
05413229 11306 case 0xD: /* 8-bit - preindex with wb. */
c19d1205 11307 offset = -i8;
78933a4a 11308 writeback = true;
c19d1205
ZW		 11309 break;
11310
05413229 11311 case 0xB: /* 8-bit + postindex. */
c19d1205 11312 offset = i8;
78933a4a 11313 postind = true;
c19d1205
ZW		 11314 break;
11315
05413229 11316 case 0x9: /* 8-bit - postindex. */
c19d1205 11317 offset = -i8;
78933a4a 11318 postind = true;
c19d1205
ZW		 11319 break;
11320
11321 default:
6576bffe 11322 func (stream, dis_style_text, ", <undefined>]");
c19d1205
ZW		 11323 goto skip;
11324 }
11325
11326 if (postind)
6576bffe
AB		 11327 {
11328 func (stream, dis_style_text, "], ");
11329 func (stream, dis_style_immediate, "#%d", (int) offset);
11330 }
c19d1205
ZW		 11331 else
11332 {
11333 if (offset)
6576bffe
AB		 11334 {
11335 func (stream, dis_style_text, ", ");
11336 func (stream, dis_style_immediate, "#%d",
11337 (int) offset);
11338 }
11339 func (stream, dis_style_text, writeback ? "]!" : "]");
c19d1205
ZW		 11340 }
11341
11342 if (Rn == 15)
11343 {
6576bffe 11344 func (stream, dis_style_comment_start, "\t@ ");
c19d1205
ZW		 11345 info->print_address_func (((pc + 4) & ~3) + offset, info);
11346 }
11347 }
11348 skip:
11349 break;
11350
11351 case 'A':
11352 {
c1e26897
NC		 11353 unsigned int U = ! NEGATIVE_BIT_SET;
11354 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11355 unsigned int Rn = (given & 0x000f0000) >> 16;
11356 unsigned int off = (given & 0x000000ff);
11357
6576bffe
AB		 11358 func (stream, dis_style_text, "[");
11359 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
c1e26897
NC		 11360
11361 if (PRE_BIT_SET)
c19d1205
ZW		 11362 {
11363 if (off || !U)
05413229 11364 {
6576bffe
AB		 11365 func (stream, dis_style_text, ", ");
11366 func (stream, dis_style_immediate, "#%c%u",
11367 U ? '+' : '-', off * 4);
fe50e98c 11368 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11369 }
6576bffe 11370 func (stream, dis_style_text, "]");
c19d1205 11371 if (W)
6576bffe 11372 func (stream, dis_style_text, "!");
c19d1205
ZW		 11373 }
11374 else
11375 {
6576bffe 11376 func (stream, dis_style_text, "], ");
c19d1205 11377 if (W)
05413229 11378 {
6576bffe
AB		 11379 func (stream, dis_style_immediate, "#%c%u",
11380 U ? '+' : '-', off * 4);
fe50e98c 11381 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11382 }
c19d1205 11383 else
fe56b6ce 11384 {
6576bffe
AB		 11385 func (stream, dis_style_text, "{");
11386 func (stream, dis_style_immediate, "%u", off);
11387 func (stream, dis_style_text, "}");
fe56b6ce
NC		 11388 value_in_comment = off;
11389 }
c19d1205
ZW		 11390 }
11391 }
11392 break;
11393
11394 case 'w':
11395 {
11396 unsigned int Sbit = (given & 0x01000000) >> 24;
11397 unsigned int type = (given & 0x00600000) >> 21;
05413229 11398
c19d1205
ZW		 11399 switch (type)
11400 {
6576bffe
AB		 11401 case 0:
11402 func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11403 break;
11404 case 1:
11405 func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11406 break;
c19d1205
ZW		 11407 case 2:
11408 if (Sbit)
6576bffe 11409 func (stream, dis_style_text, "??");
c19d1205
ZW		 11410 break;
11411 case 3:
6576bffe 11412 func (stream, dis_style_text, "??");
c19d1205
ZW		 11413 break;
11414 }
11415 }
11416 break;
11417
4b5a202f 11418 case 'n':
78933a4a 11419 is_clrm = true;
4b5a202f 11420 /* Fall through. */
c19d1205
ZW		 11421 case 'm':
11422 {
11423 int started = 0;
11424 int reg;
11425
6576bffe 11426 func (stream, dis_style_text, "{");
c19d1205
ZW		 11427 for (reg = 0; reg < 16; reg++)
11428 if ((given & (1 << reg)) != 0)
11429 {
11430 if (started)
6576bffe 11431 func (stream, dis_style_text, ", ");
c19d1205 11432 started = 1;
4b5a202f 11433 if (is_clrm && reg == 13)
6576bffe
AB		 11434 func (stream, dis_style_text, "(invalid: %s)",
11435 arm_regnames[reg]);
4b5a202f 11436 else if (is_clrm && reg == 15)
6576bffe 11437 func (stream, dis_style_register, "%s", "APSR");
4b5a202f 11438 else
6576bffe
AB		 11439 func (stream, dis_style_register, "%s",
11440 arm_regnames[reg]);
c19d1205 11441 }
6576bffe 11442 func (stream, dis_style_text, "}");
c19d1205
ZW		 11443 }
11444 break;
11445
11446 case 'E':
11447 {
11448 unsigned int msb = (given & 0x0000001f);
11449 unsigned int lsb = 0;
fe56b6ce 11450
c19d1205
ZW		 11451 lsb |= (given & 0x000000c0u) >> 6;
11452 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11453 func (stream, dis_style_immediate, "#%u", lsb);
11454 func (stream, dis_style_text, ", ");
11455 func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
c19d1205
ZW		 11456 }
11457 break;
11458
11459 case 'F':
11460 {
11461 unsigned int width = (given & 0x0000001f) + 1;
11462 unsigned int lsb = 0;
fe56b6ce 11463
c19d1205
ZW		 11464 lsb |= (given & 0x000000c0u) >> 6;
11465 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11466 func (stream, dis_style_immediate, "#%u", lsb);
11467 func (stream, dis_style_text, ", ");
11468 func (stream, dis_style_immediate, "#%u", width);
c19d1205
ZW		 11469 }
11470 break;
11471
e12437dc
AV		 11472 case 'G':
11473 {
11474 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
6576bffe 11475 func (stream, dis_style_immediate, "%x", boff);
e12437dc
AV		 11476 }
11477 break;
11478
e5d6e09e
AV		 11479 case 'W':
11480 {
11481 unsigned int immA = (given & 0x001f0000u) >> 16;
11482 unsigned int immB = (given & 0x000007feu) >> 1;
11483 unsigned int immC = (given & 0x00000800u) >> 11;
11484 bfd_vma offset = 0;
11485
11486 offset |= immA << 12;
11487 offset |= immB << 2;
11488 offset |= immC << 1;
11489 /* Sign extend. */
11490 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11491
11492 info->print_address_func (pc + 4 + offset, info);
11493 }
11494 break;
11495
1caf72a5
AV		 11496 case 'Y':
11497 {
11498 unsigned int immA = (given & 0x007f0000u) >> 16;
11499 unsigned int immB = (given & 0x000007feu) >> 1;
11500 unsigned int immC = (given & 0x00000800u) >> 11;
11501 bfd_vma offset = 0;
11502
11503 offset |= immA << 12;
11504 offset |= immB << 2;
11505 offset |= immC << 1;
11506 /* Sign extend. */
11507 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11508
11509 info->print_address_func (pc + 4 + offset, info);
11510 }
11511 break;
11512
1889da70
AV		 11513 case 'Z':
11514 {
11515 unsigned int immA = (given & 0x00010000u) >> 16;
11516 unsigned int immB = (given & 0x000007feu) >> 1;
11517 unsigned int immC = (given & 0x00000800u) >> 11;
11518 bfd_vma offset = 0;
11519
11520 offset |= immA << 12;
11521 offset |= immB << 2;
11522 offset |= immC << 1;
11523 /* Sign extend. */
11524 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11525
11526 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11527
11528 unsigned int T = (given & 0x00020000u) >> 17;
11529 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11530 unsigned int boffset = (T == 1) ? 4 : 2;
6576bffe
AB		 11531 func (stream, dis_style_text, ", ");
11532 func (stream, dis_style_immediate, "%x",
11533 endoffset + boffset);
1889da70
AV		 11534 }
11535 break;
11536
60f993ce
AV		 11537 case 'Q':
11538 {
11539 unsigned int immh = (given & 0x000007feu) >> 1;
11540 unsigned int imml = (given & 0x00000800u) >> 11;
11541 bfd_vma imm32 = 0;
11542
11543 imm32 |= immh << 2;
11544 imm32 |= imml << 1;
11545
11546 info->print_address_func (pc + 4 + imm32, info);
11547 }
11548 break;
11549
11550 case 'P':
11551 {
11552 unsigned int immh = (given & 0x000007feu) >> 1;
11553 unsigned int imml = (given & 0x00000800u) >> 11;
11554 bfd_vma imm32 = 0;
11555
11556 imm32 |= immh << 2;
11557 imm32 |= imml << 1;
11558
11559 info->print_address_func (pc + 4 - imm32, info);
11560 }
11561 break;
11562
c19d1205
ZW		 11563 case 'b':
11564 {
11565 unsigned int S = (given & 0x04000000u) >> 26;
11566 unsigned int J1 = (given & 0x00002000u) >> 13;
11567 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11568 bfd_vma offset = 0;
c19d1205
ZW		 11569
11570 offset |= !S << 20;
11571 offset |= J2 << 19;
11572 offset |= J1 << 18;
11573 offset |= (given & 0x003f0000) >> 4;
11574 offset |= (given & 0x000007ff) << 1;
11575 offset -= (1 << 20);
11576
1d67fe3b
TT		 11577 bfd_vma target = pc + 4 + offset;
11578 info->print_address_func (target, info);
11579
11580 /* Fill in instruction information. */
11581 info->insn_info_valid = 1;
11582 info->insn_type = dis_branch;
11583 info->target = target;
c19d1205
ZW		 11584 }
11585 break;
11586
11587 case 'B':
11588 {
11589 unsigned int S = (given & 0x04000000u) >> 26;
11590 unsigned int I1 = (given & 0x00002000u) >> 13;
11591 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11592 bfd_vma offset = 0;
c19d1205
ZW		 11593
11594 offset |= !S << 24;
11595 offset |= !(I1 ^ S) << 23;
11596 offset |= !(I2 ^ S) << 22;
11597 offset |= (given & 0x03ff0000u) >> 4;
11598 offset |= (given & 0x000007ffu) << 1;
11599 offset -= (1 << 24);
36b0c57d 11600 offset += pc + 4;
c19d1205 11601
36b0c57d
PB		 11602 /* BLX target addresses are always word aligned. */
11603 if ((given & 0x00001000u) == 0)
11604 offset &= ~2u;
11605
11606 info->print_address_func (offset, info);
1d67fe3b
TT		 11607
11608 /* Fill in instruction information. */
11609 info->insn_info_valid = 1;
11610 info->insn_type = dis_branch;
11611 info->target = offset;
c19d1205
ZW		 11612 }
11613 break;
11614
11615 case 's':
11616 {
11617 unsigned int shift = 0;
fe56b6ce 11618
c19d1205
ZW		 11619 shift |= (given & 0x000000c0u) >> 6;
11620 shift |= (given & 0x00007000u) >> 10;
c1e26897 11621 if (WRITEBACK_BIT_SET)
6576bffe
AB		 11622 {
11623 func (stream, dis_style_text, ", ");
11624 func (stream, dis_style_sub_mnemonic, "asr ");
11625 func (stream, dis_style_immediate, "#%u", shift);
11626 }
c19d1205 11627 else if (shift)
6576bffe
AB		 11628 {
11629 func (stream, dis_style_text, ", ");
11630 func (stream, dis_style_sub_mnemonic, "lsl ");
11631 func (stream, dis_style_immediate, "#%u", shift);
11632 }
c19d1205
ZW		 11633 /* else print nothing - lsl #0 */
11634 }
11635 break;
11636
11637 case 'R':
11638 {
11639 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11640
c19d1205 11641 if (rot)
6576bffe
AB		 11642 {
11643 func (stream, dis_style_text, ", ");
11644 func (stream, dis_style_sub_mnemonic, "ror ");
11645 func (stream, dis_style_immediate, "#%u", rot * 8);
11646 }
c19d1205
ZW		 11647 }
11648 break;
11649
62b3e311 11650 case 'U':
43e65147 11651 if ((given & 0xf0) == 0x60)
62b3e311 11652 {
52e7f43d
RE		 11653 switch (given & 0xf)
11654 {
6576bffe
AB		 11655 case 0xf:
11656 func (stream, dis_style_sub_mnemonic, "sy");
11657 break;
11658 default:
11659 func (stream, dis_style_immediate, "#%d",
11660 (int) given & 0xf);
11661 break;
52e7f43d 11662 }
62b3e311 11663 }
43e65147 11664 else
52e7f43d 11665 {
e797f7e0
MGD		 11666 const char * opt = data_barrier_option (given & 0xf);
11667 if (opt != NULL)
6576bffe 11668 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 11669 else
6576bffe
AB		 11670 func (stream, dis_style_immediate, "#%d",
11671 (int) given & 0xf);
52e7f43d 11672 }
62b3e311
PB		 11673 break;
11674
11675 case 'C':
11676 if ((given & 0xff) == 0)
11677 {
6576bffe
AB		 11678 func (stream, dis_style_register, "%cPSR_",
11679 (given & 0x100000) ? 'S' : 'C');
11680
62b3e311 11681 if (given & 0x800)
6576bffe 11682 func (stream, dis_style_register, "f");
62b3e311 11683 if (given & 0x400)
6576bffe 11684 func (stream, dis_style_register, "s");
62b3e311 11685 if (given & 0x200)
6576bffe 11686 func (stream, dis_style_register, "x");
62b3e311 11687 if (given & 0x100)
6576bffe 11688 func (stream, dis_style_register, "c");
62b3e311 11689 }
1fb5ccd6
AV		 11690 else if (is_v81m_architecture (info))
11691 func (stream, dis_style_register, "%s",
11692 psr_name (given & 0xff));
11693
90ec0d68
MGD		 11694 else if ((given & 0x20) == 0x20)
11695 {
11696 char const* name;
11697 unsigned sysm = (given & 0xf00) >> 8;
11698
11699 sysm |= (given & 0x30);
11700 sysm |= (given & 0x00100000) >> 14;
11701 name = banked_regname (sysm);
43e65147 11702
90ec0d68 11703 if (name != NULL)
6576bffe 11704 func (stream, dis_style_register, "%s", name);
90ec0d68 11705 else
6576bffe
AB		 11706 func (stream, dis_style_text,
11707 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11708 }
62b3e311
PB		 11709 else
11710 {
6576bffe
AB		 11711 func (stream, dis_style_register, "%s",
11712 psr_name (given & 0xff));
62b3e311
PB		 11713 }
11714 break;
11715
11716 case 'D':
1fb5ccd6
AV		 11717 if (is_v81m_architecture (info))
11718 func (stream, dis_style_register, "%s",
11719 psr_name (given & 0xff));
11720 else if (((given & 0xff) == 0)
11721 || ((given & 0x20) == 0x20))
90ec0d68
MGD		 11722 {
11723 char const* name;
11724 unsigned sm = (given & 0xf0000) >> 16;
11725
11726 sm |= (given & 0x30);
11727 sm |= (given & 0x00100000) >> 14;
11728 name = banked_regname (sm);
11729
11730 if (name != NULL)
6576bffe 11731 func (stream, dis_style_register, "%s", name);
90ec0d68 11732 else
6576bffe
AB		 11733 func (stream, dis_style_text,
11734 "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11735 }
62b3e311 11736 else
6576bffe
AB		 11737 func (stream, dis_style_register, "%s",
11738 psr_name (given & 0xff));
62b3e311
PB		 11739 break;
11740
c19d1205
ZW		 11741 case '0': case '1': case '2': case '3': case '4':
11742 case '5': case '6': case '7': case '8': case '9':
11743 {
16980d0b
JB		 11744 int width;
11745 unsigned long val;
c19d1205 11746
16980d0b 11747 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11748
c19d1205
ZW		 11749 switch (*c)
11750 {
d052b9b7
AV		 11751 case 's':
11752 if (val <= 3)
6576bffe
AB		 11753 func (stream, dis_style_mnemonic, "%s",
11754 mve_vec_sizename[val]);
d052b9b7 11755 else
6576bffe 11756 func (stream, dis_style_text, "<undef size>");
d052b9b7
AV		 11757 break;
11758
05413229 11759 case 'd':
6576bffe 11760 func (stream, base_style, "%lu", val);
05413229
NC		 11761 value_in_comment = val;
11762 break;
ff4a8d2b 11763
f0fba320 11764 case 'D':
6576bffe 11765 func (stream, dis_style_immediate, "%lu", val + 1);
f0fba320
RL		 11766 value_in_comment = val + 1;
11767 break;
11768
05413229 11769 case 'W':
6576bffe 11770 func (stream, dis_style_immediate, "%lu", val * 4);
05413229
NC		 11771 value_in_comment = val * 4;
11772 break;
ff4a8d2b 11773
f1c7f421
AV		 11774 case 'S':
11775 if (val == 13)
78933a4a 11776 is_unpredictable = true;
f1c7f421 11777 /* Fall through. */
ff4a8d2b
NC		 11778 case 'R':
11779 if (val == 15)
78933a4a 11780 is_unpredictable = true;
ff4a8d2b
NC		 11781 /* Fall through. */
11782 case 'r':
6576bffe
AB		 11783 func (stream, dis_style_register, "%s",
11784 arm_regnames[val]);
ff4a8d2b 11785 break;
c19d1205
ZW		 11786
11787 case 'c':
6576bffe 11788 func (stream, base_style, "%s", arm_conditional[val]);
c19d1205
ZW		 11789 break;
11790
11791 case '\'':
c19d1205 11792 c++;
16980d0b 11793 if (val == ((1ul << width) - 1))
6576bffe 11794 func (stream, base_style, "%c", *c);
c19d1205 11795 break;
43e65147 11796
c19d1205 11797 case '`':
c19d1205 11798 c++;
16980d0b 11799 if (val == 0)
6576bffe 11800 func (stream, dis_style_immediate, "%c", *c);
c19d1205
ZW		 11801 break;
11802
11803 case '?':
6576bffe
AB		 11804 func (stream, dis_style_mnemonic, "%c",
11805 c[(1 << width) - (int) val]);
16980d0b 11806 c += 1 << width;
c19d1205 11807 break;
43e65147 11808
0bb027fd 11809 case 'x':
6576bffe
AB		 11810 func (stream, dis_style_immediate, "0x%lx",
11811 val & 0xffffffffUL);
0bb027fd 11812 break;
c19d1205
ZW		 11813
11814 default:
11815 abort ();
11816 }
11817 }
11818 break;
11819
32a94698
NC		 11820 case 'L':
11821 /* PR binutils/12534
11822 If we have a PC relative offset in an LDRD or STRD
11823 instructions then display the decoded address. */
11824 if (((given >> 16) & 0xf) == 0xf)
11825 {
11826 bfd_vma offset = (given & 0xff) * 4;
11827
11828 if ((given & (1 << 23)) == 0)
11829 offset = - offset;
6576bffe 11830 func (stream, dis_style_comment_start, "\t@ ");
32a94698
NC		 11831 info->print_address_func ((pc & ~3) + 4 + offset, info);
11832 }
11833 break;
11834
c19d1205
ZW		 11835 default:
11836 abort ();
11837 }
11838 }
05413229
NC		 11839
11840 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 11841 func (stream, dis_style_comment_start, "\t@ 0x%lx",
11842 value_in_comment);
ff4a8d2b
NC		 11843
11844 if (is_unpredictable)
6576bffe 11845 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 11846
4a5329c6 11847 return;
c19d1205 11848 }
252b5132 11849
58efb6c0 11850 /* No match. */
6576bffe
AB		 11851 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11852 (unsigned) given);
0b347048 11853 return;
252b5132
RH		 11854}
11855
e821645d
DJ		 11856/* Print data bytes on INFO->STREAM. */
11857
11858static void
fe56b6ce
NC		 11859print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11860 struct disassemble_info *info,
e821645d
DJ		 11861 long given)
11862{
6576bffe
AB		 11863 fprintf_styled_ftype func = info->fprintf_styled_func;
11864
e821645d
DJ		 11865 switch (info->bytes_per_chunk)
11866 {
11867 case 1:
6576bffe
AB		 11868 func (info->stream, dis_style_assembler_directive, ".byte");
11869 func (info->stream, dis_style_text, "\t");
11870 func (info->stream, dis_style_immediate, "0x%02lx", given);
e821645d
DJ		 11871 break;
11872 case 2:
6576bffe
AB		 11873 func (info->stream, dis_style_assembler_directive, ".short");
11874 func (info->stream, dis_style_text, "\t");
11875 func (info->stream, dis_style_immediate, "0x%04lx", given);
e821645d
DJ		 11876 break;
11877 case 4:
6576bffe
AB		 11878 func (info->stream, dis_style_assembler_directive, ".word");
11879 func (info->stream, dis_style_text, "\t");
11880 func (info->stream, dis_style_immediate, "0x%08lx", given);
e821645d
DJ		 11881 break;
11882 default:
11883 abort ();
11884 }
11885}
11886
22a398e1 11887/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11888 being displayed in symbol relative addresses.
11889
11890 Also disallow private symbol, with __tagsym$$ prefix,
11891 from ARM RVCT toolchain being displayed. */
22a398e1 11892
78933a4a 11893bool
22a398e1
NC		 11894arm_symbol_is_valid (asymbol * sym,
11895 struct disassemble_info * info ATTRIBUTE_UNUSED)
11896{
11897 const char * name;
43e65147 11898
22a398e1 11899 if (sym == NULL)
78933a4a 11900 return false;
22a398e1
NC		 11901
11902 name = bfd_asymbol_name (sym);
11903
d8282f0e 11904 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11905}
11906
65b48a81 11907/* Parse the string of disassembler options. */
baf0cc5e 11908
65b48a81 11909static void
f995bbe8 11910parse_arm_disassembler_options (const char *options)
dd92f639 11911{
f995bbe8 11912 const char *opt;
b34976b6 11913
cad152f2 11914 force_thumb = false;
65b48a81 11915 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11916 {
08dedd66 11917 if (startswith (opt, "reg-names-"))
65b48a81
PB		 11918 {
11919 unsigned int i;
11920 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11921 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11922 {
11923 regname_selected = i;
11924 break;
11925 }
b34976b6 11926
65b48a81 11927 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11928 /* xgettext: c-format */
11929 opcodes_error_handler (_("unrecognised register name set: %s"),
11930 opt);
65b48a81 11931 }
08dedd66 11932 else if (startswith (opt, "force-thumb"))
65b48a81 11933 force_thumb = 1;
08dedd66 11934 else if (startswith (opt, "no-force-thumb"))
65b48a81 11935 force_thumb = 0;
08dedd66 11936 else if (startswith (opt, "coproc"))
4934a27c
MM		 11937 {
11938 const char *procptr = opt + sizeof ("coproc") - 1;
11939 char *endptr;
11940 uint8_t coproc_number = strtol (procptr, &endptr, 10);
11941 if (endptr != procptr + 1 || coproc_number > 7)
11942 {
11943 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11944 opt);
11945 continue;
11946 }
11947 if (*endptr != '=')
11948 {
11949 opcodes_error_handler (_("coproc must have an argument: %s"),
11950 opt);
11951 continue;
11952 }
11953 endptr += 1;
08dedd66 11954 if (startswith (endptr, "generic"))
4934a27c 11955 cde_coprocs &= ~(1 << coproc_number);
08dedd66
ML		 11956 else if (startswith (endptr, "cde")
11957 || startswith (endptr, "CDE"))
4934a27c
MM		 11958 cde_coprocs |= (1 << coproc_number);
11959 else
11960 {
11961 opcodes_error_handler (
11962 _("coprocN argument takes options \"generic\","
11963 " \"cde\", or \"CDE\": %s"), opt);
11964 }
11965 }
65b48a81 11966 else
a6743a54
AM		 11967 /* xgettext: c-format */
11968 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11969 }
b34976b6 11970
dd92f639
NC		 11971 return;
11972}
11973
78933a4a 11974static bool
5bc5ae88
RL		 11975mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11976 enum map_type *map_symbol);
11977
c22aaad1
PB		 11978/* Search back through the insn stream to determine if this instruction is
11979 conditionally executed. */
fe56b6ce 11980
c22aaad1 11981static void
fe56b6ce
NC		 11982find_ifthen_state (bfd_vma pc,
11983 struct disassemble_info *info,
78933a4a 11984 bool little)
c22aaad1
PB		 11985{
11986 unsigned char b[2];
11987 unsigned int insn;
11988 int status;
11989 /* COUNT is twice the number of instructions seen. It will be odd if we
11990 just crossed an instruction boundary. */
11991 int count;
11992 int it_count;
11993 unsigned int seen_it;
11994 bfd_vma addr;
11995
11996 ifthen_address = pc;
11997 ifthen_state = 0;
11998
11999 addr = pc;
12000 count = 1;
12001 it_count = 0;
12002 seen_it = 0;
12003 /* Scan backwards looking for IT instructions, keeping track of where
12004 instruction boundaries are. We don't know if something is actually an
12005 IT instruction until we find a definite instruction boundary. */
12006 for (;;)
12007 {
fe56b6ce 12008 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 12009 {
12010 /* A symbol must be on an instruction boundary, and will not
12011 be within an IT block. */
12012 if (seen_it && (count & 1))
12013 break;
12014
12015 return;
12016 }
12017 addr -= 2;
fe56b6ce 12018 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 12019 if (status)
12020 return;
12021
12022 if (little)
12023 insn = (b[0]) | (b[1] << 8);
12024 else
12025 insn = (b[1]) | (b[0] << 8);
12026 if (seen_it)
12027 {
12028 if ((insn & 0xf800) < 0xe800)
12029 {
12030 /* Addr + 2 is an instruction boundary. See if this matches
12031 the expected boundary based on the position of the last
12032 IT candidate. */
12033 if (count & 1)
12034 break;
12035 seen_it = 0;
12036 }
12037 }
12038 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12039 {
5bc5ae88 12040 enum map_type type = MAP_ARM;
78933a4a 12041 bool found = mapping_symbol_for_insn (addr, info, &type);
5bc5ae88
RL		 12042
12043 if (!found || (found && type == MAP_THUMB))
12044 {
12045 /* This could be an IT instruction. */
12046 seen_it = insn;
12047 it_count = count >> 1;
12048 }
c22aaad1
PB		 12049 }
12050 if ((insn & 0xf800) >= 0xe800)
12051 count++;
12052 else
12053 count = (count + 2) | 1;
12054 /* IT blocks contain at most 4 instructions. */
12055 if (count >= 8 && !seen_it)
12056 return;
12057 }
12058 /* We found an IT instruction. */
12059 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12060 if ((ifthen_state & 0xf) == 0)
12061 ifthen_state = 0;
12062}
12063
b0e28b39
DJ		 12064/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12065 mapping symbol. */
12066
12067static int
77186045
NC		 12068is_mapping_symbol (struct disassemble_info *info,
12069 int n,
b0e28b39
DJ		 12070 enum map_type *map_type)
12071{
77186045 12072 const char *name = bfd_asymbol_name (info->symtab[n]);
b0e28b39 12073
77186045
NC		 12074 if (name[0] == '$'
12075 && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
b0e28b39
DJ		 12076 && (name[2] == 0 || name[2] == '.'))
12077 {
12078 *map_type = ((name[1] == 'a') ? MAP_ARM
12079 : (name[1] == 't') ? MAP_THUMB
12080 : MAP_DATA);
78933a4a 12081 return true;
b0e28b39
DJ		 12082 }
12083
78933a4a 12084 return false;
b0e28b39
DJ		 12085}
12086
12087/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12088 Returns nonzero if *MAP_TYPE was set. */
12089
12090static int
12091get_map_sym_type (struct disassemble_info *info,
12092 int n,
12093 enum map_type *map_type)
12094{
12095 /* If the symbol is in a different section, ignore it. */
12096 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12097 return false;
b0e28b39
DJ		 12098
12099 return is_mapping_symbol (info, n, map_type);
12100}
12101
12102/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 12103 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 12104
12105static int
fe56b6ce
NC		 12106get_sym_code_type (struct disassemble_info *info,
12107 int n,
e821645d 12108 enum map_type *map_type)
2087ad84
PB		 12109{
12110 elf_symbol_type *es;
12111 unsigned int type;
77186045 12112 asymbol * sym;
b0e28b39
DJ		 12113
12114 /* If the symbol is in a different section, ignore it. */
12115 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12116 return false;
2087ad84 12117
77186045
NC		 12118 /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */
12119 sym = info->symtab[n];
12120 if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12121 return false;
12122
12123 es = (elf_symbol_type *) sym;
2087ad84
PB		 12124 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12125
12126 /* If the symbol has function type then use that. */
34e77a92 12127 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 12128 {
39d911fc
TP		 12129 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12130 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 12131 *map_type = MAP_THUMB;
12132 else
12133 *map_type = MAP_ARM;
78933a4a 12134 return true;
2087ad84
PB		 12135 }
12136
78933a4a 12137 return false;
2087ad84
PB		 12138}
12139
5bc5ae88
RL		 12140/* Search the mapping symbol state for instruction at pc. This is only
12141 applicable for elf target.
12142
12143 There is an assumption Here, info->private_data contains the correct AND
12144 up-to-date information about current scan process. The information will be
12145 used to speed this search process.
12146
12147 Return TRUE if the mapping state can be determined, and map_symbol
12148 will be updated accordingly. Otherwise, return FALSE. */
12149
78933a4a 12150static bool
5bc5ae88
RL		 12151mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12152 enum map_type *map_symbol)
12153{
796d6298
TC		 12154 bfd_vma addr, section_vma = 0;
12155 int n, last_sym = -1;
78933a4a
AM		 12156 bool found = false;
12157 bool can_use_search_opt_p = false;
796d6298 12158
76a95fac
LM		 12159 /* Sanity check. */
12160 if (info == NULL)
12161 return false;
12162
796d6298
TC		 12163 /* Default to DATA. A text section is required by the ABI to contain an
12164 INSN mapping symbol at the start. A data section has no such
12165 requirement, hence if no mapping symbol is found the section must
12166 contain only data. This however isn't very useful if the user has
12167 fully stripped the binaries. If this is the case use the section
12168 attributes to determine the default. If we have no section default to
12169 INSN as well, as we may be disassembling some raw bytes on a baremetal
12170 HEX file or similar. */
12171 enum map_type type = MAP_DATA;
12172 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12173 type = MAP_ARM;
5bc5ae88
RL		 12174 struct arm_private_data *private_data;
12175
76a95fac 12176 if (info->private_data == NULL || info->symtab == NULL
4eeb0013 12177 || info->symtab_size == 0
5bc5ae88 12178 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
78933a4a 12179 return false;
5bc5ae88
RL		 12180
12181 private_data = info->private_data;
5bc5ae88 12182
796d6298 12183 /* First, look for mapping symbols. */
4eeb0013
AM		 12184 if (pc <= private_data->last_mapping_addr)
12185 private_data->last_mapping_sym = -1;
12186
12187 /* Start scanning at the start of the function, or wherever
12188 we finished last time. */
12189 n = info->symtab_pos + 1;
12190
12191 /* If the last stop offset is different from the current one it means we
12192 are disassembling a different glob of bytes. As such the optimization
12193 would not be safe and we should start over. */
12194 can_use_search_opt_p
12195 = (private_data->last_mapping_sym >= 0
12196 && info->stop_offset == private_data->last_stop_offset);
12197
12198 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12199 n = private_data->last_mapping_sym;
12200
12201 /* Look down while we haven't passed the location being disassembled.
12202 The reason for this is that there's no defined order between a symbol
12203 and an mapping symbol that may be at the same address. We may have to
12204 look at least one position ahead. */
12205 for (; n < info->symtab_size; n++)
12206 {
12207 addr = bfd_asymbol_value (info->symtab[n]);
12208 if (addr > pc)
12209 break;
12210 if (get_map_sym_type (info, n, &type))
12211 {
12212 last_sym = n;
12213 found = true;
12214 }
12215 }
5bc5ae88 12216
4eeb0013
AM		 12217 if (!found)
12218 {
12219 n = info->symtab_pos;
12220 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12221 n = private_data->last_mapping_sym;
12222
12223 /* No mapping symbol found at this address. Look backwards
12224 for a preceeding one, but don't go pass the section start
12225 otherwise a data section with no mapping symbol can pick up
12226 a text mapping symbol of a preceeding section. The documentation
12227 says section can be NULL, in which case we will seek up all the
12228 way to the top. */
12229 if (info->section)
12230 section_vma = info->section->vma;
12231
12232 for (; n >= 0; n--)
12233 {
12234 addr = bfd_asymbol_value (info->symtab[n]);
12235 if (addr < section_vma)
12236 break;
796d6298 12237
4eeb0013
AM		 12238 if (get_map_sym_type (info, n, &type))
12239 {
12240 last_sym = n;
12241 found = true;
12242 break;
12243 }
12244 }
12245 }
796d6298
TC		 12246
12247 /* If no mapping symbol was found, try looking up without a mapping
12248 symbol. This is done by walking up from the current PC to the nearest
12249 symbol. We don't actually have to loop here since symtab_pos will
12250 contain the nearest symbol already. */
12251 if (!found)
5bc5ae88 12252 {
796d6298
TC		 12253 n = info->symtab_pos;
12254 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 12255 {
796d6298 12256 last_sym = n;
78933a4a 12257 found = true;
5bc5ae88
RL		 12258 }
12259 }
12260
796d6298
TC		 12261 private_data->last_mapping_sym = last_sym;
12262 private_data->last_type = type;
12263 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 12264
12265 *map_symbol = type;
12266 return found;
12267}
12268
0313a2b8
NC		 12269/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12270 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 12271 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 12272
12273 FIXME: This could more efficiently implemented as a constant array,
12274 although it would also be less robust. */
12275
12276static void
12277select_arm_features (unsigned long mach,
12278 arm_feature_set * features)
12279{
c0c468d5
TP		 12280 arm_feature_set arch_fset;
12281 const arm_feature_set fpu_any = FPU_ANY;
12282
1af1dd51
MW		 12283#undef ARM_SET_FEATURES
12284#define ARM_SET_FEATURES(FSET) \
12285 { \
12286 const arm_feature_set fset = FSET; \
c0c468d5 12287 arch_fset = fset; \
1af1dd51 12288 }
823d2571 12289
c0c468d5
TP		 12290 /* When several architecture versions share the same bfd_mach_arm_XXX value
12291 the most featureful is chosen. */
0313a2b8
NC		 12292 switch (mach)
12293 {
c0c468d5
TP		 12294 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
12295 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12296 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
12297 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12298 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
ad5da6e6 12299 case bfd_mach_arm_ep9312:
c0c468d5
TP		 12300 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12301 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
12302 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12303 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12304 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
c0c468d5
TP		 12305 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12306 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12307 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12308 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
12309 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12310 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12311 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12312 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12313 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12314 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12315 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12316 case bfd_mach_arm_8:
12317 {
aab2c27d
MM		 12318 /* Add bits for extensions that Armv8.6-A recognizes. */
12319 arm_feature_set armv8_6_ext_fset
0632eeea 12320 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 12321 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12322 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 12323 break;
12324 }
2c9d089c 12325 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R_CRC); break;
c0c468d5
TP		 12326 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12327 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12328 case bfd_mach_arm_8_1M_MAIN:
12329 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12330 arm_feature_set mve_all
12331 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12332 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12333 force_thumb = 1;
12334 break;
3197e593 12335 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
c0c468d5 12336 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12337 extensions, with the exception of MVE as that clashes with NEON. */
12338 case bfd_mach_arm_unknown:
3197e593 12339 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
2da2eaf4 12340 break;
0313a2b8
NC		 12341 default:
12342 abort ();
12343 }
1af1dd51 12344#undef ARM_SET_FEATURES
c0c468d5
TP		 12345
12346 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12347 and thus on bfd_mach_arm_XXX value. Therefore for a given
12348 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12349 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12350}
12351
12352
58efb6c0
NC		 12353/* NOTE: There are no checks in these routines that
12354 the relevant number of data bytes exist. */
baf0cc5e 12355
58efb6c0 12356static int
78933a4a 12357print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
252b5132 12358{
c19d1205 12359 unsigned char b[4];
2480b6fa 12360 unsigned long given;
78933a4a
AM		 12361 int status;
12362 int is_thumb = false;
12363 int is_data = false;
12364 int little_code;
e821645d 12365 unsigned int size = 4;
78933a4a
AM		 12366 void (*printer) (bfd_vma, struct disassemble_info *, long);
12367 bool found = false;
b0e28b39 12368 struct arm_private_data *private_data;
58efb6c0 12369
1d67fe3b
TT		 12370 /* Clear instruction information field. */
12371 info->insn_info_valid = 0;
12372 info->branch_delay_insns = 0;
12373 info->data_size = 0;
12374 info->insn_type = dis_noninsn;
12375 info->target = 0;
12376 info->target2 = 0;
12377
dd92f639
NC		 12378 if (info->disassembler_options)
12379 {
65b48a81 12380 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12381
58efb6c0 12382 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12383 info->disassembler_options = NULL;
12384 }
b34976b6 12385
0313a2b8
NC		 12386 /* PR 10288: Control which instructions will be disassembled. */
12387 if (info->private_data == NULL)
12388 {
b0e28b39 12389 static struct arm_private_data private;
0313a2b8 12390
2c9d089c
AV		 12391 if (info->flavour != bfd_target_elf_flavour
12392 && (info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
0313a2b8
NC		 12393 /* If the user did not use the -m command line switch then default to
12394 disassembling all types of ARM instruction.
43e65147 12395
2c9d089c
AV		 12396 If this is an arm elf target, build attributes will be used to
12397 determine info->mach, which enable us to be more accurate when
12398 disassembling since we know what the target architecture version is.
12399 For any other target see the comment below:
12400
0313a2b8
NC		 12401 The info->mach value has to be ignored as this will be based on
12402 the default archictecture for the target and/or hints in the notes
12403 section, but it will never be greater than the current largest arm
12404 machine value (iWMMXt2), which is only equivalent to the V5TE
12405 architecture. ARM architectures have advanced beyond the machine
12406 value encoding, and these newer architectures would be ignored if
12407 the machine value was used.
12408
12409 Ie the -m switch is used to restrict which instructions will be
12410 disassembled. If it is necessary to use the -m switch to tell
12411 objdump that an ARM binary is being disassembled, eg because the
12412 input is a raw binary file, but it is also desired to disassemble
12413 all ARM instructions then use "-marm". This will select the
12414 "unknown" arm architecture which is compatible with any ARM
12415 instruction. */
12416 info->mach = bfd_mach_arm_unknown;
12417
12418 /* Compute the architecture bitmask from the machine number.
12419 Note: This assumes that the machine number will not change
12420 during disassembly.... */
b0e28b39 12421 select_arm_features (info->mach, & private.features);
0313a2b8 12422
1fbaefec
PB		 12423 private.last_mapping_sym = -1;
12424 private.last_mapping_addr = 0;
796d6298 12425 private.last_stop_offset = 0;
b0e28b39
DJ		 12426
12427 info->private_data = & private;
0313a2b8 12428 }
b0e28b39
DJ		 12429
12430 private_data = info->private_data;
12431
bd2e2557
SS		 12432 /* Decide if our code is going to be little-endian, despite what the
12433 function argument might say. */
12434 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12435
b0e28b39
DJ		 12436 /* For ELF, consult the symbol table to determine what kind of code
12437 or data we have. */
8977d4b2 12438 if (info->symtab_size != 0
e821645d
DJ		 12439 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12440 {
12441 bfd_vma addr;
796d6298 12442 int n;
e821645d 12443 int last_sym = -1;
b0e28b39 12444 enum map_type type = MAP_ARM;
e821645d 12445
796d6298
TC		 12446 found = mapping_symbol_for_insn (pc, info, &type);
12447 last_sym = private_data->last_mapping_sym;
e821645d 12448
1fbaefec
PB		 12449 is_thumb = (private_data->last_type == MAP_THUMB);
12450 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12451
e821645d
DJ		 12452 /* Look a little bit ahead to see if we should print out
12453 two or four bytes of data. If there's a symbol,
12454 mapping or otherwise, after two bytes then don't
12455 print more. */
12456 if (is_data)
12457 {
12458 size = 4 - (pc & 3);
12459 for (n = last_sym + 1; n < info->symtab_size; n++)
12460 {
12461 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12462 if (addr > pc
12463 && (info->section == NULL
12464 || info->section == info->symtab[n]->section))
e821645d
DJ		 12465 {
12466 if (addr - pc < size)
12467 size = addr - pc;
12468 break;
12469 }
12470 }
12471 /* If the next symbol is after three bytes, we need to
12472 print only part of the data, so that we can use either
12473 .byte or .short. */
12474 if (size == 3)
12475 size = (pc & 1) ? 1 : 2;
12476 }
12477 }
12478
12479 if (info->symbols != NULL)
252b5132 12480 {
5876e06d
NC		 12481 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12482 {
2f0ca46a 12483 coff_symbol_type * cs;
b34976b6 12484
5876e06d
NC		 12485 cs = coffsymbol (*info->symbols);
12486 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12487 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12488 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12489 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12490 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12491 }
e821645d
DJ		 12492 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12493 && !found)
5876e06d 12494 {
2087ad84
PB		 12495 /* If no mapping symbol has been found then fall back to the type
12496 of the function symbol. */
e821645d
DJ		 12497 elf_symbol_type * es;
12498 unsigned int type;
2087ad84 12499
e821645d
DJ		 12500 es = *(elf_symbol_type **)(info->symbols);
12501 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12502
39d911fc
TP		 12503 is_thumb =
12504 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12505 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12506 }
e49d43ff
TG		 12507 else if (bfd_asymbol_flavour (*info->symbols)
12508 == bfd_target_mach_o_flavour)
12509 {
12510 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12511
12512 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12513 }
5876e06d 12514 }
b34976b6 12515
e821645d 12516 if (force_thumb)
78933a4a 12517 is_thumb = true;
e821645d 12518
b8f9ee44
CL		 12519 if (is_data)
12520 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12521 else
12522 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12523
c19d1205 12524 info->bytes_per_line = 4;
252b5132 12525
1316c8b3
NC		 12526 /* PR 10263: Disassemble data if requested to do so by the user. */
12527 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12528 {
12529 int i;
12530
1316c8b3 12531 /* Size was already set above. */
e821645d
DJ		 12532 info->bytes_per_chunk = size;
12533 printer = print_insn_data;
12534
fe56b6ce 12535 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12536 given = 0;
12537 if (little)
12538 for (i = size - 1; i >= 0; i--)
12539 given = b[i] | (given << 8);
12540 else
12541 for (i = 0; i < (int) size; i++)
12542 given = b[i] | (given << 8);
12543 }
12544 else if (!is_thumb)
252b5132 12545 {
c19d1205
ZW		 12546 /* In ARM mode endianness is a straightforward issue: the instruction
12547 is four bytes long and is either ordered 0123 or 3210. */
12548 printer = print_insn_arm;
12549 info->bytes_per_chunk = 4;
4a5329c6 12550 size = 4;
c19d1205 12551
0313a2b8 12552 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12553 if (little_code)
2480b6fa 12554 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12555 else
2480b6fa 12556 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12557 }
58efb6c0 12558 else
252b5132 12559 {
c19d1205
ZW		 12560 /* In Thumb mode we have the additional wrinkle of two
12561 instruction lengths. Fortunately, the bits that determine
12562 the length of the current instruction are always to be found
12563 in the first two bytes. */
4a5329c6 12564 printer = print_insn_thumb16;
c19d1205 12565 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12566 size = 2;
12567
fe56b6ce 12568 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12569 if (little_code)
9a2ff3f5
AM		 12570 given = (b[0]) | (b[1] << 8);
12571 else
12572 given = (b[1]) | (b[0] << 8);
12573
c19d1205 12574 if (!status)
252b5132 12575 {
c19d1205
ZW		 12576 /* These bit patterns signal a four-byte Thumb
12577 instruction. */
12578 if ((given & 0xF800) == 0xF800
12579 || (given & 0xF800) == 0xF000
12580 || (given & 0xF800) == 0xE800)
252b5132 12581 {
0313a2b8 12582 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12583 if (little_code)
c19d1205 12584 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12585 else
c19d1205
ZW		 12586 given = (b[1]) | (b[0] << 8) | (given << 16);
12587
12588 printer = print_insn_thumb32;
4a5329c6 12589 size = 4;
252b5132 12590 }
252b5132 12591 }
c22aaad1
PB		 12592
12593 if (ifthen_address != pc)
0313a2b8 12594 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12595
12596 if (ifthen_state)
12597 {
12598 if ((ifthen_state & 0xf) == 0x8)
12599 ifthen_next_state = 0;
12600 else
12601 ifthen_next_state = (ifthen_state & 0xe0)
12602 | ((ifthen_state & 0xf) << 1);
12603 }
252b5132 12604 }
b34976b6 12605
c19d1205
ZW		 12606 if (status)
12607 {
12608 info->memory_error_func (status, pc, info);
12609 return -1;
12610 }
6a56ec7e
NC		 12611 if (info->flags & INSN_HAS_RELOC)
12612 /* If the instruction has a reloc associated with it, then
12613 the offset field in the instruction will actually be the
12614 addend for the reloc. (We are using REL type relocs).
12615 In such cases, we can ignore the pc when computing
12616 addresses, since the addend is not currently pc-relative. */
12617 pc = 0;
b34976b6 12618
4a5329c6 12619 printer (pc, info, given);
c22aaad1
PB		 12620
12621 if (is_thumb)
12622 {
12623 ifthen_state = ifthen_next_state;
12624 ifthen_address += size;
12625 }
4a5329c6 12626 return size;
252b5132
RH		 12627}
12628
12629int
4a5329c6 12630print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12631{
bd2e2557
SS		 12632 /* Detect BE8-ness and record it in the disassembler info. */
12633 if (info->flavour == bfd_target_elf_flavour
12634 && info->section != NULL
12635 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12636 info->endian_code = BFD_ENDIAN_LITTLE;
12637
78933a4a 12638 return print_insn (pc, info, false);
58efb6c0 12639}
01c7f630 12640
58efb6c0 12641int
4a5329c6 12642print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12643{
78933a4a 12644 return print_insn (pc, info, true);
58efb6c0 12645}
252b5132 12646
471b9d15 12647const disasm_options_and_args_t *
65b48a81
PB		 12648disassembler_options_arm (void)
12649{
471b9d15 12650 static disasm_options_and_args_t *opts_and_args;
65b48a81 12651
471b9d15 12652 if (opts_and_args == NULL)
65b48a81 12653 {
471b9d15 12654 disasm_options_t *opts;
65b48a81 12655 unsigned int i;
471b9d15
MR		 12656
12657 opts_and_args = XNEW (disasm_options_and_args_t);
12658 opts_and_args->args = NULL;
12659
12660 opts = &opts_and_args->options;
65b48a81
PB		 12661 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12662 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12663 opts->arg = NULL;
65b48a81
PB		 12664 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12665 {
12666 opts->name[i] = regnames[i].name;
12667 if (regnames[i].description != NULL)
12668 opts->description[i] = _(regnames[i].description);
12669 else
12670 opts->description[i] = NULL;
12671 }
12672 /* The array we return must be NULL terminated. */
12673 opts->name[i] = NULL;
12674 opts->description[i] = NULL;
12675 }
12676
471b9d15 12677 return opts_and_args;
65b48a81
PB		 12678}
12679
58efb6c0 12680void
4a5329c6 12681print_arm_disassembler_options (FILE *stream)
58efb6c0 12682{
65b48a81 12683 unsigned int i, max_len = 0;
58efb6c0
NC		 12684 fprintf (stream, _("\n\
12685The following ARM specific disassembler options are supported for use with\n\
12686the -M switch:\n"));
b34976b6 12687
65b48a81
PB		 12688 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12689 {
12690 unsigned int len = strlen (regnames[i].name);
12691 if (max_len < len)
12692 max_len = len;
12693 }
58efb6c0 12694
65b48a81
PB		 12695 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12696 fprintf (stream, " %s%*c %s\n",
12697 regnames[i].name,
12698 (int)(max_len - strlen (regnames[i].name)), ' ',
12699 _(regnames[i].description));
252b5132 12700}
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