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40b8e679 | 1 | // i386 opcode table. |
fd67aa11 | 2 | // Copyright (C) 2007-2024 Free Software Foundation, Inc. |
9b201bb5 NC |
3 | // |
4 | // This file is part of the GNU opcodes library. | |
5 | // | |
6 | // This library is free software; you can redistribute it and/or modify | |
7 | // it under the terms of the GNU General Public License as published by | |
8 | // the Free Software Foundation; either version 3, or (at your option) | |
9 | // any later version. | |
10 | // | |
11 | // It is distributed in the hope that it will be useful, but WITHOUT | |
12 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | // License for more details. | |
15 | // | |
16 | // You should have received a copy of the GNU General Public License | |
17 | // along with GAS; see the file COPYING. If not, write to the Free | |
18 | // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | // 02110-1301, USA. | |
40b8e679 | 20 | |
c30be56e JB |
21 | #define OPCODE_I386_H |
22 | #include "i386-opc.h" | |
c30be56e | 23 | |
33b6a20a JB |
24 | // When necessary lines can be split in a non-standard way, by placing a |
25 | // trailing + on a to-be-continued line. This is intended mainly for non-insn | |
26 | // templates. Insn templates are better kept all on one line to make grep and | |
27 | // alike produce useful results. | |
28 | ||
4b5aaf5f L |
29 | #define Amd64 ISA64=AMD64 |
30 | #define Intel64 ISA64=INTEL64 | |
31 | #define Intel64Only ISA64=INTEL64ONLY | |
32 | ||
bab6aec1 JB |
33 | #define Reg8 Class=Reg|Byte |
34 | #define Reg16 Class=Reg|Word | |
35 | #define Reg32 Class=Reg|Dword | |
36 | #define Reg64 Class=Reg|Qword | |
3cc17af5 | 37 | |
474da251 JB |
38 | #define Acc Instance=Accum |
39 | #define RegC Instance=RegC | |
40 | #define RegD Instance=RegD | |
41 | #define RegB Instance=RegB | |
42 | ||
43 | #define ShiftCount RegC|Byte | |
44 | #define InOutPortReg RegD|Word | |
75e5731b | 45 | |
3cc17af5 | 46 | #define FloatAcc Acc|Tbyte |
bab6aec1 | 47 | #define FloatReg Class=Reg|Tbyte |
3cc17af5 | 48 | |
00cee14f JB |
49 | #define SReg Class=SReg |
50 | ||
4a5c67ed JB |
51 | #define Control Class=RegCR |
52 | #define Debug Class=RegDR | |
53 | #define Test Class=RegTR | |
54 | ||
3528c362 JB |
55 | #define RegMMX Class=RegMMX |
56 | #define RegXMM Class=RegSIMD|Xmmword | |
57 | #define RegYMM Class=RegSIMD|Ymmword | |
58 | #define RegZMM Class=RegSIMD|Zmmword | |
260cd341 | 59 | #define RegTMM Class=RegSIMD|Tmmword |
3cc17af5 | 60 | |
f74a6307 JB |
61 | #define RegMask Class=RegMask |
62 | ||
63 | #define RegBND Class=RegBND | |
64 | ||
b818b220 JB |
65 | #define Mmword Qword |
66 | #define Oword Xmmword | |
67 | ||
0cfa3eb3 JB |
68 | #define JumpByte Jump=JUMP_BYTE |
69 | #define JumpDword Jump=JUMP_DWORD | |
70 | #define JumpAbsolute Jump=JUMP_ABSOLUTE | |
71 | #define JumpInterSegment Jump=JUMP_INTERSEGMENT | |
72 | ||
673fe0f0 JB |
73 | #define Size16 Size=SIZE16 |
74 | #define Size32 Size=SIZE32 | |
75 | #define Size64 Size=SIZE64 | |
76 | ||
f207f1c1 | 77 | #define NoSuf No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf |
2368c6bf L |
78 | |
79 | #define AddrPrefixOpReg OperandConstraint=ADDR_PREFIX_OP_REG | |
255571cd JB |
80 | #define Anysize OperandConstraint=ANY_SIZE |
81 | #define DistinctDest OperandConstraint=DISTINCT_DEST | |
82 | #define Implicit1stXmm0 OperandConstraint=IMPLICIT_1ST_XMM0 | |
83 | #define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP | |
84 | #define NoDefMask OperandConstraint=NO_DEFAULT_MASK | |
85 | #define RegKludge OperandConstraint=REG_KLUDGE | |
255571cd | 86 | #define Ugh OperandConstraint=UGH |
448cf9e6 | 87 | #define ImplicitStackOp OperandConstraint=IMPLICIT_STACK_OP |
255571cd | 88 | |
35266cb1 JB |
89 | #define ATTSyntax Dialect=ATT_SYNTAX |
90 | #define ATTMnemonic Dialect=ATT_MNEMONIC | |
91 | #define IntelSyntax Dialect=INTEL_SYNTAX | |
92 | ||
3cd7f3e3 L |
93 | #define IgnoreSize MnemonicSize=IGNORESIZE |
94 | #define DefaultSize MnemonicSize=DEFAULTSIZE | |
95 | ||
dfd69174 JB |
96 | // RegMem implies a ModR/M byte |
97 | #define RegMem Modrm|RegMem | |
98 | ||
51c8edf6 JB |
99 | #define IsStringEsOp0 IsString=IS_STRING_ES_OP0 |
100 | #define IsStringEsOp1 IsString=IS_STRING_ES_OP1 | |
101 | ||
742732c7 JB |
102 | #define RepPrefixOk PrefixOk=PrefixRep |
103 | #define LockPrefixOk PrefixOk=PrefixLock | |
104 | #define HLEPrefixAny PrefixOk=PrefixHLEAny | |
105 | #define HLEPrefixLock PrefixOk=PrefixHLELock | |
106 | #define HLEPrefixRelease PrefixOk=PrefixHLERelease | |
107 | #define NoTrackPrefixOk PrefixOk=PrefixNoTrack | |
108 | ||
441f6aca JB |
109 | #define Space0F OpcodeSpace=SPACE_0F |
110 | #define Space0F38 OpcodeSpace=SPACE_0F38 | |
111 | #define Space0F3A OpcodeSpace=SPACE_0F3A | |
112 | #define SpaceXOP08 OpcodeSpace=SPACE_XOP08 | |
113 | #define SpaceXOP09 OpcodeSpace=SPACE_XOP09 | |
114 | #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A | |
115 | ||
6177c84d | 116 | #define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4|EVex128 |
0cc78721 CL |
117 | #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 |
118 | #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 | |
119 | ||
8170af78 HL |
120 | #define VexMap7 OpcodeSpace=SPACE_VEXMAP7 |
121 | ||
bbae6b11 JB |
122 | #define VexW0 VexW=VEXW0 |
123 | #define VexW1 VexW=VEXW1 | |
6fa52824 L |
124 | #define VexWIG VexW=VEXWIG |
125 | ||
fd71a375 JB |
126 | #define Vex128 Vex=VEX128 |
127 | #define Vex256 Vex=VEX256 | |
128 | #define VexLIG Vex=VEXScalar | |
e978ad62 | 129 | |
79b32e73 | 130 | #define VecSIB128 SIB=VECSIB128 |
63112cd6 L |
131 | #define VecSIB256 SIB=VECSIB256 |
132 | #define VecSIB512 SIB=VECSIB512 | |
260cd341 | 133 | #define Sibmem SIB=SIBMEM|Modrm |
fd71a375 JB |
134 | |
135 | #define EVex128 EVex=EVEX128 | |
136 | #define EVex256 EVex=EVEX256 | |
137 | #define EVex512 EVex=EVEX512 | |
138 | #define EVexLIG EVex=EVEXLIG | |
139 | #define EVexDYN EVex=EVEXDYN | |
140 | ||
a6f3add0 JB |
141 | #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL |
142 | ||
f2a3a881 | 143 | #define Src1VVVV VexVVVV=VexVVVV_SRC1 |
0820c9f5 | 144 | #define Src2VVVV VexVVVV=VexVVVV_SRC2 |
f2a3a881 | 145 | #define DstVVVV VexVVVV=VexVVVV_DST |
3083f376 | 146 | |
7c3df3c6 JB |
147 | // The template supports VEX format for cpuid and EVEX format for cpuid & APX_F. |
148 | // While therefore we really mean cpuid|(cpuid&APX_F) here, this can't be | |
149 | // expressed in the generated templates. It's equivalent to just cpuid|APX_F | |
150 | // anyway, but that is not what we want (as APX_F alone isn't a sufficient | |
151 | // prereq for such insns). Instead the assembler will massage the CPU specifier | |
152 | // to the equivalent of either cpuid&(cpuid) or cpuid&(APX_F) (or something | |
153 | // substantially similar), depending on what encoding was requested. | |
6177c84d CL |
154 | #define APX_F(cpuid) cpuid&(cpuid|APX_F) |
155 | ||
79dec6b7 JB |
156 | // The EVEX purpose of StaticRounding appears only together with SAE. Re-use |
157 | // the bit to mark commutative VEX encodings where swapping the source | |
158 | // operands may allow to switch from 3-byte to 2-byte VEX encoding. | |
3083f376 | 159 | // And re-use the bit to mark some NDD insns that swapping the source operands |
160 | // may allow to switch from EVEX encoding to REX2 encoding. | |
79dec6b7 JB |
161 | #define C StaticRounding |
162 | ||
4fdeb2a3 JB |
163 | #define FP 387|287|8087 |
164 | ||
165 | // To avoid CPU specifiers to look like plain number tokens in the table, | |
166 | // introduce some aliases. | |
167 | #define i186 186 | |
168 | #define i286 286 | |
169 | #undef i386 | |
170 | #define i386 386 | |
171 | #define i486 486 | |
172 | #define i586 586 | |
173 | #define i686 686 | |
174 | #define i8087 8087 | |
175 | #define i287 287 | |
176 | #define i387 387 | |
177 | #define i687 687 | |
3e624fa4 JB |
178 | // Note: Don't add this one to any templates already specifying a 64-bit-mode- |
179 | // only ISA extension: i386-gen takes care of adding such dependencies. | |
4fdeb2a3 | 180 | #define x64 64 |
b818b220 | 181 | |
bbae6b11 JB |
182 | ### MARKER ### |
183 | ||
40b8e679 | 184 | // Move instructions. |
9c19e9ec JB |
185 | mov, 0xa0, No64, D|W|CheckOperandSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } |
186 | mov, 0xa0, x64, D|W|CheckOperandSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } | |
187 | movabs, 0xa0, x64, D|W|CheckOperandSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } | |
e20298da | 188 | mov, 0x88, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
40b8e679 L |
189 | // In the 64bit mode the short form mov immediate is redefined to have |
190 | // 64bit value. | |
68993386 | 191 | mov, 0xb0, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } |
e20298da | 192 | mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
4fdeb2a3 JB |
193 | mov, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 } |
194 | movabs, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 } | |
40b8e679 L |
195 | // The segment register moves accept WordReg so that a segment register |
196 | // can be copied to a 32 bit register, and vice versa, without using a | |
197 | // size prefix. When moving to a 32 bit register, the upper 16 bits | |
198 | // are set to an implementation defined value (on the Pentium Pro, the | |
199 | // implementation defined value is zero). | |
68993386 JB |
200 | mov, 0x8c, 0, RegMem|No_bSuf|No_sSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 } |
201 | mov, 0x8c, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|Unspecified|BaseIndex } | |
202 | mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } | |
40b8e679 L |
203 | // Move to/from control debug registers. In the 16 or 32bit modes |
204 | // they are 32bit. In the 64bit mode they are 64bit. | |
a5e91879 | 205 | mov, 0xf20, i386&No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } |
4fdeb2a3 | 206 | mov, 0xf20, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 } |
a5e91879 | 207 | mov, 0xf21, i386&No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } |
4fdeb2a3 | 208 | mov, 0xf21, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 } |
a5e91879 | 209 | mov, 0xf24, i386&No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } |
40b8e679 | 210 | |
f1f8f695 | 211 | // Move after swapping the bytes |
9c19e9ec | 212 | movbe, 0x0f38f0, Movbe, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
6177c84d | 213 | movbe, 0x60, Movbe&APX_F, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
0ebcbb1b JB |
214 | // This needs to live here for easy EVEX -> REX2 conversion, which wants to |
215 | // restart with the next sequential template. | |
216 | bswap, 0xfc8, i486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } | |
f1f8f695 | 217 | |
40b8e679 | 218 | // Move with sign extend. |
4fdeb2a3 JB |
219 | movsb, 0xfbe, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
220 | movsw, 0xfbf, i386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } | |
221 | movsl, 0x63, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 } | |
222 | movsx, 0xfbe, i386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
223 | movsx, 0x63, x64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } | |
224 | movsxd, 0x63, x64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } | |
225 | movsxd, 0x63, x64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } | |
226 | movsxd, 0x63, x64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } | |
40b8e679 | 227 | |
c07315e0 | 228 | // Move with zero extend. |
e20298da CL |
229 | movzb, 0xfb6, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
230 | movzw, 0xfb7, i386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } | |
6867aac0 L |
231 | // The 64-bit variant is not particularly useful since the zero extend |
232 | // 32->64 is implicit, but we can encode them. | |
4fdeb2a3 | 233 | movzx, 0xfb6, i386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 L |
234 | |
235 | // Push instructions. | |
448cf9e6 IB |
236 | push, 0x50, No64, ImplicitStackOp|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } |
237 | push, 0xff/6, No64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unspecified|BaseIndex } | |
238 | push, 0x6a, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } | |
239 | push, 0x68, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } | |
240 | push, 0x6, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } | |
40b8e679 | 241 | // In 64bit mode, the operand size is implicitly 64bit. |
448cf9e6 IB |
242 | push, 0x50, x64, ImplicitStackOp|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } |
243 | pushp, 0x50, APX_F, ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 } | |
244 | push, 0xff/6, x64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex } | |
245 | push, 0x6a, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } | |
246 | push, 0x68, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } | |
247 | push, 0xfa0, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } | |
40b8e679 | 248 | |
448cf9e6 | 249 | pusha, 0x60, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} |
40b8e679 L |
250 | |
251 | // Pop instructions. | |
448cf9e6 IB |
252 | pop, 0x58, No64, ImplicitStackOp|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } |
253 | pop, 0x8f/0, No64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unspecified|BaseIndex } | |
254 | pop, 0x7, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } | |
40b8e679 | 255 | // In 64bit mode, the operand size is implicitly 64bit. |
448cf9e6 IB |
256 | pop, 0x58, x64, ImplicitStackOp|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } |
257 | popp, 0x58, APX_F, ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 } | |
258 | pop, 0x8f/0, x64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex } | |
259 | pop, 0xfa1, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } | |
40b8e679 | 260 | |
448cf9e6 | 261 | popa, 0x61, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} |
40b8e679 L |
262 | |
263 | // Exchange instructions. | |
264 | // xchg commutes: we allow both operand orders. | |
265 | ||
266 | // In the 64bit code, xchg rax, rax is reused for new nop instruction. | |
9c19e9ec JB |
267 | xchg, 0x90, 0, D|C|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } |
268 | xchg, 0x86, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
40b8e679 L |
269 | |
270 | // In/out from ports. | |
68993386 JB |
271 | in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword } |
272 | in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword } | |
273 | in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8 } | |
274 | in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg } | |
275 | out, 0xe6, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 } | |
276 | out, 0xee, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg } | |
277 | out, 0xe6, 0, W|No_sSuf|No_qSuf, { Imm8 } | |
278 | out, 0xee, 0, W|No_sSuf|No_qSuf, { InOutPortReg } | |
40b8e679 L |
279 | |
280 | // Load effective address. | |
68993386 | 281 | lea, 0x8d, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 L |
282 | |
283 | // Load segment registers from memory. | |
4fdeb2a3 JB |
284 | lds, 0xc5, No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } |
285 | les, 0xc4, No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
286 | lfs, 0xfb4, i386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
287 | lfs, 0xfb4, x64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
288 | lgs, 0xfb5, i386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
289 | lgs, 0xfb5, x64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
290 | lss, 0xfb2, i386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
291 | lss, 0xfb2, x64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
40b8e679 L |
292 | |
293 | // Flags register instructions. | |
68993386 JB |
294 | clc, 0xf8, 0, NoSuf, {} |
295 | cld, 0xfc, 0, NoSuf, {} | |
296 | cli, 0xfa, 0, NoSuf, {} | |
4fdeb2a3 | 297 | clts, 0xf06, i286, NoSuf, {} |
68993386 | 298 | cmc, 0xf5, 0, NoSuf, {} |
c3bb24f5 JB |
299 | lahf, 0x9f, No64, NoSuf, {} |
300 | lahf, 0x9f, LAHF_SAHF, NoSuf, {} | |
301 | sahf, 0x9e, No64, NoSuf, {} | |
302 | sahf, 0x9e, LAHF_SAHF, NoSuf, {} | |
448cf9e6 IB |
303 | pushf, 0x9c, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} |
304 | pushf, 0x9c, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} | |
305 | popf, 0x9d, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} | |
306 | popf, 0x9d, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} | |
68993386 JB |
307 | stc, 0xf9, 0, NoSuf, {} |
308 | std, 0xfd, 0, NoSuf, {} | |
309 | sti, 0xfb, 0, NoSuf, {} | |
40b8e679 L |
310 | |
311 | // Arithmetic. | |
42eb20eb JB |
312 | |
313 | <alu2:opc:c:optz:optt:opti:nf, + | |
314 | add:0:C::::NF, + | |
315 | or:1:C::Optimize::NF, + | |
316 | adc:2:C::::, + | |
317 | sbb:3:::::, + | |
318 | and:4:C::Optimize:Optimize:NF, + | |
319 | sub:5::Optimize:::NF, + | |
320 | xor:6:C:Optimize:::NF> | |
321 | ||
322 | <alu2>, <alu2:opc> << 3, APX_F, D|<alu2:c>|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>|<alu2:optz>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } | |
323 | <alu2>, <alu2:opc> << 3, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|<alu2:optz>|<alu2:optt>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 324 | <alu2>, <alu2:opc> << 3, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|<alu2:nf>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
42eb20eb JB |
325 | <alu2>, 0x83/<alu2:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
326 | <alu2>, 0x83/<alu2:opc>, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|<alu2:opti>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 327 | <alu2>, 0x83/<alu2:opc>, 0, Modrm|No_bSuf|No_sSuf|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
42eb20eb JB |
328 | <alu2>, 0x04 | (<alu2:opc> << 3), 0, W|No_sSuf|<alu2:opti>, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } |
329 | <alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } | |
330 | <alu2>, 0x80/<alu2:opc>, 0, W|Modrm|No_sSuf|HLEPrefixLock|<alu2:opti>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 331 | <alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|EVexMap4|No_sSuf|<alu2:nf>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
42eb20eb JB |
332 | |
333 | <alu2> | |
334 | ||
335 | // clr with 1 operand is really xor with 2 operands. | |
336 | clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } | |
dd74a603 | 337 | clr, 0x30, APX_F, W|Modrm|No_sSuf|RegKludge|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64 } |
68993386 | 338 | |
e20298da CL |
339 | cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
340 | cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
68993386 | 341 | cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } |
e20298da | 342 | cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
68993386 | 343 | |
9c19e9ec | 344 | test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
68993386 | 345 | test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } |
e20298da | 346 | test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
68993386 | 347 | |
cd9ca24d JB |
348 | <incdec:opc, inc:0, dec:1> |
349 | ||
350 | <incdec>, 0x40 | (<incdec:opc> << 3), No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } | |
351 | <incdec>, 0xfe/<incdec:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} | |
352 | <incdec>, 0xfe/<incdec:opc>, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 353 | <incdec>, 0xfe/<incdec:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
cd9ca24d JB |
354 | |
355 | <incdec> | |
356 | ||
568473a4 | 357 | <alu1:opc:nf, not:2:, neg:3:NF> |
3083f376 | 358 | |
568473a4 JB |
359 | <alu1>, 0xf6/<alu1:opc>, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|<alu1:nf>, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } |
360 | <alu1>, 0xf6/<alu1:opc>, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 361 | <alu1>, 0xf6/<alu1:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<alu1:nf>, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
568473a4 JB |
362 | |
363 | <alu1> | |
40b8e679 | 364 | |
4fdeb2a3 JB |
365 | aaa, 0x37, No64, NoSuf, {} |
366 | aas, 0x3f, No64, NoSuf, {} | |
367 | daa, 0x27, No64, NoSuf, {} | |
368 | das, 0x2f, No64, NoSuf, {} | |
369 | aad, 0xd50a, No64, NoSuf, {} | |
370 | aad, 0xd5, No64, NoSuf, { Imm8 } | |
371 | aam, 0xd40a, No64, NoSuf, {} | |
372 | aam, 0xd4, No64, NoSuf, { Imm8 } | |
40b8e679 L |
373 | |
374 | // Conversion insns. | |
375 | // Intel naming | |
68993386 | 376 | cbw, 0x98, 0, Size16|NoSuf, {} |
4fdeb2a3 JB |
377 | cwde, 0x98, i386, Size32|NoSuf, {} |
378 | cdqe, 0x98, x64, Size64|NoSuf, {} | |
68993386 | 379 | cwd, 0x99, 0, Size16|NoSuf, {} |
4fdeb2a3 JB |
380 | cdq, 0x99, i386, Size32|NoSuf, {} |
381 | cqo, 0x99, x64, Size64|NoSuf, {} | |
40b8e679 | 382 | // AT&T naming |
68993386 | 383 | cbtw, 0x98, 0, Size16|NoSuf, {} |
4fdeb2a3 JB |
384 | cwtl, 0x98, i386, Size32|NoSuf, {} |
385 | cltq, 0x98, x64, Size64|NoSuf, {} | |
68993386 | 386 | cwtd, 0x99, 0, Size16|NoSuf, {} |
4fdeb2a3 JB |
387 | cltd, 0x99, i386, Size32|NoSuf, {} |
388 | cqto, 0x99, x64, Size64|NoSuf, {} | |
40b8e679 L |
389 | |
390 | // Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are | |
391 | // expanding 64-bit multiplies, and *cannot* be selected to accomplish | |
392 | // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) | |
393 | // These multiplies can only be selected with single operand forms. | |
568473a4 JB |
394 | <mul:opc, mul:4, imul:5> |
395 | ||
396 | <mul>, 0xf6/<mul:opc>, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 397 | <mul>, 0xf6/<mul:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
3083f376 | 398 | imul, 0xaf, APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } |
e20298da | 399 | imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
dd74a603 | 400 | imul, 0xaf, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
e20298da | 401 | imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
dd74a603 | 402 | imul, 0x6b, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
e20298da | 403 | imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
dd74a603 | 404 | imul, 0x69, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 L |
405 | // imul with 2 operands mimics imul with 3 by putting the register in |
406 | // both i.rm.reg & i.rm.regmem fields. RegKludge enables this | |
407 | // transformation. | |
4fdeb2a3 | 408 | imul, 0x6b, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } |
dd74a603 | 409 | imul, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64 } |
4fdeb2a3 | 410 | imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } |
dd74a603 | 411 | imul, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } |
68993386 | 412 | |
568473a4 JB |
413 | <mul> |
414 | ||
415 | <div:opc, div:6, idiv:7> | |
416 | ||
417 | <div>, 0xf6/<div:opc>, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 418 | <div>, 0xf6/<div:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
568473a4 | 419 | <div>, 0xf6/<div:opc>, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } |
dd74a603 | 420 | <div>, 0xf6/<div:opc>, APX_F, W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } |
568473a4 JB |
421 | |
422 | <div> | |
e20298da | 423 | |
fe17c026 JB |
424 | <sr:opc:imm8:nf, + |
425 | rol:0:Imm8|Imm8S:NF, + | |
426 | ror:1:Imm8|Imm8S:NF, + | |
427 | rcl:2:Imm8:, + | |
428 | rcr:3:Imm8:, + | |
429 | sal:4:Imm8:NF, + | |
430 | shl:4:Imm8:NF, + | |
431 | shr:5:Imm8:NF, + | |
432 | sar:7:Imm8:NF> | |
433 | ||
434 | <sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } | |
435 | <sr>, 0xd0/<sr:opc>, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
436 | <sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
437 | <sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } | |
438 | <sr>, 0xc0/<sr:opc>, i186, W|Modrm|No_sSuf, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
439 | <sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
440 | <sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } | |
441 | <sr>, 0xd2/<sr:opc>, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
442 | <sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
443 | <sr>, 0xd0/<sr:opc>, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
444 | ||
445 | <sr> | |
e20298da | 446 | |
ffa25710 JB |
447 | <shd:opc, l:0, r:8> |
448 | ||
449 | sh<shd>d, 0x24 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
450 | sh<shd>d, 0x0fa4 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 451 | sh<shd>d, 0x24 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
ffa25710 JB |
452 | sh<shd>d, 0xa5 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
453 | sh<shd>d, 0x0fa5 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
dd74a603 | 454 | sh<shd>d, 0xa5 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
ffa25710 JB |
455 | sh<shd>d, 0x0fa5 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
456 | ||
457 | <shd> | |
40b8e679 L |
458 | |
459 | // Control transfer instructions. | |
448cf9e6 IB |
460 | call, 0xe8, No64, JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } |
461 | call, 0xe8, x64, Amd64|JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } | |
462 | call, 0xe8, x64, Intel64|JumpDword|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } | |
463 | call, 0xff/2, No64, Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } | |
464 | call, 0xff/2, x64, Amd64|Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } | |
465 | call, 0xff/2, x64, Intel64|Modrm|JumpAbsolute|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } | |
5990e377 | 466 | // Intel Syntax remaining call instances. |
448cf9e6 IB |
467 | call, 0x9a, No64, JumpInterSegment|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } |
468 | call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|NoSuf, { Dword|Fword|BaseIndex } | |
469 | call, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|ImplicitStackOp|NoSuf, { Dword|Fword|Tbyte|BaseIndex } | |
4fdeb2a3 | 470 | lcall, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } |
68993386 | 471 | lcall, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } |
4fdeb2a3 | 472 | lcall, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } |
68993386 JB |
473 | |
474 | jmp, 0xeb, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } | |
4fdeb2a3 JB |
475 | jmp, 0xeb, x64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 } |
476 | jmp, 0xff/4, No64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } | |
477 | jmp, 0xff/4, x64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } | |
478 | jmp, 0xff/4, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } | |
5990e377 | 479 | // Intel Syntax remaining jmp instances. |
4fdeb2a3 | 480 | jmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } |
68993386 | 481 | jmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex } |
4fdeb2a3 JB |
482 | jmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } |
483 | ljmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } | |
68993386 | 484 | ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } |
4fdeb2a3 JB |
485 | ljmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } |
486 | ||
448cf9e6 IB |
487 | ret, 0xc3, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} |
488 | ret, 0xc2, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } | |
489 | ret, 0xc3, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} | |
490 | ret, 0xc2, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } | |
491 | ret, 0xc3, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} | |
492 | ret, 0xc2, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } | |
68993386 JB |
493 | lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} |
494 | lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } | |
ddab3d59 | 495 | // Intel Syntax. |
68993386 JB |
496 | retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} |
497 | retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } | |
ddab3d59 | 498 | |
448cf9e6 IB |
499 | enter, 0xc8, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } |
500 | enter, 0xc8, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } | |
501 | leave, 0xc9, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} | |
502 | leave, 0xc9, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} | |
40b8e679 | 503 | |
33b6a20a | 504 | <cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, + |
4c4898e8 JB |
505 | s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f> |
506 | ||
40b8e679 | 507 | // Conditional jumps. |
68993386 | 508 | j<cc>, 0x7<cc:opc>, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } |
40b8e679 L |
509 | |
510 | // jcxz vs. jecxz is chosen on the basis of the address size prefix. | |
4fdeb2a3 JB |
511 | jcxz, 0xe3, No64, JumpByte|Size16|NoSuf, { Disp8 } |
512 | jecxz, 0xe3, i386, JumpByte|Size32|NoSuf, { Disp8 } | |
513 | jrcxz, 0xe3, x64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 } | |
40b8e679 L |
514 | |
515 | // The loop instructions also use the address size prefix to select | |
516 | // %cx rather than %ecx for the loop count, so the `w' form of these | |
517 | // instructions emit an address size prefix rather than a data size | |
518 | // prefix. | |
4fdeb2a3 JB |
519 | loop, 0xe2, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } |
520 | loop, 0xe2, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } | |
521 | loopz, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } | |
522 | loopz, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } | |
523 | loope, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } | |
524 | loope, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } | |
525 | loopnz, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } | |
526 | loopnz, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } | |
527 | loopne, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } | |
528 | loopne, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } | |
40b8e679 L |
529 | |
530 | // Set byte on flag instructions. | |
e20298da | 531 | set<cc>, 0xf9<cc:opc>/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Unspecified|BaseIndex } |
40b8e679 L |
532 | |
533 | // String manipulation. | |
68993386 JB |
534 | cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} |
535 | cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
536 | scmp, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} | |
537 | scmp, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
4fdeb2a3 JB |
538 | ins, 0x6c, i186, W|No_sSuf|No_qSuf|RepPrefixOk, {} |
539 | ins, 0x6c, i186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex } | |
540 | outs, 0x6e, i186, W|No_sSuf|No_qSuf|RepPrefixOk, {} | |
541 | outs, 0x6e, i186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg } | |
68993386 JB |
542 | lods, 0xac, 0, W|No_sSuf|RepPrefixOk, {} |
543 | lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
544 | lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
545 | slod, 0xac, 0, W|No_sSuf|RepPrefixOk, {} | |
546 | slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
547 | slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
548 | movs, 0xa4, 0, W|No_sSuf|RepPrefixOk, {} | |
549 | movs, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
550 | smov, 0xa4, 0, W|No_sSuf|RepPrefixOk, {} | |
551 | smov, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
552 | scas, 0xae, 0, W|No_sSuf|RepPrefixOk, {} | |
553 | scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
554 | scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
555 | ssca, 0xae, 0, W|No_sSuf|RepPrefixOk, {} | |
556 | ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
557 | ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
558 | stos, 0xaa, 0, W|No_sSuf|RepPrefixOk, {} | |
559 | stos, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
560 | stos, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
561 | ssto, 0xaa, 0, W|No_sSuf|RepPrefixOk, {} | |
562 | ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
563 | ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
564 | xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {} | |
565 | xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex } | |
40b8e679 L |
566 | |
567 | // Bit manipulation. | |
e20298da CL |
568 | bsf, 0xfbc, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
569 | bsr, 0xfbd, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
570 | bt, 0xfa3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
ad2f4436 | 571 | bt, 0xfba/4, i386, Modrm|No_bSuf|No_sSuf|Optimize, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
e20298da | 572 | btc, 0xfbb, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
ad2f4436 | 573 | btc, 0xfba/7, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
e20298da | 574 | btr, 0xfb3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
ad2f4436 | 575 | btr, 0xfba/6, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
e20298da | 576 | bts, 0xfab, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
ad2f4436 | 577 | bts, 0xfba/5, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
40b8e679 L |
578 | |
579 | // Interrupts & op. sys insns. | |
580 | // See gas/config/tc-i386.c for conversion of 'int $3' into the special | |
581 | // int 3 insn. | |
448cf9e6 IB |
582 | int, 0xcd, 0, ImplicitStackOp|NoSuf, { Imm8 } |
583 | int1, 0xf1, 0, ImplicitStackOp|NoSuf, {} | |
584 | int3, 0xcc, 0, ImplicitStackOp|NoSuf, {} | |
585 | into, 0xce, No64, ImplicitStackOp|NoSuf, {} | |
586 | iret, 0xcf, 0, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf, {} | |
40b8e679 | 587 | // i386sl, i486sl, later 486, and Pentium. |
4fdeb2a3 | 588 | rsm, 0xfaa, i386, NoSuf, {} |
40b8e679 | 589 | |
a5e91879 | 590 | bound, 0x62, i186&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } |
40b8e679 | 591 | |
68993386 | 592 | hlt, 0xf4, 0, NoSuf, {} |
40b8e679 | 593 | |
e20298da | 594 | nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
40b8e679 L |
595 | |
596 | // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in | |
597 | // 32bit mode and "xchg %rax,%rax" in 64bit mode. | |
68993386 | 598 | nop, 0x90, 0, NoSuf|RepPrefixOk, {} |
40b8e679 L |
599 | |
600 | // Protection control. | |
a5e91879 JB |
601 | arpl, 0x63, i286&No64, RegMem|CheckOperandSize|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Reg16|Reg32 } |
602 | arpl, 0x63, i286&No64, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Word|Unspecified|BaseIndex } | |
ba25141c JB |
603 | lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } |
604 | lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
a5e91879 | 605 | lgdt, 0xf01/2, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } |
4fdeb2a3 | 606 | lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } |
a5e91879 | 607 | lidt, 0xf01/3, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } |
4fdeb2a3 | 608 | lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } |
5eeeafe0 JB |
609 | lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } |
610 | lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
e20298da | 611 | lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Unspecified|BaseIndex } |
ba25141c JB |
612 | lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } |
613 | lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
5eeeafe0 JB |
614 | ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } |
615 | ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
4fdeb2a3 | 616 | |
a5e91879 | 617 | sgdt, 0xf01/0, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } |
4fdeb2a3 | 618 | sgdt, 0xf01/0, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } |
a5e91879 | 619 | sidt, 0xf01/1, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } |
4fdeb2a3 JB |
620 | sidt, 0xf01/1, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } |
621 | sldt, 0xf00/0, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } | |
622 | sldt, 0xf00/0, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
623 | smsw, 0xf01/4, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 } | |
624 | smsw, 0xf01/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
625 | str, 0xf00/1, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } | |
626 | str, 0xf00/1, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
627 | ||
5eeeafe0 JB |
628 | verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } |
629 | verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
630 | verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } | |
631 | verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
40b8e679 L |
632 | |
633 | // Floating point instructions. | |
634 | ||
635 | // load | |
bd782808 | 636 | fld, 0xd9/0, FP, Modrm|NoSuf, { FloatReg } |
4fdeb2a3 | 637 | fld, 0xd9/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
bd782808 | 638 | fld, 0xd9/0, FP, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } |
40b8e679 | 639 | // Intel Syntax |
4fdeb2a3 JB |
640 | fld, 0xdb/5, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } |
641 | fild, 0xdf/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
642 | fild, 0xdf/5, FP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } | |
643 | fildll, 0xdf/5, FP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } | |
644 | fldt, 0xdb/5, FP, Modrm|NoSuf, { Unspecified|BaseIndex } | |
645 | fbld, 0xdf/4, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } | |
40b8e679 L |
646 | |
647 | // store (no pop) | |
bd782808 | 648 | fst, 0xdd/2, FP, Modrm|NoSuf, { FloatReg } |
4fdeb2a3 | 649 | fst, 0xd9/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
bd782808 | 650 | fst, 0xdd/2, FP, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } |
4fdeb2a3 | 651 | fist, 0xdf/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } |
40b8e679 L |
652 | |
653 | // store (with pop) | |
bd782808 | 654 | fstp, 0xdd/3, FP, Modrm|NoSuf, { FloatReg } |
4fdeb2a3 | 655 | fstp, 0xd9/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
bd782808 | 656 | fstp, 0xdd/3, FP, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } |
40b8e679 | 657 | // Intel Syntax |
4fdeb2a3 JB |
658 | fstp, 0xdb/7, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } |
659 | fistp, 0xdf/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
660 | fistp, 0xdf/7, FP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } | |
661 | fistpll, 0xdf/7, FP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } | |
662 | fstpt, 0xdb/7, FP, Modrm|NoSuf, { Unspecified|BaseIndex } | |
663 | fbstp, 0xdf/6, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } | |
40b8e679 L |
664 | |
665 | // exchange %st<n> with %st0 | |
bd782808 | 666 | fxch, 0xd9/1, FP, Modrm|NoSuf, { FloatReg } |
40b8e679 | 667 | // alias for fxch %st(1) |
4fdeb2a3 | 668 | fxch, 0xd9c9, FP, NoSuf, {} |
40b8e679 L |
669 | |
670 | // comparison (without pop) | |
bd782808 | 671 | fcom, 0xd8/2, FP, Modrm|NoSuf, { FloatReg } |
40b8e679 | 672 | // alias for fcom %st(1) |
4fdeb2a3 JB |
673 | fcom, 0xd8d1, FP, NoSuf, {} |
674 | fcom, 0xd8/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } | |
bd782808 | 675 | fcom, 0xd8/2, FP, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } |
4fdeb2a3 | 676 | ficom, 0xde/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } |
40b8e679 L |
677 | |
678 | // comparison (with pop) | |
bd782808 | 679 | fcomp, 0xd8/3, FP, Modrm|NoSuf, { FloatReg } |
40b8e679 | 680 | // alias for fcomp %st(1) |
4fdeb2a3 JB |
681 | fcomp, 0xd8d9, FP, NoSuf, {} |
682 | fcomp, 0xd8/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } | |
bd782808 | 683 | fcomp, 0xd8/3, FP, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } |
4fdeb2a3 JB |
684 | ficomp, 0xde/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } |
685 | fcompp, 0xded9, FP, NoSuf, {} | |
40b8e679 L |
686 | |
687 | // unordered comparison (with pop) | |
bd782808 | 688 | fucom, 0xdd/4, i387, Modrm|NoSuf, { FloatReg } |
40b8e679 | 689 | // alias for fucom %st(1) |
4fdeb2a3 | 690 | fucom, 0xdde1, i387, NoSuf, {} |
25a0d393 | 691 | fucomp, 0xdd/5, i387, Modrm|NoSuf, { FloatReg } |
40b8e679 | 692 | // alias for fucomp %st(1) |
4fdeb2a3 JB |
693 | fucomp, 0xdde9, i387, NoSuf, {} |
694 | fucompp, 0xdae9, i387, NoSuf, {} | |
40b8e679 | 695 | |
4fdeb2a3 JB |
696 | ftst, 0xd9e4, FP, NoSuf, {} |
697 | fxam, 0xd9e5, FP, NoSuf, {} | |
40b8e679 L |
698 | |
699 | // load constants into %st0 | |
4fdeb2a3 JB |
700 | fld1, 0xd9e8, FP, NoSuf, {} |
701 | fldl2t, 0xd9e9, FP, NoSuf, {} | |
702 | fldl2e, 0xd9ea, FP, NoSuf, {} | |
703 | fldpi, 0xd9eb, FP, NoSuf, {} | |
704 | fldlg2, 0xd9ec, FP, NoSuf, {} | |
705 | fldln2, 0xd9ed, FP, NoSuf, {} | |
706 | fldz, 0xd9ee, FP, NoSuf, {} | |
40b8e679 L |
707 | |
708 | // Arithmetic. | |
709 | ||
710 | // add | |
bd782808 | 711 | fadd, 0xd8/0, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } |
40b8e679 | 712 | // alias for fadd %st(i), %st |
bd782808 | 713 | fadd, 0xd8/0, FP, Modrm|NoSuf, { FloatReg } |
40b8e679 | 714 | // alias for faddp |
4fdeb2a3 JB |
715 | fadd, 0xdec1, FP, NoSuf|Ugh|ATTMnemonic, {} |
716 | fadd, 0xd8/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } | |
717 | fiadd, 0xde/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
40b8e679 | 718 | |
bd782808 JB |
719 | faddp, 0xde/0, FP, D|Modrm|NoSuf|Ugh, { FloatAcc, FloatReg } |
720 | faddp, 0xde/0, FP, Modrm|NoSuf, { FloatReg } | |
40b8e679 | 721 | // alias for faddp %st, %st(1) |
4fdeb2a3 | 722 | faddp, 0xdec1, FP, NoSuf, {} |
40b8e679 L |
723 | |
724 | // subtract | |
bd782808 JB |
725 | fsub, 0xd8/4, FP, Modrm|NoSuf, { FloatReg } |
726 | fsub, 0xd8/4, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } | |
40b8e679 | 727 | // alias for fsubp |
7d3182d6 | 728 | fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {} |
4fdeb2a3 JB |
729 | fsub, 0xd8/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
730 | fisub, 0xde/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
731 | ||
7d3182d6 JB |
732 | fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } |
733 | fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } | |
734 | fsubp, 0xdee1, FP, NoSuf|ATTMnemonic, {} | |
bd782808 JB |
735 | fsubp, 0xde/5, FP, Modrm|NoSuf, { FloatAcc, FloatReg } |
736 | fsubp, 0xde/5, FP, Modrm|NoSuf, { FloatReg } | |
4fdeb2a3 | 737 | fsubp, 0xdee9, FP, NoSuf, {} |
40b8e679 L |
738 | |
739 | // subtract reverse | |
bd782808 JB |
740 | fsubr, 0xd8/5, FP, Modrm|NoSuf, { FloatReg } |
741 | fsubr, 0xd8/5, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } | |
40b8e679 | 742 | // alias for fsubrp |
7d3182d6 | 743 | fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {} |
4fdeb2a3 JB |
744 | fsubr, 0xd8/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
745 | fisubr, 0xde/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
746 | ||
7d3182d6 JB |
747 | fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } |
748 | fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } | |
749 | fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic, {} | |
bd782808 JB |
750 | fsubrp, 0xde/4, FP, Modrm|NoSuf, { FloatAcc, FloatReg } |
751 | fsubrp, 0xde/4, FP, Modrm|NoSuf, { FloatReg } | |
4fdeb2a3 | 752 | fsubrp, 0xdee1, FP, NoSuf, {} |
40b8e679 L |
753 | |
754 | // multiply | |
bd782808 JB |
755 | fmul, 0xd8/1, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } |
756 | fmul, 0xd8/1, FP, Modrm|NoSuf, { FloatReg } | |
40b8e679 | 757 | // alias for fmulp |
4fdeb2a3 JB |
758 | fmul, 0xdec9, FP, NoSuf|Ugh|ATTMnemonic, {} |
759 | fmul, 0xd8/1, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } | |
760 | fimul, 0xde/1, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
40b8e679 | 761 | |
bd782808 JB |
762 | fmulp, 0xde/1, FP, D|Modrm|NoSuf|Ugh, { FloatAcc, FloatReg } |
763 | fmulp, 0xde/1, FP, Modrm|NoSuf, { FloatReg } | |
4943d587 | 764 | // alias for fmulp %st, %st(1) |
4fdeb2a3 | 765 | fmulp, 0xdec9, FP, NoSuf, {} |
40b8e679 L |
766 | |
767 | // divide | |
bd782808 JB |
768 | fdiv, 0xd8/6, FP, Modrm|NoSuf, { FloatReg } |
769 | fdiv, 0xd8/6, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } | |
40b8e679 | 770 | // alias for fdivp |
7d3182d6 | 771 | fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {} |
4fdeb2a3 JB |
772 | fdiv, 0xd8/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
773 | fidiv, 0xde/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
774 | ||
7d3182d6 JB |
775 | fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } |
776 | fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } | |
777 | fdivp, 0xdef1, FP, NoSuf|ATTMnemonic, {} | |
bd782808 JB |
778 | fdivp, 0xde/7, FP, Modrm|NoSuf, { FloatAcc, FloatReg } |
779 | fdivp, 0xde/7, FP, Modrm|NoSuf, { FloatReg } | |
4fdeb2a3 | 780 | fdivp, 0xdef9, FP, NoSuf, {} |
40b8e679 L |
781 | |
782 | // divide reverse | |
bd782808 JB |
783 | fdivr, 0xd8/7, FP, Modrm|NoSuf, { FloatReg } |
784 | fdivr, 0xd8/7, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } | |
40b8e679 | 785 | // alias for fdivrp |
7d3182d6 | 786 | fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {} |
4fdeb2a3 JB |
787 | fdivr, 0xd8/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } |
788 | fidivr, 0xde/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } | |
789 | ||
7d3182d6 JB |
790 | fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } |
791 | fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } | |
792 | fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic, {} | |
bd782808 JB |
793 | fdivrp, 0xde/6, FP, Modrm|NoSuf, { FloatAcc, FloatReg } |
794 | fdivrp, 0xde/6, FP, Modrm|NoSuf, { FloatReg } | |
4fdeb2a3 JB |
795 | fdivrp, 0xdef1, FP, NoSuf, {} |
796 | ||
797 | f2xm1, 0xd9f0, FP, NoSuf, {} | |
798 | fyl2x, 0xd9f1, FP, NoSuf, {} | |
799 | fptan, 0xd9f2, FP, NoSuf, {} | |
800 | fpatan, 0xd9f3, FP, NoSuf, {} | |
801 | fxtract, 0xd9f4, FP, NoSuf, {} | |
802 | fprem1, 0xd9f5, i387, NoSuf, {} | |
803 | fdecstp, 0xd9f6, FP, NoSuf, {} | |
804 | fincstp, 0xd9f7, FP, NoSuf, {} | |
805 | fprem, 0xd9f8, FP, NoSuf, {} | |
806 | fyl2xp1, 0xd9f9, FP, NoSuf, {} | |
807 | fsqrt, 0xd9fa, FP, NoSuf, {} | |
808 | fsincos, 0xd9fb, i387, NoSuf, {} | |
809 | frndint, 0xd9fc, FP, NoSuf, {} | |
810 | fscale, 0xd9fd, FP, NoSuf, {} | |
811 | fsin, 0xd9fe, i387, NoSuf, {} | |
812 | fcos, 0xd9ff, i387, NoSuf, {} | |
813 | fchs, 0xd9e0, FP, NoSuf, {} | |
814 | fabs, 0xd9e1, FP, NoSuf, {} | |
40b8e679 L |
815 | |
816 | // processor control | |
4fdeb2a3 JB |
817 | fninit, 0xdbe3, FP, NoSuf, {} |
818 | finit, 0xdbe3, FP, NoSuf|FWait, {} | |
819 | fldcw, 0xd9/5, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
820 | fnstcw, 0xd9/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
821 | fstcw, 0xd9/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } | |
822 | fnstsw, 0xdfe0, i287|i387, IgnoreSize|NoSuf, { Acc|Word } | |
823 | fnstsw, 0xdd/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
824 | fnstsw, 0xdfe0, i287|i387, NoSuf, {} | |
825 | fstsw, 0xdfe0, i287|i387, IgnoreSize|NoSuf|FWait, { Acc|Word } | |
826 | fstsw, 0xdd/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } | |
827 | fstsw, 0xdfe0, i287|i387, NoSuf|FWait, {} | |
828 | fnclex, 0xdbe2, FP, NoSuf, {} | |
829 | fclex, 0xdbe2, FP, NoSuf|FWait, {} | |
62b3f548 | 830 | // Short forms of fldenv, fstenv, fsave, and frstor use data size prefix. |
4fdeb2a3 JB |
831 | fnstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } |
832 | fstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } | |
833 | fldenv, 0xd9/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } | |
834 | fnsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } | |
835 | fsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } | |
836 | frstor, 0xdd/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } | |
309d3373 | 837 | // 8087 only |
4fdeb2a3 JB |
838 | fneni, 0xdbe0, i8087, NoSuf, {} |
839 | feni, 0xdbe0, i8087, NoSuf|FWait, {} | |
840 | fndisi, 0xdbe1, i8087, NoSuf, {} | |
841 | fdisi, 0xdbe1, i8087, NoSuf|FWait, {} | |
309d3373 | 842 | // 287 only |
4fdeb2a3 JB |
843 | fnsetpm, 0xdbe4, i287, NoSuf, {} |
844 | fsetpm, 0xdbe4, i287, NoSuf|FWait, {} | |
845 | frstpm, 0xdbe5, i287, NoSuf, {} | |
309d3373 | 846 | |
bd782808 | 847 | ffree, 0xdd/0, FP, Modrm|NoSuf, { FloatReg } |
40b8e679 | 848 | // P6:free st(i), pop st |
bd782808 | 849 | ffreep, 0xdf/0, i687, Modrm|NoSuf, { FloatReg } |
4fdeb2a3 JB |
850 | fnop, 0xd9d0, FP, NoSuf, {} |
851 | fwait, 0x9b, FP, NoSuf, {} | |
40b8e679 L |
852 | |
853 | // Opcode prefixes; we allow them as separate insns too. | |
854 | ||
a5e91879 | 855 | addr16, 0x67, i386&No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} |
4fdeb2a3 | 856 | addr32, 0x67, i386, Size32|IgnoreSize|NoSuf|IsPrefix, {} |
a5e91879 | 857 | aword, 0x67, i386&No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} |
4fdeb2a3 JB |
858 | adword, 0x67, i386, Size32|IgnoreSize|NoSuf|IsPrefix, {} |
859 | data16, 0x66, i386, Size16|IgnoreSize|NoSuf|IsPrefix, {} | |
a5e91879 | 860 | data32, 0x66, i386&No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} |
4fdeb2a3 | 861 | word, 0x66, i386, Size16|IgnoreSize|NoSuf|IsPrefix, {} |
a5e91879 | 862 | dword, 0x66, i386&No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} |
68993386 JB |
863 | lock, 0xf0, 0, NoSuf|IsPrefix, {} |
864 | wait, 0x9b, 0, NoSuf|IsPrefix, {} | |
865 | cs, 0x2e, 0, NoSuf|IsPrefix, {} | |
866 | ds, 0x3e, 0, NoSuf|IsPrefix, {} | |
4fdeb2a3 JB |
867 | es, 0x26, No64, NoSuf|IsPrefix, {} |
868 | fs, 0x64, i386, NoSuf|IsPrefix, {} | |
869 | gs, 0x65, i386, NoSuf|IsPrefix, {} | |
870 | ss, 0x36, No64, NoSuf|IsPrefix, {} | |
68993386 JB |
871 | rep, 0xf3, 0, NoSuf|IsPrefix, {} |
872 | repe, 0xf3, 0, NoSuf|IsPrefix, {} | |
873 | repz, 0xf3, 0, NoSuf|IsPrefix, {} | |
874 | repne, 0xf2, 0, NoSuf|IsPrefix, {} | |
875 | repnz, 0xf2, 0, NoSuf|IsPrefix, {} | |
876 | ht, 0x3e, 0, NoSuf|IsPrefix, {} | |
877 | hnt, 0x2e, 0, NoSuf|IsPrefix, {} | |
4fdeb2a3 JB |
878 | rex, 0x40, x64, NoSuf|IsPrefix, {} |
879 | rexz, 0x41, x64, NoSuf|IsPrefix, {} | |
880 | rexy, 0x42, x64, NoSuf|IsPrefix, {} | |
881 | rexyz, 0x43, x64, NoSuf|IsPrefix, {} | |
882 | rexx, 0x44, x64, NoSuf|IsPrefix, {} | |
883 | rexxz, 0x45, x64, NoSuf|IsPrefix, {} | |
884 | rexxy, 0x46, x64, NoSuf|IsPrefix, {} | |
885 | rexxyz, 0x47, x64, NoSuf|IsPrefix, {} | |
886 | rex64, 0x48, x64, NoSuf|IsPrefix, {} | |
887 | rex64z, 0x49, x64, NoSuf|IsPrefix, {} | |
888 | rex64y, 0x4a, x64, NoSuf|IsPrefix, {} | |
889 | rex64yz, 0x4b, x64, NoSuf|IsPrefix, {} | |
890 | rex64x, 0x4c, x64, NoSuf|IsPrefix, {} | |
891 | rex64xz, 0x4d, x64, NoSuf|IsPrefix, {} | |
892 | rex64xy, 0x4e, x64, NoSuf|IsPrefix, {} | |
893 | rex64xyz, 0x4f, x64, NoSuf|IsPrefix, {} | |
894 | rex.b, 0x41, x64, NoSuf|IsPrefix, {} | |
895 | rex.x, 0x42, x64, NoSuf|IsPrefix, {} | |
896 | rex.xb, 0x43, x64, NoSuf|IsPrefix, {} | |
897 | rex.r, 0x44, x64, NoSuf|IsPrefix, {} | |
898 | rex.rb, 0x45, x64, NoSuf|IsPrefix, {} | |
899 | rex.rx, 0x46, x64, NoSuf|IsPrefix, {} | |
900 | rex.rxb, 0x47, x64, NoSuf|IsPrefix, {} | |
901 | rex.w, 0x48, x64, NoSuf|IsPrefix, {} | |
902 | rex.wb, 0x49, x64, NoSuf|IsPrefix, {} | |
903 | rex.wx, 0x4a, x64, NoSuf|IsPrefix, {} | |
904 | rex.wxb, 0x4b, x64, NoSuf|IsPrefix, {} | |
905 | rex.wr, 0x4c, x64, NoSuf|IsPrefix, {} | |
906 | rex.wrb, 0x4d, x64, NoSuf|IsPrefix, {} | |
907 | rex.wrx, 0x4e, x64, NoSuf|IsPrefix, {} | |
908 | rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {} | |
40b8e679 | 909 | |
31184569 JB |
910 | // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) |
911 | ||
3086ed9a | 912 | <pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:No64, disp32:Disp32:i386, + |
33b6a20a JB |
913 | load:Load:0, store:Store:0, + |
914 | vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, + | |
dd74a603 CL |
915 | rex:REX:x64, rex2:REX2:APX_F, nf:NF:APX_F, + |
916 | nooptimize:NoOptimize:0> | |
31184569 | 917 | |
68993386 | 918 | {<pseudopfx>}, PSEUDO_PREFIX/Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, NoSuf|IsPrefix, {} |
86fa6981 | 919 | |
0ebcbb1b | 920 | // 486 extensions (BSWAP moved elsewhere). |
40b8e679 | 921 | |
e20298da CL |
922 | xadd, 0xfc0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |
923 | cmpxchg, 0xfb0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } | |
4fdeb2a3 JB |
924 | invd, 0xf08, i486, NoSuf, {} |
925 | wbinvd, 0xf09, i486, NoSuf, {} | |
926 | invlpg, 0xf01/7, i486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
40b8e679 L |
927 | |
928 | // 586 and late 486 extensions. | |
4fdeb2a3 | 929 | cpuid, 0xfa2, i486, NoSuf, {} |
40b8e679 L |
930 | |
931 | // Pentium extensions. | |
4fdeb2a3 JB |
932 | wrmsr, 0xf30, i586, NoSuf, {} |
933 | rdtsc, 0xf31, i586, NoSuf, {} | |
934 | rdmsr, 0xf32, i586, NoSuf, {} | |
935 | cmpxchg8b, 0xfc7/1, i586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex } | |
40b8e679 L |
936 | |
937 | // Pentium II/Pentium Pro extensions. | |
4fdeb2a3 | 938 | sysenter, 0xf34, x64, Intel64Only|NoSuf, {} |
a5e91879 | 939 | sysenter, 0xf34, i686&No64, NoSuf, {} |
4fdeb2a3 | 940 | sysexit, 0xf35, x64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {} |
a5e91879 | 941 | sysexit, 0xf35, i686&No64, NoSuf, {} |
4fdeb2a3 | 942 | fxsave, 0xfae/0, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } |
a5e91879 | 943 | fxsave64, 0xfae/0, FXSR&x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
4fdeb2a3 | 944 | fxrstor, 0xfae/1, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } |
a5e91879 | 945 | fxrstor64, 0xfae/1, FXSR&x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
4fdeb2a3 | 946 | rdpmc, 0xf33, i686, NoSuf, {} |
40b8e679 | 947 | // official undefined instr. |
4fdeb2a3 | 948 | ud2, 0xf0b, i186, NoSuf, {} |
40b8e679 | 949 | // alias for ud2 |
4fdeb2a3 | 950 | ud2a, 0xf0b, i186, NoSuf, {} |
40b8e679 | 951 | // 2nd. official undefined instr. |
9c19e9ec | 952 | ud1, 0xfb9, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
b414985b | 953 | // alias for ud1 |
9c19e9ec | 954 | ud2b, 0xfb9, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
66f1eba0 | 955 | // 3rd official undefined instr (older CPUs don't take a ModR/M byte) |
9c19e9ec | 956 | ud0, 0xfff, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
4fdeb2a3 | 957 | |
3083f376 | 958 | cmov<cc>, 0x4<cc:opc>, CMOV&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } |
e20298da | 959 | cmov<cc>, 0xf4<cc:opc>, CMOV, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
4fdeb2a3 | 960 | |
bd782808 JB |
961 | fcmovb, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } |
962 | fcmovnae, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
963 | fcmove, 0xda/1, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
964 | fcmovbe, 0xda/2, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
965 | fcmovna, 0xda/2, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
966 | fcmovu, 0xda/3, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
967 | fcmovae, 0xdb/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
968 | fcmovnb, 0xdb/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
969 | fcmovne, 0xdb/1, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
970 | fcmova, 0xdb/2, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
971 | fcmovnbe, 0xdb/2, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
972 | fcmovnu, 0xdb/3, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
973 | ||
974 | fcomi, 0xdb/6, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
4fdeb2a3 | 975 | fcomi, 0xdbf1, i687, NoSuf, {} |
bd782808 JB |
976 | fcomi, 0xdb/6, i687, Modrm|NoSuf, { FloatReg } |
977 | fucomi, 0xdb/5, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
4fdeb2a3 | 978 | fucomi, 0xdbe9, i687, NoSuf, {} |
bd782808 JB |
979 | fucomi, 0xdb/5, i687, Modrm|NoSuf, { FloatReg } |
980 | fcomip, 0xdf/6, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
4fdeb2a3 | 981 | fcomip, 0xdff1, i687, NoSuf, {} |
bd782808 JB |
982 | fcomip, 0xdf/6, i687, Modrm|NoSuf, { FloatReg } |
983 | fcompi, 0xdf/6, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
4fdeb2a3 | 984 | fcompi, 0xdff1, i687, NoSuf, {} |
bd782808 JB |
985 | fcompi, 0xdf/6, i687, Modrm|NoSuf, { FloatReg } |
986 | fucomip, 0xdf/5, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
4fdeb2a3 | 987 | fucomip, 0xdfe9, i687, NoSuf, {} |
bd782808 JB |
988 | fucomip, 0xdf/5, i687, Modrm|NoSuf, { FloatReg } |
989 | fucompi, 0xdf/5, i687, Modrm|NoSuf, { FloatReg, FloatAcc } | |
4fdeb2a3 | 990 | fucompi, 0xdfe9, i687, NoSuf, {} |
bd782808 | 991 | fucompi, 0xdf/5, i687, Modrm|NoSuf, { FloatReg } |
40b8e679 L |
992 | |
993 | // Pentium4 extensions. | |
994 | ||
9c19e9ec | 995 | movnti, 0xfc3, SSE2, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
4fdeb2a3 JB |
996 | clflush, 0xfae/7, Clflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
997 | lfence, 0xfaee8, SSE2, NoSuf, {} | |
998 | mfence, 0xfaef0, SSE2, NoSuf, {} | |
bd5295b2 | 999 | // Processors that do not support PAUSE treat this opcode as a NOP instruction. |
4fdeb2a3 | 1000 | pause, 0xf390, i186, NoSuf, {} |
40b8e679 L |
1001 | |
1002 | // MMX/SSE2 instructions. | |
1003 | ||
3f155099 | 1004 | <mmx:cpu:pfx:attr:reg:mem, + |
f2a3a881 | 1005 | $avx:AVX:66:Vex128|Src1VVVV|VexW0|SSE2AVX:RegXMM:Xmmword, + |
3f155099 JB |
1006 | $sse:SSE2:66::RegXMM:Xmmword, + |
1007 | $mmx:MMX:::RegMMX:Qword> | |
24187fb9 JB |
1008 | // As above, but also allowing AVX512 (EVEX) encoding, to transform |
1009 | // in particular insns using eGPR-s. | |
c8866e3e CL |
1010 | <MMX:cpu:pfx:attr:vvvv:reg:mem, + |
1011 | $avx:AVX|AVX512VL:66:Vex128|EVex128|Src1VVVV|VexW0|Disp8MemShift=4|SSE2AVX:Vex128|EVex128|DstVVVV|VexW0|Disp8MemShift=4|SSE2AVX:RegXMM:Xmmword, + | |
1012 | $sse:SSE2:66:::RegXMM:Xmmword, + | |
1013 | $mmx:MMX::::RegMMX:Qword> | |
1014 | <MMXdq:opc:cpu:pfx:attr:vvvv:reg:mem, + | |
1015 | d:0:AVX|AVX512VL:66:Vex128|EVex128|Src1VVVV|VexW0|Disp8MemShift=4|SSE2AVX:Vex128|EVex128|DstVVVV|VexW0|Disp8MemShift=4|SSE2AVX:RegXMM:Xmmword, + | |
1016 | d:0:SSE2:66:::RegXMM:Xmmword, + | |
1017 | d:0:MMX::::RegMMX:Qword, + | |
1018 | q:1:AVX:66:Vex128|Src1VVVV|VexW0|SSE2AVX:Vex128|DstVVVV|VexW0|SSE2AVX:RegXMM:Xmmword, + | |
1019 | q:1:AVX512VL:66:EVex128|Src1VVVV|VexW1|Disp8MemShift=4|SSE2AVX:EVex128|DstVVVV|VexW1|Disp8MemShift=4|SSE2AVX:RegXMM:Xmmword, + | |
1020 | q:1:SSE2:66:::RegXMM:Xmmword, + | |
1021 | q:1:MMX::::RegMMX:Qword> | |
1022 | <MMXBW:cpu:pfx:attr:vvvv:reg:mem, + | |
1023 | $avx:AVX:66:Vex128|Src1VVVV|VexW0|SSE2AVX:Vex128|DstVVVV|VexW0|SSE2AVX:RegXMM:Xmmword, + | |
1024 | $apx:AVX512BW&AVX512VL:66:EVex128|Src1VVVV|VexW0|Disp8MemShift=4|SSE2AVX:EVex128|DstVVVV|VexW0|Disp8MemShift=4|SSE2AVX:RegXMM:Xmmword, + | |
1025 | $sse:SSE2:66:::RegXMM:Xmmword, + | |
1026 | $mmx:MMX::::RegMMX:Qword> | |
5cdaf100 | 1027 | |
3f155099 | 1028 | <sse2:cpu:attr:scal:vvvv, + |
f2a3a881 | 1029 | $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:Src1VVVV, + |
3f155099 | 1030 | $sse:SSE2:::> |
24187fb9 | 1031 | <SSE2BW:cpu:attr:vvvv, + |
f2a3a881 CL |
1032 | $avx:AVX:Vex128|VexW0|SSE2AVX:Src1VVVV, + |
1033 | $apx:AVX512BW&AVX512VL:EVex128|VexW0|Disp8MemShift=4|SSE2AVX:Src1VVVV, + | |
24187fb9 JB |
1034 | $sse:SSE2::> |
1035 | <SSE2D:cpu:attr:scal:vvvv, + | |
f2a3a881 | 1036 | $avx:AVX|AVX512VL:Vex128|EVex128|VexW0|Disp8MemShift=4|SSE2AVX:VexLIG|EVexLIG|VexW0|Disp8MemShift=2|SSE2AVX:Src1VVVV, + |
24187fb9 JB |
1037 | $sse:SSE2:::> |
1038 | <SSE2Q:cpu:attr:scal:vvvv, + | |
f2a3a881 CL |
1039 | $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:Src1VVVV, + |
1040 | $apx:AVX512VL:EVex128|VexW1|Disp8MemShift=4|SSE2AVX:EVexLIG|VexW1|Disp8MemShift=3|SSE2AVX:Src1VVVV, + | |
24187fb9 | 1041 | $sse:SSE2:::> |
5cdaf100 | 1042 | |
b9df5afb | 1043 | <bw:opc:vexw:elem:kcpu:kpfx:cpubmi, + |
4fdeb2a3 JB |
1044 | b:0:VexW0:Byte:AVX512DQ:66:AVX512VBMI, + |
1045 | w:1:VexW1:Word:AVX512F::AVX512BW> | |
b9df5afb | 1046 | |
fa88a361 HJ |
1047 | <dq:opc:vexw:vexw64:elem:cpu64:gpr:kpfx, + |
1048 | d:0:VexW0::Dword::Reg32:66, + | |
1049 | q:1:VexW1:VexW1:Qword:x64:Reg64:> | |
6473a592 | 1050 | |
4fdeb2a3 | 1051 | emms, 0xf77, MMX, NoSuf, {} |
40b8e679 L |
1052 | // These really shouldn't allow for Reg64 (movq is the right mnemonic for |
1053 | // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's | |
1054 | // spec). AMD's spec, having been in existence for much longer, failed to | |
1055 | // recognize that and specified movd for 32- and 64-bit operations. | |
24187fb9 JB |
1056 | movd, 0x666e, AVX|AVX512F, D|Modrm|Vex128|EVex128|Space0F|VexW0|Disp8MemShift=2|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } |
1057 | movd, 0x666e, x64&(AVX|AVX512F), D|Modrm|Vex128|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } | |
4fdeb2a3 | 1058 | movd, 0x660f6e, SSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
a5e91879 | 1059 | movd, 0x660f6e, SSE2&x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } |
04784e33 | 1060 | // The MMX templates have to remain after at least the SSE2AVX ones. |
4fdeb2a3 | 1061 | movd, 0xf6e, MMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } |
a5e91879 | 1062 | movd, 0xf6e, MMX&x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } |
9405f24b JB |
1063 | movq, 0xf37e, AVX, Load|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1064 | movq, 0x66d6, AVX, Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
24187fb9 JB |
1065 | movq, 0xf37e, AVX512F, Load|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1066 | movq, 0x66d6, AVX512F, Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
1067 | movq, 0x666e, x64&(AVX|AVX512F), D|Modrm|Vex128|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1068 | movq, 0xf30f7e, SSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } |
1069 | movq, 0x660fd6, SSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } | |
a5e91879 | 1070 | movq, 0x660f6e, SSE2&x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } |
04784e33 | 1071 | // The MMX templates have to remain after at least the SSE2AVX ones. |
4fdeb2a3 | 1072 | movq, 0xf6f, MMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } |
a5e91879 | 1073 | movq, 0xf6e, MMX&x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } |
24187fb9 JB |
1074 | packssdw<MMXBW>, 0x<MMXBW:pfx>0f6b, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
1075 | packsswb<MMXBW>, 0x<MMXBW:pfx>0f63, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1076 | packuswb<MMXBW>, 0x<MMXBW:pfx>0f67, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1077 | padd<bw><MMXBW>, 0x<MMXBW:pfx>0ffc | <bw:opc>, <MMXBW:cpu>, Modrm|<MMXBW:attr>|C|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1078 | paddd<MMX>, 0x<MMX:pfx>0ffe, <MMX:cpu>, Modrm|<MMX:attr>|C|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } | |
1079 | paddq<SSE2Q>, 0x660fd4, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1080 | paddq, 0xfd4, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 JB |
1081 | padds<bw><MMXBW>, 0x<MMXBW:pfx>0fec | <bw:opc>, <MMXBW:cpu>, Modrm|<MMXBW:attr>|C|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
1082 | paddus<bw><MMXBW>, 0x<MMXBW:pfx>0fdc | <bw:opc>, <MMXBW:cpu>, Modrm|<MMXBW:attr>|C|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1083 | pand<MMX>, 0x<MMX:pfx>0fdb, <MMX:cpu>, Modrm|<MMX:attr>|C|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } | |
1084 | pandn<MMX>, 0x<MMX:pfx>0fdf, <MMX:cpu>, Modrm|<MMX:attr>|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } | |
68993386 JB |
1085 | pcmpeq<bw><mmx>, 0x<mmx:pfx>0f74 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } |
1086 | pcmpeqd<mmx>, 0x<mmx:pfx>0f76, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
b5c37946 SJ |
1087 | pcmpgt<bw><mmx>, 0x<mmx:pfx>0f64 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf|Optimize, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } |
1088 | pcmpgtd<mmx>, 0x<mmx:pfx>0f66, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf|Optimize, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
24187fb9 JB |
1089 | pmaddwd<MMXBW>, 0x<MMXBW:pfx>0ff5, <MMXBW:cpu>, Modrm|<MMXBW:attr>|C|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
1090 | pmulhw<MMXBW>, 0x<MMXBW:pfx>0fe5, <MMXBW:cpu>, Modrm|<MMXBW:attr>|C|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1091 | pmullw<MMXBW>, 0x<MMXBW:pfx>0fd5, <MMXBW:cpu>, Modrm|<MMXBW:attr>|C|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1092 | por<MMX>, 0x<MMX:pfx>0feb, <MMX:cpu>, Modrm|<MMX:attr>|C|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } | |
1093 | psllw<MMXBW>, 0x<MMXBW:pfx>0ff1, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
c8866e3e | 1094 | psllw<MMXBW>, 0x<MMXBW:pfx>0f71/6, <MMXBW:cpu>, Modrm|<MMXBW:vvvv>|NoSuf, { Imm8, <MMXBW:reg> } |
24187fb9 | 1095 | psll<MMXdq>, 0x<MMXdq:pfx>0ff2 | <MMXdq:opc>, <MMXdq:cpu>, Modrm|<MMXdq:attr>|NoSuf, { <MMXdq:reg>|<MMXdq:mem>|Unspecified|BaseIndex, <MMXdq:reg> } |
c8866e3e | 1096 | psll<MMXdq>, 0x<MMXdq:pfx>0f72 | <MMXdq:opc>/6, <MMXdq:cpu>, Modrm|<MMXdq:vvvv>|NoSuf, { Imm8, <MMXdq:reg> } |
24187fb9 | 1097 | psraw<MMXBW>, 0x<MMXBW:pfx>0fe1, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
c8866e3e | 1098 | psraw<MMXBW>, 0x<MMXBW:pfx>0f71/4, <MMXBW:cpu>, Modrm|<MMXBW:vvvv>|NoSuf, { Imm8, <MMXBW:reg> } |
24187fb9 | 1099 | psrad<MMX>, 0x<MMX:pfx>0fe2, <MMX:cpu>, Modrm|<MMX:attr>|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } |
c8866e3e | 1100 | psrad<MMX>, 0x<MMX:pfx>0f72/4, <MMX:cpu>, Modrm|<MMX:vvvv>|NoSuf, { Imm8, <MMX:reg> } |
24187fb9 | 1101 | psrlw<MMXBW>, 0x<MMXBW:pfx>0fd1, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
c8866e3e | 1102 | psrlw<MMXBW>, 0x<MMXBW:pfx>0f71/2, <MMXBW:cpu>, Modrm|<MMXBW:vvvv>|NoSuf, { Imm8, <MMXBW:reg> } |
24187fb9 | 1103 | psrl<MMXdq>, 0x<MMXdq:pfx>0fd2 | <MMXdq:opc>, <MMXdq:cpu>, Modrm|<MMXdq:attr>|NoSuf, { <MMXdq:reg>|<MMXdq:mem>|Unspecified|BaseIndex, <MMXdq:reg> } |
c8866e3e | 1104 | psrl<MMXdq>, 0x<MMXdq:pfx>0f72 | <MMXdq:opc>/2, <MMXdq:cpu>, Modrm|<MMXdq:vvvv>|NoSuf, { Imm8, <MMXdq:reg> } |
24187fb9 JB |
1105 | psub<bw><MMXBW>, 0x<MMXBW:pfx>0ff8 | <bw:opc>, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
1106 | psubd<MMX>, 0x<MMX:pfx>0ffa, <MMX:cpu>, Modrm|<MMX:attr>|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } | |
1107 | psubq<SSE2Q>, 0x660ffb, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1108 | psubq, 0xffb, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 JB |
1109 | psubs<bw><MMXBW>, 0x<MMXBW:pfx>0fe8 | <bw:opc>, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } |
1110 | psubus<bw><MMXBW>, 0x<MMXBW:pfx>0fd8 | <bw:opc>, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1111 | punpckhbw<MMXBW>, 0x<MMXBW:pfx>0f68, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1112 | punpckhwd<MMXBW>, 0x<MMXBW:pfx>0f69, <MMXBW:cpu>, Modrm|<MMXBW:attr>|NoSuf, { <MMXBW:reg>|<MMXBW:mem>|Unspecified|BaseIndex, <MMXBW:reg> } | |
1113 | punpckhdq<MMX>, 0x<MMX:pfx>0f6a, <MMX:cpu>, Modrm|<MMX:attr>|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } | |
1114 | punpcklbw<SSE2BW>, 0x660f60, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1115 | punpcklbw, 0xf60, MMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 | 1116 | punpcklwd<SSE2BW>, 0x660f61, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1117 | punpcklwd, 0xf61, MMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 | 1118 | punpckldq<SSE2D>, 0x660f62, <SSE2D:cpu>, Modrm|<SSE2D:attr>|<SSE2D:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1119 | punpckldq, 0xf62, MMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 | 1120 | pxor<MMX>, 0x<MMX:pfx>0fef, <MMX:cpu>, Modrm|<MMX:attr>|C|NoSuf, { <MMX:reg>|<MMX:mem>|Unspecified|BaseIndex, <MMX:reg> } |
40b8e679 | 1121 | |
458fa392 | 1122 | // SSE instructions. |
40b8e679 | 1123 | |
33b6a20a | 1124 | <sse:cpu:attr:scal:vvvv, + |
f2a3a881 | 1125 | $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:Src1VVVV, + |
4fdeb2a3 | 1126 | $sse:SSE:::> |
24187fb9 | 1127 | <SSE:cpu:attr:scal:vvvv, + |
f2a3a881 | 1128 | $avx:AVX|AVX512VL:Vex128|EVex128|VexW0|Disp8MemShift=4|SSE2AVX:VexLIG|EVexLIG|VexW0|Disp8MemShift=2|SSE2AVX:Src1VVVV, + |
24187fb9 JB |
1129 | $sse:SSE:::> |
1130 | <SSEDQ:cpu:attr, + | |
f2a3a881 CL |
1131 | $avx:AVX:Vex128|VexW0|Src1VVVV|SSE2AVX, + |
1132 | $apx:AVX512DQ&AVX512VL:EVex128|VexW0|Src1VVVV|Disp8MemShift=4|SSE2AVX, + | |
24187fb9 JB |
1133 | $sse:SSE:> |
1134 | <SSERP:recip:rsqrt:cpu:attr, + | |
1135 | $avx:0x0f53:0x0f52:AVX:Vex128|VexW0|SSE2AVX, + | |
1136 | $apx:0x660f384c:0x660f384e:AVX512VL:EVex128|VexW0|Disp8MemShift=4|SSE2AVX, + | |
1137 | $sse:0x0f53:0x0f52:SSE:::> | |
1138 | <SSERS:recip:rsqrt:cpu:attr, + | |
f2a3a881 CL |
1139 | $avx:0xf30f53:0xf30f52:AVX:VexLIG|VexW0|Src1VVVV|SSE2AVX, + |
1140 | $apx:0x660f384d:0x660f384f:AVX512F:EVexLIG|VexW0|Src1VVVV|Disp8MemShift=2|SSE2AVX, + | |
24187fb9 | 1141 | $sse:0xf30f53:0xf30f52:SSE:::> |
390ddd6f | 1142 | <frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:, ord:7:C> |
3677e4c1 | 1143 | |
24187fb9 JB |
1144 | addps<SSE>, 0x0f58, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1145 | addss<SSE>, 0xf30f58, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1146 | andnps<SSEDQ>, 0x0f55, <SSEDQ:cpu>, Modrm|<SSEDQ:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1147 | andps<SSEDQ>, 0x0f54, <SSEDQ:cpu>, Modrm|<SSEDQ:attr>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
68993386 JB |
1148 | cmp<frel>ps<sse>, 0x0fc2/<frel:imm>, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1149 | cmp<frel>ss<sse>, 0xf30fc2/<frel:imm>, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
1150 | cmpps<sse>, 0x0fc2, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1151 | cmpss<sse>, 0xf30fc2, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
24187fb9 | 1152 | comiss<SSE>, 0x0f2f, <SSE:cpu>, Modrm|<SSE:scal>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } |
4fdeb2a3 JB |
1153 | cvtpi2ps, 0xf2a, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } |
1154 | cvtps2pi, 0xf2d, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } | |
a5e91879 | 1155 | cvtsi2ss<sse>, 0xf30f2a, <sse:cpu>&No64, Modrm|<sse:scal>|<sse:vvvv>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
1156 | cvtsi2ss, 0xf32a, x64&(AVX|AVX512F), Modrm|VexLIG|EVexLIG|Space0F|Src1VVVV|IgnoreSize|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } |
1157 | cvtsi2ss, 0xf32a, x64&(AVX|AVX512F), Modrm|VexLIG|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } | |
e20298da CL |
1158 | cvtsi2ss, 0xf30f2a, SSE&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } |
1159 | cvtsi2ss, 0xf30f2a, SSE&x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } | |
24187fb9 | 1160 | cvtss2si, 0xf32d, AVX|AVX512F, Modrm|VexLIG|EVexLIG|Space0F|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
4fdeb2a3 JB |
1161 | cvtss2si, 0xf30f2d, SSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
1162 | cvttps2pi, 0xf2c, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } | |
24187fb9 | 1163 | cvttss2si, 0xf32c, AVX|AVX512F, Modrm|VexLIG|EVexLIG|Space0F|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
4fdeb2a3 | 1164 | cvttss2si, 0xf30f2c, SSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
24187fb9 JB |
1165 | divps<SSE>, 0x0f5e, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1166 | divss<SSE>, 0xf30f5e, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
68993386 | 1167 | ldmxcsr<sse>, 0x0fae/2, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { Dword|Unspecified|BaseIndex } |
4fdeb2a3 | 1168 | maskmovq, 0xff7, SSE|3dnowA, Modrm|NoSuf, { RegMMX, RegMMX } |
24187fb9 JB |
1169 | maxps<SSE>, 0x0f5f, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1170 | maxss<SSE>, 0xf30f5f, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1171 | minps<SSE>, 0x0f5d, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1172 | minss<SSE>, 0xf30f5d, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1173 | movaps<SSE>, 0x0f28, <SSE:cpu>, D|Modrm|<SSE:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1d026d6b | 1174 | movhlps<SSE>, 0x0f12, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM, RegXMM } |
f2a3a881 | 1175 | movhps, 0x16, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|Src1VVVV|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
24187fb9 | 1176 | movhps, 0x17, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } |
4fdeb2a3 | 1177 | movhps, 0xf16, SSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } |
1d026d6b | 1178 | movlhps<SSE>, 0x0f16, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM, RegXMM } |
f2a3a881 | 1179 | movlps, 0x12, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|Src1VVVV|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
24187fb9 | 1180 | movlps, 0x13, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } |
4fdeb2a3 | 1181 | movlps, 0xf12, SSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } |
68993386 | 1182 | movmskps<sse>, 0x0f50, <sse:cpu>, Modrm|<sse:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } |
24187fb9 | 1183 | movntps<SSE>, 0x0f2b, <SSE:cpu>, Modrm|<SSE:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } |
4fdeb2a3 | 1184 | movntq, 0xfe7, SSE|3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } |
24187fb9 JB |
1185 | movntdq<SSE2D>, 0x660fe7, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } |
1186 | movss, 0xf310, AVX|AVX512F, D|Modrm|VexLIG|EVexLIG|Space0F|VexW0|Disp8MemShift=2|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } | |
f2a3a881 | 1187 | movss, 0xf310, AVX|AVX512F, D|Modrm|VexLIG|EVexLIG|Space0F|Src1VVVV|VexW0|NoSuf|SSE2AVX, { RegXMM, RegXMM } |
4fdeb2a3 | 1188 | movss, 0xf30f10, SSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } |
24187fb9 JB |
1189 | movups<SSE>, 0x0f10, <SSE:cpu>, D|Modrm|<SSE:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1190 | mulps<SSE>, 0x0f59, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1191 | mulss<SSE>, 0xf30f59, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1192 | orps<SSEDQ>, 0x0f56, <SSEDQ:cpu>, Modrm|<SSEDQ:attr>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1193 | pavg<bw>, 0xfe0 | (3 * <bw:opc>), SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 JB |
1194 | pavg<bw><SSE2BW>, 0x660fe0 | (3 * <bw:opc>), <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1195 | pextrw<SSE2D>, 0x660fc5, <SSE2D:cpu>, Load|Modrm|<SSE2D:attr>|No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } | |
4fdeb2a3 | 1196 | pextrw, 0xfc5, SSE|3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } |
24187fb9 JB |
1197 | pinsrw<SSE2D>, 0x660fc4, <SSE2D:cpu>, Modrm|<SSE2D:attr>|<SSE2D:vvvv>|No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } |
1198 | pinsrw<SSE2D>, 0x660fc4, <SSE2D:cpu>, Modrm|<SSE2D:attr>|<SSE2D:vvvv>|Disp8MemShift|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1199 | pinsrw, 0xfc4, SSE|3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } |
1200 | pinsrw, 0xfc4, SSE|3dnowA, Modrm|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } | |
24187fb9 | 1201 | pmaxsw<SSE2BW>, 0x660fee, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1202 | pmaxsw, 0xfee, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 | 1203 | pmaxub<SSE2BW>, 0x660fde, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1204 | pmaxub, 0xfde, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 | 1205 | pminsw<SSE2BW>, 0x660fea, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1206 | pminsw, 0xfea, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 | 1207 | pminub<SSE2BW>, 0x660fda, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1208 | pminub, 0xfda, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
68993386 | 1209 | pmovmskb<sse2>, 0x660fd7, <sse2:cpu>, Modrm|<sse2:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } |
4fdeb2a3 | 1210 | pmovmskb, 0xfd7, SSE|3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegMMX, Reg32|Reg64 } |
24187fb9 | 1211 | pmulhuw<SSE2BW>, 0x660fe4, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 JB |
1212 | pmulhuw, 0xfe4, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
1213 | prefetchnta, 0xf18/0, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1214 | prefetcht0, 0xf18/1, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1215 | prefetcht1, 0xf18/2, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1216 | prefetcht2, 0xf18/3, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1217 | psadbw, 0xff6, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
24187fb9 | 1218 | psadbw<SSE2BW>, 0x660ff6, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
c34d1cc9 | 1219 | pshufw, 0xf70, SSE|3dnowA, Modrm|NoSuf, { Imm8|Imm8S, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 JB |
1220 | rcpps<SSERP>, <SSERP:recip>, <SSERP:cpu>, Modrm|<SSERP:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1221 | rcpss<SSERS>, <SSERS:recip>, <SSERS:cpu>, Modrm|<SSERS:attr>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1222 | rsqrtps<SSERP>, <SSERP:rsqrt>, <SSERP:cpu>, Modrm|<SSERP:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1223 | rsqrtss<SSERS>, <SSERS:rsqrt>, <SSERS:cpu>, Modrm|<SSERS:attr>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
4fdeb2a3 | 1224 | sfence, 0xfaef8, SSE|3dnowA, NoSuf, {} |
24187fb9 JB |
1225 | shufps<SSE>, 0x0fc6, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
1226 | sqrtps<SSE>, 0x0f51, <SSE:cpu>, Modrm|<SSE:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1227 | sqrtss<SSE>, 0xf30f51, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
68993386 | 1228 | stmxcsr<sse>, 0x0fae/3, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { Dword|Unspecified|BaseIndex } |
24187fb9 JB |
1229 | subps<SSE>, 0x0f5c, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1230 | subss<SSE>, 0xf30f5c, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1231 | ucomiss<SSE>, 0x0f2e, <SSE:cpu>, Modrm|<SSE:scal>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1232 | unpckhps<SSE>, 0x0f15, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1233 | unpcklps<SSE>, 0x0f14, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1234 | xorps<SSEDQ>, 0x0f57, <SSEDQ:cpu>, Modrm|<SSEDQ:attr>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
40b8e679 | 1235 | |
458fa392 | 1236 | // SSE2 instructions. |
40b8e679 | 1237 | |
24187fb9 | 1238 | <SSE2DQ:cpu:attr, + |
f2a3a881 CL |
1239 | $avx:AVX:Vex128|VexW0|Src1VVVV|SSE2AVX, + |
1240 | $apx:AVX512DQ&AVX512VL:EVex128|VexW1|Src1VVVV|Disp8MemShift=4|SSE2AVX, + | |
24187fb9 JB |
1241 | $sse:SSE2:> |
1242 | ||
1243 | addpd<SSE2Q>, 0x660f58, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1244 | addsd<SSE2Q>, 0xf20f58, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1245 | andnpd<SSE2DQ>, 0x660f55, <SSE2DQ:cpu>, Modrm|<SSE2DQ:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1246 | andpd<SSE2DQ>, 0x660f54, <SSE2DQ:cpu>, Modrm|<SSE2DQ:attr>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
68993386 JB |
1247 | cmp<frel>pd<sse2>, 0x660fc2/<frel:imm>, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1248 | cmp<frel>sd<sse2>, 0xf20fc2/<frel:imm>, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
1249 | cmppd<sse2>, 0x660fc2, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1250 | cmpsd<sse2>, 0xf20fc2, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
24187fb9 | 1251 | comisd<SSE2Q>, 0x660f2f, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
4fdeb2a3 | 1252 | cvtpi2pd, 0x660f2a, SSE2, Modrm|NoSuf, { RegMMX, RegXMM } |
24187fb9 | 1253 | cvtpi2pd, 0xf3e6, AVX|AVX512VL, Modrm|Vex128|EVex128|Space0F|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1254 | cvtpi2pd, 0x660f2a, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } |
a5e91879 | 1255 | cvtsi2sd<sse2>, 0xf20f2a, <sse2:cpu>&No64, Modrm|IgnoreSize|<sse2:scal>|<sse2:vvvv>|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
1256 | cvtsi2sd, 0xf22a, x64&(AVX|AVX512F), Modrm|VexLIG|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } |
1257 | cvtsi2sd, 0xf22a, x64&(AVX|AVX512F), Modrm|VexLIG|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } | |
e20298da CL |
1258 | cvtsi2sd, 0xf20f2a, SSE2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } |
1259 | cvtsi2sd, 0xf20f2a, SSE2&x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } | |
24187fb9 JB |
1260 | divpd<SSE2Q>, 0x660f5e, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1261 | divsd<SSE2Q>, 0xf20f5e, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1262 | maxpd<SSE2Q>, 0x660f5f, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1263 | maxsd<SSE2Q>, 0xf20f5f, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1264 | minpd<SSE2Q>, 0x660f5d, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1265 | minsd<SSE2Q>, 0xf20f5d, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1266 | movapd<SSE2Q>, 0x660f28, <SSE2Q:cpu>, D|Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
f2a3a881 CL |
1267 | movhpd, 0x6616, AVX, Modrm|Vex|Space0F|Src1VVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
1268 | movhpd, 0x6616, AVX512F, Modrm|EVex128|Space0F|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1269 | movhpd, 0x6617, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } |
24187fb9 | 1270 | movhpd, 0x6617, AVX512F, Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } |
4fdeb2a3 | 1271 | movhpd, 0x660f16, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
1272 | movlpd, 0x6612, AVX, Modrm|Vex|Space0F|Src1VVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
1273 | movlpd, 0x6612, AVX512F, Modrm|EVex128|Space0F|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1274 | movlpd, 0x6613, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } |
24187fb9 | 1275 | movlpd, 0x6613, AVX512F, Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } |
4fdeb2a3 | 1276 | movlpd, 0x660f12, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } |
68993386 | 1277 | movmskpd<sse2>, 0x660f50, <sse2:cpu>, Modrm|<sse2:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } |
24187fb9 | 1278 | movntpd<SSE2Q>, 0x660f2b, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } |
4fdeb2a3 | 1279 | movsd, 0xf210, AVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
24187fb9 | 1280 | movsd, 0xf210, AVX512F, D|Modrm|EVexLIG|Space0F|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
1281 | movsd, 0xf210, AVX, D|Modrm|VexLIG|Space0F|Src1VVVV|VexW0|NoSuf|SSE2AVX, { RegXMM, RegXMM } |
1282 | movsd, 0xf210, AVX512F, D|Modrm|EVexLIG|Space0F|Src1VVVV|VexW1|NoSuf|SSE2AVX, { RegXMM, RegXMM } | |
4fdeb2a3 | 1283 | movsd, 0xf20f10, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
24187fb9 JB |
1284 | movupd<SSE2Q>, 0x660f10, <SSE2Q:cpu>, D|Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1285 | mulpd<SSE2Q>, 0x660f59, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1286 | mulsd<SSE2Q>, 0xf20f59, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1287 | orpd<SSE2DQ>, 0x660f56, <SSE2DQ:cpu>, Modrm|<SSE2DQ:attr>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1288 | shufpd<SSE2Q>, 0x660fc6, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1289 | sqrtpd<SSE2Q>, 0x660f51, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1290 | sqrtsd<SSE2Q>, 0xf20f51, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1291 | subpd<SSE2Q>, 0x660f5c, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1292 | subsd<SSE2Q>, 0xf20f5c, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1293 | ucomisd<SSE2Q>, 0x660f2e, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1294 | unpckhpd<SSE2Q>, 0x660f15, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1295 | unpcklpd<SSE2Q>, 0x660f14, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1296 | xorpd<SSE2DQ>, 0x660f57, <SSE2DQ:cpu>, Modrm|<SSE2DQ:attr>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1297 | cvtdq2pd<SSE2D>, 0xf30fe6, <SSE2D:cpu>, Modrm|<SSE2D:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1298 | cvtpd2dq<SSE2Q>, 0xf20fe6, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1299 | cvtdq2ps<SSE2D>, 0x0f5b, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1300 | cvtpd2pi, 0x660f2d, SSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } |
24187fb9 JB |
1301 | cvtpd2ps<SSE2Q>, 0x660f5a, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1302 | cvtps2pd<SSE2D>, 0x0f5a, <SSE2D:cpu>, Modrm|<SSE2D:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1303 | cvtps2dq<SSE2D>, 0x660f5b, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1304 | cvtsd2si, 0xf22d, AVX|AVX512F, Modrm|VexLIG|EVexLIG|Space0F|Disp8MemShift=3|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
4fdeb2a3 | 1305 | cvtsd2si, 0xf20f2d, SSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
24187fb9 JB |
1306 | cvtsd2ss<SSE2Q>, 0xf20f5a, <SSE2Q:cpu>, Modrm|<SSE2Q:scal>|<SSE2Q:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1307 | cvtss2sd<SSE2D>, 0xf30f5a, <SSE2D:cpu>, Modrm|<SSE2D:scal>|<SSE2D:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
4fdeb2a3 | 1308 | cvttpd2pi, 0x660f2c, SSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } |
24187fb9 | 1309 | cvttsd2si, 0xf22c, AVX|AVX512F, Modrm|VexLIG|EVexLIG|Space0F|Disp8MemShift=3|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
4fdeb2a3 | 1310 | cvttsd2si, 0xf20f2c, SSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
24187fb9 JB |
1311 | cvttpd2dq<SSE2Q>, 0x660fe6, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1312 | cvttps2dq<SSE2D>, 0xf30f5b, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
68993386 | 1313 | maskmovdqu<sse2>, 0x660ff7, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, RegXMM } |
24187fb9 JB |
1314 | movdqa<SSE2D>, 0x660f6f, <SSE2D:cpu>, D|Modrm|<SSE2D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1315 | movdqu<SSE2D>, 0xf30f6f, <SSE2D:cpu>, D|Modrm|<SSE2D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1316 | movdq2q, 0xf20fd6, SSE2, Modrm|NoSuf, { RegXMM, RegMMX } |
1317 | movq2dq, 0xf30fd6, SSE2, Modrm|NoSuf, { RegMMX, RegXMM } | |
24187fb9 | 1318 | pmuludq<SSE2Q>, 0x660ff4, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1319 | pmuludq, 0xff4, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } |
24187fb9 JB |
1320 | pshufd<SSE2D>, 0x660f70, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
1321 | pshufhw<SSE2BW>, 0xf30f70, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1322 | pshuflw<SSE2BW>, 0xf20f70, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1d026d6b JB |
1323 | pslldq<SSE2BW>, 0x660f73/7, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|NoSuf, { Imm8, RegXMM } |
1324 | psrldq<SSE2BW>, 0x660f73/3, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|NoSuf, { Imm8, RegXMM } | |
24187fb9 JB |
1325 | punpckhqdq<SSE2Q>, 0x660f6d, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1326 | punpcklqdq<SSE2Q>, 0x660f6c, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
40b8e679 | 1327 | |
390ddd6f JB |
1328 | <frel> |
1329 | ||
458fa392 | 1330 | // SSE3 instructions. |
40b8e679 | 1331 | |
f2a3a881 | 1332 | <sse3:cpu:attr, $avx:AVX:Vex128|VexW0|Src1VVVV|SSE2AVX, $sse:SSE3:> |
24187fb9 JB |
1333 | <SSE3D:cpu:attr, + |
1334 | $avx:AVX|AVX512VL:Vex128|EVex128|VexW0|Disp8MemShift=4|SSE2AVX, + | |
1335 | $sse:SSE3:> | |
1336 | <SSE3Q:cpu:attr, + | |
f2a3a881 | 1337 | $avx:AVX:Vex128|VexW0|SSE2AVX:Src1VVVV, + |
24187fb9 JB |
1338 | $apx:AVX512VL:EVex128|VexW1|Disp8MemShift=3|SSE2AVX, + |
1339 | $sse:SSE3:> | |
5cdaf100 | 1340 | |
e6d60e76 JB |
1341 | addsubpd<sse3>, 0x660fd0, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1342 | addsubps<sse3>, 0xf20fd0, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1343 | haddpd<sse3>, 0x660f7c, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1344 | haddps<sse3>, 0xf20f7c, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1345 | hsubpd<sse3>, 0x660f7d, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1346 | hsubps<sse3>, 0xf20f7d, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
24187fb9 JB |
1347 | lddqu, 0xf20ff0, AVX, Modrm|Vex128|VexW0|SSE2AVX|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } |
1348 | // For use with eGPR-s in the memory operand, utilize VMOVDQU32. | |
1349 | lddqu, 0xf30f6f, AVX512VL, Modrm|EVex128|VexW0|Disp8MemShift=4|SSE2AVX|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } | |
1350 | lddqu, 0xf20ff0, SSE3, Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } | |
1351 | movddup<SSE3Q>, 0xf20f12, <SSE3Q:cpu>, Modrm|<SSE3Q:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1352 | movshdup<SSE3D>, 0xf30f16, <SSE3D:cpu>, Modrm|<SSE3D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1353 | movsldup<SSE3D>, 0xf30f12, <SSE3D:cpu>, Modrm|<SSE3D:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
bbe1eca6 JB |
1354 | |
1355 | // FPU instructions also covered by SSE3 CPUID flag. | |
1356 | ||
4fdeb2a3 JB |
1357 | fisttp, 0xdf/1, FISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } |
1358 | fisttp, 0xdd/1, FISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } | |
1359 | fisttpll, 0xdd/1, FISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } | |
bbe1eca6 JB |
1360 | |
1361 | // CMPXCHG16B instruction. | |
1362 | ||
3e624fa4 | 1363 | cmpxchg16b, 0xfc7/1, CX16, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } |
bbe1eca6 JB |
1364 | |
1365 | // MONITOR instructions. | |
1366 | ||
cafa5ef7 | 1367 | monitor, 0xf01c8, MONITOR, NoSuf, {} |
a79eaed6 | 1368 | // monitor is very special. CX and DX are always 32 bits. The |
40b8e679 L |
1369 | // address size override prefix can be used to overrride the AX size in |
1370 | // all modes. | |
cafa5ef7 | 1371 | monitor, 0xf01c8, MONITOR, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } |
a79eaed6 | 1372 | // The 64-bit form exists only for compatibility with older gas. |
a5e91879 | 1373 | monitor, 0xf01c8, MONITOR&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } |
cafa5ef7 | 1374 | mwait, 0xf01c9, MONITOR, NoSuf, {} |
a79eaed6 | 1375 | // mwait is very special. AX and CX are always 32 bits. |
a79eaed6 | 1376 | // The 64-bit form exists only for compatibility with older gas. |
cafa5ef7 | 1377 | mwait, 0xf01c9, MONITOR, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword } |
40b8e679 L |
1378 | |
1379 | // VMX instructions. | |
47dd174c | 1380 | |
4fdeb2a3 JB |
1381 | vmcall, 0xf01c1, VMX, NoSuf, {} |
1382 | vmclear, 0x660fc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
1383 | vmlaunch, 0xf01c2, VMX, NoSuf, {} | |
1384 | vmresume, 0xf01c3, VMX, NoSuf, {} | |
1385 | vmptrld, 0xfc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
1386 | vmptrst, 0xfc7/7, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
a5e91879 | 1387 | vmread, 0xf78, VMX&No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } |
e20298da | 1388 | vmread, 0xf78, VMX&x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Unspecified|BaseIndex } |
a5e91879 | 1389 | vmwrite, 0xf79, VMX&No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } |
e20298da | 1390 | vmwrite, 0xf79, VMX&x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Unspecified|BaseIndex, Reg64 } |
4fdeb2a3 JB |
1391 | vmxoff, 0xf01c4, VMX, NoSuf, {} |
1392 | vmxon, 0xf30fc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
40b8e679 | 1393 | |
8729a6f6 L |
1394 | // VMFUNC instruction |
1395 | ||
4fdeb2a3 | 1396 | vmfunc, 0xf01d4, VMFUNC, NoSuf, {} |
8729a6f6 | 1397 | |
47dd174c L |
1398 | // SMX instructions. |
1399 | ||
4fdeb2a3 | 1400 | getsec, 0xf37, SMX, NoSuf, {} |
47dd174c | 1401 | |
f1f8f695 L |
1402 | // EPT instructions. |
1403 | ||
a5e91879 JB |
1404 | invept, 0x660f3880, EPT&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } |
1405 | invept, 0x660f3880, EPT&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } | |
2f630f60 | 1406 | invept, 0xf3f0, EPT&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } |
a5e91879 JB |
1407 | invvpid, 0x660f3881, EPT&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } |
1408 | invvpid, 0x660f3881, EPT&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } | |
2f630f60 | 1409 | invvpid, 0xf3f1, EPT&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } |
f1f8f695 | 1410 | |
6c30d220 L |
1411 | // INVPCID instruction |
1412 | ||
a5e91879 JB |
1413 | invpcid, 0x660f3882, INVPCID&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } |
1414 | invpcid, 0x660f3882, INVPCID&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } | |
2f630f60 | 1415 | invpcid, 0xf3f2, INVPCID&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } |
6c30d220 | 1416 | |
458fa392 | 1417 | // SSSE3 instructions. |
40b8e679 | 1418 | |
e6d60e76 | 1419 | <ssse3:cpu:pfx:attr:reg:mem, + |
f2a3a881 | 1420 | $avx:AVX:66:Vex128|VexW0|Src1VVVV|SSE2AVX:RegXMM:Xmmword, + |
e6d60e76 JB |
1421 | $sse:SSSE3:66::RegXMM:Xmmword, + |
1422 | $mmx:SSSE3:::RegMMX:Qword> | |
24187fb9 | 1423 | <SSSE3BW:cpu:pfx:attr:vvvv:reg:mem, + |
f2a3a881 CL |
1424 | $avx:AVX:66:Vex128|VexW0|SSE2AVX:Src1VVVV:RegXMM:Xmmword, + |
1425 | $apx:AVX512BW&AVX512VL:66:EVex128|VexW0|Disp8MemShift=4|SSE2AVX:Src1VVVV:RegXMM:Xmmword, + | |
24187fb9 JB |
1426 | $sse:SSSE3:66:::RegXMM:Xmmword, + |
1427 | $mmx:SSSE3::::RegMMX:Qword> | |
1428 | <SSSE3D:cpu:pfx:attr:reg:mem, + | |
1429 | $avx:AVX|AVX512VL:66:Vex128|EVex128|VexW0|Disp8MemShift=4|SSE2AVX:RegXMM:Xmmword, + | |
1430 | $sse:SSSE3:66::RegXMM:Xmmword, + | |
1431 | $mmx:SSSE3:::RegMMX:Qword> | |
5cdaf100 | 1432 | |
e6d60e76 JB |
1433 | phaddw<ssse3>, 0x<ssse3:pfx>0f3801, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } |
1434 | phaddd<ssse3>, 0x<ssse3:pfx>0f3802, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1435 | phaddsw<ssse3>, 0x<ssse3:pfx>0f3803, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1436 | phsubw<ssse3>, 0x<ssse3:pfx>0f3805, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1437 | phsubd<ssse3>, 0x<ssse3:pfx>0f3806, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1438 | phsubsw<ssse3>, 0x<ssse3:pfx>0f3807, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
24187fb9 JB |
1439 | pmaddubsw<SSSE3BW>, 0x<SSSE3BW:pfx>0f3804, <SSSE3BW:cpu>, Modrm|<SSSE3BW:attr>|<SSSE3BW:vvvv>|NoSuf, { <SSSE3BW:reg>|<SSSE3BW:mem>|Unspecified|BaseIndex, <SSSE3BW:reg> } |
1440 | pmulhrsw<SSSE3BW>, 0x<SSSE3BW:pfx>0f380b, <SSSE3BW:cpu>, Modrm|<SSSE3BW:attr>|<SSSE3BW:vvvv>|NoSuf, { <SSSE3BW:reg>|<SSSE3BW:mem>|Unspecified|BaseIndex, <SSSE3BW:reg> } | |
1441 | pshufb<SSSE3BW>, 0x<SSSE3BW:pfx>0f3800, <SSSE3BW:cpu>, Modrm|<SSSE3BW:attr>|<SSSE3BW:vvvv>|NoSuf, { <SSSE3BW:reg>|<SSSE3BW:mem>|Unspecified|BaseIndex, <SSSE3BW:reg> } | |
e6d60e76 JB |
1442 | psign<bw><ssse3>, 0x<ssse3:pfx>0f3808 | <bw:opc>, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } |
1443 | psignd<ssse3>, 0x<ssse3:pfx>0f380a, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
24187fb9 JB |
1444 | palignr<SSSE3BW>, 0x<SSSE3BW:pfx>0f3a0f, <SSSE3BW:cpu>, Modrm|<SSSE3BW:attr>|<SSSE3BW:vvvv>|NoSuf, { Imm8, <SSSE3BW:reg>|<SSSE3BW:mem>|Unspecified|BaseIndex, <SSSE3BW:reg> } |
1445 | pabs<bw><SSSE3BW>, 0x<SSSE3BW:pfx>0f381c | <bw:opc>, <SSSE3BW:cpu>, Modrm|<SSSE3BW:attr>|NoSuf, { <SSSE3BW:reg>|<SSSE3BW:mem>|Unspecified|BaseIndex, <SSSE3BW:reg> } | |
1446 | pabsd<SSSE3D>, 0x<SSSE3D:pfx>0f381e, <SSSE3D:cpu>, Modrm|<SSSE3D:attr>|NoSuf, { <SSSE3D:reg>|<SSSE3D:mem>|Unspecified|BaseIndex, <SSSE3D:reg> } | |
40b8e679 | 1447 | |
458fa392 | 1448 | // SSE4.1 instructions. |
40b8e679 | 1449 | |
f2a3a881 | 1450 | <sse41:cpu:attr:scal:vvvv, $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:Src1VVVV, $sse:SSE4_1:::> |
24187fb9 | 1451 | <SSE41BW:cpu:attr:vvvv, + |
f2a3a881 CL |
1452 | $avx:AVX:Vex128|VexW0|SSE2AVX:Src1VVVV, + |
1453 | $apx:AVX512BW&AVX512VL:EVex128|VexW0|Disp8MemShift=4|SSE2AVX:Src1VVVV, + | |
24187fb9 JB |
1454 | $sse:SSE4_1::> |
1455 | <SSE41DQ:cpu:attr:vvvv, + | |
f2a3a881 CL |
1456 | $avx:AVX:Vex128|VexW0|SSE2AVX:Src1VVVV, + |
1457 | $apx:AVX512DQ&AVX512VL:EVex128|VexW0|Disp8MemShift=4|SSE2AVX:Src1VVVV, + | |
24187fb9 JB |
1458 | $sse:SSE4_1::> |
1459 | <SSE41D:cpu:attr:scal:vvvv, + | |
f2a3a881 | 1460 | $avx:AVX|AVX512VL:Vex128|EVex128|VexW0|Disp8MemShift=4|SSE2AVX:VexLIG|EVexLIG|VexW0|Disp8MemShift=2|SSE2AVX:Src1VVVV, + |
24187fb9 JB |
1461 | $sse:SSE4_1:::> |
1462 | <SSE41Q:cpu:attr:scal:vvvv, + | |
f2a3a881 CL |
1463 | $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:Src1VVVV, + |
1464 | $apx:AVX512VL:EVex128|VexW1|Disp8MemShift=4|SSE2AVX:EVexLIG|VexW1|Disp8MemShift=3|SSE2AVX:Src1VVVV, + | |
24187fb9 JB |
1465 | $sse:SSE4_1:::> |
1466 | ||
1cb0ab18 | 1467 | <sd:ppfx:spfx:opc:vexw:elem, s::f3:0:VexW0:Dword, d:66:f2:1:VexW1:Qword> |
73d214b2 | 1468 | |
c34d1cc9 | 1469 | blendp<sd><sse41>, 0x660f3a0c | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
1470 | blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex128|Space0F3A|Src1VVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } |
1471 | blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex128|Space0F3A|Src1VVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1472 | blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } |
1473 | blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
c34d1cc9 | 1474 | dpp<sd><sse41>, 0x660f3a40 | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
24187fb9 JB |
1475 | extractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexW0|Disp8MemShift=2|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } |
1476 | extractps, 0x6617, x64&(AVX|AVX512F), RegMem|Vex128|EVex128|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } | |
e20298da | 1477 | extractps, 0x660f3a17, SSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } |
a5e91879 | 1478 | extractps, 0x660f3a17, SSE4_1&x64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } |
24187fb9 JB |
1479 | insertps<SSE41D>, 0x660f3a21, <SSE41D:cpu>, Modrm|<SSE41D:attr>|<SSE41D:vvvv>|Disp8MemShift|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1480 | movntdqa<SSE41D>, 0x660f382a, <SSE41D:cpu>, Modrm|<SSE41D:attr>|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } | |
c34d1cc9 | 1481 | mpsadbw<sse41>, 0x660f3a42, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
24187fb9 | 1482 | packusdw<SSE41BW>, 0x660f382b, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
1483 | pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|Src1VVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } |
1484 | pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|Src1VVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1485 | pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } |
1486 | pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
c34d1cc9 | 1487 | pblendw<sse41>, 0x660f3a0e, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
b5c37946 | 1488 | pcmpeqq<sse41>, 0x660f3829, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf|Optimize, { RegXMM|Unspecified|BaseIndex, RegXMM } |
24187fb9 JB |
1489 | pextr<bw><SSE41BW>, 0x660f3a14 | <bw:opc>, <SSE41BW:cpu>, RegMem|<SSE41BW:attr>|NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } |
1490 | pextr<bw><SSE41BW>, 0x660f3a14 | <bw:opc>, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|Disp8MemShift|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } | |
1491 | pextrd<SSE41DQ>, 0x660f3a16, <SSE41DQ:cpu>, Modrm|<SSE41DQ:attr>|Disp8MemShift|NoSuf|IgnoreSize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } | |
a5e91879 | 1492 | pextrq, 0x6616, AVX&x64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } |
24187fb9 | 1493 | pextrq, 0x6616, AVX512DQ&AVX512VL&x64, Modrm|EVex128|Space0F3A|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } |
a5e91879 | 1494 | pextrq, 0x660f3a16, SSE4_1&x64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } |
68993386 | 1495 | phminposuw<sse41>, 0x660f3841, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
24187fb9 JB |
1496 | pinsrb<SSE41BW>, 0x660f3a20, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|NoSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } |
1497 | pinsrb<SSE41BW>, 0x660f3a20, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|Disp8MemShift|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM } | |
1498 | pinsrd<SSE41DQ>, 0x660f3a22, <SSE41DQ:cpu>, Modrm|<SSE41DQ:attr>|<SSE41DQ:vvvv>|Disp8MemShift|NoSuf|IgnoreSize, { Imm8, Reg32|Unspecified|BaseIndex, RegXMM } | |
f2a3a881 CL |
1499 | pinsrq, 0x6622, AVX&x64, Modrm|Vex|Space0F3A|Src1VVVV|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } |
1500 | pinsrq, 0x6622, AVX512DQ&AVX512VL&AVX&x64, Modrm|EVex128|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } | |
a5e91879 | 1501 | pinsrq, 0x660f3a22, SSE4_1&x64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } |
24187fb9 JB |
1502 | pmaxsb<SSE41BW>, 0x660f383c, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1503 | pmaxsd<SSE41D>, 0x660f383d, <SSE41D:cpu>, Modrm|<SSE41D:attr>|<SSE41D:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1504 | pmaxud<SSE41D>, 0x660f383f, <SSE41D:cpu>, Modrm|<SSE41D:attr>|<SSE41D:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1505 | pmaxuw<SSE41BW>, 0x660f383e, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1506 | pminsb<SSE41BW>, 0x660f3838, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1507 | pminsd<SSE41D>, 0x660f3839, <SSE41D:cpu>, Modrm|<SSE41D:attr>|<SSE41D:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1508 | pminud<SSE41D>, 0x660f383b, <SSE41D:cpu>, Modrm|<SSE41D:attr>|<SSE41D:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1509 | pminuw<SSE41BW>, 0x660f383a, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|<SSE41BW:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1510 | pmovsxbw<SSE41BW>, 0x660f3820, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1511 | pmovsxbd<SSE41D>, 0x660f3821, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1512 | pmovsxbq<SSE41D>, 0x660f3822, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1513 | pmovsxwd<SSE41D>, 0x660f3823, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1514 | pmovsxwq<SSE41D>, 0x660f3824, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1515 | pmovsxdq<SSE41D>, 0x660f3825, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1516 | pmovzxbw<SSE41BW>, 0x660f3830, <SSE41BW:cpu>, Modrm|<SSE41BW:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1517 | pmovzxbd<SSE41D>, 0x660f3831, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1518 | pmovzxbq<SSE41D>, 0x660f3832, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1519 | pmovzxwd<SSE41D>, 0x660f3833, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1520 | pmovzxwq<SSE41D>, 0x660f3834, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1521 | pmovzxdq<SSE41D>, 0x660f3835, <SSE41D:cpu>, Modrm|<SSE41D:attr>|Disp8MemShift|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1522 | pmuldq<SSE41Q>, 0x660f3828, <SSE41Q:cpu>, Modrm|<SSE41Q:attr>|<SSE41Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1523 | pmulld<SSE41D>, 0x660f3840, <SSE41D:cpu>, Modrm|<SSE41D:attr>|<SSE41D:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
68993386 | 1524 | ptest<sse41>, 0x660f3817, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
24187fb9 JB |
1525 | roundpd<SSE41Q>, 0x660f3a09, <SSE41Q:cpu>, Modrm|<SSE41Q:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1526 | roundps<SSE41D>, 0x660f3a08, <SSE41D:cpu>, Modrm|<SSE41D:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1527 | roundsd<SSE41Q>, 0x660f3a0b, <SSE41Q:cpu>, Modrm|<SSE41Q:scal>|<SSE41Q:vvvv>|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1528 | roundss<SSE41D>, 0x660f3a0a, <SSE41D:cpu>, Modrm|<SSE41D:scal>|<SSE41D:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
40b8e679 | 1529 | |
458fa392 | 1530 | // SSE4.2 instructions. |
40b8e679 | 1531 | |
f2a3a881 | 1532 | <sse42:cpu:attr:vvvv, $avx:AVX:Vex128|VexW0|SSE2AVX:Src1VVVV, $sse:SSE4_2::> |
5cdaf100 | 1533 | |
b5c37946 | 1534 | pcmpgtq<sse42>, 0x660f3837, <sse42:cpu>, Modrm|<sse42:attr>|<sse42:vvvv>|NoSuf|Optimize, { RegXMM|Unspecified|BaseIndex, RegXMM } |
a5e91879 | 1535 | pcmpestri<sse42>, 0x660f3a61, <sse42:cpu>&No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
73f55087 JB |
1536 | pcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1537 | pcmpestri, 0x660f3a61, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
a5e91879 | 1538 | pcmpestrm<sse42>, 0x660f3a60, <sse42:cpu>&No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
73f55087 JB |
1539 | pcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1540 | pcmpestrm, 0x660f3a60, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
68993386 JB |
1541 | pcmpistri<sse42>, 0x660f3a63, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1542 | pcmpistrm<sse42>, 0x660f3a62, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 | 1543 | crc32, 0xf20f38f0, SSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } |
a5e91879 | 1544 | crc32, 0xf20f38f0, SSE4_2&x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } |
6177c84d CL |
1545 | crc32, 0xf0, APX_F, W|Modrm|No_sSuf|No_qSuf|EVexMap4, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } |
1546 | crc32, 0xf0, APX_F, W|Modrm|No_wSuf|No_lSuf|No_sSuf|EVexMap4, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } | |
40b8e679 | 1547 | |
475a2301 L |
1548 | // xsave/xrstor New Instructions. |
1549 | ||
80d61d8d CL |
1550 | xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex } |
1551 | xsave64, 0xfae/4, Xsave&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } | |
1552 | xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex } | |
1553 | xrstor64, 0xfae/5, Xsave&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } | |
4fdeb2a3 JB |
1554 | xgetbv, 0xf01d0, Xsave, NoSuf, {} |
1555 | xsetbv, 0xf01d1, Xsave, NoSuf, {} | |
475a2301 | 1556 | |
29c048b6 | 1557 | // xsaveopt |
80d61d8d CL |
1558 | |
1559 | xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex } | |
1560 | xsaveopt64, 0xfae/6, Xsaveopt&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } | |
c7b8aa3a | 1561 | |
c0f3af97 L |
1562 | // AES instructions. |
1563 | ||
e6d60e76 | 1564 | <aes:cpu:attr, $avx:AVX&:Vex128|VexW0|SSE2AVX, $sse:::> |
24187fb9 | 1565 | <AES:cpu:attr, + |
f2a3a881 | 1566 | $avx:&(AVX|AVX512VL):Vex128|EVex128|VexW0|Src1VVVV|Disp8MemShift=4|SSE2AVX, + |
24187fb9 JB |
1567 | $sse::> |
1568 | ||
1569 | aesdec<AES>, 0x660f38de, AES<AES:cpu>, Modrm|<AES:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1570 | aesdeclast<AES>, 0x660f38df, AES<AES:cpu>, Modrm|<AES:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1571 | aesenc<AES>, 0x660f38dc, AES<AES:cpu>, Modrm|<AES:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1572 | aesenclast<AES>, 0x660f38dd, AES<AES:cpu>, Modrm|<AES:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1573 | aesimc<aes>, 0x660f38db, <aes:cpu>AES, Modrm|<aes:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1574 | aeskeygenassist<aes>, 0x660f3adf, <aes:cpu>AES, Modrm|<aes:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
c0f3af97 | 1575 | |
d54678eb | 1576 | // PCLMULQDQ |
c0f3af97 | 1577 | |
24187fb9 | 1578 | <pclmul:cpu:attr, + |
f2a3a881 | 1579 | $avx:&(AVX|AVX512VL):Vex128|EVex128|VexW0|Src1VVVV|Disp8MemShift=4|SSE2AVX, + |
24187fb9 | 1580 | $sse::> |
5cdaf100 | 1581 | |
24187fb9 JB |
1582 | pclmulqdq<pclmul>, 0x660f3a44, PCLMULQDQ<pclmul:cpu>, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
1583 | pclmullqlqdq<pclmul>, 0x660f3a44/0x00, PCLMULQDQ<pclmul:cpu>, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1584 | pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, PCLMULQDQ<pclmul:cpu>, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1585 | pclmullqhqdq<pclmul>, 0x660f3a44/0x10, PCLMULQDQ<pclmul:cpu>, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1586 | pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, PCLMULQDQ<pclmul:cpu>, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
c0f3af97 | 1587 | |
48521003 IT |
1588 | // GFNI |
1589 | ||
24187fb9 | 1590 | <gfni:cpu:attr:vexw0:vexw1, + |
f2a3a881 | 1591 | $avx:&(AVX|AVX512VL):Vex128|EVex128|Src1VVVV|Disp8MemShift=4|SSE2AVX:VexW0:VexW1, + |
24187fb9 | 1592 | $sse::::> |
5cdaf100 | 1593 | |
24187fb9 JB |
1594 | gf2p8affineqb<gfni>, 0x660f3ace, GFNI<gfni:cpu>, Modrm|<gfni:attr>|<gfni:vexw1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1595 | gf2p8affineinvqb<gfni>, 0x660f3acf, GFNI<gfni:cpu>, Modrm|<gfni:attr>|<gfni:vexw1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1596 | gf2p8mulb<gfni>, 0x660f38cf, GFNI<gfni:cpu>, Modrm|<gfni:attr>|<gfni:vexw0>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
48521003 | 1597 | |
c0f3af97 L |
1598 | // AVX instructions. |
1599 | ||
390ddd6f | 1600 | <frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:, + |
33b6a20a JB |
1601 | unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, + |
1602 | nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, + | |
1603 | nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, + | |
1604 | neq_oq:0c:C, ge:0d:, ge_os:0d:, gt:0e:, gt_os:0e:, true:0f:C, + | |
1605 | true_uq:0f:C, eq_os:10:C, lt_oq:11:, le_oq:12:, + | |
1606 | unord_s:13:C, neq_us:14:C, nlt_uq:15:, nle_uq:16:, ord_s:17:C, eq_us:18:C, + | |
1607 | nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1e:, + | |
3fabc179 JB |
1608 | true_us:1f:C> |
1609 | ||
4e0dd3ab | 1610 | // <Vxy> is used for VEX instructions with x/y suffixes. |
39bb3ade JB |
1611 | // NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain |
1612 | // in sync with <Exy>, for match_template()'s EVEX-to-VEX lowering to | |
1613 | // continue to work. | |
d7680f13 | 1614 | <Vxy:vex:syntax:src, + |
e07ae9a3 JB |
1615 | $i:Vex:IntelSyntax:RegXMM|RegYMM|Unspecified|BaseIndex, + |
1616 | $a:Vex:ATTSyntax:RegXMM|RegYMM, + | |
1617 | x:Vex128:ATTSyntax:RegXMM|Unspecified|BaseIndex, + | |
1618 | y:Vex256:ATTSyntax:RegYMM|Unspecified|BaseIndex> | |
1619 | ||
f2a3a881 CL |
1620 | vaddp<sd>, 0x<sd:ppfx>58, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1621 | vadds<sd>, 0x<sd:spfx>58, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1622 | vaddsubpd, 0x66d0, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1623 | vaddsubps, 0xf2d0, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1624 | vandnp<sd>, 0x<sd:ppfx>55, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1625 | vandp<sd>, 0x<sd:ppfx>54, AVX, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1626 | vblendp<sd>, 0x660c | <sd:opc>, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1627 | vblendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
ec3babb8 JB |
1628 | vbroadcastf128, 0x661a, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } |
1629 | // vbroadcastf32x4 in disguise (see vround{p,s}{s,d} comment) | |
1630 | vbroadcastf128, 0x661a, APX_F&AVX512VL, Modrm|EVex256|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } | |
4fdeb2a3 JB |
1631 | vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } |
1632 | vbroadcastss, 0x6618, AVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
f2a3a881 CL |
1633 | vcmp<frel>p<sd>, 0x<sd:ppfx>c2/0x<frel:imm>, AVX, Modrm|<frel:comm>|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
1634 | vcmp<frel>s<sd>, 0x<sd:spfx>c2/0x<frel:imm>, AVX, Modrm|<frel:comm>|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1635 | vcmpp<sd>, 0x<sd:ppfx>c2, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1636 | vcmps<sd>, 0x<sd:spfx>c2, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
4fdeb2a3 JB |
1637 | vcomis<sd>, 0x<sd:ppfx>2f, AVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } |
1638 | vcvtdq2pd, 0xf3e6, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
1639 | vcvtdq2pd, 0xf3e6, AVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
9c19e9ec | 1640 | vcvtdq2ps, 0x5b, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
d7680f13 JB |
1641 | vcvtpd2dq<Vxy>, 0xf2e6, AVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:src>, RegXMM } |
1642 | vcvtpd2ps<Vxy>, 0x665a, AVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:src>, RegXMM } | |
9c19e9ec | 1643 | vcvtps2dq, 0x665b, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
4fdeb2a3 JB |
1644 | vcvtps2pd, 0x5a, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } |
1645 | vcvtps2pd, 0x5a, AVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
1646 | vcvts<sd>2si, 0x<sd:spfx>2d, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
f2a3a881 CL |
1647 | vcvtsd2ss, 0xf25a, AVX, Modrm|Vex=3|Space0F|Src1VVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1648 | vcvtsi2s<sd>, 0x<sd:spfx>2a, AVX, Modrm|VexLIG|Space0F|Src1VVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1649 | vcvtsi2s<sd>, 0x<sd:spfx>2a, AVX, Modrm|VexLIG|Space0F|Src1VVVV|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1650 | vcvtss2sd, 0xf35a, AVX, Modrm|Vex=3|Space0F|Src1VVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
d7680f13 | 1651 | vcvttpd2dq<Vxy>, 0x66e6, AVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:src>, RegXMM } |
4fdeb2a3 JB |
1652 | vcvttps2dq, 0xf35b, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
1653 | vcvtts<sd>2si, 0x<sd:spfx>2c, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
f2a3a881 CL |
1654 | vdivp<sd>, 0x<sd:ppfx>5e, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1655 | vdivs<sd>, 0x<sd:spfx>5e, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1656 | vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1657 | vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
ec3babb8 JB |
1658 | vextractf128, 0x6619, AVX, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } |
1659 | // vextractf32x4 in disguise (see vround{p,s}{s,d} comment) | |
1660 | vextractf128, 0x6619, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex } | |
e20298da | 1661 | vextractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } |
a5e91879 | 1662 | vextractps, 0x6617, x64&(AVX|AVX512F), RegMem|Vex128|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } |
f2a3a881 CL |
1663 | vhaddpd, 0x667c, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1664 | vhaddps, 0xf27c, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1665 | vhsubpd, 0x667d, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1666 | vhsubps, 0xf27d, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1667 | vinsertf128, 0x6618, AVX, Modrm|Vex256|Space0F3A|Src1VVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } | |
ec3babb8 | 1668 | // vinsertf32x4 in disguise (see vround{p,s}{s,d} comment) |
f2a3a881 CL |
1669 | vinsertf128, 0x6618, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf, { Imm8, Xmmword|Unspecified|BaseIndex, RegYMM, RegYMM } |
1670 | vinsertps, 0x6621, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
9c19e9ec | 1671 | vlddqu, 0xf2f0, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } |
4fdeb2a3 JB |
1672 | vldmxcsr, 0xae/2, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } |
1673 | vmaskmovdqu, 0x66f7, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, RegXMM } | |
f2a3a881 CL |
1674 | vmaskmovp<sd>, 0x662e | <sd:opc>, AVX, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } |
1675 | vmaskmovp<sd>, 0x662c | <sd:opc>, AVX, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
1676 | vmaxp<sd>, 0x<sd:ppfx>5f, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1677 | vmaxs<sd>, 0x<sd:spfx>5f, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1678 | vminp<sd>, 0x<sd:ppfx>5d, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1679 | vmins<sd>, 0x<sd:spfx>5d, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
9c19e9ec | 1680 | vmovap<sd>, 0x<sd:ppfx>28, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
a5dabbb0 L |
1681 | // vmovd really shouldn't allow for 64bit operand (vmovq is the right |
1682 | // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated | |
1683 | // by Intel AVX spec). To avoid extra template in gcc x86 backend and | |
1684 | // support assembler for AMD64, we accept 64bit operand on vmovd so | |
1685 | // that we can use one template for both SSE and AVX instructions. | |
a6f3add0 | 1686 | vmovd, 0x666e, AVX|AVX512F, D|Modrm|Vex128|EVex128|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
a5e91879 | 1687 | vmovd, 0x667e, AVX&x64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } |
4fdeb2a3 JB |
1688 | vmovddup, 0xf212, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1689 | vmovddup, 0xf212, AVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } | |
9c19e9ec JB |
1690 | vmovdqa, 0x666f, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
1691 | vmovdqu, 0xf36f, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
f2a3a881 CL |
1692 | vmovhlps, 0x12, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } |
1693 | vmovhp<sd>, 0x<sd:ppfx>16, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
4fdeb2a3 | 1694 | vmovhp<sd>, 0x<sd:ppfx>17, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } |
f2a3a881 CL |
1695 | vmovlhps, 0x16, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } |
1696 | vmovlp<sd>, 0x<sd:ppfx>12, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
4fdeb2a3 JB |
1697 | vmovlp<sd>, 0x<sd:ppfx>13, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } |
1698 | vmovmskp<sd>, 0x<sd:ppfx>50, AVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } | |
9c19e9ec JB |
1699 | vmovntdq, 0x66e7, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } |
1700 | vmovntdqa, 0x662a, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
1701 | vmovntp<sd>, 0x<sd:ppfx>2b, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } | |
4fdeb2a3 JB |
1702 | vmovq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1703 | vmovq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
a5e91879 | 1704 | vmovq, 0x666e, x64&(AVX|AVX512F), D|Modrm|Vex128|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 | 1705 | vmovs<sd>, 0x<sd:spfx>10, AVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } |
f2a3a881 | 1706 | vmovs<sd>, 0x<sd:spfx>10, AVX, D|Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } |
9c19e9ec JB |
1707 | vmovshdup, 0xf316, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
1708 | vmovsldup, 0xf312, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1709 | vmovup<sd>, 0x<sd:ppfx>10, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
f2a3a881 CL |
1710 | vmpsadbw, 0x6642, AVX|AVX2, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1711 | vmulp<sd>, 0x<sd:ppfx>59, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1712 | vmuls<sd>, 0x<sd:spfx>59, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1713 | vorp<sd>, 0x<sd:ppfx>56, AVX, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
9c19e9ec JB |
1714 | vpabs<bw>, 0x661c | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
1715 | vpabsd, 0x661e, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
f2a3a881 CL |
1716 | vpackssdw, 0x666b, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1717 | vpacksswb, 0x6663, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1718 | vpackusdw, 0x662b, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1719 | vpackuswb, 0x6667, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1720 | vpadds<bw>, 0x66ec | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1721 | vpadd<bw>, 0x66fc | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1722 | vpaddd, 0x66fe, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1723 | vpaddq, 0x66d4, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1724 | vpaddus<bw>, 0x66dc | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1725 | vpalignr, 0x660f, AVX|AVX2, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1726 | vpand, 0x66db, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1727 | vpandn, 0x66df, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1728 | vpavg<bw>, 0x66e0 | (3 * <bw:opc>), AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1729 | vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1730 | vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1731 | vpcmpeq<bw>, 0x6674 | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1732 | vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1733 | vpcmpeqq, 0x6629, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
a5e91879 | 1734 | vpcmpestri, 0x6661, AVX&No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } |
73f55087 | 1735 | vpcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } |
a5e91879 | 1736 | vpcmpestrm, 0x6660, AVX&No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } |
73f55087 | 1737 | vpcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } |
f2a3a881 CL |
1738 | vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1739 | vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1740 | vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
4fdeb2a3 JB |
1741 | vpcmpistri, 0x6663, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } |
1742 | vpcmpistrm, 0x6662, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } | |
f2a3a881 CL |
1743 | vperm2f128, 0x6606, AVX, Modrm|Vex256|Space0F3A|Src1VVVV|VexW0|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } |
1744 | vpermilps, 0x660c, AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
a6f3add0 | 1745 | vpermilps, 0x6604, AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F3A|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 1746 | vpermilpd, 0x660d, AVX, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
a6f3add0 | 1747 | vpermilpd, 0x6605, AVX, Modrm|Vex|Space0F3A|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
a5e91879 | 1748 | vpextr<dq>, 0x6616, AVX&<dq:cpu64>, Modrm|Vex|Space0F3A|<dq:vexw64>|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } |
4fdeb2a3 JB |
1749 | vpextrw, 0x66c5, AVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } |
1750 | vpextr<bw>, 0x6614 | <bw:opc>, AVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } | |
1751 | vpextr<bw>, 0x6614 | <bw:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } | |
f2a3a881 CL |
1752 | vphaddd, 0x6602, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1753 | vphaddsw, 0x6603, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1754 | vphaddw, 0x6601, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
4fdeb2a3 | 1755 | vphminposuw, 0x6641, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } |
f2a3a881 CL |
1756 | vphsubd, 0x6606, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1757 | vphsubsw, 0x6607, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1758 | vphsubw, 0x6605, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1759 | vpinsrb, 0x6620, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } | |
1760 | vpinsrb, 0x6620, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1761 | vpinsr<dq>, 0x6622, AVX&<dq:cpu64>, Modrm|Vex|Space0F3A|Src1VVVV|<dq:vexw64>|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1762 | vpinsrw, 0x66c4, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } | |
1763 | vpinsrw, 0x66c4, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1764 | vpmaddubsw, 0x6604, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1765 | vpmaddwd, 0x66f5, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1766 | vpmaxsb, 0x663c, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1767 | vpmaxsd, 0x663d, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1768 | vpmaxsw, 0x66ee, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1769 | vpmaxub, 0x66de, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1770 | vpmaxud, 0x663f, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1771 | vpmaxuw, 0x663e, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1772 | vpminsb, 0x6638, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1773 | vpminsd, 0x6639, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1774 | vpminsw, 0x66ea, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1775 | vpminub, 0x66da, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1776 | vpminud, 0x663b, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1777 | vpminuw, 0x663a, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
4fdeb2a3 | 1778 | vpmovmskb, 0x66d7, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } |
a5e91879 JB |
1779 | vpmovsxbd, 0x6621, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } |
1780 | vpmovsxbq, 0x6622, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1781 | vpmovsxbw, 0x6620, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1782 | vpmovsxdq, 0x6625, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
a5e91879 JB |
1783 | vpmovsxwd, 0x6623, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } |
1784 | vpmovsxwq, 0x6624, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
1785 | vpmovzxbd, 0x6631, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
1786 | vpmovzxbq, 0x6632, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } | |
4fdeb2a3 JB |
1787 | vpmovzxbw, 0x6630, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1788 | vpmovzxdq, 0x6635, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
a5e91879 JB |
1789 | vpmovzxwd, 0x6633, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } |
1790 | vpmovzxwq, 0x6634, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
f2a3a881 CL |
1791 | vpmuldq, 0x6628, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1792 | vpmulhrsw, 0x660b, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1793 | vpmulhuw, 0x66e4, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1794 | vpmulhw, 0x66e5, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1795 | vpmulld, 0x6640, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1796 | vpmullw, 0x66d5, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1797 | vpmuludq, 0x66f4, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1798 | vpor, 0x66eb, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1799 | vpsadbw, 0x66f6, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1800 | vpshufb, 0x6600, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
c34d1cc9 JB |
1801 | vpshufd, 0x6670, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
1802 | vpshufhw, 0xf370, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1803 | vpshuflw, 0xf270, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
f2a3a881 CL |
1804 | vpsign<bw>, 0x6608 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1805 | vpsignd, 0x660a, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
c8866e3e | 1806 | vpsll<dq>, 0x6672 | <dq:opc>/6, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1807 | vpsll<dq>, 0x66f2 | <dq:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } |
c8866e3e CL |
1808 | vpslldq, 0x6673/7, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } |
1809 | vpsllw, 0x6671/6, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
f2a3a881 | 1810 | vpsllw, 0x66f1, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } |
c8866e3e | 1811 | vpsrad, 0x6672/4, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1812 | vpsrad, 0x66e2, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } |
c8866e3e | 1813 | vpsraw, 0x6671/4, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1814 | vpsraw, 0x66e1, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } |
c8866e3e | 1815 | vpsrl<dq>, 0x6672 | <dq:opc>/2, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1816 | vpsrl<dq>, 0x66d2 | <dq:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } |
c8866e3e CL |
1817 | vpsrldq, 0x6673/3, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } |
1818 | vpsrlw, 0x6671/2, AVX|AVX2, Modrm|Vex|Space0F|DstVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
f2a3a881 CL |
1819 | vpsrlw, 0x66d1, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1820 | vpsub<bw>, 0x66f8 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1821 | vpsub<dq>, 0x66fa | <dq:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1822 | vpsubs<bw>, 0x66e8 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1823 | vpsubus<bw>, 0x66d8 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
9c19e9ec | 1824 | vptest, 0x6617, AVX, Modrm|Vex|Space0F38|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 CL |
1825 | vpunpckhbw, 0x6668, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1826 | vpunpckhdq, 0x666a, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1827 | vpunpckhqdq, 0x666d, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1828 | vpunpckhwd, 0x6669, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1829 | vpunpcklbw, 0x6660, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1830 | vpunpckldq, 0x6662, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1831 | vpunpcklqdq, 0x666c, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1832 | vpunpcklwd, 0x6661, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1833 | vpxor, 0x66ef, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
9c19e9ec | 1834 | vrcpps, 0x53, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1835 | vrcpss, 0xf353, AVX, Modrm|Vex=3|Space0F|Src1VVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
9c19e9ec | 1836 | vroundp<sd>, 0x6608 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1837 | vrounds<sd>, 0x660a | <sd:opc>, AVX, Modrm|VexLIG|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
eea43579 JB |
1838 | // These are really clones of VRNDSCALE{P,S}{S,D}, with broadcast, masking, SAE, |
1839 | // 512-bit operand size, and register sources dropped. | |
5a635f1f | 1840 | vroundp<sd>, 0x6608 | <sd:opc>, APX_F&AVX512VL, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } |
f2a3a881 | 1841 | vrounds<sd>, 0x660a | <sd:opc>, APX_F&AVX512F, Modrm|EVexLIG|Space0F3A|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
9c19e9ec | 1842 | vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 CL |
1843 | vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|Src1VVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1844 | vshufp<sd>, 0x<sd:ppfx>c6, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
9c19e9ec | 1845 | vsqrtp<sd>, 0x<sd:ppfx>51, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
f2a3a881 | 1846 | vsqrts<sd>, 0x<sd:spfx>51, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
4fdeb2a3 | 1847 | vstmxcsr, 0xae/3, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } |
f2a3a881 CL |
1848 | vsubp<sd>, 0x<sd:ppfx>5c, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1849 | vsubs<sd>, 0x<sd:spfx>5c, AVX, Modrm|VexLIG|Space0F|Src1VVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
9c19e9ec | 1850 | vtestp<sd>, 0x660e | <sd:opc>, AVX, Modrm|Vex|Space0F38|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
4fdeb2a3 | 1851 | vucomis<sd>, 0x<sd:ppfx>2e, AVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } |
f2a3a881 CL |
1852 | vunpckhp<sd>, 0x<sd:ppfx>15, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1853 | vunpcklp<sd>, 0x<sd:ppfx>14, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1854 | vxorp<sd>, 0x<sd:ppfx>57, AVX, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
4fdeb2a3 JB |
1855 | vzeroall, 0x77, AVX, Vex=2|Space0F|VexWIG|NoSuf, {} |
1856 | vzeroupper, 0x77, AVX, Vex|Space0F|VexWIG|NoSuf, {} | |
c0f3af97 | 1857 | |
e07ae9a3 | 1858 | |
6c30d220 L |
1859 | // 256bit integer AVX2 instructions. |
1860 | ||
a5e91879 JB |
1861 | vpmovsxbd, 0x6621, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } |
1862 | vpmovsxbq, 0x6622, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
4fdeb2a3 JB |
1863 | vpmovsxbw, 0x6620, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } |
1864 | vpmovsxdq, 0x6625, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
a5e91879 JB |
1865 | vpmovsxwd, 0x6623, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } |
1866 | vpmovsxwq, 0x6624, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
1867 | vpmovzxbd, 0x6631, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
1868 | vpmovzxbq, 0x6632, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
4fdeb2a3 JB |
1869 | vpmovzxbw, 0x6630, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } |
1870 | vpmovzxdq, 0x6635, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
a5e91879 JB |
1871 | vpmovzxwd, 0x6633, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } |
1872 | vpmovzxwq, 0x6634, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
6c30d220 L |
1873 | |
1874 | // New AVX2 instructions. | |
1875 | ||
ec3babb8 JB |
1876 | vbroadcasti128, 0x665A, AVX2, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } |
1877 | // vbroadcasti32x4 in disguise (see vround{p,s}{s,d} comment) | |
1878 | vbroadcasti128, 0x665a, APX_F&AVX512VL, Modrm|EVex256|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } | |
4fdeb2a3 | 1879 | vbroadcastsd, 0x6619, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } |
a6f3add0 | 1880 | vbroadcastss, 0x6618, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 1881 | vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
4fdeb2a3 | 1882 | vpbroadcast<bw>, 0x6678 | <bw:opc>, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <bw:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } |
a6f3add0 JB |
1883 | vpbroadcastd, 0x6658, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
1884 | vpbroadcastq, 0x6659, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf|Optimize, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
f2a3a881 CL |
1885 | vperm2i128, 0x6646, AVX2, Modrm|Vex=2|Space0F3A|Src1VVVV|VexW0|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } |
1886 | vpermd, 0x6636, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
a6f3add0 | 1887 | vpermpd, 0x6601, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } |
f2a3a881 | 1888 | vpermps, 0x6616, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
a6f3add0 | 1889 | vpermq, 0x6600, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } |
ec3babb8 JB |
1890 | vextracti128, 0x6639, AVX2, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } |
1891 | // vextracti32x4 in disguise (see vround{p,s}{s,d} comment) | |
1892 | vextracti128, 0x6639, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex } | |
f2a3a881 | 1893 | vinserti128, 0x6638, AVX2, Modrm|Vex256|Space0F3A|Src1VVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } |
ec3babb8 | 1894 | // vinserti32x4 in disguise (see vround{p,s}{s,d} comment) |
f2a3a881 CL |
1895 | vinserti128, 0x6638, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf, { Imm8, Xmmword|Unspecified|BaseIndex, RegYMM, RegYMM } |
1896 | vpmaskmov<dq>, 0x668e, AVX2, Modrm|Vex|Space0F38|Src1VVVV|<dq:vexw>|CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } | |
1897 | vpmaskmov<dq>, 0x668c, AVX2, Modrm|Vex|Space0F38|Src1VVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
1898 | vpsllv<dq>, 0x6647, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1899 | vpsravd, 0x6646, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1900 | vpsrlv<dq>, 0x6645, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
6c30d220 L |
1901 | |
1902 | // AVX gather instructions | |
0820c9f5 CL |
1903 | vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|Src2VVVV|VexW1|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } |
1904 | vgatherdps, 0x6692, AVX2, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1905 | vgatherdps, 0x6692, AVX2, Modrm|Vex256|Space0F38|Src2VVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } | |
1906 | vgatherqp<sd>, 0x6693, AVX2, Modrm|Vex|Space0F38|Src2VVVV|<sd:vexw>|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM } | |
1907 | vgatherqpd, 0x6693, AVX2, Modrm|Vex256|Space0F38|Src2VVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } | |
1908 | vgatherqps, 0x6693, AVX2, Modrm|Vex256|Space0F38|Src2VVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1909 | vpgatherdd, 0x6690, AVX2, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1910 | vpgatherdd, 0x6690, AVX2, Modrm|Vex256|Space0F38|Src2VVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } | |
1911 | vpgatherdq, 0x6690, AVX2, Modrm|Vex|Space0F38|Src2VVVV|VexW1|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
1912 | vpgatherq<dq>, 0x6691, AVX2, Modrm|Vex128|Space0F38|Src2VVVV|<dq:vexw>|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM } | |
1913 | vpgatherqd, 0x6691, AVX2, Modrm|Vex256|Space0F38|Src2VVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1914 | vpgatherqq, 0x6691, AVX2, Modrm|Vex256|Space0F38|Src2VVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } | |
6c30d220 | 1915 | |
a5ff0eb2 L |
1916 | // AES + AVX |
1917 | ||
f2a3a881 CL |
1918 | vaesdec, 0x66de, AVX&AES, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1919 | vaesdeclast, 0x66df, AVX&AES, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1920 | vaesenc, 0x66dc, AVX&AES, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1921 | vaesenclast, 0x66dd, AVX&AES, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
a5e91879 JB |
1922 | vaesimc, 0x66db, AVX&AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } |
1923 | vaeskeygenassist, 0x66df, AVX&AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } | |
a5ff0eb2 | 1924 | |
d54678eb | 1925 | // PCLMULQDQ + AVX |
ce2f5b3c | 1926 | |
f2a3a881 CL |
1927 | vpclmulqdq, 0x6644, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1928 | vpclmullqlqdq, 0x6644/0x00, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1929 | vpclmulhqlqdq, 0x6644/0x01, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1930 | vpclmullqhqdq, 0x6644/0x10, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1931 | vpclmulhqhqdq, 0x6644/0x11, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
ce2f5b3c | 1932 | |
48521003 IT |
1933 | // GFNI + AVX |
1934 | ||
f2a3a881 CL |
1935 | vgf2p8affineinvqb, 0x66cf, AVX&GFNI, Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1936 | vgf2p8affineqb, 0x66ce, AVX&GFNI, Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1937 | vgf2p8mulb, 0x66cf, GFNI&(AVX|AVX512F), Modrm|Vex|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
48521003 | 1938 | |
c7b8aa3a L |
1939 | // FSGSBASE, RDRND and F16C |
1940 | ||
4fdeb2a3 JB |
1941 | rdfsbase, 0xf30fae/0, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } |
1942 | rdgsbase, 0xf30fae/1, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } | |
1943 | rdrand, 0xfc7/6, RdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } | |
1944 | wrfsbase, 0xf30fae/2, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } | |
1945 | wrgsbase, 0xf30fae/3, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } | |
1946 | vcvtph2ps, 0x6613, F16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1947 | vcvtph2ps, 0x6613, F16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1948 | vcvtps2ph, 0x661d, F16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
1949 | vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } | |
c7b8aa3a | 1950 | |
c0f3af97 L |
1951 | // FMA instructions |
1952 | ||
edb7c8ec JB |
1953 | <fma:opc, 132:10, 213:20, 231:30> |
1954 | ||
da0784f9 | 1955 | <sdh:cpu:cpudq:fma:ppfx:spfx:pfx:spc1:spc2:opc:vex:vexlig:vexw:elem, + |
a5e91879 JB |
1956 | s:AVX512F:AVX512DQ:FMA|AVX512F::f3:66:Space0F:Space0F38:0:Vex|EVexDYN:VexLIG|EVexLIG:VexW0:Dword, + |
1957 | d:AVX512F:AVX512DQ:FMA|AVX512F:66:f2:66:Space0F:Space0F38:1:Vex|EVexDYN:VexLIG|EVexLIG:VexW1:Qword, + | |
da0784f9 JB |
1958 | h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::EVexMap5:EVexMap6:0::EVexLIG:VexW0:Word> |
1959 | ||
f2a3a881 CL |
1960 | vfmadd<fma>p<sdh>, 0x6688 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
1961 | vfmadd<fma>s<sdh>, 0x6689 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1962 | vfmaddsub<fma>p<sdh>, 0x6686 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1963 | vfmsub<fma>p<sdh>, 0x668a | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1964 | vfmsub<fma>s<sdh>, 0x668b | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1965 | vfmsubadd<fma>p<sdh>, 0x6687 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1966 | vfnmadd<fma>p<sdh>, 0x668c | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1967 | vfnmadd<fma>s<sdh>, 0x668d | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1968 | vfnmsub<fma>p<sdh>, 0x668e | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
1969 | vfnmsub<fma>s<sdh>, 0x668f | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
c0f3af97 | 1970 | |
42164a71 L |
1971 | // HLE prefixes |
1972 | ||
4fdeb2a3 JB |
1973 | xacquire, 0xf2, HLE, NoSuf|IsPrefix, {} |
1974 | xrelease, 0xf3, HLE, NoSuf|IsPrefix, {} | |
42164a71 L |
1975 | |
1976 | // RTM instructions | |
4fdeb2a3 JB |
1977 | xabort, 0xc6f8, RTM, NoSuf, { Imm8 } |
1978 | xbegin, 0xc7f8, RTM, JumpDword|NoSuf, { Disp16|Disp32 } | |
1979 | xend, 0xf01d5, RTM, NoSuf, {} | |
1980 | xtest, 0xf01d6, HLE|RTM, NoSuf, {} | |
42164a71 | 1981 | |
6c30d220 | 1982 | // BMI2 instructions. |
eea96d3f | 1983 | |
0820c9f5 | 1984 | bzhi, 0xf5, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src2VVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
f2a3a881 CL |
1985 | mulx, 0xf2f6, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src1VVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } |
1986 | pdep, 0xf2f5, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src1VVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } | |
1987 | pext, 0xf3f5, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src1VVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } | |
6177c84d | 1988 | rorx, 0xf2f0, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
0820c9f5 CL |
1989 | sarx, 0xf3f7, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src2VVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
1990 | shlx, 0x66f7, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src2VVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
1991 | shrx, 0xf2f7, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src2VVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
6c30d220 | 1992 | |
922d8de8 DR |
1993 | // FMA4 instructions |
1994 | ||
f2a3a881 CL |
1995 | vfmaddp<sd>, 0x6668 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1996 | vfmadds<sd>, 0x666a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|Src1VVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
1997 | vfmaddsubp<sd>, 0x665c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1998 | vfmsubaddp<sd>, 0x665e | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1999 | vfmsubp<sd>, 0x666c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
2000 | vfmsubs<sd>, 0x666e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|Src1VVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
2001 | vfnmaddp<sd>, 0x6678 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
2002 | vfnmadds<sd>, 0x667a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|Src1VVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
2003 | vfnmsubp<sd>, 0x667c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
2004 | vfnmsubs<sd>, 0x667e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|Src1VVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
922d8de8 | 2005 | |
5dd85c99 SP |
2006 | // XOP instructions |
2007 | ||
390ddd6f JB |
2008 | <xop:opc, b:0, w:1, d:2, q:3> |
2009 | <irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7> | |
2010 | <sign:opc, :00, u:20> | |
2f13234b | 2011 | |
9c19e9ec | 2012 | vfrczp<sd>, 0x80 | <sd:opc>, XOP, Modrm|SpaceXOP09|VexW0|CheckOperandSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
4fdeb2a3 | 2013 | vfrczs<sd>, 0x82 | <sd:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { <sd:elem>|RegXMM|Unspecified|BaseIndex, RegXMM } |
f2a3a881 CL |
2014 | vpcmov, 0xa2, XOP, D|Modrm|Vex|SpaceXOP08|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
2015 | vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2016 | vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>/<irel:imm>, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2017 | vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Vex|Space0F3A|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
2018 | vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
4fdeb2a3 JB |
2019 | vphaddb<dq>, 0xc2 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } |
2020 | vphaddbw, 0xc1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2021 | vphadddq, 0xcb, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2022 | vphaddub<dq>, 0xd2 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2023 | vphaddubw, 0xd1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2024 | vphaddudq, 0xdb, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2025 | vphadduw<dq>, 0xd6 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2026 | vphaddw<dq>, 0xc6 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2027 | vphsubbw, 0xe1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2028 | vphsubdq, 0xe3, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2029 | vphsubwd, 0xe2, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
f2a3a881 CL |
2030 | vpmacsdd, 0x9e, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } |
2031 | vpmacsdqh, 0x9f, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2032 | vpmacsdql, 0x97, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2033 | vpmacssdd, 0x8e, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2034 | vpmacssdqh, 0x8f, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2035 | vpmacssdql, 0x87, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2036 | vpmacsswd, 0x86, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2037 | vpmacssww, 0x85, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2038 | vpmacswd, 0x96, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2039 | vpmacsww, 0x95, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2040 | vpmadcsswd, 0xa6, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2041 | vpmadcswd, 0xb6, XOP, Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2042 | vpperm, 0xa3, XOP, D|Modrm|Vex128|SpaceXOP08|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0820c9f5 | 2043 | vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|Src2VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } |
c34d1cc9 | 2044 | vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
0820c9f5 CL |
2045 | vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|Src2VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } |
2046 | vpshl<xop>, 0x94 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|Src2VVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } | |
390ddd6f JB |
2047 | |
2048 | <xop> | |
2049 | <irel> | |
2050 | <sign> | |
5dd85c99 | 2051 | |
f88c9eb0 SP |
2052 | // LWP instructions |
2053 | ||
4fdeb2a3 JB |
2054 | llwpcb, 0x12/0, LWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } |
2055 | slwpcb, 0x12/1, LWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } | |
c8866e3e CL |
2056 | lwpval, 0x12/1, LWP, Modrm|SpaceXOP0A|NoSuf|DstVVVV|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } |
2057 | lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|DstVVVV|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } | |
f88c9eb0 | 2058 | |
f12dc422 L |
2059 | // BMI instructions |
2060 | ||
f2a3a881 | 2061 | andn, 0xf2, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src1VVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } |
0820c9f5 | 2062 | bextr, 0xf7, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|Src2VVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
c8866e3e CL |
2063 | blsi, 0xf3/3, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|DstVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
2064 | blsmsk, 0xf3/2, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|DstVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2065 | blsr, 0xf3/1, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|DstVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
e20298da | 2066 | tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
dd74a603 | 2067 | tzcnt, 0xf4, BMI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
f12dc422 | 2068 | |
2a2a0f38 | 2069 | // TBM instructions |
eea96d3f JB |
2070 | |
2071 | bextr, 0x10, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP0A|No_bSuf|No_wSuf|No_sSuf, { Imm32|Imm32S, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
c8866e3e CL |
2072 | blcfill, 0x01/1, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
2073 | blci, 0x02/6, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2074 | blcic, 0x01/5, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2075 | blcmsk, 0x02/1, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2076 | blcs, 0x01/3, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2077 | blsfill, 0x01/2, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2078 | blsic, 0x01/6, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2079 | t1mskc, 0x01/7, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2080 | tzmsk, 0x01/4, TBM, Modrm|CheckOperandSize|Vex128|SpaceXOP09|DstVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2a2a0f38 | 2081 | |
40b8e679 L |
2082 | // AMD 3DNow! instructions. |
2083 | ||
4fdeb2a3 JB |
2084 | prefetch, 0xf0d/0, 3dnow|PRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
2085 | prefetchw, 0xf0d/1, 3dnow|PRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
2086 | femms, 0xf0e, 3dnow, NoSuf, {} | |
2087 | pavgusb, 0xf0f/0xbf, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2088 | pf2id, 0xf0f/0x1d, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2089 | pf2iw, 0xf0f/0x1c, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2090 | pfacc, 0xf0f/0xae, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2091 | pfadd, 0xf0f/0x9e, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2092 | pfcmpeq, 0xf0f/0xb0, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2093 | pfcmpge, 0xf0f/0x90, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2094 | pfcmpgt, 0xf0f/0xa0, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2095 | pfmax, 0xf0f/0xa4, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2096 | pfmin, 0xf0f/0x94, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2097 | pfmul, 0xf0f/0xb4, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2098 | pfnacc, 0xf0f/0x8a, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2099 | pfpnacc, 0xf0f/0x8e, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2100 | pfrcp, 0xf0f/0x96, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2101 | pfrcpit1, 0xf0f/0xa6, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2102 | pfrcpit2, 0xf0f/0xb6, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2103 | pfrsqit1, 0xf0f/0xa7, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2104 | pfrsqrt, 0xf0f/0x97, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2105 | pfsub, 0xf0f/0x9a, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2106 | pfsubr, 0xf0f/0xaa, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2107 | pi2fd, 0xf0f/0x0d, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2108 | pi2fw, 0xf0f/0x0c, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2109 | pmulhrw, 0xf0f/0xb7, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
2110 | pswapd, 0xf0f/0xbb, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
40b8e679 L |
2111 | |
2112 | // AMD extensions. | |
4fdeb2a3 JB |
2113 | syscall, 0xf05, SYSCALL, NoSuf, {} |
2114 | sysret, 0xf07, SYSCALL, No_bSuf|No_wSuf|No_sSuf, {} | |
2115 | swapgs, 0xf01f8, x64, NoSuf, {} | |
2116 | rdtscp, 0xf01f9, Rdtscp, NoSuf, {} | |
40b8e679 L |
2117 | |
2118 | // AMD Pacifica additions. | |
4fdeb2a3 JB |
2119 | clgi, 0xf01dd, SVME, NoSuf, {} |
2120 | invlpga, 0xf01df, SVME, NoSuf, {} | |
2121 | invlpga, 0xf01df, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword } | |
2122 | skinit, 0xf01de, SVME, NoSuf, {} | |
2123 | skinit, 0xf01de, SVME, IgnoreSize|NoSuf, { Acc|Dword } | |
2124 | stgi, 0xf01dc, SVME, NoSuf, {} | |
2125 | vmgexit, 0xf30f01d9, SEV_ES, NoSuf, {} | |
2126 | vmload, 0xf01da, SVME, NoSuf, {} | |
2127 | vmload, 0xf01da, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
2128 | vmmcall, 0xf01d9, SVME, NoSuf, {} | |
2129 | vmrun, 0xf01d8, SVME, NoSuf, {} | |
2130 | vmrun, 0xf01d8, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
2131 | vmsave, 0xf01db, SVME, NoSuf, {} | |
2132 | vmsave, 0xf01db, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
40b8e679 L |
2133 | |
2134 | ||
2135 | // SSE4a instructions | |
4fdeb2a3 JB |
2136 | movntsd, 0xf20f2b, SSE4a, Modrm|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } |
2137 | movntss, 0xf30f2b, SSE4a, Modrm|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2138 | extrq, 0x660f78/0, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM } | |
2139 | extrq, 0x660f79, SSE4a, Modrm|NoSuf, { RegXMM, RegXMM } | |
2140 | insertq, 0xf20f79, SSE4a, Modrm|NoSuf, { RegXMM, RegXMM } | |
2141 | insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } | |
40b8e679 | 2142 | |
272a84b1 | 2143 | // LZCNT instruction |
e20298da | 2144 | lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
dd74a603 | 2145 | lzcnt, 0xf5, LZCNT&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
272a84b1 L |
2146 | |
2147 | // POPCNT instruction | |
e20298da | 2148 | popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
dd74a603 | 2149 | popcnt, 0x88, POPCNT&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 | 2150 | |
40b8e679 | 2151 | // VIA PadLock extensions. |
4fdeb2a3 JB |
2152 | xstore-rng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} |
2153 | xcrypt-ecb, 0xf30fa7c8, PadLock, NoSuf|RepPrefixOk, {} | |
2154 | xcrypt-cbc, 0xf30fa7d0, PadLock, NoSuf|RepPrefixOk, {} | |
2155 | xcrypt-ctr, 0xf30fa7d8, PadLock, NoSuf|RepPrefixOk, {} | |
2156 | xcrypt-cfb, 0xf30fa7e0, PadLock, NoSuf|RepPrefixOk, {} | |
2157 | xcrypt-ofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {} | |
2158 | montmul, 0xf30fa6c0, PadLock, NoSuf|RepPrefixOk, {} | |
2159 | xsha1, 0xf30fa6c8, PadLock, NoSuf|RepPrefixOk, {} | |
2160 | xsha256, 0xf30fa6d0, PadLock, NoSuf|RepPrefixOk, {} | |
40b8e679 | 2161 | // Aliases without hyphens. |
4fdeb2a3 JB |
2162 | xstorerng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} |
2163 | xcryptecb, 0xf30fa7c8, PadLock, NoSuf|RepPrefixOk, {} | |
2164 | xcryptcbc, 0xf30fa7d0, PadLock, NoSuf|RepPrefixOk, {} | |
2165 | xcryptctr, 0xf30fa7d8, PadLock, NoSuf|RepPrefixOk, {} | |
2166 | xcryptcfb, 0xf30fa7e0, PadLock, NoSuf|RepPrefixOk, {} | |
2167 | xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {} | |
40b8e679 | 2168 | // Alias for xstore-rng. |
4fdeb2a3 | 2169 | xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} |
e2e1fcde L |
2170 | |
2171 | // Multy-precision Add Carry, rdseed instructions. | |
b38b161e JB |
2172 | <adx:pfx, c:66, o:f3> |
2173 | ad<adx>x, 0x<adx:pfx>66, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } | |
2174 | ad<adx>x, 0x<adx:pfx>0f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2175 | ad<adx>x, 0x<adx:pfx>66, ADX&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2176 | <adx> | |
4fdeb2a3 | 2177 | rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } |
5c111e37 L |
2178 | |
2179 | // SMAP instructions. | |
4fdeb2a3 JB |
2180 | clac, 0xf01ca, SMAP, NoSuf, {} |
2181 | stac, 0xf01cb, SMAP, NoSuf, {} | |
7e8b059b L |
2182 | |
2183 | // BND prefix | |
4fdeb2a3 | 2184 | bnd, 0xf2, MPX, NoSuf|IsPrefix, {} |
7e8b059b L |
2185 | |
2186 | // MPX instructions. | |
4fdeb2a3 JB |
2187 | bndmk, 0xf30f1b, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } |
2188 | bndmov, 0x660f1a, MPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } | |
a5e91879 JB |
2189 | bndcl, 0xf30f1a, MPX&No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } |
2190 | bndcl, 0xf30f1a, MPX&x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } | |
2191 | bndcu, 0xf20f1a, MPX&No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } | |
2192 | bndcu, 0xf20f1a, MPX&x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } | |
2193 | bndcn, 0xf20f1b, MPX&No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } | |
2194 | bndcn, 0xf20f1b, MPX&x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } | |
4fdeb2a3 JB |
2195 | bndstx, 0x0f1b, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } |
2196 | bndldx, 0x0f1a, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } | |
a0046408 L |
2197 | |
2198 | // SHA instructions. | |
c34d1cc9 | 2199 | sha1rnds4, 0xf3acc, SHA, Modrm|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } |
4fdeb2a3 JB |
2200 | sha1nexte, 0xf38c8, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
2201 | sha1msg1, 0xf38c9, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2202 | sha1msg2, 0xf38ca, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2203 | sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } | |
2204 | sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2205 | sha256msg1, 0xf38cc, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2206 | sha256msg2, 0xf38cd, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
43234a1e | 2207 | |
b5c37946 SJ |
2208 | // SHA512 instructions. |
2209 | ||
f2a3a881 | 2210 | vsha512rnds2, 0xf2cb, SHA512, Modrm|Vex256|Space0F38|Src1VVVV|VexW0|NoSuf, { RegXMM, RegYMM, RegYMM } |
b5c37946 SJ |
2211 | vsha512msg1, 0xf2cc, SHA512, Modrm|Vex256|Space0F38|VexW0|NoSuf, { RegXMM, RegYMM } |
2212 | vsha512msg2, 0xf2cd, SHA512, Modrm|Vex256|Space0F38|VexW0|NoSuf, { RegYMM, RegYMM } | |
2213 | ||
2214 | // SHA512 instructions end. | |
2215 | ||
2216 | // SM3 instructions. | |
f2a3a881 CL |
2217 | vsm3rnds2, 0x66de, SM3, Modrm|Space0F3A|Vex128|Src1VVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } |
2218 | vsm3msg1, 0xda, SM3, Modrm|Space0F38|Vex128|Src1VVVV|VexW0|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2219 | vsm3msg2, 0x66da, SM3, Modrm|Space0F38|Vex128|Src1VVVV|VexW0|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
b5c37946 SJ |
2220 | |
2221 | // SM3 instructions end. | |
2222 | ||
2223 | // SM4 instructions. | |
2224 | ||
f2a3a881 CL |
2225 | vsm4key4, 0xf3da, SM4, Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
2226 | vsm4rnds4, 0xf2da, SM4, Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
b5c37946 SJ |
2227 | |
2228 | // SM4 instructions end. | |
2229 | ||
d5f9027c JB |
2230 | // VAES |
2231 | ||
f2a3a881 CL |
2232 | vaesdec, 0x66de, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2233 | vaesdeclast, 0x66df, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2234 | vaesenc, 0x66dc, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2235 | vaesenclast, 0x66dd, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
d5f9027c JB |
2236 | |
2237 | // VAES instructions end | |
2238 | ||
ff1982d5 IT |
2239 | // VPCLMULQDQ instructions |
2240 | ||
f2a3a881 CL |
2241 | vpclmulqdq, 0x6644, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2242 | vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2243 | vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2244 | vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2245 | vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
ff1982d5 IT |
2246 | |
2247 | // VPCLMULQDQ instructions end | |
2248 | ||
43234a1e L |
2249 | // AVX512F instructions. |
2250 | ||
4e0dd3ab | 2251 | // <Exy> is used for EVEX instructions with x/y suffixes. |
39bb3ade JB |
2252 | // NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain |
2253 | // in sync with <Vxy>, for match_template()'s EVEX-to-VEX lowering to | |
2254 | // continue to work. | |
4e0dd3ab | 2255 | <Exy:vl:attr:sr:sae:src:dst, + |
e07ae9a3 | 2256 | $z::EVex512|Disp8MemShift=6:StaticRounding|SAE:SAE:RegZMM|Unspecified|BaseIndex:RegYMM, + |
4fdeb2a3 JB |
2257 | $i:AVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, + |
2258 | $a:AVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegXMM, + | |
2259 | x:AVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, + | |
2260 | y:AVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM> | |
e07ae9a3 | 2261 | |
f2a3a881 CL |
2262 | kand<bw>, 0x<bw:kpfx>41, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } |
2263 | kandn<bw>, 0x<bw:kpfx>42, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
2264 | kor<bw>, 0x<bw:kpfx>45, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
2265 | kxnor<bw>, 0x<bw:kpfx>46, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
2266 | kxor<bw>, 0x<bw:kpfx>47, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
9a182d04 | 2267 | |
6177c84d CL |
2268 | kmov<bw>, 0x<bw:kpfx>90, APX_F(<bw:kcpu>), Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { RegMask|<bw:elem>|Unspecified|BaseIndex, RegMask } |
2269 | kmov<bw>, 0x<bw:kpfx>91, APX_F(<bw:kcpu>), Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { RegMask, <bw:elem>|Unspecified|BaseIndex } | |
2270 | kmov<bw>, 0x<bw:kpfx>92, APX_F(<bw:kcpu>), D|Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } | |
9a182d04 | 2271 | |
68993386 JB |
2272 | knot<bw>, 0x<bw:kpfx>44, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } |
2273 | kortest<bw>, 0x<bw:kpfx>98, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } | |
9a182d04 | 2274 | |
68993386 JB |
2275 | kshiftl<bw>, 0x6632, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|NoSuf, { Imm8, RegMask, RegMask } |
2276 | kshiftr<bw>, 0x6630, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|NoSuf, { Imm8, RegMask, RegMask } | |
9a182d04 | 2277 | |
f2a3a881 | 2278 | kunpckbw, 0x664B, AVX512F, Modrm|Vex=2|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } |
9a182d04 | 2279 | |
f2a3a881 CL |
2280 | vaddp<sdh>, 0x<sdh:ppfx>58, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2281 | vdivp<sdh>, 0x<sdh:ppfx>5e, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2282 | vmulp<sdh>, 0x<sdh:ppfx>59, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
b1c79256 | 2283 | vsqrtp<sdh>, 0x<sdh:ppfx>51, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 CL |
2284 | vsubp<sdh>, 0x<sdh:ppfx>5c, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2285 | ||
2286 | vadds<sdh>, 0x<sdh:spfx>58, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2287 | vdivs<sdh>, 0x<sdh:spfx>5e, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2288 | vmuls<sdh>, 0x<sdh:spfx>59, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2289 | vsqrts<sdh>, 0x<sdh:spfx>51, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2290 | vsubs<sdh>, 0x<sdh:spfx>5C, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2291 | ||
2292 | valign<dq>, 0x6603, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2293 | vblendmp<sd>, 0x6665, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2294 | vpblendm<dq>, 0x6664, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2295 | vpermi2<dq>, 0x6676, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2296 | vpermi2p<sd>, 0x6677, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2297 | vpermt2<dq>, 0x667E, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2298 | vpermt2p<sd>, 0x667F, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2299 | vpmaxs<dq>, 0x663D, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2300 | vpmaxu<dq>, 0x663F, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2301 | vpmins<dq>, 0x6639, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2302 | vpminu<dq>, 0x663B, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2303 | vpmuldq, 0x6628, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2304 | vpmulld, 0x6640, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2305 | vprolv<dq>, 0x6615, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2306 | vprorv<dq>, 0x6614, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2307 | vpsravq, 0x6646, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2308 | vpternlog<dq>, 0x6625, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
b1c79256 JB |
2309 | |
2310 | vbroadcastf32x4, 0x661A, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
2311 | vbroadcasti32x4, 0x665A, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
2312 | ||
2313 | vbroadcastf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
2314 | vbroadcasti64x4, 0x665B, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
2315 | ||
b1c79256 JB |
2316 | vbroadcastsd, 0x6619, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2317 | ||
a6f3add0 | 2318 | vpbroadcastq, 0x6659, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
b1c79256 JB |
2319 | vpbroadcast<dq>, 0x667c, AVX512F, Modrm|Masking|Space0F38|<dq:vexw64>|NoSuf, { <dq:gpr>, RegXMM|RegYMM|RegZMM } |
2320 | ||
f2a3a881 CL |
2321 | vcmp<frel>p<sd>, 0x<sd:ppfx>C2/0x<frel:imm>, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2322 | vcmpp<sd>, 0x<sd:ppfx>C2, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
b1c79256 | 2323 | |
f2a3a881 CL |
2324 | vcmp<frel>s<sd>, 0x<sd:spfx>C2/0x<frel:imm>, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } |
2325 | vcmps<sd>, 0x<sd:spfx>C2, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } | |
9a182d04 | 2326 | |
68993386 JB |
2327 | vcomis<sdh>, 0x<sdh:ppfx>2f, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM } |
2328 | vucomis<sdh>, 0x<sdh:ppfx>2e, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM } | |
9a182d04 | 2329 | |
b1c79256 JB |
2330 | vcompresspd, 0x668A, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } |
2331 | vcompressps, 0x668A, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
2332 | vpcompressq, 0x668B, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
2333 | vpcompressd, 0x668B, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
9a182d04 | 2334 | |
b1c79256 JB |
2335 | vpscatterdd, 0x66A0, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } |
2336 | vpscatterdq, 0x66A0, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2337 | vpscatterqd, 0x66A1, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
2338 | vpscatterqq, 0x66A1, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2339 | vscatterdpd, 0x66A2, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2340 | vscatterdps, 0x66A2, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } | |
2341 | vscatterqpd, 0x66A3, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2342 | vscatterqps, 0x66A3, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
9a182d04 | 2343 | |
b1c79256 JB |
2344 | vcvtdq2pd, 0xF3E6, AVX512F, Modrm|EVex=1|Masking|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
2345 | vcvtudq2pd, 0xF37A, AVX512F, Modrm|EVex=1|Masking|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } | |
9a182d04 | 2346 | |
b1c79256 JB |
2347 | vcvtdq2ps, 0x5B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2348 | vcvtps2udq, 0x79, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
cf665fee | 2349 | |
a5e91879 | 2350 | vcvtpd2dq<Exy>, 0xf2e6, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
cf665fee | 2351 | |
a5e91879 | 2352 | vcvtpd2ps<Exy>, 0x665a, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
cf665fee | 2353 | |
a5e91879 | 2354 | vcvtpd2udq<Exy>, 0x79, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
cf665fee | 2355 | |
b1c79256 | 2356 | vcvtph2ps, 0x6613, AVX512F, Modrm|EVex512|Masking|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } |
cf665fee | 2357 | |
b1c79256 | 2358 | vcvtps2dq, 0x665B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
cf665fee | 2359 | |
b1c79256 | 2360 | vcvtps2pd, 0x5A, AVX512F, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
cf665fee | 2361 | |
b1c79256 | 2362 | vcvtps2ph, 0x661D, AVX512F, Modrm|EVex512|Masking|Space0F3A|VexW0|Disp8MemShift=5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } |
cf665fee | 2363 | |
4fdeb2a3 | 2364 | vcvts<sd>2si, 0x<sd:spfx>2d, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
68993386 | 2365 | vcvts<sdh>2usi, 0x<sdh:spfx>79, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
cf665fee | 2366 | |
f2a3a881 | 2367 | vcvtsd2ss, 0xF25A, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
cf665fee | 2368 | |
f2a3a881 CL |
2369 | vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } |
2370 | vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2371 | vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2372 | vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2373 | vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2374 | vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2375 | vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2376 | vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
cf665fee | 2377 | |
f2a3a881 CL |
2378 | vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } |
2379 | vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2380 | vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2381 | vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
cf665fee | 2382 | |
f2a3a881 | 2383 | vcvtss2sd, 0xF35A, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } |
cf665fee | 2384 | |
a5e91879 JB |
2385 | vcvttpd2dq<Exy>, 0x66e6, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } |
2386 | vcvttpd2udq<Exy>, 0x78, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } | |
cf665fee | 2387 | |
b1c79256 JB |
2388 | vcvttps2dq, 0xF35B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2389 | vcvttps2udq, 0x78, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
cf665fee | 2390 | |
4fdeb2a3 | 2391 | vcvtts<sd>2si, 0x<sd:spfx>2c, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
68993386 | 2392 | vcvtts<sdh>2usi, 0x<sdh:spfx>78, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
cf665fee | 2393 | |
b1c79256 | 2394 | vcvtudq2ps, 0xF27A, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2395 | |
b1c79256 JB |
2396 | vexpandpd, 0x6688, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2397 | vpexpandq, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2398 | |
b1c79256 JB |
2399 | vexpandps, 0x6688, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2400 | vpexpandd, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2401 | |
b1c79256 JB |
2402 | vextractf32x4, 0x6619, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } |
2403 | vextracti32x4, 0x6639, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } | |
9a182d04 | 2404 | |
b1c79256 JB |
2405 | vextractf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } |
2406 | vextracti64x4, 0x663B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } | |
9a182d04 | 2407 | |
f2a3a881 CL |
2408 | vfixupimmp<sd>, 0x6654, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2409 | vfixupimms<sd>, 0x6655, AVX512F, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
b1c79256 JB |
2410 | |
2411 | vgetmantp<sdh>, 0x<sdh:pfx>26, <sdh:cpu>, Modrm|Masking|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
f2a3a881 | 2412 | vgetmants<sdh>, 0x<sdh:pfx>27, <sdh:cpu>, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
b1c79256 JB |
2413 | |
2414 | vrndscalep<sdh>, 0x<sdh:pfx>08 | <sdh:opc>, <sdh:cpu>, Modrm|Masking|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
f2a3a881 | 2415 | vrndscales<sdh>, 0x<sdh:pfx>0a | <sdh:opc>, <sdh:cpu>, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
b1c79256 | 2416 | |
f2a3a881 CL |
2417 | vscalefp<sdh>, 0x662c, <sdh:cpu>, Modrm|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2418 | vscalefs<sdh>, 0x662d, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
b1c79256 JB |
2419 | |
2420 | vgatherdpd, 0x6692, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
2421 | vgatherdps, 0x6692, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } | |
2422 | vgatherqpd, 0x6693, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
2423 | vgatherqps, 0x6693, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2424 | vpgatherdd, 0x6690, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } | |
2425 | vpgatherdq, 0x6690, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
2426 | vpgatherqd, 0x6691, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2427 | vpgatherqq, 0x6691, AVX512F, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
9a182d04 | 2428 | |
9c19e9ec | 2429 | vmovntdqa, 0x662A, AVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2430 | |
b1c79256 | 2431 | vgetexpp<sdh>, 0x6642, <sdh:cpu>, Modrm|Masking|<sdh:spc2>|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2432 | vgetexps<sdh>, 0x6643, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
9a182d04 | 2433 | |
f2a3a881 CL |
2434 | vinsertf32x4, 0x6618, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2435 | vinserti32x4, 0x6638, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
9a182d04 | 2436 | |
f2a3a881 CL |
2437 | vinsertf64x4, 0x661A, AVX512F, Modrm|EVex=1|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } |
2438 | vinserti64x4, 0x663A, AVX512F, Modrm|EVex=1|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } | |
9a182d04 | 2439 | |
f2a3a881 | 2440 | vinsertps, 0x6621, AVX512F, Modrm|EVex128|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } |
9a182d04 | 2441 | |
f2a3a881 CL |
2442 | vmaxp<sdh>, 0x<sdh:ppfx>5f, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2443 | vmaxs<sdh>, 0x<sdh:spfx>5f, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2444 | |
f2a3a881 CL |
2445 | vminp<sdh>, 0x<sdh:ppfx>5d, <sdh:cpu>, Modrm|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2446 | vmins<sdh>, 0x<sdh:spfx>5d, <sdh:cpu>, Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2447 | |
b1c79256 | 2448 | vmovap<sd>, 0x<sd:ppfx>28, AVX512F, D|Modrm|Masking|Space0F|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
9c19e9ec | 2449 | vmovntp<sd>, 0x<sd:ppfx>2B, AVX512F, Modrm|Space0F|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } |
b1c79256 | 2450 | vmovup<sd>, 0x<sd:ppfx>10, AVX512F, D|Modrm|Masking|Space0F|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2451 | |
b1c79256 | 2452 | vmovddup, 0xF212, AVX512F, Modrm|Masking|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } |
9a182d04 | 2453 | |
b1c79256 JB |
2454 | vmovdqa64, 0x666F, AVX512F, D|Modrm|Masking|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2455 | vmovdqa32, 0x666F, AVX512F, D|Modrm|Masking|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9c19e9ec | 2456 | vmovntdq, 0x66E7, AVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } |
b1c79256 JB |
2457 | vmovdqu32, 0xF36F, AVX512F, D|Modrm|Masking|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2458 | vmovdqu64, 0xF36F, AVX512F, D|Modrm|Masking|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2459 | |
f2a3a881 CL |
2460 | vmovhlps, 0x12, AVX512F, Modrm|EVex=4|Space0F|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM, RegXMM } |
2461 | vmovlhps, 0x16, AVX512F, Modrm|EVex=4|Space0F|Src1VVVV|VexW0|NoSuf, { RegXMM, RegXMM, RegXMM } | |
9a182d04 | 2462 | |
f2a3a881 | 2463 | vmovhp<sd>, 0x<sd:ppfx>16, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
4fdeb2a3 | 2464 | vmovhp<sd>, 0x<sd:ppfx>17, AVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } |
f2a3a881 | 2465 | vmovlp<sd>, 0x<sd:ppfx>12, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
4fdeb2a3 | 2466 | vmovlp<sd>, 0x<sd:ppfx>13, AVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } |
9a182d04 | 2467 | |
4fdeb2a3 JB |
2468 | vmovq, 0xF37E, AVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
2469 | vmovq, 0x66D6, AVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
9a182d04 | 2470 | |
b1c79256 | 2471 | vmovs<sdh>, 0x<sdh:spfx>10, <sdh:cpu>, D|Modrm|EVexLIG|Masking|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf, { <sdh:elem>|Unspecified|BaseIndex, RegXMM } |
f2a3a881 | 2472 | vmovs<sdh>, 0x<sdh:spfx>10, <sdh:cpu>, D|Modrm|EVexLIG|Masking|<sdh:spc1>|Src1VVVV|<sdh:vexw>|NoSuf, { RegXMM, RegXMM, RegXMM } |
b1c79256 JB |
2473 | |
2474 | vmovshdup, 0xF316, AVX512F, Modrm|Masking|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2475 | vmovsldup, 0xF312, AVX512F, Modrm|Masking|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2476 | ||
2477 | vpabs<dq>, 0x661e | <dq:opc>, AVX512F, Modrm|Masking|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
f2a3a881 CL |
2478 | vpaddd, 0x66FE, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2479 | vpaddq, 0x66d4, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2480 | vpand<dq>, 0x66db, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2481 | vpandn<dq>, 0x66df, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2482 | vpmuludq, 0x66f4, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2483 | vpor<dq>, 0x66eb, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2484 | vpsub<dq>, 0x66fa | <dq:opc>, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2485 | vpunpckhdq, 0x666A, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2486 | vpunpckhqdq, 0x666d, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2487 | vpunpckldq, 0x6662, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2488 | vpunpcklqdq, 0x666c, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2489 | vpxor<dq>, 0x66ef, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2490 | |
390ddd6f | 2491 | <irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6> |
865e2027 | 2492 | |
f2a3a881 CL |
2493 | vpcmpeqd, 0x6676, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2494 | vpcmpeqq, 0x6629, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2495 | vpcmpgtd, 0x6666, AVX512F, Modrm|Masking|Space0F|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2496 | vpcmpgtq, 0x6637, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2497 | vpcmp<dq>, 0x661f, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2498 | vpcmpu<dq>, 0x661e, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2499 | vpcmp<irel><dq>, 0x661f/<irel:imm>, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2500 | vpcmp<irel>u<dq>, 0x661e/<irel:imm>, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
7091c612 | 2501 | |
f2a3a881 CL |
2502 | vptestm<dq>, 0x6627, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2503 | vptestnm<dq>, 0xf327, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
7091c612 | 2504 | |
a6f3add0 | 2505 | vpermilpd, 0x6605, AVX512F, Modrm|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2506 | vpermilpd, 0x660d, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
7091c612 | 2507 | |
f2a3a881 CL |
2508 | vpermpd, 0x6616, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2509 | vpermq, 0x6636, AVX512F, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
43234a1e | 2510 | |
b1c79256 JB |
2511 | vpmovdb, 0xF331, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } |
2512 | vpmovsdb, 0xF321, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
2513 | vpmovusdb, 0xF311, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
ae2387fe | 2514 | |
b1c79256 JB |
2515 | vpmovdw, 0xF333, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
2516 | vpmovsdw, 0xF323, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2517 | vpmovusdw, 0xF313, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
ae2387fe | 2518 | |
b1c79256 JB |
2519 | vpmovqb, 0xF332, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } |
2520 | vpmovsqb, 0xF322, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2521 | vpmovusqb, 0xF312, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } | |
ae2387fe | 2522 | |
b1c79256 JB |
2523 | vpmovqd, 0xF335, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
2524 | vpmovsqd, 0xF325, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2525 | vpmovusqd, 0xF315, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
ae2387fe | 2526 | |
b1c79256 JB |
2527 | vpmovqw, 0xF334, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } |
2528 | vpmovsqw, 0xF324, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
2529 | vpmovusqw, 0xF314, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
43234a1e | 2530 | |
b1c79256 JB |
2531 | vpmovsxbd, 0x6621, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } |
2532 | vpmovzxbd, 0x6631, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2533 | |
b1c79256 JB |
2534 | vpmovsxbq, 0x6622, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } |
2535 | vpmovzxbq, 0x6632, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2536 | |
b1c79256 JB |
2537 | vpmovsxdq, 0x6625, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } |
2538 | vpmovzxdq, 0x6635, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2539 | |
b1c79256 JB |
2540 | vpmovsxwd, 0x6623, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } |
2541 | vpmovzxwd, 0x6633, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2542 | |
b1c79256 JB |
2543 | vpmovsxwq, 0x6624, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } |
2544 | vpmovzxwq, 0x6634, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2545 | |
c8866e3e CL |
2546 | vprol<dq>, 0x6672/1, AVX512F, Modrm|Masking|Space0F|DstVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2547 | vpror<dq>, 0x6672/0, AVX512F, Modrm|Masking|Space0F|DstVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2548 | |
b1c79256 | 2549 | vpshufd, 0x6670, AVX512F, Modrm|Masking|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2550 | |
f2a3a881 | 2551 | vpsll<dq>, 0x66f2 | <dq:opc>, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
c8866e3e | 2552 | vpsll<dq>, 0x6672 | <dq:opc>/6, AVX512F, Modrm|Masking|Space0F|DstVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2553 | vpsra<dq>, 0x66e2, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
c8866e3e | 2554 | vpsra<dq>, 0x6672/4, AVX512F, Modrm|Masking|Space0F|DstVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2555 | vpsrl<dq>, 0x66d2 | <dq:opc>, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<dq:vexw>|Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
c8866e3e | 2556 | vpsrl<dq>, 0x6672 | <dq:opc>/2, AVX512F, Modrm|Masking|Space0F|DstVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2557 | |
b1c79256 | 2558 | vrcp14p<sd>, 0x664C, AVX512F, Modrm|Masking|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2559 | vrcp14s<sd>, 0x664D, AVX512F, Modrm|EVexLIG|Masking|Space0F38|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
43234a1e | 2560 | |
b1c79256 | 2561 | vrsqrt14p<sd>, 0x664E, AVX512F, Modrm|Masking|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2562 | vrsqrt14s<sd>, 0x664F, AVX512F, Modrm|EVexLIG|Masking|Space0F38|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
43234a1e | 2563 | |
f2a3a881 CL |
2564 | vshuff32x4, 0x6623, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2565 | vshufi32x4, 0x6643, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
43234a1e | 2566 | |
f2a3a881 CL |
2567 | vshuff64x2, 0x6623, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2568 | vshufi64x2, 0x6643, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
43234a1e | 2569 | |
f2a3a881 | 2570 | vshufp<sd>, 0x<sd:ppfx>C6, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
43234a1e | 2571 | |
f2a3a881 CL |
2572 | vunpckhp<sd>, 0x<sd:ppfx>15, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2573 | vunpcklp<sd>, 0x<sd:ppfx>14, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
957d0955 | 2574 | |
43234a1e L |
2575 | // AVX512F instructions end. |
2576 | ||
2577 | // AVX512CD instructions. | |
2578 | ||
4fdeb2a3 JB |
2579 | vpbroadcastmb2q, 0xF32A, AVX512CD, Modrm|Space0F38|EVex=5|VexW=2|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } |
2580 | vpbroadcastmw2d, 0xF33A, AVX512CD, Modrm|Space0F38|EVex=5|VexW=1|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2581 | |
b1c79256 | 2582 | vpconflict<dq>, 0x66c4, AVX512CD, Modrm|Masking|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2583 | |
b1c79256 | 2584 | vplzcnt<dq>, 0x6644, AVX512CD, Modrm|Masking|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2585 | |
43234a1e L |
2586 | // AVX512CD instructions end. |
2587 | ||
2588 | // AVX512ER instructions. | |
2589 | ||
b1c79256 | 2590 | vexp2p<sd>, 0x66C8, AVX512ER, Modrm|EVex512|Masking|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } |
43234a1e | 2591 | |
b1c79256 | 2592 | vrcp28p<sd>, 0x66CA, AVX512ER, Modrm|EVex512|Masking|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } |
f2a3a881 | 2593 | vrcp28s<sd>, 0x66CB, AVX512ER, Modrm|EVexLIG|Masking|Space0F38|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
43234a1e | 2594 | |
b1c79256 | 2595 | vrsqrt28p<sd>, 0x66CC, AVX512ER, Modrm|EVex512|Masking|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } |
f2a3a881 | 2596 | vrsqrt28s<sd>, 0x66CD, AVX512ER, Modrm|EVexLIG|Masking|Space0F38|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
43234a1e L |
2597 | |
2598 | // AVX512ER instructions end. | |
2599 | ||
2600 | // AVX512PF instructions. | |
2601 | ||
b1c79256 JB |
2602 | vgatherpf0dpd, 0x66C6/1, AVX512PF, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } |
2603 | vgatherpf0dps, 0x66C6/1, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2604 | vgatherpf0qp<sd>, 0x66C7/1, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
2605 | vgatherpf1dpd, 0x66C6/2, AVX512PF, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } | |
2606 | vgatherpf1dps, 0x66C6/2, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2607 | vgatherpf1qp<sd>, 0x66C7/2, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
d580ae46 | 2608 | |
b1c79256 JB |
2609 | vscatterpf0dpd, 0x66C6/5, AVX512PF, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } |
2610 | vscatterpf0dps, 0x66C6/5, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2611 | vscatterpf0qp<sd>, 0x66C7/5, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
2612 | vscatterpf1dpd, 0x66C6/6, AVX512PF, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } | |
2613 | vscatterpf1dps, 0x66C6/6, AVX512PF, Modrm|EVex=1|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2614 | vscatterpf1qp<sd>, 0x66C7/6, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
43234a1e | 2615 | |
43234a1e | 2616 | // AVX512PF instructions end. |
963f3586 | 2617 | |
4fdeb2a3 | 2618 | // PREFETCHWT1 instructions. |
dcf893b5 | 2619 | |
4fdeb2a3 | 2620 | prefetchwt1, 0x0F0D/2, PREFETCHWT1, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
dcf893b5 | 2621 | |
4fdeb2a3 | 2622 | // PREFETCHWT1 instructions end. |
dcf893b5 | 2623 | |
963f3586 IT |
2624 | // CLFLUSHOPT instructions. |
2625 | ||
4fdeb2a3 | 2626 | clflushopt, 0x660fae/7, ClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
963f3586 IT |
2627 | |
2628 | // CLFLUSHOPT instructions end. | |
2629 | ||
2630 | // XSAVES/XRSTORS instructions. | |
2631 | ||
80d61d8d CL |
2632 | xrstors, 0xfc7/3, XSAVES, Modrm|NoSuf|NoEgpr, { Unspecified|BaseIndex } |
2633 | xrstors64, 0xfc7/3, XSAVES&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } | |
2634 | xsaves, 0xfc7/5, XSAVES, Modrm|NoSuf|NoEgpr, { Unspecified|BaseIndex } | |
2635 | xsaves64, 0xfc7/5, XSAVES&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } | |
963f3586 IT |
2636 | |
2637 | // XSAVES instructions end. | |
2638 | ||
2639 | // XSAVEC instructions. | |
2640 | ||
80d61d8d CL |
2641 | xsavec, 0xfc7/4, XSAVEC, Modrm|NoSuf|NoEgpr, { Unspecified|BaseIndex } |
2642 | xsavec64, 0xfc7/4, XSAVEC&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } | |
963f3586 IT |
2643 | |
2644 | // XSAVEC instructions end. | |
2cf200a4 IT |
2645 | |
2646 | // SGX instructions. | |
2647 | ||
4fdeb2a3 JB |
2648 | encls, 0xf01cf, SE1, NoSuf, {} |
2649 | enclu, 0xf01d7, SE1, NoSuf, {} | |
2650 | enclv, 0xf01c0, SE1, NoSuf, {} | |
2cf200a4 IT |
2651 | |
2652 | // SGX instructions end. | |
b28d1bda IT |
2653 | |
2654 | // AVX512VL instructions. | |
2655 | ||
a5e91879 JB |
2656 | vgatherdpd, 0x6692, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } |
2657 | vgatherdps, 0x6692, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2658 | vgatherdps, 0x6692, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2659 | vgatherqp<sd>, 0x6693, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } | |
2660 | vgatherqpd, 0x6693, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } | |
2661 | vgatherqps, 0x6693, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2662 | vpgatherdd, 0x6690, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2663 | vpgatherdd, 0x6690, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2664 | vpgatherdq, 0x6690, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
2665 | vpgatherq<dq>, 0x6691, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <dq:elem>|Unspecified|BaseIndex, RegXMM } | |
2666 | vpgatherqd, 0x6691, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2667 | vpgatherqq, 0x6691, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } | |
2668 | ||
2669 | vpscatterdd, 0x66A0, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2670 | vpscatterdd, 0x66A0, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
2671 | vpscatterdq, 0x66A0, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } | |
2672 | vpscatterq<dq>, 0x66A1, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <dq:elem>|Unspecified|BaseIndex } | |
2673 | vpscatterqd, 0x66A1, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2674 | vpscatterqq, 0x66A1, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } | |
2675 | vscatterdpd, 0x66A2, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } | |
2676 | vscatterdps, 0x66A2, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2677 | vscatterdps, 0x66A2, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
2678 | vscatterqp<sd>, 0x66A3, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <sd:elem>|Unspecified|BaseIndex } | |
2679 | vscatterqpd, 0x66A3, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } | |
2680 | vscatterqps, 0x66A3, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2681 | ||
2682 | vcvtdq2pd, 0xF3E6, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2683 | vcvtdq2pd, 0xF3E6, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2684 | vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2685 | vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2686 | ||
2687 | vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2688 | vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2689 | ||
2690 | vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2691 | vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2692 | ||
2693 | vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex128|Masking|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2694 | vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex256|Masking|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } | |
2695 | ||
2696 | vmovddup, 0xF212, AVX512VL, Modrm|EVex=2|Masking|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2697 | ||
2698 | vpmovdb, 0xF331, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2699 | vpmovdb, 0xF331, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2700 | vpmovsdb, 0xF321, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2701 | vpmovsdb, 0xF321, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2702 | vpmovusdb, 0xF311, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2703 | vpmovusdb, 0xF311, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2704 | ||
2705 | vpmovdw, 0xF333, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2706 | vpmovdw, 0xF333, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2707 | vpmovsdw, 0xF323, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2708 | vpmovsdw, 0xF323, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2709 | vpmovusdw, 0xF313, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2710 | vpmovusdw, 0xF313, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2711 | ||
2712 | vpmovqb, 0xF332, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } | |
2713 | vpmovqb, 0xF332, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2714 | vpmovsqb, 0xF322, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } | |
2715 | vpmovsqb, 0xF322, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2716 | vpmovusqb, 0xF312, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } | |
2717 | vpmovusqb, 0xF312, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2718 | ||
2719 | vpmovqd, 0xF335, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2720 | vpmovqd, 0xF335, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2721 | vpmovsqd, 0xF325, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2722 | vpmovsqd, 0xF325, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2723 | vpmovusqd, 0xF315, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2724 | vpmovusqd, 0xF315, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2725 | ||
2726 | vpmovqw, 0xF334, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2727 | vpmovqw, 0xF334, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2728 | vpmovsqw, 0xF324, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2729 | vpmovsqw, 0xF324, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2730 | vpmovusqw, 0xF314, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2731 | vpmovusqw, 0xF314, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2732 | ||
2733 | vpmovsxdq, 0x6625, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2734 | vpmovsxdq, 0x6625, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2735 | vpmovzxdq, 0x6635, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2736 | vpmovzxdq, 0x6635, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 2737 | |
b28d1bda | 2738 | // AVX512VL instructions end. |
99282af6 | 2739 | |
e771e7c9 | 2740 | // AVX512BW instructions. |
1ba585e8 | 2741 | |
f2a3a881 CL |
2742 | kadd<dq>, 0x<dq:kpfx>4a, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } |
2743 | kand<dq>, 0x<dq:kpfx>41, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } | |
2744 | kandn<dq>, 0x<dq:kpfx>42, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } | |
6177c84d CL |
2745 | kmov<dq>, 0x<dq:kpfx>90, APX_F(AVX512BW), Modrm|Vex128|EVex128|Space0F|VexW1|NoSuf, { RegMask|<dq:elem>|Unspecified|BaseIndex, RegMask } |
2746 | kmov<dq>, 0x<dq:kpfx>91, APX_F(AVX512BW), Modrm|Vex128|EVex128|Space0F|VexW1|NoSuf, { RegMask, <dq:elem>|Unspecified|BaseIndex } | |
2747 | kmov<dq>, 0xf292, APX_F(AVX512BW), D|Modrm|Vex128|EVex128|Space0F|<dq:vexw64>|NoSuf, { <dq:gpr>, RegMask } | |
fa88a361 | 2748 | knot<dq>, 0x<dq:kpfx>44, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } |
f2a3a881 | 2749 | kor<dq>, 0x<dq:kpfx>45, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } |
fa88a361 HJ |
2750 | kortest<dq>, 0x<dq:kpfx>98, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } |
2751 | ktest<dq>, 0x<dq:kpfx>99, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } | |
f2a3a881 CL |
2752 | kxnor<dq>, 0x<dq:kpfx>46, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } |
2753 | kxor<dq>, 0x<dq:kpfx>47, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } | |
2754 | kunpckdq, 0x4B, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } | |
2755 | kunpckwd, 0x4B, AVX512BW, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
fa88a361 HJ |
2756 | kshiftl<dq>, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } |
2757 | kshiftr<dq>, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } | |
4fdeb2a3 | 2758 | |
f2a3a881 | 2759 | vdbpsadbw, 0x6642, AVX512BW, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
b1c79256 JB |
2760 | |
2761 | vmovdqu8, 0xF26F, AVX512BW, D|Modrm|Masking|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2762 | vmovdqu16, 0xF26F, AVX512BW, D|Modrm|Masking|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2763 | ||
2764 | vpabs<bw>, 0x661c | <bw:opc>, AVX512BW, Modrm|Masking|Space0F38|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
f2a3a881 CL |
2765 | vpmaxsb, 0x663C, AVX512BW, Modrm|Masking|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2766 | vpminsb, 0x6638, AVX512BW, Modrm|Masking|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2767 | vpshufb, 0x6600, AVX512BW, Modrm|Masking|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2768 | ||
2769 | vpmaddubsw, 0x6604, AVX512BW, Modrm|Masking|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2770 | vpmaxuw, 0x663E, AVX512BW, Modrm|Masking|VexWIG|Space0F38|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2771 | vpminuw, 0x663A, AVX512BW, Modrm|Masking|VexWIG|Space0F38|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2772 | vpmulhrsw, 0x660B, AVX512BW, Modrm|Masking|Space0F38|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2773 | ||
2774 | vpackssdw, 0x666B, AVX512BW, Modrm|Masking|Space0F|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2775 | vpacksswb, 0x6663, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2776 | vpackuswb, 0x6667, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2777 | vpackusdw, 0x662B, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2778 | ||
2779 | vpadd<bw>, 0x66fc | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2780 | vpadds<bw>, 0x66ec | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2781 | vpaddus<bw>, 0x66dc | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2782 | vpavg<bw>, 0x66e0 | (3 * <bw:opc>), AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2783 | vpmaxub, 0x66DE, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2784 | vpminub, 0x66DA, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2785 | vpsub<bw>, 0x66f8 | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2786 | vpsubs<bw>, 0x66e8 | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2787 | vpsubus<bw>, 0x66d8 | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2788 | vpunpckhbw, 0x6668, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2789 | vpunpcklbw, 0x6660, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2790 | ||
2791 | vpmaxsw, 0x66EE, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2792 | vpminsw, 0x66EA, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2793 | vpmulhuw, 0x66E4, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2794 | vpmulhw, 0x66E5, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2795 | vpmullw, 0x66D5, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
c8866e3e | 2796 | vpsllw, 0x6671/6, AVX512BW, Modrm|Masking|Space0F|VexWIG|DstVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2797 | vpsllw, 0x66F1, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
c8866e3e | 2798 | vpsraw, 0x6671/4, AVX512BW, Modrm|Masking|Space0F|VexWIG|DstVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2799 | vpsraw, 0x66E1, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
c8866e3e | 2800 | vpsrlw, 0x6671/2, AVX512BW, Modrm|Masking|Space0F|VexWIG|DstVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 CL |
2801 | vpsrlw, 0x66D1, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2802 | vpunpckhwd, 0x6669, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2803 | vpunpcklwd, 0x6661, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2804 | ||
2805 | vpalignr, 0x660F, AVX512BW, Modrm|Masking|Space0F3A|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2806 | ||
2807 | vpblendm<bw>, 0x6666, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
b1c79256 JB |
2808 | vpbroadcast<bw>, 0x6678 | <bw:opc>, AVX512BW, Modrm|Masking|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM|<bw:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2809 | vpbroadcast<bw>, 0x667a | <bw:opc>, AVX512BW, Modrm|Masking|Space0F38|VexW0|NoSuf, { Reg32, RegXMM|RegYMM|RegZMM } | |
2810 | ||
f2a3a881 CL |
2811 | vpermi2<bw>, 0x6675, <bw:cpubmi>, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2812 | vpermt2<bw>, 0x667d, <bw:cpubmi>, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2813 | vperm<bw>, 0x668d, <bw:cpubmi>, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2814 | vpsllvw, 0x6612, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2815 | vpsravw, 0x6611, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2816 | vpsrlvw, 0x6610, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
b1c79256 | 2817 | |
f2a3a881 CL |
2818 | vpcmpeq<bw>, 0x6674 | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2819 | vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX512BW, Modrm|Masking|Space0F|VexWIG|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2820 | vpcmp<bw>, 0x663f, AVX512BW, Modrm|Masking|Space0F3A|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2821 | vpcmpu<bw>, 0x663e, AVX512BW, Modrm|Masking|Space0F3A|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2822 | vpcmp<irel><bw>, 0x663f/<irel:imm>, AVX512BW, Modrm|Masking|Space0F3A|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2823 | vpcmp<irel>u<bw>, 0x663e/<irel:imm>, AVX512BW, Modrm|Masking|Space0F3A|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
68993386 | 2824 | |
c8866e3e CL |
2825 | vpslldq, 0x6673/7, AVX512BW, Modrm|Space0F|VexWIG|DstVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2826 | vpsrldq, 0x6673/3, AVX512BW, Modrm|Space0F|VexWIG|DstVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
68993386 | 2827 | |
4fdeb2a3 JB |
2828 | vpextrw, 0x66C5, AVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } |
2829 | vpextr<bw>, 0x6614 | <bw:opc>, AVX512BW, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } | |
2830 | vpextr<bw>, 0x6614 | <bw:opc>, AVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } | |
68993386 | 2831 | |
f2a3a881 CL |
2832 | vpinsrw, 0x66C4, AVX512BW, Modrm|EVex128|Space0F|VexWIG|Src1VVVV|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } |
2833 | vpinsrw, 0x66C4, AVX512BW, Modrm|EVex128|Space0F|VexWIG|Src1VVVV|Disp8MemShift=1|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2834 | vpinsrb, 0x6620, AVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Src1VVVV|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } | |
2835 | vpinsrb, 0x6620, AVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Src1VVVV|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } | |
68993386 | 2836 | |
f2a3a881 | 2837 | vpmaddwd, 0x66F5, AVX512BW, Modrm|Masking|Space0F|Src1VVVV|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
68993386 | 2838 | |
4fdeb2a3 JB |
2839 | vpmov<bw>2m, 0xf329, AVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } |
2840 | vpmovm2<bw>, 0xf328, AVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } | |
68993386 | 2841 | |
b1c79256 | 2842 | vpmovswb, 0xF320, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
a5e91879 JB |
2843 | vpmovswb, 0xF320, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } |
2844 | vpmovswb, 0xF320, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
68993386 | 2845 | |
b1c79256 | 2846 | vpmovuswb, 0xF310, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
a5e91879 JB |
2847 | vpmovuswb, 0xF310, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } |
2848 | vpmovuswb, 0xF310, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
68993386 | 2849 | |
b1c79256 | 2850 | vpmovwb, 0xF330, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
a5e91879 JB |
2851 | vpmovwb, 0xF330, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } |
2852 | vpmovwb, 0xF330, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
68993386 | 2853 | |
b1c79256 | 2854 | vpmovsxbw, 0x6620, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } |
a5e91879 JB |
2855 | vpmovsxbw, 0x6620, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } |
2856 | vpmovsxbw, 0x6620, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 2857 | vpmovzxbw, 0x6630, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } |
a5e91879 JB |
2858 | vpmovzxbw, 0x6630, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } |
2859 | vpmovzxbw, 0x6630, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
68993386 | 2860 | |
f2a3a881 | 2861 | vpsadbw, 0x66F6, AVX512BW, Modrm|Space0F|Src1VVVV|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
68993386 | 2862 | |
b1c79256 JB |
2863 | vpshufhw, 0xF370, AVX512BW, Modrm|Masking|Space0F|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2864 | vpshuflw, 0xF270, AVX512BW, Modrm|Masking|Space0F|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
68993386 | 2865 | |
f2a3a881 CL |
2866 | vptestm<bw>, 0x6626, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2867 | vptestnm<bw>, 0xf326, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
1ba585e8 IT |
2868 | |
2869 | // AVX512BW instructions end. | |
90a915bf IT |
2870 | |
2871 | // AVX512DQ instructions. | |
2872 | ||
e07ae9a3 JB |
2873 | <xyz:vl:attr:sr:att:src, + |
2874 | $i::Disp8ShiftVL|IntelSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, + | |
2875 | $a::Disp8ShiftVL|ATTSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|BaseIndex, + | |
2876 | z::EVex512|Disp8MemShift=6:StaticRounding|SAE:ATTSyntax:RegZMM|Unspecified|BaseIndex, + | |
4fdeb2a3 JB |
2877 | x:AVX512VL:EVex128|Disp8MemShift=4::ATTSyntax:RegXMM|Unspecified|BaseIndex, + |
2878 | y:AVX512VL:EVex256|Disp8MemShift=5::ATTSyntax:RegYMM|Unspecified|BaseIndex> | |
2879 | ||
f2a3a881 | 2880 | kadd<bw>, 0x<bw:kpfx>4A, AVX512DQ, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } |
4fdeb2a3 JB |
2881 | ktest<bw>, 0x<bw:kpfx>99, AVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } |
2882 | ||
f2a3a881 CL |
2883 | vandnp<sd>, 0x<sd:ppfx>55, AVX512DQ, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2884 | vandp<sd>, 0x<sd:ppfx>54, AVX512DQ, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2885 | vorp<sd>, 0x<sd:ppfx>56, AVX512DQ, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2886 | vxorp<sd>, 0x<sd:ppfx>57, AVX512DQ, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
4fdeb2a3 | 2887 | |
b1c79256 JB |
2888 | vbroadcastf32x2, 0x6619, AVX512DQ, Modrm|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2889 | vbroadcastf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
2890 | vbroadcasti32x2, 0x6659, AVX512DQ, Modrm|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2891 | vbroadcasti32x8, 0x665B, AVX512DQ, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
4fdeb2a3 | 2892 | |
b1c79256 JB |
2893 | vbroadcastf64x2, 0x661A, AVX512DQ, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2894 | vbroadcasti64x2, 0x665A, AVX512DQ, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
4fdeb2a3 | 2895 | |
b1c79256 JB |
2896 | vcvtpd2qq, 0x667B, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2897 | vcvtpd2uqq, 0x6679, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
4fdeb2a3 | 2898 | |
b1c79256 | 2899 | vcvtps2qq, 0x667B, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
a5e91879 JB |
2900 | vcvtps2qq, 0x667B, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
2901 | vcvtps2qq, 0x667B, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 2902 | vcvtps2uqq, 0x6679, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
a5e91879 JB |
2903 | vcvtps2uqq, 0x6679, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
2904 | vcvtps2uqq, 0x6679, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
4fdeb2a3 | 2905 | |
b1c79256 JB |
2906 | vcvtqq2pd, 0xF3E6, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2907 | vcvtuqq2pd, 0xF37A, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
4fdeb2a3 | 2908 | |
a5e91879 | 2909 | vcvtqq2ps<Exy>, 0x5b, AVX512DQ&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
4fdeb2a3 | 2910 | |
b1c79256 JB |
2911 | vcvttpd2qq, 0x667A, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2912 | vcvttpd2uqq, 0x6678, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
4fdeb2a3 | 2913 | |
b1c79256 | 2914 | vcvttps2qq, 0x667A, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
a5e91879 JB |
2915 | vcvttps2qq, 0x667A, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
2916 | vcvttps2qq, 0x667A, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 2917 | vcvttps2uqq, 0x6678, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
a5e91879 JB |
2918 | vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
2919 | vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
4fdeb2a3 | 2920 | |
a5e91879 | 2921 | vcvtuqq2ps<Exy>, 0xf27a, AVX512DQ&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
4fdeb2a3 | 2922 | |
b1c79256 JB |
2923 | vextractf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } |
2924 | vextracti32x8, 0x663B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } | |
f2a3a881 CL |
2925 | vinsertf32x8, 0x661A, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } |
2926 | vinserti32x8, 0x663A, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } | |
4fdeb2a3 | 2927 | |
a5e91879 | 2928 | vpextr<dq>, 0x6616, AVX512DQ&<dq:cpu64>, Modrm|EVex128|Space0F3A|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } |
f2a3a881 | 2929 | vpinsr<dq>, 0x6622, AVX512DQ&<dq:cpu64>, Modrm|EVex128|Space0F3A|Src1VVVV|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } |
4fdeb2a3 | 2930 | |
b1c79256 JB |
2931 | vextractf64x2, 0x6619, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } |
2932 | vextracti64x2, 0x6639, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } | |
f2a3a881 CL |
2933 | vinsertf64x2, 0x6618, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2934 | vinserti64x2, 0x6638, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
4fdeb2a3 | 2935 | |
b1c79256 JB |
2936 | vfpclassp<sd>, 0x6666, AVX512DQ, Modrm|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } |
2937 | vfpclassp<sd>, 0x6666, AVX512DQ, Modrm|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|BaseIndex, RegMask } | |
2938 | vfpclassp<sd>z, 0x6666, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf, { Imm8|Imm8S, RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } | |
a5e91879 JB |
2939 | vfpclassp<sd>x, 0x6666, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=4|NoSuf, { Imm8|Imm8S, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegMask } |
2940 | vfpclassp<sd>y, 0x6666, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=5|NoSuf, { Imm8|Imm8S, RegYMM|<sd:elem>|Unspecified|BaseIndex, RegMask } | |
b1c79256 | 2941 | vfpclasss<sdh>, 0x<sdh:pfx>67, <sdh:cpudq>, Modrm|EVexLIG|Masking|Space0F3A|<sdh:vexw>|Disp8MemShift|NoSuf, { Imm8|Imm8S, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegMask } |
9a182d04 | 2942 | |
4fdeb2a3 JB |
2943 | vpmov<dq>2m, 0xf339, AVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } |
2944 | vpmovm2<dq>, 0xf338, AVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2945 | |
f2a3a881 | 2946 | vpmullq, 0x6640, AVX512DQ, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2947 | |
f2a3a881 CL |
2948 | vrangep<sd>, 0x6650, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2949 | vranges<sd>, 0x6651, AVX512DQ, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2950 | |
b1c79256 | 2951 | vreducep<sdh>, 0x<sdh:pfx>56, <sdh:cpudq>, Modrm|Masking|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
f2a3a881 | 2952 | vreduces<sdh>, 0x<sdh:pfx>57, <sdh:cpudq>, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
90a915bf IT |
2953 | |
2954 | // AVX512DQ instructions end. | |
c5e7287a IT |
2955 | |
2956 | // CLWB instructions. | |
2957 | ||
4fdeb2a3 | 2958 | clwb, 0x660fae/6, CLWB, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
c5e7287a IT |
2959 | |
2960 | // CLWB instructions end. | |
9d8596f0 | 2961 | |
2cc1b5aa IT |
2962 | // AVX512IFMA instructions |
2963 | ||
f2a3a881 CL |
2964 | vpmadd52huq, 0x66B5, AVX512IFMA, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2965 | vpmadd52luq, 0x66B4, AVX512IFMA, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2cc1b5aa IT |
2966 | |
2967 | // AVX512IFMA instructions end | |
14f195c9 | 2968 | |
4321af3e HW |
2969 | // AVX-IFMA instructions. |
2970 | ||
f2a3a881 CL |
2971 | vpmadd52huq, 0x66B5, AVX_IFMA, Modrm|Vex|Space0F38|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
2972 | vpmadd52luq, 0x66B4, AVX_IFMA, Modrm|Vex|Space0F38|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
4321af3e HW |
2973 | |
2974 | // AVX-IFMA instructions end. | |
2975 | ||
14f195c9 IT |
2976 | // AVX512VBMI instructions |
2977 | ||
f2a3a881 | 2978 | vpmultishiftqb, 0x6683, AVX512VBMI, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
14f195c9 IT |
2979 | |
2980 | // AVX512VBMI instructions end | |
920d2ddc IT |
2981 | |
2982 | // AVX512_4FMAPS instructions | |
2983 | ||
f2a3a881 CL |
2984 | v4fmaddps, 0xf29a, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } |
2985 | v4fnmaddps, 0xf2aa, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } | |
2986 | v4fmaddss, 0xf29b, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2987 | v4fnmaddss, 0xf2ab, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
920d2ddc IT |
2988 | |
2989 | // AVX512_4FMAPS instructions end | |
029f3522 | 2990 | |
47acf0bd IT |
2991 | // AVX512_4VNNIW instructions |
2992 | ||
f2a3a881 CL |
2993 | vp4dpwssd, 0xf252, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } |
2994 | vp4dpwssds, 0xf253, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } | |
47acf0bd | 2995 | |
620214f7 IT |
2996 | // AVX512_4VNNIW instructions end |
2997 | ||
2998 | // AVX512_VPOPCNTDQ instructions | |
2999 | ||
b1c79256 | 3000 | vpopcnt<dq>, 0x6655, AVX512_VPOPCNTDQ, Modrm|Masking|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
620214f7 IT |
3001 | |
3002 | // AVX512_VPOPCNTDQ instructions end | |
47acf0bd | 3003 | |
53467f57 IT |
3004 | // AVX512_VBMI2 instructions |
3005 | ||
b1c79256 JB |
3006 | vpcompressb, 0x6663, AVX512_VBMI2, Modrm|Masking|Space0F38|VexW=1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } |
3007 | vpcompressw, 0x6663, AVX512_VBMI2, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
53467f57 | 3008 | |
b1c79256 JB |
3009 | vpexpandb, 0x6662, AVX512_VBMI2, Modrm|Masking|Space0F38|VexW=1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3010 | vpexpandw, 0x6662, AVX512_VBMI2, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
53467f57 | 3011 | |
f2a3a881 CL |
3012 | vpshldv<dq>, 0x6671, AVX512_VBMI2, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3013 | vpshldvw, 0x6670, AVX512_VBMI2, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 | 3014 | |
f2a3a881 CL |
3015 | vpshrdv<dq>, 0x6673, AVX512_VBMI2, Modrm|Masking|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3016 | vpshrdvw, 0x6672, AVX512_VBMI2, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 | 3017 | |
f2a3a881 CL |
3018 | vpshld<dq>, 0x6671, AVX512_VBMI2, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3019 | vpshldw, 0x6670, AVX512_VBMI2, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 | 3020 | |
f2a3a881 CL |
3021 | vpshrd<dq>, 0x6673, AVX512_VBMI2, Modrm|Masking|Space0F3A|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3022 | vpshrdw, 0x6672, AVX512_VBMI2, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 IT |
3023 | |
3024 | // AVX512_VBMI2 instructions end | |
3025 | ||
8cfcb765 IT |
3026 | // AVX512_VNNI instructions |
3027 | ||
f2a3a881 CL |
3028 | vpdpbusd, 0x6650, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3029 | vpdpwssd, 0x6652, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
8cfcb765 | 3030 | |
f2a3a881 CL |
3031 | vpdpbusds, 0x6651, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3032 | vpdpwssds, 0x6653, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
8cfcb765 IT |
3033 | |
3034 | // AVX512_VNNI instructions end | |
3035 | ||
837e225b JB |
3036 | // AVX_VNNI instructions |
3037 | ||
f2a3a881 CL |
3038 | vpdpbusd, 0x6650, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
3039 | vpdpwssd, 0x6652, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
837e225b | 3040 | |
f2a3a881 CL |
3041 | vpdpbusds, 0x6651, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
3042 | vpdpwssds, 0x6653, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
837e225b JB |
3043 | |
3044 | // AVX_VNNI instructions end | |
3045 | ||
23ae61ad CL |
3046 | // AVX-VNNI-INT8 instructions. |
3047 | ||
f2a3a881 CL |
3048 | vpdpbuud, 0x50, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
3049 | vpdpbuuds, 0x51, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3050 | vpdpbssd, 0xf250, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3051 | vpdpbssds, 0xf251, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3052 | vpdpbsud, 0xf350, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3053 | vpdpbsuds, 0xf351, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
23ae61ad CL |
3054 | |
3055 | // AVX-VNNI-INT8 instructions end. | |
3056 | ||
b5c37946 SJ |
3057 | // AVX-VNNI-INT16 instructions. |
3058 | ||
f2a3a881 CL |
3059 | vpdpwuud, 0xd2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
3060 | vpdpwuuds, 0xd3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3061 | vpdpwusd, 0x66d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3062 | vpdpwusds, 0x66d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3063 | vpdpwsud, 0xf3d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
3064 | vpdpwsuds, 0xf3d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
b5c37946 SJ |
3065 | |
3066 | // AVX-VNNI-INT16 instructions end. | |
3067 | ||
ee6872be IT |
3068 | // AVX512_BITALG instructions |
3069 | ||
b1c79256 | 3070 | vpopcnt<bw>, 0x6654, AVX512_BITALG, Modrm|Masking|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
ee6872be | 3071 | |
f2a3a881 | 3072 | vpshufbitqmb, 0x668f, AVX512_BITALG, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
ee6872be IT |
3073 | |
3074 | // AVX512_BITALG instructions end | |
3075 | ||
48521003 IT |
3076 | // AVX512 + GFNI instructions |
3077 | ||
f2a3a881 CL |
3078 | vgf2p8affineinvqb, 0x66cf, GFNI&AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3079 | vgf2p8affineqb, 0x66ce, GFNI&AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
48521003 IT |
3080 | |
3081 | // AVX512 + GFNI instructions end | |
3082 | ||
646cc3e0 GG |
3083 | // INVLPGB instructions |
3084 | ||
4fdeb2a3 JB |
3085 | invlpgb, 0xf01fe, INVLPGB, NoSuf, {} |
3086 | invlpgb, 0xf01fe, INVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } | |
646cc3e0 GG |
3087 | |
3088 | // INVLPGB instructions end | |
3089 | ||
3090 | // TLBSYNC instructions | |
3091 | ||
4fdeb2a3 | 3092 | tlbsync, 0xf01ff, TLBSYNC, NoSuf, {} |
646cc3e0 GG |
3093 | |
3094 | // TLBSYNC instructions end | |
3095 | ||
029f3522 GG |
3096 | // CLZERO instructions |
3097 | ||
4fdeb2a3 JB |
3098 | clzero, 0xf01fc, CLZERO, NoSuf, {} |
3099 | clzero, 0xf01fc, CLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
029f3522 GG |
3100 | |
3101 | // CLZERO instructions end | |
3102 | ||
9916071f | 3103 | // MONITORX/MWAITX instructions |
474da251 | 3104 | |
4fdeb2a3 JB |
3105 | monitorx, 0xf01fa, MWAITX, NoSuf, {} |
3106 | monitorx, 0xf01fa, MWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } | |
a79eaed6 | 3107 | // The 64-bit form exists only for compatibility with older gas. |
a5e91879 | 3108 | monitorx, 0xf01fa, MWAITX&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } |
9916071f | 3109 | |
4fdeb2a3 | 3110 | mwaitx, 0xf01fb, MWAITX, NoSuf, {} |
a79eaed6 | 3111 | // The 64-bit form exists only for compatibility with older gas. |
9c19e9ec | 3112 | mwaitx, 0xf01fb, MWAITX, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword } |
474da251 | 3113 | |
9916071f | 3114 | // MONITORX/MWAITX instructions end |
8eab4136 L |
3115 | |
3116 | // OSPKE instructions. | |
3117 | ||
4fdeb2a3 JB |
3118 | rdpkru, 0xf01ee, OSPKE, NoSuf, {} |
3119 | wrpkru, 0xf01ef, OSPKE, NoSuf, {} | |
8eab4136 L |
3120 | |
3121 | // OSPKE instructions end. | |
8bc52696 AF |
3122 | |
3123 | // RDPID instructions. | |
3124 | ||
a5e91879 JB |
3125 | rdpid, 0xf30fc7/7, RDPID&No64, Modrm|IgnoreSize|NoSuf, { Reg32 } |
3126 | rdpid, 0xf30fc7/7, RDPID&x64, Modrm|NoSuf|NoRex64, { Reg64 } | |
8bc52696 AF |
3127 | |
3128 | // RDPID instructions end. | |
6b40c462 L |
3129 | |
3130 | // PTWRITE instructions. | |
3131 | ||
ef9a6314 | 3132 | ptwrite, 0xf30fae/4, PTWRITE&No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex } |
a5e91879 | 3133 | ptwrite, 0xf30fae/4, PTWRITE&x64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } |
6b40c462 L |
3134 | |
3135 | // PTWRITE instructions end. | |
603555e5 L |
3136 | |
3137 | // CET instructions. | |
3138 | ||
4fdeb2a3 | 3139 | incsspd, 0xf30fae/5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } |
a5e91879 | 3140 | incsspq, 0xf30fae/5, SHSTK&x64, Modrm|NoSuf, { Reg64 } |
4fdeb2a3 | 3141 | rdsspd, 0xf30f1e/1, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } |
a5e91879 | 3142 | rdsspq, 0xf30f1e/1, SHSTK&x64, Modrm|NoSuf, { Reg64 } |
4fdeb2a3 JB |
3143 | saveprevssp, 0xf30f01ea, SHSTK, NoSuf, {} |
3144 | rstorssp, 0xf30f01/5, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
3145 | wrssd, 0x0f38f6, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } | |
c8054e73 | 3146 | wrssd, 0x66, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } |
0006623c JB |
3147 | wrssq, 0x0f38f6, SHSTK&x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } |
3148 | wrssq, 0x66, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } | |
4fdeb2a3 | 3149 | wrussd, 0x660f38f5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } |
c8054e73 | 3150 | wrussd, 0x6665, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } |
a5e91879 | 3151 | wrussq, 0x660f38f5, SHSTK&x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } |
6177c84d | 3152 | wrussq, 0x6665, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } |
4fdeb2a3 JB |
3153 | setssbsy, 0xf30f01e8, SHSTK, NoSuf, {} |
3154 | clrssbsy, 0xf30fae/6, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
3155 | endbr64, 0xf30f1efa, IBT, NoSuf, {} | |
3156 | endbr32, 0xf30f1efb, IBT, NoSuf, {} | |
603555e5 | 3157 | |
04ef582a | 3158 | // notrack prefix |
4fdeb2a3 | 3159 | notrack, 0x3e, IBT, NoSuf|IsPrefix, {} |
04ef582a | 3160 | |
603555e5 | 3161 | // CET instructions end. |
3233d7d0 IT |
3162 | |
3163 | // WBNOINVD instruction. | |
3164 | ||
4fdeb2a3 | 3165 | wbnoinvd, 0xf30f09, WBNOINVD, NoSuf, {} |
3233d7d0 IT |
3166 | |
3167 | // WBNOINVD instruction end. | |
be3a8dca IT |
3168 | |
3169 | // PCONFIG instruction. | |
3170 | ||
4fdeb2a3 | 3171 | pconfig, 0x0f01c5, PCONFIG, NoSuf, {} |
be3a8dca IT |
3172 | |
3173 | // PCONFIG instruction end. | |
de89d0a3 | 3174 | |
b5c37946 SJ |
3175 | // PBNDKB instruction. |
3176 | ||
3e624fa4 | 3177 | pbndkb, 0x0f01c7, PBNDKB, NoSuf, {} |
b5c37946 SJ |
3178 | |
3179 | // PBNDKB instruction end. | |
3180 | ||
de89d0a3 IT |
3181 | // WAITPKG instructions. |
3182 | ||
4fdeb2a3 JB |
3183 | umonitor, 0xf30fae/6, WAITPKG, Modrm|AddrPrefixOpReg|NoSuf, { Reg16|Reg32|Reg64 } |
3184 | tpause, 0x660fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } | |
3185 | tpause, 0x660fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } | |
3186 | umwait, 0xf20fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } | |
3187 | umwait, 0xf20fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } | |
de89d0a3 IT |
3188 | |
3189 | // WAITPKG instructions end. | |
c48935d7 IT |
3190 | |
3191 | // CLDEMOTE instructions. | |
3192 | ||
4fdeb2a3 | 3193 | cldemote, 0x0f1c/0, CLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
c48935d7 IT |
3194 | |
3195 | // CLDEMOTE instructions end. | |
c0a30a9f L |
3196 | |
3197 | // MOVDIR[I,64B] instructions. | |
3198 | ||
9c19e9ec | 3199 | movdiri, 0xf38f9, MOVDIRI, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
c8054e73 | 3200 | movdiri, 0xf9, MOVDIRI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
4fdeb2a3 | 3201 | movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
6177c84d | 3202 | movdir64b, 0x66f8, MOVDIR64B&APX_F, Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } |
c0a30a9f L |
3203 | |
3204 | // MOVEDIR instructions end. | |
d6aab7a1 XG |
3205 | |
3206 | // AVX512_BF16 instructions. | |
3207 | ||
f2a3a881 | 3208 | vcvtne2ps2bf16, 0xf272, AVX512_BF16, Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
d6aab7a1 | 3209 | |
a5e91879 | 3210 | vcvtneps2bf16<Exy>, 0xf372, AVX512_BF16&<Exy:vl>, Modrm|Space0F38|<Exy:attr>|Masking|VexW0|Broadcast|NoSuf, { <Exy:src>|Dword, <Exy:dst> } |
d6aab7a1 | 3211 | |
f2a3a881 | 3212 | vdpbf16ps, 0xf352, AVX512_BF16, Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
d6aab7a1 | 3213 | |
d6aab7a1 | 3214 | // AVX512_BF16 instructions end. |
5d79adc4 | 3215 | |
01d8ce74 | 3216 | // AVX-NE-CONVERT instructions. |
3217 | ||
4fdeb2a3 JB |
3218 | vbcstnebf162ps, 0xf3b1, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } |
3219 | vbcstnesh2ps, 0x66b1, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } | |
9c19e9ec JB |
3220 | vcvtneebf162ps, 0xf3b0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } |
3221 | vcvtneeph2ps, 0x66b0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3222 | vcvtneobf162ps, 0xf2b0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3223 | vcvtneoph2ps, 0xb0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
d7680f13 | 3224 | vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSuf|<Vxy:syntax>, { <Vxy:src>, RegXMM } |
01d8ce74 | 3225 | |
3226 | // AVX-NE-CONVERT instructions end. | |
3227 | ||
5d79adc4 L |
3228 | // ENQCMD instructions. |
3229 | ||
4fdeb2a3 | 3230 | enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
6177c84d | 3231 | enqcmd, 0xf2f8, APX_F(ENQCMD), Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } |
4fdeb2a3 | 3232 | enqcmds, 0xf30f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
6177c84d | 3233 | enqcmds, 0xf3f8, APX_F(ENQCMD), Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } |
5d79adc4 L |
3234 | |
3235 | // ENQCMD instructions end. | |
9186c494 L |
3236 | |
3237 | // VP2INTERSECT instructions. | |
3238 | ||
f2a3a881 | 3239 | vp2intersect<dq>, 0xf268, AVX512_VP2INTERSECT, Modrm|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
9186c494 L |
3240 | |
3241 | // VP2INTERSECT instructions end. | |
142861df JB |
3242 | |
3243 | // MCOMMIT instruction | |
3244 | ||
4fdeb2a3 | 3245 | mcommit, 0xf30f01fa, MCOMMIT, NoSuf, {} |
142861df JB |
3246 | |
3247 | // MCOMMIT instruction end | |
3248 | ||
646cc3e0 GG |
3249 | // SNP instructions |
3250 | ||
a5e91879 JB |
3251 | psmash, 0xf30f01ff, SNP&x64, NoSuf, {} |
3252 | psmash, 0xf30f01ff, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } | |
4fdeb2a3 JB |
3253 | pvalidate, 0xf20f01ff, SNP, NoSuf, {} |
3254 | pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } | |
a5e91879 JB |
3255 | rmpupdate, 0xf20f01fe, SNP&x64, NoSuf, {} |
3256 | rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } | |
3257 | rmpadjust, 0xf30f01fe, SNP&x64, NoSuf, {} | |
3258 | rmpadjust, 0xf30f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } | |
c0e54661 | 3259 | // The single-operand forms exist only for compatibility with older gas. |
4fdeb2a3 | 3260 | pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } |
a5e91879 JB |
3261 | rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } |
3262 | rmpadjust, 0xf30f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } | |
646cc3e0 GG |
3263 | |
3264 | // SNP instructions end | |
3265 | ||
b0e8fa7f TJ |
3266 | // RMPQUERY instruction |
3267 | ||
3e624fa4 JB |
3268 | rmpquery, 0xf30f01fd, RMPQUERY, NoSuf, {} |
3269 | rmpquery, 0xf30f01fd, RMPQUERY, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } | |
b0e8fa7f TJ |
3270 | |
3271 | // RMPQUERY instruction end | |
3272 | ||
142861df JB |
3273 | // RDPRU instruction |
3274 | ||
4fdeb2a3 | 3275 | rdpru, 0x0f01fd, RDPRU, NoSuf, {} |
142861df JB |
3276 | |
3277 | // RDPRU instruction end | |
4b27d27c L |
3278 | |
3279 | // SERIALIZE instruction. | |
3280 | ||
4fdeb2a3 | 3281 | serialize, 0x0f01e8, SERIALIZE, NoSuf, {} |
4b27d27c L |
3282 | |
3283 | // SERIALIZE instruction end. | |
bb651e8b CL |
3284 | |
3285 | // TSXLDTRK instructions. | |
3286 | ||
4fdeb2a3 JB |
3287 | xsusldtrk, 0xf20f01e8, TSXLDTRK, NoSuf, {} |
3288 | xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {} | |
bb651e8b CL |
3289 | |
3290 | // TSXLDTRK instructions end. | |
260cd341 LC |
3291 | |
3292 | // AMX instructions. | |
3293 | ||
6177c84d CL |
3294 | ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } |
3295 | sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } | |
260cd341 | 3296 | |
0820c9f5 CL |
3297 | tcmmimfp16ps, 0x666c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } |
3298 | tcmmrlfp16ps, 0x6c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } | |
d100d8c1 | 3299 | |
0820c9f5 CL |
3300 | tdpbf16ps, 0xf35c, AMX_BF16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } |
3301 | tdpfp16ps, 0xf25c, AMX_FP16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3302 | tdpbssd, 0xf25e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3303 | tdpbuud, 0x5e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3304 | tdpbusd, 0x665e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3305 | tdpbsud, 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } | |
260cd341 | 3306 | |
6177c84d CL |
3307 | tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } |
3308 | tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } | |
3309 | tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } | |
260cd341 | 3310 | |
3e624fa4 | 3311 | tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {} |
260cd341 | 3312 | |
3e624fa4 | 3313 | tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } |
260cd341 LC |
3314 | |
3315 | // AMX instructions end. | |
c4694f17 TG |
3316 | |
3317 | // KEYLOCKER instructions. | |
3318 | ||
4fdeb2a3 JB |
3319 | loadiwkey, 0xf30f38dc, KL, Load|Modrm|NoSuf, { RegXMM, RegXMM } |
3320 | encodekey128, 0xf30f38fa, KL, Modrm|NoSuf, { Reg32, Reg32 } | |
3321 | encodekey256, 0xf30f38fb, KL, Modrm|NoSuf, { Reg32, Reg32 } | |
3322 | aesenc128kl, 0xf30f38dc, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3323 | aesdec128kl, 0xf30f38dd, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3324 | aesenc256kl, 0xf30f38de, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3325 | aesdec256kl, 0xf30f38df, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3326 | aesencwide128kl, 0xf30f38d8/0, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
3327 | aesdecwide128kl, 0xf30f38d8/1, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
3328 | aesencwide256kl, 0xf30f38d8/2, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
3329 | aesdecwide256kl, 0xf30f38d8/3, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
c4694f17 TG |
3330 | |
3331 | // KEYLOCKER instructions end. | |
81d54bb7 CL |
3332 | |
3333 | // TDX instructions. | |
3334 | ||
4fdeb2a3 | 3335 | tdcall, 0x660f01cc, TDX, NoSuf, {} |
a5e91879 JB |
3336 | seamret, 0x660f01cd, TDX&x64, NoSuf, {} |
3337 | seamops, 0x660f01ce, TDX&x64, NoSuf, {} | |
3338 | seamcall, 0x660f01cf, TDX&x64, NoSuf, {} | |
81d54bb7 CL |
3339 | |
3340 | // TDX instructions end. | |
f64c42a9 LC |
3341 | |
3342 | // UINTR instructions. | |
3343 | ||
3e624fa4 JB |
3344 | uiret, 0xf30f01ec, UINTR, NoSuf, {} |
3345 | clui, 0xf30f01ee, UINTR, NoSuf, {} | |
3346 | stui, 0xf30f01ef, UINTR, NoSuf, {} | |
3347 | testui, 0xf30f01ed, UINTR, NoSuf, {} | |
3348 | senduipi, 0xf30fc7/6, UINTR, Modrm|NoSuf|NoRex64, { Reg64 } | |
f64c42a9 LC |
3349 | |
3350 | // UINTR instructions end. | |
c1fa250a LC |
3351 | |
3352 | // HRESET instructions. | |
3353 | ||
4fdeb2a3 | 3354 | hreset, 0xf30f3af0c0, HRESET, NoSuf, { Imm8 } |
c1fa250a LC |
3355 | |
3356 | // HRESET instructions end. | |
0cc78721 CL |
3357 | |
3358 | // FP16 (HFNI) instructions. | |
3359 | ||
f2a3a881 CL |
3360 | vfcmaddcph, 0xf256, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3361 | vfcmaddcsh, 0xf257, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3362 | |
f2a3a881 CL |
3363 | vfmaddcph, 0xf356, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3364 | vfmaddcsh, 0xf357, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3365 | |
f2a3a881 CL |
3366 | vfcmulcph, 0xf2d6, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3367 | vfcmulcsh, 0xf2d7, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3368 | |
f2a3a881 CL |
3369 | vfmulcph, 0xf3d6, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3370 | vfmulcsh, 0xf3d7, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3371 | |
f2a3a881 CL |
3372 | vcmp<frel>ph, 0xc2/0x<frel:imm>, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
3373 | vcmpph, 0xc2, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
0cc78721 | 3374 | |
f2a3a881 CL |
3375 | vcmp<frel>sh, 0xf3c2/0x<frel:imm>, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } |
3376 | vcmpsh, 0xf3c2, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } | |
0cc78721 | 3377 | |
a5e91879 JB |
3378 | vcvtdq2ph<Exy>, 0x5b, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } |
3379 | vcvtudq2ph<Exy>, 0xf27a, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } | |
e07ae9a3 | 3380 | |
a5e91879 JB |
3381 | vcvtqq2ph<xyz>, 0x5b, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } |
3382 | vcvtuqq2ph<xyz>, 0xf27a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } | |
e07ae9a3 | 3383 | |
a5e91879 | 3384 | vcvtpd2ph<xyz>, 0x665a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } |
e07ae9a3 | 3385 | |
a5e91879 | 3386 | vcvtps2phx<Exy>, 0x661d, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } |
0cc78721 | 3387 | |
b1c79256 JB |
3388 | vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3389 | vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
0cc78721 | 3390 | |
a5e91879 JB |
3391 | vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3392 | vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3393 | vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3394 | |
a5e91879 JB |
3395 | vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3396 | vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3397 | vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3398 | |
a5e91879 JB |
3399 | vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3400 | vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3401 | vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3402 | |
a5e91879 JB |
3403 | vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3404 | vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3405 | vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3406 | |
a5e91879 JB |
3407 | vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3408 | vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3409 | vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3410 | |
b1c79256 JB |
3411 | vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3412 | vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
0cc78721 | 3413 | |
f2a3a881 CL |
3414 | vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
3415 | vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3416 | |
f2a3a881 CL |
3417 | vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } |
3418 | vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3419 | |
f2a3a881 CL |
3420 | vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } |
3421 | vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3422 | |
f2a3a881 CL |
3423 | vcvtsh2sd, 0xf35a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
3424 | vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3425 | |
4fdeb2a3 | 3426 | vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } |
0cc78721 | 3427 | |
a5e91879 JB |
3428 | vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3429 | vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3430 | vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3431 | |
a5e91879 JB |
3432 | vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3433 | vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3434 | vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3435 | |
a5e91879 JB |
3436 | vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3437 | vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3438 | vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3439 | |
a5e91879 JB |
3440 | vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3441 | vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3442 | vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } |
0cc78721 | 3443 | |
a5e91879 JB |
3444 | vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3445 | vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
b1c79256 | 3446 | vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } |
cf665fee | 3447 | |
b1c79256 JB |
3448 | vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3449 | vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
cf665fee | 3450 | |
4fdeb2a3 | 3451 | vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } |
cf665fee | 3452 | |
a5e91879 | 3453 | vfpclassph<xyz>, 0x66, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8|Imm8S, <xyz:src>|Word, RegMask } |
0cc78721 | 3454 | |
4fdeb2a3 JB |
3455 | vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } |
3456 | vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } | |
0cc78721 | 3457 | |
b1c79256 | 3458 | vrcpph, 0x664c, AVX512_FP16, Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
0cc78721 | 3459 | |
f2a3a881 | 3460 | vrcpsh, 0x664d, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
0cc78721 | 3461 | |
b1c79256 | 3462 | vrsqrtph, 0x664e, AVX512_FP16, Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
0cc78721 | 3463 | |
f2a3a881 | 3464 | vrsqrtsh, 0x664f, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
0cc78721 | 3465 | |
0cc78721 | 3466 | // FP16 (HFNI) instructions end. |
ef07be45 CL |
3467 | |
3468 | // PREFETCHI instructions. | |
3469 | ||
3e624fa4 JB |
3470 | prefetchit0, 0xf18/7, PREFETCHI, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
3471 | prefetchit1, 0xf18/6, PREFETCHI, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
ef07be45 CL |
3472 | |
3473 | // PREFETCHI instructions end. | |
a93e3234 HJ |
3474 | |
3475 | // CMPCCXADD instructions. | |
3476 | ||
0820c9f5 | 3477 | cmp<cc>xadd, 0x66e<cc:opc>, APX_F(CMPCCXADD), Modrm|Vex|EVex128|Space0F38|Src2VVVV|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
a93e3234 HJ |
3478 | |
3479 | // CMPCCXADD instructions end. | |
941f0833 HL |
3480 | |
3481 | // WRMSRNS instruction. | |
3482 | ||
4fdeb2a3 | 3483 | wrmsrns, 0x0f01c6, WRMSRNS, NoSuf, {} |
941f0833 HL |
3484 | |
3485 | // WRMSRNS instruction end. | |
2188d6ea HL |
3486 | |
3487 | // MSRLIST instructions. | |
3488 | ||
3e624fa4 JB |
3489 | rdmsrlist, 0xf20f01c6, MSRLIST, NoSuf, {} |
3490 | wrmsrlist, 0xf30f01c6, MSRLIST, NoSuf, {} | |
2188d6ea HL |
3491 | |
3492 | // MSRLIST instructions end. | |
b06311ad KL |
3493 | |
3494 | // RAO-INT instructions. | |
3495 | ||
5fc0b1f7 JB |
3496 | <rao:pfx, add:, and:66, or:f2, xor:f3> |
3497 | a<rao>, 0x<rao:pfx>0f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } | |
3498 | a<rao>, 0x<rao:pfx>fc, RAO_INT&APX_F, Modrm|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } | |
3499 | <rao> | |
b06311ad KL |
3500 | |
3501 | // RAO-INT instructions end. | |
c88ed92f ZJ |
3502 | |
3503 | // LKGS instruction. | |
3504 | ||
3e624fa4 JB |
3505 | lkgs, 0xf20f00/6, LKGS, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } |
3506 | lkgs, 0xf20f00/6, LKGS, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } | |
c88ed92f ZJ |
3507 | |
3508 | // LKGS instruction end. | |
3509 | ||
3510 | // FRED instructions. | |
3511 | ||
3e624fa4 JB |
3512 | erets, 0xf20f01ca, FRED, NoSuf, {} |
3513 | eretu, 0xf30f01ca, FRED, NoSuf, {} | |
c88ed92f ZJ |
3514 | |
3515 | // FRED instructions end. | |
8170af78 HL |
3516 | |
3517 | // USER_MSR instructions. | |
3518 | ||
df5a4840 | 3519 | urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } |
5190fa38 JB |
3520 | urdmsr, 0xf2f8, USER_MSR&APX_F, RegMem|EVexMap4|VexW0|NoSuf, { Reg64, Reg64 } |
3521 | urdmsr, 0xf2f8/0, APX_F(USER_MSR), Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 } | |
df5a4840 | 3522 | uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } |
e59144c6 | 3523 | uwrmsr, 0xf3f8, USER_MSR&APX_F, Modrm|EVexMap4|VexW0|NoSuf, { Reg64, Reg64 } |
e7d74879 JB |
3524 | // Immediates want to be first; md_assemble() takes care of swapping operands |
3525 | // accordingly. | |
5190fa38 | 3526 | uwrmsr, 0xf3f8/0, APX_F(USER_MSR), Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 } |
8170af78 HL |
3527 | |
3528 | // USER_MSR instructions end. | |
08a98d4c MZ |
3529 | |
3530 | // APX Push2/Pop2 instructions. | |
c8866e3e CL |
3531 | //PUSH2/POP2 pushes/pops 2 GPRs at a time to/from the stack. So 2 GPRs are both |
3532 | //Dst/Src, here the V register is used to encode the Operand 1 (Intel format). | |
08a98d4c | 3533 | |
c8866e3e CL |
3534 | push2, 0xff/6, APX_F, Modrm|VexW0|EVexMap4|DstVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } |
3535 | push2p, 0xff/6, APX_F, Modrm|VexW1|EVexMap4|DstVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } | |
3536 | pop2, 0x8f/0, APX_F, Modrm|VexW0|EVexMap4|DstVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } | |
3537 | pop2p, 0x8f/0, APX_F, Modrm|VexW1|EVexMap4|DstVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } | |
08a98d4c MZ |
3538 | |
3539 | // APX Push2/Pop2 instructions end. |