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[thirdparty/binutils-gdb.git] / bfd / elf32-msp430.c
1 /* MSP430-specific support for 32-bit ELF
2 Copyright (C) 2002-2020 Free Software Foundation, Inc.
3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include "bfd.h"
24 #include "libiberty.h"
25 #include "libbfd.h"
26 #include "elf-bfd.h"
27 #include "elf/msp430.h"
28
29 static bfd_boolean debug_relocs = 0;
30
31 /* All users of this file have bfd_octets_per_byte (abfd, sec) == 1. */
32 #define OCTETS_PER_BYTE(ABFD, SEC) 1
33
34 static bfd_reloc_status_type
35 rl78_sym_diff_handler (bfd * abfd,
36 arelent * reloc,
37 asymbol * sym ATTRIBUTE_UNUSED,
38 void * addr ATTRIBUTE_UNUSED,
39 asection * input_sec,
40 bfd * out_bfd ATTRIBUTE_UNUSED,
41 char ** error_message ATTRIBUTE_UNUSED)
42 {
43 bfd_size_type octets;
44 octets = reloc->address * OCTETS_PER_BYTE (abfd, input_sec);
45
46 /* Catch the case where bfd_install_relocation would return
47 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
48 small section. It does not actually matter if this happens because all
49 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
50 this value, and it is that reloc that must fit into the section.
51
52 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
53 if ((octets + bfd_get_reloc_size (reloc->howto))
54 > bfd_get_section_limit_octets (abfd, input_sec))
55 return bfd_reloc_ok;
56 return bfd_reloc_continue;
57 }
58
59 static reloc_howto_type elf_msp430_howto_table[] =
60 {
61 HOWTO (R_MSP430_NONE, /* type */
62 0, /* rightshift */
63 3, /* size (0 = byte, 1 = short, 2 = long) */
64 0, /* bitsize */
65 FALSE, /* pc_relative */
66 0, /* bitpos */
67 complain_overflow_dont,/* complain_on_overflow */
68 bfd_elf_generic_reloc, /* special_function */
69 "R_MSP430_NONE", /* name */
70 FALSE, /* partial_inplace */
71 0, /* src_mask */
72 0, /* dst_mask */
73 FALSE), /* pcrel_offset */
74
75 HOWTO (R_MSP430_32, /* type */
76 0, /* rightshift */
77 2, /* size (0 = byte, 1 = short, 2 = long) */
78 32, /* bitsize */
79 FALSE, /* pc_relative */
80 0, /* bitpos */
81 complain_overflow_bitfield,/* complain_on_overflow */
82 bfd_elf_generic_reloc, /* special_function */
83 "R_MSP430_32", /* name */
84 FALSE, /* partial_inplace */
85 0xffffffff, /* src_mask */
86 0xffffffff, /* dst_mask */
87 FALSE), /* pcrel_offset */
88
89 /* A 10 bit PC relative relocation. */
90 HOWTO (R_MSP430_10_PCREL, /* type */
91 1, /* rightshift */
92 1, /* size (0 = byte, 1 = short, 2 = long) */
93 10, /* bitsize */
94 TRUE, /* pc_relative */
95 0, /* bitpos */
96 complain_overflow_bitfield,/* complain_on_overflow */
97 bfd_elf_generic_reloc, /* special_function */
98 "R_MSP430_10_PCREL", /* name */
99 FALSE, /* partial_inplace */
100 0x3ff, /* src_mask */
101 0x3ff, /* dst_mask */
102 TRUE), /* pcrel_offset */
103
104 /* A 16 bit absolute relocation. */
105 HOWTO (R_MSP430_16, /* type */
106 0, /* rightshift */
107 1, /* size (0 = byte, 1 = short, 2 = long) */
108 16, /* bitsize */
109 FALSE, /* pc_relative */
110 0, /* bitpos */
111 complain_overflow_dont,/* complain_on_overflow */
112 bfd_elf_generic_reloc, /* special_function */
113 "R_MSP430_16", /* name */
114 FALSE, /* partial_inplace */
115 0, /* src_mask */
116 0xffff, /* dst_mask */
117 FALSE), /* pcrel_offset */
118
119 /* A 16 bit PC relative relocation for command address. */
120 HOWTO (R_MSP430_16_PCREL, /* type */
121 1, /* rightshift */
122 1, /* size (0 = byte, 1 = short, 2 = long) */
123 16, /* bitsize */
124 TRUE, /* pc_relative */
125 0, /* bitpos */
126 complain_overflow_dont,/* complain_on_overflow */
127 bfd_elf_generic_reloc, /* special_function */
128 "R_MSP430_16_PCREL", /* name */
129 FALSE, /* partial_inplace */
130 0, /* src_mask */
131 0xffff, /* dst_mask */
132 TRUE), /* pcrel_offset */
133
134 /* A 16 bit absolute relocation, byte operations. */
135 HOWTO (R_MSP430_16_BYTE, /* type */
136 0, /* rightshift */
137 1, /* size (0 = byte, 1 = short, 2 = long) */
138 16, /* bitsize */
139 FALSE, /* pc_relative */
140 0, /* bitpos */
141 complain_overflow_dont,/* complain_on_overflow */
142 bfd_elf_generic_reloc, /* special_function */
143 "R_MSP430_16_BYTE", /* name */
144 FALSE, /* partial_inplace */
145 0xffff, /* src_mask */
146 0xffff, /* dst_mask */
147 FALSE), /* pcrel_offset */
148
149 /* A 16 bit absolute relocation for command address. */
150 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
151 1, /* rightshift */
152 1, /* size (0 = byte, 1 = short, 2 = long) */
153 16, /* bitsize */
154 TRUE, /* pc_relative */
155 0, /* bitpos */
156 complain_overflow_dont,/* complain_on_overflow */
157 bfd_elf_generic_reloc, /* special_function */
158 "R_MSP430_16_PCREL_BYTE",/* name */
159 FALSE, /* partial_inplace */
160 0xffff, /* src_mask */
161 0xffff, /* dst_mask */
162 TRUE), /* pcrel_offset */
163
164 /* A 10 bit PC relative relocation for complicated polymorphs. */
165 HOWTO (R_MSP430_2X_PCREL, /* type */
166 1, /* rightshift */
167 2, /* size (0 = byte, 1 = short, 2 = long) */
168 10, /* bitsize */
169 TRUE, /* pc_relative */
170 0, /* bitpos */
171 complain_overflow_bitfield,/* complain_on_overflow */
172 bfd_elf_generic_reloc, /* special_function */
173 "R_MSP430_2X_PCREL", /* name */
174 FALSE, /* partial_inplace */
175 0x3ff, /* src_mask */
176 0x3ff, /* dst_mask */
177 TRUE), /* pcrel_offset */
178
179 /* A 16 bit relaxable relocation for command address. */
180 HOWTO (R_MSP430_RL_PCREL, /* type */
181 1, /* rightshift */
182 1, /* size (0 = byte, 1 = short, 2 = long) */
183 16, /* bitsize */
184 TRUE, /* pc_relative */
185 0, /* bitpos */
186 complain_overflow_dont,/* complain_on_overflow */
187 bfd_elf_generic_reloc, /* special_function */
188 "R_MSP430_RL_PCREL", /* name */
189 FALSE, /* partial_inplace */
190 0, /* src_mask */
191 0xffff, /* dst_mask */
192 TRUE) /* pcrel_offset */
193
194 /* A 8-bit absolute relocation. */
195 , HOWTO (R_MSP430_8, /* type */
196 0, /* rightshift */
197 0, /* size (0 = byte, 1 = short, 2 = long) */
198 8, /* bitsize */
199 FALSE, /* pc_relative */
200 0, /* bitpos */
201 complain_overflow_dont,/* complain_on_overflow */
202 bfd_elf_generic_reloc, /* special_function */
203 "R_MSP430_8", /* name */
204 FALSE, /* partial_inplace */
205 0, /* src_mask */
206 0xffff, /* dst_mask */
207 FALSE), /* pcrel_offset */
208
209 /* Together with a following reloc, allows for the difference
210 between two symbols to be the real addend of the second reloc. */
211 HOWTO (R_MSP430_SYM_DIFF, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 rl78_sym_diff_handler, /* special handler. */
219 "R_MSP430_SYM_DIFF", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE) /* pcrel_offset */
224 };
225
226 static reloc_howto_type elf_msp430x_howto_table[] =
227 {
228 HOWTO (R_MSP430_NONE, /* type */
229 0, /* rightshift */
230 3, /* size (0 = byte, 1 = short, 2 = long) */
231 0, /* bitsize */
232 FALSE, /* pc_relative */
233 0, /* bitpos */
234 complain_overflow_dont,/* complain_on_overflow */
235 bfd_elf_generic_reloc, /* special_function */
236 "R_MSP430_NONE", /* name */
237 FALSE, /* partial_inplace */
238 0, /* src_mask */
239 0, /* dst_mask */
240 FALSE), /* pcrel_offset */
241
242 HOWTO (R_MSP430_ABS32, /* type */
243 0, /* rightshift */
244 2, /* size (0 = byte, 1 = short, 2 = long) */
245 32, /* bitsize */
246 FALSE, /* pc_relative */
247 0, /* bitpos */
248 complain_overflow_bitfield,/* complain_on_overflow */
249 bfd_elf_generic_reloc, /* special_function */
250 "R_MSP430_ABS32", /* name */
251 FALSE, /* partial_inplace */
252 0xffffffff, /* src_mask */
253 0xffffffff, /* dst_mask */
254 FALSE), /* pcrel_offset */
255
256 HOWTO (R_MSP430_ABS16, /* type */
257 0, /* rightshift */
258 1, /* size (0 = byte, 1 = short, 2 = long) */
259 16, /* bitsize */
260 FALSE, /* pc_relative */
261 0, /* bitpos */
262 complain_overflow_dont,/* complain_on_overflow */
263 bfd_elf_generic_reloc, /* special_function */
264 "R_MSP430_ABS16", /* name */
265 FALSE, /* partial_inplace */
266 0, /* src_mask */
267 0xffff, /* dst_mask */
268 FALSE), /* pcrel_offset */
269
270 HOWTO (R_MSP430_ABS8, /* type */
271 0, /* rightshift */
272 0, /* size (0 = byte, 1 = short, 2 = long) */
273 8, /* bitsize */
274 FALSE, /* pc_relative */
275 0, /* bitpos */
276 complain_overflow_bitfield,/* complain_on_overflow */
277 bfd_elf_generic_reloc, /* special_function */
278 "R_MSP430_ABS8", /* name */
279 FALSE, /* partial_inplace */
280 0xff, /* src_mask */
281 0xff, /* dst_mask */
282 FALSE), /* pcrel_offset */
283
284 HOWTO (R_MSP430_PCR16, /* type */
285 1, /* rightshift */
286 1, /* size (0 = byte, 1 = short, 2 = long) */
287 16, /* bitsize */
288 TRUE, /* pc_relative */
289 0, /* bitpos */
290 complain_overflow_dont,/* complain_on_overflow */
291 bfd_elf_generic_reloc, /* special_function */
292 "R_MSP430_PCR16", /* name */
293 FALSE, /* partial_inplace */
294 0, /* src_mask */
295 0xffff, /* dst_mask */
296 TRUE), /* pcrel_offset */
297
298 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
299 0, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
301 32, /* bitsize */
302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_dont,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_MSP430X_PCR20_EXT_SRC",/* name */
307 FALSE, /* partial_inplace */
308 0, /* src_mask */
309 0xffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
313 0, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
315 32, /* bitsize */
316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_dont,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_MSP430X_PCR20_EXT_DST",/* name */
321 FALSE, /* partial_inplace */
322 0, /* src_mask */
323 0xffff, /* dst_mask */
324 TRUE), /* pcrel_offset */
325
326 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
327 0, /* rightshift */
328 2, /* size (0 = byte, 1 = short, 2 = long) */
329 32, /* bitsize */
330 TRUE, /* pc_relative */
331 0, /* bitpos */
332 complain_overflow_dont,/* complain_on_overflow */
333 bfd_elf_generic_reloc, /* special_function */
334 "R_MSP430X_PCR20_EXT_ODST",/* name */
335 FALSE, /* partial_inplace */
336 0, /* src_mask */
337 0xffff, /* dst_mask */
338 TRUE), /* pcrel_offset */
339
340 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
341 0, /* rightshift */
342 2, /* size (0 = byte, 1 = short, 2 = long) */
343 32, /* bitsize */
344 TRUE, /* pc_relative */
345 0, /* bitpos */
346 complain_overflow_dont,/* complain_on_overflow */
347 bfd_elf_generic_reloc, /* special_function */
348 "R_MSP430X_ABS20_EXT_SRC",/* name */
349 FALSE, /* partial_inplace */
350 0, /* src_mask */
351 0xffff, /* dst_mask */
352 TRUE), /* pcrel_offset */
353
354 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
355 0, /* rightshift */
356 2, /* size (0 = byte, 1 = short, 2 = long) */
357 32, /* bitsize */
358 TRUE, /* pc_relative */
359 0, /* bitpos */
360 complain_overflow_dont,/* complain_on_overflow */
361 bfd_elf_generic_reloc, /* special_function */
362 "R_MSP430X_ABS20_EXT_DST",/* name */
363 FALSE, /* partial_inplace */
364 0, /* src_mask */
365 0xffff, /* dst_mask */
366 TRUE), /* pcrel_offset */
367
368 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
369 0, /* rightshift */
370 2, /* size (0 = byte, 1 = short, 2 = long) */
371 32, /* bitsize */
372 TRUE, /* pc_relative */
373 0, /* bitpos */
374 complain_overflow_dont,/* complain_on_overflow */
375 bfd_elf_generic_reloc, /* special_function */
376 "R_MSP430X_ABS20_EXT_ODST",/* name */
377 FALSE, /* partial_inplace */
378 0, /* src_mask */
379 0xffff, /* dst_mask */
380 TRUE), /* pcrel_offset */
381
382 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
383 0, /* rightshift */
384 2, /* size (0 = byte, 1 = short, 2 = long) */
385 32, /* bitsize */
386 TRUE, /* pc_relative */
387 0, /* bitpos */
388 complain_overflow_dont,/* complain_on_overflow */
389 bfd_elf_generic_reloc, /* special_function */
390 "R_MSP430X_ABS20_ADR_SRC",/* name */
391 FALSE, /* partial_inplace */
392 0, /* src_mask */
393 0xffff, /* dst_mask */
394 TRUE), /* pcrel_offset */
395
396 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
397 0, /* rightshift */
398 2, /* size (0 = byte, 1 = short, 2 = long) */
399 32, /* bitsize */
400 TRUE, /* pc_relative */
401 0, /* bitpos */
402 complain_overflow_dont,/* complain_on_overflow */
403 bfd_elf_generic_reloc, /* special_function */
404 "R_MSP430X_ABS20_ADR_DST",/* name */
405 FALSE, /* partial_inplace */
406 0, /* src_mask */
407 0xffff, /* dst_mask */
408 TRUE), /* pcrel_offset */
409
410 HOWTO (R_MSP430X_PCR16, /* type */
411 0, /* rightshift */
412 2, /* size (0 = byte, 1 = short, 2 = long) */
413 32, /* bitsize */
414 TRUE, /* pc_relative */
415 0, /* bitpos */
416 complain_overflow_dont,/* complain_on_overflow */
417 bfd_elf_generic_reloc, /* special_function */
418 "R_MSP430X_PCR16", /* name */
419 FALSE, /* partial_inplace */
420 0, /* src_mask */
421 0xffff, /* dst_mask */
422 TRUE), /* pcrel_offset */
423
424 HOWTO (R_MSP430X_PCR20_CALL, /* type */
425 0, /* rightshift */
426 2, /* size (0 = byte, 1 = short, 2 = long) */
427 32, /* bitsize */
428 TRUE, /* pc_relative */
429 0, /* bitpos */
430 complain_overflow_dont,/* complain_on_overflow */
431 bfd_elf_generic_reloc, /* special_function */
432 "R_MSP430X_PCR20_CALL",/* name */
433 FALSE, /* partial_inplace */
434 0, /* src_mask */
435 0xffff, /* dst_mask */
436 TRUE), /* pcrel_offset */
437
438 HOWTO (R_MSP430X_ABS16, /* type */
439 0, /* rightshift */
440 2, /* size (0 = byte, 1 = short, 2 = long) */
441 32, /* bitsize */
442 TRUE, /* pc_relative */
443 0, /* bitpos */
444 complain_overflow_dont,/* complain_on_overflow */
445 bfd_elf_generic_reloc, /* special_function */
446 "R_MSP430X_ABS16", /* name */
447 FALSE, /* partial_inplace */
448 0, /* src_mask */
449 0xffff, /* dst_mask */
450 TRUE), /* pcrel_offset */
451
452 HOWTO (R_MSP430_ABS_HI16, /* type */
453 0, /* rightshift */
454 2, /* size (0 = byte, 1 = short, 2 = long) */
455 32, /* bitsize */
456 TRUE, /* pc_relative */
457 0, /* bitpos */
458 complain_overflow_dont,/* complain_on_overflow */
459 bfd_elf_generic_reloc, /* special_function */
460 "R_MSP430_ABS_HI16", /* name */
461 FALSE, /* partial_inplace */
462 0, /* src_mask */
463 0xffff, /* dst_mask */
464 TRUE), /* pcrel_offset */
465
466 HOWTO (R_MSP430_PREL31, /* type */
467 0, /* rightshift */
468 2, /* size (0 = byte, 1 = short, 2 = long) */
469 32, /* bitsize */
470 TRUE, /* pc_relative */
471 0, /* bitpos */
472 complain_overflow_dont,/* complain_on_overflow */
473 bfd_elf_generic_reloc, /* special_function */
474 "R_MSP430_PREL31", /* name */
475 FALSE, /* partial_inplace */
476 0, /* src_mask */
477 0xffff, /* dst_mask */
478 TRUE), /* pcrel_offset */
479
480 EMPTY_HOWTO (R_MSP430_EHTYPE),
481
482 /* A 10 bit PC relative relocation. */
483 HOWTO (R_MSP430X_10_PCREL, /* type */
484 1, /* rightshift */
485 1, /* size (0 = byte, 1 = short, 2 = long) */
486 10, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_bitfield,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_MSP430X_10_PCREL", /* name */
492 FALSE, /* partial_inplace */
493 0x3ff, /* src_mask */
494 0x3ff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 /* A 10 bit PC relative relocation for complicated polymorphs. */
498 HOWTO (R_MSP430X_2X_PCREL, /* type */
499 1, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 10, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_bitfield,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_MSP430X_2X_PCREL", /* name */
507 FALSE, /* partial_inplace */
508 0x3ff, /* src_mask */
509 0x3ff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
512 /* Together with a following reloc, allows for the difference
513 between two symbols to be the real addend of the second reloc. */
514 HOWTO (R_MSP430X_SYM_DIFF, /* type */
515 0, /* rightshift */
516 2, /* size (0 = byte, 1 = short, 2 = long) */
517 32, /* bitsize */
518 FALSE, /* pc_relative */
519 0, /* bitpos */
520 complain_overflow_dont,/* complain_on_overflow */
521 rl78_sym_diff_handler, /* special handler. */
522 "R_MSP430X_SYM_DIFF", /* name */
523 FALSE, /* partial_inplace */
524 0xffffffff, /* src_mask */
525 0xffffffff, /* dst_mask */
526 FALSE) /* pcrel_offset */
527 };
528
529 /* Map BFD reloc types to MSP430 ELF reloc types. */
530
531 struct msp430_reloc_map
532 {
533 bfd_reloc_code_real_type bfd_reloc_val;
534 unsigned int elf_reloc_val;
535 };
536
537 static const struct msp430_reloc_map msp430_reloc_map[] =
538 {
539 {BFD_RELOC_NONE, R_MSP430_NONE},
540 {BFD_RELOC_32, R_MSP430_32},
541 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
542 {BFD_RELOC_16, R_MSP430_16_BYTE},
543 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
544 {BFD_RELOC_MSP430_16, R_MSP430_16},
545 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
546 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
547 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
548 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
549 {BFD_RELOC_8, R_MSP430_8},
550 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
551 };
552
553 static const struct msp430_reloc_map msp430x_reloc_map[] =
554 {
555 {BFD_RELOC_NONE, R_MSP430_NONE},
556 {BFD_RELOC_32, R_MSP430_ABS32},
557 {BFD_RELOC_16, R_MSP430_ABS16},
558 {BFD_RELOC_8, R_MSP430_ABS8},
559 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
560 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
561 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
562 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
563 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
564 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
565 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
566 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
567 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
568 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
569 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
570 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
571 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
572 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
573 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
574 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
575 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
576 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
577 };
578
579 static inline bfd_boolean
580 uses_msp430x_relocs (bfd * abfd)
581 {
582 extern const bfd_target msp430_elf32_ti_vec;
583
584 return bfd_get_mach (abfd) == bfd_mach_msp430x
585 || abfd->xvec == & msp430_elf32_ti_vec;
586 }
587
588 static reloc_howto_type *
589 bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
590 bfd_reloc_code_real_type code)
591 {
592 unsigned int i;
593
594 if (uses_msp430x_relocs (abfd))
595 {
596 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
597 if (msp430x_reloc_map[i].bfd_reloc_val == code)
598 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
599 }
600 else
601 {
602 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
603 if (msp430_reloc_map[i].bfd_reloc_val == code)
604 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
605 }
606
607 return NULL;
608 }
609
610 static reloc_howto_type *
611 bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
612 const char *r_name)
613 {
614 unsigned int i;
615
616 if (uses_msp430x_relocs (abfd))
617 {
618 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
619 if (elf_msp430x_howto_table[i].name != NULL
620 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
621 return elf_msp430x_howto_table + i;
622 }
623 else
624 {
625 for (i = 0;
626 i < (sizeof (elf_msp430_howto_table)
627 / sizeof (elf_msp430_howto_table[0]));
628 i++)
629 if (elf_msp430_howto_table[i].name != NULL
630 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
631 return &elf_msp430_howto_table[i];
632 }
633
634 return NULL;
635 }
636
637 /* Set the howto pointer for an MSP430 ELF reloc. */
638
639 static bfd_boolean
640 msp430_info_to_howto_rela (bfd * abfd,
641 arelent * cache_ptr,
642 Elf_Internal_Rela * dst)
643 {
644 unsigned int r_type;
645
646 r_type = ELF32_R_TYPE (dst->r_info);
647
648 if (uses_msp430x_relocs (abfd))
649 {
650 if (r_type >= (unsigned int) R_MSP430x_max)
651 {
652 /* xgettext:c-format */
653 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
654 abfd, r_type);
655 bfd_set_error (bfd_error_bad_value);
656 return FALSE;
657 }
658 cache_ptr->howto = elf_msp430x_howto_table + r_type;
659 }
660 else if (r_type >= (unsigned int) R_MSP430_max)
661 {
662 /* xgettext:c-format */
663 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
664 abfd, r_type);
665 bfd_set_error (bfd_error_bad_value);
666 return FALSE;
667 }
668 else
669 cache_ptr->howto = &elf_msp430_howto_table[r_type];
670
671 return TRUE;
672 }
673
674 /* Look through the relocs for a section during the first phase.
675 Since we don't do .gots or .plts, we just need to consider the
676 virtual table relocs for gc. */
677
678 static bfd_boolean
679 elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
680 asection * sec, const Elf_Internal_Rela * relocs)
681 {
682 Elf_Internal_Shdr *symtab_hdr;
683 struct elf_link_hash_entry **sym_hashes;
684 const Elf_Internal_Rela *rel;
685 const Elf_Internal_Rela *rel_end;
686
687 if (bfd_link_relocatable (info))
688 return TRUE;
689
690 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
691 sym_hashes = elf_sym_hashes (abfd);
692
693 rel_end = relocs + sec->reloc_count;
694 for (rel = relocs; rel < rel_end; rel++)
695 {
696 struct elf_link_hash_entry *h;
697 unsigned long r_symndx;
698
699 r_symndx = ELF32_R_SYM (rel->r_info);
700 if (r_symndx < symtab_hdr->sh_info)
701 h = NULL;
702 else
703 {
704 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
705 while (h->root.type == bfd_link_hash_indirect
706 || h->root.type == bfd_link_hash_warning)
707 h = (struct elf_link_hash_entry *) h->root.u.i.link;
708 }
709 }
710
711 return TRUE;
712 }
713
714 /* Perform a single relocation. By default we use the standard BFD
715 routines, but a few relocs, we have to do them ourselves. */
716
717 static bfd_reloc_status_type
718 msp430_final_link_relocate (reloc_howto_type * howto,
719 bfd * input_bfd,
720 asection * input_section,
721 bfd_byte * contents,
722 Elf_Internal_Rela * rel,
723 bfd_vma relocation,
724 struct bfd_link_info * info)
725 {
726 static asection * sym_diff_section;
727 static bfd_vma sym_diff_value;
728
729 struct bfd_elf_section_data * esd = elf_section_data (input_section);
730 bfd_reloc_status_type r = bfd_reloc_ok;
731 bfd_vma x;
732 bfd_signed_vma srel;
733 bfd_boolean is_rel_reloc = FALSE;
734
735 if (uses_msp430x_relocs (input_bfd))
736 {
737 /* See if we have a REL type relocation. */
738 is_rel_reloc = (esd->rel.hdr != NULL);
739 /* Sanity check - only one type of relocation per section.
740 FIXME: Theoretically it is possible to have both types,
741 but if that happens how can we distinguish between the two ? */
742 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
743 /* If we are using a REL relocation then the addend should be empty. */
744 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
745 }
746
747 if (debug_relocs)
748 printf ("writing relocation (%p) at 0x%lx type: %d\n", rel,
749 (long) (input_section->output_section->vma + input_section->output_offset
750 + rel->r_offset), howto->type);
751 if (sym_diff_section != NULL)
752 {
753 BFD_ASSERT (sym_diff_section == input_section);
754
755 if (uses_msp430x_relocs (input_bfd))
756 switch (howto->type)
757 {
758 case R_MSP430_ABS32:
759 /* If we are computing a 32-bit value for the location lists
760 and the result is 0 then we add one to the value. A zero
761 value can result because of linker relaxation deleteing
762 prologue instructions and using a value of 1 (for the begin
763 and end offsets in the location list entry) results in a
764 nul entry which does not prevent the following entries from
765 being parsed. */
766 if (relocation == sym_diff_value
767 && strcmp (input_section->name, ".debug_loc") == 0)
768 ++ relocation;
769 /* Fall through. */
770 case R_MSP430_ABS16:
771 case R_MSP430X_ABS16:
772 case R_MSP430_ABS8:
773 BFD_ASSERT (! is_rel_reloc);
774 relocation -= sym_diff_value;
775 break;
776
777 default:
778 return bfd_reloc_dangerous;
779 }
780 else
781 switch (howto->type)
782 {
783 case R_MSP430_32:
784 case R_MSP430_16:
785 case R_MSP430_16_BYTE:
786 case R_MSP430_8:
787 relocation -= sym_diff_value;
788 break;
789
790 default:
791 return bfd_reloc_dangerous;
792 }
793
794 sym_diff_section = NULL;
795 }
796
797 if (uses_msp430x_relocs (input_bfd))
798 switch (howto->type)
799 {
800 case R_MSP430X_SYM_DIFF:
801 /* Cache the input section and value.
802 The offset is unreliable, since relaxation may
803 have reduced the following reloc's offset. */
804 BFD_ASSERT (! is_rel_reloc);
805 sym_diff_section = input_section;
806 sym_diff_value = relocation;
807 return bfd_reloc_ok;
808
809 case R_MSP430_ABS16:
810 contents += rel->r_offset;
811 srel = (bfd_signed_vma) relocation;
812 if (is_rel_reloc)
813 srel += bfd_get_16 (input_bfd, contents);
814 else
815 srel += rel->r_addend;
816 bfd_put_16 (input_bfd, srel & 0xffff, contents);
817 break;
818
819 case R_MSP430X_10_PCREL:
820 contents += rel->r_offset;
821 srel = (bfd_signed_vma) relocation;
822 if (is_rel_reloc)
823 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
824 else
825 srel += rel->r_addend;
826 srel -= rel->r_offset;
827 srel -= 2; /* Branch instructions add 2 to the PC... */
828 srel -= (input_section->output_section->vma +
829 input_section->output_offset);
830 if (srel & 1)
831 return bfd_reloc_outofrange;
832
833 /* MSP430 addresses commands as words. */
834 srel >>= 1;
835
836 /* Check for an overflow. */
837 if (srel < -512 || srel > 511)
838 {
839 if (info->disable_target_specific_optimizations < 0)
840 {
841 static bfd_boolean warned = FALSE;
842 if (! warned)
843 {
844 info->callbacks->warning
845 (info,
846 _("try enabling relaxation to avoid relocation truncations"),
847 NULL, input_bfd, input_section, relocation);
848 warned = TRUE;
849 }
850 }
851 return bfd_reloc_overflow;
852 }
853
854 x = bfd_get_16 (input_bfd, contents);
855 x = (x & 0xfc00) | (srel & 0x3ff);
856 bfd_put_16 (input_bfd, x, contents);
857 break;
858
859 case R_MSP430X_PCR20_EXT_ODST:
860 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
861 contents += rel->r_offset;
862 srel = (bfd_signed_vma) relocation;
863 if (is_rel_reloc)
864 {
865 bfd_vma addend;
866 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
867 addend |= bfd_get_16 (input_bfd, contents + 6);
868 srel += addend;
869
870 }
871 else
872 srel += rel->r_addend;
873 srel -= rel->r_offset;
874 srel -= (input_section->output_section->vma +
875 input_section->output_offset);
876 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
877 x = bfd_get_16 (input_bfd, contents);
878 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
879 bfd_put_16 (input_bfd, x, contents);
880 break;
881
882 case R_MSP430X_ABS20_EXT_SRC:
883 /* [7,4]+[32,16] = -78- ---- FFFF */
884 contents += rel->r_offset;
885 srel = (bfd_signed_vma) relocation;
886 if (is_rel_reloc)
887 {
888 bfd_vma addend;
889 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
890 addend |= bfd_get_16 (input_bfd, contents + 4);
891 srel += addend;
892 }
893 else
894 srel += rel->r_addend;
895 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
896 srel >>= 16;
897 x = bfd_get_16 (input_bfd, contents);
898 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
899 bfd_put_16 (input_bfd, x, contents);
900 break;
901
902 case R_MSP430_16_PCREL:
903 contents += rel->r_offset;
904 srel = (bfd_signed_vma) relocation;
905 if (is_rel_reloc)
906 srel += bfd_get_16 (input_bfd, contents);
907 else
908 srel += rel->r_addend;
909 srel -= rel->r_offset;
910 /* Only branch instructions add 2 to the PC... */
911 srel -= (input_section->output_section->vma +
912 input_section->output_offset);
913 if (srel & 1)
914 return bfd_reloc_outofrange;
915 bfd_put_16 (input_bfd, srel & 0xffff, contents);
916 break;
917
918 case R_MSP430X_PCR20_EXT_DST:
919 /* [0,4]+[32,16] = ---F ---- FFFF */
920 contents += rel->r_offset;
921 srel = (bfd_signed_vma) relocation;
922 if (is_rel_reloc)
923 {
924 bfd_vma addend;
925 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
926 addend |= bfd_get_16 (input_bfd, contents + 4);
927 srel += addend;
928 }
929 else
930 srel += rel->r_addend;
931 srel -= rel->r_offset;
932 srel -= (input_section->output_section->vma +
933 input_section->output_offset);
934 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
935 srel >>= 16;
936 x = bfd_get_16 (input_bfd, contents);
937 x = (x & 0xfff0) | (srel & 0xf);
938 bfd_put_16 (input_bfd, x, contents);
939 break;
940
941 case R_MSP430X_PCR20_EXT_SRC:
942 /* [7,4]+[32,16] = -78- ---- FFFF */
943 contents += rel->r_offset;
944 srel = (bfd_signed_vma) relocation;
945 if (is_rel_reloc)
946 {
947 bfd_vma addend;
948 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
949 addend |= bfd_get_16 (input_bfd, contents + 4);
950 srel += addend;;
951 }
952 else
953 srel += rel->r_addend;
954 srel -= rel->r_offset;
955 /* Only branch instructions add 2 to the PC... */
956 srel -= (input_section->output_section->vma +
957 input_section->output_offset);
958 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
959 srel >>= 16;
960 x = bfd_get_16 (input_bfd, contents);
961 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
962 bfd_put_16 (input_bfd, x, contents);
963 break;
964
965 case R_MSP430_ABS8:
966 contents += rel->r_offset;
967 srel = (bfd_signed_vma) relocation;
968 if (is_rel_reloc)
969 srel += bfd_get_8 (input_bfd, contents);
970 else
971 srel += rel->r_addend;
972 bfd_put_8 (input_bfd, srel & 0xff, contents);
973 break;
974
975 case R_MSP430X_ABS20_EXT_DST:
976 /* [0,4]+[32,16] = ---F ---- FFFF */
977 contents += rel->r_offset;
978 srel = (bfd_signed_vma) relocation;
979 if (is_rel_reloc)
980 {
981 bfd_vma addend;
982 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
983 addend |= bfd_get_16 (input_bfd, contents + 4);
984 srel += addend;
985 }
986 else
987 srel += rel->r_addend;
988 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
989 srel >>= 16;
990 x = bfd_get_16 (input_bfd, contents);
991 x = (x & 0xfff0) | (srel & 0xf);
992 bfd_put_16 (input_bfd, x, contents);
993 break;
994
995 case R_MSP430X_ABS20_EXT_ODST:
996 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
997 contents += rel->r_offset;
998 srel = (bfd_signed_vma) relocation;
999 if (is_rel_reloc)
1000 {
1001 bfd_vma addend;
1002 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
1003 addend |= bfd_get_16 (input_bfd, contents + 6);
1004 srel += addend;
1005 }
1006 else
1007 srel += rel->r_addend;
1008 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
1009 srel >>= 16;
1010 x = bfd_get_16 (input_bfd, contents);
1011 x = (x & 0xfff0) | (srel & 0xf);
1012 bfd_put_16 (input_bfd, x, contents);
1013 break;
1014
1015 case R_MSP430X_ABS20_ADR_SRC:
1016 /* [8,4]+[16,16] = -F-- FFFF */
1017 contents += rel->r_offset;
1018 srel = (bfd_signed_vma) relocation;
1019 if (is_rel_reloc)
1020 {
1021 bfd_vma addend;
1022
1023 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
1024 addend |= bfd_get_16 (input_bfd, contents + 2);
1025 srel += addend;
1026 }
1027 else
1028 srel += rel->r_addend;
1029 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1030 srel >>= 16;
1031 x = bfd_get_16 (input_bfd, contents);
1032 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
1033 bfd_put_16 (input_bfd, x, contents);
1034 break;
1035
1036 case R_MSP430X_ABS20_ADR_DST:
1037 /* [0,4]+[16,16] = ---F FFFF */
1038 contents += rel->r_offset;
1039 srel = (bfd_signed_vma) relocation;
1040 if (is_rel_reloc)
1041 {
1042 bfd_vma addend;
1043 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
1044 addend |= bfd_get_16 (input_bfd, contents + 2);
1045 srel += addend;
1046 }
1047 else
1048 srel += rel->r_addend;
1049 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1050 srel >>= 16;
1051 x = bfd_get_16 (input_bfd, contents);
1052 x = (x & 0xfff0) | (srel & 0xf);
1053 bfd_put_16 (input_bfd, x, contents);
1054 break;
1055
1056 case R_MSP430X_ABS16:
1057 contents += rel->r_offset;
1058 srel = (bfd_signed_vma) relocation;
1059 if (is_rel_reloc)
1060 srel += bfd_get_16 (input_bfd, contents);
1061 else
1062 srel += rel->r_addend;
1063 x = srel;
1064 if (x > 0xffff)
1065 return bfd_reloc_overflow;
1066 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1067 break;
1068
1069 case R_MSP430_ABS_HI16:
1070 /* The EABI specifies that this must be a RELA reloc. */
1071 BFD_ASSERT (! is_rel_reloc);
1072 contents += rel->r_offset;
1073 srel = (bfd_signed_vma) relocation;
1074 srel += rel->r_addend;
1075 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1076 break;
1077
1078 case R_MSP430X_PCR20_CALL:
1079 /* [0,4]+[16,16] = ---F FFFF*/
1080 contents += rel->r_offset;
1081 srel = (bfd_signed_vma) relocation;
1082 if (is_rel_reloc)
1083 {
1084 bfd_vma addend;
1085 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
1086 addend |= bfd_get_16 (input_bfd, contents + 2);
1087 srel += addend;
1088 }
1089 else
1090 srel += rel->r_addend;
1091 srel -= rel->r_offset;
1092 srel -= (input_section->output_section->vma +
1093 input_section->output_offset);
1094 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1095 srel >>= 16;
1096 x = bfd_get_16 (input_bfd, contents);
1097 x = (x & 0xfff0) | (srel & 0xf);
1098 bfd_put_16 (input_bfd, x, contents);
1099 break;
1100
1101 case R_MSP430X_PCR16:
1102 contents += rel->r_offset;
1103 srel = (bfd_signed_vma) relocation;
1104 if (is_rel_reloc)
1105 srel += bfd_get_16 (input_bfd, contents);
1106 else
1107 srel += rel->r_addend;
1108 srel -= rel->r_offset;
1109 srel -= (input_section->output_section->vma +
1110 input_section->output_offset);
1111 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1112 break;
1113
1114 case R_MSP430_PREL31:
1115 contents += rel->r_offset;
1116 srel = (bfd_signed_vma) relocation;
1117 if (is_rel_reloc)
1118 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1119 else
1120 srel += rel->r_addend;
1121 srel += rel->r_addend;
1122 x = bfd_get_32 (input_bfd, contents);
1123 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1124 bfd_put_32 (input_bfd, x, contents);
1125 break;
1126
1127 default:
1128 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1129 contents, rel->r_offset,
1130 relocation, rel->r_addend);
1131 }
1132 else
1133 switch (howto->type)
1134 {
1135 case R_MSP430_10_PCREL:
1136 contents += rel->r_offset;
1137 srel = (bfd_signed_vma) relocation;
1138 srel += rel->r_addend;
1139 srel -= rel->r_offset;
1140 srel -= 2; /* Branch instructions add 2 to the PC... */
1141 srel -= (input_section->output_section->vma +
1142 input_section->output_offset);
1143
1144 if (srel & 1)
1145 return bfd_reloc_outofrange;
1146
1147 /* MSP430 addresses commands as words. */
1148 srel >>= 1;
1149
1150 /* Check for an overflow. */
1151 if (srel < -512 || srel > 511)
1152 {
1153 if (info->disable_target_specific_optimizations < 0)
1154 {
1155 static bfd_boolean warned = FALSE;
1156 if (! warned)
1157 {
1158 info->callbacks->warning
1159 (info,
1160 _("try enabling relaxation to avoid relocation truncations"),
1161 NULL, input_bfd, input_section, relocation);
1162 warned = TRUE;
1163 }
1164 }
1165 return bfd_reloc_overflow;
1166 }
1167
1168 x = bfd_get_16 (input_bfd, contents);
1169 x = (x & 0xfc00) | (srel & 0x3ff);
1170 bfd_put_16 (input_bfd, x, contents);
1171 break;
1172
1173 case R_MSP430_2X_PCREL:
1174 contents += rel->r_offset;
1175 srel = (bfd_signed_vma) relocation;
1176 srel += rel->r_addend;
1177 srel -= rel->r_offset;
1178 srel -= 2; /* Branch instructions add 2 to the PC... */
1179 srel -= (input_section->output_section->vma +
1180 input_section->output_offset);
1181
1182 if (srel & 1)
1183 return bfd_reloc_outofrange;
1184
1185 /* MSP430 addresses commands as words. */
1186 srel >>= 1;
1187
1188 /* Check for an overflow. */
1189 if (srel < -512 || srel > 511)
1190 return bfd_reloc_overflow;
1191
1192 x = bfd_get_16 (input_bfd, contents);
1193 x = (x & 0xfc00) | (srel & 0x3ff);
1194 bfd_put_16 (input_bfd, x, contents);
1195 /* Handle second jump instruction. */
1196 x = bfd_get_16 (input_bfd, contents - 2);
1197 srel += 1;
1198 x = (x & 0xfc00) | (srel & 0x3ff);
1199 bfd_put_16 (input_bfd, x, contents - 2);
1200 break;
1201
1202 case R_MSP430_RL_PCREL:
1203 case R_MSP430_16_PCREL:
1204 contents += rel->r_offset;
1205 srel = (bfd_signed_vma) relocation;
1206 srel += rel->r_addend;
1207 srel -= rel->r_offset;
1208 /* Only branch instructions add 2 to the PC... */
1209 srel -= (input_section->output_section->vma +
1210 input_section->output_offset);
1211
1212 if (srel & 1)
1213 return bfd_reloc_outofrange;
1214
1215 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1216 break;
1217
1218 case R_MSP430_16_PCREL_BYTE:
1219 contents += rel->r_offset;
1220 srel = (bfd_signed_vma) relocation;
1221 srel += rel->r_addend;
1222 srel -= rel->r_offset;
1223 /* Only branch instructions add 2 to the PC... */
1224 srel -= (input_section->output_section->vma +
1225 input_section->output_offset);
1226
1227 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1228 break;
1229
1230 case R_MSP430_16_BYTE:
1231 contents += rel->r_offset;
1232 srel = (bfd_signed_vma) relocation;
1233 srel += rel->r_addend;
1234 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1235 break;
1236
1237 case R_MSP430_16:
1238 contents += rel->r_offset;
1239 srel = (bfd_signed_vma) relocation;
1240 srel += rel->r_addend;
1241
1242 if (srel & 1)
1243 return bfd_reloc_notsupported;
1244
1245 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1246 break;
1247
1248 case R_MSP430_8:
1249 contents += rel->r_offset;
1250 srel = (bfd_signed_vma) relocation;
1251 srel += rel->r_addend;
1252
1253 bfd_put_8 (input_bfd, srel & 0xff, contents);
1254 break;
1255
1256 case R_MSP430_SYM_DIFF:
1257 /* Cache the input section and value.
1258 The offset is unreliable, since relaxation may
1259 have reduced the following reloc's offset. */
1260 sym_diff_section = input_section;
1261 sym_diff_value = relocation;
1262 return bfd_reloc_ok;
1263
1264 default:
1265 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1266 contents, rel->r_offset,
1267 relocation, rel->r_addend);
1268 }
1269
1270 return r;
1271 }
1272
1273 /* Relocate an MSP430 ELF section. */
1274
1275 static bfd_boolean
1276 elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1277 struct bfd_link_info * info,
1278 bfd * input_bfd,
1279 asection * input_section,
1280 bfd_byte * contents,
1281 Elf_Internal_Rela * relocs,
1282 Elf_Internal_Sym * local_syms,
1283 asection ** local_sections)
1284 {
1285 Elf_Internal_Shdr *symtab_hdr;
1286 struct elf_link_hash_entry **sym_hashes;
1287 Elf_Internal_Rela *rel;
1288 Elf_Internal_Rela *relend;
1289
1290 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1291 sym_hashes = elf_sym_hashes (input_bfd);
1292 relend = relocs + input_section->reloc_count;
1293
1294 for (rel = relocs; rel < relend; rel++)
1295 {
1296 reloc_howto_type *howto;
1297 unsigned long r_symndx;
1298 Elf_Internal_Sym *sym;
1299 asection *sec;
1300 struct elf_link_hash_entry *h;
1301 bfd_vma relocation;
1302 bfd_reloc_status_type r;
1303 const char *name = NULL;
1304 int r_type;
1305
1306 r_type = ELF32_R_TYPE (rel->r_info);
1307 r_symndx = ELF32_R_SYM (rel->r_info);
1308
1309 if (uses_msp430x_relocs (input_bfd))
1310 howto = elf_msp430x_howto_table + r_type;
1311 else
1312 howto = elf_msp430_howto_table + r_type;
1313
1314 h = NULL;
1315 sym = NULL;
1316 sec = NULL;
1317
1318 if (r_symndx < symtab_hdr->sh_info)
1319 {
1320 sym = local_syms + r_symndx;
1321 sec = local_sections[r_symndx];
1322 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
1323
1324 name = bfd_elf_string_from_elf_section
1325 (input_bfd, symtab_hdr->sh_link, sym->st_name);
1326 name = name == NULL || *name == 0 ? bfd_section_name (sec) : name;
1327 }
1328 else
1329 {
1330 bfd_boolean unresolved_reloc, warned, ignored;
1331
1332 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1333 r_symndx, symtab_hdr, sym_hashes,
1334 h, sec, relocation,
1335 unresolved_reloc, warned, ignored);
1336 name = h->root.root.string;
1337 }
1338
1339 if (sec != NULL && discarded_section (sec))
1340 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
1341 rel, 1, relend, howto, 0, contents);
1342
1343 if (bfd_link_relocatable (info))
1344 continue;
1345
1346 r = msp430_final_link_relocate (howto, input_bfd, input_section,
1347 contents, rel, relocation, info);
1348
1349 if (r != bfd_reloc_ok)
1350 {
1351 const char *msg = (const char *) NULL;
1352
1353 switch (r)
1354 {
1355 case bfd_reloc_overflow:
1356 (*info->callbacks->reloc_overflow)
1357 (info, (h ? &h->root : NULL), name, howto->name,
1358 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
1359 break;
1360
1361 case bfd_reloc_undefined:
1362 (*info->callbacks->undefined_symbol)
1363 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
1364 break;
1365
1366 case bfd_reloc_outofrange:
1367 msg = _("internal error: branch/jump to an odd address detected");
1368 break;
1369
1370 case bfd_reloc_notsupported:
1371 msg = _("internal error: unsupported relocation error");
1372 break;
1373
1374 case bfd_reloc_dangerous:
1375 msg = _("internal error: dangerous relocation");
1376 break;
1377
1378 default:
1379 msg = _("internal error: unknown error");
1380 break;
1381 }
1382
1383 if (msg)
1384 (*info->callbacks->warning) (info, msg, name, input_bfd,
1385 input_section, rel->r_offset);
1386 }
1387
1388 }
1389
1390 return TRUE;
1391 }
1392
1393 /* The final processing done just before writing out a MSP430 ELF object
1394 file. This gets the MSP430 architecture right based on the machine
1395 number. */
1396
1397 static bfd_boolean
1398 bfd_elf_msp430_final_write_processing (bfd *abfd)
1399 {
1400 unsigned long val;
1401
1402 switch (bfd_get_mach (abfd))
1403 {
1404 default:
1405 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1406 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1407 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1408 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1409 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1410 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1411 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1412 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1413 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1414 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1415 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1416 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1417 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1418 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1419 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1420 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1421 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1422 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1423 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1424 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1425 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1426 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1427 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
1428 }
1429
1430 elf_elfheader (abfd)->e_machine = EM_MSP430;
1431 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1432 elf_elfheader (abfd)->e_flags |= val;
1433 return _bfd_elf_final_write_processing (abfd);
1434 }
1435
1436 /* Set the right machine number. */
1437
1438 static bfd_boolean
1439 elf32_msp430_object_p (bfd * abfd)
1440 {
1441 int e_set = bfd_mach_msp14;
1442
1443 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1444 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1445 {
1446 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1447
1448 switch (e_mach)
1449 {
1450 default:
1451 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1452 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1453 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1454 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1455 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1456 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1457 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1458 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1459 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1460 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1461 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1462 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1463 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1464 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1465 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1466 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1467 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1468 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1469 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1470 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1471 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1472 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1473 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
1474 }
1475 }
1476
1477 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1478 }
1479
1480 /* These functions handle relaxing for the msp430.
1481 Relaxation required only in two cases:
1482 - Bad hand coding like jumps from one section to another or
1483 from file to file.
1484 - Sibling calls. This will affect only 'jump label' polymorph. Without
1485 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1486 do not work in gcc's port by the reason I do not know.
1487 - To convert out of range conditional jump instructions (found inside
1488 a function) into inverted jumps over an unconditional branch instruction.
1489 Anyway, if a relaxation required, user should pass -relax option to the
1490 linker.
1491
1492 There are quite a few relaxing opportunities available on the msp430:
1493
1494 ================================================================
1495
1496 1. 3 words -> 1 word
1497
1498 eq == jeq label jne +4; br lab
1499 ne != jne label jeq +4; br lab
1500 lt < jl label jge +4; br lab
1501 ltu < jlo label lhs +4; br lab
1502 ge >= jge label jl +4; br lab
1503 geu >= jhs label jlo +4; br lab
1504
1505 2. 4 words -> 1 word
1506
1507 ltn < jn jn +2; jmp +4; br lab
1508
1509 3. 4 words -> 2 words
1510
1511 gt > jeq +2; jge label jeq +6; jl +4; br label
1512 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
1513
1514 4. 4 words -> 2 words and 2 labels
1515
1516 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1517 le <= jeq label; jl label jeq +2; jge +4; br label
1518 =================================================================
1519
1520 codemap for first cases is (labels masked ):
1521 eq: 0x2002,0x4010,0x0000 -> 0x2400
1522 ne: 0x2402,0x4010,0x0000 -> 0x2000
1523 lt: 0x3402,0x4010,0x0000 -> 0x3800
1524 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1525 ge: 0x3802,0x4010,0x0000 -> 0x3400
1526 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1527
1528 second case:
1529 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1530
1531 third case:
1532 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1533 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1534
1535 fourth case:
1536 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1537 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1538
1539 Unspecified case :)
1540 jump: 0x4010,0x0000 -> 0x3c00. */
1541
1542 #define NUMB_RELAX_CODES 12
1543 static struct rcodes_s
1544 {
1545 int f0, f1; /* From code. */
1546 int t0, t1; /* To code. */
1547 int labels; /* Position of labels: 1 - one label at first
1548 word, 2 - one at second word, 3 - two
1549 labels at both. */
1550 int cdx; /* Words to match. */
1551 int bs; /* Shrink bytes. */
1552 int off; /* Offset from old label for new code. */
1553 int ncl; /* New code length. */
1554 } rcode[] =
1555 {/* lab,cdx,bs,off,ncl */
1556 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1557 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1558 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1559 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1560 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1561 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1562 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1563 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1564 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1565 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1566 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1567 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
1568 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
1569 };
1570
1571 /* Return TRUE if a symbol exists at the given address. */
1572
1573 static bfd_boolean
1574 msp430_elf_symbol_address_p (bfd * abfd,
1575 asection * sec,
1576 Elf_Internal_Sym * isym,
1577 bfd_vma addr)
1578 {
1579 Elf_Internal_Shdr *symtab_hdr;
1580 unsigned int sec_shndx;
1581 Elf_Internal_Sym *isymend;
1582 struct elf_link_hash_entry **sym_hashes;
1583 struct elf_link_hash_entry **end_hashes;
1584 unsigned int symcount;
1585
1586 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1587
1588 /* Examine all the local symbols. */
1589 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1590 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1591 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1592 return TRUE;
1593
1594 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1595 - symtab_hdr->sh_info);
1596 sym_hashes = elf_sym_hashes (abfd);
1597 end_hashes = sym_hashes + symcount;
1598 for (; sym_hashes < end_hashes; sym_hashes++)
1599 {
1600 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1601
1602 if ((sym_hash->root.type == bfd_link_hash_defined
1603 || sym_hash->root.type == bfd_link_hash_defweak)
1604 && sym_hash->root.u.def.section == sec
1605 && sym_hash->root.u.def.value == addr)
1606 return TRUE;
1607 }
1608
1609 return FALSE;
1610 }
1611
1612 /* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1613 sec_shndx) referenced from current and other sections. */
1614
1615 static bfd_boolean
1616 msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1617 int count, unsigned int sec_shndx,
1618 bfd_vma toaddr)
1619 {
1620 Elf_Internal_Shdr *symtab_hdr;
1621 Elf_Internal_Rela *irel;
1622 Elf_Internal_Rela *irelend;
1623 Elf_Internal_Sym *isym;
1624
1625 irel = elf_section_data (sec)->relocs;
1626 if (irel == NULL)
1627 return TRUE;
1628
1629 irelend = irel + sec->reloc_count;
1630 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1631 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1632
1633 for (;irel < irelend; irel++)
1634 {
1635 unsigned int sidx = ELF32_R_SYM(irel->r_info);
1636 Elf_Internal_Sym *lsym = isym + sidx;
1637
1638 /* Adjust symbols referenced by .sec+0xXX. */
1639 if (irel->r_addend > addr && irel->r_addend < toaddr
1640 && sidx < symtab_hdr->sh_info
1641 && lsym->st_shndx == sec_shndx)
1642 irel->r_addend -= count;
1643 }
1644
1645 return TRUE;
1646 }
1647
1648 /* Delete some bytes from a section while relaxing. */
1649
1650 static bfd_boolean
1651 msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1652 int count)
1653 {
1654 Elf_Internal_Shdr *symtab_hdr;
1655 unsigned int sec_shndx;
1656 bfd_byte *contents;
1657 Elf_Internal_Rela *irel;
1658 Elf_Internal_Rela *irelend;
1659 bfd_vma toaddr;
1660 Elf_Internal_Sym *isym;
1661 Elf_Internal_Sym *isymend;
1662 struct elf_link_hash_entry **sym_hashes;
1663 struct elf_link_hash_entry **end_hashes;
1664 unsigned int symcount;
1665 asection *p;
1666
1667 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1668
1669 contents = elf_section_data (sec)->this_hdr.contents;
1670
1671 toaddr = sec->size;
1672 if (debug_relocs)
1673 printf (" deleting %d bytes between 0x%lx to 0x%lx\n",
1674 count, (long) addr, (long) toaddr);
1675
1676 irel = elf_section_data (sec)->relocs;
1677 irelend = irel + sec->reloc_count;
1678
1679 /* Actually delete the bytes. */
1680 memmove (contents + addr, contents + addr + count,
1681 (size_t) (toaddr - addr - count));
1682 sec->size -= count;
1683
1684 /* Adjust all the relocs. */
1685 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1686 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1687 for (; irel < irelend; irel++)
1688 {
1689 /* Get the new reloc address. */
1690 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1691 irel->r_offset -= count;
1692 }
1693
1694 for (p = abfd->sections; p != NULL; p = p->next)
1695 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1696
1697 /* Adjust the local symbols defined in this section. */
1698 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1699 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1700 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1701 {
1702 const char * name;
1703
1704 name = bfd_elf_string_from_elf_section
1705 (abfd, symtab_hdr->sh_link, isym->st_name);
1706 name = name == NULL || *name == 0 ? bfd_section_name (sec) : name;
1707
1708 if (isym->st_shndx != sec_shndx)
1709 continue;
1710
1711 if (isym->st_value > addr
1712 && (isym->st_value < toaddr
1713 /* We also adjust a symbol at the end of the section if its name is
1714 on the list below. These symbols are used for debug info
1715 generation and they refer to the end of the current section, not
1716 the start of the next section. */
1717 || (isym->st_value == toaddr
1718 && name != NULL
1719 && (CONST_STRNEQ (name, ".Letext")
1720 || CONST_STRNEQ (name, ".LFE")))))
1721 {
1722 if (debug_relocs)
1723 printf (" adjusting value of local symbol %s from 0x%lx ",
1724 name, (long) isym->st_value);
1725 if (isym->st_value < addr + count)
1726 isym->st_value = addr;
1727 else
1728 isym->st_value -= count;
1729 if (debug_relocs)
1730 printf ("to 0x%lx\n", (long) isym->st_value);
1731 }
1732 /* Adjust the function symbol's size as well. */
1733 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1734 && isym->st_value + isym->st_size > addr
1735 && isym->st_value + isym->st_size < toaddr)
1736 isym->st_size -= count;
1737 }
1738
1739 /* Now adjust the global symbols defined in this section. */
1740 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1741 - symtab_hdr->sh_info);
1742 sym_hashes = elf_sym_hashes (abfd);
1743 end_hashes = sym_hashes + symcount;
1744 for (; sym_hashes < end_hashes; sym_hashes++)
1745 {
1746 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1747
1748 if ((sym_hash->root.type == bfd_link_hash_defined
1749 || sym_hash->root.type == bfd_link_hash_defweak)
1750 && sym_hash->root.u.def.section == sec
1751 && sym_hash->root.u.def.value > addr
1752 && sym_hash->root.u.def.value < toaddr)
1753 {
1754 if (sym_hash->root.u.def.value < addr + count)
1755 sym_hash->root.u.def.value = addr;
1756 else
1757 sym_hash->root.u.def.value -= count;
1758 }
1759 /* Adjust the function symbol's size as well. */
1760 else if (sym_hash->root.type == bfd_link_hash_defined
1761 && sym_hash->root.u.def.section == sec
1762 && sym_hash->type == STT_FUNC
1763 && sym_hash->root.u.def.value + sym_hash->size > addr
1764 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1765 sym_hash->size -= count;
1766 }
1767
1768 return TRUE;
1769 }
1770
1771 /* Insert one or two words into a section whilst relaxing. */
1772
1773 static bfd_byte *
1774 msp430_elf_relax_add_words (bfd * abfd, asection * sec, bfd_vma addr,
1775 int num_words, int word1, int word2)
1776 {
1777 Elf_Internal_Shdr *symtab_hdr;
1778 unsigned int sec_shndx;
1779 bfd_byte *contents;
1780 Elf_Internal_Rela *irel;
1781 Elf_Internal_Rela *irelend;
1782 Elf_Internal_Sym *isym;
1783 Elf_Internal_Sym *isymend;
1784 struct elf_link_hash_entry **sym_hashes;
1785 struct elf_link_hash_entry **end_hashes;
1786 unsigned int symcount;
1787 bfd_vma sec_end;
1788 asection *p;
1789 if (debug_relocs)
1790 printf (" adding %d words at 0x%lx\n", num_words,
1791 (long) (sec->output_section->vma + sec->output_offset + addr));
1792
1793 contents = elf_section_data (sec)->this_hdr.contents;
1794 sec_end = sec->size;
1795 int num_bytes = num_words * 2;
1796
1797 /* Make space for the new words. */
1798 contents = bfd_realloc (contents, sec_end + num_bytes);
1799 memmove (contents + addr + num_bytes, contents + addr, sec_end - addr);
1800
1801 /* Insert the new words. */
1802 bfd_put_16 (abfd, word1, contents + addr);
1803 if (num_words == 2)
1804 bfd_put_16 (abfd, word2, contents + addr + 2);
1805
1806 /* Update the section information. */
1807 sec->size += num_bytes;
1808 elf_section_data (sec)->this_hdr.contents = contents;
1809
1810 /* Adjust all the relocs. */
1811 irel = elf_section_data (sec)->relocs;
1812 irelend = irel + sec->reloc_count;
1813
1814 for (; irel < irelend; irel++)
1815 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1816 irel->r_offset += num_bytes;
1817
1818 /* Adjust the local symbols defined in this section. */
1819 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1820 for (p = abfd->sections; p != NULL; p = p->next)
1821 msp430_elf_relax_adjust_locals (abfd, p, addr, -num_bytes,
1822 sec_shndx, sec_end);
1823
1824 /* Adjust the global symbols affected by the move. */
1825 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1826 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1827 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1828 if (isym->st_shndx == sec_shndx
1829 && isym->st_value >= addr && isym->st_value < sec_end)
1830 {
1831 if (debug_relocs)
1832 printf (" adjusting value of local symbol %s from 0x%lx to "
1833 "0x%lx\n", bfd_elf_string_from_elf_section
1834 (abfd, symtab_hdr->sh_link, isym->st_name),
1835 (long) isym->st_value, (long)(isym->st_value + num_bytes));
1836 isym->st_value += num_bytes;
1837 }
1838
1839 /* Now adjust the global symbols defined in this section. */
1840 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1841 - symtab_hdr->sh_info);
1842 sym_hashes = elf_sym_hashes (abfd);
1843 end_hashes = sym_hashes + symcount;
1844 for (; sym_hashes < end_hashes; sym_hashes++)
1845 {
1846 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1847
1848 if ((sym_hash->root.type == bfd_link_hash_defined
1849 || sym_hash->root.type == bfd_link_hash_defweak)
1850 && sym_hash->root.u.def.section == sec
1851 && sym_hash->root.u.def.value >= addr
1852 && sym_hash->root.u.def.value < sec_end)
1853 sym_hash->root.u.def.value += num_bytes;
1854 }
1855
1856 return contents;
1857 }
1858
1859 static bfd_boolean
1860 msp430_elf_relax_section (bfd * abfd, asection * sec,
1861 struct bfd_link_info * link_info,
1862 bfd_boolean * again)
1863 {
1864 Elf_Internal_Shdr * symtab_hdr;
1865 Elf_Internal_Rela * internal_relocs;
1866 Elf_Internal_Rela * irel;
1867 Elf_Internal_Rela * irelend;
1868 bfd_byte * contents = NULL;
1869 Elf_Internal_Sym * isymbuf = NULL;
1870
1871 /* Assume nothing changes. */
1872 *again = FALSE;
1873
1874 /* We don't have to do anything for a relocatable link, if
1875 this section does not have relocs, or if this is not a
1876 code section. */
1877 if (bfd_link_relocatable (link_info)
1878 || (sec->flags & SEC_RELOC) == 0
1879 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
1880 return TRUE;
1881
1882 if (debug_relocs)
1883 printf ("Relaxing %s (%p), output_offset: 0x%lx sec size: 0x%lx\n",
1884 sec->name, sec, (long) sec->output_offset, (long) sec->size);
1885
1886 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1887
1888 /* Get a copy of the native relocations. */
1889 internal_relocs =
1890 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1891 if (internal_relocs == NULL)
1892 goto error_return;
1893
1894 /* Walk through them looking for relaxing opportunities. */
1895 irelend = internal_relocs + sec->reloc_count;
1896
1897 if (debug_relocs)
1898 printf (" trying code size growing relocs\n");
1899 /* Do code size growing relocs first. */
1900 for (irel = internal_relocs; irel < irelend; irel++)
1901 {
1902 bfd_vma symval;
1903
1904 /* If this isn't something that can be relaxed, then ignore
1905 this reloc. */
1906 if (uses_msp430x_relocs (abfd)
1907 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
1908 ;
1909 else if (! uses_msp430x_relocs (abfd)
1910 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
1911 ;
1912 else
1913 continue;
1914
1915 /* Get the section contents if we haven't done so already. */
1916 if (contents == NULL)
1917 {
1918 /* Get cached copy if it exists. */
1919 if (elf_section_data (sec)->this_hdr.contents != NULL)
1920 contents = elf_section_data (sec)->this_hdr.contents;
1921 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1922 goto error_return;
1923 }
1924
1925 /* Read this BFD's local symbols if we haven't done so already. */
1926 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1927 {
1928 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1929 if (isymbuf == NULL)
1930 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1931 symtab_hdr->sh_info, 0,
1932 NULL, NULL, NULL);
1933 if (isymbuf == NULL)
1934 goto error_return;
1935 }
1936
1937 /* Get the value of the symbol referred to by the reloc. */
1938 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1939 {
1940 /* A local symbol. */
1941 Elf_Internal_Sym *isym;
1942 asection *sym_sec;
1943
1944 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1945 if (isym->st_shndx == SHN_UNDEF)
1946 sym_sec = bfd_und_section_ptr;
1947 else if (isym->st_shndx == SHN_ABS)
1948 sym_sec = bfd_abs_section_ptr;
1949 else if (isym->st_shndx == SHN_COMMON)
1950 sym_sec = bfd_com_section_ptr;
1951 else
1952 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1953 symval = (isym->st_value
1954 + sym_sec->output_section->vma + sym_sec->output_offset);
1955
1956 if (debug_relocs)
1957 printf (" processing reloc at 0x%lx for local sym: %s "
1958 "st_value: 0x%lx adj value: 0x%lx\n",
1959 (long) (sec->output_offset + sec->output_section->vma
1960 + irel->r_offset),
1961 bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link,
1962 isym->st_name),
1963 (long) isym->st_value, (long) symval);
1964 }
1965 else
1966 {
1967 unsigned long indx;
1968 struct elf_link_hash_entry *h;
1969
1970 /* An external symbol. */
1971 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1972 h = elf_sym_hashes (abfd)[indx];
1973 BFD_ASSERT (h != NULL);
1974
1975 if (h->root.type != bfd_link_hash_defined
1976 && h->root.type != bfd_link_hash_defweak)
1977 /* This appears to be a reference to an undefined
1978 symbol. Just ignore it--it will be caught by the
1979 regular reloc processing. */
1980 continue;
1981
1982 symval = (h->root.u.def.value
1983 + h->root.u.def.section->output_section->vma
1984 + h->root.u.def.section->output_offset);
1985 if (debug_relocs)
1986 printf (" processing reloc at 0x%lx for global sym: %s "
1987 "st_value: 0x%lx adj value: 0x%lx\n",
1988 (long) (sec->output_offset + sec->output_section->vma
1989 + irel->r_offset),
1990 h->root.root.string, (long) h->root.u.def.value,
1991 (long) symval);
1992 }
1993
1994 /* For simplicity of coding, we are going to modify the section
1995 contents, the section relocs, and the BFD symbol table. We
1996 must tell the rest of the code not to free up this
1997 information. It would be possible to instead create a table
1998 of changes which have to be made, as is done in coff-mips.c;
1999 that would be more work, but would require less memory when
2000 the linker is run. */
2001
2002 bfd_signed_vma value = symval;
2003 int opcode;
2004
2005 /* Compute the value that will be relocated. */
2006 value += irel->r_addend;
2007 /* Convert to PC relative. */
2008 value -= (sec->output_section->vma + sec->output_offset);
2009 value -= irel->r_offset;
2010 value -= 2;
2011
2012 /* Scale. */
2013 value >>= 1;
2014
2015 /* If it is in range then no modifications are needed. */
2016 if (value >= -512 && value <= 511)
2017 continue;
2018
2019 /* Get the opcode. */
2020 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
2021
2022 /* Compute the new opcode. We are going to convert:
2023 JMP label
2024 into:
2025 BR[A] label
2026 or
2027 J<cond> label
2028 into:
2029 J<inv-cond> 1f
2030 BR[A] #label
2031 1: */
2032 switch (opcode & 0xfc00)
2033 {
2034 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
2035 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
2036 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
2037 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
2038 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
2039 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
2040 case 0x3000: /* jn */
2041 /* There is no direct inverse of the Jn insn.
2042 FIXME: we could do this as:
2043 Jn 1f
2044 br 2f
2045 1: br label
2046 2: */
2047 continue;
2048 case 0x3c00:
2049 if (uses_msp430x_relocs (abfd))
2050 opcode = 0x0080; /* JMP -> BRA */
2051 else
2052 opcode = 0x4030; /* JMP -> BR */
2053 break;
2054 default:
2055 /* Unhandled branch instruction. */
2056 /* fprintf (stderr, "unrecog: %x\n", opcode); */
2057 continue;
2058 }
2059
2060 /* Note that we've changed the relocs, section contents, etc. */
2061 elf_section_data (sec)->relocs = internal_relocs;
2062 elf_section_data (sec)->this_hdr.contents = contents;
2063 symtab_hdr->contents = (unsigned char *) isymbuf;
2064
2065 /* Install the new opcode. */
2066 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
2067
2068 /* Insert the new branch instruction. */
2069 if (uses_msp430x_relocs (abfd))
2070 {
2071 if (debug_relocs)
2072 printf (" R_MSP430X_10_PCREL -> R_MSP430X_ABS20_ADR_SRC "
2073 "(growing with new opcode 0x%x)\n", opcode);
2074
2075 /* Insert an absolute branch (aka MOVA) instruction.
2076 Note that bits 19:16 of the address are stored in the first word
2077 of the insn, so this is where r_offset will point to. */
2078 if (opcode == 0x0080)
2079 {
2080 /* If we're inserting a BRA because we are converting from a JMP,
2081 then only add one word for destination address; the BRA opcode
2082 has already been written. */
2083 contents = msp430_elf_relax_add_words
2084 (abfd, sec, irel->r_offset + 2, 1, 0x0000, 0);
2085 }
2086 else
2087 {
2088 contents = msp430_elf_relax_add_words
2089 (abfd, sec, irel->r_offset + 2, 2, 0x0080, 0x0000);
2090 /* Update the relocation to point to the inserted branch
2091 instruction. Note - we are changing a PC-relative reloc
2092 into an absolute reloc, but this is OK because we have
2093 arranged with the assembler to have the reloc's value be
2094 a (local) symbol, not a section+offset value. */
2095 irel->r_offset += 2;
2096 }
2097
2098 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2099 R_MSP430X_ABS20_ADR_SRC);
2100 }
2101 else
2102 {
2103 if (debug_relocs)
2104 printf (" R_MSP430_10_PCREL -> R_MSP430_16 "
2105 "(growing with new opcode 0x%x)\n", opcode);
2106 if (opcode == 0x4030)
2107 {
2108 /* If we're inserting a BR because we are converting from a JMP,
2109 then only add one word for destination address; the BR opcode
2110 has already been written. */
2111 contents = msp430_elf_relax_add_words
2112 (abfd, sec, irel->r_offset + 2, 1, 0x0000, 0);
2113 irel->r_offset += 2;
2114 }
2115 else
2116 {
2117 contents = msp430_elf_relax_add_words
2118 (abfd, sec, irel->r_offset + 2, 2, 0x4030, 0x0000);
2119 /* See comment above about converting a 10-bit PC-rel
2120 relocation into a 16-bit absolute relocation. */
2121 irel->r_offset += 4;
2122 }
2123 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2124 R_MSP430_16);
2125 }
2126
2127 /* Growing the section may mean that other
2128 conditional branches need to be fixed. */
2129 *again = TRUE;
2130 }
2131
2132 if (debug_relocs)
2133 printf (" trying code size shrinking relocs\n");
2134
2135 for (irel = internal_relocs; irel < irelend; irel++)
2136 {
2137 bfd_vma symval;
2138
2139 /* Get the section contents if we haven't done so already. */
2140 if (contents == NULL)
2141 {
2142 /* Get cached copy if it exists. */
2143 if (elf_section_data (sec)->this_hdr.contents != NULL)
2144 contents = elf_section_data (sec)->this_hdr.contents;
2145 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2146 goto error_return;
2147 }
2148
2149 /* Read this BFD's local symbols if we haven't done so already. */
2150 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2151 {
2152 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2153 if (isymbuf == NULL)
2154 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2155 symtab_hdr->sh_info, 0,
2156 NULL, NULL, NULL);
2157 if (isymbuf == NULL)
2158 goto error_return;
2159 }
2160
2161 /* Get the value of the symbol referred to by the reloc. */
2162 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2163 {
2164 /* A local symbol. */
2165 Elf_Internal_Sym *isym;
2166 asection *sym_sec;
2167
2168 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2169 if (isym->st_shndx == SHN_UNDEF)
2170 sym_sec = bfd_und_section_ptr;
2171 else if (isym->st_shndx == SHN_ABS)
2172 sym_sec = bfd_abs_section_ptr;
2173 else if (isym->st_shndx == SHN_COMMON)
2174 sym_sec = bfd_com_section_ptr;
2175 else
2176 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2177 symval = (isym->st_value
2178 + sym_sec->output_section->vma + sym_sec->output_offset);
2179
2180 if (debug_relocs)
2181 printf (" processing reloc at 0x%lx for local sym: %s "
2182 "st_value: 0x%lx adj value: 0x%lx\n",
2183 (long) (sec->output_offset + sec->output_section->vma
2184 + irel->r_offset),
2185 bfd_elf_string_from_elf_section
2186 (abfd, symtab_hdr->sh_link, isym->st_name),
2187 (long) isym->st_value, (long) symval);
2188 }
2189 else
2190 {
2191 unsigned long indx;
2192 struct elf_link_hash_entry *h;
2193
2194 /* An external symbol. */
2195 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2196 h = elf_sym_hashes (abfd)[indx];
2197 BFD_ASSERT (h != NULL);
2198
2199 if (h->root.type != bfd_link_hash_defined
2200 && h->root.type != bfd_link_hash_defweak)
2201 /* This appears to be a reference to an undefined
2202 symbol. Just ignore it--it will be caught by the
2203 regular reloc processing. */
2204 continue;
2205
2206 symval = (h->root.u.def.value
2207 + h->root.u.def.section->output_section->vma
2208 + h->root.u.def.section->output_offset);
2209 if (debug_relocs)
2210 printf (" processing reloc at 0x%lx for global sym: %s "
2211 "st_value: 0x%lx adj value: 0x%lx\n", (long)
2212 (sec->output_offset + sec->output_section->vma
2213 + irel->r_offset),
2214 h->root.root.string, (long) h->root.u.def.value,
2215 (long) symval);
2216 }
2217
2218 /* For simplicity of coding, we are going to modify the section
2219 contents, the section relocs, and the BFD symbol table. We
2220 must tell the rest of the code not to free up this
2221 information. It would be possible to instead create a table
2222 of changes which have to be made, as is done in coff-mips.c;
2223 that would be more work, but would require less memory when
2224 the linker is run. */
2225
2226 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2227 branch. */
2228 /* Paranoia? paranoia... */
2229 if (! uses_msp430x_relocs (abfd)
2230 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
2231 {
2232 bfd_vma value = symval;
2233
2234 /* Deal with pc-relative gunk. */
2235 value -= (sec->output_section->vma + sec->output_offset);
2236 value -= irel->r_offset;
2237 value += irel->r_addend;
2238
2239 /* See if the value will fit in 10 bits, note the high value is
2240 1016 as the target will be two bytes closer if we are
2241 able to relax. */
2242 if ((long) value < 1016 && (long) value > -1016)
2243 {
2244 int code0 = 0, code1 = 0, code2 = 0;
2245 int i;
2246 struct rcodes_s *rx;
2247
2248 /* Get the opcode. */
2249 if (irel->r_offset >= 6)
2250 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2251
2252 if (irel->r_offset >= 4)
2253 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2254
2255 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2256
2257 if (code2 != 0x4010)
2258 continue;
2259
2260 /* Check r4 and r3. */
2261 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2262 {
2263 rx = &rcode[i];
2264 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2265 break;
2266 else if (rx->cdx == 1 && rx->f1 == code1)
2267 break;
2268 else if (rx->cdx == 0) /* This is an unconditional jump. */
2269 break;
2270 }
2271
2272 /* Check labels:
2273 .Label0: ; we do not care about this label
2274 jeq +6
2275 .Label1: ; make sure there is no label here
2276 jl +4
2277 .Label2: ; make sure there is no label here
2278 br .Label_dst
2279
2280 So, if there is .Label1 or .Label2 we cannot relax this code.
2281 This actually should not happen, cause for relaxable
2282 instructions we use RL_PCREL reloc instead of 16_PCREL.
2283 Will change this in the future. */
2284
2285 if (rx->cdx > 0
2286 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2287 irel->r_offset - 2))
2288 continue;
2289 if (rx->cdx > 1
2290 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2291 irel->r_offset - 4))
2292 continue;
2293
2294 /* Note that we've changed the relocs, section contents, etc. */
2295 elf_section_data (sec)->relocs = internal_relocs;
2296 elf_section_data (sec)->this_hdr.contents = contents;
2297 symtab_hdr->contents = (unsigned char *) isymbuf;
2298
2299 if (debug_relocs)
2300 printf (" R_MSP430_RL_PCREL -> ");
2301 /* Fix the relocation's type. */
2302 if (uses_msp430x_relocs (abfd))
2303 {
2304 if (rx->labels == 3) /* Handle special cases. */
2305 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2306 R_MSP430X_2X_PCREL);
2307 else
2308 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2309 R_MSP430X_10_PCREL);
2310 }
2311 else
2312 {
2313 if (rx->labels == 3) /* Handle special cases. */
2314 {
2315 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2316 R_MSP430_2X_PCREL);
2317 if (debug_relocs)
2318 printf ("R_MSP430_2X_PCREL (shrinking with new opcode"
2319 " 0x%x)\n", rx->t0);
2320 }
2321 else
2322 {
2323 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2324 R_MSP430_10_PCREL);
2325 if (debug_relocs)
2326 printf ("R_MSP430_10_PCREL (shrinking with new opcode"
2327 " 0x%x)\n", rx->t0);
2328 }
2329 }
2330
2331 /* Fix the opcode right way. */
2332 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2333 if (rx->t1)
2334 bfd_put_16 (abfd, rx->t1,
2335 contents + irel->r_offset - rx->off + 2);
2336
2337 /* Delete bytes. */
2338 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2339 irel->r_offset - rx->off +
2340 rx->ncl, rx->bs))
2341 goto error_return;
2342
2343 /* Handle unconditional jumps. */
2344 if (rx->cdx == 0)
2345 irel->r_offset -= 2;
2346
2347 /* That will change things, so, we should relax again.
2348 Note that this is not required, and it may be slow. */
2349 *again = TRUE;
2350 }
2351 }
2352
2353 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2354 branch. */
2355 if ((uses_msp430x_relocs (abfd)
2356 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2357 || (! uses_msp430x_relocs (abfd)
2358 && ELF32_R_TYPE (irel->r_info) == R_MSP430_16))
2359 {
2360 bfd_vma value = symval;
2361
2362 value -= (sec->output_section->vma + sec->output_offset);
2363 value -= irel->r_offset;
2364 value += irel->r_addend;
2365
2366 /* See if the value will fit in 10 bits, note the high value is
2367 1016 as the target will be two bytes closer if we are
2368 able to relax. */
2369 if ((long) value < 1016 && (long) value > -1016)
2370 {
2371 int code1, code2, opcode;
2372
2373 /* Get the opcode. */
2374 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2375 if (code2 != 0x4030) /* BR -> JMP */
2376 continue;
2377 /* FIXME: check r4 and r3 ? */
2378 /* FIXME: Handle 0x4010 as well ? */
2379
2380 /* Note that we've changed the relocs, section contents, etc. */
2381 elf_section_data (sec)->relocs = internal_relocs;
2382 elf_section_data (sec)->this_hdr.contents = contents;
2383 symtab_hdr->contents = (unsigned char *) isymbuf;
2384
2385 /* Fix the relocation's type. */
2386 if (uses_msp430x_relocs (abfd))
2387 {
2388 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2389 R_MSP430X_10_PCREL);
2390 if (debug_relocs)
2391 printf (" R_MSP430X_16 -> R_MSP430X_10_PCREL ");
2392 }
2393 else
2394 {
2395 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2396 R_MSP430_10_PCREL);
2397 if (debug_relocs)
2398 printf (" R_MSP430_16 -> R_MSP430_10_PCREL ");
2399 }
2400 /* If we're trying to shrink a BR[A] after previously having
2401 grown a JMP for this reloc, then we have a sequence like
2402 this:
2403 J<cond> 1f
2404 BR[A]
2405 1:
2406 The opcode for J<cond> has the target hard-coded as 2 words
2407 ahead of the insn, instead of using a reloc.
2408 This means we cannot rely on any of the helper functions to
2409 update this hard-coded jump destination if we remove the
2410 BR[A] insn, so we must explicitly update it here.
2411 This does mean that we can remove the entire branch
2412 instruction, and invert the conditional jump, saving us 4
2413 bytes rather than only 2 if we detected this in the normal
2414 way. */
2415 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2416 switch (code1)
2417 {
2418 case 0x3802: opcode = 0x3401; break; /* Jl +2 -> Jge +1 */
2419 case 0x3402: opcode = 0x3801; break; /* Jge +2 -> Jl +1 */
2420 case 0x2c02: opcode = 0x2801; break; /* Jhs +2 -> Jlo +1 */
2421 case 0x2802: opcode = 0x2c01; break; /* Jlo +2 -> Jhs +1 */
2422 case 0x2402: opcode = 0x2001; break; /* Jeq +2 -> Jne +1 */
2423 case 0x2002: opcode = 0x2401; break; /* jne +2 -> Jeq +1 */
2424 case 0x3002: /* jn +2 */
2425 /* FIXME: There is no direct inverse of the Jn insn. */
2426 continue;
2427 default:
2428 /* The previous opcode does not have a hard-coded jump
2429 that we added when previously relaxing, so relax the
2430 current branch as normal. */
2431 opcode = 0x3c00;
2432 break;
2433 }
2434 if (debug_relocs)
2435 printf ("(shrinking with new opcode 0x%x)\n", opcode);
2436
2437 if (opcode != 0x3c00)
2438 {
2439 /* Invert the opcode of the conditional jump. */
2440 bfd_put_16 (abfd, opcode, contents + irel->r_offset - 4);
2441 irel->r_offset -= 4;
2442
2443 /* Delete 4 bytes - the full BR insn. */
2444 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2445 irel->r_offset + 2, 4))
2446 goto error_return;
2447 }
2448 else
2449 {
2450 /* Fix the opcode right way. */
2451 bfd_put_16 (abfd, opcode, contents + irel->r_offset - 2);
2452 irel->r_offset -= 2;
2453
2454 /* Delete bytes. */
2455 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2456 irel->r_offset + 2, 2))
2457 goto error_return;
2458 }
2459
2460 /* That will change things, so, we should relax again.
2461 Note that this is not required, and it may be slow. */
2462 *again = TRUE;
2463 }
2464 }
2465 }
2466
2467 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2468 {
2469 if (!link_info->keep_memory)
2470 free (isymbuf);
2471 else
2472 {
2473 /* Cache the symbols for elf_link_input_bfd. */
2474 symtab_hdr->contents = (unsigned char *) isymbuf;
2475 }
2476 }
2477
2478 if (contents != NULL
2479 && elf_section_data (sec)->this_hdr.contents != contents)
2480 {
2481 if (!link_info->keep_memory)
2482 free (contents);
2483 else
2484 {
2485 /* Cache the section contents for elf_link_input_bfd. */
2486 elf_section_data (sec)->this_hdr.contents = contents;
2487 }
2488 }
2489
2490 if (elf_section_data (sec)->relocs != internal_relocs)
2491 free (internal_relocs);
2492
2493 return TRUE;
2494
2495 error_return:
2496 if (symtab_hdr->contents != (unsigned char *) isymbuf)
2497 free (isymbuf);
2498 if (elf_section_data (sec)->this_hdr.contents != contents)
2499 free (contents);
2500 if (elf_section_data (sec)->relocs != internal_relocs)
2501 free (internal_relocs);
2502
2503 return FALSE;
2504 }
2505
2506 /* Handle an MSP430 specific section when reading an object file.
2507 This is called when bfd_section_from_shdr finds a section with
2508 an unknown type. */
2509
2510 static bfd_boolean
2511 elf32_msp430_section_from_shdr (bfd *abfd,
2512 Elf_Internal_Shdr * hdr,
2513 const char *name,
2514 int shindex)
2515 {
2516 switch (hdr->sh_type)
2517 {
2518 case SHT_MSP430_SEC_FLAGS:
2519 case SHT_MSP430_SYM_ALIASES:
2520 case SHT_MSP430_ATTRIBUTES:
2521 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2522 default:
2523 return FALSE;
2524 }
2525 }
2526
2527 static bfd_boolean
2528 elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2529 {
2530 _bfd_error_handler
2531 /* xgettext:c-format */
2532 (_("warning: %pB: unknown MSPABI object attribute %d"),
2533 abfd, tag);
2534 return TRUE;
2535 }
2536
2537 /* Determine whether an object attribute tag takes an integer, a
2538 string or both. */
2539
2540 static int
2541 elf32_msp430_obj_attrs_arg_type (int tag)
2542 {
2543 if (tag == Tag_compatibility)
2544 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2545
2546 if (tag < 32)
2547 return ATTR_TYPE_FLAG_INT_VAL;
2548
2549 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2550 }
2551
2552 static inline const char *
2553 isa_type (int isa)
2554 {
2555 switch (isa)
2556 {
2557 case 1: return "MSP430";
2558 case 2: return "MSP430X";
2559 default: return "unknown";
2560 }
2561 }
2562
2563 static inline const char *
2564 code_model (int model)
2565 {
2566 switch (model)
2567 {
2568 case 1: return "small";
2569 case 2: return "large";
2570 default: return "unknown";
2571 }
2572 }
2573
2574 static inline const char *
2575 data_model (int model)
2576 {
2577 switch (model)
2578 {
2579 case 1: return "small";
2580 case 2: return "large";
2581 case 3: return "restricted large";
2582 default: return "unknown";
2583 }
2584 }
2585
2586 /* Merge MSPABI and GNU object attributes from IBFD into OBFD.
2587 Raise an error if there are conflicting attributes. */
2588
2589 static bfd_boolean
2590 elf32_msp430_merge_msp430_attributes (bfd *ibfd, struct bfd_link_info *info)
2591 {
2592 bfd *obfd = info->output_bfd;
2593 obj_attribute *in_msp_attr, *in_gnu_attr;
2594 obj_attribute *out_msp_attr, *out_gnu_attr;
2595 bfd_boolean result = TRUE;
2596 static bfd * first_input_bfd = NULL;
2597
2598 /* Skip linker created files. */
2599 if (ibfd->flags & BFD_LINKER_CREATED)
2600 return TRUE;
2601
2602 /* LTO can create temporary files for linking which may not have an attribute
2603 section. */
2604 if (ibfd->lto_output
2605 && bfd_get_section_by_name (ibfd, ".MSP430.attributes") == NULL)
2606 return TRUE;
2607
2608 /* If this is the first real object just copy the attributes. */
2609 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2610 {
2611 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2612
2613 out_msp_attr = elf_known_obj_attributes_proc (obfd);
2614
2615 /* Use the Tag_null value to indicate that
2616 the attributes have been initialized. */
2617 out_msp_attr[0].i = 1;
2618
2619 first_input_bfd = ibfd;
2620 return TRUE;
2621 }
2622
2623 in_msp_attr = elf_known_obj_attributes_proc (ibfd);
2624 out_msp_attr = elf_known_obj_attributes_proc (obfd);
2625 in_gnu_attr = elf_known_obj_attributes (ibfd) [OBJ_ATTR_GNU];
2626 out_gnu_attr = elf_known_obj_attributes (obfd) [OBJ_ATTR_GNU];
2627
2628 /* The ISAs must be the same. */
2629 if (in_msp_attr[OFBA_MSPABI_Tag_ISA].i != out_msp_attr[OFBA_MSPABI_Tag_ISA].i)
2630 {
2631 _bfd_error_handler
2632 /* xgettext:c-format */
2633 (_("error: %pB uses %s instructions but %pB uses %s"),
2634 ibfd, isa_type (in_msp_attr[OFBA_MSPABI_Tag_ISA].i),
2635 first_input_bfd, isa_type (out_msp_attr[OFBA_MSPABI_Tag_ISA].i));
2636 result = FALSE;
2637 }
2638
2639 /* The code models must be the same. */
2640 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i
2641 != out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i)
2642 {
2643 _bfd_error_handler
2644 /* xgettext:c-format */
2645 (_("error: %pB uses the %s code model whereas %pB uses the %s code model"),
2646 ibfd, code_model (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i),
2647 first_input_bfd,
2648 code_model (out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i));
2649 result = FALSE;
2650 }
2651
2652 /* The large code model is only supported by the MSP430X. */
2653 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2654 && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2655 {
2656 _bfd_error_handler
2657 /* xgettext:c-format */
2658 (_("error: %pB uses the large code model but %pB uses MSP430 instructions"),
2659 ibfd, first_input_bfd);
2660 result = FALSE;
2661 }
2662
2663 /* The data models must be the same. */
2664 if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i
2665 != out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i)
2666 {
2667 _bfd_error_handler
2668 /* xgettext:c-format */
2669 (_("error: %pB uses the %s data model whereas %pB uses the %s data model"),
2670 ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i),
2671 first_input_bfd,
2672 data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i));
2673 result = FALSE;
2674 }
2675
2676 /* The small code model requires the use of the small data model. */
2677 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2678 && out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
2679 {
2680 _bfd_error_handler
2681 /* xgettext:c-format */
2682 (_("error: %pB uses the small code model but %pB uses the %s data model"),
2683 ibfd, first_input_bfd,
2684 data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i));
2685 result = FALSE;
2686 }
2687
2688 /* The large data models are only supported by the MSP430X. */
2689 if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2690 && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2691 {
2692 _bfd_error_handler
2693 /* xgettext:c-format */
2694 (_("error: %pB uses the %s data model but %pB only uses MSP430 instructions"),
2695 ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i),
2696 first_input_bfd);
2697 result = FALSE;
2698 }
2699
2700 /* Just ignore the data region unless the large memory model is in use.
2701 We have already checked that ibfd and obfd use the same memory model. */
2702 if ((in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i
2703 == OFBA_MSPABI_Val_Code_Model_LARGE)
2704 && (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i
2705 == OFBA_MSPABI_Val_Data_Model_LARGE))
2706 {
2707 /* We cannot allow "lower region only" to be linked with any other
2708 values (i.e. ANY or NONE).
2709 Before this attribute existed, "ANY" region was the default. */
2710 bfd_boolean ibfd_lower_region_used
2711 = (in_gnu_attr[Tag_GNU_MSP430_Data_Region].i
2712 == Val_GNU_MSP430_Data_Region_Lower);
2713 bfd_boolean obfd_lower_region_used
2714 = (out_gnu_attr[Tag_GNU_MSP430_Data_Region].i
2715 == Val_GNU_MSP430_Data_Region_Lower);
2716 if (ibfd_lower_region_used != obfd_lower_region_used)
2717 {
2718 _bfd_error_handler
2719 (_("error: %pB can use the upper region for data, "
2720 "but %pB assumes data is exclusively in lower memory"),
2721 ibfd_lower_region_used ? obfd : ibfd,
2722 ibfd_lower_region_used ? ibfd : obfd);
2723 result = FALSE;
2724 }
2725 }
2726
2727 return result;
2728 }
2729
2730 /* Merge backend specific data from an object file to the output
2731 object file when linking. */
2732
2733 static bfd_boolean
2734 elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
2735 {
2736 bfd *obfd = info->output_bfd;
2737 /* Make sure that the machine number reflects the most
2738 advanced version of the MSP architecture required. */
2739 #define max(a,b) ((a) > (b) ? (a) : (b))
2740 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2741 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2742 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2743 #undef max
2744
2745 return elf32_msp430_merge_msp430_attributes (ibfd, info);
2746 }
2747
2748 static bfd_boolean
2749 msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2750 {
2751 return _bfd_elf_is_local_label_name (abfd, sym->name);
2752 }
2753
2754 static bfd_boolean
2755 uses_large_model (bfd *abfd)
2756 {
2757 obj_attribute * attr;
2758
2759 if (abfd->flags & BFD_LINKER_CREATED)
2760 return FALSE;
2761
2762 attr = elf_known_obj_attributes_proc (abfd);
2763 if (attr == NULL)
2764 return FALSE;
2765
2766 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2;
2767 }
2768
2769 static unsigned int
2770 elf32_msp430_eh_frame_address_size (bfd *abfd,
2771 const asection *sec ATTRIBUTE_UNUSED)
2772 {
2773 return uses_large_model (abfd) ? 4 : 2;
2774 }
2775
2776 /* This is gross. The MSP430 EABI says that (sec 11.5):
2777
2778 "An implementation may choose to use Rel or Rela
2779 type relocations for other relocations."
2780
2781 But it also says that:
2782
2783 "Certain relocations are identified as Rela only. [snip]
2784 Where Rela is specified, an implementation must honor
2785 this requirement."
2786
2787 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2788 to keep things simple we choose to use RELA relocations throughout. The
2789 problem is that the TI compiler generates REL relocations, so we have to
2790 be able to accept those as well. */
2791
2792 #define elf_backend_may_use_rel_p 1
2793 #define elf_backend_may_use_rela_p 1
2794 #define elf_backend_default_use_rela_p 1
2795
2796 #undef elf_backend_obj_attrs_vendor
2797 #define elf_backend_obj_attrs_vendor "mspabi"
2798 #undef elf_backend_obj_attrs_section
2799 #define elf_backend_obj_attrs_section ".MSP430.attributes"
2800 #undef elf_backend_obj_attrs_section_type
2801 #define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
2802 #define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2803 #define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2804 #undef elf_backend_obj_attrs_arg_type
2805 #define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
2806 #define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
2807 #define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size
2808
2809 #define ELF_ARCH bfd_arch_msp430
2810 #define ELF_MACHINE_CODE EM_MSP430
2811 #define ELF_MACHINE_ALT1 EM_MSP430_OLD
2812 #define ELF_MAXPAGESIZE 4
2813 #define ELF_OSABI ELFOSABI_STANDALONE
2814
2815 #define TARGET_LITTLE_SYM msp430_elf32_vec
2816 #define TARGET_LITTLE_NAME "elf32-msp430"
2817
2818 #define elf_info_to_howto msp430_info_to_howto_rela
2819 #define elf_info_to_howto_rel NULL
2820 #define elf_backend_relocate_section elf32_msp430_relocate_section
2821 #define elf_backend_check_relocs elf32_msp430_check_relocs
2822 #define elf_backend_can_gc_sections 1
2823 #define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2824 #define elf_backend_object_p elf32_msp430_object_p
2825 #define bfd_elf32_bfd_relax_section msp430_elf_relax_section
2826 #define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2827
2828 #undef elf32_bed
2829 #define elf32_bed elf32_msp430_bed
2830
2831 #include "elf32-target.h"
2832
2833 /* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
2834 #undef TARGET_LITTLE_SYM
2835 #define TARGET_LITTLE_SYM msp430_elf32_ti_vec
2836
2837 #undef elf32_bed
2838 #define elf32_bed elf32_msp430_ti_bed
2839
2840 #undef ELF_OSABI
2841 #define ELF_OSABI ELFOSABI_NONE
2842
2843 static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2844 {
2845 /* prefix, prefix_length, suffix_len, type, attributes. */
2846 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2847 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2848 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
2849 { NULL, 0, 0, 0, 0 }
2850 };
2851
2852 #undef elf_backend_special_sections
2853 #define elf_backend_special_sections msp430_ti_elf_special_sections
2854
2855 #include "elf32-target.h"
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