1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
30 #include "cpu-aarch64.h"
33 #include "elf/aarch64.h"
34 #include "dw2gencfi.h"
37 #include "dwarf2dbg.h"
39 /* Types of processor to assemble for. */
41 #define CPU_DEFAULT AARCH64_ARCH_V8
44 #define streq(a, b) (strcmp (a, b) == 0)
46 #define END_OF_INSN '\0'
48 #define MAP_CUR_INSN (AARCH64_CPU_HAS_FEATURE (cpu_variant, \
49 AARCH64_FEATURE_C64) \
52 #define IS_C64 (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64) \
55 static aarch64_feature_set cpu_variant
;
57 /* Variables that we set while parsing command-line options. Once all
58 options have been read we re-process these values to set the real
60 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
61 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
63 /* Constants for known architecture features. */
64 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
66 /* Currently active instruction sequence. */
67 static aarch64_instr_sequence
*insn_sequence
= NULL
;
70 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
71 static symbolS
*GOT_symbol
;
73 /* Which ABI to use. */
78 AARCH64_ABI_ILP32
= 2,
79 AARCH64_ABI_PURECAP
= 3,
80 AARCH64_ABI_HYBRID
= 4,
84 #define DEFAULT_ARCH "aarch64"
87 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
88 static const char *default_arch
= DEFAULT_ARCH
;
90 /* AArch64 ABI for the output file. */
91 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
93 /* When non-zero, program to a 32-bit model, in which the C data types
94 int, long and all pointer types are 32-bit objects (ILP32); or to a
95 64-bit model, in which the C int type is 32-bits but the C long type
96 and all pointer types are 64-bit objects (LP64). */
97 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
112 /* Bits for DEFINED field in vector_type_el. */
113 #define NTA_HASTYPE 1
114 #define NTA_HASINDEX 2
115 #define NTA_HASVARWIDTH 4
117 struct vector_type_el
119 enum vector_el_type type
;
120 unsigned char defined
;
125 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
126 #define FIXUP_F_C64 0x00000002
130 bfd_reloc_code_real_type type
;
133 enum aarch64_opnd opnd
;
135 unsigned need_libopcodes_p
: 1;
138 struct aarch64_instruction
140 /* libopcodes structure for instruction intermediate representation. */
142 /* Record assembly errors found during the parsing. */
145 enum aarch64_operand_error_kind kind
;
148 /* The condition that appears in the assembly line. */
150 /* Relocation information (including the GAS internal fixup). */
152 /* Need to generate an immediate in the literal pool. */
153 unsigned gen_lit_pool
: 1;
156 typedef struct aarch64_instruction aarch64_instruction
;
158 static aarch64_instruction inst
;
160 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
161 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
164 # define now_instr_sequence seg_info \
165 (now_seg)->tc_segment_info_data.insn_sequence
167 static struct aarch64_instr_sequence now_instr_sequence
;
170 /* Diagnostics inline function utilities.
172 These are lightweight utilities which should only be called by parse_operands
173 and other parsers. GAS processes each assembly line by parsing it against
174 instruction template(s), in the case of multiple templates (for the same
175 mnemonic name), those templates are tried one by one until one succeeds or
176 all fail. An assembly line may fail a few templates before being
177 successfully parsed; an error saved here in most cases is not a user error
178 but an error indicating the current template is not the right template.
179 Therefore it is very important that errors can be saved at a low cost during
180 the parsing; we don't want to slow down the whole parsing by recording
181 non-user errors in detail.
183 Remember that the objective is to help GAS pick up the most appropriate
184 error message in the case of multiple templates, e.g. FMOV which has 8
190 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
191 inst
.parsing_error
.error
= NULL
;
194 static inline bfd_boolean
197 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
200 static inline const char *
201 get_error_message (void)
203 return inst
.parsing_error
.error
;
206 static inline enum aarch64_operand_error_kind
207 get_error_kind (void)
209 return inst
.parsing_error
.kind
;
213 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
215 inst
.parsing_error
.kind
= kind
;
216 inst
.parsing_error
.error
= error
;
220 set_recoverable_error (const char *error
)
222 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
225 /* Use the DESC field of the corresponding aarch64_operand entry to compose
226 the error message. */
228 set_default_error (void)
230 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
234 set_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_first_syntax_error (const char *error
)
243 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
247 set_fatal_syntax_error (const char *error
)
249 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
252 /* Return value for certain parsers when the parsing fails; those parsers
253 return the information of the parsed result, e.g. register number, on
255 #define PARSE_FAIL -1
257 /* This is an invalid condition code that means no conditional field is
259 #define COND_ALWAYS 0x10
263 const char *template;
270 bfd_reloc_code_real_type reloc
;
273 /* Macros to define the register types and masks for the purpose
276 #undef AARCH64_REG_TYPES
277 #define AARCH64_REG_TYPES \
278 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
279 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
280 BASIC_REG_TYPE(SP_32) /* wsp */ \
281 BASIC_REG_TYPE(SP_64) /* sp */ \
282 BASIC_REG_TYPE(Z_32) /* wzr */ \
283 BASIC_REG_TYPE(Z_64) /* xzr */ \
284 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
285 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
286 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
287 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
288 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
289 BASIC_REG_TYPE(CA_N) /* c[0-30] */ \
290 BASIC_REG_TYPE(CA_SP) /* csp */ \
291 BASIC_REG_TYPE(CA_Z) /* czr */ \
292 BASIC_REG_TYPE(CA_D) /* ddc */ \
293 BASIC_REG_TYPE(VN) /* v[0-31] */ \
294 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
295 BASIC_REG_TYPE(PN) /* p[0-15] */ \
296 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
297 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
301 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
302 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
303 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
304 /* Typecheck: same, plus SVE registers. */ \
305 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
306 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
308 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
309 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
310 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
311 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
312 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
313 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
315 /* Typecheck: any [BHSDQ]P FP. */ \
316 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
317 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
318 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
319 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
321 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
322 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
323 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
324 be used for SVE instructions, since Zn and Pn are valid symbols \
325 in other contexts. */ \
326 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
327 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
328 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
329 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
330 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
331 | REG_TYPE(ZN) | REG_TYPE(PN)) \
332 /* Any integer register; used for error messages only. */ \
333 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
334 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
335 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
336 /* Typecheck: any capability register (inc CSP) */ \
337 MULTI_REG_TYPE(CA_N_SP, REG_TYPE(CA_N) | REG_TYPE(CA_SP)) \
338 MULTI_REG_TYPE(CA_N_Z, REG_TYPE(CA_N) | REG_TYPE(CA_Z)) \
339 /* Pseudo type to mark the end of the enumerator sequence. */ \
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
344 #undef MULTI_REG_TYPE
345 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
347 /* Register type enumerators. */
348 typedef enum aarch64_reg_type_
350 /* A list of REG_TYPE_*. */
354 #undef BASIC_REG_TYPE
355 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
357 #define REG_TYPE(T) (1 << REG_TYPE_##T)
358 #undef MULTI_REG_TYPE
359 #define MULTI_REG_TYPE(T,V) V,
361 /* Structure for a hash table entry for a register. */
365 unsigned char number
;
366 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
367 unsigned char builtin
;
370 /* Values indexed by aarch64_reg_type to assist the type checking. */
371 static const unsigned reg_type_masks
[] =
376 #undef BASIC_REG_TYPE
378 #undef MULTI_REG_TYPE
379 #undef AARCH64_REG_TYPES
381 /* Diagnostics used when we don't get a register of the expected type.
382 Note: this has to synchronized with aarch64_reg_type definitions
385 get_reg_expected_msg (aarch64_reg_type reg_type
)
392 msg
= N_("integer 32-bit register expected");
395 msg
= N_("integer 64-bit register expected");
398 msg
= N_("integer register expected");
400 case REG_TYPE_R64_SP
:
401 msg
= N_("64-bit integer or SP register expected");
403 case REG_TYPE_SVE_BASE
:
404 msg
= N_("base register expected");
407 msg
= N_("integer or zero register expected");
409 case REG_TYPE_SVE_OFFSET
:
410 msg
= N_("offset register expected");
413 msg
= N_("integer or SP register expected");
415 case REG_TYPE_R_Z_SP
:
416 msg
= N_("integer, zero or SP register expected");
419 msg
= N_("8-bit SIMD scalar register expected");
422 msg
= N_("16-bit SIMD scalar or floating-point half precision "
423 "register expected");
426 msg
= N_("32-bit SIMD scalar or floating-point single precision "
427 "register expected");
430 msg
= N_("64-bit SIMD scalar or floating-point double precision "
431 "register expected");
434 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
435 "register expected");
437 case REG_TYPE_R_Z_BHSDQ_V
:
438 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
439 msg
= N_("register expected");
441 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
442 msg
= N_("SIMD scalar or floating-point register expected");
444 case REG_TYPE_VN
: /* any V reg */
445 msg
= N_("vector register expected");
448 msg
= N_("SVE vector register expected");
451 msg
= N_("SVE predicate register expected");
454 msg
= N_("Capability register C0 - C30 expected");
457 msg
= N_("Capability register CSP expected");
459 case REG_TYPE_CA_N_SP
:
460 msg
= N_("Capability register C0 - C30 or CSP expected");
463 msg
= N_("Capability register CZR expected");
466 as_fatal (_("invalid register type %d"), reg_type
);
471 /* Some well known registers that we refer to directly elsewhere. */
474 #define REG_DW_CSP (31 + 198)
475 #define REG_DW_CLR (30 + 198)
477 /* Instructions take 4 bytes in the object file. */
480 static htab_t aarch64_ops_hsh
;
481 static htab_t aarch64_cond_hsh
;
482 static htab_t aarch64_shift_hsh
;
483 static htab_t aarch64_sys_regs_hsh
;
484 static htab_t aarch64_pstatefield_hsh
;
485 static htab_t aarch64_sys_regs_ic_hsh
;
486 static htab_t aarch64_sys_regs_dc_hsh
;
487 static htab_t aarch64_sys_regs_at_hsh
;
488 static htab_t aarch64_sys_regs_tlbi_hsh
;
489 static htab_t aarch64_sys_regs_sr_hsh
;
490 static htab_t aarch64_reg_hsh
;
491 static htab_t aarch64_barrier_opt_hsh
;
492 static htab_t aarch64_nzcv_hsh
;
493 static htab_t aarch64_pldop_hsh
;
494 static htab_t aarch64_hint_opt_hsh
;
496 /* Stuff needed to resolve the label ambiguity
505 static symbolS
*last_label_seen
;
507 /* Literal pool structure. Held on a per-section
508 and per-sub-section basis. */
510 #define MAX_LITERAL_POOL_SIZE 1024
511 typedef struct literal_expression
514 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
515 LITTLENUM_TYPE
* bignum
;
516 } literal_expression
;
518 typedef struct literal_pool
520 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
521 unsigned int next_free_entry
;
527 struct literal_pool
*next
;
530 /* Pointer to a linked list of literal pools. */
531 static literal_pool
*list_of_pools
= NULL
;
535 /* This array holds the chars that always start a comment. If the
536 pre-processor is disabled, these aren't very useful. */
537 const char comment_chars
[] = "";
539 /* This array holds the chars that only start a comment at the beginning of
540 a line. If the line seems to have the form '# 123 filename'
541 .line and .file directives will appear in the pre-processed output. */
542 /* Note that input_file.c hand checks for '#' at the beginning of the
543 first line of the input file. This is because the compiler outputs
544 #NO_APP at the beginning of its output. */
545 /* Also note that comments like this one will always work. */
546 const char line_comment_chars
[] = "#";
548 const char line_separator_chars
[] = ";";
550 /* Chars that can be used to separate mant
551 from exp in floating point numbers. */
552 const char EXP_CHARS
[] = "eE";
554 /* Chars that mean this number is a floating point constant. */
558 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
560 /* Prefix character that indicates the start of an immediate value. */
561 #define is_immediate_prefix(C) ((C) == '#')
563 /* Separator character handling. */
565 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
567 static inline bfd_boolean
568 skip_past_char (char **str
, char c
)
579 #define skip_past_comma(str) skip_past_char (str, ',')
581 /* Arithmetic expressions (possibly involving symbols). */
583 static bfd_boolean in_my_get_expression_p
= FALSE
;
585 /* Third argument to my_get_expression. */
586 #define GE_NO_PREFIX 0
587 #define GE_OPT_PREFIX 1
589 /* Return TRUE if the string pointed by *STR is successfully parsed
590 as an valid expression; *EP will be filled with the information of
591 such an expression. Otherwise return FALSE. */
594 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
599 int prefix_present_p
= 0;
606 if (is_immediate_prefix (**str
))
609 prefix_present_p
= 1;
616 memset (ep
, 0, sizeof (expressionS
));
618 save_in
= input_line_pointer
;
619 input_line_pointer
= *str
;
620 in_my_get_expression_p
= TRUE
;
621 seg
= expression (ep
);
622 in_my_get_expression_p
= FALSE
;
624 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
626 /* We found a bad expression in md_operand(). */
627 *str
= input_line_pointer
;
628 input_line_pointer
= save_in
;
629 if (prefix_present_p
&& ! error_p ())
630 set_fatal_syntax_error (_("bad expression"));
632 set_first_syntax_error (_("bad expression"));
637 if (seg
!= absolute_section
638 && seg
!= text_section
639 && seg
!= data_section
640 && seg
!= bss_section
&& seg
!= undefined_section
)
642 set_syntax_error (_("bad segment"));
643 *str
= input_line_pointer
;
644 input_line_pointer
= save_in
;
651 *str
= input_line_pointer
;
652 input_line_pointer
= save_in
;
656 /* Turn a string in input_line_pointer into a floating point constant
657 of type TYPE, and store the appropriate bytes in *LITP. The number
658 of LITTLENUMS emitted is stored in *SIZEP. An error message is
659 returned, or NULL on OK. */
662 md_atof (int type
, char *litP
, int *sizeP
)
664 /* If this is a bfloat16 type, then parse it slightly differently -
665 as it does not follow the IEEE standard exactly. */
669 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
670 FLONUM_TYPE generic_float
;
672 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
675 input_line_pointer
= t
;
677 return _("invalid floating point number");
679 switch (generic_float
.sign
)
692 /* bfloat16 has two types of NaN - quiet and signalling.
693 Quiet NaN has bit[6] == 1 && faction != 0, whereas
694 signalling Nan's have bit[0] == 0 && fraction != 0.
695 Chose this specific encoding as it is the same form
696 as used by other IEEE 754 encodings in GAS. */
707 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
712 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
715 /* We handle all bad expressions here, so that we can report the faulty
716 instruction in the error message. */
718 md_operand (expressionS
* exp
)
720 if (in_my_get_expression_p
)
721 exp
->X_op
= O_illegal
;
724 /* Immediate values. */
726 /* Errors may be set multiple times during parsing or bit encoding
727 (particularly in the Neon bits), but usually the earliest error which is set
728 will be the most meaningful. Avoid overwriting it with later (cascading)
729 errors by calling this function. */
732 first_error (const char *error
)
735 set_syntax_error (error
);
738 /* Similar to first_error, but this function accepts formatted error
741 first_error_fmt (const char *format
, ...)
746 /* N.B. this single buffer will not cause error messages for different
747 instructions to pollute each other; this is because at the end of
748 processing of each assembly line, error message if any will be
749 collected by as_bad. */
750 static char buffer
[size
];
754 int ret ATTRIBUTE_UNUSED
;
755 va_start (args
, format
);
756 ret
= vsnprintf (buffer
, size
, format
, args
);
757 know (ret
<= size
- 1 && ret
>= 0);
759 set_syntax_error (buffer
);
763 /* Register parsing. */
765 /* Generic register parser which is called by other specialized
767 CCP points to what should be the beginning of a register name.
768 If it is indeed a valid register name, advance CCP over it and
769 return the reg_entry structure; otherwise return NULL.
770 It does not issue diagnostics. */
773 parse_reg (char **ccp
)
779 #ifdef REGISTER_PREFIX
780 if (*start
!= REGISTER_PREFIX
)
786 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
791 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
793 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
802 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
805 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
807 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
810 /* Try to parse a base or offset register. Allow SVE base and offset
811 registers if REG_TYPE includes SVE registers. Return the register
812 entry on success, setting *QUALIFIER to the register qualifier.
813 Return null otherwise.
815 Note that this function does not issue any diagnostics. */
817 static const reg_entry
*
818 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
819 aarch64_opnd_qualifier_t
*qualifier
)
822 const reg_entry
*reg
= parse_reg (&str
);
832 *qualifier
= AARCH64_OPND_QLF_W
;
838 *qualifier
= AARCH64_OPND_QLF_X
;
842 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
845 switch (TOLOWER (str
[1]))
848 *qualifier
= AARCH64_OPND_QLF_S_S
;
851 *qualifier
= AARCH64_OPND_QLF_S_D
;
861 *qualifier
= AARCH64_OPND_QLF_CA
;
873 /* Try to parse a base or offset register. Return the register entry
874 on success, setting *QUALIFIER to the register qualifier. Return null
877 Note that this function does not issue any diagnostics. */
879 static const reg_entry
*
880 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
882 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
885 /* Parse the qualifier of a vector register or vector element of type
886 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
887 succeeds; otherwise return FALSE.
889 Accept only one occurrence of:
890 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
893 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
894 struct vector_type_el
*parsed_type
, char **str
)
898 unsigned element_size
;
899 enum vector_el_type type
;
902 gas_assert (*ptr
== '.');
905 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
910 width
= strtoul (ptr
, &ptr
, 10);
911 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
913 first_error_fmt (_("bad size %d in vector width specifier"), width
);
918 switch (TOLOWER (*ptr
))
937 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
946 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
948 first_error (_("missing element size"));
951 if (width
!= 0 && width
* element_size
!= 64
952 && width
* element_size
!= 128
953 && !(width
== 2 && element_size
== 16)
954 && !(width
== 4 && element_size
== 8))
957 ("invalid element size %d and vector size combination %c"),
963 parsed_type
->type
= type
;
964 parsed_type
->width
= width
;
971 /* *STR contains an SVE zero/merge predication suffix. Parse it into
972 *PARSED_TYPE and point *STR at the end of the suffix. */
975 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
980 gas_assert (*ptr
== '/');
982 switch (TOLOWER (*ptr
))
985 parsed_type
->type
= NT_zero
;
988 parsed_type
->type
= NT_merge
;
991 if (*ptr
!= '\0' && *ptr
!= ',')
992 first_error_fmt (_("unexpected character `%c' in predication type"),
995 first_error (_("missing predication type"));
998 parsed_type
->width
= 0;
1003 /* Parse a register of the type TYPE.
1005 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
1006 name or the parsed register is not of TYPE.
1008 Otherwise return the register number, and optionally fill in the actual
1009 type of the register in *RTYPE when multiple alternatives were given, and
1010 return the register shape and element index information in *TYPEINFO.
1012 IN_REG_LIST should be set with TRUE if the caller is parsing a register
1016 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
1017 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
1020 const reg_entry
*reg
= parse_reg (&str
);
1021 struct vector_type_el atype
;
1022 struct vector_type_el parsetype
;
1023 bfd_boolean is_typed_vecreg
= FALSE
;
1026 atype
.type
= NT_invtype
;
1034 set_default_error ();
1038 if (! aarch64_check_reg_type (reg
, type
))
1040 DEBUG_TRACE ("reg type check failed");
1041 set_default_error ();
1046 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1047 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1051 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1056 if (!parse_predication_for_operand (&parsetype
, &str
))
1060 /* Register if of the form Vn.[bhsdq]. */
1061 is_typed_vecreg
= TRUE
;
1063 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1065 /* The width is always variable; we don't allow an integer width
1067 gas_assert (parsetype
.width
== 0);
1068 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1070 else if (parsetype
.width
== 0)
1071 /* Expect index. In the new scheme we cannot have
1072 Vn.[bhsdq] represent a scalar. Therefore any
1073 Vn.[bhsdq] should have an index following it.
1074 Except in reglists of course. */
1075 atype
.defined
|= NTA_HASINDEX
;
1077 atype
.defined
|= NTA_HASTYPE
;
1079 atype
.type
= parsetype
.type
;
1080 atype
.width
= parsetype
.width
;
1083 if (skip_past_char (&str
, '['))
1087 /* Reject Sn[index] syntax. */
1088 if (!is_typed_vecreg
)
1090 first_error (_("this type of register can't be indexed"));
1096 first_error (_("index not allowed inside register list"));
1100 atype
.defined
|= NTA_HASINDEX
;
1102 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1104 if (exp
.X_op
!= O_constant
)
1106 first_error (_("constant expression required"));
1110 if (! skip_past_char (&str
, ']'))
1113 atype
.index
= exp
.X_add_number
;
1115 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1117 /* Indexed vector register expected. */
1118 first_error (_("indexed vector register expected"));
1122 /* A vector reg Vn should be typed or indexed. */
1123 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1125 first_error (_("invalid use of vector register"));
1141 Return the register number on success; return PARSE_FAIL otherwise.
1143 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1144 the register (e.g. NEON double or quad reg when either has been requested).
1146 If this is a NEON vector register with additional type information, fill
1147 in the struct pointed to by VECTYPE (if non-NULL).
1149 This parser does not handle register list. */
1152 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1153 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1155 struct vector_type_el atype
;
1157 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1158 /*in_reg_list= */ FALSE
);
1160 if (reg
== PARSE_FAIL
)
1171 static inline bfd_boolean
1172 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1176 && e1
.defined
== e2
.defined
1177 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1180 /* This function parses a list of vector registers of type TYPE.
1181 On success, it returns the parsed register list information in the
1182 following encoded format:
1184 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1185 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1187 The information of the register shape and/or index is returned in
1190 It returns PARSE_FAIL if the register list is invalid.
1192 The list contains one to four registers.
1193 Each register can be one of:
1196 All <T> should be identical.
1197 All <index> should be identical.
1198 There are restrictions on <Vt> numbers which are checked later
1199 (by reg_list_valid_p). */
1202 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1203 struct vector_type_el
*vectype
)
1207 struct vector_type_el typeinfo
, typeinfo_first
;
1212 bfd_boolean error
= FALSE
;
1213 bfd_boolean expect_index
= FALSE
;
1217 set_syntax_error (_("expecting {"));
1223 typeinfo_first
.defined
= 0;
1224 typeinfo_first
.type
= NT_invtype
;
1225 typeinfo_first
.width
= -1;
1226 typeinfo_first
.index
= 0;
1235 str
++; /* skip over '-' */
1238 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1239 /*in_reg_list= */ TRUE
);
1240 if (val
== PARSE_FAIL
)
1242 set_first_syntax_error (_("invalid vector register in list"));
1246 /* reject [bhsd]n */
1247 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1249 set_first_syntax_error (_("invalid scalar register in list"));
1254 if (typeinfo
.defined
& NTA_HASINDEX
)
1255 expect_index
= TRUE
;
1259 if (val
< val_range
)
1261 set_first_syntax_error
1262 (_("invalid range in vector register list"));
1271 typeinfo_first
= typeinfo
;
1272 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1274 set_first_syntax_error
1275 (_("type mismatch in vector register list"));
1280 for (i
= val_range
; i
<= val
; i
++)
1282 ret_val
|= i
<< (5 * nb_regs
);
1287 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1289 skip_whitespace (str
);
1292 set_first_syntax_error (_("end of vector register list not found"));
1297 skip_whitespace (str
);
1301 if (skip_past_char (&str
, '['))
1305 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1306 if (exp
.X_op
!= O_constant
)
1308 set_first_syntax_error (_("constant expression required."));
1311 if (! skip_past_char (&str
, ']'))
1314 typeinfo_first
.index
= exp
.X_add_number
;
1318 set_first_syntax_error (_("expected index"));
1325 set_first_syntax_error (_("too many registers in vector register list"));
1328 else if (nb_regs
== 0)
1330 set_first_syntax_error (_("empty vector register list"));
1336 *vectype
= typeinfo_first
;
1338 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1341 /* Directives: register aliases. */
1344 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1349 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1352 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1355 /* Only warn about a redefinition if it's not defined as the
1357 else if (new->number
!= number
|| new->type
!= type
)
1358 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1363 name
= xstrdup (str
);
1364 new = XNEW (reg_entry
);
1367 new->number
= number
;
1369 new->builtin
= FALSE
;
1371 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1376 /* Look for the .req directive. This is of the form:
1378 new_register_name .req existing_register_name
1380 If we find one, or if it looks sufficiently like one that we want to
1381 handle any error here, return TRUE. Otherwise return FALSE. */
1384 create_register_alias (char *newname
, char *p
)
1386 const reg_entry
*old
;
1387 char *oldname
, *nbuf
;
1390 /* The input scrubber ensures that whitespace after the mnemonic is
1391 collapsed to single spaces. */
1393 if (strncmp (oldname
, " .req ", 6) != 0)
1397 if (*oldname
== '\0')
1400 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1403 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1407 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1408 the desired alias name, and p points to its end. If not, then
1409 the desired alias name is in the global original_case_string. */
1410 #ifdef TC_CASE_SENSITIVE
1413 newname
= original_case_string
;
1414 nlen
= strlen (newname
);
1417 nbuf
= xmemdup0 (newname
, nlen
);
1419 /* Create aliases under the new name as stated; an all-lowercase
1420 version of the new name; and an all-uppercase version of the new
1422 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1424 for (p
= nbuf
; *p
; p
++)
1427 if (strncmp (nbuf
, newname
, nlen
))
1429 /* If this attempt to create an additional alias fails, do not bother
1430 trying to create the all-lower case alias. We will fail and issue
1431 a second, duplicate error message. This situation arises when the
1432 programmer does something like:
1435 The second .req creates the "Foo" alias but then fails to create
1436 the artificial FOO alias because it has already been created by the
1438 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1445 for (p
= nbuf
; *p
; p
++)
1448 if (strncmp (nbuf
, newname
, nlen
))
1449 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1456 /* Should never be called, as .req goes between the alias and the
1457 register name, not at the beginning of the line. */
1459 s_req (int a ATTRIBUTE_UNUSED
)
1461 as_bad (_("invalid syntax for .req directive"));
1464 /* The .unreq directive deletes an alias which was previously defined
1465 by .req. For example:
1471 s_unreq (int a ATTRIBUTE_UNUSED
)
1476 name
= input_line_pointer
;
1478 while (*input_line_pointer
!= 0
1479 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1480 ++input_line_pointer
;
1482 saved_char
= *input_line_pointer
;
1483 *input_line_pointer
= 0;
1486 as_bad (_("invalid syntax for .unreq directive"));
1489 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1492 as_bad (_("unknown register alias '%s'"), name
);
1493 else if (reg
->builtin
)
1494 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1501 str_hash_delete (aarch64_reg_hsh
, name
);
1502 free ((char *) reg
->name
);
1505 /* Also locate the all upper case and all lower case versions.
1506 Do not complain if we cannot find one or the other as it
1507 was probably deleted above. */
1509 nbuf
= strdup (name
);
1510 for (p
= nbuf
; *p
; p
++)
1512 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1515 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1516 free ((char *) reg
->name
);
1520 for (p
= nbuf
; *p
; p
++)
1522 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1525 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1526 free ((char *) reg
->name
);
1534 *input_line_pointer
= saved_char
;
1535 demand_empty_rest_of_line ();
1538 /* Directives: Instruction set selection. */
1541 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1542 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1543 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1544 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1546 /* Create a new mapping symbol for the transition to STATE. */
1549 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1552 const char *symname
;
1559 type
= BSF_NO_FLAGS
;
1563 type
= BSF_NO_FLAGS
;
1567 type
= BSF_NO_FLAGS
;
1573 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1574 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1576 if (state
== MAP_C64
)
1577 AARCH64_SET_C64 (symbolP
, 1);
1578 else if (state
== MAP_INSN
)
1579 AARCH64_SET_C64 (symbolP
, 0);
1581 /* Save the mapping symbols for future reference. Also check that
1582 we do not place two mapping symbols at the same offset within a
1583 frag. We'll handle overlap between frags in
1584 check_mapping_symbols.
1586 If .fill or other data filling directive generates zero sized data,
1587 the mapping symbol for the following code will have the same value
1588 as the one generated for the data filling directive. In this case,
1589 we replace the old symbol with the new one at the same address. */
1592 if (frag
->tc_frag_data
.first_map
!= NULL
)
1594 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1595 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1598 frag
->tc_frag_data
.first_map
= symbolP
;
1600 if (frag
->tc_frag_data
.last_map
!= NULL
)
1602 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1603 S_GET_VALUE (symbolP
));
1604 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1605 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1608 frag
->tc_frag_data
.last_map
= symbolP
;
1611 /* We must sometimes convert a region marked as code to data during
1612 code alignment, if an odd number of bytes have to be padded. The
1613 code mapping symbol is pushed to an aligned address. */
1616 insert_data_mapping_symbol (enum mstate state
,
1617 valueT value
, fragS
* frag
, offsetT bytes
)
1619 /* If there was already a mapping symbol, remove it. */
1620 if (frag
->tc_frag_data
.last_map
!= NULL
1621 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1622 frag
->fr_address
+ value
)
1624 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1628 know (frag
->tc_frag_data
.first_map
== symp
);
1629 frag
->tc_frag_data
.first_map
= NULL
;
1631 frag
->tc_frag_data
.last_map
= NULL
;
1632 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1635 make_mapping_symbol (MAP_DATA
, value
, frag
);
1636 make_mapping_symbol (state
, value
+ bytes
, frag
);
1639 static void mapping_state_2 (enum mstate state
, int max_chars
);
1641 /* Set the mapping state to STATE. Only call this when about to
1642 emit some STATE bytes to the file. */
1645 mapping_state (enum mstate state
)
1647 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1649 if (state
== MAP_CUR_INSN
)
1650 /* AArch64 instructions require 4-byte alignment. When emitting
1651 instructions into any section, record the appropriate section
1653 record_alignment (now_seg
, 2);
1655 if (mapstate
== state
)
1656 /* The mapping symbol has already been emitted.
1657 There is nothing else to do. */
1660 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1661 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1662 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1663 evaluated later in the next else. */
1665 else if (TRANSITION (MAP_UNDEFINED
, MAP_CUR_INSN
))
1667 /* Only add the symbol if the offset is > 0:
1668 if we're at the first frag, check it's size > 0;
1669 if we're not at the first frag, then for sure
1670 the offset is > 0. */
1671 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1672 const int add_symbol
= (frag_now
!= frag_first
)
1673 || (frag_now_fix () > 0);
1676 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1680 mapping_state_2 (state
, 0);
1683 /* Same as mapping_state, but MAX_CHARS bytes have already been
1684 allocated. Put the mapping symbol that far back. */
1687 mapping_state_2 (enum mstate state
, int max_chars
)
1689 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1691 if (!SEG_NORMAL (now_seg
))
1694 if (mapstate
== state
)
1695 /* The mapping symbol has already been emitted.
1696 There is nothing else to do. */
1699 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1700 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1703 #define mapping_state(x) /* nothing */
1704 #define mapping_state_2(x, y) /* nothing */
1707 /* Directives: sectioning and alignment. */
1710 s_bss (int ignore ATTRIBUTE_UNUSED
)
1712 /* We don't support putting frags in the BSS segment, we fake it by
1713 marking in_bss, then looking at s_skip for clues. */
1714 subseg_set (bss_section
, 0);
1715 demand_empty_rest_of_line ();
1716 mapping_state (MAP_DATA
);
1720 s_even (int ignore ATTRIBUTE_UNUSED
)
1722 /* Never make frag if expect extra pass. */
1724 frag_align (1, 0, 0);
1726 record_alignment (now_seg
, 1);
1728 demand_empty_rest_of_line ();
1731 /* Directives: Literal pools. */
1733 static literal_pool
*
1734 find_literal_pool (int size
)
1738 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1740 if (pool
->section
== now_seg
1741 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1748 static literal_pool
*
1749 find_or_make_literal_pool (int size
)
1751 /* Next literal pool ID number. */
1752 static unsigned int latest_pool_num
= 1;
1755 pool
= find_literal_pool (size
);
1759 /* Create a new pool. */
1760 pool
= XNEW (literal_pool
);
1764 /* Currently we always put the literal pool in the current text
1765 section. If we were generating "small" model code where we
1766 knew that all code and initialised data was within 1MB then
1767 we could output literals to mergeable, read-only data
1770 pool
->next_free_entry
= 0;
1771 pool
->section
= now_seg
;
1772 pool
->sub_section
= now_subseg
;
1774 pool
->next
= list_of_pools
;
1775 pool
->symbol
= NULL
;
1777 /* Add it to the list. */
1778 list_of_pools
= pool
;
1781 /* New pools, and emptied pools, will have a NULL symbol. */
1782 if (pool
->symbol
== NULL
)
1784 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1785 &zero_address_frag
, 0);
1786 pool
->id
= latest_pool_num
++;
1793 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1794 Return TRUE on success, otherwise return FALSE. */
1796 add_to_lit_pool (expressionS
*exp
, int size
)
1801 pool
= find_or_make_literal_pool (size
);
1803 /* Check if this literal value is already in the pool. */
1804 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1806 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1808 if ((litexp
->X_op
== exp
->X_op
)
1809 && (exp
->X_op
== O_constant
)
1810 && (litexp
->X_add_number
== exp
->X_add_number
)
1811 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1814 if ((litexp
->X_op
== exp
->X_op
)
1815 && (exp
->X_op
== O_symbol
)
1816 && (litexp
->X_add_number
== exp
->X_add_number
)
1817 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1818 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1822 /* Do we need to create a new entry? */
1823 if (entry
== pool
->next_free_entry
)
1825 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1827 set_syntax_error (_("literal pool overflow"));
1831 pool
->literals
[entry
].exp
= *exp
;
1832 pool
->next_free_entry
+= 1;
1833 if (exp
->X_op
== O_big
)
1835 /* PR 16688: Bignums are held in a single global array. We must
1836 copy and preserve that value now, before it is overwritten. */
1837 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1839 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1840 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1843 pool
->literals
[entry
].bignum
= NULL
;
1846 exp
->X_op
= O_symbol
;
1847 exp
->X_add_number
= ((int) entry
) * size
;
1848 exp
->X_add_symbol
= pool
->symbol
;
1853 /* Can't use symbol_new here, so have to create a symbol and then at
1854 a later date assign it a value. That's what these functions do. */
1857 symbol_locate (symbolS
* symbolP
,
1858 const char *name
,/* It is copied, the caller can modify. */
1859 segT segment
, /* Segment identifier (SEG_<something>). */
1860 valueT valu
, /* Symbol value. */
1861 fragS
* frag
) /* Associated fragment. */
1864 char *preserved_copy_of_name
;
1866 name_length
= strlen (name
) + 1; /* +1 for \0. */
1867 obstack_grow (¬es
, name
, name_length
);
1868 preserved_copy_of_name
= obstack_finish (¬es
);
1870 #ifdef tc_canonicalize_symbol_name
1871 preserved_copy_of_name
=
1872 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1875 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1877 S_SET_SEGMENT (symbolP
, segment
);
1878 S_SET_VALUE (symbolP
, valu
);
1879 symbol_clear_list_pointers (symbolP
);
1881 symbol_set_frag (symbolP
, frag
);
1883 /* Link to end of symbol chain. */
1885 extern int symbol_table_frozen
;
1887 if (symbol_table_frozen
)
1891 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1893 obj_symbol_new_hook (symbolP
);
1895 #ifdef tc_symbol_new_hook
1896 tc_symbol_new_hook (symbolP
);
1900 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1901 #endif /* DEBUG_SYMS */
1906 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1913 for (align
= 2; align
<= 4; align
++)
1915 int size
= 1 << align
;
1917 pool
= find_literal_pool (size
);
1918 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1921 /* Align pool as you have word accesses.
1922 Only make a frag if we have to. */
1924 frag_align (align
, 0, 0);
1926 mapping_state (MAP_DATA
);
1928 record_alignment (now_seg
, align
);
1930 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1932 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1933 (valueT
) frag_now_fix (), frag_now
);
1934 symbol_table_insert (pool
->symbol
);
1936 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1938 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1940 if (exp
->X_op
== O_big
)
1942 /* PR 16688: Restore the global bignum value. */
1943 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1944 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1945 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1948 /* First output the expression in the instruction to the pool. */
1949 emit_expr (exp
, size
); /* .word|.xword */
1951 if (exp
->X_op
== O_big
)
1953 free (pool
->literals
[entry
].bignum
);
1954 pool
->literals
[entry
].bignum
= NULL
;
1958 /* Mark the pool as empty. */
1959 pool
->next_free_entry
= 0;
1960 pool
->symbol
= NULL
;
1965 /* Forward declarations for functions below, in the MD interface
1967 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1968 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1970 /* Directives: Data. */
1971 /* N.B. the support for relocation suffix in this directive needs to be
1972 implemented properly. */
1975 s_aarch64_elf_cons (int nbytes
)
1979 #ifdef md_flush_pending_output
1980 md_flush_pending_output ();
1983 if (is_it_end_of_statement ())
1985 demand_empty_rest_of_line ();
1989 #ifdef md_cons_align
1990 md_cons_align (nbytes
);
1993 mapping_state (MAP_DATA
);
1996 struct reloc_table_entry
*reloc
;
2000 if (exp
.X_op
!= O_symbol
)
2001 emit_expr (&exp
, (unsigned int) nbytes
);
2004 skip_past_char (&input_line_pointer
, '#');
2005 if (skip_past_char (&input_line_pointer
, ':'))
2007 reloc
= find_reloc_table_entry (&input_line_pointer
);
2009 as_bad (_("unrecognized relocation suffix"));
2011 as_bad (_("unimplemented relocation suffix"));
2012 ignore_rest_of_line ();
2016 emit_expr (&exp
, (unsigned int) nbytes
);
2019 while (*input_line_pointer
++ == ',');
2021 /* Put terminator back into stream. */
2022 input_line_pointer
--;
2023 demand_empty_rest_of_line ();
2026 /* Mark symbol that it follows a variant PCS convention. */
2029 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2035 elf_symbol_type
*elfsym
;
2037 c
= get_symbol_name (&name
);
2039 as_bad (_("Missing symbol name in directive"));
2040 sym
= symbol_find_or_make (name
);
2041 restore_line_pointer (c
);
2042 demand_empty_rest_of_line ();
2043 bfdsym
= symbol_get_bfdsym (sym
);
2044 elfsym
= elf_symbol_from (bfdsym
);
2045 gas_assert (elfsym
);
2046 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2048 #endif /* OBJ_ELF */
2050 /* Output a 32-bit word, but mark as an instruction. */
2053 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2057 #ifdef md_flush_pending_output
2058 md_flush_pending_output ();
2061 if (is_it_end_of_statement ())
2063 demand_empty_rest_of_line ();
2067 /* Sections are assumed to start aligned. In executable section, there is no
2068 MAP_DATA symbol pending. So we only align the address during
2069 MAP_DATA --> MAP_CUR_INSN transition.
2070 For other sections, this is not guaranteed. */
2071 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2072 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2073 frag_align_code (2, 0);
2076 mapping_state (MAP_CUR_INSN
);
2082 if (exp
.X_op
!= O_constant
)
2084 as_bad (_("constant expression required"));
2085 ignore_rest_of_line ();
2089 if (target_big_endian
)
2091 unsigned int val
= exp
.X_add_number
;
2092 exp
.X_add_number
= SWAP_32 (val
);
2094 emit_expr (&exp
, 4);
2096 while (*input_line_pointer
++ == ',');
2098 /* Put terminator back into stream. */
2099 input_line_pointer
--;
2100 demand_empty_rest_of_line ();
2104 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2106 demand_empty_rest_of_line ();
2107 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2108 fde
->entry_extras
.pauth_key
= AARCH64_PAUTH_KEY_B
;
2112 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2115 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2121 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2122 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2124 demand_empty_rest_of_line ();
2127 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2130 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2134 /* Since we're just labelling the code, there's no need to define a
2137 /* Make sure there is enough room in this frag for the following
2138 blr. This trick only works if the blr follows immediately after
2139 the .tlsdesc directive. */
2141 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2142 (IS_C64
? BFD_RELOC_MORELLO_TLSDESC_CALL
2143 : BFD_RELOC_AARCH64_TLSDESC_CALL
));
2145 demand_empty_rest_of_line ();
2148 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2151 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2157 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2158 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2160 demand_empty_rest_of_line ();
2164 s_aarch64_capinit (int ignored ATTRIBUTE_UNUSED
)
2169 /* align to 16 bytes. */
2170 do_align (4, (char *) NULL
, 0, 0);
2173 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 16, &exp
, 0,
2174 BFD_RELOC_MORELLO_CAPINIT
);
2176 demand_empty_rest_of_line ();
2180 s_aarch64_chericap (int ignored ATTRIBUTE_UNUSED
)
2185 #ifdef md_flush_pending_output
2186 md_flush_pending_output ();
2189 /* align to 16 bytes. */
2190 do_align (4, (char *) NULL
, 0, 0);
2193 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 16, &exp
, 0,
2194 BFD_RELOC_MORELLO_CAPINIT
);
2196 mapping_state (MAP_DATA
);
2198 for (i
= 0; i
< 4; i
++)
2200 /* The documentation of our md_number_to_chars says the greatest value
2201 size it can handle is 4 bytes. */
2202 char *p
= frag_more (4);
2203 md_number_to_chars (p
, 0, 4);
2205 demand_empty_rest_of_line ();
2207 #endif /* OBJ_ELF */
2209 static void s_aarch64_arch (int);
2210 static void s_aarch64_cpu (int);
2211 static void s_aarch64_arch_extension (int);
2213 /* This table describes all the machine specific pseudo-ops the assembler
2214 has to support. The fields are:
2215 pseudo-op name without dot
2216 function to call to execute this pseudo-op
2217 Integer arg to pass to the function. */
2219 const pseudo_typeS md_pseudo_table
[] = {
2220 /* Never called because '.req' does not start a line. */
2222 {"unreq", s_unreq
, 0},
2224 {"even", s_even
, 0},
2225 {"ltorg", s_ltorg
, 0},
2226 {"pool", s_ltorg
, 0},
2227 {"cpu", s_aarch64_cpu
, 0},
2228 {"arch", s_aarch64_arch
, 0},
2229 {"arch_extension", s_aarch64_arch_extension
, 0},
2230 {"inst", s_aarch64_inst
, 0},
2231 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2233 {"tlsdescadd", s_tlsdescadd
, 0},
2234 {"tlsdesccall", s_tlsdesccall
, 0},
2235 {"tlsdescldr", s_tlsdescldr
, 0},
2236 {"word", s_aarch64_elf_cons
, 4},
2237 {"long", s_aarch64_elf_cons
, 4},
2238 {"xword", s_aarch64_elf_cons
, 8},
2239 {"dword", s_aarch64_elf_cons
, 8},
2240 {"variant_pcs", s_variant_pcs
, 0},
2241 {"capinit", s_aarch64_capinit
, 0},
2242 {"chericap", s_aarch64_chericap
, 0},
2244 {"float16", float_cons
, 'h'},
2245 {"bfloat16", float_cons
, 'b'},
2250 /* Check whether STR points to a register name followed by a comma or the
2251 end of line; REG_TYPE indicates which register types are checked
2252 against. Return TRUE if STR is such a register name; otherwise return
2253 FALSE. The function does not intend to produce any diagnostics, but since
2254 the register parser aarch64_reg_parse, which is called by this function,
2255 does produce diagnostics, we call clear_error to clear any diagnostics
2256 that may be generated by aarch64_reg_parse.
2257 Also, the function returns FALSE directly if there is any user error
2258 present at the function entry. This prevents the existing diagnostics
2259 state from being spoiled.
2260 The function currently serves parse_constant_immediate and
2261 parse_big_immediate only. */
2263 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2267 /* Prevent the diagnostics state from being spoiled. */
2271 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2273 /* Clear the parsing error that may be set by the reg parser. */
2276 if (reg
== PARSE_FAIL
)
2279 skip_whitespace (str
);
2280 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2286 /* Parser functions used exclusively in instruction operands. */
2288 /* Parse an immediate expression which may not be constant.
2290 To prevent the expression parser from pushing a register name
2291 into the symbol table as an undefined symbol, firstly a check is
2292 done to find out whether STR is a register of type REG_TYPE followed
2293 by a comma or the end of line. Return FALSE if STR is such a string. */
2296 parse_immediate_expression (char **str
, expressionS
*exp
,
2297 aarch64_reg_type reg_type
)
2299 if (reg_name_p (*str
, reg_type
))
2301 set_recoverable_error (_("immediate operand required"));
2305 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2307 if (exp
->X_op
== O_absent
)
2309 set_fatal_syntax_error (_("missing immediate expression"));
2316 /* Constant immediate-value read function for use in insn parsing.
2317 STR points to the beginning of the immediate (with the optional
2318 leading #); *VAL receives the value. REG_TYPE says which register
2319 names should be treated as registers rather than as symbolic immediates.
2321 Return TRUE on success; otherwise return FALSE. */
2324 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2328 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2331 if (exp
.X_op
!= O_constant
)
2333 set_syntax_error (_("constant expression required"));
2337 *val
= exp
.X_add_number
;
2342 encode_imm_float_bits (uint32_t imm
)
2344 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2345 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2348 /* Return TRUE if the single-precision floating-point value encoded in IMM
2349 can be expressed in the AArch64 8-bit signed floating-point format with
2350 3-bit exponent and normalized 4 bits of precision; in other words, the
2351 floating-point value must be expressable as
2352 (+/-) n / 16 * power (2, r)
2353 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2356 aarch64_imm_float_p (uint32_t imm
)
2358 /* If a single-precision floating-point value has the following bit
2359 pattern, it can be expressed in the AArch64 8-bit floating-point
2362 3 32222222 2221111111111
2363 1 09876543 21098765432109876543210
2364 n Eeeeeexx xxxx0000000000000000000
2366 where n, e and each x are either 0 or 1 independently, with
2371 /* Prepare the pattern for 'Eeeeee'. */
2372 if (((imm
>> 30) & 0x1) == 0)
2373 pattern
= 0x3e000000;
2375 pattern
= 0x40000000;
2377 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2378 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2381 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2382 as an IEEE float without any loss of precision. Store the value in
2386 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2388 /* If a double-precision floating-point value has the following bit
2389 pattern, it can be expressed in a float:
2391 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2392 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2393 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2395 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2396 if Eeee_eeee != 1111_1111
2398 where n, e, s and S are either 0 or 1 independently and where ~ is the
2402 uint32_t high32
= imm
>> 32;
2403 uint32_t low32
= imm
;
2405 /* Lower 29 bits need to be 0s. */
2406 if ((imm
& 0x1fffffff) != 0)
2409 /* Prepare the pattern for 'Eeeeeeeee'. */
2410 if (((high32
>> 30) & 0x1) == 0)
2411 pattern
= 0x38000000;
2413 pattern
= 0x40000000;
2416 if ((high32
& 0x78000000) != pattern
)
2419 /* Check Eeee_eeee != 1111_1111. */
2420 if ((high32
& 0x7ff00000) == 0x47f00000)
2423 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2424 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2425 | (low32
>> 29)); /* 3 S bits. */
2429 /* Return true if we should treat OPERAND as a double-precision
2430 floating-point operand rather than a single-precision one. */
2432 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2434 /* Check for unsuffixed SVE registers, which are allowed
2435 for LDR and STR but not in instructions that require an
2436 immediate. We get better error messages if we arbitrarily
2437 pick one size, parse the immediate normally, and then
2438 report the match failure in the normal way. */
2439 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2440 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2443 /* Parse a floating-point immediate. Return TRUE on success and return the
2444 value in *IMMED in the format of IEEE754 single-precision encoding.
2445 *CCP points to the start of the string; DP_P is TRUE when the immediate
2446 is expected to be in double-precision (N.B. this only matters when
2447 hexadecimal representation is involved). REG_TYPE says which register
2448 names should be treated as registers rather than as symbolic immediates.
2450 This routine accepts any IEEE float; it is up to the callers to reject
2454 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2455 aarch64_reg_type reg_type
)
2459 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2461 unsigned fpword
= 0;
2462 bfd_boolean hex_p
= FALSE
;
2464 skip_past_char (&str
, '#');
2467 skip_whitespace (fpnum
);
2469 if (strncmp (fpnum
, "0x", 2) == 0)
2471 /* Support the hexadecimal representation of the IEEE754 encoding.
2472 Double-precision is expected when DP_P is TRUE, otherwise the
2473 representation should be in single-precision. */
2474 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2479 if (!can_convert_double_to_float (val
, &fpword
))
2482 else if ((uint64_t) val
> 0xffffffff)
2489 else if (reg_name_p (str
, reg_type
))
2491 set_recoverable_error (_("immediate operand required"));
2499 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2502 /* Our FP word must be 32 bits (single-precision FP). */
2503 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2505 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2515 set_fatal_syntax_error (_("invalid floating-point constant"));
2519 /* Less-generic immediate-value read function with the possibility of loading
2520 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2523 To prevent the expression parser from pushing a register name into the
2524 symbol table as an undefined symbol, a check is firstly done to find
2525 out whether STR is a register of type REG_TYPE followed by a comma or
2526 the end of line. Return FALSE if STR is such a register. */
2529 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2533 if (reg_name_p (ptr
, reg_type
))
2535 set_syntax_error (_("immediate operand required"));
2539 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2541 if (inst
.reloc
.exp
.X_op
== O_constant
)
2542 *imm
= inst
.reloc
.exp
.X_add_number
;
2549 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2550 if NEED_LIBOPCODES is non-zero, the fixup will need
2551 assistance from the libopcodes. */
2554 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2555 const aarch64_opnd_info
*operand
,
2556 int need_libopcodes_p
)
2558 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2559 reloc
->opnd
= operand
->type
;
2560 if (need_libopcodes_p
)
2561 reloc
->need_libopcodes_p
= 1;
2564 /* Return TRUE if the instruction needs to be fixed up later internally by
2565 the GAS; otherwise return FALSE. */
2567 static inline bfd_boolean
2568 aarch64_gas_internal_fixup_p (void)
2570 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2573 /* Assign the immediate value to the relevant field in *OPERAND if
2574 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2575 needs an internal fixup in a later stage.
2576 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2577 IMM.VALUE that may get assigned with the constant. */
2579 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2580 aarch64_opnd_info
*operand
,
2582 int need_libopcodes_p
,
2585 if (reloc
->exp
.X_op
== O_constant
)
2588 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2590 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2591 reloc
->type
= BFD_RELOC_UNUSED
;
2595 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2596 /* Tell libopcodes to ignore this operand or not. This is helpful
2597 when one of the operands needs to be fixed up later but we need
2598 libopcodes to check the other operands. */
2599 operand
->skip
= skip_p
;
2603 /* Relocation modifiers. Each entry in the table contains the textual
2604 name for the relocation which may be placed before a symbol used as
2605 a load/store offset, or add immediate. It must be surrounded by a
2606 leading and trailing colon, for example:
2608 ldr x0, [x1, #:rello:varsym]
2609 add x0, x1, #:rello:varsym */
2611 struct reloc_table_entry
2615 bfd_reloc_code_real_type adr_type
;
2616 bfd_reloc_code_real_type adrp_type
;
2617 bfd_reloc_code_real_type c64_adrp_type
;
2618 bfd_reloc_code_real_type movw_type
;
2619 bfd_reloc_code_real_type add_type
;
2620 bfd_reloc_code_real_type ldst_type
;
2621 bfd_reloc_code_real_type ld_literal_type
;
2624 static struct reloc_table_entry reloc_table
[] = {
2625 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2631 BFD_RELOC_AARCH64_ADD_LO12
,
2632 BFD_RELOC_AARCH64_LDST_LO12
,
2635 /* Higher 21 bits of pc-relative page offset: ADRP */
2638 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2639 BFD_RELOC_MORELLO_ADR_HI20_PCREL
,
2645 /* Higher 21 bits (20 bits for C64) of pc-relative page offset: ADRP, no
2649 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2650 BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
,
2656 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2661 BFD_RELOC_AARCH64_MOVW_G0
,
2666 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2671 BFD_RELOC_AARCH64_MOVW_G0_S
,
2676 /* Less significant bits 0-15 of address/value: MOVK, no check */
2681 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2686 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2691 BFD_RELOC_AARCH64_MOVW_G1
,
2696 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2701 BFD_RELOC_AARCH64_MOVW_G1_S
,
2706 /* Less significant bits 16-31 of address/value: MOVK, no check */
2711 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2716 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2721 BFD_RELOC_AARCH64_MOVW_G2
,
2726 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2731 BFD_RELOC_AARCH64_MOVW_G2_S
,
2736 /* Less significant bits 32-47 of address/value: MOVK, no check */
2741 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2746 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2751 BFD_RELOC_AARCH64_MOVW_G3
,
2756 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2761 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2766 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2771 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2776 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2781 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2786 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2791 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2796 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2801 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2806 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2811 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2816 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2821 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2826 /* Get to the page containing GOT entry for a symbol. */
2829 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2830 BFD_RELOC_MORELLO_ADR_GOT_PAGE
,
2834 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2836 /* 12 bit offset into the page containing GOT entry for that symbol. */
2843 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2846 /* 0-15 bits of address/value: MOVk, no check. */
2851 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2856 /* Most significant bits 16-31 of address/value: MOVZ. */
2861 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2866 /* 15 bit offset into the page containing GOT entry for that symbol. */
2873 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2876 /* Get to the page containing GOT TLS entry for a symbol */
2877 {"gottprel_g0_nc", 0,
2881 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2886 /* Get to the page containing GOT TLS entry for a symbol */
2891 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2896 /* Get to the page containing GOT TLS entry for a symbol */
2898 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2899 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2906 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2912 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2916 /* Lower 16 bits address/value: MOVk. */
2921 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2926 /* Most significant bits 16-31 of address/value: MOVZ. */
2931 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2936 /* Get to the page containing GOT TLS entry for a symbol */
2938 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2939 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2940 BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20
,
2944 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2946 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2952 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2953 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2956 /* Get to the page containing GOT TLS entry for a symbol.
2957 The same as GD, we allocate two consecutive GOT slots
2958 for module index and module offset, the only difference
2959 with GD is the module offset should be initialized to
2960 zero without any outstanding runtime relocation. */
2962 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2963 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2970 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2971 {"tlsldm_lo12_nc", 0,
2976 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2980 /* 12 bit offset into the module TLS base address. */
2986 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2987 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2990 /* Same as dtprel_lo12, no overflow check. */
2991 {"dtprel_lo12_nc", 0,
2996 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2997 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3000 /* bits[23:12] of offset to the module TLS base address. */
3006 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3010 /* bits[15:0] of offset to the module TLS base address. */
3015 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3020 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3025 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3030 /* bits[31:16] of offset to the module TLS base address. */
3035 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3040 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3045 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3050 /* bits[47:32] of offset to the module TLS base address. */
3055 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3060 /* Lower 16 bit offset into GOT entry for a symbol */
3061 {"tlsdesc_off_g0_nc", 0,
3065 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3070 /* Higher 16 bit offset into GOT entry for a symbol */
3071 {"tlsdesc_off_g1", 0,
3075 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3080 /* Get to the page containing GOT TLS entry for a symbol */
3083 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3084 BFD_RELOC_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20
,
3088 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3090 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3091 {"gottprel_lo12", 0,
3096 BFD_RELOC_MORELLO_TLSIE_ADD_LO12
,
3097 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3100 /* Get tp offset for a symbol. */
3106 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3110 /* Get tp offset for a symbol. */
3116 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3117 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3120 /* Get tp offset for a symbol. */
3126 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3130 /* Get tp offset for a symbol. */
3131 {"tprel_lo12_nc", 0,
3136 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3137 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3140 /* Most significant bits 32-47 of address/value: MOVZ. */
3145 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3150 /* Most significant bits 16-31 of address/value: MOVZ. */
3155 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3160 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3165 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3170 /* Most significant bits 0-15 of address/value: MOVZ. */
3175 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3180 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3185 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3190 /* 15bit offset from got entry to base address of GOT table. */
3197 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3200 /* 14bit offset from got entry to base address of GOT table. */
3207 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3210 /* Most significant bits 0-15 of the size of a symbol: MOVZ */
3215 BFD_RELOC_MORELLO_MOVW_SIZE_G0
,
3220 /* Less significant bits 0-15 of the size of a symbol: MOVK, no check */
3225 BFD_RELOC_MORELLO_MOVW_SIZE_G0_NC
,
3230 /* Most significant bits 16-31 of the size of a symbol: MOVZ */
3235 BFD_RELOC_MORELLO_MOVW_SIZE_G1
,
3240 /* Less significant bits 16-31 of the size of a symbol: MOVK, no check */
3245 BFD_RELOC_MORELLO_MOVW_SIZE_G1_NC
,
3250 /* Most significant bits 32-47 of the size of a symbol: MOVZ */
3255 BFD_RELOC_MORELLO_MOVW_SIZE_G2
,
3260 /* Less significant bits 32-47 of the size of a symbol: MOVK, no check */
3265 BFD_RELOC_MORELLO_MOVW_SIZE_G2_NC
,
3270 /* Most significant bits 48-63 of the size of a symbol: MOVZ */
3275 BFD_RELOC_MORELLO_MOVW_SIZE_G3
,
3282 /* Given the address of a pointer pointing to the textual name of a
3283 relocation as may appear in assembler source, attempt to find its
3284 details in reloc_table. The pointer will be updated to the character
3285 after the trailing colon. On failure, NULL will be returned;
3286 otherwise return the reloc_table_entry. */
3288 static struct reloc_table_entry
*
3289 find_reloc_table_entry (char **str
)
3292 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3294 int length
= strlen (reloc_table
[i
].name
);
3296 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3297 && (*str
)[length
] == ':')
3299 *str
+= (length
+ 1);
3300 return &reloc_table
[i
];
3307 /* Mode argument to parse_shift and parser_shifter_operand. */
3308 enum parse_shift_mode
3310 SHIFTED_NONE
, /* no shifter allowed */
3311 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3313 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3315 SHIFTED_LSL
, /* bare "lsl #n" */
3316 SHIFTED_MUL
, /* bare "mul #n" */
3317 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3318 SHIFTED_MUL_VL
, /* "mul vl" */
3319 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3322 /* Parse a <shift> operator on an AArch64 data processing instruction.
3323 Return TRUE on success; otherwise return FALSE. */
3325 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3327 const struct aarch64_name_value_pair
*shift_op
;
3328 enum aarch64_modifier_kind kind
;
3334 for (p
= *str
; ISALPHA (*p
); p
++)
3339 set_syntax_error (_("shift expression expected"));
3343 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3345 if (shift_op
== NULL
)
3347 set_syntax_error (_("shift operator expected"));
3351 kind
= aarch64_get_operand_modifier (shift_op
);
3353 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3355 set_syntax_error (_("invalid use of 'MSL'"));
3359 if (kind
== AARCH64_MOD_MUL
3360 && mode
!= SHIFTED_MUL
3361 && mode
!= SHIFTED_MUL_VL
)
3363 set_syntax_error (_("invalid use of 'MUL'"));
3369 case SHIFTED_LOGIC_IMM
:
3370 if (aarch64_extend_operator_p (kind
))
3372 set_syntax_error (_("extending shift is not permitted"));
3377 case SHIFTED_ARITH_IMM
:
3378 if (kind
== AARCH64_MOD_ROR
)
3380 set_syntax_error (_("'ROR' shift is not permitted"));
3386 if (kind
!= AARCH64_MOD_LSL
)
3388 set_syntax_error (_("only 'LSL' shift is permitted"));
3394 if (kind
!= AARCH64_MOD_MUL
)
3396 set_syntax_error (_("only 'MUL' is permitted"));
3401 case SHIFTED_MUL_VL
:
3402 /* "MUL VL" consists of two separate tokens. Require the first
3403 token to be "MUL" and look for a following "VL". */
3404 if (kind
== AARCH64_MOD_MUL
)
3406 skip_whitespace (p
);
3407 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3410 kind
= AARCH64_MOD_MUL_VL
;
3414 set_syntax_error (_("only 'MUL VL' is permitted"));
3417 case SHIFTED_REG_OFFSET
:
3418 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3419 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3421 set_fatal_syntax_error
3422 (_("invalid shift for the register offset addressing mode"));
3427 case SHIFTED_LSL_MSL
:
3428 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3430 set_syntax_error (_("invalid shift operator"));
3439 /* Whitespace can appear here if the next thing is a bare digit. */
3440 skip_whitespace (p
);
3442 /* Parse shift amount. */
3444 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3445 exp
.X_op
= O_absent
;
3448 if (is_immediate_prefix (*p
))
3453 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3455 if (kind
== AARCH64_MOD_MUL_VL
)
3456 /* For consistency, give MUL VL the same shift amount as an implicit
3458 operand
->shifter
.amount
= 1;
3459 else if (exp
.X_op
== O_absent
)
3461 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3463 set_syntax_error (_("missing shift amount"));
3466 operand
->shifter
.amount
= 0;
3468 else if (exp
.X_op
== O_big
)
3470 set_fatal_syntax_error (_("shift amount out of range"));
3473 else if (exp
.X_op
!= O_constant
)
3475 set_syntax_error (_("constant shift amount required"));
3478 /* For parsing purposes, MUL #n has no inherent range. The range
3479 depends on the operand and will be checked by operand-specific
3481 else if (kind
!= AARCH64_MOD_MUL
3482 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3484 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3489 operand
->shifter
.amount
= exp
.X_add_number
;
3490 operand
->shifter
.amount_present
= 1;
3493 operand
->shifter
.operator_present
= 1;
3494 operand
->shifter
.kind
= kind
;
3500 /* Parse a <shifter_operand> for a data processing instruction:
3503 #<immediate>, LSL #imm
3505 Validation of immediate operands is deferred to md_apply_fix.
3507 Return TRUE on success; otherwise return FALSE. */
3510 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3511 enum parse_shift_mode mode
)
3515 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3520 /* Accept an immediate expression. */
3521 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3524 /* Accept optional LSL for arithmetic immediate values. */
3525 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3526 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3529 /* Not accept any shifter for logical immediate values. */
3530 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3531 && parse_shift (&p
, operand
, mode
))
3533 set_syntax_error (_("unexpected shift operator"));
3541 /* Parse a <shifter_operand> for a data processing instruction:
3546 #<immediate>, LSL #imm
3548 where <shift> is handled by parse_shift above, and the last two
3549 cases are handled by the function above.
3551 Validation of immediate operands is deferred to md_apply_fix.
3553 Return TRUE on success; otherwise return FALSE. */
3556 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3557 enum parse_shift_mode mode
)
3559 const reg_entry
*reg
;
3560 aarch64_opnd_qualifier_t qualifier
;
3561 enum aarch64_operand_class opd_class
3562 = aarch64_get_operand_class (operand
->type
);
3564 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3567 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3569 set_syntax_error (_("unexpected register in the immediate operand"));
3573 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3575 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3579 operand
->reg
.regno
= reg
->number
;
3580 operand
->qualifier
= qualifier
;
3582 /* Accept optional shift operation on register. */
3583 if (! skip_past_comma (str
))
3586 if (! parse_shift (str
, operand
, mode
))
3591 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3594 (_("integer register expected in the extended/shifted operand "
3599 /* We have a shifted immediate variable. */
3600 return parse_shifter_operand_imm (str
, operand
, mode
);
3603 /* Return TRUE on success; return FALSE otherwise. */
3606 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3607 enum parse_shift_mode mode
)
3611 /* Determine if we have the sequence of characters #: or just :
3612 coming next. If we do, then we check for a :rello: relocation
3613 modifier. If we don't, punt the whole lot to
3614 parse_shifter_operand. */
3616 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3618 struct reloc_table_entry
*entry
;
3626 /* Try to parse a relocation. Anything else is an error. */
3627 if (!(entry
= find_reloc_table_entry (str
)))
3629 set_syntax_error (_("unknown relocation modifier"));
3633 if (entry
->add_type
== 0)
3636 (_("this relocation modifier is not allowed on this instruction"));
3639 if (entry
->add_type
== BFD_RELOC_MORELLO_TLSIE_ADD_LO12
&& !IS_C64
)
3642 (_("this relocation modifier is not allowed in non-C64 mode"));
3646 /* Save str before we decompose it. */
3649 /* Next, we parse the expression. */
3650 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3653 /* Record the relocation type (use the ADD variant here). */
3654 inst
.reloc
.type
= entry
->add_type
;
3655 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3657 /* If str is empty, we've reached the end, stop here. */
3661 /* Otherwise, we have a shifted reloc modifier, so rewind to
3662 recover the variable name and continue parsing for the shifter. */
3664 return parse_shifter_operand_imm (str
, operand
, mode
);
3667 return parse_shifter_operand (str
, operand
, mode
);
3670 /* Parse all forms of an address expression. Information is written
3671 to *OPERAND and/or inst.reloc.
3673 The A64 instruction set has the following addressing modes:
3676 [base] // in SIMD ld/st structure
3677 [base{,#0}] // in ld/st exclusive
3679 [base,Xm{,LSL #imm}]
3680 [base,Xm,SXTX {#imm}]
3681 [base,Wm,(S|U)XTW {#imm}]
3683 [base]! // in ldraa/ldrab exclusive
3687 [base],Xm // in SIMD ld/st structure
3688 PC-relative (literal)
3692 [base,Zm.D{,LSL #imm}]
3693 [base,Zm.S,(S|U)XTW {#imm}]
3694 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3698 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3699 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3700 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3702 (As a convenience, the notation "=immediate" is permitted in conjunction
3703 with the pc-relative literal load instructions to automatically place an
3704 immediate value or symbolic address in a nearby literal pool and generate
3705 a hidden label which references it.)
3707 Upon a successful parsing, the address structure in *OPERAND will be
3708 filled in the following way:
3710 .base_regno = <base>
3711 .offset.is_reg // 1 if the offset is a register
3713 .offset.regno = <Rm>
3715 For different addressing modes defined in the A64 ISA:
3718 .pcrel=0; .preind=1; .postind=0; .writeback=0
3720 .pcrel=0; .preind=1; .postind=0; .writeback=1
3722 .pcrel=0; .preind=0; .postind=1; .writeback=1
3723 PC-relative (literal)
3724 .pcrel=1; .preind=1; .postind=0; .writeback=0
3726 The shift/extension information, if any, will be stored in .shifter.
3727 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3728 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3729 corresponding register.
3731 BASE_TYPE says which types of base register should be accepted and
3732 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3733 is the type of shifter that is allowed for immediate offsets,
3734 or SHIFTED_NONE if none.
3736 In all other respects, it is the caller's responsibility to check
3737 for addressing modes not supported by the instruction, and to set
3741 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3742 aarch64_opnd_qualifier_t
*base_qualifier
,
3743 aarch64_opnd_qualifier_t
*offset_qualifier
,
3744 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3745 enum parse_shift_mode imm_shift_mode
)
3748 const reg_entry
*reg
;
3749 expressionS
*exp
= &inst
.reloc
.exp
;
3751 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3752 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3753 if (! skip_past_char (&p
, '['))
3755 /* =immediate or label. */
3756 operand
->addr
.pcrel
= 1;
3757 operand
->addr
.preind
= 1;
3759 /* #:<reloc_op>:<symbol> */
3760 skip_past_char (&p
, '#');
3761 if (skip_past_char (&p
, ':'))
3763 bfd_reloc_code_real_type ty
;
3764 struct reloc_table_entry
*entry
;
3766 /* Try to parse a relocation modifier. Anything else is
3768 entry
= find_reloc_table_entry (&p
);
3771 set_syntax_error (_("unknown relocation modifier"));
3775 switch (operand
->type
)
3777 case AARCH64_OPND_ADDR_PCREL21
:
3779 ty
= entry
->adr_type
;
3783 ty
= entry
->ld_literal_type
;
3790 (_("this relocation modifier is not allowed on this "
3796 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3798 set_syntax_error (_("invalid relocation expression"));
3802 /* #:<reloc_op>:<expr> */
3803 /* Record the relocation type. */
3804 inst
.reloc
.type
= ty
;
3805 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3810 if (skip_past_char (&p
, '='))
3811 /* =immediate; need to generate the literal in the literal pool. */
3812 inst
.gen_lit_pool
= 1;
3814 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3816 set_syntax_error (_("invalid address"));
3827 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3828 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3830 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3833 operand
->addr
.base_regno
= reg
->number
;
3836 if (skip_past_comma (&p
))
3839 operand
->addr
.preind
= 1;
3841 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3844 if (!aarch64_check_reg_type (reg
, offset_type
))
3846 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3851 operand
->addr
.offset
.regno
= reg
->number
;
3852 operand
->addr
.offset
.is_reg
= 1;
3853 /* Shifted index. */
3854 if (skip_past_comma (&p
))
3857 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3858 /* Use the diagnostics set in parse_shift, so not set new
3859 error message here. */
3863 [base,Xm] # For vector plus scalar SVE2 indexing.
3864 [base,Xm{,LSL #imm}]
3865 [base,Xm,SXTX {#imm}]
3866 [base,Wm,(S|U)XTW {#imm}] */
3867 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3868 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3869 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3871 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3873 set_syntax_error (_("invalid use of 32-bit register offset"));
3876 if (aarch64_get_qualifier_esize (*base_qualifier
)
3877 != aarch64_get_qualifier_esize (*offset_qualifier
)
3878 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3879 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3880 || *offset_qualifier
!= AARCH64_OPND_QLF_X
)
3881 /* Capabilities can have W as well as X registers as
3883 && (*base_qualifier
!= AARCH64_OPND_QLF_CA
))
3885 set_syntax_error (_("offset has different size from base"));
3889 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3891 set_syntax_error (_("invalid use of 64-bit register offset"));
3897 /* [Xn,#:<reloc_op>:<symbol> */
3898 skip_past_char (&p
, '#');
3899 if (skip_past_char (&p
, ':'))
3901 struct reloc_table_entry
*entry
;
3903 /* Try to parse a relocation modifier. Anything else is
3905 if (!(entry
= find_reloc_table_entry (&p
)))
3907 set_syntax_error (_("unknown relocation modifier"));
3911 if (entry
->ldst_type
== 0)
3914 (_("this relocation modifier is not allowed on this "
3919 /* [Xn,#:<reloc_op>: */
3920 /* We now have the group relocation table entry corresponding to
3921 the name in the assembler source. Next, we parse the
3923 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3925 set_syntax_error (_("invalid relocation expression"));
3929 /* [Xn,#:<reloc_op>:<expr> */
3930 /* Record the load/store relocation type. */
3931 inst
.reloc
.type
= entry
->ldst_type
;
3932 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3936 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3938 set_syntax_error (_("invalid expression in the address"));
3942 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3943 /* [Xn,<expr>,<shifter> */
3944 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3950 if (! skip_past_char (&p
, ']'))
3952 set_syntax_error (_("']' expected"));
3956 if (skip_past_char (&p
, '!'))
3958 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3960 set_syntax_error (_("register offset not allowed in pre-indexed "
3961 "addressing mode"));
3965 operand
->addr
.writeback
= 1;
3967 else if (skip_past_comma (&p
))
3970 operand
->addr
.postind
= 1;
3971 operand
->addr
.writeback
= 1;
3973 if (operand
->addr
.preind
)
3975 set_syntax_error (_("cannot combine pre- and post-indexing"));
3979 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3983 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3985 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3989 operand
->addr
.offset
.regno
= reg
->number
;
3990 operand
->addr
.offset
.is_reg
= 1;
3992 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3995 set_syntax_error (_("invalid expression in the address"));
4000 /* If at this point neither .preind nor .postind is set, we have a
4001 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4002 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4003 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4005 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4007 if (operand
->addr
.writeback
)
4009 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4011 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4012 operand
->addr
.offset
.is_reg
= 0;
4013 operand
->addr
.offset
.imm
= 0;
4014 operand
->addr
.preind
= 1;
4019 set_syntax_error (_("missing offset in the pre-indexed address"));
4025 operand
->addr
.preind
= 1;
4026 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4028 operand
->addr
.offset
.is_reg
= 1;
4029 operand
->addr
.offset
.regno
= REG_ZR
;
4030 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4034 inst
.reloc
.exp
.X_op
= O_constant
;
4035 inst
.reloc
.exp
.X_add_number
= 0;
4044 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4047 parse_address (char **str
, aarch64_opnd_info
*operand
)
4049 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4051 aarch64_reg_type base
;
4053 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
))
4054 base
= REG_TYPE_CA_N_SP
;
4056 base
= REG_TYPE_R64_SP
;
4058 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4059 base
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4062 /* Parse a base capability address. Return TRUE on success. */
4064 parse_cap_address (char **str
, aarch64_opnd_info
*operand
,
4065 enum aarch64_insn_class
class)
4067 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4068 aarch64_reg_type base
;
4070 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
)
4071 && class != br_capaddr
)
4072 base
= REG_TYPE_R64_SP
;
4074 base
= REG_TYPE_CA_N_SP
;
4076 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4077 base
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4080 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4081 The arguments have the same meaning as for parse_address_main.
4082 Return TRUE on success. */
4084 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4085 aarch64_opnd_qualifier_t
*base_qualifier
,
4086 aarch64_opnd_qualifier_t
*offset_qualifier
)
4088 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4089 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4093 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4094 Return TRUE on success; otherwise return FALSE. */
4096 parse_half (char **str
, int *internal_fixup_p
)
4100 skip_past_char (&p
, '#');
4102 gas_assert (internal_fixup_p
);
4103 *internal_fixup_p
= 0;
4107 struct reloc_table_entry
*entry
;
4109 /* Try to parse a relocation. Anything else is an error. */
4111 if (!(entry
= find_reloc_table_entry (&p
)))
4113 set_syntax_error (_("unknown relocation modifier"));
4117 if (entry
->movw_type
== 0)
4120 (_("this relocation modifier is not allowed on this instruction"));
4124 inst
.reloc
.type
= entry
->movw_type
;
4127 *internal_fixup_p
= 1;
4129 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
4132 bfd_boolean is_morello_size_reloc
4133 = (inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G0
4134 || inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G0_NC
4135 || inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G1
4136 || inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G1_NC
4137 || inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G2
4138 || inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G2_NC
4139 || inst
.reloc
.type
== BFD_RELOC_MORELLO_MOVW_SIZE_G3
);
4140 if (inst
.reloc
.exp
.X_add_symbol
== 0 && is_morello_size_reloc
)
4143 (_("size relocation is not allowed on non-symbol expression"));
4146 if (is_morello_size_reloc
&& !IS_C64
)
4148 set_syntax_error (_("size relocation is not allowed in non-C64 mode"));
4156 /* Parse an operand for an ADRP instruction:
4158 Return TRUE on success; otherwise return FALSE. */
4161 parse_adrp (char **str
)
4168 struct reloc_table_entry
*entry
;
4169 bfd_reloc_code_real_type adrp_type
;
4171 /* Try to parse a relocation. Anything else is an error. */
4173 if (!(entry
= find_reloc_table_entry (&p
)))
4175 set_syntax_error (_("unknown relocation modifier"));
4179 adrp_type
= (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
)
4180 ? entry
->c64_adrp_type
: entry
->adrp_type
);
4185 (_("this relocation modifier is not allowed on this instruction"));
4189 inst
.reloc
.type
= adrp_type
;
4192 inst
.reloc
.type
= (AARCH64_CPU_HAS_FEATURE (cpu_variant
,
4193 AARCH64_FEATURE_C64
)
4194 ? BFD_RELOC_MORELLO_ADR_HI20_PCREL
4195 : BFD_RELOC_AARCH64_ADR_HI21_PCREL
);
4197 inst
.reloc
.pc_rel
= 1;
4199 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
4206 /* Miscellaneous. */
4208 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4209 of SIZE tokens in which index I gives the token for field value I,
4210 or is null if field value I is invalid. REG_TYPE says which register
4211 names should be treated as registers rather than as symbolic immediates.
4213 Return true on success, moving *STR past the operand and storing the
4214 field value in *VAL. */
4217 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4218 size_t size
, aarch64_reg_type reg_type
)
4224 /* Match C-like tokens. */
4226 while (ISALNUM (*q
))
4229 for (i
= 0; i
< size
; ++i
)
4231 && strncasecmp (array
[i
], p
, q
- p
) == 0
4232 && array
[i
][q
- p
] == 0)
4239 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4242 if (exp
.X_op
== O_constant
4243 && (uint64_t) exp
.X_add_number
< size
)
4245 *val
= exp
.X_add_number
;
4250 /* Use the default error for this operand. */
4254 /* Parse an option for a preload instruction. Returns the encoding for the
4255 option, or PARSE_FAIL. */
4258 parse_pldop (char **str
)
4261 const struct aarch64_name_value_pair
*o
;
4264 while (ISALNUM (*q
))
4267 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4275 /* Parse an option for a barrier instruction. Returns the encoding for the
4276 option, or PARSE_FAIL. */
4279 parse_barrier (char **str
)
4282 const struct aarch64_name_value_pair
*o
;
4285 while (ISALPHA (*q
))
4288 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4296 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4297 return 0 if successful. Otherwise return PARSE_FAIL. */
4300 parse_barrier_psb (char **str
,
4301 const struct aarch64_name_value_pair
** hint_opt
)
4304 const struct aarch64_name_value_pair
*o
;
4307 while (ISALPHA (*q
))
4310 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4313 set_fatal_syntax_error
4314 ( _("unknown or missing option to PSB/TSB"));
4318 if (o
->value
!= 0x11)
4320 /* PSB only accepts option name 'CSYNC'. */
4322 (_("the specified option is not accepted for PSB/TSB"));
4331 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4332 return 0 if successful. Otherwise return PARSE_FAIL. */
4335 parse_bti_operand (char **str
,
4336 const struct aarch64_name_value_pair
** hint_opt
)
4339 const struct aarch64_name_value_pair
*o
;
4342 while (ISALPHA (*q
))
4345 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4348 set_fatal_syntax_error
4349 ( _("unknown option to BTI"));
4355 /* Valid BTI operands. */
4363 (_("unknown option to BTI"));
4372 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4373 Returns the encoding for the option, or PARSE_FAIL.
4375 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4376 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4378 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4379 field, otherwise as a system register.
4383 parse_sys_reg (const aarch64_opcode
*opcode
, char **str
, htab_t sys_regs
,
4384 int imple_defined_p
, int pstatefield_p
,
4388 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4389 const aarch64_sys_reg
*o
;
4393 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4394 if (p
< buf
+ (sizeof (buf
) - 1))
4395 *p
++ = TOLOWER (*q
);
4398 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4399 valid system register. This is enforced by construction of the hash
4401 if (p
- buf
!= q
- *str
)
4404 o
= str_hash_find (sys_regs
, buf
);
4407 if (!imple_defined_p
)
4411 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4412 unsigned int op0
, op1
, cn
, cm
, op2
;
4414 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4417 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4419 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4426 if (!aarch64_sys_reg_capreg_supported_p (opcode
->iclass
, o
))
4429 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4430 as_bad (_("selected processor does not support PSTATE field "
4433 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4434 o
->value
, o
->flags
, o
->features
))
4435 as_bad (_("selected processor does not support system register "
4437 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4438 as_warn (_("system register name '%s' is deprecated and may be "
4439 "removed in a future release"), buf
);
4449 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4450 for the option, or NULL. */
4452 static const aarch64_sys_ins_reg
*
4453 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4456 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4457 const aarch64_sys_ins_reg
*o
;
4460 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4461 if (p
< buf
+ (sizeof (buf
) - 1))
4462 *p
++ = TOLOWER (*q
);
4465 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4466 valid system register. This is enforced by construction of the hash
4468 if (p
- buf
!= q
- *str
)
4471 o
= str_hash_find (sys_ins_regs
, buf
);
4475 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4476 o
->name
, o
->value
, o
->flags
, 0))
4477 as_bad (_("selected processor does not support system register "
4479 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4480 as_warn (_("system register name '%s' is deprecated and may be "
4481 "removed in a future release"), buf
);
4487 #define po_char_or_fail(chr) do { \
4488 if (! skip_past_char (&str, chr)) \
4492 #define po_reg_or_fail(regtype) do { \
4493 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4494 if (val == PARSE_FAIL) \
4496 set_default_error (); \
4501 #define po_int_reg_or_fail(reg_type) do { \
4502 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4503 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4505 set_default_error (); \
4508 info->reg.regno = reg->number; \
4509 info->qualifier = qualifier; \
4512 #define po_imm_nc_or_fail() do { \
4513 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4517 #define po_imm_or_fail(min, max) do { \
4518 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4520 if (val < min || val > max) \
4522 set_fatal_syntax_error (_("immediate value out of range "\
4523 #min " to "#max)); \
4528 #define po_enum_or_fail(array) do { \
4529 if (!parse_enum_string (&str, &val, array, \
4530 ARRAY_SIZE (array), imm_reg_type)) \
4534 #define po_misc_or_fail(expr) do { \
4539 /* encode the 12-bit imm field of Add/sub immediate */
4540 static inline uint32_t
4541 encode_addsub_imm (uint32_t imm
)
4546 /* encode the shift amount field of Add/sub immediate */
4547 static inline uint32_t
4548 encode_addsub_imm_shift_amount (uint32_t cnt
)
4554 /* encode the imm field of Adr instruction */
4555 static inline uint32_t
4556 encode_adr_imm (uint32_t imm
)
4558 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4559 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4562 /* encode the immediate field of Move wide immediate */
4563 static inline uint32_t
4564 encode_movw_imm (uint32_t imm
)
4569 /* encode the 26-bit offset of unconditional branch */
4570 static inline uint32_t
4571 encode_branch_ofs_26 (uint32_t ofs
)
4573 return ofs
& ((1 << 26) - 1);
4576 /* encode the 19-bit offset of conditional branch and compare & branch */
4577 static inline uint32_t
4578 encode_cond_branch_ofs_19 (uint32_t ofs
)
4580 return (ofs
& ((1 << 19) - 1)) << 5;
4583 /* encode the 17-bit offset of ld literal */
4584 static inline uint32_t
4585 encode_ld_lit_ofs_17 (uint32_t ofs
)
4587 return (ofs
& ((1 << 17) - 1)) << 5;
4590 /* encode the 19-bit offset of ld literal */
4591 static inline uint32_t
4592 encode_ld_lit_ofs_19 (uint32_t ofs
)
4594 return (ofs
& ((1 << 19) - 1)) << 5;
4597 /* Encode the 14-bit offset of test & branch. */
4598 static inline uint32_t
4599 encode_tst_branch_ofs_14 (uint32_t ofs
)
4601 return (ofs
& ((1 << 14) - 1)) << 5;
4604 /* Encode the 16-bit imm field of svc/hvc/smc. */
4605 static inline uint32_t
4606 encode_svc_imm (uint32_t imm
)
4611 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4612 static inline uint32_t
4613 reencode_addsub_switch_add_sub (uint32_t opcode
)
4615 return opcode
^ (1 << 30);
4618 static inline uint32_t
4619 reencode_movzn_to_movz (uint32_t opcode
)
4621 return opcode
| (1 << 30);
4624 static inline uint32_t
4625 reencode_movzn_to_movn (uint32_t opcode
)
4627 return opcode
& ~(1 << 30);
4630 /* Overall per-instruction processing. */
4632 /* We need to be able to fix up arbitrary expressions in some statements.
4633 This is so that we can handle symbols that are an arbitrary distance from
4634 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4635 which returns part of an address in a form which will be valid for
4636 a data instruction. We do this by pushing the expression into a symbol
4637 in the expr_section, and creating a fix for that. */
4640 fix_new_aarch64 (fragS
* frag
,
4655 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4659 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4666 /* Diagnostics on operands errors. */
4668 /* By default, output verbose error message.
4669 Disable the verbose error message by -mno-verbose-error. */
4670 static int verbose_error_p
= 1;
4672 #ifdef DEBUG_AARCH64
4673 /* N.B. this is only for the purpose of debugging. */
4674 const char* operand_mismatch_kind_names
[] =
4677 "AARCH64_OPDE_RECOVERABLE",
4678 "AARCH64_OPDE_SYNTAX_ERROR",
4679 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4680 "AARCH64_OPDE_INVALID_VARIANT",
4681 "AARCH64_OPDE_OUT_OF_RANGE",
4682 "AARCH64_OPDE_UNALIGNED",
4683 "AARCH64_OPDE_REG_LIST",
4684 "AARCH64_OPDE_OTHER_ERROR",
4686 #endif /* DEBUG_AARCH64 */
4688 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4690 When multiple errors of different kinds are found in the same assembly
4691 line, only the error of the highest severity will be picked up for
4692 issuing the diagnostics. */
4694 static inline bfd_boolean
4695 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4696 enum aarch64_operand_error_kind rhs
)
4698 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4699 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4700 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4701 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4702 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4703 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4704 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4705 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4709 /* Helper routine to get the mnemonic name from the assembly instruction
4710 line; should only be called for the diagnosis purpose, as there is
4711 string copy operation involved, which may affect the runtime
4712 performance if used in elsewhere. */
4715 get_mnemonic_name (const char *str
)
4717 static char mnemonic
[32];
4720 /* Get the first 15 bytes and assume that the full name is included. */
4721 strncpy (mnemonic
, str
, 31);
4722 mnemonic
[31] = '\0';
4724 /* Scan up to the end of the mnemonic, which must end in white space,
4725 '.', or end of string. */
4726 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4731 /* Append '...' to the truncated long name. */
4732 if (ptr
- mnemonic
== 31)
4733 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4739 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4741 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4742 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4745 /* Data structures storing one user error in the assembly code related to
4748 struct operand_error_record
4750 const aarch64_opcode
*opcode
;
4751 aarch64_operand_error detail
;
4752 struct operand_error_record
*next
;
4755 typedef struct operand_error_record operand_error_record
;
4757 struct operand_errors
4759 operand_error_record
*head
;
4760 operand_error_record
*tail
;
4763 typedef struct operand_errors operand_errors
;
4765 /* Top-level data structure reporting user errors for the current line of
4767 The way md_assemble works is that all opcodes sharing the same mnemonic
4768 name are iterated to find a match to the assembly line. In this data
4769 structure, each of the such opcodes will have one operand_error_record
4770 allocated and inserted. In other words, excessive errors related with
4771 a single opcode are disregarded. */
4772 operand_errors operand_error_report
;
4774 /* Free record nodes. */
4775 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4777 /* Initialize the data structure that stores the operand mismatch
4778 information on assembling one line of the assembly code. */
4780 init_operand_error_report (void)
4782 if (operand_error_report
.head
!= NULL
)
4784 gas_assert (operand_error_report
.tail
!= NULL
);
4785 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4786 free_opnd_error_record_nodes
= operand_error_report
.head
;
4787 operand_error_report
.head
= NULL
;
4788 operand_error_report
.tail
= NULL
;
4791 gas_assert (operand_error_report
.tail
== NULL
);
4794 /* Return TRUE if some operand error has been recorded during the
4795 parsing of the current assembly line using the opcode *OPCODE;
4796 otherwise return FALSE. */
4797 static inline bfd_boolean
4798 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4800 operand_error_record
*record
= operand_error_report
.head
;
4801 return record
&& record
->opcode
== opcode
;
4804 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4805 OPCODE field is initialized with OPCODE.
4806 N.B. only one record for each opcode, i.e. the maximum of one error is
4807 recorded for each instruction template. */
4810 add_operand_error_record (const operand_error_record
* new_record
)
4812 const aarch64_opcode
*opcode
= new_record
->opcode
;
4813 operand_error_record
* record
= operand_error_report
.head
;
4815 /* The record may have been created for this opcode. If not, we need
4817 if (! opcode_has_operand_error_p (opcode
))
4819 /* Get one empty record. */
4820 if (free_opnd_error_record_nodes
== NULL
)
4822 record
= XNEW (operand_error_record
);
4826 record
= free_opnd_error_record_nodes
;
4827 free_opnd_error_record_nodes
= record
->next
;
4829 record
->opcode
= opcode
;
4830 /* Insert at the head. */
4831 record
->next
= operand_error_report
.head
;
4832 operand_error_report
.head
= record
;
4833 if (operand_error_report
.tail
== NULL
)
4834 operand_error_report
.tail
= record
;
4836 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4837 && record
->detail
.index
<= new_record
->detail
.index
4838 && operand_error_higher_severity_p (record
->detail
.kind
,
4839 new_record
->detail
.kind
))
4841 /* In the case of multiple errors found on operands related with a
4842 single opcode, only record the error of the leftmost operand and
4843 only if the error is of higher severity. */
4844 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4845 " the existing error %s on operand %d",
4846 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4847 new_record
->detail
.index
,
4848 operand_mismatch_kind_names
[record
->detail
.kind
],
4849 record
->detail
.index
);
4853 record
->detail
= new_record
->detail
;
4857 record_operand_error_info (const aarch64_opcode
*opcode
,
4858 aarch64_operand_error
*error_info
)
4860 operand_error_record record
;
4861 record
.opcode
= opcode
;
4862 record
.detail
= *error_info
;
4863 add_operand_error_record (&record
);
4866 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4867 error message *ERROR, for operand IDX (count from 0). */
4870 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4871 enum aarch64_operand_error_kind kind
,
4874 aarch64_operand_error info
;
4875 memset(&info
, 0, sizeof (info
));
4879 info
.non_fatal
= FALSE
;
4880 record_operand_error_info (opcode
, &info
);
4884 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4885 enum aarch64_operand_error_kind kind
,
4886 const char* error
, const int *extra_data
)
4888 aarch64_operand_error info
;
4892 info
.data
[0] = extra_data
[0];
4893 info
.data
[1] = extra_data
[1];
4894 info
.data
[2] = extra_data
[2];
4895 info
.non_fatal
= FALSE
;
4896 record_operand_error_info (opcode
, &info
);
4900 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4901 const char* error
, int lower_bound
,
4904 int data
[3] = {lower_bound
, upper_bound
, 0};
4905 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4909 /* Remove the operand error record for *OPCODE. */
4910 static void ATTRIBUTE_UNUSED
4911 remove_operand_error_record (const aarch64_opcode
*opcode
)
4913 if (opcode_has_operand_error_p (opcode
))
4915 operand_error_record
* record
= operand_error_report
.head
;
4916 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4917 operand_error_report
.head
= record
->next
;
4918 record
->next
= free_opnd_error_record_nodes
;
4919 free_opnd_error_record_nodes
= record
;
4920 if (operand_error_report
.head
== NULL
)
4922 gas_assert (operand_error_report
.tail
== record
);
4923 operand_error_report
.tail
= NULL
;
4928 /* Given the instruction in *INSTR, return the index of the best matched
4929 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4931 Return -1 if there is no qualifier sequence; return the first match
4932 if there is multiple matches found. */
4935 find_best_match (const aarch64_inst
*instr
,
4936 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4938 int i
, num_opnds
, max_num_matched
, idx
;
4940 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4943 DEBUG_TRACE ("no operand");
4947 max_num_matched
= 0;
4950 /* For each pattern. */
4951 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4954 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4956 /* Most opcodes has much fewer patterns in the list. */
4957 if (empty_qualifier_sequence_p (qualifiers
))
4959 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4963 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4964 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4967 if (num_matched
> max_num_matched
)
4969 max_num_matched
= num_matched
;
4974 DEBUG_TRACE ("return with %d", idx
);
4978 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4979 corresponding operands in *INSTR. */
4982 assign_qualifier_sequence (aarch64_inst
*instr
,
4983 const aarch64_opnd_qualifier_t
*qualifiers
)
4986 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4987 gas_assert (num_opnds
);
4988 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4989 instr
->operands
[i
].qualifier
= *qualifiers
;
4992 /* Print operands for the diagnosis purpose. */
4995 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4996 const aarch64_opnd_info
*opnds
)
5000 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5004 /* We regard the opcode operand info more, however we also look into
5005 the inst->operands to support the disassembling of the optional
5007 The two operand code should be the same in all cases, apart from
5008 when the operand can be optional. */
5009 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5010 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5013 /* Generate the operand string in STR. */
5014 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5019 strcat (buf
, i
== 0 ? " " : ", ");
5021 /* Append the operand string. */
5026 /* Send to stderr a string as information. */
5029 output_info (const char *format
, ...)
5035 file
= as_where (&line
);
5039 fprintf (stderr
, "%s:%u: ", file
, line
);
5041 fprintf (stderr
, "%s: ", file
);
5043 fprintf (stderr
, _("Info: "));
5044 va_start (args
, format
);
5045 vfprintf (stderr
, format
, args
);
5047 (void) putc ('\n', stderr
);
5050 /* Output one operand error record. */
5053 output_operand_error_record (const operand_error_record
*record
, char *str
)
5055 const aarch64_operand_error
*detail
= &record
->detail
;
5056 int idx
= detail
->index
;
5057 const aarch64_opcode
*opcode
= record
->opcode
;
5058 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5059 : AARCH64_OPND_NIL
);
5061 typedef void (*handler_t
)(const char *format
, ...);
5062 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5064 switch (detail
->kind
)
5066 case AARCH64_OPDE_NIL
:
5069 case AARCH64_OPDE_SYNTAX_ERROR
:
5070 case AARCH64_OPDE_RECOVERABLE
:
5071 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5072 case AARCH64_OPDE_OTHER_ERROR
:
5073 /* Use the prepared error message if there is, otherwise use the
5074 operand description string to describe the error. */
5075 if (detail
->error
!= NULL
)
5078 handler (_("%s -- `%s'"), detail
->error
, str
);
5080 handler (_("%s at operand %d -- `%s'"),
5081 detail
->error
, idx
+ 1, str
);
5085 gas_assert (idx
>= 0);
5086 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5087 aarch64_get_operand_desc (opd_code
), str
);
5091 case AARCH64_OPDE_INVALID_VARIANT
:
5092 handler (_("operand mismatch -- `%s'"), str
);
5093 if (verbose_error_p
)
5095 /* We will try to correct the erroneous instruction and also provide
5096 more information e.g. all other valid variants.
5098 The string representation of the corrected instruction and other
5099 valid variants are generated by
5101 1) obtaining the intermediate representation of the erroneous
5103 2) manipulating the IR, e.g. replacing the operand qualifier;
5104 3) printing out the instruction by calling the printer functions
5105 shared with the disassembler.
5107 The limitation of this method is that the exact input assembly
5108 line cannot be accurately reproduced in some cases, for example an
5109 optional operand present in the actual assembly line will be
5110 omitted in the output; likewise for the optional syntax rules,
5111 e.g. the # before the immediate. Another limitation is that the
5112 assembly symbols and relocation operations in the assembly line
5113 currently cannot be printed out in the error report. Last but not
5114 least, when there is other error(s) co-exist with this error, the
5115 'corrected' instruction may be still incorrect, e.g. given
5116 'ldnp h0,h1,[x0,#6]!'
5117 this diagnosis will provide the version:
5118 'ldnp s0,s1,[x0,#6]!'
5119 which is still not right. */
5120 size_t len
= strlen (get_mnemonic_name (str
));
5124 aarch64_inst
*inst_base
= &inst
.base
;
5125 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5128 reset_aarch64_instruction (&inst
);
5129 inst_base
->opcode
= opcode
;
5131 /* Reset the error report so that there is no side effect on the
5132 following operand parsing. */
5133 init_operand_error_report ();
5136 result
= parse_operands (str
+ len
, opcode
)
5137 && programmer_friendly_fixup (&inst
);
5138 gas_assert (result
);
5139 result
= aarch64_opcode_encode (cpu_variant
, opcode
, inst_base
,
5140 &inst_base
->value
, NULL
, NULL
,
5142 gas_assert (!result
);
5144 /* Find the most matched qualifier sequence. */
5145 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5146 gas_assert (qlf_idx
> -1);
5148 /* Assign the qualifiers. */
5149 assign_qualifier_sequence (inst_base
,
5150 opcode
->qualifiers_list
[qlf_idx
]);
5152 /* Print the hint. */
5153 output_info (_(" did you mean this?"));
5154 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5155 print_operands (buf
, opcode
, inst_base
->operands
);
5156 output_info (_(" %s"), buf
);
5158 /* Print out other variant(s) if there is any. */
5160 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5161 output_info (_(" other valid variant(s):"));
5163 /* For each pattern. */
5164 qualifiers_list
= opcode
->qualifiers_list
;
5165 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5167 /* Most opcodes has much fewer patterns in the list.
5168 First NIL qualifier indicates the end in the list. */
5169 if (empty_qualifier_sequence_p (*qualifiers_list
))
5174 /* Mnemonics name. */
5175 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5177 /* Assign the qualifiers. */
5178 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5180 /* Print instruction. */
5181 print_operands (buf
, opcode
, inst_base
->operands
);
5183 output_info (_(" %s"), buf
);
5189 case AARCH64_OPDE_UNTIED_OPERAND
:
5190 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5191 detail
->index
+ 1, str
);
5194 case AARCH64_OPDE_OUT_OF_RANGE
:
5195 if (detail
->data
[0] != detail
->data
[1])
5196 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5197 detail
->error
? detail
->error
: _("immediate value"),
5198 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
5200 handler (_("%s must be %d at operand %d -- `%s'"),
5201 detail
->error
? detail
->error
: _("immediate value"),
5202 detail
->data
[0], idx
+ 1, str
);
5205 case AARCH64_OPDE_REG_LIST
:
5206 if (detail
->data
[0] == 1)
5207 handler (_("invalid number of registers in the list; "
5208 "only 1 register is expected at operand %d -- `%s'"),
5211 handler (_("invalid number of registers in the list; "
5212 "%d registers are expected at operand %d -- `%s'"),
5213 detail
->data
[0], idx
+ 1, str
);
5216 case AARCH64_OPDE_UNALIGNED
:
5217 handler (_("immediate value must be a multiple of "
5218 "%d at operand %d -- `%s'"),
5219 detail
->data
[0], idx
+ 1, str
);
5228 /* Process and output the error message about the operand mismatching.
5230 When this function is called, the operand error information had
5231 been collected for an assembly line and there will be multiple
5232 errors in the case of multiple instruction templates; output the
5233 error message that most closely describes the problem.
5235 The errors to be printed can be filtered on printing all errors
5236 or only non-fatal errors. This distinction has to be made because
5237 the error buffer may already be filled with fatal errors we don't want to
5238 print due to the different instruction templates. */
5241 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
5243 int largest_error_pos
, largest_error_pos2
;
5244 const char *msg
= NULL
, *msg2
= NULL
;
5245 enum aarch64_operand_error_kind kind
;
5246 operand_error_record
*curr
;
5247 operand_error_record
*head
= operand_error_report
.head
;
5248 operand_error_record
*record
= NULL
, *record2
= NULL
;
5250 /* No error to report. */
5254 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5256 /* Only one error. */
5257 if (head
== operand_error_report
.tail
)
5259 /* If the only error is a non-fatal one and we don't want to print it,
5261 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5263 DEBUG_TRACE ("single opcode entry with error kind: %s",
5264 operand_mismatch_kind_names
[head
->detail
.kind
]);
5265 output_operand_error_record (head
, str
);
5270 /* Find the error kind of the highest severity. */
5271 DEBUG_TRACE ("multiple opcode entries with error kind");
5272 kind
= AARCH64_OPDE_NIL
;
5273 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5275 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5276 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5277 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5278 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5279 kind
= curr
->detail
.kind
;
5282 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5284 /* Pick up one of errors of KIND to report. */
5285 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5286 largest_error_pos2
= -2; /* Index can be -1 which means unknown index. */
5287 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5289 /* If we don't want to print non-fatal errors then don't consider them
5291 if (curr
->detail
.kind
!= kind
5292 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5294 /* If there are multiple errors, pick up the one with the highest
5295 mismatching operand index. In the case of multiple errors with
5296 the equally highest operand index, pick up the first one or the
5297 first one with non-NULL error message. */
5298 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, *curr
->opcode
->avariant
))
5300 if (curr
->detail
.index
> largest_error_pos
5301 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5302 && curr
->detail
.error
!= NULL
))
5304 largest_error_pos
= curr
->detail
.index
;
5306 msg
= record
->detail
.error
;
5311 if (curr
->detail
.index
> largest_error_pos2
5312 || (curr
->detail
.index
== largest_error_pos2
&& msg2
== NULL
5313 && curr
->detail
.error
!= NULL
))
5315 largest_error_pos2
= curr
->detail
.index
;
5317 msg2
= record2
->detail
.error
;
5322 /* No errors in enabled cpu feature variants, look for errors in the disabled
5323 ones. XXX we should do this segregation when prioritizing too. */
5326 largest_error_pos
= largest_error_pos2
;
5331 /* The way errors are collected in the back-end is a bit non-intuitive. But
5332 essentially, because each operand template is tried recursively you may
5333 always have errors collected from the previous tried OPND. These are
5334 usually skipped if there is one successful match. However now with the
5335 non-fatal errors we have to ignore those previously collected hard errors
5336 when we're only interested in printing the non-fatal ones. This condition
5337 prevents us from printing errors that are not appropriate, since we did
5338 match a condition, but it also has warnings that it wants to print. */
5339 if (non_fatal_only
&& !record
)
5342 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5343 DEBUG_TRACE ("Pick up error kind %s to report",
5344 operand_mismatch_kind_names
[record
->detail
.kind
]);
5347 output_operand_error_record (record
, str
);
5350 /* Write an AARCH64 instruction to buf - always little-endian. */
5352 put_aarch64_insn (char *buf
, uint32_t insn
)
5354 unsigned char *where
= (unsigned char *) buf
;
5356 where
[1] = insn
>> 8;
5357 where
[2] = insn
>> 16;
5358 where
[3] = insn
>> 24;
5362 get_aarch64_insn (char *buf
)
5364 unsigned char *where
= (unsigned char *) buf
;
5366 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5367 | ((uint32_t) where
[3] << 24)));
5372 output_inst (struct aarch64_inst
*new_inst
)
5376 to
= frag_more (INSN_SIZE
);
5378 frag_now
->tc_frag_data
.recorded
= 1;
5380 put_aarch64_insn (to
, inst
.base
.value
);
5382 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5384 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5385 INSN_SIZE
, &inst
.reloc
.exp
,
5388 DEBUG_TRACE ("Prepared relocation fix up");
5389 /* Don't check the addend value against the instruction size,
5390 that's the job of our code in md_apply_fix(). */
5391 fixp
->fx_no_overflow
= 1;
5392 if (new_inst
!= NULL
)
5393 fixp
->tc_fix_data
.inst
= new_inst
;
5394 if (aarch64_gas_internal_fixup_p ())
5396 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5397 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5398 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5400 if (inst
.reloc
.flags
& FIXUP_F_C64
)
5401 fixp
->tc_fix_data
.c64
= TRUE
;
5404 dwarf2_emit_insn (INSN_SIZE
);
5407 /* Link together opcodes of the same name. */
5411 aarch64_opcode
*opcode
;
5412 struct templates
*next
;
5415 typedef struct templates templates
;
5418 lookup_mnemonic (const char *start
, int len
)
5420 templates
*templ
= NULL
;
5422 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5426 /* Subroutine of md_assemble, responsible for looking up the primary
5427 opcode from the mnemonic the user wrote. STR points to the
5428 beginning of the mnemonic. */
5431 opcode_lookup (char **str
)
5433 char *end
, *base
, *dot
;
5434 const aarch64_cond
*cond
;
5438 /* Scan up to the end of the mnemonic, which must end in white space,
5439 '.', or end of string. */
5441 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5442 if (*end
== '.' && !dot
)
5445 if (end
== base
|| dot
== base
)
5448 inst
.cond
= COND_ALWAYS
;
5450 /* Handle a possible condition. */
5453 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5456 inst
.cond
= cond
->value
;
5472 if (inst
.cond
== COND_ALWAYS
)
5474 /* Look for unaffixed mnemonic. */
5475 return lookup_mnemonic (base
, len
);
5479 /* append ".c" to mnemonic if conditional */
5480 memcpy (condname
, base
, len
);
5481 memcpy (condname
+ len
, ".c", 2);
5484 return lookup_mnemonic (base
, len
);
5490 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5491 to a corresponding operand qualifier. */
5493 static inline aarch64_opnd_qualifier_t
5494 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5496 /* Element size in bytes indexed by vector_el_type. */
5497 const unsigned char ele_size
[5]
5499 const unsigned int ele_base
[5] =
5501 AARCH64_OPND_QLF_V_4B
,
5502 AARCH64_OPND_QLF_V_2H
,
5503 AARCH64_OPND_QLF_V_2S
,
5504 AARCH64_OPND_QLF_V_1D
,
5505 AARCH64_OPND_QLF_V_1Q
5508 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5509 goto vectype_conversion_fail
;
5511 if (vectype
->type
== NT_zero
)
5512 return AARCH64_OPND_QLF_P_Z
;
5513 if (vectype
->type
== NT_merge
)
5514 return AARCH64_OPND_QLF_P_M
;
5516 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5518 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5520 /* Special case S_4B. */
5521 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5522 return AARCH64_OPND_QLF_S_4B
;
5524 /* Special case S_2H. */
5525 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5526 return AARCH64_OPND_QLF_S_2H
;
5528 /* Vector element register. */
5529 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5533 /* Vector register. */
5534 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5537 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5538 goto vectype_conversion_fail
;
5540 /* The conversion is by calculating the offset from the base operand
5541 qualifier for the vector type. The operand qualifiers are regular
5542 enough that the offset can established by shifting the vector width by
5543 a vector-type dependent amount. */
5545 if (vectype
->type
== NT_b
)
5547 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5549 else if (vectype
->type
>= NT_d
)
5554 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5555 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5556 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5560 vectype_conversion_fail
:
5561 first_error (_("bad vector arrangement type"));
5562 return AARCH64_OPND_QLF_NIL
;
5565 /* Process an optional operand that is found omitted from the assembly line.
5566 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5567 instruction's opcode entry while IDX is the index of this omitted operand.
5571 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5572 int idx
, aarch64_opnd_info
*operand
)
5574 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5575 gas_assert (optional_operand_p (opcode
, idx
));
5576 gas_assert (!operand
->present
);
5580 case AARCH64_OPND_Can
:
5581 case AARCH64_OPND_Cat_SYS
:
5582 case AARCH64_OPND_Rd
:
5583 case AARCH64_OPND_Rn
:
5584 case AARCH64_OPND_Rm
:
5585 case AARCH64_OPND_Rt
:
5586 case AARCH64_OPND_Rt2
:
5587 case AARCH64_OPND_Rt_SP
:
5588 case AARCH64_OPND_Rs
:
5589 case AARCH64_OPND_Ra
:
5590 case AARCH64_OPND_Rt_SYS
:
5591 case AARCH64_OPND_Rd_SP
:
5592 case AARCH64_OPND_Rn_SP
:
5593 case AARCH64_OPND_Rm_SP
:
5594 case AARCH64_OPND_Fd
:
5595 case AARCH64_OPND_Fn
:
5596 case AARCH64_OPND_Fm
:
5597 case AARCH64_OPND_Fa
:
5598 case AARCH64_OPND_Ft
:
5599 case AARCH64_OPND_Ft2
:
5600 case AARCH64_OPND_Sd
:
5601 case AARCH64_OPND_Sn
:
5602 case AARCH64_OPND_Sm
:
5603 case AARCH64_OPND_Va
:
5604 case AARCH64_OPND_Vd
:
5605 case AARCH64_OPND_Vn
:
5606 case AARCH64_OPND_Vm
:
5607 case AARCH64_OPND_VdD1
:
5608 case AARCH64_OPND_VnD1
:
5609 operand
->reg
.regno
= default_value
;
5612 case AARCH64_OPND_Ed
:
5613 case AARCH64_OPND_En
:
5614 case AARCH64_OPND_Em
:
5615 case AARCH64_OPND_Em16
:
5616 case AARCH64_OPND_SM3_IMM2
:
5617 operand
->reglane
.regno
= default_value
;
5620 case AARCH64_OPND_IDX
:
5621 case AARCH64_OPND_BIT_NUM
:
5622 case AARCH64_OPND_IMMR
:
5623 case AARCH64_OPND_IMMS
:
5624 case AARCH64_OPND_SHLL_IMM
:
5625 case AARCH64_OPND_IMM_VLSL
:
5626 case AARCH64_OPND_IMM_VLSR
:
5627 case AARCH64_OPND_CCMP_IMM
:
5628 case AARCH64_OPND_FBITS
:
5629 case AARCH64_OPND_UIMM4
:
5630 case AARCH64_OPND_UIMM3_OP1
:
5631 case AARCH64_OPND_UIMM3_OP2
:
5632 case AARCH64_OPND_IMM
:
5633 case AARCH64_OPND_IMM_2
:
5634 case AARCH64_OPND_WIDTH
:
5635 case AARCH64_OPND_UIMM7
:
5636 case AARCH64_OPND_NZCV
:
5637 case AARCH64_OPND_SVE_PATTERN
:
5638 case AARCH64_OPND_SVE_PRFOP
:
5639 operand
->imm
.value
= default_value
;
5642 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5643 operand
->imm
.value
= default_value
;
5644 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5645 operand
->shifter
.amount
= 1;
5648 case AARCH64_OPND_EXCEPTION
:
5649 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5652 case AARCH64_OPND_BARRIER_ISB
:
5653 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5656 case AARCH64_OPND_BTI_TARGET
:
5657 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5665 /* Process the relocation type for move wide instructions.
5666 Return TRUE on success; otherwise return FALSE. */
5669 process_movw_reloc_info (void)
5674 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5676 if (inst
.base
.opcode
->op
== OP_MOVK
)
5677 switch (inst
.reloc
.type
)
5679 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5680 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5681 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5682 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5683 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5684 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5685 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5686 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5687 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5688 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5689 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5691 (_("the specified relocation type is not allowed for MOVK"));
5697 switch (inst
.reloc
.type
)
5699 case BFD_RELOC_MORELLO_MOVW_SIZE_G0
:
5700 case BFD_RELOC_MORELLO_MOVW_SIZE_G0_NC
:
5701 case BFD_RELOC_AARCH64_MOVW_G0
:
5702 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5703 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5704 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5705 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5706 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5707 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5708 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5709 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5710 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5711 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5712 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5713 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5716 case BFD_RELOC_MORELLO_MOVW_SIZE_G1
:
5717 case BFD_RELOC_MORELLO_MOVW_SIZE_G1_NC
:
5718 case BFD_RELOC_AARCH64_MOVW_G1
:
5719 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5720 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5721 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5722 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5723 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5724 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5725 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5726 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5727 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5728 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5729 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5730 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5733 case BFD_RELOC_MORELLO_MOVW_SIZE_G2
:
5734 case BFD_RELOC_MORELLO_MOVW_SIZE_G2_NC
:
5735 case BFD_RELOC_AARCH64_MOVW_G2
:
5736 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5737 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5738 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5739 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5740 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5741 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5744 set_fatal_syntax_error
5745 (_("the specified relocation type is not allowed for 32-bit "
5751 case BFD_RELOC_MORELLO_MOVW_SIZE_G3
:
5752 case BFD_RELOC_AARCH64_MOVW_G3
:
5753 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5756 set_fatal_syntax_error
5757 (_("the specified relocation type is not allowed for 32-bit "
5764 /* More cases should be added when more MOVW-related relocation types
5765 are supported in GAS. */
5766 gas_assert (aarch64_gas_internal_fixup_p ());
5767 /* The shift amount should have already been set by the parser. */
5770 inst
.base
.operands
[1].shifter
.amount
= shift
;
5774 /* A primitive log calculator. */
5776 static inline unsigned int
5777 get_logsz (unsigned int size
)
5779 const unsigned char ls
[16] =
5780 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5786 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5787 return ls
[size
- 1];
5790 /* Determine and return the real reloc type code for an instruction
5791 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5793 static inline bfd_reloc_code_real_type
5794 ldst_lo12_determine_real_reloc_type (void)
5797 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5798 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5800 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5802 BFD_RELOC_AARCH64_LDST8_LO12
,
5803 BFD_RELOC_AARCH64_LDST16_LO12
,
5804 BFD_RELOC_AARCH64_LDST32_LO12
,
5805 BFD_RELOC_AARCH64_LDST64_LO12
,
5806 BFD_RELOC_AARCH64_LDST128_LO12
5809 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5810 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5811 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5812 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5813 BFD_RELOC_AARCH64_NONE
5816 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5817 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5818 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5819 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5820 BFD_RELOC_AARCH64_NONE
5823 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5824 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5825 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5826 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5827 BFD_RELOC_AARCH64_NONE
5830 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5831 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5832 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5833 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5834 BFD_RELOC_AARCH64_NONE
5838 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5839 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5841 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5843 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5845 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5846 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
5847 || inst
.base
.opcode
->operands
[1] == AARCH64_OPND_CAPADDR_UIMM9
);
5849 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5851 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5853 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5855 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5856 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5857 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5858 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5859 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5860 gas_assert (logsz
<= 3);
5862 gas_assert (logsz
<= 4);
5864 /* In reloc.c, these pseudo relocation types should be defined in similar
5865 order as above reloc_ldst_lo12 array. Because the array index calculation
5866 below relies on this. */
5867 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5870 /* Check whether a register list REGINFO is valid. The registers must be
5871 numbered in increasing order (modulo 32), in increments of one or two.
5873 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5876 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5879 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5881 uint32_t i
, nb_regs
, prev_regno
, incr
;
5883 nb_regs
= 1 + (reginfo
& 0x3);
5885 prev_regno
= reginfo
& 0x1f;
5886 incr
= accept_alternate
? 2 : 1;
5888 for (i
= 1; i
< nb_regs
; ++i
)
5890 uint32_t curr_regno
;
5892 curr_regno
= reginfo
& 0x1f;
5893 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5895 prev_regno
= curr_regno
;
5902 parse_perms (char **str
, aarch64_opnd_info
*info
)
5906 aarch64_insn perms
= 0;
5908 /* Numeric value of permissions. */
5909 if (ISDIGIT (*p
) || (*p
== '#' && p
++))
5912 if (p
[1] > 0 || perms
> 7)
5914 set_syntax_error (_("invalid permission value"));
5921 /* Permission specifier mnemonics r, w and x, in that order. Do not accept
5922 jumbled up sequences such as rxw, wrx, etc. and also reject duplicate
5923 permissions such as rrxw. */
5924 while ((c
= *p
++) != '\0')
5926 aarch64_insn i
= get_perm_bit (c
);
5927 if (i
> 7 || i
& perms
|| (i
- 1) & perms
)
5929 set_syntax_error (_("invalid permissions"));
5941 /* Generic instruction operand parser. This does no encoding and no
5942 semantic validation; it merely squirrels values away in the inst
5943 structure. Returns TRUE or FALSE depending on whether the
5944 specified grammar matched. */
5947 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5950 char *backtrack_pos
= 0;
5951 const enum aarch64_opnd
*operands
= opcode
->operands
;
5952 aarch64_reg_type imm_reg_type
;
5955 skip_whitespace (str
);
5957 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5958 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5960 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5962 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5965 const reg_entry
*reg
;
5966 int comma_skipped_p
= 0;
5967 aarch64_reg_type rtype
;
5968 struct vector_type_el vectype
;
5969 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5970 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5971 aarch64_reg_type reg_type
;
5973 DEBUG_TRACE ("parse operand %d", i
);
5975 /* Assign the operand code. */
5976 info
->type
= operands
[i
];
5978 if (optional_operand_p (opcode
, i
))
5980 /* Remember where we are in case we need to backtrack. */
5981 gas_assert (!backtrack_pos
);
5982 backtrack_pos
= str
;
5985 /* Expect comma between operands; the backtrack mechanism will take
5986 care of cases of omitted optional operand. */
5987 if (i
> 0 && ! skip_past_char (&str
, ','))
5989 set_syntax_error (_("comma expected between operands"));
5993 comma_skipped_p
= 1;
5995 switch (operands
[i
])
5997 case AARCH64_OPND_Rsz
:
5998 case AARCH64_OPND_Rsz2
:
5999 case AARCH64_OPND_Rd
:
6000 case AARCH64_OPND_Rn
:
6001 case AARCH64_OPND_Rm
:
6002 case AARCH64_OPND_Rt
:
6003 case AARCH64_OPND_Rt2
:
6004 case AARCH64_OPND_Rs
:
6005 case AARCH64_OPND_Ra
:
6006 case AARCH64_OPND_Rt_SYS
:
6007 case AARCH64_OPND_PAIRREG
:
6008 case AARCH64_OPND_SVE_Rm
:
6009 po_int_reg_or_fail (REG_TYPE_R_Z
);
6012 case AARCH64_OPND_Rd_SP
:
6013 case AARCH64_OPND_Rn_SP
:
6014 case AARCH64_OPND_Rt_SP
:
6015 case AARCH64_OPND_SVE_Rn_SP
:
6016 case AARCH64_OPND_Rm_SP
:
6017 po_int_reg_or_fail (REG_TYPE_R_SP
);
6020 case AARCH64_OPND_A64C_Rm_EXT
:
6021 case AARCH64_OPND_Rm_EXT
:
6022 case AARCH64_OPND_Rm_SFT
:
6023 po_misc_or_fail (parse_shifter_operand
6024 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_SFT
6026 : SHIFTED_ARITH_IMM
)));
6027 if (!info
->shifter
.operator_present
)
6029 /* Default to LSL if not present. Libopcodes prefers shifter
6030 kind to be explicit. */
6031 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6032 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6033 /* For Rm_EXT, libopcodes will carry out further check on whether
6034 or not stack pointer is used in the instruction (Recall that
6035 "the extend operator is not optional unless at least one of
6036 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6040 case AARCH64_OPND_Fsz
:
6041 case AARCH64_OPND_Fd
:
6042 case AARCH64_OPND_Fn
:
6043 case AARCH64_OPND_Fm
:
6044 case AARCH64_OPND_Fa
:
6045 case AARCH64_OPND_Ft
:
6046 case AARCH64_OPND_Ft2
:
6047 case AARCH64_OPND_Sd
:
6048 case AARCH64_OPND_Sn
:
6049 case AARCH64_OPND_Sm
:
6050 case AARCH64_OPND_St
:
6051 case AARCH64_OPND_SVE_VZn
:
6052 case AARCH64_OPND_SVE_Vd
:
6053 case AARCH64_OPND_SVE_Vm
:
6054 case AARCH64_OPND_SVE_Vn
:
6055 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6056 if (val
== PARSE_FAIL
)
6058 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6061 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6063 info
->reg
.regno
= val
;
6064 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6067 case AARCH64_OPND_SVE_Pd
:
6068 case AARCH64_OPND_SVE_Pg3
:
6069 case AARCH64_OPND_SVE_Pg4_5
:
6070 case AARCH64_OPND_SVE_Pg4_10
:
6071 case AARCH64_OPND_SVE_Pg4_16
:
6072 case AARCH64_OPND_SVE_Pm
:
6073 case AARCH64_OPND_SVE_Pn
:
6074 case AARCH64_OPND_SVE_Pt
:
6075 reg_type
= REG_TYPE_PN
;
6078 case AARCH64_OPND_SVE_Za_5
:
6079 case AARCH64_OPND_SVE_Za_16
:
6080 case AARCH64_OPND_SVE_Zd
:
6081 case AARCH64_OPND_SVE_Zm_5
:
6082 case AARCH64_OPND_SVE_Zm_16
:
6083 case AARCH64_OPND_SVE_Zn
:
6084 case AARCH64_OPND_SVE_Zt
:
6085 reg_type
= REG_TYPE_ZN
;
6088 case AARCH64_OPND_Va
:
6089 case AARCH64_OPND_Vd
:
6090 case AARCH64_OPND_Vn
:
6091 case AARCH64_OPND_Vm
:
6092 reg_type
= REG_TYPE_VN
;
6094 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6095 if (val
== PARSE_FAIL
)
6097 first_error (_(get_reg_expected_msg (reg_type
)));
6100 if (vectype
.defined
& NTA_HASINDEX
)
6103 info
->reg
.regno
= val
;
6104 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6105 && vectype
.type
== NT_invtype
)
6106 /* Unqualified Pn and Zn registers are allowed in certain
6107 contexts. Rely on F_STRICT qualifier checking to catch
6109 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6112 info
->qualifier
= vectype_to_qualifier (&vectype
);
6113 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6118 case AARCH64_OPND_VdD1
:
6119 case AARCH64_OPND_VnD1
:
6120 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6121 if (val
== PARSE_FAIL
)
6123 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6126 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6128 set_fatal_syntax_error
6129 (_("the top half of a 128-bit FP/SIMD register is expected"));
6132 info
->reg
.regno
= val
;
6133 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6134 here; it is correct for the purpose of encoding/decoding since
6135 only the register number is explicitly encoded in the related
6136 instructions, although this appears a bit hacky. */
6137 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6140 case AARCH64_OPND_SVE_Zm3_INDEX
:
6141 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6142 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6143 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6144 case AARCH64_OPND_SVE_Zm4_INDEX
:
6145 case AARCH64_OPND_SVE_Zn_INDEX
:
6146 reg_type
= REG_TYPE_ZN
;
6147 goto vector_reg_index
;
6149 case AARCH64_OPND_Ed
:
6150 case AARCH64_OPND_En
:
6151 case AARCH64_OPND_Em
:
6152 case AARCH64_OPND_Em16
:
6153 case AARCH64_OPND_SM3_IMM2
:
6154 reg_type
= REG_TYPE_VN
;
6156 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6157 if (val
== PARSE_FAIL
)
6159 first_error (_(get_reg_expected_msg (reg_type
)));
6162 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6165 info
->reglane
.regno
= val
;
6166 info
->reglane
.index
= vectype
.index
;
6167 info
->qualifier
= vectype_to_qualifier (&vectype
);
6168 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6172 case AARCH64_OPND_SVE_ZnxN
:
6173 case AARCH64_OPND_SVE_ZtxN
:
6174 reg_type
= REG_TYPE_ZN
;
6175 goto vector_reg_list
;
6177 case AARCH64_OPND_LVn
:
6178 case AARCH64_OPND_LVt
:
6179 case AARCH64_OPND_LVt_AL
:
6180 case AARCH64_OPND_LEt
:
6181 reg_type
= REG_TYPE_VN
;
6183 if (reg_type
== REG_TYPE_ZN
6184 && get_opcode_dependent_value (opcode
) == 1
6187 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6188 if (val
== PARSE_FAIL
)
6190 first_error (_(get_reg_expected_msg (reg_type
)));
6193 info
->reglist
.first_regno
= val
;
6194 info
->reglist
.num_regs
= 1;
6198 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6199 if (val
== PARSE_FAIL
)
6202 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6204 set_fatal_syntax_error (_("invalid register list"));
6208 if (vectype
.width
!= 0 && *str
!= ',')
6210 set_fatal_syntax_error
6211 (_("expected element type rather than vector type"));
6215 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6216 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6218 if (operands
[i
] == AARCH64_OPND_LEt
)
6220 if (!(vectype
.defined
& NTA_HASINDEX
))
6222 info
->reglist
.has_index
= 1;
6223 info
->reglist
.index
= vectype
.index
;
6227 if (vectype
.defined
& NTA_HASINDEX
)
6229 if (!(vectype
.defined
& NTA_HASTYPE
))
6231 if (reg_type
== REG_TYPE_ZN
)
6232 set_fatal_syntax_error (_("missing type suffix"));
6236 info
->qualifier
= vectype_to_qualifier (&vectype
);
6237 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6241 case AARCH64_OPND_Can
:
6242 case AARCH64_OPND_Cam
:
6243 case AARCH64_OPND_Cas
:
6244 case AARCH64_OPND_Cad
:
6245 case AARCH64_OPND_Cat
:
6246 case AARCH64_OPND_Cat2
:
6247 case AARCH64_OPND_Cat_SYS
:
6248 po_reg_or_fail (REG_TYPE_CA_N_Z
);
6249 if (opcode
->op
== OP_MOV_C_ZR
&& operands
[i
] == AARCH64_OPND_Can
6252 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CA_Z
)));
6257 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CA_N
)));
6260 info
->reg
.regno
= val
;
6261 info
->qualifier
= AARCH64_OPND_QLF_CA
;
6264 case AARCH64_OPND_A64C_CST_REG
:
6265 po_reg_or_fail (REG_TYPE_CA_N
);
6267 && (opcode
->iclass
== br_sealed
))
6269 set_fatal_syntax_error
6270 (_(N_ ("Capability register c29 expected")));
6273 info
->reg
.regno
= val
;
6274 info
->qualifier
= AARCH64_OPND_QLF_CA
;
6277 case AARCH64_OPND_Cam_SP
:
6278 case AARCH64_OPND_Can_SP
:
6279 case AARCH64_OPND_Cad_SP
:
6280 po_reg_or_fail (REG_TYPE_CA_N_SP
);
6281 info
->reg
.regno
= val
;
6282 info
->qualifier
= AARCH64_OPND_QLF_CA
;
6285 case AARCH64_OPND_CRn
:
6286 case AARCH64_OPND_CRm
:
6288 char prefix
= *(str
++);
6289 if (prefix
!= 'c' && prefix
!= 'C')
6292 po_imm_nc_or_fail ();
6295 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6298 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6299 info
->imm
.value
= val
;
6303 case AARCH64_OPND_SHLL_IMM
:
6304 case AARCH64_OPND_IMM_VLSR
:
6305 po_imm_or_fail (1, 64);
6306 info
->imm
.value
= val
;
6309 case AARCH64_OPND_A64C_IMM8
:
6310 case AARCH64_OPND_CCMP_IMM
:
6311 case AARCH64_OPND_SIMM5
:
6312 case AARCH64_OPND_FBITS
:
6313 case AARCH64_OPND_TME_UIMM16
:
6314 case AARCH64_OPND_UIMM4
:
6315 case AARCH64_OPND_UIMM4_ADDG
:
6316 case AARCH64_OPND_UIMM10
:
6317 case AARCH64_OPND_UIMM3_OP1
:
6318 case AARCH64_OPND_UIMM3_OP2
:
6319 case AARCH64_OPND_IMM_VLSL
:
6320 case AARCH64_OPND_IMM
:
6321 case AARCH64_OPND_IMM_2
:
6322 case AARCH64_OPND_WIDTH
:
6323 case AARCH64_OPND_SVE_INV_LIMM
:
6324 case AARCH64_OPND_SVE_LIMM
:
6325 case AARCH64_OPND_SVE_LIMM_MOV
:
6326 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6327 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6328 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6329 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6330 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6331 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6332 case AARCH64_OPND_SVE_SIMM5
:
6333 case AARCH64_OPND_SVE_SIMM5B
:
6334 case AARCH64_OPND_SVE_SIMM6
:
6335 case AARCH64_OPND_SVE_SIMM8
:
6336 case AARCH64_OPND_SVE_UIMM3
:
6337 case AARCH64_OPND_SVE_UIMM7
:
6338 case AARCH64_OPND_SVE_UIMM8
:
6339 case AARCH64_OPND_SVE_UIMM8_53
:
6340 case AARCH64_OPND_IMM_ROT1
:
6341 case AARCH64_OPND_IMM_ROT2
:
6342 case AARCH64_OPND_IMM_ROT3
:
6343 case AARCH64_OPND_SVE_IMM_ROT1
:
6344 case AARCH64_OPND_SVE_IMM_ROT2
:
6345 case AARCH64_OPND_SVE_IMM_ROT3
:
6346 po_imm_nc_or_fail ();
6347 info
->imm
.value
= val
;
6350 case AARCH64_OPND_SVE_AIMM
:
6351 case AARCH64_OPND_SVE_ASIMM
:
6352 po_imm_nc_or_fail ();
6353 info
->imm
.value
= val
;
6354 skip_whitespace (str
);
6355 if (skip_past_comma (&str
))
6356 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6358 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6361 case AARCH64_OPND_SVE_PATTERN
:
6362 po_enum_or_fail (aarch64_sve_pattern_array
);
6363 info
->imm
.value
= val
;
6366 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6367 po_enum_or_fail (aarch64_sve_pattern_array
);
6368 info
->imm
.value
= val
;
6369 if (skip_past_comma (&str
)
6370 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6372 if (!info
->shifter
.operator_present
)
6374 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6375 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6376 info
->shifter
.amount
= 1;
6380 case AARCH64_OPND_SVE_PRFOP
:
6381 po_enum_or_fail (aarch64_sve_prfop_array
);
6382 info
->imm
.value
= val
;
6385 case AARCH64_OPND_UIMM7
:
6386 po_imm_or_fail (0, 127);
6387 info
->imm
.value
= val
;
6390 case AARCH64_OPND_IDX
:
6391 case AARCH64_OPND_MASK
:
6392 case AARCH64_OPND_BIT_NUM
:
6393 case AARCH64_OPND_IMMR
:
6394 case AARCH64_OPND_IMMS
:
6395 po_imm_or_fail (0, 63);
6396 info
->imm
.value
= val
;
6399 case AARCH64_OPND_A64C_IMMV4
:
6400 po_imm_nc_or_fail ();
6403 set_fatal_syntax_error (_("immediate #4 expected"));
6406 info
->imm
.value
= 4;
6409 case AARCH64_OPND_IMM0
:
6410 po_imm_nc_or_fail ();
6413 set_fatal_syntax_error (_("immediate zero expected"));
6416 info
->imm
.value
= 0;
6419 case AARCH64_OPND_FPIMM0
:
6422 bfd_boolean res1
= FALSE
, res2
= FALSE
;
6423 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6424 it is probably not worth the effort to support it. */
6425 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
6428 || !(res2
= parse_constant_immediate (&str
, &val
,
6431 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6433 info
->imm
.value
= 0;
6434 info
->imm
.is_fp
= 1;
6437 set_fatal_syntax_error (_("immediate zero expected"));
6441 case AARCH64_OPND_IMM_MOV
:
6444 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6445 reg_name_p (str
, REG_TYPE_VN
))
6448 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6450 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6451 later. fix_mov_imm_insn will try to determine a machine
6452 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6453 message if the immediate cannot be moved by a single
6455 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6456 inst
.base
.operands
[i
].skip
= 1;
6460 case AARCH64_OPND_SIMD_IMM
:
6461 case AARCH64_OPND_SIMD_IMM_SFT
:
6462 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6464 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6466 /* need_libopcodes_p */ 1,
6469 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6470 shift, we don't check it here; we leave the checking to
6471 the libopcodes (operand_general_constraint_met_p). By
6472 doing this, we achieve better diagnostics. */
6473 if (skip_past_comma (&str
)
6474 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6476 if (!info
->shifter
.operator_present
6477 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6479 /* Default to LSL if not present. Libopcodes prefers shifter
6480 kind to be explicit. */
6481 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6482 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6486 case AARCH64_OPND_FPIMM
:
6487 case AARCH64_OPND_SIMD_FPIMM
:
6488 case AARCH64_OPND_SVE_FPIMM8
:
6493 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6494 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6495 || !aarch64_imm_float_p (qfloat
))
6498 set_fatal_syntax_error (_("invalid floating-point"
6502 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6503 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6507 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6508 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6509 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6514 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6515 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6518 set_fatal_syntax_error (_("invalid floating-point"
6522 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6523 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6527 case AARCH64_OPND_LIMM
:
6528 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6529 SHIFTED_LOGIC_IMM
));
6530 if (info
->shifter
.operator_present
)
6532 set_fatal_syntax_error
6533 (_("shift not allowed for bitmask immediate"));
6536 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6538 /* need_libopcodes_p */ 1,
6542 case AARCH64_OPND_A64C_IMM6_EXT
:
6543 po_misc_or_fail (parse_shifter_operand_imm (&str
, info
,
6544 SHIFTED_ARITH_IMM
));
6546 if (inst
.reloc
.exp
.X_op
!= O_constant
)
6548 set_fatal_syntax_error (_(inst
.reloc
.exp
.X_op
== O_big
6549 ? "immediate out of range"
6550 : "expected constant expression"));
6554 /* Try to coerce into shifted form if the immediate is out of
6556 if (inst
.reloc
.exp
.X_add_number
> 63
6557 && (inst
.reloc
.exp
.X_add_number
& 0xf) == 0
6558 && (inst
.reloc
.exp
.X_add_number
>> 4) <= 63
6559 && info
->shifter
.amount
== 0)
6561 info
->shifter
.amount
= 4;
6562 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6563 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
>> 4;
6566 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6569 case AARCH64_OPND_AIMM
:
6570 case AARCH64_OPND_A64C_AIMM
:
6571 if (opcode
->op
== OP_ADD
|| opcode
->op
== OP_A64C_ADD
)
6572 /* ADD may have relocation types. */
6573 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6574 SHIFTED_ARITH_IMM
));
6576 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6577 SHIFTED_ARITH_IMM
));
6578 switch (inst
.reloc
.type
)
6580 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6581 info
->shifter
.amount
= 12;
6583 case BFD_RELOC_UNUSED
:
6584 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6585 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6586 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6587 inst
.reloc
.pc_rel
= 0;
6592 info
->imm
.value
= 0;
6593 if (!info
->shifter
.operator_present
)
6595 /* Default to LSL if not present. Libopcodes prefers shifter
6596 kind to be explicit. */
6597 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6598 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6602 case AARCH64_OPND_HALF
:
6604 /* #<imm16> or relocation. */
6605 int internal_fixup_p
;
6606 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6607 if (internal_fixup_p
)
6608 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6609 skip_whitespace (str
);
6610 if (skip_past_comma (&str
))
6612 /* {, LSL #<shift>} */
6613 if (! aarch64_gas_internal_fixup_p ())
6615 set_fatal_syntax_error (_("can't mix relocation modifier "
6616 "with explicit shift"));
6619 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6622 inst
.base
.operands
[i
].shifter
.amount
= 0;
6623 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6624 inst
.base
.operands
[i
].imm
.value
= 0;
6625 if (! process_movw_reloc_info ())
6630 case AARCH64_OPND_EXCEPTION
:
6631 case AARCH64_OPND_UNDEFINED
:
6632 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6634 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6636 /* need_libopcodes_p */ 0,
6640 case AARCH64_OPND_NZCV
:
6642 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6646 info
->imm
.value
= nzcv
->value
;
6649 po_imm_or_fail (0, 15);
6650 info
->imm
.value
= val
;
6654 case AARCH64_OPND_PERM
:
6655 po_misc_or_fail (parse_perms (&str
, info
));
6658 case AARCH64_OPND_FORM
:
6663 while (ISALPHA (*str
));
6664 info
->form
= get_form_from_str (start
, str
- start
);
6665 if (info
->form
== NULL
)
6667 set_syntax_error (_("invalid form"));
6673 case AARCH64_OPND_COND
:
6674 case AARCH64_OPND_COND1
:
6679 while (ISALPHA (*str
));
6680 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6681 if (info
->cond
== NULL
)
6683 set_syntax_error (_("invalid condition"));
6686 else if (operands
[i
] == AARCH64_OPND_COND1
6687 && (info
->cond
->value
& 0xe) == 0xe)
6689 /* Do not allow AL or NV. */
6690 set_default_error ();
6696 /* ADRP variants. Clear the value as operand needs to be
6698 case AARCH64_OPND_A64C_ADDR_ADRDP
:
6699 if (!AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
))
6701 as_bad (_("instruction not allowed on this processor"));
6704 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6706 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6708 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6709 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6710 if (info
->imm
.value
& 0xfff)
6713 info
->imm
.value
>>= 12;
6718 (_("20-bit 4K page aligned integer constant expected"));
6721 case AARCH64_OPND_ADDR_ADRP
:
6722 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
))
6723 info
->imm
.value
= 1UL << 20;
6725 info
->imm
.value
= 0;
6727 po_misc_or_fail (parse_adrp (&str
));
6730 case AARCH64_OPND_ADDR_PCREL14
:
6731 case AARCH64_OPND_ADDR_PCREL17
:
6732 case AARCH64_OPND_ADDR_PCREL19
:
6733 case AARCH64_OPND_ADDR_PCREL21
:
6734 case AARCH64_OPND_ADDR_PCREL26
:
6735 po_misc_or_fail (parse_address (&str
, info
));
6736 if (!info
->addr
.pcrel
)
6738 set_syntax_error (_("invalid pc-relative address"));
6741 if (inst
.gen_lit_pool
6742 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6744 /* Only permit "=value" in the literal load instructions.
6745 The literal will be generated by programmer_friendly_fixup. */
6746 set_syntax_error (_("invalid use of \"=immediate\""));
6749 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6751 set_syntax_error (_("unrecognized relocation suffix"));
6754 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6756 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6757 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6761 bfd_boolean c64
= AARCH64_CPU_HAS_FEATURE (cpu_variant
,
6762 AARCH64_FEATURE_C64
);
6764 info
->imm
.value
= 0;
6765 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6766 switch (opcode
->iclass
)
6770 /* e.g. CBZ or B.COND */
6771 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6772 inst
.reloc
.type
= (c64
? BFD_RELOC_MORELLO_BRANCH19
6773 : BFD_RELOC_AARCH64_BRANCH19
);
6777 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6778 inst
.reloc
.type
= (c64
? BFD_RELOC_MORELLO_TSTBR14
6779 : BFD_RELOC_AARCH64_TSTBR14
);
6784 bfd_reloc_code_real_type jump
, call
;
6786 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6788 jump
= (c64
? BFD_RELOC_MORELLO_JUMP26
6789 : BFD_RELOC_AARCH64_JUMP26
);
6790 call
= (c64
? BFD_RELOC_MORELLO_CALL26
6791 : BFD_RELOC_AARCH64_CALL26
);
6793 inst
.reloc
.type
= opcode
->op
== OP_BL
? call
: jump
;
6797 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
6798 || operands
[i
] == AARCH64_OPND_ADDR_PCREL17
);
6799 inst
.reloc
.type
= (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
6800 ? BFD_RELOC_AARCH64_LD_LO19_PCREL
6801 : BFD_RELOC_MORELLO_LD_LO17_PCREL
);
6804 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6805 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6812 inst
.reloc
.flags
= FIXUP_F_C64
;
6813 inst
.reloc
.pc_rel
= 1;
6817 case AARCH64_OPND_ADDR_SIMPLE
:
6818 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6820 /* [<Xn|SP>{, #<simm>}] */
6822 /* First use the normal address-parsing routines, to get
6823 the usual syntax errors. */
6824 po_misc_or_fail (parse_address (&str
, info
));
6825 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6826 || !info
->addr
.preind
|| info
->addr
.postind
6827 || info
->addr
.writeback
)
6829 set_syntax_error (_("invalid addressing mode"));
6833 /* Then retry, matching the specific syntax of these addresses. */
6835 po_char_or_fail ('[');
6836 po_reg_or_fail (AARCH64_CPU_HAS_FEATURE (cpu_variant
,
6837 AARCH64_FEATURE_C64
)
6838 ? REG_TYPE_CA_N_SP
: REG_TYPE_R64_SP
);
6840 /* Accept optional ", #0". */
6841 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6842 && skip_past_char (&str
, ','))
6844 skip_past_char (&str
, '#');
6845 if (! skip_past_char (&str
, '0'))
6847 set_fatal_syntax_error
6848 (_("the optional immediate offset can only be 0"));
6852 po_char_or_fail (']');
6856 case AARCH64_OPND_CAPADDR_REGOFF
:
6857 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6860 case AARCH64_OPND_ADDR_REGOFF
:
6861 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6862 po_misc_or_fail (parse_address (&str
, info
));
6864 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6865 || !info
->addr
.preind
|| info
->addr
.postind
6866 || info
->addr
.writeback
)
6868 set_syntax_error (_("invalid addressing mode"));
6871 if (!info
->shifter
.operator_present
)
6873 /* Default to LSL if not present. Libopcodes prefers shifter
6874 kind to be explicit. */
6875 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6876 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6878 /* Qualifier to be deduced by libopcodes. */
6881 case AARCH64_OPND_CAPADDR_SIMPLE
:
6882 case AARCH64_OPND_CAPADDR_SIMM7
:
6884 /* A little hack to prevent the address parser from trying to
6885 pretend that a BLR with a register may be a BLR with an
6886 address. It fails the addressing mode test below, but still
6887 ends up adding a symbol with the name of the register. */
6889 po_char_or_fail ('[');
6892 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6893 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6894 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6895 || info
->addr
.writeback
)
6897 set_syntax_error (_("invalid addressing mode"));
6900 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6902 set_syntax_error (_("relocation not allowed"));
6905 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6906 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6909 set_syntax_error (_("Invalid offset constant"));
6912 if (info
->type
== AARCH64_OPND_CAPADDR_SIMPLE
6913 && info
->addr
.offset
.imm
!= 0)
6915 set_syntax_error (_("non-zero offset not allowed"));
6921 case AARCH64_OPND_A64C_ADDR_SIMM7
:
6922 case AARCH64_OPND_ADDR_SIMM7
:
6923 po_misc_or_fail (parse_address (&str
, info
));
6924 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6925 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6927 set_syntax_error (_("invalid addressing mode"));
6930 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6932 set_syntax_error (_("relocation not allowed"));
6935 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6937 /* need_libopcodes_p */ 1,
6941 case AARCH64_OPND_CAPADDR_SIMM9
:
6942 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6945 case AARCH64_OPND_A64C_ADDR_SIMM9
:
6946 case AARCH64_OPND_ADDR_SIMM9
:
6947 case AARCH64_OPND_ADDR_SIMM9_2
:
6948 case AARCH64_OPND_ADDR_SIMM11
:
6949 case AARCH64_OPND_ADDR_SIMM13
:
6950 po_misc_or_fail (parse_address (&str
, info
));
6952 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6953 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6954 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6955 && info
->addr
.writeback
))
6957 set_syntax_error (_("invalid addressing mode"));
6960 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6962 set_syntax_error (_("relocation not allowed"));
6965 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6967 /* need_libopcodes_p */ 1,
6971 case AARCH64_OPND_ADDR_SIMM10
:
6972 case AARCH64_OPND_ADDR_OFFSET
:
6973 po_misc_or_fail (parse_address (&str
, info
));
6974 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6975 || !info
->addr
.preind
|| info
->addr
.postind
)
6977 set_syntax_error (_("invalid addressing mode"));
6980 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6982 set_syntax_error (_("relocation not allowed"));
6985 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6987 /* need_libopcodes_p */ 1,
6991 case AARCH64_OPND_CAPADDR_UIMM9
:
6992 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6995 case AARCH64_OPND_ADDR_UIMM12
:
6996 po_misc_or_fail (parse_address (&str
, info
));
6998 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6999 || !info
->addr
.preind
|| info
->addr
.writeback
)
7001 set_syntax_error (_("invalid addressing mode"));
7004 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7005 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7006 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7008 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7010 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7012 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7014 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7016 /* The altbase ldrb instruction does not have enough range to
7017 accommodate a LO12 relocation. */
7018 if (opcode
->flags
& F_NOSHIFT
&& opcode
->iclass
== ldst_altbase
)
7020 set_syntax_error (_("relocation not allowed"));
7024 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7026 else if ((inst
.reloc
.type
== BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7027 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
)
7028 && inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_CA
)
7029 inst
.reloc
.flags
= FIXUP_F_C64
;
7031 /* Leave qualifier to be determined by libopcodes. */
7034 case AARCH64_OPND_SIMD_ADDR_POST
:
7035 /* [<Xn|SP>], <Xm|#<amount>> */
7036 po_misc_or_fail (parse_address (&str
, info
));
7037 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7039 set_syntax_error (_("invalid addressing mode"));
7042 if (!info
->addr
.offset
.is_reg
)
7044 if (inst
.reloc
.exp
.X_op
== O_constant
)
7045 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7048 set_fatal_syntax_error
7049 (_("writeback value must be an immediate constant"));
7056 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7057 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7058 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7059 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7060 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7061 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7062 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7063 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7064 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7065 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7066 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7067 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7068 /* [X<n>{, #imm, MUL VL}]
7070 but recognizing SVE registers. */
7071 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7072 &offset_qualifier
));
7073 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7075 set_syntax_error (_("invalid addressing mode"));
7079 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7080 || !info
->addr
.preind
|| info
->addr
.writeback
)
7082 set_syntax_error (_("invalid addressing mode"));
7085 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7086 || inst
.reloc
.exp
.X_op
!= O_constant
)
7088 /* Make sure this has priority over
7089 "invalid addressing mode". */
7090 set_fatal_syntax_error (_("constant offset required"));
7093 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7096 case AARCH64_OPND_SVE_ADDR_R
:
7097 /* [<Xn|SP>{, <R><m>}]
7098 but recognizing SVE registers. */
7099 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7100 &offset_qualifier
));
7101 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7103 offset_qualifier
= AARCH64_OPND_QLF_X
;
7104 info
->addr
.offset
.is_reg
= 1;
7105 info
->addr
.offset
.regno
= 31;
7107 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7108 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7110 set_syntax_error (_("invalid addressing mode"));
7115 case AARCH64_OPND_SVE_ADDR_RR
:
7116 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7117 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7118 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7119 case AARCH64_OPND_SVE_ADDR_RX
:
7120 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7121 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7122 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7123 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7124 but recognizing SVE registers. */
7125 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7126 &offset_qualifier
));
7127 if (base_qualifier
!= AARCH64_OPND_QLF_X
7128 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7130 set_syntax_error (_("invalid addressing mode"));
7135 case AARCH64_OPND_SVE_ADDR_RZ
:
7136 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7137 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7138 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7139 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7140 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7141 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7142 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7143 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7144 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7145 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7146 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7147 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7148 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7149 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7150 &offset_qualifier
));
7151 if (base_qualifier
!= AARCH64_OPND_QLF_X
7152 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7153 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7155 set_syntax_error (_("invalid addressing mode"));
7158 info
->qualifier
= offset_qualifier
;
7161 case AARCH64_OPND_SVE_ADDR_ZX
:
7162 /* [Zn.<T>{, <Xm>}]. */
7163 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7164 &offset_qualifier
));
7166 base_qualifier either S_S or S_D
7167 offset_qualifier must be X
7169 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7170 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7171 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7173 set_syntax_error (_("invalid addressing mode"));
7176 info
->qualifier
= base_qualifier
;
7177 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7178 || !info
->addr
.preind
|| info
->addr
.writeback
7179 || info
->shifter
.operator_present
!= 0)
7181 set_syntax_error (_("invalid addressing mode"));
7184 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7188 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7189 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7190 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7191 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7192 /* [Z<n>.<T>{, #imm}] */
7193 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7194 &offset_qualifier
));
7195 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7196 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7198 set_syntax_error (_("invalid addressing mode"));
7201 info
->qualifier
= base_qualifier
;
7204 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7205 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7206 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7207 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7208 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7212 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7214 here since we get better error messages by leaving it to
7215 the qualifier checking routines. */
7216 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7217 &offset_qualifier
));
7218 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7219 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7220 || offset_qualifier
!= base_qualifier
)
7222 set_syntax_error (_("invalid addressing mode"));
7225 info
->qualifier
= base_qualifier
;
7228 case AARCH64_OPND_SYSREG
:
7230 uint32_t sysreg_flags
;
7232 if ((val
= parse_sys_reg (opcode
, &str
, aarch64_sys_regs_hsh
, 1, 0,
7233 &sysreg_flags
)) == PARSE_FAIL
)
7235 set_syntax_error (_("unknown or missing system register name"));
7238 inst
.base
.operands
[i
].sysreg
.value
= val
;
7239 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7243 case AARCH64_OPND_PSTATEFIELD
:
7244 if ((val
= parse_sys_reg (opcode
, &str
, aarch64_pstatefield_hsh
, 0, 1,
7248 set_syntax_error (_("unknown or missing PSTATE field name"));
7251 inst
.base
.operands
[i
].pstatefield
= val
;
7254 case AARCH64_OPND_SYSREG_IC
:
7255 inst
.base
.operands
[i
].sysins_op
=
7256 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7259 case AARCH64_OPND_SYSREG_DC
:
7260 inst
.base
.operands
[i
].sysins_op
=
7261 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7264 case AARCH64_OPND_SYSREG_AT
:
7265 inst
.base
.operands
[i
].sysins_op
=
7266 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7269 case AARCH64_OPND_SYSREG_SR
:
7270 inst
.base
.operands
[i
].sysins_op
=
7271 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7274 case AARCH64_OPND_SYSREG_TLBI
:
7275 inst
.base
.operands
[i
].sysins_op
=
7276 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7278 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7280 set_fatal_syntax_error ( _("unknown or missing operation name"));
7285 case AARCH64_OPND_BARRIER
:
7286 case AARCH64_OPND_BARRIER_ISB
:
7287 val
= parse_barrier (&str
);
7288 if (val
!= PARSE_FAIL
7289 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7291 /* ISB only accepts options name 'sy'. */
7293 (_("the specified option is not accepted in ISB"));
7294 /* Turn off backtrack as this optional operand is present. */
7298 /* This is an extension to accept a 0..15 immediate. */
7299 if (val
== PARSE_FAIL
)
7300 po_imm_or_fail (0, 15);
7301 info
->barrier
= aarch64_barrier_options
+ val
;
7304 case AARCH64_OPND_PRFOP
:
7305 val
= parse_pldop (&str
);
7306 /* This is an extension to accept a 0..31 immediate. */
7307 if (val
== PARSE_FAIL
)
7308 po_imm_or_fail (0, 31);
7309 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7312 case AARCH64_OPND_BARRIER_PSB
:
7313 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7314 if (val
== PARSE_FAIL
)
7318 case AARCH64_OPND_BTI_TARGET
:
7319 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7320 if (val
== PARSE_FAIL
)
7325 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7328 /* If we get here, this operand was successfully parsed. */
7329 inst
.base
.operands
[i
].present
= 1;
7333 /* The parse routine should already have set the error, but in case
7334 not, set a default one here. */
7336 set_default_error ();
7338 if (! backtrack_pos
)
7339 goto parse_operands_return
;
7342 /* We reach here because this operand is marked as optional, and
7343 either no operand was supplied or the operand was supplied but it
7344 was syntactically incorrect. In the latter case we report an
7345 error. In the former case we perform a few more checks before
7346 dropping through to the code to insert the default operand. */
7348 char *tmp
= backtrack_pos
;
7349 char endchar
= END_OF_INSN
;
7351 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7353 skip_past_char (&tmp
, ',');
7355 if (*tmp
!= endchar
)
7356 /* The user has supplied an operand in the wrong format. */
7357 goto parse_operands_return
;
7359 /* Make sure there is not a comma before the optional operand.
7360 For example the fifth operand of 'sys' is optional:
7362 sys #0,c0,c0,#0, <--- wrong
7363 sys #0,c0,c0,#0 <--- correct. */
7364 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7366 set_fatal_syntax_error
7367 (_("unexpected comma before the omitted optional operand"));
7368 goto parse_operands_return
;
7372 /* Reaching here means we are dealing with an optional operand that is
7373 omitted from the assembly line. */
7374 gas_assert (optional_operand_p (opcode
, i
));
7376 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7378 /* Try again, skipping the optional operand at backtrack_pos. */
7379 str
= backtrack_pos
;
7382 /* Clear any error record after the omitted optional operand has been
7383 successfully handled. */
7387 /* Check if we have parsed all the operands. */
7388 if (*str
!= '\0' && ! error_p ())
7390 /* Set I to the index of the last present operand; this is
7391 for the purpose of diagnostics. */
7392 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7394 set_fatal_syntax_error
7395 (_("unexpected characters following instruction"));
7398 parse_operands_return
:
7402 DEBUG_TRACE ("parsing FAIL: %s - %s",
7403 operand_mismatch_kind_names
[get_error_kind ()],
7404 get_error_message ());
7405 /* Record the operand error properly; this is useful when there
7406 are multiple instruction templates for a mnemonic name, so that
7407 later on, we can select the error that most closely describes
7409 record_operand_error (opcode
, i
, get_error_kind (),
7410 get_error_message ());
7415 DEBUG_TRACE ("parsing SUCCESS");
7420 /* It does some fix-up to provide some programmer friendly feature while
7421 keeping the libopcodes happy, i.e. libopcodes only accepts
7422 the preferred architectural syntax.
7423 Return FALSE if there is any failure; otherwise return TRUE. */
7426 programmer_friendly_fixup (aarch64_instruction
*instr
)
7428 aarch64_inst
*base
= &instr
->base
;
7429 const aarch64_opcode
*opcode
= base
->opcode
;
7430 enum aarch64_op op
= opcode
->op
;
7431 aarch64_opnd_info
*operands
= base
->operands
;
7433 DEBUG_TRACE ("enter");
7435 switch (opcode
->iclass
)
7438 /* TBNZ Xn|Wn, #uimm6, label
7439 Test and Branch Not Zero: conditionally jumps to label if bit number
7440 uimm6 in register Xn is not zero. The bit number implies the width of
7441 the register, which may be written and should be disassembled as Wn if
7442 uimm is less than 32. */
7443 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7445 if (operands
[1].imm
.value
>= 32)
7447 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7451 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7455 /* LDR Wt, label | =value
7456 As a convenience assemblers will typically permit the notation
7457 "=value" in conjunction with the pc-relative literal load instructions
7458 to automatically place an immediate value or symbolic address in a
7459 nearby literal pool and generate a hidden label which references it.
7460 ISREG has been set to 0 in the case of =value. */
7461 if (instr
->gen_lit_pool
7462 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
7463 || op
== OP_LDR_LIT_2
))
7465 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7466 if (op
== OP_LDRSW_LIT
)
7468 if (instr
->reloc
.exp
.X_op
!= O_constant
7469 && instr
->reloc
.exp
.X_op
!= O_big
7470 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7472 record_operand_error (opcode
, 1,
7473 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7474 _("constant expression expected"));
7477 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7479 record_operand_error (opcode
, 1,
7480 AARCH64_OPDE_OTHER_ERROR
,
7481 _("literal pool insertion failed"));
7489 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7490 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7491 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7492 A programmer-friendly assembler should accept a destination Xd in
7493 place of Wd, however that is not the preferred form for disassembly.
7495 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7496 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7497 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7498 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7503 /* In the 64-bit form, the final register operand is written as Wm
7504 for all but the (possibly omitted) UXTX/LSL and SXTX
7506 As a programmer-friendly assembler, we accept e.g.
7507 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7508 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7509 int idx
= aarch64_operand_index (opcode
->operands
,
7510 AARCH64_OPND_Rm_EXT
);
7511 gas_assert (idx
== 1 || idx
== 2);
7512 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7513 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7514 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7515 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7516 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7517 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7525 DEBUG_TRACE ("exit with SUCCESS");
7529 /* Check for loads and stores that will cause unpredictable behavior. */
7532 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7534 aarch64_inst
*base
= &instr
->base
;
7535 const aarch64_opcode
*opcode
= base
->opcode
;
7536 const aarch64_opnd_info
*opnds
= base
->operands
;
7537 switch (opcode
->iclass
)
7544 /* Loading/storing the base register is unpredictable if writeback. */
7545 if ((aarch64_get_operand_class (opnds
[0].type
)
7546 == AARCH64_OPND_CLASS_INT_REG
)
7547 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7548 && opnds
[1].addr
.base_regno
!= REG_SP
7549 /* Exempt STG/STZG/ST2G/STZ2G. */
7550 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7551 && opnds
[1].addr
.writeback
)
7552 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7556 case ldstnapair_offs
:
7557 case ldstpair_indexed
:
7558 /* Loading/storing the base register is unpredictable if writeback. */
7559 if ((aarch64_get_operand_class (opnds
[0].type
)
7560 == AARCH64_OPND_CLASS_INT_REG
)
7561 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7562 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7563 && opnds
[2].addr
.base_regno
!= REG_SP
7565 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7566 && opnds
[2].addr
.writeback
)
7567 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7568 /* Load operations must load different registers. */
7569 if ((opcode
->opcode
& (1 << 22))
7570 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7571 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7575 /* It is unpredictable if the destination and status registers are the
7577 if ((aarch64_get_operand_class (opnds
[0].type
)
7578 == AARCH64_OPND_CLASS_INT_REG
)
7579 && (aarch64_get_operand_class (opnds
[1].type
)
7580 == AARCH64_OPND_CLASS_INT_REG
7581 || (aarch64_get_operand_class (opnds
[1].type
)
7582 == AARCH64_OPND_CLASS_CAP_REG
))
7583 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
7584 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
7585 as_warn (_("unpredictable: identical transfer and status registers"
7597 force_automatic_sequence_close (void)
7599 if (now_instr_sequence
.instr
)
7601 as_warn (_("previous `%s' sequence has not been closed"),
7602 now_instr_sequence
.instr
->opcode
->name
);
7603 init_insn_sequence (NULL
, &now_instr_sequence
);
7607 /* A wrapper function to interface with libopcodes on encoding and
7608 record the error message if there is any.
7610 Return TRUE on success; otherwise return FALSE. */
7613 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7616 aarch64_operand_error error_info
;
7617 memset (&error_info
, '\0', sizeof (error_info
));
7618 error_info
.kind
= AARCH64_OPDE_NIL
;
7619 if (aarch64_opcode_encode (cpu_variant
, opcode
, instr
, code
, NULL
,
7620 &error_info
, insn_sequence
)
7621 && !error_info
.non_fatal
)
7624 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7625 record_operand_error_info (opcode
, &error_info
);
7626 return error_info
.non_fatal
;
7629 #ifdef DEBUG_AARCH64
7631 dump_opcode_operands (const aarch64_opcode
*opcode
)
7634 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7636 aarch64_verbose ("\t\t opnd%d: %s", i
,
7637 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7638 ? aarch64_get_operand_name (opcode
->operands
[i
])
7639 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7643 #endif /* DEBUG_AARCH64 */
7645 /* This is the guts of the machine-dependent assembler. STR points to a
7646 machine dependent instruction. This function is supposed to emit
7647 the frags/bytes it assembles to. */
7650 md_assemble (char *str
)
7653 templates
*template;
7654 aarch64_opcode
*opcode
;
7655 aarch64_inst
*inst_base
;
7656 unsigned saved_cond
;
7658 /* Align the previous label if needed. */
7659 if (last_label_seen
!= NULL
)
7661 symbol_set_frag (last_label_seen
, frag_now
);
7662 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7663 S_SET_SEGMENT (last_label_seen
, now_seg
);
7666 /* Update the current insn_sequence from the segment. */
7667 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7669 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7671 DEBUG_TRACE ("\n\n");
7672 DEBUG_TRACE ("==============================");
7673 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7675 template = opcode_lookup (&p
);
7678 /* It wasn't an instruction, but it might be a register alias of
7679 the form alias .req reg directive. */
7680 if (!create_register_alias (str
, p
))
7681 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7686 skip_whitespace (p
);
7689 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7690 get_mnemonic_name (str
), str
);
7694 init_operand_error_report ();
7696 /* Sections are assumed to start aligned. In executable section, there is no
7697 MAP_DATA symbol pending. So we only align the address during
7698 MAP_DATA --> MAP_CUR_INSN transition.
7699 For other sections, this is not guaranteed. */
7700 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7701 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7702 frag_align_code (2, 0);
7704 saved_cond
= inst
.cond
;
7705 reset_aarch64_instruction (&inst
);
7706 inst
.cond
= saved_cond
;
7708 /* Iterate through all opcode entries with the same mnemonic name. */
7711 opcode
= template->opcode
;
7713 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7714 #ifdef DEBUG_AARCH64
7716 dump_opcode_operands (opcode
);
7717 #endif /* DEBUG_AARCH64 */
7719 mapping_state (MAP_CUR_INSN
);
7721 inst_base
= &inst
.base
;
7722 inst_base
->opcode
= opcode
;
7724 /* Truly conditionally executed instructions, e.g. b.cond. */
7725 if (opcode
->flags
& F_COND
)
7727 gas_assert (inst
.cond
!= COND_ALWAYS
);
7728 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7729 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7731 else if (inst
.cond
!= COND_ALWAYS
)
7733 /* It shouldn't arrive here, where the assembly looks like a
7734 conditional instruction but the found opcode is unconditional. */
7739 if (parse_operands (p
, opcode
)
7740 && programmer_friendly_fixup (&inst
)
7741 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7743 /* Check that this instruction is supported for this CPU. */
7744 if (!opcode
->avariant
7745 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7747 as_bad (_("selected processor does not support `%s'"), str
);
7751 warn_unpredictable_ldst (&inst
, str
);
7753 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7754 || !inst
.reloc
.need_libopcodes_p
)
7758 /* If there is relocation generated for the instruction,
7759 store the instruction information for the future fix-up. */
7760 struct aarch64_inst
*copy
;
7761 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7762 copy
= XNEW (struct aarch64_inst
);
7763 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7767 /* Issue non-fatal messages if any. */
7768 output_operand_error_report (str
, TRUE
);
7772 template = template->next
;
7773 if (template != NULL
)
7775 reset_aarch64_instruction (&inst
);
7776 inst
.cond
= saved_cond
;
7779 while (template != NULL
);
7781 /* Issue the error messages if any. */
7782 output_operand_error_report (str
, FALSE
);
7785 /* Various frobbings of labels and their addresses. */
7788 aarch64_start_line_hook (void)
7790 last_label_seen
= NULL
;
7794 aarch64_frob_label (symbolS
* sym
)
7796 last_label_seen
= sym
;
7798 AARCH64_SET_C64 (sym
, IS_C64
);
7799 if (AARCH64_IS_C64 (sym
) && S_IS_FUNCTION (sym
))
7801 gas_assert ((*symbol_X_add_number (sym
) & 1) == 0);
7802 *symbol_X_add_number (sym
) += 1;
7805 dwarf2_emit_label (sym
);
7809 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7811 /* Check to see if we have a block to close. */
7812 force_automatic_sequence_close ();
7816 aarch64_data_in_code (void)
7818 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7820 *input_line_pointer
= '/';
7821 input_line_pointer
+= 5;
7822 *input_line_pointer
= 0;
7830 aarch64_canonicalize_symbol_name (char *name
)
7834 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7835 *(name
+ len
- 5) = 0;
7840 /* Table of all register names defined by default. The user can
7841 define additional names with .req. Note that all register names
7842 should appear in both upper and lowercase variants. Some registers
7843 also have mixed-case names. */
7845 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7846 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7847 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7848 #define REGSET16(p,t) \
7849 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7850 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7851 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7852 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7853 #define REGSET31(p,t) \
7855 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7856 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7857 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7858 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7859 #define REGSET(p,t) \
7860 REGSET31(p,t), REGNUM(p,31,t)
7862 /* These go into aarch64_reg_hsh hash-table. */
7863 static const reg_entry reg_names
[] = {
7864 /* Integer registers. */
7865 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7866 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7868 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7869 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7870 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7871 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7872 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7873 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7875 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7876 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7878 /* Capability Registers. */
7879 REGSET31 (c
, CA_N
), REGSET31 (C
, CA_N
),
7880 REGDEF (csp
, 31, CA_SP
), REGDEF (CSP
, 31, CA_SP
),
7881 REGDEF (czr
, 31, CA_Z
), REGDEF (CZR
, 31, CA_Z
),
7882 REGDEF (ddc
, 33, CA_D
), REGDEF (DDC
, 33, CA_D
),
7883 REGDEF_ALIAS (clr
, 30, CA_N
), REGDEF_ALIAS (CLR
, 30, CA_N
),
7885 /* Floating-point single precision registers. */
7886 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7888 /* Floating-point double precision registers. */
7889 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7891 /* Floating-point half precision registers. */
7892 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7894 /* Floating-point byte precision registers. */
7895 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7897 /* Floating-point quad precision registers. */
7898 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7900 /* FP/SIMD registers. */
7901 REGSET (v
, VN
), REGSET (V
, VN
),
7903 /* SVE vector registers. */
7904 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7906 /* SVE predicate registers. */
7907 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7925 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7926 static const asm_nzcv nzcv_names
[] = {
7927 {"nzcv", B (n
, z
, c
, v
)},
7928 {"nzcV", B (n
, z
, c
, V
)},
7929 {"nzCv", B (n
, z
, C
, v
)},
7930 {"nzCV", B (n
, z
, C
, V
)},
7931 {"nZcv", B (n
, Z
, c
, v
)},
7932 {"nZcV", B (n
, Z
, c
, V
)},
7933 {"nZCv", B (n
, Z
, C
, v
)},
7934 {"nZCV", B (n
, Z
, C
, V
)},
7935 {"Nzcv", B (N
, z
, c
, v
)},
7936 {"NzcV", B (N
, z
, c
, V
)},
7937 {"NzCv", B (N
, z
, C
, v
)},
7938 {"NzCV", B (N
, z
, C
, V
)},
7939 {"NZcv", B (N
, Z
, c
, v
)},
7940 {"NZcV", B (N
, Z
, c
, V
)},
7941 {"NZCv", B (N
, Z
, C
, v
)},
7942 {"NZCV", B (N
, Z
, C
, V
)}
7955 /* MD interface: bits in the object file. */
7957 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7958 for use in the a.out file, and stores them in the array pointed to by buf.
7959 This knows about the endian-ness of the target machine and does
7960 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7961 2 (short) and 4 (long) Floating numbers are put out as a series of
7962 LITTLENUMS (shorts, here at least). */
7965 md_number_to_chars (char *buf
, valueT val
, int n
)
7967 if (target_big_endian
)
7968 number_to_chars_bigendian (buf
, val
, n
);
7970 number_to_chars_littleendian (buf
, val
, n
);
7973 /* MD interface: Sections. */
7975 /* Estimate the size of a frag before relaxing. Assume everything fits in
7979 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7985 /* Round up a section size to the appropriate boundary. */
7988 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7993 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7994 of an rs_align_code fragment.
7996 Here we fill the frag with the appropriate info for padding the
7997 output stream. The resulting frag will consist of a fixed (fr_fix)
7998 and of a repeating (fr_var) part.
8000 The fixed content is always emitted before the repeating content and
8001 these two parts are used as follows in constructing the output:
8002 - the fixed part will be used to align to a valid instruction word
8003 boundary, in case that we start at a misaligned address; as no
8004 executable instruction can live at the misaligned location, we
8005 simply fill with zeros;
8006 - the variable part will be used to cover the remaining padding and
8007 we fill using the AArch64 NOP instruction.
8009 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8010 enough storage space for up to 3 bytes for padding the back to a valid
8011 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8014 aarch64_handle_align (fragS
* fragP
)
8016 /* NOP = d503201f */
8017 /* AArch64 instructions are always little-endian. */
8018 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8020 int bytes
, fix
, noop_size
;
8023 if (fragP
->fr_type
!= rs_align_code
)
8026 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8027 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8030 gas_assert (fragP
->tc_frag_data
.recorded
);
8033 noop_size
= sizeof (aarch64_noop
);
8035 fix
= bytes
& (noop_size
- 1);
8039 insert_data_mapping_symbol (MAP_CUR_INSN
, fragP
->fr_fix
, fragP
, fix
);
8043 fragP
->fr_fix
+= fix
;
8047 memcpy (p
, aarch64_noop
, noop_size
);
8048 fragP
->fr_var
= noop_size
;
8051 /* Perform target specific initialisation of a frag.
8052 Note - despite the name this initialisation is not done when the frag
8053 is created, but only when its type is assigned. A frag can be created
8054 and used a long time before its type is set, so beware of assuming that
8055 this initialisation is performed first. */
8059 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8060 int max_chars ATTRIBUTE_UNUSED
)
8064 #else /* OBJ_ELF is defined. */
8066 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8068 /* Record a mapping symbol for alignment frags. We will delete this
8069 later if the alignment ends up empty. */
8070 if (!fragP
->tc_frag_data
.recorded
)
8071 fragP
->tc_frag_data
.recorded
= 1;
8073 /* PR 21809: Do not set a mapping state for debug sections
8074 - it just confuses other tools. */
8075 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8078 switch (fragP
->fr_type
)
8082 mapping_state_2 (MAP_DATA
, max_chars
);
8085 /* PR 20364: We can get alignment frags in code sections,
8086 so do not just assume that we should use the MAP_DATA state. */
8087 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_CUR_INSN
: MAP_DATA
, max_chars
);
8090 mapping_state_2 (MAP_CUR_INSN
, max_chars
);
8097 /* Initialize the DWARF-2 unwind information for this procedure. */
8100 tc_aarch64_frame_initial_instructions (void)
8104 cfi_set_return_column (REG_DW_CLR
);
8105 cfi_add_CFA_def_cfa (REG_DW_CSP
, 0);
8108 cfi_add_CFA_def_cfa (REG_SP
, 0);
8112 /* The extra initialisation steps needed by AArch64 in alloc_fde_entry.
8113 Currently only used to initialise the key used to sign the return
8116 tc_aarch64_fde_entry_init_extra(struct fde_entry
*fde
)
8118 fde
->entry_extras
.pauth_key
= AARCH64_PAUTH_KEY_A
;
8119 fde
->entry_extras
.c64
= IS_C64
;
8123 tc_aarch64_cfi_startproc_exp (const char *arg
)
8125 /* Allow purecap only for C64 functions. */
8126 if (!strcmp ("purecap", arg
) && IS_C64
)
8132 #endif /* OBJ_ELF */
8134 /* Convert REGNAME to a DWARF-2 register number. */
8137 tc_aarch64_regname_to_dw2regnum (char *regname
)
8139 const reg_entry
*reg
= parse_reg (®name
);
8145 case REG_TYPE_SP_32
:
8146 case REG_TYPE_SP_64
:
8156 return reg
->number
+ 64;
8159 case REG_TYPE_CA_SP
:
8161 return reg
->number
+ 198;
8169 /* Implement DWARF2_ADDR_SIZE. */
8172 aarch64_dwarf2_addr_size (void)
8174 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8178 return bfd_arch_bits_per_address (stdoutput
) / 8;
8181 /* MD interface: Symbol and relocation handling. */
8183 /* Return the address within the segment that a PC-relative fixup is
8184 relative to. For AArch64 PC-relative fixups applied to instructions
8185 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8188 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8190 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8192 /* If this is pc-relative and we are going to emit a relocation
8193 then we just want to put out any pipeline compensation that the linker
8194 will need. Otherwise we want to use the calculated base. */
8196 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8197 || aarch64_force_relocation (fixP
)))
8200 /* AArch64 should be consistent for all pc-relative relocations. */
8201 return base
+ AARCH64_PCREL_OFFSET
;
8204 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8205 Otherwise we have no need to default values of symbols. */
8208 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8211 if (name
[0] == '_' && name
[1] == 'G'
8212 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8216 if (symbol_find (name
))
8217 as_bad (_("GOT already in the symbol table"));
8219 GOT_symbol
= symbol_new (name
, undefined_section
,
8220 &zero_address_frag
, 0);
8230 /* Return non-zero if the indicated VALUE has overflowed the maximum
8231 range expressible by a unsigned number with the indicated number of
8235 unsigned_overflow (valueT value
, unsigned bits
)
8238 if (bits
>= sizeof (valueT
) * 8)
8240 lim
= (valueT
) 1 << bits
;
8241 return (value
>= lim
);
8245 /* Return non-zero if the indicated VALUE has overflowed the maximum
8246 range expressible by an signed number with the indicated number of
8250 signed_overflow (offsetT value
, unsigned bits
)
8253 if (bits
>= sizeof (offsetT
) * 8)
8255 lim
= (offsetT
) 1 << (bits
- 1);
8256 return (value
< -lim
|| value
>= lim
);
8259 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8260 unsigned immediate offset load/store instruction, try to encode it as
8261 an unscaled, 9-bit, signed immediate offset load/store instruction.
8262 Return TRUE if it is successful; otherwise return FALSE.
8264 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8265 in response to the standard LDR/STR mnemonics when the immediate offset is
8266 unambiguous, i.e. when it is negative or unaligned. */
8269 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8272 enum aarch64_op new_op
;
8273 const aarch64_opcode
*new_opcode
;
8274 enum aarch64_opnd target
;
8276 gas_assert (instr
->opcode
->iclass
== ldst_pos
8277 || instr
->opcode
->iclass
== ldst_altbase
);
8279 target
= (instr
->opcode
->iclass
== ldst_pos
? AARCH64_OPND_ADDR_SIMM9
8280 : AARCH64_OPND_CAPADDR_SIMM9
);
8282 switch (instr
->opcode
->op
)
8284 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8285 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8286 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8287 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8288 case OP_LDRH_POS_A
: new_op
= OP_LDURH_A
; break;
8290 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8291 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8292 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8293 case OP_STR_POS
: new_op
= OP_STUR
; break;
8294 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8295 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8296 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8297 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8298 case OP_LDR_POS_C
: new_op
= OP_LDUR_C
; break;
8299 case OP_STR_POS_C
: new_op
= OP_STUR_C
; break;
8300 case OP_LDRB_POS_A
:new_op
= OP_LDURB_A
; break;
8301 case OP_STRB_POS_A
: new_op
= OP_STURB_A
; break;
8302 case OP_LDR_POS_AC
: new_op
= OP_LDUR_AC
; break;
8303 case OP_LDR_POS_AX
: new_op
= OP_LDUR_AX
; break;
8304 case OP_STR_POS_AC
: new_op
= OP_STUR_AC
; break;
8305 case OP_STR_POS_AX
: new_op
= OP_STUR_AX
; break;
8307 case OP_LDRFP_POS_A
: new_op
= OP_LDURFP_A
; break;
8308 case OP_LDRFPQ_POS_A
: new_op
= OP_LDURFPQ_POS_A
; break;
8309 case OP_STRFP_POS_A
: new_op
= OP_STURFP_POS_A
; break;
8310 case OP_STRFPQ_POS_A
: new_op
= OP_STURFPQ_POS_A
; break;
8312 default: new_op
= OP_NIL
; break;
8315 if (new_op
== OP_NIL
)
8318 new_opcode
= aarch64_get_opcode (new_op
);
8319 gas_assert (new_opcode
!= NULL
);
8321 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8322 instr
->opcode
->op
, new_opcode
->op
);
8324 aarch64_replace_opcode (instr
, new_opcode
);
8326 /* Clear up the address operand's qualifier; otherwise the
8327 qualifier matching may fail because the out-of-date qualifier will
8328 prevent the operand being updated with a new and correct qualifier. */
8329 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8331 gas_assert (idx
== 1);
8332 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8334 DEBUG_TRACE ("Found LDUR entry to encode programmer-friendly LDR");
8336 if (!aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
, &instr
->value
,
8337 NULL
, NULL
, insn_sequence
))
8343 /* Called by fix_insn to fix a MOV immediate alias instruction.
8345 Operand for a generic move immediate instruction, which is an alias
8346 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8347 a 32-bit/64-bit immediate value into general register. An assembler error
8348 shall result if the immediate cannot be created by a single one of these
8349 instructions. If there is a choice, then to ensure reversability an
8350 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8353 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8355 const aarch64_opcode
*opcode
;
8357 /* Need to check if the destination is SP/ZR. The check has to be done
8358 before any aarch64_replace_opcode. */
8359 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8360 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8362 instr
->operands
[1].imm
.value
= value
;
8363 instr
->operands
[1].skip
= 0;
8367 /* Try the MOVZ alias. */
8368 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8369 aarch64_replace_opcode (instr
, opcode
);
8370 if (aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
,
8371 &instr
->value
, NULL
, NULL
, insn_sequence
))
8373 put_aarch64_insn (buf
, instr
->value
);
8376 /* Try the MOVK alias. */
8377 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8378 aarch64_replace_opcode (instr
, opcode
);
8379 if (aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
,
8380 &instr
->value
, NULL
, NULL
, insn_sequence
))
8382 put_aarch64_insn (buf
, instr
->value
);
8387 if (try_mov_bitmask_p
)
8389 /* Try the ORR alias. */
8390 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8391 aarch64_replace_opcode (instr
, opcode
);
8392 if (aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
,
8393 &instr
->value
, NULL
, NULL
, insn_sequence
))
8395 put_aarch64_insn (buf
, instr
->value
);
8400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8401 _("immediate cannot be moved by a single instruction"));
8404 /* An instruction operand which is immediate related may have symbol used
8405 in the assembly, e.g.
8408 .set u32, 0x00ffff00
8410 At the time when the assembly instruction is parsed, a referenced symbol,
8411 like 'u32' in the above example may not have been seen; a fixS is created
8412 in such a case and is handled here after symbols have been resolved.
8413 Instruction is fixed up with VALUE using the information in *FIXP plus
8414 extra information in FLAGS.
8416 This function is called by md_apply_fix to fix up instructions that need
8417 a fix-up described above but does not involve any linker-time relocation. */
8420 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8424 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8425 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8426 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8430 /* Now the instruction is about to be fixed-up, so the operand that
8431 was previously marked as 'ignored' needs to be unmarked in order
8432 to get the encoding done properly. */
8433 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8434 new_inst
->operands
[idx
].skip
= 0;
8437 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8441 case AARCH64_OPND_EXCEPTION
:
8442 case AARCH64_OPND_UNDEFINED
:
8443 if (unsigned_overflow (value
, 16))
8444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8445 _("immediate out of range"));
8446 insn
= get_aarch64_insn (buf
);
8447 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8448 put_aarch64_insn (buf
, insn
);
8451 case AARCH64_OPND_AIMM
:
8452 case AARCH64_OPND_A64C_AIMM
:
8453 /* ADD or SUB with immediate.
8454 NOTE this assumes we come here with a add/sub shifted reg encoding
8455 3 322|2222|2 2 2 21111 111111
8456 1 098|7654|3 2 1 09876 543210 98765 43210
8457 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8458 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8459 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8460 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8462 3 322|2222|2 2 221111111111
8463 1 098|7654|3 2 109876543210 98765 43210
8464 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8465 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8466 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8467 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8468 Fields sf Rn Rd are already set. */
8469 insn
= get_aarch64_insn (buf
);
8473 insn
= reencode_addsub_switch_add_sub (insn
);
8477 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8478 && unsigned_overflow (value
, 12))
8480 /* Try to shift the value by 12 to make it fit. */
8481 if (((value
>> 12) << 12) == value
8482 && ! unsigned_overflow (value
, 12 + 12))
8485 insn
|= encode_addsub_imm_shift_amount (1);
8489 if (unsigned_overflow (value
, 12))
8490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8491 _("immediate out of range"));
8493 insn
|= encode_addsub_imm (value
);
8495 put_aarch64_insn (buf
, insn
);
8498 case AARCH64_OPND_SIMD_IMM
:
8499 case AARCH64_OPND_SIMD_IMM_SFT
:
8500 case AARCH64_OPND_LIMM
:
8501 /* Bit mask immediate. */
8502 gas_assert (new_inst
!= NULL
);
8503 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8504 new_inst
->operands
[idx
].imm
.value
= value
;
8505 if (aarch64_opcode_encode (cpu_variant
, new_inst
->opcode
, new_inst
,
8506 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8507 put_aarch64_insn (buf
, new_inst
->value
);
8509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8510 _("invalid immediate"));
8513 case AARCH64_OPND_HALF
:
8514 /* 16-bit unsigned immediate. */
8515 if (unsigned_overflow (value
, 16))
8516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8517 _("immediate out of range"));
8518 insn
= get_aarch64_insn (buf
);
8519 insn
|= encode_movw_imm (value
& 0xffff);
8520 put_aarch64_insn (buf
, insn
);
8523 case AARCH64_OPND_IMM_MOV
:
8524 /* Operand for a generic move immediate instruction, which is
8525 an alias instruction that generates a single MOVZ, MOVN or ORR
8526 instruction to loads a 32-bit/64-bit immediate value into general
8527 register. An assembler error shall result if the immediate cannot be
8528 created by a single one of these instructions. If there is a choice,
8529 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8530 and MOVZ or MOVN to ORR. */
8531 gas_assert (new_inst
!= NULL
);
8532 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8535 case AARCH64_OPND_CAPADDR_UIMM9
:
8536 case AARCH64_OPND_A64C_ADDR_SIMM9
:
8537 case AARCH64_OPND_A64C_ADDR_SIMM7
:
8538 case AARCH64_OPND_ADDR_SIMM7
:
8539 case AARCH64_OPND_ADDR_SIMM9
:
8540 case AARCH64_OPND_ADDR_SIMM9_2
:
8541 case AARCH64_OPND_ADDR_SIMM10
:
8542 case AARCH64_OPND_ADDR_UIMM12
:
8543 case AARCH64_OPND_ADDR_SIMM11
:
8544 case AARCH64_OPND_ADDR_SIMM13
:
8545 /* Immediate offset in an address. */
8546 insn
= get_aarch64_insn (buf
);
8548 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8549 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8550 || new_inst
->opcode
->operands
[2] == opnd
);
8552 /* Get the index of the address operand. */
8553 if (new_inst
->opcode
->operands
[1] == opnd
)
8554 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8557 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8560 /* Update the resolved offset value. */
8561 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8563 /* Encode/fix-up. */
8564 if (aarch64_opcode_encode (cpu_variant
, new_inst
->opcode
, new_inst
,
8565 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8567 put_aarch64_insn (buf
, new_inst
->value
);
8570 else if ((new_inst
->opcode
->iclass
== ldst_pos
8571 || new_inst
->opcode
->iclass
== ldst_altbase
)
8572 && try_to_encode_as_unscaled_ldst (new_inst
))
8574 put_aarch64_insn (buf
, new_inst
->value
);
8578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8579 _("immediate offset out of range"));
8584 as_fatal (_("unhandled operand code %d"), opnd
);
8588 /* Apply a fixup (fixP) to segment data, once it has been determined
8589 by our caller that we have all the info we need to fix it up.
8591 Parameter valP is the pointer to the value of the bits. */
8594 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8596 offsetT value
= *valP
;
8598 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8600 unsigned flags
= fixP
->fx_addnumber
;
8601 /* We check alignment for relocations of this kind. These relocations could
8602 be applied on a C64 STT_FUNC symbol and hence may have the LSB set on
8603 `*valP`, their AARCH64 counterparts can not be applied on such symbols and
8604 hence should never have the LSB set on their value. */
8605 valueT alignment_mask
= (fixP
->fx_r_type
== BFD_RELOC_MORELLO_BRANCH19
8606 || fixP
->fx_r_type
== BFD_RELOC_MORELLO_TSTBR14
8607 || fixP
->fx_r_type
== BFD_RELOC_MORELLO_CALL26
8608 || fixP
->fx_r_type
== BFD_RELOC_MORELLO_JUMP26
)
8611 DEBUG_TRACE ("\n\n");
8612 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8613 DEBUG_TRACE ("Enter md_apply_fix");
8615 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8617 /* Note whether this will delete the relocation. */
8619 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8622 /* Process the relocations. */
8623 switch (fixP
->fx_r_type
)
8625 case BFD_RELOC_NONE
:
8626 /* This will need to go in the object file. */
8631 case BFD_RELOC_8_PCREL
:
8632 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8633 md_number_to_chars (buf
, value
, 1);
8637 case BFD_RELOC_16_PCREL
:
8638 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8639 md_number_to_chars (buf
, value
, 2);
8643 case BFD_RELOC_32_PCREL
:
8644 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8645 md_number_to_chars (buf
, value
, 4);
8649 case BFD_RELOC_64_PCREL
:
8650 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8651 md_number_to_chars (buf
, value
, 8);
8654 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8655 /* We claim that these fixups have been processed here, even if
8656 in fact we generate an error because we do not have a reloc
8657 for them, so tc_gen_reloc() will reject them. */
8659 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8662 _("undefined symbol %s used as an immediate value"),
8663 S_GET_NAME (fixP
->fx_addsy
));
8664 goto apply_fix_return
;
8666 fix_insn (fixP
, flags
, value
);
8669 case BFD_RELOC_MORELLO_LD_LO17_PCREL
:
8670 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8672 /* The LDR-immediate that uses LO17 aligns the address down to
8673 16-byte boundary to get the final address of the capability.
8674 Since the fixed up immediate also needs to be 16-byte aligned,
8675 align it up to the 16-byte boundary so that the downward alignment
8676 of the load literal instruction gets us the correct address. */
8677 value
= (value
+ 0xf) & ~(offsetT
) 0xf;
8679 if (signed_overflow (value
, 21))
8680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8681 _("pcc-relative load offset out of range"));
8682 insn
= get_aarch64_insn (buf
);
8683 insn
|= encode_ld_lit_ofs_17 (value
>> 4);
8684 put_aarch64_insn (buf
, insn
);
8688 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8689 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8693 _("pc-relative load offset not word aligned"));
8694 if (signed_overflow (value
, 21))
8695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8696 _("pc-relative load offset out of range"));
8697 insn
= get_aarch64_insn (buf
);
8698 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8699 put_aarch64_insn (buf
, insn
);
8703 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8704 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8706 if (signed_overflow (value
, 21))
8707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8708 _("pc-relative address offset out of range"));
8709 insn
= get_aarch64_insn (buf
);
8710 insn
|= encode_adr_imm (value
);
8711 put_aarch64_insn (buf
, insn
);
8715 case BFD_RELOC_AARCH64_BRANCH19
:
8716 case BFD_RELOC_MORELLO_BRANCH19
:
8717 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8719 if (value
& alignment_mask
)
8720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8721 _("conditional branch target not word aligned"));
8722 if (signed_overflow (value
, 21))
8723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8724 _("conditional branch out of range"));
8725 insn
= get_aarch64_insn (buf
);
8726 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8727 put_aarch64_insn (buf
, insn
);
8731 case BFD_RELOC_MORELLO_TSTBR14
:
8732 case BFD_RELOC_AARCH64_TSTBR14
:
8733 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8735 if (value
& alignment_mask
)
8736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8737 _("conditional branch target not word aligned"));
8738 if (signed_overflow (value
, 16))
8739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8740 _("conditional branch out of range"));
8741 insn
= get_aarch64_insn (buf
);
8742 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8743 put_aarch64_insn (buf
, insn
);
8747 case BFD_RELOC_MORELLO_CALL26
:
8748 case BFD_RELOC_MORELLO_JUMP26
:
8749 case BFD_RELOC_AARCH64_CALL26
:
8750 case BFD_RELOC_AARCH64_JUMP26
:
8751 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8753 if (value
& alignment_mask
)
8754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8755 _("branch target not word aligned"));
8756 if (signed_overflow (value
, 28))
8757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8758 _("branch out of range"));
8759 insn
= get_aarch64_insn (buf
);
8760 insn
|= encode_branch_ofs_26 (value
>> 2);
8761 put_aarch64_insn (buf
, insn
);
8765 case BFD_RELOC_MORELLO_MOVW_SIZE_G0
:
8766 case BFD_RELOC_MORELLO_MOVW_SIZE_G0_NC
:
8767 case BFD_RELOC_AARCH64_MOVW_G0
:
8768 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8769 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8770 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8771 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8772 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8775 case BFD_RELOC_MORELLO_MOVW_SIZE_G1
:
8776 case BFD_RELOC_MORELLO_MOVW_SIZE_G1_NC
:
8777 case BFD_RELOC_AARCH64_MOVW_G1
:
8778 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8779 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8780 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8781 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8782 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8785 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8787 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8788 /* Should always be exported to object file, see
8789 aarch64_force_relocation(). */
8790 gas_assert (!fixP
->fx_done
);
8791 gas_assert (seg
->use_rela_p
);
8793 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8795 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8796 /* Should always be exported to object file, see
8797 aarch64_force_relocation(). */
8798 gas_assert (!fixP
->fx_done
);
8799 gas_assert (seg
->use_rela_p
);
8801 case BFD_RELOC_MORELLO_MOVW_SIZE_G2
:
8802 case BFD_RELOC_MORELLO_MOVW_SIZE_G2_NC
:
8803 case BFD_RELOC_AARCH64_MOVW_G2
:
8804 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8805 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8806 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8807 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8810 case BFD_RELOC_MORELLO_MOVW_SIZE_G3
:
8811 case BFD_RELOC_AARCH64_MOVW_G3
:
8812 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8815 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8817 insn
= get_aarch64_insn (buf
);
8821 /* REL signed addend must fit in 16 bits */
8822 if (signed_overflow (value
, 16))
8823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8824 _("offset out of range"));
8828 /* Check for overflow and scale. */
8829 switch (fixP
->fx_r_type
)
8831 case BFD_RELOC_MORELLO_MOVW_SIZE_G0
:
8832 case BFD_RELOC_MORELLO_MOVW_SIZE_G1
:
8833 case BFD_RELOC_MORELLO_MOVW_SIZE_G2
:
8834 case BFD_RELOC_MORELLO_MOVW_SIZE_G3
:
8835 case BFD_RELOC_AARCH64_MOVW_G0
:
8836 case BFD_RELOC_AARCH64_MOVW_G1
:
8837 case BFD_RELOC_AARCH64_MOVW_G2
:
8838 case BFD_RELOC_AARCH64_MOVW_G3
:
8839 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8840 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8841 if (unsigned_overflow (value
, scale
+ 16))
8842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8843 _("unsigned value out of range"));
8845 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8846 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8847 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8848 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8849 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8850 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8851 /* NOTE: We can only come here with movz or movn. */
8852 if (signed_overflow (value
, scale
+ 16))
8853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8854 _("signed value out of range"));
8857 /* Force use of MOVN. */
8859 insn
= reencode_movzn_to_movn (insn
);
8863 /* Force use of MOVZ. */
8864 insn
= reencode_movzn_to_movz (insn
);
8868 /* Unchecked relocations. */
8874 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8875 insn
|= encode_movw_imm (value
& 0xffff);
8877 put_aarch64_insn (buf
, insn
);
8881 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8882 fixP
->fx_r_type
= (ilp32_p
8883 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8884 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8885 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8886 /* Should always be exported to object file, see
8887 aarch64_force_relocation(). */
8888 gas_assert (!fixP
->fx_done
);
8889 gas_assert (seg
->use_rela_p
);
8892 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8893 if (fixP
->tc_fix_data
.c64
)
8894 fixP
->fx_r_type
= BFD_RELOC_MORELLO_TLSDESC_LD128_LO12
;
8896 fixP
->fx_r_type
= BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
;
8898 fixP
->fx_r_type
= BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
;
8899 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8900 /* Should always be exported to object file, see
8901 aarch64_force_relocation(). */
8902 gas_assert (!fixP
->fx_done
);
8903 gas_assert (seg
->use_rela_p
);
8906 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8907 case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20
:
8908 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8909 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8910 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8911 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8912 case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12
:
8913 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8914 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8915 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8916 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8917 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8918 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8919 case BFD_RELOC_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20
:
8920 case BFD_RELOC_MORELLO_TLSIE_ADD_LO12
:
8921 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8922 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8923 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8924 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8925 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8926 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8927 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8928 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8929 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8930 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8931 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8932 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8933 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8934 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8935 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8936 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8937 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8938 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8939 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8940 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8941 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8942 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8943 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8944 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8945 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8946 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8947 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8948 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8949 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8950 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8951 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8952 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8953 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8954 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8955 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8956 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8957 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8958 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8959 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8960 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8961 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8962 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8963 /* Should always be exported to object file, see
8964 aarch64_force_relocation(). */
8965 gas_assert (!fixP
->fx_done
);
8966 gas_assert (seg
->use_rela_p
);
8969 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8970 /* Should always be exported to object file, see
8971 aarch64_force_relocation(). */
8972 if (fixP
->tc_fix_data
.c64
)
8973 fixP
->fx_r_type
= BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
;
8975 fixP
->fx_r_type
= BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
;
8977 fixP
->fx_r_type
= BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
;
8978 gas_assert (!fixP
->fx_done
);
8979 gas_assert (seg
->use_rela_p
);
8982 case BFD_RELOC_AARCH64_ADD_LO12
:
8983 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8984 case BFD_RELOC_MORELLO_ADR_GOT_PAGE
:
8985 case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
:
8986 case BFD_RELOC_MORELLO_ADR_HI20_PCREL
:
8987 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8988 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8989 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8990 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8991 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8992 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8993 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8994 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8995 case BFD_RELOC_AARCH64_LDST128_LO12
:
8996 case BFD_RELOC_AARCH64_LDST16_LO12
:
8997 case BFD_RELOC_AARCH64_LDST32_LO12
:
8998 case BFD_RELOC_AARCH64_LDST64_LO12
:
8999 case BFD_RELOC_AARCH64_LDST8_LO12
:
9000 case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
:
9001 /* Should always be exported to object file, see
9002 aarch64_force_relocation(). */
9003 gas_assert (!fixP
->fx_done
);
9004 gas_assert (seg
->use_rela_p
);
9007 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9008 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9009 case BFD_RELOC_MORELLO_TLSDESC_CALL
:
9010 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9011 case BFD_RELOC_MORELLO_CAPINIT
:
9014 case BFD_RELOC_UNUSED
:
9015 /* An error will already have been reported. */
9019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9020 _("unexpected %s fixup"),
9021 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9026 /* Free the allocated the struct aarch64_inst.
9027 N.B. currently there are very limited number of fix-up types actually use
9028 this field, so the impact on the performance should be minimal . */
9029 free (fixP
->tc_fix_data
.inst
);
9034 /* Translate internal representation of relocation info to BFD target
9038 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9041 bfd_reloc_code_real_type code
;
9043 reloc
= XNEW (arelent
);
9045 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9046 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9047 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9051 if (section
->use_rela_p
)
9052 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9054 fixp
->fx_offset
= reloc
->address
;
9056 reloc
->addend
= fixp
->fx_offset
;
9058 code
= fixp
->fx_r_type
;
9063 code
= BFD_RELOC_16_PCREL
;
9068 code
= BFD_RELOC_32_PCREL
;
9073 code
= BFD_RELOC_64_PCREL
;
9080 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9081 if (reloc
->howto
== NULL
)
9083 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9085 ("cannot represent %s relocation in this object file format"),
9086 bfd_get_reloc_code_name (code
));
9093 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9096 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9098 bfd_reloc_code_real_type type
;
9102 FIXME: @@ Should look at CPU word size. */
9109 type
= BFD_RELOC_16
;
9112 type
= BFD_RELOC_32
;
9115 type
= BFD_RELOC_64
;
9118 as_bad (_("cannot do %u-byte relocation"), size
);
9119 type
= BFD_RELOC_UNUSED
;
9123 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9127 aarch64_force_relocation (struct fix
*fixp
)
9129 switch (fixp
->fx_r_type
)
9131 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
9132 /* Perform these "immediate" internal relocations
9133 even if the symbol is extern or weak. */
9136 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9137 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9138 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9139 /* Pseudo relocs that need to be fixed up according to
9143 case BFD_RELOC_AARCH64_ADD_LO12
:
9144 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9145 case BFD_RELOC_MORELLO_ADR_GOT_PAGE
:
9146 case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
:
9147 case BFD_RELOC_MORELLO_ADR_HI20_PCREL
:
9148 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9149 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9150 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9151 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9152 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9153 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9154 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9155 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9156 case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
:
9157 case BFD_RELOC_AARCH64_LDST128_LO12
:
9158 case BFD_RELOC_AARCH64_LDST16_LO12
:
9159 case BFD_RELOC_AARCH64_LDST32_LO12
:
9160 case BFD_RELOC_AARCH64_LDST64_LO12
:
9161 case BFD_RELOC_AARCH64_LDST8_LO12
:
9162 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9163 case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20
:
9164 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9165 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9166 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9167 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9168 case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12
:
9169 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9170 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9171 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9172 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9173 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9174 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9175 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9176 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9177 case BFD_RELOC_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20
:
9178 case BFD_RELOC_MORELLO_TLSIE_ADD_LO12
:
9179 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9180 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9181 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9182 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9183 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9184 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9185 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9186 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9187 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9188 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9189 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9190 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9191 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9192 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9193 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9194 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9195 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9196 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9197 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9198 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9199 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9200 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9201 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9202 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9203 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9204 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9205 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9206 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9207 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9208 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9209 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9210 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9211 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9212 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9213 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9214 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9215 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9216 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9217 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9218 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9219 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9220 /* Always leave these relocations for the linker. */
9223 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9224 case BFD_RELOC_MORELLO_BRANCH19
:
9225 case BFD_RELOC_MORELLO_TSTBR14
:
9226 case BFD_RELOC_AARCH64_BRANCH19
:
9227 case BFD_RELOC_AARCH64_TSTBR14
:
9228 case BFD_RELOC_MORELLO_CALL26
:
9229 case BFD_RELOC_MORELLO_JUMP26
:
9230 case BFD_RELOC_AARCH64_CALL26
:
9231 case BFD_RELOC_AARCH64_JUMP26
:
9232 gas_assert (fixp
->fx_addsy
!= NULL
);
9234 /* A jump/call destination will get adjusted to section+offset only
9235 if both caller and callee are of the same type. */
9236 if (symbol_section_p (fixp
->fx_addsy
))
9239 if ((fixp
->tc_fix_data
.c64
9240 && !AARCH64_IS_C64 (fixp
->fx_addsy
))
9241 || (!fixp
->tc_fix_data
.c64
9242 && AARCH64_IS_C64 (fixp
->fx_addsy
)))
9251 return generic_force_reloc (fixp
);
9256 /* Implement md_after_parse_args. This is the earliest time we need to decide
9257 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9260 aarch64_after_parse_args (void)
9262 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9265 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9266 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9267 aarch64_abi
= AARCH64_ABI_ILP32
;
9269 aarch64_abi
= AARCH64_ABI_LP64
;
9273 elf64_aarch64_target_format (void)
9276 /* FIXME: What to do for ilp32_p ? */
9277 if (target_big_endian
)
9278 return "elf64-bigaarch64-cloudabi";
9280 return "elf64-littleaarch64-cloudabi";
9282 if (target_big_endian
)
9283 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9285 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9290 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9292 elf_frob_symbol (symp
, puntp
);
9296 /* MD interface: Finalization. */
9298 /* A good place to do this, although this was probably not intended
9299 for this kind of use. We need to dump the literal pool before
9300 references are made to a null symbol pointer. */
9303 aarch64_cleanup (void)
9307 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9309 /* Put it at the end of the relevant section. */
9310 subseg_set (pool
->section
, pool
->sub_section
);
9316 /* Remove any excess mapping symbols generated for alignment frags in
9317 SEC. We may have created a mapping symbol before a zero byte
9318 alignment; remove it if there's a mapping symbol after the
9321 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9322 void *dummy ATTRIBUTE_UNUSED
)
9324 segment_info_type
*seginfo
= seg_info (sec
);
9327 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9330 for (fragp
= seginfo
->frchainP
->frch_root
;
9331 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9333 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9334 fragS
*next
= fragp
->fr_next
;
9336 /* Variable-sized frags have been converted to fixed size by
9337 this point. But if this was variable-sized to start with,
9338 there will be a fixed-size frag after it. So don't handle
9340 if (sym
== NULL
|| next
== NULL
)
9343 if (S_GET_VALUE (sym
) < next
->fr_address
)
9344 /* Not at the end of this frag. */
9346 know (S_GET_VALUE (sym
) == next
->fr_address
);
9350 if (next
->tc_frag_data
.first_map
!= NULL
)
9352 /* Next frag starts with a mapping symbol. Discard this
9354 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9358 if (next
->fr_next
== NULL
)
9360 /* This mapping symbol is at the end of the section. Discard
9362 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9363 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9367 /* As long as we have empty frags without any mapping symbols,
9369 /* If the next frag is non-empty and does not start with a
9370 mapping symbol, then this mapping symbol is required. */
9371 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9374 next
= next
->fr_next
;
9376 while (next
!= NULL
);
9381 /* Avoid relocations from using section symbols in some cases. */
9383 aarch64_fix_adjustable (struct fix
*fixP
)
9385 switch (fixP
->fx_r_type
)
9387 /* The AArch64 GNU bfd linker can not handle 'symbol + offset' entries in the
9388 GOT (it internally uses a symbol to reference a GOT slot). Hence we can't
9389 emit any "section symbol + offset" relocations for the GOT. */
9390 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9391 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9392 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9393 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9394 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9395 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9396 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9397 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9398 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9399 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9400 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9401 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9402 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9403 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9404 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9405 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9406 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9409 /* We need size information of the target symbols to initialise
9411 case BFD_RELOC_MORELLO_CAPINIT
:
9412 case BFD_RELOC_MORELLO_ADR_GOT_PAGE
:
9413 case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
:
9416 /* We need to retain symbol information when jumping between A64 and C64
9417 states or between two C64 functions. In the C64 -> C64 situation it's
9418 really only a corner case that breaks when symbols get replaced with
9419 section symbols; this is when the jump distance is longer than what a
9420 branch instruction can handle and we want to branch through a stub.
9421 In such a case, the linker needs to know the symbol types of the
9422 source and the destination and section symbols are an unreliable
9423 source of this information. */
9424 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9425 case BFD_RELOC_AARCH64_ADD_LO12
:
9426 case BFD_RELOC_AARCH64_BRANCH19
:
9427 case BFD_RELOC_AARCH64_TSTBR14
:
9428 case BFD_RELOC_AARCH64_JUMP26
:
9429 case BFD_RELOC_AARCH64_CALL26
:
9430 case BFD_RELOC_MORELLO_BRANCH19
:
9431 case BFD_RELOC_MORELLO_TSTBR14
:
9432 case BFD_RELOC_MORELLO_JUMP26
:
9433 case BFD_RELOC_MORELLO_CALL26
:
9434 if (fixP
->tc_fix_data
.c64
|| AARCH64_IS_C64 (fixP
->fx_addsy
))
9444 /* Adjust the symbol table. */
9447 aarch64_adjust_symtab (void)
9452 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
9454 if (AARCH64_IS_C64 (sym
)
9455 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
))
9457 elf_symbol_type
* elf_sym
;
9459 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
9461 if (!bfd_is_aarch64_special_symbol_name
9462 (elf_sym
->symbol
.name
, BFD_AARCH64_SPECIAL_SYM_TYPE_ANY
))
9463 elf_sym
->internal_elf_sym
.st_target_internal
= ST_BRANCH_TO_C64
;
9467 /* Remove any overlapping mapping symbols generated by alignment frags. */
9468 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9469 /* Now do generic ELF adjustments. */
9470 elf_adjust_symtab ();
9475 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9477 str_hash_insert (table
, key
, value
, 0);
9481 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9483 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9484 checked_hash_insert (table
, key
, value
);
9488 fill_instruction_hash_table (void)
9490 aarch64_opcode
*opcode
= aarch64_opcode_table
;
9492 while (opcode
->name
!= NULL
)
9494 templates
*templ
, *new_templ
;
9495 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9497 new_templ
= XNEW (templates
);
9498 new_templ
->opcode
= opcode
;
9499 new_templ
->next
= NULL
;
9502 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9505 new_templ
->next
= templ
->next
;
9506 templ
->next
= new_templ
;
9513 convert_to_upper (char *dst
, const char *src
, size_t num
)
9516 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9517 *dst
= TOUPPER (*src
);
9521 /* Assume STR point to a lower-case string, allocate, convert and return
9522 the corresponding upper-case string. */
9523 static inline const char*
9524 get_upper_str (const char *str
)
9527 size_t len
= strlen (str
);
9528 ret
= XNEWVEC (char, len
+ 1);
9529 convert_to_upper (ret
, str
, len
);
9533 /* MD interface: Initialization. */
9541 aarch64_ops_hsh
= str_htab_create ();
9542 aarch64_cond_hsh
= str_htab_create ();
9543 aarch64_shift_hsh
= str_htab_create ();
9544 aarch64_sys_regs_hsh
= str_htab_create ();
9545 aarch64_pstatefield_hsh
= str_htab_create ();
9546 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9547 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9548 aarch64_sys_regs_at_hsh
= str_htab_create ();
9549 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9550 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9551 aarch64_reg_hsh
= str_htab_create ();
9552 aarch64_barrier_opt_hsh
= str_htab_create ();
9553 aarch64_nzcv_hsh
= str_htab_create ();
9554 aarch64_pldop_hsh
= str_htab_create ();
9555 aarch64_hint_opt_hsh
= str_htab_create ();
9557 fill_instruction_hash_table ();
9559 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9560 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9561 (void *) (aarch64_sys_regs
+ i
));
9563 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9564 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9565 aarch64_pstatefields
[i
].name
,
9566 (void *) (aarch64_pstatefields
+ i
));
9568 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9569 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9570 aarch64_sys_regs_ic
[i
].name
,
9571 (void *) (aarch64_sys_regs_ic
+ i
));
9573 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9574 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9575 aarch64_sys_regs_dc
[i
].name
,
9576 (void *) (aarch64_sys_regs_dc
+ i
));
9578 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9579 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9580 aarch64_sys_regs_at
[i
].name
,
9581 (void *) (aarch64_sys_regs_at
+ i
));
9583 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9584 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9585 aarch64_sys_regs_tlbi
[i
].name
,
9586 (void *) (aarch64_sys_regs_tlbi
+ i
));
9588 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9589 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9590 aarch64_sys_regs_sr
[i
].name
,
9591 (void *) (aarch64_sys_regs_sr
+ i
));
9593 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9594 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9595 (void *) (reg_names
+ i
));
9597 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9598 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9599 (void *) (nzcv_names
+ i
));
9601 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9603 const char *name
= aarch64_operand_modifiers
[i
].name
;
9604 checked_hash_insert (aarch64_shift_hsh
, name
,
9605 (void *) (aarch64_operand_modifiers
+ i
));
9606 /* Also hash the name in the upper case. */
9607 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9608 (void *) (aarch64_operand_modifiers
+ i
));
9611 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9614 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9615 the same condition code. */
9616 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9618 const char *name
= aarch64_conds
[i
].names
[j
];
9621 checked_hash_insert (aarch64_cond_hsh
, name
,
9622 (void *) (aarch64_conds
+ i
));
9623 /* Also hash the name in the upper case. */
9624 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9625 (void *) (aarch64_conds
+ i
));
9629 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9631 const char *name
= aarch64_barrier_options
[i
].name
;
9632 /* Skip xx00 - the unallocated values of option. */
9635 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9636 (void *) (aarch64_barrier_options
+ i
));
9637 /* Also hash the name in the upper case. */
9638 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9639 (void *) (aarch64_barrier_options
+ i
));
9642 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9644 const char* name
= aarch64_prfops
[i
].name
;
9645 /* Skip the unallocated hint encodings. */
9648 checked_hash_insert (aarch64_pldop_hsh
, name
,
9649 (void *) (aarch64_prfops
+ i
));
9650 /* Also hash the name in the upper case. */
9651 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9652 (void *) (aarch64_prfops
+ i
));
9655 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9657 const char* name
= aarch64_hint_options
[i
].name
;
9658 const char* upper_name
= get_upper_str(name
);
9660 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9661 (void *) (aarch64_hint_options
+ i
));
9663 /* Also hash the name in the upper case if not the same. */
9664 if (strcmp (name
, upper_name
) != 0)
9665 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9666 (void *) (aarch64_hint_options
+ i
));
9669 /* Set the cpu variant based on the command-line options. */
9671 mcpu_cpu_opt
= march_cpu_opt
;
9674 mcpu_cpu_opt
= &cpu_default
;
9676 cpu_variant
= *mcpu_cpu_opt
;
9678 /* Record the CPU type. */
9679 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
9681 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9685 bfd_set_private_flags (stdoutput
, EF_AARCH64_CHERI_PURECAP
);
9689 /* Command line processing. */
9691 const char *md_shortopts
= "m:";
9693 #ifdef AARCH64_BI_ENDIAN
9694 #define OPTION_EB (OPTION_MD_BASE + 0)
9695 #define OPTION_EL (OPTION_MD_BASE + 1)
9697 #if TARGET_BYTES_BIG_ENDIAN
9698 #define OPTION_EB (OPTION_MD_BASE + 0)
9700 #define OPTION_EL (OPTION_MD_BASE + 1)
9704 struct option md_longopts
[] = {
9706 {"EB", no_argument
, NULL
, OPTION_EB
},
9709 {"EL", no_argument
, NULL
, OPTION_EL
},
9711 {NULL
, no_argument
, NULL
, 0}
9714 size_t md_longopts_size
= sizeof (md_longopts
);
9716 struct aarch64_option_table
9718 const char *option
; /* Option name to match. */
9719 const char *help
; /* Help information. */
9720 int *var
; /* Variable to change. */
9721 int value
; /* What to change it to. */
9722 char *deprecated
; /* If non-null, print this message. */
9725 static struct aarch64_option_table aarch64_opts
[] = {
9726 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9727 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9729 #ifdef DEBUG_AARCH64
9730 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9731 #endif /* DEBUG_AARCH64 */
9732 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9734 {"mno-verbose-error", N_("do not output verbose error messages"),
9735 &verbose_error_p
, 0, NULL
},
9736 {NULL
, NULL
, NULL
, 0, NULL
}
9739 struct aarch64_cpu_option_table
9742 const aarch64_feature_set value
;
9743 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9745 const char *canonical_name
;
9748 /* This list should, at a minimum, contain all the cpu names
9749 recognized by GCC. */
9750 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9751 {"all", AARCH64_ANY
, NULL
},
9752 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9753 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9754 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9755 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9756 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9757 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9758 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9759 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9760 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9761 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9762 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9763 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9764 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9765 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9767 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9768 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9770 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9771 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9773 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9774 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9775 | AARCH64_FEATURE_DOTPROD
9776 | AARCH64_FEATURE_SSBS
),
9778 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9779 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9780 | AARCH64_FEATURE_DOTPROD
9781 | AARCH64_FEATURE_SSBS
),
9783 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9784 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9785 | AARCH64_FEATURE_DOTPROD
9786 | AARCH64_FEATURE_SSBS
),
9788 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9789 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9790 | AARCH64_FEATURE_DOTPROD
9791 | AARCH64_FEATURE_SSBS
),
9793 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9795 | AARCH64_FEATURE_RCPC
9796 | AARCH64_FEATURE_DOTPROD
9797 | AARCH64_FEATURE_SSBS
9798 | AARCH64_FEATURE_PROFILE
),
9800 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9802 | AARCH64_FEATURE_RCPC
9803 | AARCH64_FEATURE_DOTPROD
9804 | AARCH64_FEATURE_SSBS
9805 | AARCH64_FEATURE_PROFILE
),
9807 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9808 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9809 | AARCH64_FEATURE_DOTPROD
9810 | AARCH64_FEATURE_PROFILE
),
9812 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9813 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9814 "Samsung Exynos M1"},
9815 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9816 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9817 | AARCH64_FEATURE_RDMA
),
9819 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9820 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9821 | AARCH64_FEATURE_DOTPROD
9822 | AARCH64_FEATURE_SSBS
),
9824 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9825 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9826 | AARCH64_FEATURE_DOTPROD
9827 | AARCH64_FEATURE_PROFILE
),
9829 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9830 AARCH64_FEATURE_BFLOAT16
9831 | AARCH64_FEATURE_I8MM
9832 | AARCH64_FEATURE_F16
9833 | AARCH64_FEATURE_SVE
9834 | AARCH64_FEATURE_SVE2
9835 | AARCH64_FEATURE_SVE2_BITPERM
9836 | AARCH64_FEATURE_MEMTAG
9837 | AARCH64_FEATURE_RNG
),
9839 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9840 AARCH64_FEATURE_PROFILE
9841 | AARCH64_FEATURE_CVADP
9842 | AARCH64_FEATURE_SVE
9843 | AARCH64_FEATURE_SSBS
9844 | AARCH64_FEATURE_RNG
9845 | AARCH64_FEATURE_F16
9846 | AARCH64_FEATURE_BFLOAT16
9847 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9848 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9849 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9850 | AARCH64_FEATURE_RDMA
),
9851 "Qualcomm QDF24XX"},
9852 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9853 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9854 "Qualcomm Saphira"},
9855 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9856 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9858 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9859 AARCH64_FEATURE_CRYPTO
),
9861 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9862 in earlier releases and is superseded by 'xgene1' in all
9864 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9865 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9866 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9867 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9868 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9869 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9871 | AARCH64_FEATURE_RCPC
9872 | AARCH64_FEATURE_DOTPROD
9873 | AARCH64_FEATURE_SSBS
9874 | AARCH64_FEATURE_PROFILE
),
9876 {"generic", AARCH64_ARCH_V8
, NULL
},
9878 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9881 struct aarch64_arch_option_table
9884 const aarch64_feature_set value
;
9887 /* This list should, at a minimum, contain all the architecture names
9888 recognized by GCC. */
9889 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9890 {"all", AARCH64_ANY
},
9891 {"armv8-a", AARCH64_ARCH_V8
},
9892 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9893 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9894 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9895 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9896 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9897 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9898 {"armv8-r", AARCH64_ARCH_V8_R
},
9899 {"morello", AARCH64_ARCH_MORELLO
},
9900 {NULL
, AARCH64_ARCH_NONE
}
9903 /* ISA extensions. */
9904 struct aarch64_option_cpu_value_table
9907 const aarch64_feature_set value
;
9908 const aarch64_feature_set require
; /* Feature dependencies. */
9911 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9912 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9914 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9915 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9916 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9918 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9920 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9921 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9922 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9924 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9926 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9928 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9929 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9930 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9931 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9932 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9933 AARCH64_FEATURE (AARCH64_FEATURE_FP
9934 | AARCH64_FEATURE_F16
, 0)},
9935 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9937 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9938 AARCH64_FEATURE (AARCH64_FEATURE_F16
9939 | AARCH64_FEATURE_SIMD
9940 | AARCH64_FEATURE_COMPNUM
, 0)},
9941 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9943 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9944 AARCH64_FEATURE (AARCH64_FEATURE_F16
9945 | AARCH64_FEATURE_SIMD
, 0)},
9946 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9948 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9950 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9952 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9954 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9956 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9958 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9960 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9961 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9962 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9964 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9966 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9968 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9969 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9970 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9971 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9972 | AARCH64_FEATURE_SM4
, 0)},
9973 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9974 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9975 | AARCH64_FEATURE_AES
, 0)},
9976 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9977 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9978 | AARCH64_FEATURE_SHA3
, 0)},
9979 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9980 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9981 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9983 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9985 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9986 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9987 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9988 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9989 {"a64c", AARCH64_FEATURE (AARCH64_FEATURE_A64C
, 0),
9991 {"c64", AARCH64_FEATURE (AARCH64_FEATURE_C64
, 0),
9992 AARCH64_FEATURE (AARCH64_FEATURE_A64C
, 0)},
9993 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9996 struct aarch64_long_option_table
9998 const char *option
; /* Substring to match. */
9999 const char *help
; /* Help information. */
10000 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10001 char *deprecated
; /* If non-null, print this message. */
10004 /* Transitive closure of features depending on set. */
10005 static aarch64_feature_set
10006 aarch64_feature_disable_set (aarch64_feature_set set
)
10008 const struct aarch64_option_cpu_value_table
*opt
;
10009 aarch64_feature_set prev
= 0;
10011 while (prev
!= set
) {
10013 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10014 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10015 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10020 /* Transitive closure of dependencies of set. */
10021 static aarch64_feature_set
10022 aarch64_feature_enable_set (aarch64_feature_set set
)
10024 const struct aarch64_option_cpu_value_table
*opt
;
10025 aarch64_feature_set prev
= 0;
10027 while (prev
!= set
) {
10029 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10030 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10031 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10037 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10038 bfd_boolean ext_only
)
10040 /* We insist on extensions being added before being removed. We achieve
10041 this by using the ADDING_VALUE variable to indicate whether we are
10042 adding an extension (1) or removing it (0) and only allowing it to
10043 change in the order -1 -> 1 -> 0. */
10044 int adding_value
= -1;
10045 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10047 /* Copy the feature set, so that we can modify it. */
10048 *ext_set
= **opt_p
;
10051 while (str
!= NULL
&& *str
!= 0)
10053 const struct aarch64_option_cpu_value_table
*opt
;
10054 const char *ext
= NULL
;
10061 as_bad (_("invalid architectural extension"));
10065 ext
= strchr (++str
, '+');
10069 optlen
= ext
- str
;
10071 optlen
= strlen (str
);
10073 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
10075 if (adding_value
!= 0)
10080 else if (optlen
> 0)
10082 if (adding_value
== -1)
10084 else if (adding_value
!= 1)
10086 as_bad (_("must specify extensions to add before specifying "
10087 "those to remove"));
10094 as_bad (_("missing architectural extension"));
10098 gas_assert (adding_value
!= -1);
10100 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10101 if (strncmp (opt
->name
, str
, optlen
) == 0)
10103 aarch64_feature_set set
;
10105 /* Add or remove the extension. */
10108 set
= aarch64_feature_enable_set (opt
->value
);
10109 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10113 set
= aarch64_feature_disable_set (opt
->value
);
10114 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10119 if (opt
->name
== NULL
)
10121 as_bad (_("unknown architectural extension `%s'"), str
);
10132 aarch64_parse_cpu (const char *str
)
10134 const struct aarch64_cpu_option_table
*opt
;
10135 const char *ext
= strchr (str
, '+');
10139 optlen
= ext
- str
;
10141 optlen
= strlen (str
);
10145 as_bad (_("missing cpu name `%s'"), str
);
10149 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10150 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10152 mcpu_cpu_opt
= &opt
->value
;
10154 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
10159 as_bad (_("unknown cpu `%s'"), str
);
10164 aarch64_parse_arch (const char *str
)
10166 const struct aarch64_arch_option_table
*opt
;
10167 const char *ext
= strchr (str
, '+');
10171 optlen
= ext
- str
;
10173 optlen
= strlen (str
);
10177 as_bad (_("missing architecture name `%s'"), str
);
10181 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10182 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10184 march_cpu_opt
= &opt
->value
;
10186 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
10191 as_bad (_("unknown architecture `%s'\n"), str
);
10196 struct aarch64_option_abi_value_table
10199 enum aarch64_abi_type value
;
10202 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10203 {"ilp32", AARCH64_ABI_ILP32
},
10204 {"lp64", AARCH64_ABI_LP64
},
10205 /* Note that these values are accepted since they are valid parameters to
10206 the -mabi argument for GCC. However we base no decision on them. */
10207 {"purecap", AARCH64_ABI_PURECAP
},
10208 {"hybrid", AARCH64_ABI_HYBRID
},
10212 aarch64_parse_abi (const char *str
)
10216 if (str
[0] == '\0')
10218 as_bad (_("missing abi name `%s'"), str
);
10222 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10223 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10225 aarch64_abi
= aarch64_abis
[i
].value
;
10229 as_bad (_("unknown abi `%s'\n"), str
);
10233 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10235 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10236 aarch64_parse_abi
, NULL
},
10237 #endif /* OBJ_ELF */
10238 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10239 aarch64_parse_cpu
, NULL
},
10240 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10241 aarch64_parse_arch
, NULL
},
10242 {NULL
, NULL
, 0, NULL
}
10246 md_parse_option (int c
, const char *arg
)
10248 struct aarch64_option_table
*opt
;
10249 struct aarch64_long_option_table
*lopt
;
10255 target_big_endian
= 1;
10261 target_big_endian
= 0;
10266 /* Listing option. Just ignore these, we don't support additional
10271 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10273 if (c
== opt
->option
[0]
10274 && ((arg
== NULL
&& opt
->option
[1] == 0)
10275 || streq (arg
, opt
->option
+ 1)))
10277 /* If the option is deprecated, tell the user. */
10278 if (opt
->deprecated
!= NULL
)
10279 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10280 arg
? arg
: "", _(opt
->deprecated
));
10282 if (opt
->var
!= NULL
)
10283 *opt
->var
= opt
->value
;
10289 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10291 /* These options are expected to have an argument. */
10292 if (c
== lopt
->option
[0]
10294 && strncmp (arg
, lopt
->option
+ 1,
10295 strlen (lopt
->option
+ 1)) == 0)
10297 /* If the option is deprecated, tell the user. */
10298 if (lopt
->deprecated
!= NULL
)
10299 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10300 _(lopt
->deprecated
));
10302 /* Call the sup-option parser. */
10303 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10314 md_show_usage (FILE * fp
)
10316 struct aarch64_option_table
*opt
;
10317 struct aarch64_long_option_table
*lopt
;
10319 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10321 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10322 if (opt
->help
!= NULL
)
10323 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10325 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10326 if (lopt
->help
!= NULL
)
10327 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10331 -EB assemble code for a big-endian cpu\n"));
10336 -EL assemble code for a little-endian cpu\n"));
10340 /* Parse a .cpu directive. */
10343 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10345 const struct aarch64_cpu_option_table
*opt
;
10351 name
= input_line_pointer
;
10352 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10353 input_line_pointer
++;
10354 saved_char
= *input_line_pointer
;
10355 *input_line_pointer
= 0;
10357 ext
= strchr (name
, '+');
10360 optlen
= ext
- name
;
10362 optlen
= strlen (name
);
10364 /* Skip the first "all" entry. */
10365 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10366 if (strlen (opt
->name
) == optlen
10367 && strncmp (name
, opt
->name
, optlen
) == 0)
10369 mcpu_cpu_opt
= &opt
->value
;
10371 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
10374 cpu_variant
= *mcpu_cpu_opt
;
10376 *input_line_pointer
= saved_char
;
10377 demand_empty_rest_of_line ();
10380 as_bad (_("unknown cpu `%s'"), name
);
10381 *input_line_pointer
= saved_char
;
10382 ignore_rest_of_line ();
10386 /* Parse a .arch directive. */
10389 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10391 const struct aarch64_arch_option_table
*opt
;
10397 name
= input_line_pointer
;
10398 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10399 input_line_pointer
++;
10400 saved_char
= *input_line_pointer
;
10401 *input_line_pointer
= 0;
10403 ext
= strchr (name
, '+');
10406 optlen
= ext
- name
;
10408 optlen
= strlen (name
);
10410 /* Skip the first "all" entry. */
10411 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10412 if (strlen (opt
->name
) == optlen
10413 && strncmp (name
, opt
->name
, optlen
) == 0)
10415 mcpu_cpu_opt
= &opt
->value
;
10417 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
10420 cpu_variant
= *mcpu_cpu_opt
;
10422 *input_line_pointer
= saved_char
;
10423 demand_empty_rest_of_line ();
10427 as_bad (_("unknown architecture `%s'\n"), name
);
10428 *input_line_pointer
= saved_char
;
10429 ignore_rest_of_line ();
10432 /* Parse a .arch_extension directive. */
10435 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10438 char *ext
= input_line_pointer
;;
10440 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10441 input_line_pointer
++;
10442 saved_char
= *input_line_pointer
;
10443 *input_line_pointer
= 0;
10445 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
10448 cpu_variant
= *mcpu_cpu_opt
;
10450 *input_line_pointer
= saved_char
;
10451 demand_empty_rest_of_line ();
10454 /* Copy symbol information. */
10457 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10459 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10463 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10464 This is needed so AArch64 specific st_other values can be independently
10465 specified for an IFUNC resolver (that is called by the dynamic linker)
10466 and the symbol it resolves (aliased to the resolver). In particular,
10467 if a function symbol has special st_other value set via directives,
10468 then attaching an IFUNC resolver to that symbol should not override
10469 the st_other setting. Requiring the directive on the IFUNC resolver
10470 symbol would be unexpected and problematic in C code, where the two
10471 symbols appear as two independent function declarations. */
10474 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10476 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10477 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10480 if (destelf
->size
== NULL
)
10481 destelf
->size
= XNEW (expressionS
);
10482 *destelf
->size
= *srcelf
->size
;
10486 free (destelf
->size
);
10487 destelf
->size
= NULL
;
10489 S_SET_SIZE (dest
, S_GET_SIZE (src
));