1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
30 #include "cpu-aarch64.h"
33 #include "elf/aarch64.h"
34 #include "dw2gencfi.h"
37 #include "dwarf2dbg.h"
39 /* Types of processor to assemble for. */
41 #define CPU_DEFAULT AARCH64_ARCH_V8
44 #define streq(a, b) (strcmp (a, b) == 0)
46 #define END_OF_INSN '\0'
48 #define MAP_CUR_INSN (AARCH64_CPU_HAS_FEATURE (cpu_variant, \
49 AARCH64_FEATURE_C64) \
52 #define IS_C64 (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64) \
55 static aarch64_feature_set cpu_variant
;
57 /* Variables that we set while parsing command-line options. Once all
58 options have been read we re-process these values to set the real
60 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
61 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
63 /* Constants for known architecture features. */
64 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
66 /* Currently active instruction sequence. */
67 static aarch64_instr_sequence
*insn_sequence
= NULL
;
70 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
71 static symbolS
*GOT_symbol
;
73 /* Which ABI to use. */
78 AARCH64_ABI_ILP32
= 2,
79 AARCH64_ABI_PURECAP
= 3,
80 AARCH64_ABI_HYBRID
= 4,
84 #define DEFAULT_ARCH "aarch64"
87 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
88 static const char *default_arch
= DEFAULT_ARCH
;
90 /* AArch64 ABI for the output file. */
91 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
93 /* When non-zero, program to a 32-bit model, in which the C data types
94 int, long and all pointer types are 32-bit objects (ILP32); or to a
95 64-bit model, in which the C int type is 32-bits but the C long type
96 and all pointer types are 64-bit objects (LP64). */
97 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
112 /* Bits for DEFINED field in vector_type_el. */
113 #define NTA_HASTYPE 1
114 #define NTA_HASINDEX 2
115 #define NTA_HASVARWIDTH 4
117 struct vector_type_el
119 enum vector_el_type type
;
120 unsigned char defined
;
125 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
126 #define FIXUP_F_C64 0x00000002
130 bfd_reloc_code_real_type type
;
133 enum aarch64_opnd opnd
;
135 unsigned need_libopcodes_p
: 1;
138 struct aarch64_instruction
140 /* libopcodes structure for instruction intermediate representation. */
142 /* Record assembly errors found during the parsing. */
145 enum aarch64_operand_error_kind kind
;
148 /* The condition that appears in the assembly line. */
150 /* Relocation information (including the GAS internal fixup). */
152 /* Need to generate an immediate in the literal pool. */
153 unsigned gen_lit_pool
: 1;
156 typedef struct aarch64_instruction aarch64_instruction
;
158 static aarch64_instruction inst
;
160 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
161 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
164 # define now_instr_sequence seg_info \
165 (now_seg)->tc_segment_info_data.insn_sequence
167 static struct aarch64_instr_sequence now_instr_sequence
;
170 /* Diagnostics inline function utilities.
172 These are lightweight utilities which should only be called by parse_operands
173 and other parsers. GAS processes each assembly line by parsing it against
174 instruction template(s), in the case of multiple templates (for the same
175 mnemonic name), those templates are tried one by one until one succeeds or
176 all fail. An assembly line may fail a few templates before being
177 successfully parsed; an error saved here in most cases is not a user error
178 but an error indicating the current template is not the right template.
179 Therefore it is very important that errors can be saved at a low cost during
180 the parsing; we don't want to slow down the whole parsing by recording
181 non-user errors in detail.
183 Remember that the objective is to help GAS pick up the most appropriate
184 error message in the case of multiple templates, e.g. FMOV which has 8
190 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
191 inst
.parsing_error
.error
= NULL
;
194 static inline bfd_boolean
197 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
200 static inline const char *
201 get_error_message (void)
203 return inst
.parsing_error
.error
;
206 static inline enum aarch64_operand_error_kind
207 get_error_kind (void)
209 return inst
.parsing_error
.kind
;
213 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
215 inst
.parsing_error
.kind
= kind
;
216 inst
.parsing_error
.error
= error
;
220 set_recoverable_error (const char *error
)
222 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
225 /* Use the DESC field of the corresponding aarch64_operand entry to compose
226 the error message. */
228 set_default_error (void)
230 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
234 set_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_first_syntax_error (const char *error
)
243 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
247 set_fatal_syntax_error (const char *error
)
249 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
252 /* Return value for certain parsers when the parsing fails; those parsers
253 return the information of the parsed result, e.g. register number, on
255 #define PARSE_FAIL -1
257 /* This is an invalid condition code that means no conditional field is
259 #define COND_ALWAYS 0x10
263 const char *template;
270 bfd_reloc_code_real_type reloc
;
273 /* Macros to define the register types and masks for the purpose
276 #undef AARCH64_REG_TYPES
277 #define AARCH64_REG_TYPES \
278 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
279 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
280 BASIC_REG_TYPE(SP_32) /* wsp */ \
281 BASIC_REG_TYPE(SP_64) /* sp */ \
282 BASIC_REG_TYPE(Z_32) /* wzr */ \
283 BASIC_REG_TYPE(Z_64) /* xzr */ \
284 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
285 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
286 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
287 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
288 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
289 BASIC_REG_TYPE(CA_N) /* c[0-30] */ \
290 BASIC_REG_TYPE(CA_SP) /* csp */ \
291 BASIC_REG_TYPE(CA_Z) /* czr */ \
292 BASIC_REG_TYPE(CA_D) /* ddc */ \
293 BASIC_REG_TYPE(VN) /* v[0-31] */ \
294 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
295 BASIC_REG_TYPE(PN) /* p[0-15] */ \
296 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
297 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
301 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
302 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
303 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
304 /* Typecheck: same, plus SVE registers. */ \
305 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
306 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
308 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
309 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
310 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
311 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
312 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
313 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
315 /* Typecheck: any [BHSDQ]P FP. */ \
316 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
317 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
318 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
319 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
321 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
322 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
323 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
324 be used for SVE instructions, since Zn and Pn are valid symbols \
325 in other contexts. */ \
326 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
327 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
328 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
329 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
330 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
331 | REG_TYPE(ZN) | REG_TYPE(PN)) \
332 /* Any integer register; used for error messages only. */ \
333 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
334 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
335 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
336 /* Typecheck: any capability register (inc CSP) */ \
337 MULTI_REG_TYPE(CA_N_SP, REG_TYPE(CA_N) | REG_TYPE(CA_SP)) \
338 MULTI_REG_TYPE(CA_N_Z, REG_TYPE(CA_N) | REG_TYPE(CA_Z)) \
339 /* Pseudo type to mark the end of the enumerator sequence. */ \
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
344 #undef MULTI_REG_TYPE
345 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
347 /* Register type enumerators. */
348 typedef enum aarch64_reg_type_
350 /* A list of REG_TYPE_*. */
354 #undef BASIC_REG_TYPE
355 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
357 #define REG_TYPE(T) (1 << REG_TYPE_##T)
358 #undef MULTI_REG_TYPE
359 #define MULTI_REG_TYPE(T,V) V,
361 /* Structure for a hash table entry for a register. */
365 unsigned char number
;
366 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
367 unsigned char builtin
;
370 /* Values indexed by aarch64_reg_type to assist the type checking. */
371 static const unsigned reg_type_masks
[] =
376 #undef BASIC_REG_TYPE
378 #undef MULTI_REG_TYPE
379 #undef AARCH64_REG_TYPES
381 /* Diagnostics used when we don't get a register of the expected type.
382 Note: this has to synchronized with aarch64_reg_type definitions
385 get_reg_expected_msg (aarch64_reg_type reg_type
)
392 msg
= N_("integer 32-bit register expected");
395 msg
= N_("integer 64-bit register expected");
398 msg
= N_("integer register expected");
400 case REG_TYPE_R64_SP
:
401 msg
= N_("64-bit integer or SP register expected");
403 case REG_TYPE_SVE_BASE
:
404 msg
= N_("base register expected");
407 msg
= N_("integer or zero register expected");
409 case REG_TYPE_SVE_OFFSET
:
410 msg
= N_("offset register expected");
413 msg
= N_("integer or SP register expected");
415 case REG_TYPE_R_Z_SP
:
416 msg
= N_("integer, zero or SP register expected");
419 msg
= N_("8-bit SIMD scalar register expected");
422 msg
= N_("16-bit SIMD scalar or floating-point half precision "
423 "register expected");
426 msg
= N_("32-bit SIMD scalar or floating-point single precision "
427 "register expected");
430 msg
= N_("64-bit SIMD scalar or floating-point double precision "
431 "register expected");
434 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
435 "register expected");
437 case REG_TYPE_R_Z_BHSDQ_V
:
438 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
439 msg
= N_("register expected");
441 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
442 msg
= N_("SIMD scalar or floating-point register expected");
444 case REG_TYPE_VN
: /* any V reg */
445 msg
= N_("vector register expected");
448 msg
= N_("SVE vector register expected");
451 msg
= N_("SVE predicate register expected");
454 msg
= N_("Capability register C0 - C30 expected");
457 msg
= N_("Capability register CSP expected");
459 case REG_TYPE_CA_N_SP
:
460 msg
= N_("Capability register C0 - C30 or CSP expected");
463 msg
= N_("Capability register CZR expected");
466 as_fatal (_("invalid register type %d"), reg_type
);
471 /* Some well known registers that we refer to directly elsewhere. */
474 #define REG_DW_CSP (31 + 198)
475 #define REG_DW_CLR (30 + 198)
477 /* Instructions take 4 bytes in the object file. */
480 static htab_t aarch64_ops_hsh
;
481 static htab_t aarch64_cond_hsh
;
482 static htab_t aarch64_shift_hsh
;
483 static htab_t aarch64_sys_regs_hsh
;
484 static htab_t aarch64_pstatefield_hsh
;
485 static htab_t aarch64_sys_regs_ic_hsh
;
486 static htab_t aarch64_sys_regs_dc_hsh
;
487 static htab_t aarch64_sys_regs_at_hsh
;
488 static htab_t aarch64_sys_regs_tlbi_hsh
;
489 static htab_t aarch64_sys_regs_sr_hsh
;
490 static htab_t aarch64_reg_hsh
;
491 static htab_t aarch64_barrier_opt_hsh
;
492 static htab_t aarch64_nzcv_hsh
;
493 static htab_t aarch64_pldop_hsh
;
494 static htab_t aarch64_hint_opt_hsh
;
496 /* Stuff needed to resolve the label ambiguity
505 static symbolS
*last_label_seen
;
507 /* Literal pool structure. Held on a per-section
508 and per-sub-section basis. */
510 #define MAX_LITERAL_POOL_SIZE 1024
511 typedef struct literal_expression
514 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
515 LITTLENUM_TYPE
* bignum
;
516 } literal_expression
;
518 typedef struct literal_pool
520 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
521 unsigned int next_free_entry
;
527 struct literal_pool
*next
;
530 /* Pointer to a linked list of literal pools. */
531 static literal_pool
*list_of_pools
= NULL
;
535 /* This array holds the chars that always start a comment. If the
536 pre-processor is disabled, these aren't very useful. */
537 const char comment_chars
[] = "";
539 /* This array holds the chars that only start a comment at the beginning of
540 a line. If the line seems to have the form '# 123 filename'
541 .line and .file directives will appear in the pre-processed output. */
542 /* Note that input_file.c hand checks for '#' at the beginning of the
543 first line of the input file. This is because the compiler outputs
544 #NO_APP at the beginning of its output. */
545 /* Also note that comments like this one will always work. */
546 const char line_comment_chars
[] = "#";
548 const char line_separator_chars
[] = ";";
550 /* Chars that can be used to separate mant
551 from exp in floating point numbers. */
552 const char EXP_CHARS
[] = "eE";
554 /* Chars that mean this number is a floating point constant. */
558 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
560 /* Prefix character that indicates the start of an immediate value. */
561 #define is_immediate_prefix(C) ((C) == '#')
563 /* Separator character handling. */
565 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
567 static inline bfd_boolean
568 skip_past_char (char **str
, char c
)
579 #define skip_past_comma(str) skip_past_char (str, ',')
581 /* Arithmetic expressions (possibly involving symbols). */
583 static bfd_boolean in_my_get_expression_p
= FALSE
;
585 /* Third argument to my_get_expression. */
586 #define GE_NO_PREFIX 0
587 #define GE_OPT_PREFIX 1
589 /* Return TRUE if the string pointed by *STR is successfully parsed
590 as an valid expression; *EP will be filled with the information of
591 such an expression. Otherwise return FALSE. */
594 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
599 int prefix_present_p
= 0;
606 if (is_immediate_prefix (**str
))
609 prefix_present_p
= 1;
616 memset (ep
, 0, sizeof (expressionS
));
618 save_in
= input_line_pointer
;
619 input_line_pointer
= *str
;
620 in_my_get_expression_p
= TRUE
;
621 seg
= expression (ep
);
622 in_my_get_expression_p
= FALSE
;
624 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
626 /* We found a bad expression in md_operand(). */
627 *str
= input_line_pointer
;
628 input_line_pointer
= save_in
;
629 if (prefix_present_p
&& ! error_p ())
630 set_fatal_syntax_error (_("bad expression"));
632 set_first_syntax_error (_("bad expression"));
637 if (seg
!= absolute_section
638 && seg
!= text_section
639 && seg
!= data_section
640 && seg
!= bss_section
&& seg
!= undefined_section
)
642 set_syntax_error (_("bad segment"));
643 *str
= input_line_pointer
;
644 input_line_pointer
= save_in
;
651 *str
= input_line_pointer
;
652 input_line_pointer
= save_in
;
656 /* Turn a string in input_line_pointer into a floating point constant
657 of type TYPE, and store the appropriate bytes in *LITP. The number
658 of LITTLENUMS emitted is stored in *SIZEP. An error message is
659 returned, or NULL on OK. */
662 md_atof (int type
, char *litP
, int *sizeP
)
664 /* If this is a bfloat16 type, then parse it slightly differently -
665 as it does not follow the IEEE standard exactly. */
669 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
670 FLONUM_TYPE generic_float
;
672 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
675 input_line_pointer
= t
;
677 return _("invalid floating point number");
679 switch (generic_float
.sign
)
692 /* bfloat16 has two types of NaN - quiet and signalling.
693 Quiet NaN has bit[6] == 1 && faction != 0, whereas
694 signalling Nan's have bit[0] == 0 && fraction != 0.
695 Chose this specific encoding as it is the same form
696 as used by other IEEE 754 encodings in GAS. */
707 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
712 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
715 /* We handle all bad expressions here, so that we can report the faulty
716 instruction in the error message. */
718 md_operand (expressionS
* exp
)
720 if (in_my_get_expression_p
)
721 exp
->X_op
= O_illegal
;
724 /* Immediate values. */
726 /* Errors may be set multiple times during parsing or bit encoding
727 (particularly in the Neon bits), but usually the earliest error which is set
728 will be the most meaningful. Avoid overwriting it with later (cascading)
729 errors by calling this function. */
732 first_error (const char *error
)
735 set_syntax_error (error
);
738 /* Similar to first_error, but this function accepts formatted error
741 first_error_fmt (const char *format
, ...)
746 /* N.B. this single buffer will not cause error messages for different
747 instructions to pollute each other; this is because at the end of
748 processing of each assembly line, error message if any will be
749 collected by as_bad. */
750 static char buffer
[size
];
754 int ret ATTRIBUTE_UNUSED
;
755 va_start (args
, format
);
756 ret
= vsnprintf (buffer
, size
, format
, args
);
757 know (ret
<= size
- 1 && ret
>= 0);
759 set_syntax_error (buffer
);
763 /* Register parsing. */
765 /* Generic register parser which is called by other specialized
767 CCP points to what should be the beginning of a register name.
768 If it is indeed a valid register name, advance CCP over it and
769 return the reg_entry structure; otherwise return NULL.
770 It does not issue diagnostics. */
773 parse_reg (char **ccp
)
779 #ifdef REGISTER_PREFIX
780 if (*start
!= REGISTER_PREFIX
)
786 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
791 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
793 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
802 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
805 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
807 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
810 /* Try to parse a base or offset register. Allow SVE base and offset
811 registers if REG_TYPE includes SVE registers. Return the register
812 entry on success, setting *QUALIFIER to the register qualifier.
813 Return null otherwise.
815 Note that this function does not issue any diagnostics. */
817 static const reg_entry
*
818 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
819 aarch64_opnd_qualifier_t
*qualifier
)
822 const reg_entry
*reg
= parse_reg (&str
);
832 *qualifier
= AARCH64_OPND_QLF_W
;
838 *qualifier
= AARCH64_OPND_QLF_X
;
842 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
845 switch (TOLOWER (str
[1]))
848 *qualifier
= AARCH64_OPND_QLF_S_S
;
851 *qualifier
= AARCH64_OPND_QLF_S_D
;
861 *qualifier
= AARCH64_OPND_QLF_CA
;
873 /* Try to parse a base or offset register. Return the register entry
874 on success, setting *QUALIFIER to the register qualifier. Return null
877 Note that this function does not issue any diagnostics. */
879 static const reg_entry
*
880 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
882 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
885 /* Parse the qualifier of a vector register or vector element of type
886 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
887 succeeds; otherwise return FALSE.
889 Accept only one occurrence of:
890 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
893 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
894 struct vector_type_el
*parsed_type
, char **str
)
898 unsigned element_size
;
899 enum vector_el_type type
;
902 gas_assert (*ptr
== '.');
905 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
910 width
= strtoul (ptr
, &ptr
, 10);
911 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
913 first_error_fmt (_("bad size %d in vector width specifier"), width
);
918 switch (TOLOWER (*ptr
))
937 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
946 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
948 first_error (_("missing element size"));
951 if (width
!= 0 && width
* element_size
!= 64
952 && width
* element_size
!= 128
953 && !(width
== 2 && element_size
== 16)
954 && !(width
== 4 && element_size
== 8))
957 ("invalid element size %d and vector size combination %c"),
963 parsed_type
->type
= type
;
964 parsed_type
->width
= width
;
971 /* *STR contains an SVE zero/merge predication suffix. Parse it into
972 *PARSED_TYPE and point *STR at the end of the suffix. */
975 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
980 gas_assert (*ptr
== '/');
982 switch (TOLOWER (*ptr
))
985 parsed_type
->type
= NT_zero
;
988 parsed_type
->type
= NT_merge
;
991 if (*ptr
!= '\0' && *ptr
!= ',')
992 first_error_fmt (_("unexpected character `%c' in predication type"),
995 first_error (_("missing predication type"));
998 parsed_type
->width
= 0;
1003 /* Parse a register of the type TYPE.
1005 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
1006 name or the parsed register is not of TYPE.
1008 Otherwise return the register number, and optionally fill in the actual
1009 type of the register in *RTYPE when multiple alternatives were given, and
1010 return the register shape and element index information in *TYPEINFO.
1012 IN_REG_LIST should be set with TRUE if the caller is parsing a register
1016 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
1017 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
1020 const reg_entry
*reg
= parse_reg (&str
);
1021 struct vector_type_el atype
;
1022 struct vector_type_el parsetype
;
1023 bfd_boolean is_typed_vecreg
= FALSE
;
1026 atype
.type
= NT_invtype
;
1034 set_default_error ();
1038 if (! aarch64_check_reg_type (reg
, type
))
1040 DEBUG_TRACE ("reg type check failed");
1041 set_default_error ();
1046 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1047 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1051 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1056 if (!parse_predication_for_operand (&parsetype
, &str
))
1060 /* Register if of the form Vn.[bhsdq]. */
1061 is_typed_vecreg
= TRUE
;
1063 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1065 /* The width is always variable; we don't allow an integer width
1067 gas_assert (parsetype
.width
== 0);
1068 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1070 else if (parsetype
.width
== 0)
1071 /* Expect index. In the new scheme we cannot have
1072 Vn.[bhsdq] represent a scalar. Therefore any
1073 Vn.[bhsdq] should have an index following it.
1074 Except in reglists of course. */
1075 atype
.defined
|= NTA_HASINDEX
;
1077 atype
.defined
|= NTA_HASTYPE
;
1079 atype
.type
= parsetype
.type
;
1080 atype
.width
= parsetype
.width
;
1083 if (skip_past_char (&str
, '['))
1087 /* Reject Sn[index] syntax. */
1088 if (!is_typed_vecreg
)
1090 first_error (_("this type of register can't be indexed"));
1096 first_error (_("index not allowed inside register list"));
1100 atype
.defined
|= NTA_HASINDEX
;
1102 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1104 if (exp
.X_op
!= O_constant
)
1106 first_error (_("constant expression required"));
1110 if (! skip_past_char (&str
, ']'))
1113 atype
.index
= exp
.X_add_number
;
1115 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1117 /* Indexed vector register expected. */
1118 first_error (_("indexed vector register expected"));
1122 /* A vector reg Vn should be typed or indexed. */
1123 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1125 first_error (_("invalid use of vector register"));
1141 Return the register number on success; return PARSE_FAIL otherwise.
1143 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1144 the register (e.g. NEON double or quad reg when either has been requested).
1146 If this is a NEON vector register with additional type information, fill
1147 in the struct pointed to by VECTYPE (if non-NULL).
1149 This parser does not handle register list. */
1152 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1153 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1155 struct vector_type_el atype
;
1157 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1158 /*in_reg_list= */ FALSE
);
1160 if (reg
== PARSE_FAIL
)
1171 static inline bfd_boolean
1172 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1176 && e1
.defined
== e2
.defined
1177 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1180 /* This function parses a list of vector registers of type TYPE.
1181 On success, it returns the parsed register list information in the
1182 following encoded format:
1184 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1185 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1187 The information of the register shape and/or index is returned in
1190 It returns PARSE_FAIL if the register list is invalid.
1192 The list contains one to four registers.
1193 Each register can be one of:
1196 All <T> should be identical.
1197 All <index> should be identical.
1198 There are restrictions on <Vt> numbers which are checked later
1199 (by reg_list_valid_p). */
1202 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1203 struct vector_type_el
*vectype
)
1207 struct vector_type_el typeinfo
, typeinfo_first
;
1212 bfd_boolean error
= FALSE
;
1213 bfd_boolean expect_index
= FALSE
;
1217 set_syntax_error (_("expecting {"));
1223 typeinfo_first
.defined
= 0;
1224 typeinfo_first
.type
= NT_invtype
;
1225 typeinfo_first
.width
= -1;
1226 typeinfo_first
.index
= 0;
1235 str
++; /* skip over '-' */
1238 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1239 /*in_reg_list= */ TRUE
);
1240 if (val
== PARSE_FAIL
)
1242 set_first_syntax_error (_("invalid vector register in list"));
1246 /* reject [bhsd]n */
1247 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1249 set_first_syntax_error (_("invalid scalar register in list"));
1254 if (typeinfo
.defined
& NTA_HASINDEX
)
1255 expect_index
= TRUE
;
1259 if (val
< val_range
)
1261 set_first_syntax_error
1262 (_("invalid range in vector register list"));
1271 typeinfo_first
= typeinfo
;
1272 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1274 set_first_syntax_error
1275 (_("type mismatch in vector register list"));
1280 for (i
= val_range
; i
<= val
; i
++)
1282 ret_val
|= i
<< (5 * nb_regs
);
1287 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1289 skip_whitespace (str
);
1292 set_first_syntax_error (_("end of vector register list not found"));
1297 skip_whitespace (str
);
1301 if (skip_past_char (&str
, '['))
1305 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1306 if (exp
.X_op
!= O_constant
)
1308 set_first_syntax_error (_("constant expression required."));
1311 if (! skip_past_char (&str
, ']'))
1314 typeinfo_first
.index
= exp
.X_add_number
;
1318 set_first_syntax_error (_("expected index"));
1325 set_first_syntax_error (_("too many registers in vector register list"));
1328 else if (nb_regs
== 0)
1330 set_first_syntax_error (_("empty vector register list"));
1336 *vectype
= typeinfo_first
;
1338 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1341 /* Directives: register aliases. */
1344 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1349 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1352 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1355 /* Only warn about a redefinition if it's not defined as the
1357 else if (new->number
!= number
|| new->type
!= type
)
1358 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1363 name
= xstrdup (str
);
1364 new = XNEW (reg_entry
);
1367 new->number
= number
;
1369 new->builtin
= FALSE
;
1371 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1376 /* Look for the .req directive. This is of the form:
1378 new_register_name .req existing_register_name
1380 If we find one, or if it looks sufficiently like one that we want to
1381 handle any error here, return TRUE. Otherwise return FALSE. */
1384 create_register_alias (char *newname
, char *p
)
1386 const reg_entry
*old
;
1387 char *oldname
, *nbuf
;
1390 /* The input scrubber ensures that whitespace after the mnemonic is
1391 collapsed to single spaces. */
1393 if (strncmp (oldname
, " .req ", 6) != 0)
1397 if (*oldname
== '\0')
1400 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1403 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1407 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1408 the desired alias name, and p points to its end. If not, then
1409 the desired alias name is in the global original_case_string. */
1410 #ifdef TC_CASE_SENSITIVE
1413 newname
= original_case_string
;
1414 nlen
= strlen (newname
);
1417 nbuf
= xmemdup0 (newname
, nlen
);
1419 /* Create aliases under the new name as stated; an all-lowercase
1420 version of the new name; and an all-uppercase version of the new
1422 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1424 for (p
= nbuf
; *p
; p
++)
1427 if (strncmp (nbuf
, newname
, nlen
))
1429 /* If this attempt to create an additional alias fails, do not bother
1430 trying to create the all-lower case alias. We will fail and issue
1431 a second, duplicate error message. This situation arises when the
1432 programmer does something like:
1435 The second .req creates the "Foo" alias but then fails to create
1436 the artificial FOO alias because it has already been created by the
1438 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1445 for (p
= nbuf
; *p
; p
++)
1448 if (strncmp (nbuf
, newname
, nlen
))
1449 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1456 /* Should never be called, as .req goes between the alias and the
1457 register name, not at the beginning of the line. */
1459 s_req (int a ATTRIBUTE_UNUSED
)
1461 as_bad (_("invalid syntax for .req directive"));
1464 /* The .unreq directive deletes an alias which was previously defined
1465 by .req. For example:
1471 s_unreq (int a ATTRIBUTE_UNUSED
)
1476 name
= input_line_pointer
;
1478 while (*input_line_pointer
!= 0
1479 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1480 ++input_line_pointer
;
1482 saved_char
= *input_line_pointer
;
1483 *input_line_pointer
= 0;
1486 as_bad (_("invalid syntax for .unreq directive"));
1489 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1492 as_bad (_("unknown register alias '%s'"), name
);
1493 else if (reg
->builtin
)
1494 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1501 str_hash_delete (aarch64_reg_hsh
, name
);
1502 free ((char *) reg
->name
);
1505 /* Also locate the all upper case and all lower case versions.
1506 Do not complain if we cannot find one or the other as it
1507 was probably deleted above. */
1509 nbuf
= strdup (name
);
1510 for (p
= nbuf
; *p
; p
++)
1512 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1515 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1516 free ((char *) reg
->name
);
1520 for (p
= nbuf
; *p
; p
++)
1522 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1525 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1526 free ((char *) reg
->name
);
1534 *input_line_pointer
= saved_char
;
1535 demand_empty_rest_of_line ();
1538 /* Directives: Instruction set selection. */
1541 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1542 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1543 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1544 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1546 /* Create a new mapping symbol for the transition to STATE. */
1549 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1552 const char *symname
;
1559 type
= BSF_NO_FLAGS
;
1563 type
= BSF_NO_FLAGS
;
1567 type
= BSF_NO_FLAGS
;
1573 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1574 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1576 if (state
== MAP_C64
)
1577 AARCH64_SET_C64 (symbolP
, 1);
1578 else if (state
== MAP_INSN
)
1579 AARCH64_SET_C64 (symbolP
, 0);
1581 /* Save the mapping symbols for future reference. Also check that
1582 we do not place two mapping symbols at the same offset within a
1583 frag. We'll handle overlap between frags in
1584 check_mapping_symbols.
1586 If .fill or other data filling directive generates zero sized data,
1587 the mapping symbol for the following code will have the same value
1588 as the one generated for the data filling directive. In this case,
1589 we replace the old symbol with the new one at the same address. */
1592 if (frag
->tc_frag_data
.first_map
!= NULL
)
1594 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1595 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1598 frag
->tc_frag_data
.first_map
= symbolP
;
1600 if (frag
->tc_frag_data
.last_map
!= NULL
)
1602 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1603 S_GET_VALUE (symbolP
));
1604 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1605 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1608 frag
->tc_frag_data
.last_map
= symbolP
;
1611 /* We must sometimes convert a region marked as code to data during
1612 code alignment, if an odd number of bytes have to be padded. The
1613 code mapping symbol is pushed to an aligned address. */
1616 insert_data_mapping_symbol (enum mstate state
,
1617 valueT value
, fragS
* frag
, offsetT bytes
)
1619 /* If there was already a mapping symbol, remove it. */
1620 if (frag
->tc_frag_data
.last_map
!= NULL
1621 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1622 frag
->fr_address
+ value
)
1624 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1628 know (frag
->tc_frag_data
.first_map
== symp
);
1629 frag
->tc_frag_data
.first_map
= NULL
;
1631 frag
->tc_frag_data
.last_map
= NULL
;
1632 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1635 make_mapping_symbol (MAP_DATA
, value
, frag
);
1636 make_mapping_symbol (state
, value
+ bytes
, frag
);
1639 static void mapping_state_2 (enum mstate state
, int max_chars
);
1641 /* Set the mapping state to STATE. Only call this when about to
1642 emit some STATE bytes to the file. */
1645 mapping_state (enum mstate state
)
1647 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1649 if (state
== MAP_CUR_INSN
)
1650 /* AArch64 instructions require 4-byte alignment. When emitting
1651 instructions into any section, record the appropriate section
1653 record_alignment (now_seg
, 2);
1655 if (mapstate
== state
)
1656 /* The mapping symbol has already been emitted.
1657 There is nothing else to do. */
1660 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1661 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1662 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1663 evaluated later in the next else. */
1665 else if (TRANSITION (MAP_UNDEFINED
, MAP_CUR_INSN
))
1667 /* Only add the symbol if the offset is > 0:
1668 if we're at the first frag, check it's size > 0;
1669 if we're not at the first frag, then for sure
1670 the offset is > 0. */
1671 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1672 const int add_symbol
= (frag_now
!= frag_first
)
1673 || (frag_now_fix () > 0);
1676 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1680 mapping_state_2 (state
, 0);
1683 /* Same as mapping_state, but MAX_CHARS bytes have already been
1684 allocated. Put the mapping symbol that far back. */
1687 mapping_state_2 (enum mstate state
, int max_chars
)
1689 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1691 if (!SEG_NORMAL (now_seg
))
1694 if (mapstate
== state
)
1695 /* The mapping symbol has already been emitted.
1696 There is nothing else to do. */
1699 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1700 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1703 #define mapping_state(x) /* nothing */
1704 #define mapping_state_2(x, y) /* nothing */
1707 /* Directives: sectioning and alignment. */
1710 s_bss (int ignore ATTRIBUTE_UNUSED
)
1712 /* We don't support putting frags in the BSS segment, we fake it by
1713 marking in_bss, then looking at s_skip for clues. */
1714 subseg_set (bss_section
, 0);
1715 demand_empty_rest_of_line ();
1716 mapping_state (MAP_DATA
);
1720 s_even (int ignore ATTRIBUTE_UNUSED
)
1722 /* Never make frag if expect extra pass. */
1724 frag_align (1, 0, 0);
1726 record_alignment (now_seg
, 1);
1728 demand_empty_rest_of_line ();
1731 /* Directives: Literal pools. */
1733 static literal_pool
*
1734 find_literal_pool (int size
)
1738 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1740 if (pool
->section
== now_seg
1741 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1748 static literal_pool
*
1749 find_or_make_literal_pool (int size
)
1751 /* Next literal pool ID number. */
1752 static unsigned int latest_pool_num
= 1;
1755 pool
= find_literal_pool (size
);
1759 /* Create a new pool. */
1760 pool
= XNEW (literal_pool
);
1764 /* Currently we always put the literal pool in the current text
1765 section. If we were generating "small" model code where we
1766 knew that all code and initialised data was within 1MB then
1767 we could output literals to mergeable, read-only data
1770 pool
->next_free_entry
= 0;
1771 pool
->section
= now_seg
;
1772 pool
->sub_section
= now_subseg
;
1774 pool
->next
= list_of_pools
;
1775 pool
->symbol
= NULL
;
1777 /* Add it to the list. */
1778 list_of_pools
= pool
;
1781 /* New pools, and emptied pools, will have a NULL symbol. */
1782 if (pool
->symbol
== NULL
)
1784 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1785 &zero_address_frag
, 0);
1786 pool
->id
= latest_pool_num
++;
1793 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1794 Return TRUE on success, otherwise return FALSE. */
1796 add_to_lit_pool (expressionS
*exp
, int size
)
1801 pool
= find_or_make_literal_pool (size
);
1803 /* Check if this literal value is already in the pool. */
1804 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1806 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1808 if ((litexp
->X_op
== exp
->X_op
)
1809 && (exp
->X_op
== O_constant
)
1810 && (litexp
->X_add_number
== exp
->X_add_number
)
1811 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1814 if ((litexp
->X_op
== exp
->X_op
)
1815 && (exp
->X_op
== O_symbol
)
1816 && (litexp
->X_add_number
== exp
->X_add_number
)
1817 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1818 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1822 /* Do we need to create a new entry? */
1823 if (entry
== pool
->next_free_entry
)
1825 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1827 set_syntax_error (_("literal pool overflow"));
1831 pool
->literals
[entry
].exp
= *exp
;
1832 pool
->next_free_entry
+= 1;
1833 if (exp
->X_op
== O_big
)
1835 /* PR 16688: Bignums are held in a single global array. We must
1836 copy and preserve that value now, before it is overwritten. */
1837 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1839 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1840 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1843 pool
->literals
[entry
].bignum
= NULL
;
1846 exp
->X_op
= O_symbol
;
1847 exp
->X_add_number
= ((int) entry
) * size
;
1848 exp
->X_add_symbol
= pool
->symbol
;
1853 /* Can't use symbol_new here, so have to create a symbol and then at
1854 a later date assign it a value. That's what these functions do. */
1857 symbol_locate (symbolS
* symbolP
,
1858 const char *name
,/* It is copied, the caller can modify. */
1859 segT segment
, /* Segment identifier (SEG_<something>). */
1860 valueT valu
, /* Symbol value. */
1861 fragS
* frag
) /* Associated fragment. */
1864 char *preserved_copy_of_name
;
1866 name_length
= strlen (name
) + 1; /* +1 for \0. */
1867 obstack_grow (¬es
, name
, name_length
);
1868 preserved_copy_of_name
= obstack_finish (¬es
);
1870 #ifdef tc_canonicalize_symbol_name
1871 preserved_copy_of_name
=
1872 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1875 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1877 S_SET_SEGMENT (symbolP
, segment
);
1878 S_SET_VALUE (symbolP
, valu
);
1879 symbol_clear_list_pointers (symbolP
);
1881 symbol_set_frag (symbolP
, frag
);
1883 /* Link to end of symbol chain. */
1885 extern int symbol_table_frozen
;
1887 if (symbol_table_frozen
)
1891 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1893 obj_symbol_new_hook (symbolP
);
1895 #ifdef tc_symbol_new_hook
1896 tc_symbol_new_hook (symbolP
);
1900 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1901 #endif /* DEBUG_SYMS */
1906 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1913 for (align
= 2; align
<= 4; align
++)
1915 int size
= 1 << align
;
1917 pool
= find_literal_pool (size
);
1918 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1921 /* Align pool as you have word accesses.
1922 Only make a frag if we have to. */
1924 frag_align (align
, 0, 0);
1926 mapping_state (MAP_DATA
);
1928 record_alignment (now_seg
, align
);
1930 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1932 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1933 (valueT
) frag_now_fix (), frag_now
);
1934 symbol_table_insert (pool
->symbol
);
1936 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1938 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1940 if (exp
->X_op
== O_big
)
1942 /* PR 16688: Restore the global bignum value. */
1943 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1944 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1945 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1948 /* First output the expression in the instruction to the pool. */
1949 emit_expr (exp
, size
); /* .word|.xword */
1951 if (exp
->X_op
== O_big
)
1953 free (pool
->literals
[entry
].bignum
);
1954 pool
->literals
[entry
].bignum
= NULL
;
1958 /* Mark the pool as empty. */
1959 pool
->next_free_entry
= 0;
1960 pool
->symbol
= NULL
;
1965 /* Forward declarations for functions below, in the MD interface
1967 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1968 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1970 /* Directives: Data. */
1971 /* N.B. the support for relocation suffix in this directive needs to be
1972 implemented properly. */
1975 s_aarch64_elf_cons (int nbytes
)
1979 #ifdef md_flush_pending_output
1980 md_flush_pending_output ();
1983 if (is_it_end_of_statement ())
1985 demand_empty_rest_of_line ();
1989 #ifdef md_cons_align
1990 md_cons_align (nbytes
);
1993 mapping_state (MAP_DATA
);
1996 struct reloc_table_entry
*reloc
;
2000 if (exp
.X_op
!= O_symbol
)
2001 emit_expr (&exp
, (unsigned int) nbytes
);
2004 skip_past_char (&input_line_pointer
, '#');
2005 if (skip_past_char (&input_line_pointer
, ':'))
2007 reloc
= find_reloc_table_entry (&input_line_pointer
);
2009 as_bad (_("unrecognized relocation suffix"));
2011 as_bad (_("unimplemented relocation suffix"));
2012 ignore_rest_of_line ();
2016 emit_expr (&exp
, (unsigned int) nbytes
);
2019 while (*input_line_pointer
++ == ',');
2021 /* Put terminator back into stream. */
2022 input_line_pointer
--;
2023 demand_empty_rest_of_line ();
2026 /* Mark symbol that it follows a variant PCS convention. */
2029 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2035 elf_symbol_type
*elfsym
;
2037 c
= get_symbol_name (&name
);
2039 as_bad (_("Missing symbol name in directive"));
2040 sym
= symbol_find_or_make (name
);
2041 restore_line_pointer (c
);
2042 demand_empty_rest_of_line ();
2043 bfdsym
= symbol_get_bfdsym (sym
);
2044 elfsym
= elf_symbol_from (bfdsym
);
2045 gas_assert (elfsym
);
2046 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2048 #endif /* OBJ_ELF */
2050 /* Output a 32-bit word, but mark as an instruction. */
2053 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2057 #ifdef md_flush_pending_output
2058 md_flush_pending_output ();
2061 if (is_it_end_of_statement ())
2063 demand_empty_rest_of_line ();
2067 /* Sections are assumed to start aligned. In executable section, there is no
2068 MAP_DATA symbol pending. So we only align the address during
2069 MAP_DATA --> MAP_CUR_INSN transition.
2070 For other sections, this is not guaranteed. */
2071 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2072 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2073 frag_align_code (2, 0);
2076 mapping_state (MAP_CUR_INSN
);
2082 if (exp
.X_op
!= O_constant
)
2084 as_bad (_("constant expression required"));
2085 ignore_rest_of_line ();
2089 if (target_big_endian
)
2091 unsigned int val
= exp
.X_add_number
;
2092 exp
.X_add_number
= SWAP_32 (val
);
2094 emit_expr (&exp
, 4);
2096 while (*input_line_pointer
++ == ',');
2098 /* Put terminator back into stream. */
2099 input_line_pointer
--;
2100 demand_empty_rest_of_line ();
2104 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2106 demand_empty_rest_of_line ();
2107 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2108 fde
->entry_extras
.pauth_key
= AARCH64_PAUTH_KEY_B
;
2112 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2115 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2121 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2122 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2124 demand_empty_rest_of_line ();
2127 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2130 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2134 /* Since we're just labelling the code, there's no need to define a
2137 /* Make sure there is enough room in this frag for the following
2138 blr. This trick only works if the blr follows immediately after
2139 the .tlsdesc directive. */
2141 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2142 (IS_C64
? BFD_RELOC_MORELLO_TLSDESC_CALL
2143 : BFD_RELOC_AARCH64_TLSDESC_CALL
));
2145 demand_empty_rest_of_line ();
2148 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2151 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2157 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2158 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2160 demand_empty_rest_of_line ();
2164 s_aarch64_capinit (int ignored ATTRIBUTE_UNUSED
)
2169 /* align to 16 bytes. */
2170 do_align (4, (char *) NULL
, 0, 0);
2173 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 16, &exp
, 0,
2174 BFD_RELOC_MORELLO_CAPINIT
);
2176 demand_empty_rest_of_line ();
2180 s_aarch64_chericap (int ignored ATTRIBUTE_UNUSED
)
2185 #ifdef md_flush_pending_output
2186 md_flush_pending_output ();
2189 /* align to 16 bytes. */
2190 do_align (4, (char *) NULL
, 0, 0);
2193 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 16, &exp
, 0,
2194 BFD_RELOC_MORELLO_CAPINIT
);
2196 mapping_state (MAP_DATA
);
2198 for (i
= 0; i
< 4; i
++)
2200 /* The documentation of our md_number_to_chars says the greatest value
2201 size it can handle is 4 bytes. */
2202 char *p
= frag_more (4);
2203 md_number_to_chars (p
, 0, 4);
2205 demand_empty_rest_of_line ();
2207 #endif /* OBJ_ELF */
2209 static void s_aarch64_arch (int);
2210 static void s_aarch64_cpu (int);
2211 static void s_aarch64_arch_extension (int);
2213 /* This table describes all the machine specific pseudo-ops the assembler
2214 has to support. The fields are:
2215 pseudo-op name without dot
2216 function to call to execute this pseudo-op
2217 Integer arg to pass to the function. */
2219 const pseudo_typeS md_pseudo_table
[] = {
2220 /* Never called because '.req' does not start a line. */
2222 {"unreq", s_unreq
, 0},
2224 {"even", s_even
, 0},
2225 {"ltorg", s_ltorg
, 0},
2226 {"pool", s_ltorg
, 0},
2227 {"cpu", s_aarch64_cpu
, 0},
2228 {"arch", s_aarch64_arch
, 0},
2229 {"arch_extension", s_aarch64_arch_extension
, 0},
2230 {"inst", s_aarch64_inst
, 0},
2231 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2233 {"tlsdescadd", s_tlsdescadd
, 0},
2234 {"tlsdesccall", s_tlsdesccall
, 0},
2235 {"tlsdescldr", s_tlsdescldr
, 0},
2236 {"word", s_aarch64_elf_cons
, 4},
2237 {"long", s_aarch64_elf_cons
, 4},
2238 {"xword", s_aarch64_elf_cons
, 8},
2239 {"dword", s_aarch64_elf_cons
, 8},
2240 {"variant_pcs", s_variant_pcs
, 0},
2241 {"capinit", s_aarch64_capinit
, 0},
2242 {"chericap", s_aarch64_chericap
, 0},
2244 {"float16", float_cons
, 'h'},
2245 {"bfloat16", float_cons
, 'b'},
2250 /* Check whether STR points to a register name followed by a comma or the
2251 end of line; REG_TYPE indicates which register types are checked
2252 against. Return TRUE if STR is such a register name; otherwise return
2253 FALSE. The function does not intend to produce any diagnostics, but since
2254 the register parser aarch64_reg_parse, which is called by this function,
2255 does produce diagnostics, we call clear_error to clear any diagnostics
2256 that may be generated by aarch64_reg_parse.
2257 Also, the function returns FALSE directly if there is any user error
2258 present at the function entry. This prevents the existing diagnostics
2259 state from being spoiled.
2260 The function currently serves parse_constant_immediate and
2261 parse_big_immediate only. */
2263 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2267 /* Prevent the diagnostics state from being spoiled. */
2271 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2273 /* Clear the parsing error that may be set by the reg parser. */
2276 if (reg
== PARSE_FAIL
)
2279 skip_whitespace (str
);
2280 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2286 /* Parser functions used exclusively in instruction operands. */
2288 /* Parse an immediate expression which may not be constant.
2290 To prevent the expression parser from pushing a register name
2291 into the symbol table as an undefined symbol, firstly a check is
2292 done to find out whether STR is a register of type REG_TYPE followed
2293 by a comma or the end of line. Return FALSE if STR is such a string. */
2296 parse_immediate_expression (char **str
, expressionS
*exp
,
2297 aarch64_reg_type reg_type
)
2299 if (reg_name_p (*str
, reg_type
))
2301 set_recoverable_error (_("immediate operand required"));
2305 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2307 if (exp
->X_op
== O_absent
)
2309 set_fatal_syntax_error (_("missing immediate expression"));
2316 /* Constant immediate-value read function for use in insn parsing.
2317 STR points to the beginning of the immediate (with the optional
2318 leading #); *VAL receives the value. REG_TYPE says which register
2319 names should be treated as registers rather than as symbolic immediates.
2321 Return TRUE on success; otherwise return FALSE. */
2324 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2328 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2331 if (exp
.X_op
!= O_constant
)
2333 set_syntax_error (_("constant expression required"));
2337 *val
= exp
.X_add_number
;
2342 encode_imm_float_bits (uint32_t imm
)
2344 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2345 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2348 /* Return TRUE if the single-precision floating-point value encoded in IMM
2349 can be expressed in the AArch64 8-bit signed floating-point format with
2350 3-bit exponent and normalized 4 bits of precision; in other words, the
2351 floating-point value must be expressable as
2352 (+/-) n / 16 * power (2, r)
2353 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2356 aarch64_imm_float_p (uint32_t imm
)
2358 /* If a single-precision floating-point value has the following bit
2359 pattern, it can be expressed in the AArch64 8-bit floating-point
2362 3 32222222 2221111111111
2363 1 09876543 21098765432109876543210
2364 n Eeeeeexx xxxx0000000000000000000
2366 where n, e and each x are either 0 or 1 independently, with
2371 /* Prepare the pattern for 'Eeeeee'. */
2372 if (((imm
>> 30) & 0x1) == 0)
2373 pattern
= 0x3e000000;
2375 pattern
= 0x40000000;
2377 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2378 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2381 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2382 as an IEEE float without any loss of precision. Store the value in
2386 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2388 /* If a double-precision floating-point value has the following bit
2389 pattern, it can be expressed in a float:
2391 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2392 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2393 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2395 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2396 if Eeee_eeee != 1111_1111
2398 where n, e, s and S are either 0 or 1 independently and where ~ is the
2402 uint32_t high32
= imm
>> 32;
2403 uint32_t low32
= imm
;
2405 /* Lower 29 bits need to be 0s. */
2406 if ((imm
& 0x1fffffff) != 0)
2409 /* Prepare the pattern for 'Eeeeeeeee'. */
2410 if (((high32
>> 30) & 0x1) == 0)
2411 pattern
= 0x38000000;
2413 pattern
= 0x40000000;
2416 if ((high32
& 0x78000000) != pattern
)
2419 /* Check Eeee_eeee != 1111_1111. */
2420 if ((high32
& 0x7ff00000) == 0x47f00000)
2423 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2424 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2425 | (low32
>> 29)); /* 3 S bits. */
2429 /* Return true if we should treat OPERAND as a double-precision
2430 floating-point operand rather than a single-precision one. */
2432 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2434 /* Check for unsuffixed SVE registers, which are allowed
2435 for LDR and STR but not in instructions that require an
2436 immediate. We get better error messages if we arbitrarily
2437 pick one size, parse the immediate normally, and then
2438 report the match failure in the normal way. */
2439 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2440 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2443 /* Parse a floating-point immediate. Return TRUE on success and return the
2444 value in *IMMED in the format of IEEE754 single-precision encoding.
2445 *CCP points to the start of the string; DP_P is TRUE when the immediate
2446 is expected to be in double-precision (N.B. this only matters when
2447 hexadecimal representation is involved). REG_TYPE says which register
2448 names should be treated as registers rather than as symbolic immediates.
2450 This routine accepts any IEEE float; it is up to the callers to reject
2454 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2455 aarch64_reg_type reg_type
)
2459 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2461 unsigned fpword
= 0;
2462 bfd_boolean hex_p
= FALSE
;
2464 skip_past_char (&str
, '#');
2467 skip_whitespace (fpnum
);
2469 if (strncmp (fpnum
, "0x", 2) == 0)
2471 /* Support the hexadecimal representation of the IEEE754 encoding.
2472 Double-precision is expected when DP_P is TRUE, otherwise the
2473 representation should be in single-precision. */
2474 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2479 if (!can_convert_double_to_float (val
, &fpword
))
2482 else if ((uint64_t) val
> 0xffffffff)
2489 else if (reg_name_p (str
, reg_type
))
2491 set_recoverable_error (_("immediate operand required"));
2499 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2502 /* Our FP word must be 32 bits (single-precision FP). */
2503 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2505 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2515 set_fatal_syntax_error (_("invalid floating-point constant"));
2519 /* Less-generic immediate-value read function with the possibility of loading
2520 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2523 To prevent the expression parser from pushing a register name into the
2524 symbol table as an undefined symbol, a check is firstly done to find
2525 out whether STR is a register of type REG_TYPE followed by a comma or
2526 the end of line. Return FALSE if STR is such a register. */
2529 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2533 if (reg_name_p (ptr
, reg_type
))
2535 set_syntax_error (_("immediate operand required"));
2539 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2541 if (inst
.reloc
.exp
.X_op
== O_constant
)
2542 *imm
= inst
.reloc
.exp
.X_add_number
;
2549 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2550 if NEED_LIBOPCODES is non-zero, the fixup will need
2551 assistance from the libopcodes. */
2554 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2555 const aarch64_opnd_info
*operand
,
2556 int need_libopcodes_p
)
2558 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2559 reloc
->opnd
= operand
->type
;
2560 if (need_libopcodes_p
)
2561 reloc
->need_libopcodes_p
= 1;
2564 /* Return TRUE if the instruction needs to be fixed up later internally by
2565 the GAS; otherwise return FALSE. */
2567 static inline bfd_boolean
2568 aarch64_gas_internal_fixup_p (void)
2570 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2573 /* Assign the immediate value to the relevant field in *OPERAND if
2574 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2575 needs an internal fixup in a later stage.
2576 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2577 IMM.VALUE that may get assigned with the constant. */
2579 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2580 aarch64_opnd_info
*operand
,
2582 int need_libopcodes_p
,
2585 if (reloc
->exp
.X_op
== O_constant
)
2588 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2590 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2591 reloc
->type
= BFD_RELOC_UNUSED
;
2595 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2596 /* Tell libopcodes to ignore this operand or not. This is helpful
2597 when one of the operands needs to be fixed up later but we need
2598 libopcodes to check the other operands. */
2599 operand
->skip
= skip_p
;
2603 /* Relocation modifiers. Each entry in the table contains the textual
2604 name for the relocation which may be placed before a symbol used as
2605 a load/store offset, or add immediate. It must be surrounded by a
2606 leading and trailing colon, for example:
2608 ldr x0, [x1, #:rello:varsym]
2609 add x0, x1, #:rello:varsym */
2611 struct reloc_table_entry
2615 bfd_reloc_code_real_type adr_type
;
2616 bfd_reloc_code_real_type adrp_type
;
2617 bfd_reloc_code_real_type c64_adrp_type
;
2618 bfd_reloc_code_real_type movw_type
;
2619 bfd_reloc_code_real_type add_type
;
2620 bfd_reloc_code_real_type ldst_type
;
2621 bfd_reloc_code_real_type ld_literal_type
;
2624 static struct reloc_table_entry reloc_table
[] = {
2625 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2631 BFD_RELOC_AARCH64_ADD_LO12
,
2632 BFD_RELOC_AARCH64_LDST_LO12
,
2635 /* Higher 21 bits of pc-relative page offset: ADRP */
2638 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2639 BFD_RELOC_MORELLO_ADR_HI20_PCREL
,
2645 /* Higher 21 bits (20 bits for C64) of pc-relative page offset: ADRP, no
2649 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2650 BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
,
2656 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2661 BFD_RELOC_AARCH64_MOVW_G0
,
2666 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2671 BFD_RELOC_AARCH64_MOVW_G0_S
,
2676 /* Less significant bits 0-15 of address/value: MOVK, no check */
2681 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2686 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2691 BFD_RELOC_AARCH64_MOVW_G1
,
2696 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2701 BFD_RELOC_AARCH64_MOVW_G1_S
,
2706 /* Less significant bits 16-31 of address/value: MOVK, no check */
2711 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2716 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2721 BFD_RELOC_AARCH64_MOVW_G2
,
2726 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2731 BFD_RELOC_AARCH64_MOVW_G2_S
,
2736 /* Less significant bits 32-47 of address/value: MOVK, no check */
2741 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2746 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2751 BFD_RELOC_AARCH64_MOVW_G3
,
2756 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2761 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2766 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2771 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2776 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2781 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2786 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2791 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2796 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2801 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2806 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2811 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2816 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2821 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2826 /* Get to the page containing GOT entry for a symbol. */
2829 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2830 BFD_RELOC_MORELLO_ADR_GOT_PAGE
,
2834 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2836 /* 12 bit offset into the page containing GOT entry for that symbol. */
2843 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2846 /* 0-15 bits of address/value: MOVk, no check. */
2851 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2856 /* Most significant bits 16-31 of address/value: MOVZ. */
2861 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2866 /* 15 bit offset into the page containing GOT entry for that symbol. */
2873 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2876 /* Get to the page containing GOT TLS entry for a symbol */
2877 {"gottprel_g0_nc", 0,
2881 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2886 /* Get to the page containing GOT TLS entry for a symbol */
2891 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2896 /* Get to the page containing GOT TLS entry for a symbol */
2898 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2899 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2906 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2912 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2916 /* Lower 16 bits address/value: MOVk. */
2921 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2926 /* Most significant bits 16-31 of address/value: MOVZ. */
2931 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2936 /* Get to the page containing GOT TLS entry for a symbol */
2938 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2939 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2940 BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20
,
2944 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2946 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2952 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2953 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2956 /* Get to the page containing GOT TLS entry for a symbol.
2957 The same as GD, we allocate two consecutive GOT slots
2958 for module index and module offset, the only difference
2959 with GD is the module offset should be initialized to
2960 zero without any outstanding runtime relocation. */
2962 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2963 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2970 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2971 {"tlsldm_lo12_nc", 0,
2976 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2980 /* 12 bit offset into the module TLS base address. */
2986 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2987 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2990 /* Same as dtprel_lo12, no overflow check. */
2991 {"dtprel_lo12_nc", 0,
2996 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2997 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3000 /* bits[23:12] of offset to the module TLS base address. */
3006 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3010 /* bits[15:0] of offset to the module TLS base address. */
3015 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3020 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3025 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3030 /* bits[31:16] of offset to the module TLS base address. */
3035 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3040 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3045 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3050 /* bits[47:32] of offset to the module TLS base address. */
3055 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3060 /* Lower 16 bit offset into GOT entry for a symbol */
3061 {"tlsdesc_off_g0_nc", 0,
3065 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3070 /* Higher 16 bit offset into GOT entry for a symbol */
3071 {"tlsdesc_off_g1", 0,
3075 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3080 /* Get to the page containing GOT TLS entry for a symbol */
3083 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3088 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3090 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3091 {"gottprel_lo12", 0,
3097 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3100 /* Get tp offset for a symbol. */
3106 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3110 /* Get tp offset for a symbol. */
3116 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3117 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3120 /* Get tp offset for a symbol. */
3126 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3130 /* Get tp offset for a symbol. */
3131 {"tprel_lo12_nc", 0,
3136 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3137 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3140 /* Most significant bits 32-47 of address/value: MOVZ. */
3145 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3150 /* Most significant bits 16-31 of address/value: MOVZ. */
3155 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3160 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3165 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3170 /* Most significant bits 0-15 of address/value: MOVZ. */
3175 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3180 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3185 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3190 /* 15bit offset from got entry to base address of GOT table. */
3197 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3200 /* 14bit offset from got entry to base address of GOT table. */
3207 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3211 /* Given the address of a pointer pointing to the textual name of a
3212 relocation as may appear in assembler source, attempt to find its
3213 details in reloc_table. The pointer will be updated to the character
3214 after the trailing colon. On failure, NULL will be returned;
3215 otherwise return the reloc_table_entry. */
3217 static struct reloc_table_entry
*
3218 find_reloc_table_entry (char **str
)
3221 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3223 int length
= strlen (reloc_table
[i
].name
);
3225 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3226 && (*str
)[length
] == ':')
3228 *str
+= (length
+ 1);
3229 return &reloc_table
[i
];
3236 /* Mode argument to parse_shift and parser_shifter_operand. */
3237 enum parse_shift_mode
3239 SHIFTED_NONE
, /* no shifter allowed */
3240 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3242 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3244 SHIFTED_LSL
, /* bare "lsl #n" */
3245 SHIFTED_MUL
, /* bare "mul #n" */
3246 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3247 SHIFTED_MUL_VL
, /* "mul vl" */
3248 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3251 /* Parse a <shift> operator on an AArch64 data processing instruction.
3252 Return TRUE on success; otherwise return FALSE. */
3254 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3256 const struct aarch64_name_value_pair
*shift_op
;
3257 enum aarch64_modifier_kind kind
;
3263 for (p
= *str
; ISALPHA (*p
); p
++)
3268 set_syntax_error (_("shift expression expected"));
3272 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3274 if (shift_op
== NULL
)
3276 set_syntax_error (_("shift operator expected"));
3280 kind
= aarch64_get_operand_modifier (shift_op
);
3282 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3284 set_syntax_error (_("invalid use of 'MSL'"));
3288 if (kind
== AARCH64_MOD_MUL
3289 && mode
!= SHIFTED_MUL
3290 && mode
!= SHIFTED_MUL_VL
)
3292 set_syntax_error (_("invalid use of 'MUL'"));
3298 case SHIFTED_LOGIC_IMM
:
3299 if (aarch64_extend_operator_p (kind
))
3301 set_syntax_error (_("extending shift is not permitted"));
3306 case SHIFTED_ARITH_IMM
:
3307 if (kind
== AARCH64_MOD_ROR
)
3309 set_syntax_error (_("'ROR' shift is not permitted"));
3315 if (kind
!= AARCH64_MOD_LSL
)
3317 set_syntax_error (_("only 'LSL' shift is permitted"));
3323 if (kind
!= AARCH64_MOD_MUL
)
3325 set_syntax_error (_("only 'MUL' is permitted"));
3330 case SHIFTED_MUL_VL
:
3331 /* "MUL VL" consists of two separate tokens. Require the first
3332 token to be "MUL" and look for a following "VL". */
3333 if (kind
== AARCH64_MOD_MUL
)
3335 skip_whitespace (p
);
3336 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3339 kind
= AARCH64_MOD_MUL_VL
;
3343 set_syntax_error (_("only 'MUL VL' is permitted"));
3346 case SHIFTED_REG_OFFSET
:
3347 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3348 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3350 set_fatal_syntax_error
3351 (_("invalid shift for the register offset addressing mode"));
3356 case SHIFTED_LSL_MSL
:
3357 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3359 set_syntax_error (_("invalid shift operator"));
3368 /* Whitespace can appear here if the next thing is a bare digit. */
3369 skip_whitespace (p
);
3371 /* Parse shift amount. */
3373 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3374 exp
.X_op
= O_absent
;
3377 if (is_immediate_prefix (*p
))
3382 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3384 if (kind
== AARCH64_MOD_MUL_VL
)
3385 /* For consistency, give MUL VL the same shift amount as an implicit
3387 operand
->shifter
.amount
= 1;
3388 else if (exp
.X_op
== O_absent
)
3390 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3392 set_syntax_error (_("missing shift amount"));
3395 operand
->shifter
.amount
= 0;
3397 else if (exp
.X_op
!= O_constant
)
3399 set_syntax_error (_("constant shift amount required"));
3402 /* For parsing purposes, MUL #n has no inherent range. The range
3403 depends on the operand and will be checked by operand-specific
3405 else if (kind
!= AARCH64_MOD_MUL
3406 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3408 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3413 operand
->shifter
.amount
= exp
.X_add_number
;
3414 operand
->shifter
.amount_present
= 1;
3417 operand
->shifter
.operator_present
= 1;
3418 operand
->shifter
.kind
= kind
;
3424 /* Parse a <shifter_operand> for a data processing instruction:
3427 #<immediate>, LSL #imm
3429 Validation of immediate operands is deferred to md_apply_fix.
3431 Return TRUE on success; otherwise return FALSE. */
3434 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3435 enum parse_shift_mode mode
)
3439 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3444 /* Accept an immediate expression. */
3445 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3448 /* Accept optional LSL for arithmetic immediate values. */
3449 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3450 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3453 /* Not accept any shifter for logical immediate values. */
3454 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3455 && parse_shift (&p
, operand
, mode
))
3457 set_syntax_error (_("unexpected shift operator"));
3465 /* Parse a <shifter_operand> for a data processing instruction:
3470 #<immediate>, LSL #imm
3472 where <shift> is handled by parse_shift above, and the last two
3473 cases are handled by the function above.
3475 Validation of immediate operands is deferred to md_apply_fix.
3477 Return TRUE on success; otherwise return FALSE. */
3480 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3481 enum parse_shift_mode mode
)
3483 const reg_entry
*reg
;
3484 aarch64_opnd_qualifier_t qualifier
;
3485 enum aarch64_operand_class opd_class
3486 = aarch64_get_operand_class (operand
->type
);
3488 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3491 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3493 set_syntax_error (_("unexpected register in the immediate operand"));
3497 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3499 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3503 operand
->reg
.regno
= reg
->number
;
3504 operand
->qualifier
= qualifier
;
3506 /* Accept optional shift operation on register. */
3507 if (! skip_past_comma (str
))
3510 if (! parse_shift (str
, operand
, mode
))
3515 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3518 (_("integer register expected in the extended/shifted operand "
3523 /* We have a shifted immediate variable. */
3524 return parse_shifter_operand_imm (str
, operand
, mode
);
3527 /* Return TRUE on success; return FALSE otherwise. */
3530 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3531 enum parse_shift_mode mode
)
3535 /* Determine if we have the sequence of characters #: or just :
3536 coming next. If we do, then we check for a :rello: relocation
3537 modifier. If we don't, punt the whole lot to
3538 parse_shifter_operand. */
3540 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3542 struct reloc_table_entry
*entry
;
3550 /* Try to parse a relocation. Anything else is an error. */
3551 if (!(entry
= find_reloc_table_entry (str
)))
3553 set_syntax_error (_("unknown relocation modifier"));
3557 if (entry
->add_type
== 0)
3560 (_("this relocation modifier is not allowed on this instruction"));
3564 /* Save str before we decompose it. */
3567 /* Next, we parse the expression. */
3568 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3571 /* Record the relocation type (use the ADD variant here). */
3572 inst
.reloc
.type
= entry
->add_type
;
3573 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3575 /* If str is empty, we've reached the end, stop here. */
3579 /* Otherwise, we have a shifted reloc modifier, so rewind to
3580 recover the variable name and continue parsing for the shifter. */
3582 return parse_shifter_operand_imm (str
, operand
, mode
);
3585 return parse_shifter_operand (str
, operand
, mode
);
3588 /* Parse all forms of an address expression. Information is written
3589 to *OPERAND and/or inst.reloc.
3591 The A64 instruction set has the following addressing modes:
3594 [base] // in SIMD ld/st structure
3595 [base{,#0}] // in ld/st exclusive
3597 [base,Xm{,LSL #imm}]
3598 [base,Xm,SXTX {#imm}]
3599 [base,Wm,(S|U)XTW {#imm}]
3601 [base]! // in ldraa/ldrab exclusive
3605 [base],Xm // in SIMD ld/st structure
3606 PC-relative (literal)
3610 [base,Zm.D{,LSL #imm}]
3611 [base,Zm.S,(S|U)XTW {#imm}]
3612 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3616 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3617 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3618 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3620 (As a convenience, the notation "=immediate" is permitted in conjunction
3621 with the pc-relative literal load instructions to automatically place an
3622 immediate value or symbolic address in a nearby literal pool and generate
3623 a hidden label which references it.)
3625 Upon a successful parsing, the address structure in *OPERAND will be
3626 filled in the following way:
3628 .base_regno = <base>
3629 .offset.is_reg // 1 if the offset is a register
3631 .offset.regno = <Rm>
3633 For different addressing modes defined in the A64 ISA:
3636 .pcrel=0; .preind=1; .postind=0; .writeback=0
3638 .pcrel=0; .preind=1; .postind=0; .writeback=1
3640 .pcrel=0; .preind=0; .postind=1; .writeback=1
3641 PC-relative (literal)
3642 .pcrel=1; .preind=1; .postind=0; .writeback=0
3644 The shift/extension information, if any, will be stored in .shifter.
3645 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3646 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3647 corresponding register.
3649 BASE_TYPE says which types of base register should be accepted and
3650 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3651 is the type of shifter that is allowed for immediate offsets,
3652 or SHIFTED_NONE if none.
3654 In all other respects, it is the caller's responsibility to check
3655 for addressing modes not supported by the instruction, and to set
3659 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3660 aarch64_opnd_qualifier_t
*base_qualifier
,
3661 aarch64_opnd_qualifier_t
*offset_qualifier
,
3662 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3663 enum parse_shift_mode imm_shift_mode
)
3666 const reg_entry
*reg
;
3667 expressionS
*exp
= &inst
.reloc
.exp
;
3669 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3670 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3671 if (! skip_past_char (&p
, '['))
3673 /* =immediate or label. */
3674 operand
->addr
.pcrel
= 1;
3675 operand
->addr
.preind
= 1;
3677 /* #:<reloc_op>:<symbol> */
3678 skip_past_char (&p
, '#');
3679 if (skip_past_char (&p
, ':'))
3681 bfd_reloc_code_real_type ty
;
3682 struct reloc_table_entry
*entry
;
3684 /* Try to parse a relocation modifier. Anything else is
3686 entry
= find_reloc_table_entry (&p
);
3689 set_syntax_error (_("unknown relocation modifier"));
3693 switch (operand
->type
)
3695 case AARCH64_OPND_ADDR_PCREL21
:
3697 ty
= entry
->adr_type
;
3701 ty
= entry
->ld_literal_type
;
3708 (_("this relocation modifier is not allowed on this "
3714 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3716 set_syntax_error (_("invalid relocation expression"));
3720 /* #:<reloc_op>:<expr> */
3721 /* Record the relocation type. */
3722 inst
.reloc
.type
= ty
;
3723 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3728 if (skip_past_char (&p
, '='))
3729 /* =immediate; need to generate the literal in the literal pool. */
3730 inst
.gen_lit_pool
= 1;
3732 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3734 set_syntax_error (_("invalid address"));
3745 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3746 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3748 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3751 operand
->addr
.base_regno
= reg
->number
;
3754 if (skip_past_comma (&p
))
3757 operand
->addr
.preind
= 1;
3759 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3762 if (!aarch64_check_reg_type (reg
, offset_type
))
3764 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3769 operand
->addr
.offset
.regno
= reg
->number
;
3770 operand
->addr
.offset
.is_reg
= 1;
3771 /* Shifted index. */
3772 if (skip_past_comma (&p
))
3775 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3776 /* Use the diagnostics set in parse_shift, so not set new
3777 error message here. */
3781 [base,Xm] # For vector plus scalar SVE2 indexing.
3782 [base,Xm{,LSL #imm}]
3783 [base,Xm,SXTX {#imm}]
3784 [base,Wm,(S|U)XTW {#imm}] */
3785 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3786 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3787 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3789 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3791 set_syntax_error (_("invalid use of 32-bit register offset"));
3794 if (aarch64_get_qualifier_esize (*base_qualifier
)
3795 != aarch64_get_qualifier_esize (*offset_qualifier
)
3796 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3797 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3798 || *offset_qualifier
!= AARCH64_OPND_QLF_X
)
3799 /* Capabilities can have W as well as X registers as
3801 && (*base_qualifier
!= AARCH64_OPND_QLF_CA
))
3803 set_syntax_error (_("offset has different size from base"));
3807 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3809 set_syntax_error (_("invalid use of 64-bit register offset"));
3815 /* [Xn,#:<reloc_op>:<symbol> */
3816 skip_past_char (&p
, '#');
3817 if (skip_past_char (&p
, ':'))
3819 struct reloc_table_entry
*entry
;
3821 /* Try to parse a relocation modifier. Anything else is
3823 if (!(entry
= find_reloc_table_entry (&p
)))
3825 set_syntax_error (_("unknown relocation modifier"));
3829 if (entry
->ldst_type
== 0)
3832 (_("this relocation modifier is not allowed on this "
3837 /* [Xn,#:<reloc_op>: */
3838 /* We now have the group relocation table entry corresponding to
3839 the name in the assembler source. Next, we parse the
3841 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3843 set_syntax_error (_("invalid relocation expression"));
3847 /* [Xn,#:<reloc_op>:<expr> */
3848 /* Record the load/store relocation type. */
3849 inst
.reloc
.type
= entry
->ldst_type
;
3850 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3854 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3856 set_syntax_error (_("invalid expression in the address"));
3860 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3861 /* [Xn,<expr>,<shifter> */
3862 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3868 if (! skip_past_char (&p
, ']'))
3870 set_syntax_error (_("']' expected"));
3874 if (skip_past_char (&p
, '!'))
3876 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3878 set_syntax_error (_("register offset not allowed in pre-indexed "
3879 "addressing mode"));
3883 operand
->addr
.writeback
= 1;
3885 else if (skip_past_comma (&p
))
3888 operand
->addr
.postind
= 1;
3889 operand
->addr
.writeback
= 1;
3891 if (operand
->addr
.preind
)
3893 set_syntax_error (_("cannot combine pre- and post-indexing"));
3897 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3901 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3903 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3907 operand
->addr
.offset
.regno
= reg
->number
;
3908 operand
->addr
.offset
.is_reg
= 1;
3910 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3913 set_syntax_error (_("invalid expression in the address"));
3918 /* If at this point neither .preind nor .postind is set, we have a
3919 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3920 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3921 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3923 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3925 if (operand
->addr
.writeback
)
3927 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3929 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3930 operand
->addr
.offset
.is_reg
= 0;
3931 operand
->addr
.offset
.imm
= 0;
3932 operand
->addr
.preind
= 1;
3937 set_syntax_error (_("missing offset in the pre-indexed address"));
3943 operand
->addr
.preind
= 1;
3944 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3946 operand
->addr
.offset
.is_reg
= 1;
3947 operand
->addr
.offset
.regno
= REG_ZR
;
3948 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3952 inst
.reloc
.exp
.X_op
= O_constant
;
3953 inst
.reloc
.exp
.X_add_number
= 0;
3962 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3965 parse_address (char **str
, aarch64_opnd_info
*operand
)
3967 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3969 aarch64_reg_type base
;
3971 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
))
3972 base
= REG_TYPE_CA_N_SP
;
3974 base
= REG_TYPE_R64_SP
;
3976 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3977 base
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3980 /* Parse a base capability address. Return TRUE on success. */
3982 parse_cap_address (char **str
, aarch64_opnd_info
*operand
,
3983 enum aarch64_insn_class
class)
3985 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3986 aarch64_reg_type base
;
3988 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
)
3989 && class != br_capaddr
)
3990 base
= REG_TYPE_R64_SP
;
3992 base
= REG_TYPE_CA_N_SP
;
3994 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3995 base
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3998 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3999 The arguments have the same meaning as for parse_address_main.
4000 Return TRUE on success. */
4002 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4003 aarch64_opnd_qualifier_t
*base_qualifier
,
4004 aarch64_opnd_qualifier_t
*offset_qualifier
)
4006 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4007 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4011 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4012 Return TRUE on success; otherwise return FALSE. */
4014 parse_half (char **str
, int *internal_fixup_p
)
4018 skip_past_char (&p
, '#');
4020 gas_assert (internal_fixup_p
);
4021 *internal_fixup_p
= 0;
4025 struct reloc_table_entry
*entry
;
4027 /* Try to parse a relocation. Anything else is an error. */
4029 if (!(entry
= find_reloc_table_entry (&p
)))
4031 set_syntax_error (_("unknown relocation modifier"));
4035 if (entry
->movw_type
== 0)
4038 (_("this relocation modifier is not allowed on this instruction"));
4042 inst
.reloc
.type
= entry
->movw_type
;
4045 *internal_fixup_p
= 1;
4047 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
4054 /* Parse an operand for an ADRP instruction:
4056 Return TRUE on success; otherwise return FALSE. */
4059 parse_adrp (char **str
)
4066 struct reloc_table_entry
*entry
;
4067 bfd_reloc_code_real_type adrp_type
;
4069 /* Try to parse a relocation. Anything else is an error. */
4071 if (!(entry
= find_reloc_table_entry (&p
)))
4073 set_syntax_error (_("unknown relocation modifier"));
4077 adrp_type
= (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
)
4078 ? entry
->c64_adrp_type
: entry
->adrp_type
);
4083 (_("this relocation modifier is not allowed on this instruction"));
4087 inst
.reloc
.type
= adrp_type
;
4090 inst
.reloc
.type
= (AARCH64_CPU_HAS_FEATURE (cpu_variant
,
4091 AARCH64_FEATURE_C64
)
4092 ? BFD_RELOC_MORELLO_ADR_HI20_PCREL
4093 : BFD_RELOC_AARCH64_ADR_HI21_PCREL
);
4095 inst
.reloc
.pc_rel
= 1;
4097 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
4104 /* Miscellaneous. */
4106 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4107 of SIZE tokens in which index I gives the token for field value I,
4108 or is null if field value I is invalid. REG_TYPE says which register
4109 names should be treated as registers rather than as symbolic immediates.
4111 Return true on success, moving *STR past the operand and storing the
4112 field value in *VAL. */
4115 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4116 size_t size
, aarch64_reg_type reg_type
)
4122 /* Match C-like tokens. */
4124 while (ISALNUM (*q
))
4127 for (i
= 0; i
< size
; ++i
)
4129 && strncasecmp (array
[i
], p
, q
- p
) == 0
4130 && array
[i
][q
- p
] == 0)
4137 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4140 if (exp
.X_op
== O_constant
4141 && (uint64_t) exp
.X_add_number
< size
)
4143 *val
= exp
.X_add_number
;
4148 /* Use the default error for this operand. */
4152 /* Parse an option for a preload instruction. Returns the encoding for the
4153 option, or PARSE_FAIL. */
4156 parse_pldop (char **str
)
4159 const struct aarch64_name_value_pair
*o
;
4162 while (ISALNUM (*q
))
4165 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4173 /* Parse an option for a barrier instruction. Returns the encoding for the
4174 option, or PARSE_FAIL. */
4177 parse_barrier (char **str
)
4180 const struct aarch64_name_value_pair
*o
;
4183 while (ISALPHA (*q
))
4186 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4194 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4195 return 0 if successful. Otherwise return PARSE_FAIL. */
4198 parse_barrier_psb (char **str
,
4199 const struct aarch64_name_value_pair
** hint_opt
)
4202 const struct aarch64_name_value_pair
*o
;
4205 while (ISALPHA (*q
))
4208 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4211 set_fatal_syntax_error
4212 ( _("unknown or missing option to PSB/TSB"));
4216 if (o
->value
!= 0x11)
4218 /* PSB only accepts option name 'CSYNC'. */
4220 (_("the specified option is not accepted for PSB/TSB"));
4229 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4230 return 0 if successful. Otherwise return PARSE_FAIL. */
4233 parse_bti_operand (char **str
,
4234 const struct aarch64_name_value_pair
** hint_opt
)
4237 const struct aarch64_name_value_pair
*o
;
4240 while (ISALPHA (*q
))
4243 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4246 set_fatal_syntax_error
4247 ( _("unknown option to BTI"));
4253 /* Valid BTI operands. */
4261 (_("unknown option to BTI"));
4270 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4271 Returns the encoding for the option, or PARSE_FAIL.
4273 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4274 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4276 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4277 field, otherwise as a system register.
4281 parse_sys_reg (const aarch64_opcode
*opcode
, char **str
, htab_t sys_regs
,
4282 int imple_defined_p
, int pstatefield_p
,
4286 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4287 const aarch64_sys_reg
*o
;
4291 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4292 if (p
< buf
+ (sizeof (buf
) - 1))
4293 *p
++ = TOLOWER (*q
);
4296 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4297 valid system register. This is enforced by construction of the hash
4299 if (p
- buf
!= q
- *str
)
4302 o
= str_hash_find (sys_regs
, buf
);
4305 if (!imple_defined_p
)
4309 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4310 unsigned int op0
, op1
, cn
, cm
, op2
;
4312 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4315 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4317 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4324 if (!aarch64_sys_reg_capreg_supported_p (opcode
->iclass
, o
))
4327 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4328 as_bad (_("selected processor does not support PSTATE field "
4331 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4332 o
->value
, o
->flags
, o
->features
))
4333 as_bad (_("selected processor does not support system register "
4335 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4336 as_warn (_("system register name '%s' is deprecated and may be "
4337 "removed in a future release"), buf
);
4347 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4348 for the option, or NULL. */
4350 static const aarch64_sys_ins_reg
*
4351 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4354 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4355 const aarch64_sys_ins_reg
*o
;
4358 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4359 if (p
< buf
+ (sizeof (buf
) - 1))
4360 *p
++ = TOLOWER (*q
);
4363 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4364 valid system register. This is enforced by construction of the hash
4366 if (p
- buf
!= q
- *str
)
4369 o
= str_hash_find (sys_ins_regs
, buf
);
4373 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4374 o
->name
, o
->value
, o
->flags
, 0))
4375 as_bad (_("selected processor does not support system register "
4377 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4378 as_warn (_("system register name '%s' is deprecated and may be "
4379 "removed in a future release"), buf
);
4385 #define po_char_or_fail(chr) do { \
4386 if (! skip_past_char (&str, chr)) \
4390 #define po_reg_or_fail(regtype) do { \
4391 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4392 if (val == PARSE_FAIL) \
4394 set_default_error (); \
4399 #define po_int_reg_or_fail(reg_type) do { \
4400 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4401 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4403 set_default_error (); \
4406 info->reg.regno = reg->number; \
4407 info->qualifier = qualifier; \
4410 #define po_imm_nc_or_fail() do { \
4411 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4415 #define po_imm_or_fail(min, max) do { \
4416 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4418 if (val < min || val > max) \
4420 set_fatal_syntax_error (_("immediate value out of range "\
4421 #min " to "#max)); \
4426 #define po_enum_or_fail(array) do { \
4427 if (!parse_enum_string (&str, &val, array, \
4428 ARRAY_SIZE (array), imm_reg_type)) \
4432 #define po_misc_or_fail(expr) do { \
4437 /* encode the 12-bit imm field of Add/sub immediate */
4438 static inline uint32_t
4439 encode_addsub_imm (uint32_t imm
)
4444 /* encode the shift amount field of Add/sub immediate */
4445 static inline uint32_t
4446 encode_addsub_imm_shift_amount (uint32_t cnt
)
4452 /* encode the imm field of Adr instruction */
4453 static inline uint32_t
4454 encode_adr_imm (uint32_t imm
)
4456 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4457 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4460 /* encode the immediate field of Move wide immediate */
4461 static inline uint32_t
4462 encode_movw_imm (uint32_t imm
)
4467 /* encode the 26-bit offset of unconditional branch */
4468 static inline uint32_t
4469 encode_branch_ofs_26 (uint32_t ofs
)
4471 return ofs
& ((1 << 26) - 1);
4474 /* encode the 19-bit offset of conditional branch and compare & branch */
4475 static inline uint32_t
4476 encode_cond_branch_ofs_19 (uint32_t ofs
)
4478 return (ofs
& ((1 << 19) - 1)) << 5;
4481 /* encode the 17-bit offset of ld literal */
4482 static inline uint32_t
4483 encode_ld_lit_ofs_17 (uint32_t ofs
)
4485 return (ofs
& ((1 << 17) - 1)) << 5;
4488 /* encode the 19-bit offset of ld literal */
4489 static inline uint32_t
4490 encode_ld_lit_ofs_19 (uint32_t ofs
)
4492 return (ofs
& ((1 << 19) - 1)) << 5;
4495 /* Encode the 14-bit offset of test & branch. */
4496 static inline uint32_t
4497 encode_tst_branch_ofs_14 (uint32_t ofs
)
4499 return (ofs
& ((1 << 14) - 1)) << 5;
4502 /* Encode the 16-bit imm field of svc/hvc/smc. */
4503 static inline uint32_t
4504 encode_svc_imm (uint32_t imm
)
4509 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4510 static inline uint32_t
4511 reencode_addsub_switch_add_sub (uint32_t opcode
)
4513 return opcode
^ (1 << 30);
4516 static inline uint32_t
4517 reencode_movzn_to_movz (uint32_t opcode
)
4519 return opcode
| (1 << 30);
4522 static inline uint32_t
4523 reencode_movzn_to_movn (uint32_t opcode
)
4525 return opcode
& ~(1 << 30);
4528 /* Overall per-instruction processing. */
4530 /* We need to be able to fix up arbitrary expressions in some statements.
4531 This is so that we can handle symbols that are an arbitrary distance from
4532 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4533 which returns part of an address in a form which will be valid for
4534 a data instruction. We do this by pushing the expression into a symbol
4535 in the expr_section, and creating a fix for that. */
4538 fix_new_aarch64 (fragS
* frag
,
4553 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4557 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4564 /* Diagnostics on operands errors. */
4566 /* By default, output verbose error message.
4567 Disable the verbose error message by -mno-verbose-error. */
4568 static int verbose_error_p
= 1;
4570 #ifdef DEBUG_AARCH64
4571 /* N.B. this is only for the purpose of debugging. */
4572 const char* operand_mismatch_kind_names
[] =
4575 "AARCH64_OPDE_RECOVERABLE",
4576 "AARCH64_OPDE_SYNTAX_ERROR",
4577 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4578 "AARCH64_OPDE_INVALID_VARIANT",
4579 "AARCH64_OPDE_OUT_OF_RANGE",
4580 "AARCH64_OPDE_UNALIGNED",
4581 "AARCH64_OPDE_REG_LIST",
4582 "AARCH64_OPDE_OTHER_ERROR",
4584 #endif /* DEBUG_AARCH64 */
4586 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4588 When multiple errors of different kinds are found in the same assembly
4589 line, only the error of the highest severity will be picked up for
4590 issuing the diagnostics. */
4592 static inline bfd_boolean
4593 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4594 enum aarch64_operand_error_kind rhs
)
4596 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4597 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4598 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4599 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4600 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4601 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4602 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4603 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4607 /* Helper routine to get the mnemonic name from the assembly instruction
4608 line; should only be called for the diagnosis purpose, as there is
4609 string copy operation involved, which may affect the runtime
4610 performance if used in elsewhere. */
4613 get_mnemonic_name (const char *str
)
4615 static char mnemonic
[32];
4618 /* Get the first 15 bytes and assume that the full name is included. */
4619 strncpy (mnemonic
, str
, 31);
4620 mnemonic
[31] = '\0';
4622 /* Scan up to the end of the mnemonic, which must end in white space,
4623 '.', or end of string. */
4624 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4629 /* Append '...' to the truncated long name. */
4630 if (ptr
- mnemonic
== 31)
4631 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4637 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4639 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4640 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4643 /* Data structures storing one user error in the assembly code related to
4646 struct operand_error_record
4648 const aarch64_opcode
*opcode
;
4649 aarch64_operand_error detail
;
4650 struct operand_error_record
*next
;
4653 typedef struct operand_error_record operand_error_record
;
4655 struct operand_errors
4657 operand_error_record
*head
;
4658 operand_error_record
*tail
;
4661 typedef struct operand_errors operand_errors
;
4663 /* Top-level data structure reporting user errors for the current line of
4665 The way md_assemble works is that all opcodes sharing the same mnemonic
4666 name are iterated to find a match to the assembly line. In this data
4667 structure, each of the such opcodes will have one operand_error_record
4668 allocated and inserted. In other words, excessive errors related with
4669 a single opcode are disregarded. */
4670 operand_errors operand_error_report
;
4672 /* Free record nodes. */
4673 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4675 /* Initialize the data structure that stores the operand mismatch
4676 information on assembling one line of the assembly code. */
4678 init_operand_error_report (void)
4680 if (operand_error_report
.head
!= NULL
)
4682 gas_assert (operand_error_report
.tail
!= NULL
);
4683 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4684 free_opnd_error_record_nodes
= operand_error_report
.head
;
4685 operand_error_report
.head
= NULL
;
4686 operand_error_report
.tail
= NULL
;
4689 gas_assert (operand_error_report
.tail
== NULL
);
4692 /* Return TRUE if some operand error has been recorded during the
4693 parsing of the current assembly line using the opcode *OPCODE;
4694 otherwise return FALSE. */
4695 static inline bfd_boolean
4696 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4698 operand_error_record
*record
= operand_error_report
.head
;
4699 return record
&& record
->opcode
== opcode
;
4702 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4703 OPCODE field is initialized with OPCODE.
4704 N.B. only one record for each opcode, i.e. the maximum of one error is
4705 recorded for each instruction template. */
4708 add_operand_error_record (const operand_error_record
* new_record
)
4710 const aarch64_opcode
*opcode
= new_record
->opcode
;
4711 operand_error_record
* record
= operand_error_report
.head
;
4713 /* The record may have been created for this opcode. If not, we need
4715 if (! opcode_has_operand_error_p (opcode
))
4717 /* Get one empty record. */
4718 if (free_opnd_error_record_nodes
== NULL
)
4720 record
= XNEW (operand_error_record
);
4724 record
= free_opnd_error_record_nodes
;
4725 free_opnd_error_record_nodes
= record
->next
;
4727 record
->opcode
= opcode
;
4728 /* Insert at the head. */
4729 record
->next
= operand_error_report
.head
;
4730 operand_error_report
.head
= record
;
4731 if (operand_error_report
.tail
== NULL
)
4732 operand_error_report
.tail
= record
;
4734 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4735 && record
->detail
.index
<= new_record
->detail
.index
4736 && operand_error_higher_severity_p (record
->detail
.kind
,
4737 new_record
->detail
.kind
))
4739 /* In the case of multiple errors found on operands related with a
4740 single opcode, only record the error of the leftmost operand and
4741 only if the error is of higher severity. */
4742 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4743 " the existing error %s on operand %d",
4744 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4745 new_record
->detail
.index
,
4746 operand_mismatch_kind_names
[record
->detail
.kind
],
4747 record
->detail
.index
);
4751 record
->detail
= new_record
->detail
;
4755 record_operand_error_info (const aarch64_opcode
*opcode
,
4756 aarch64_operand_error
*error_info
)
4758 operand_error_record record
;
4759 record
.opcode
= opcode
;
4760 record
.detail
= *error_info
;
4761 add_operand_error_record (&record
);
4764 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4765 error message *ERROR, for operand IDX (count from 0). */
4768 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4769 enum aarch64_operand_error_kind kind
,
4772 aarch64_operand_error info
;
4773 memset(&info
, 0, sizeof (info
));
4777 info
.non_fatal
= FALSE
;
4778 record_operand_error_info (opcode
, &info
);
4782 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4783 enum aarch64_operand_error_kind kind
,
4784 const char* error
, const int *extra_data
)
4786 aarch64_operand_error info
;
4790 info
.data
[0] = extra_data
[0];
4791 info
.data
[1] = extra_data
[1];
4792 info
.data
[2] = extra_data
[2];
4793 info
.non_fatal
= FALSE
;
4794 record_operand_error_info (opcode
, &info
);
4798 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4799 const char* error
, int lower_bound
,
4802 int data
[3] = {lower_bound
, upper_bound
, 0};
4803 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4807 /* Remove the operand error record for *OPCODE. */
4808 static void ATTRIBUTE_UNUSED
4809 remove_operand_error_record (const aarch64_opcode
*opcode
)
4811 if (opcode_has_operand_error_p (opcode
))
4813 operand_error_record
* record
= operand_error_report
.head
;
4814 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4815 operand_error_report
.head
= record
->next
;
4816 record
->next
= free_opnd_error_record_nodes
;
4817 free_opnd_error_record_nodes
= record
;
4818 if (operand_error_report
.head
== NULL
)
4820 gas_assert (operand_error_report
.tail
== record
);
4821 operand_error_report
.tail
= NULL
;
4826 /* Given the instruction in *INSTR, return the index of the best matched
4827 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4829 Return -1 if there is no qualifier sequence; return the first match
4830 if there is multiple matches found. */
4833 find_best_match (const aarch64_inst
*instr
,
4834 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4836 int i
, num_opnds
, max_num_matched
, idx
;
4838 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4841 DEBUG_TRACE ("no operand");
4845 max_num_matched
= 0;
4848 /* For each pattern. */
4849 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4852 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4854 /* Most opcodes has much fewer patterns in the list. */
4855 if (empty_qualifier_sequence_p (qualifiers
))
4857 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4861 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4862 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4865 if (num_matched
> max_num_matched
)
4867 max_num_matched
= num_matched
;
4872 DEBUG_TRACE ("return with %d", idx
);
4876 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4877 corresponding operands in *INSTR. */
4880 assign_qualifier_sequence (aarch64_inst
*instr
,
4881 const aarch64_opnd_qualifier_t
*qualifiers
)
4884 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4885 gas_assert (num_opnds
);
4886 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4887 instr
->operands
[i
].qualifier
= *qualifiers
;
4890 /* Print operands for the diagnosis purpose. */
4893 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4894 const aarch64_opnd_info
*opnds
)
4898 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4902 /* We regard the opcode operand info more, however we also look into
4903 the inst->operands to support the disassembling of the optional
4905 The two operand code should be the same in all cases, apart from
4906 when the operand can be optional. */
4907 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4908 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4911 /* Generate the operand string in STR. */
4912 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4917 strcat (buf
, i
== 0 ? " " : ", ");
4919 /* Append the operand string. */
4924 /* Send to stderr a string as information. */
4927 output_info (const char *format
, ...)
4933 file
= as_where (&line
);
4937 fprintf (stderr
, "%s:%u: ", file
, line
);
4939 fprintf (stderr
, "%s: ", file
);
4941 fprintf (stderr
, _("Info: "));
4942 va_start (args
, format
);
4943 vfprintf (stderr
, format
, args
);
4945 (void) putc ('\n', stderr
);
4948 /* Output one operand error record. */
4951 output_operand_error_record (const operand_error_record
*record
, char *str
)
4953 const aarch64_operand_error
*detail
= &record
->detail
;
4954 int idx
= detail
->index
;
4955 const aarch64_opcode
*opcode
= record
->opcode
;
4956 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4957 : AARCH64_OPND_NIL
);
4959 typedef void (*handler_t
)(const char *format
, ...);
4960 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4962 switch (detail
->kind
)
4964 case AARCH64_OPDE_NIL
:
4967 case AARCH64_OPDE_SYNTAX_ERROR
:
4968 case AARCH64_OPDE_RECOVERABLE
:
4969 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4970 case AARCH64_OPDE_OTHER_ERROR
:
4971 /* Use the prepared error message if there is, otherwise use the
4972 operand description string to describe the error. */
4973 if (detail
->error
!= NULL
)
4976 handler (_("%s -- `%s'"), detail
->error
, str
);
4978 handler (_("%s at operand %d -- `%s'"),
4979 detail
->error
, idx
+ 1, str
);
4983 gas_assert (idx
>= 0);
4984 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4985 aarch64_get_operand_desc (opd_code
), str
);
4989 case AARCH64_OPDE_INVALID_VARIANT
:
4990 handler (_("operand mismatch -- `%s'"), str
);
4991 if (verbose_error_p
)
4993 /* We will try to correct the erroneous instruction and also provide
4994 more information e.g. all other valid variants.
4996 The string representation of the corrected instruction and other
4997 valid variants are generated by
4999 1) obtaining the intermediate representation of the erroneous
5001 2) manipulating the IR, e.g. replacing the operand qualifier;
5002 3) printing out the instruction by calling the printer functions
5003 shared with the disassembler.
5005 The limitation of this method is that the exact input assembly
5006 line cannot be accurately reproduced in some cases, for example an
5007 optional operand present in the actual assembly line will be
5008 omitted in the output; likewise for the optional syntax rules,
5009 e.g. the # before the immediate. Another limitation is that the
5010 assembly symbols and relocation operations in the assembly line
5011 currently cannot be printed out in the error report. Last but not
5012 least, when there is other error(s) co-exist with this error, the
5013 'corrected' instruction may be still incorrect, e.g. given
5014 'ldnp h0,h1,[x0,#6]!'
5015 this diagnosis will provide the version:
5016 'ldnp s0,s1,[x0,#6]!'
5017 which is still not right. */
5018 size_t len
= strlen (get_mnemonic_name (str
));
5022 aarch64_inst
*inst_base
= &inst
.base
;
5023 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5026 reset_aarch64_instruction (&inst
);
5027 inst_base
->opcode
= opcode
;
5029 /* Reset the error report so that there is no side effect on the
5030 following operand parsing. */
5031 init_operand_error_report ();
5034 result
= parse_operands (str
+ len
, opcode
)
5035 && programmer_friendly_fixup (&inst
);
5036 gas_assert (result
);
5037 result
= aarch64_opcode_encode (cpu_variant
, opcode
, inst_base
,
5038 &inst_base
->value
, NULL
, NULL
,
5040 gas_assert (!result
);
5042 /* Find the most matched qualifier sequence. */
5043 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5044 gas_assert (qlf_idx
> -1);
5046 /* Assign the qualifiers. */
5047 assign_qualifier_sequence (inst_base
,
5048 opcode
->qualifiers_list
[qlf_idx
]);
5050 /* Print the hint. */
5051 output_info (_(" did you mean this?"));
5052 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5053 print_operands (buf
, opcode
, inst_base
->operands
);
5054 output_info (_(" %s"), buf
);
5056 /* Print out other variant(s) if there is any. */
5058 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5059 output_info (_(" other valid variant(s):"));
5061 /* For each pattern. */
5062 qualifiers_list
= opcode
->qualifiers_list
;
5063 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5065 /* Most opcodes has much fewer patterns in the list.
5066 First NIL qualifier indicates the end in the list. */
5067 if (empty_qualifier_sequence_p (*qualifiers_list
))
5072 /* Mnemonics name. */
5073 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5075 /* Assign the qualifiers. */
5076 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5078 /* Print instruction. */
5079 print_operands (buf
, opcode
, inst_base
->operands
);
5081 output_info (_(" %s"), buf
);
5087 case AARCH64_OPDE_UNTIED_OPERAND
:
5088 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5089 detail
->index
+ 1, str
);
5092 case AARCH64_OPDE_OUT_OF_RANGE
:
5093 if (detail
->data
[0] != detail
->data
[1])
5094 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5095 detail
->error
? detail
->error
: _("immediate value"),
5096 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
5098 handler (_("%s must be %d at operand %d -- `%s'"),
5099 detail
->error
? detail
->error
: _("immediate value"),
5100 detail
->data
[0], idx
+ 1, str
);
5103 case AARCH64_OPDE_REG_LIST
:
5104 if (detail
->data
[0] == 1)
5105 handler (_("invalid number of registers in the list; "
5106 "only 1 register is expected at operand %d -- `%s'"),
5109 handler (_("invalid number of registers in the list; "
5110 "%d registers are expected at operand %d -- `%s'"),
5111 detail
->data
[0], idx
+ 1, str
);
5114 case AARCH64_OPDE_UNALIGNED
:
5115 handler (_("immediate value must be a multiple of "
5116 "%d at operand %d -- `%s'"),
5117 detail
->data
[0], idx
+ 1, str
);
5126 /* Process and output the error message about the operand mismatching.
5128 When this function is called, the operand error information had
5129 been collected for an assembly line and there will be multiple
5130 errors in the case of multiple instruction templates; output the
5131 error message that most closely describes the problem.
5133 The errors to be printed can be filtered on printing all errors
5134 or only non-fatal errors. This distinction has to be made because
5135 the error buffer may already be filled with fatal errors we don't want to
5136 print due to the different instruction templates. */
5139 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
5141 int largest_error_pos
, largest_error_pos2
;
5142 const char *msg
= NULL
, *msg2
= NULL
;
5143 enum aarch64_operand_error_kind kind
;
5144 operand_error_record
*curr
;
5145 operand_error_record
*head
= operand_error_report
.head
;
5146 operand_error_record
*record
= NULL
, *record2
= NULL
;
5148 /* No error to report. */
5152 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5154 /* Only one error. */
5155 if (head
== operand_error_report
.tail
)
5157 /* If the only error is a non-fatal one and we don't want to print it,
5159 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5161 DEBUG_TRACE ("single opcode entry with error kind: %s",
5162 operand_mismatch_kind_names
[head
->detail
.kind
]);
5163 output_operand_error_record (head
, str
);
5168 /* Find the error kind of the highest severity. */
5169 DEBUG_TRACE ("multiple opcode entries with error kind");
5170 kind
= AARCH64_OPDE_NIL
;
5171 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5173 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5174 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5175 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5176 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5177 kind
= curr
->detail
.kind
;
5180 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5182 /* Pick up one of errors of KIND to report. */
5183 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5184 largest_error_pos2
= -2; /* Index can be -1 which means unknown index. */
5185 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5187 /* If we don't want to print non-fatal errors then don't consider them
5189 if (curr
->detail
.kind
!= kind
5190 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5192 /* If there are multiple errors, pick up the one with the highest
5193 mismatching operand index. In the case of multiple errors with
5194 the equally highest operand index, pick up the first one or the
5195 first one with non-NULL error message. */
5196 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, *curr
->opcode
->avariant
))
5198 if (curr
->detail
.index
> largest_error_pos
5199 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5200 && curr
->detail
.error
!= NULL
))
5202 largest_error_pos
= curr
->detail
.index
;
5204 msg
= record
->detail
.error
;
5209 if (curr
->detail
.index
> largest_error_pos2
5210 || (curr
->detail
.index
== largest_error_pos2
&& msg2
== NULL
5211 && curr
->detail
.error
!= NULL
))
5213 largest_error_pos2
= curr
->detail
.index
;
5215 msg2
= record2
->detail
.error
;
5220 /* No errors in enabled cpu feature variants, look for errors in the disabled
5221 ones. XXX we should do this segregation when prioritizing too. */
5224 largest_error_pos
= largest_error_pos2
;
5229 /* The way errors are collected in the back-end is a bit non-intuitive. But
5230 essentially, because each operand template is tried recursively you may
5231 always have errors collected from the previous tried OPND. These are
5232 usually skipped if there is one successful match. However now with the
5233 non-fatal errors we have to ignore those previously collected hard errors
5234 when we're only interested in printing the non-fatal ones. This condition
5235 prevents us from printing errors that are not appropriate, since we did
5236 match a condition, but it also has warnings that it wants to print. */
5237 if (non_fatal_only
&& !record
)
5240 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5241 DEBUG_TRACE ("Pick up error kind %s to report",
5242 operand_mismatch_kind_names
[record
->detail
.kind
]);
5245 output_operand_error_record (record
, str
);
5248 /* Write an AARCH64 instruction to buf - always little-endian. */
5250 put_aarch64_insn (char *buf
, uint32_t insn
)
5252 unsigned char *where
= (unsigned char *) buf
;
5254 where
[1] = insn
>> 8;
5255 where
[2] = insn
>> 16;
5256 where
[3] = insn
>> 24;
5260 get_aarch64_insn (char *buf
)
5262 unsigned char *where
= (unsigned char *) buf
;
5264 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5265 | ((uint32_t) where
[3] << 24)));
5270 output_inst (struct aarch64_inst
*new_inst
)
5274 to
= frag_more (INSN_SIZE
);
5276 frag_now
->tc_frag_data
.recorded
= 1;
5278 put_aarch64_insn (to
, inst
.base
.value
);
5280 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5282 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5283 INSN_SIZE
, &inst
.reloc
.exp
,
5286 DEBUG_TRACE ("Prepared relocation fix up");
5287 /* Don't check the addend value against the instruction size,
5288 that's the job of our code in md_apply_fix(). */
5289 fixp
->fx_no_overflow
= 1;
5290 if (new_inst
!= NULL
)
5291 fixp
->tc_fix_data
.inst
= new_inst
;
5292 if (aarch64_gas_internal_fixup_p ())
5294 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5295 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5296 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5298 if (inst
.reloc
.flags
& FIXUP_F_C64
)
5299 fixp
->tc_fix_data
.c64
= TRUE
;
5302 dwarf2_emit_insn (INSN_SIZE
);
5305 /* Link together opcodes of the same name. */
5309 aarch64_opcode
*opcode
;
5310 struct templates
*next
;
5313 typedef struct templates templates
;
5316 lookup_mnemonic (const char *start
, int len
)
5318 templates
*templ
= NULL
;
5320 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5324 /* Subroutine of md_assemble, responsible for looking up the primary
5325 opcode from the mnemonic the user wrote. STR points to the
5326 beginning of the mnemonic. */
5329 opcode_lookup (char **str
)
5331 char *end
, *base
, *dot
;
5332 const aarch64_cond
*cond
;
5336 /* Scan up to the end of the mnemonic, which must end in white space,
5337 '.', or end of string. */
5339 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5340 if (*end
== '.' && !dot
)
5343 if (end
== base
|| dot
== base
)
5346 inst
.cond
= COND_ALWAYS
;
5348 /* Handle a possible condition. */
5351 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5354 inst
.cond
= cond
->value
;
5370 if (inst
.cond
== COND_ALWAYS
)
5372 /* Look for unaffixed mnemonic. */
5373 return lookup_mnemonic (base
, len
);
5377 /* append ".c" to mnemonic if conditional */
5378 memcpy (condname
, base
, len
);
5379 memcpy (condname
+ len
, ".c", 2);
5382 return lookup_mnemonic (base
, len
);
5388 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5389 to a corresponding operand qualifier. */
5391 static inline aarch64_opnd_qualifier_t
5392 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5394 /* Element size in bytes indexed by vector_el_type. */
5395 const unsigned char ele_size
[5]
5397 const unsigned int ele_base
[5] =
5399 AARCH64_OPND_QLF_V_4B
,
5400 AARCH64_OPND_QLF_V_2H
,
5401 AARCH64_OPND_QLF_V_2S
,
5402 AARCH64_OPND_QLF_V_1D
,
5403 AARCH64_OPND_QLF_V_1Q
5406 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5407 goto vectype_conversion_fail
;
5409 if (vectype
->type
== NT_zero
)
5410 return AARCH64_OPND_QLF_P_Z
;
5411 if (vectype
->type
== NT_merge
)
5412 return AARCH64_OPND_QLF_P_M
;
5414 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5416 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5418 /* Special case S_4B. */
5419 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5420 return AARCH64_OPND_QLF_S_4B
;
5422 /* Special case S_2H. */
5423 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5424 return AARCH64_OPND_QLF_S_2H
;
5426 /* Vector element register. */
5427 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5431 /* Vector register. */
5432 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5435 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5436 goto vectype_conversion_fail
;
5438 /* The conversion is by calculating the offset from the base operand
5439 qualifier for the vector type. The operand qualifiers are regular
5440 enough that the offset can established by shifting the vector width by
5441 a vector-type dependent amount. */
5443 if (vectype
->type
== NT_b
)
5445 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5447 else if (vectype
->type
>= NT_d
)
5452 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5453 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5454 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5458 vectype_conversion_fail
:
5459 first_error (_("bad vector arrangement type"));
5460 return AARCH64_OPND_QLF_NIL
;
5463 /* Process an optional operand that is found omitted from the assembly line.
5464 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5465 instruction's opcode entry while IDX is the index of this omitted operand.
5469 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5470 int idx
, aarch64_opnd_info
*operand
)
5472 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5473 gas_assert (optional_operand_p (opcode
, idx
));
5474 gas_assert (!operand
->present
);
5478 case AARCH64_OPND_Can
:
5479 case AARCH64_OPND_Cat_SYS
:
5480 case AARCH64_OPND_Rd
:
5481 case AARCH64_OPND_Rn
:
5482 case AARCH64_OPND_Rm
:
5483 case AARCH64_OPND_Rt
:
5484 case AARCH64_OPND_Rt2
:
5485 case AARCH64_OPND_Rt_SP
:
5486 case AARCH64_OPND_Rs
:
5487 case AARCH64_OPND_Ra
:
5488 case AARCH64_OPND_Rt_SYS
:
5489 case AARCH64_OPND_Rd_SP
:
5490 case AARCH64_OPND_Rn_SP
:
5491 case AARCH64_OPND_Rm_SP
:
5492 case AARCH64_OPND_Fd
:
5493 case AARCH64_OPND_Fn
:
5494 case AARCH64_OPND_Fm
:
5495 case AARCH64_OPND_Fa
:
5496 case AARCH64_OPND_Ft
:
5497 case AARCH64_OPND_Ft2
:
5498 case AARCH64_OPND_Sd
:
5499 case AARCH64_OPND_Sn
:
5500 case AARCH64_OPND_Sm
:
5501 case AARCH64_OPND_Va
:
5502 case AARCH64_OPND_Vd
:
5503 case AARCH64_OPND_Vn
:
5504 case AARCH64_OPND_Vm
:
5505 case AARCH64_OPND_VdD1
:
5506 case AARCH64_OPND_VnD1
:
5507 operand
->reg
.regno
= default_value
;
5510 case AARCH64_OPND_Ed
:
5511 case AARCH64_OPND_En
:
5512 case AARCH64_OPND_Em
:
5513 case AARCH64_OPND_Em16
:
5514 case AARCH64_OPND_SM3_IMM2
:
5515 operand
->reglane
.regno
= default_value
;
5518 case AARCH64_OPND_IDX
:
5519 case AARCH64_OPND_BIT_NUM
:
5520 case AARCH64_OPND_IMMR
:
5521 case AARCH64_OPND_IMMS
:
5522 case AARCH64_OPND_SHLL_IMM
:
5523 case AARCH64_OPND_IMM_VLSL
:
5524 case AARCH64_OPND_IMM_VLSR
:
5525 case AARCH64_OPND_CCMP_IMM
:
5526 case AARCH64_OPND_FBITS
:
5527 case AARCH64_OPND_UIMM4
:
5528 case AARCH64_OPND_UIMM3_OP1
:
5529 case AARCH64_OPND_UIMM3_OP2
:
5530 case AARCH64_OPND_IMM
:
5531 case AARCH64_OPND_IMM_2
:
5532 case AARCH64_OPND_WIDTH
:
5533 case AARCH64_OPND_UIMM7
:
5534 case AARCH64_OPND_NZCV
:
5535 case AARCH64_OPND_SVE_PATTERN
:
5536 case AARCH64_OPND_SVE_PRFOP
:
5537 operand
->imm
.value
= default_value
;
5540 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5541 operand
->imm
.value
= default_value
;
5542 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5543 operand
->shifter
.amount
= 1;
5546 case AARCH64_OPND_EXCEPTION
:
5547 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5550 case AARCH64_OPND_BARRIER_ISB
:
5551 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5554 case AARCH64_OPND_BTI_TARGET
:
5555 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5563 /* Process the relocation type for move wide instructions.
5564 Return TRUE on success; otherwise return FALSE. */
5567 process_movw_reloc_info (void)
5572 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5574 if (inst
.base
.opcode
->op
== OP_MOVK
)
5575 switch (inst
.reloc
.type
)
5577 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5578 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5579 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5580 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5581 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5582 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5583 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5584 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5585 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5586 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5587 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5589 (_("the specified relocation type is not allowed for MOVK"));
5595 switch (inst
.reloc
.type
)
5597 case BFD_RELOC_AARCH64_MOVW_G0
:
5598 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5599 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5600 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5601 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5602 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5603 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5604 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5605 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5606 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5607 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5608 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5609 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5612 case BFD_RELOC_AARCH64_MOVW_G1
:
5613 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5614 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5615 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5616 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5617 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5618 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5619 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5620 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5621 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5622 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5623 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5624 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5627 case BFD_RELOC_AARCH64_MOVW_G2
:
5628 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5629 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5630 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5631 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5632 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5633 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5636 set_fatal_syntax_error
5637 (_("the specified relocation type is not allowed for 32-bit "
5643 case BFD_RELOC_AARCH64_MOVW_G3
:
5644 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5647 set_fatal_syntax_error
5648 (_("the specified relocation type is not allowed for 32-bit "
5655 /* More cases should be added when more MOVW-related relocation types
5656 are supported in GAS. */
5657 gas_assert (aarch64_gas_internal_fixup_p ());
5658 /* The shift amount should have already been set by the parser. */
5661 inst
.base
.operands
[1].shifter
.amount
= shift
;
5665 /* A primitive log calculator. */
5667 static inline unsigned int
5668 get_logsz (unsigned int size
)
5670 const unsigned char ls
[16] =
5671 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5677 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5678 return ls
[size
- 1];
5681 /* Determine and return the real reloc type code for an instruction
5682 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5684 static inline bfd_reloc_code_real_type
5685 ldst_lo12_determine_real_reloc_type (void)
5688 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5689 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5691 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5693 BFD_RELOC_AARCH64_LDST8_LO12
,
5694 BFD_RELOC_AARCH64_LDST16_LO12
,
5695 BFD_RELOC_AARCH64_LDST32_LO12
,
5696 BFD_RELOC_AARCH64_LDST64_LO12
,
5697 BFD_RELOC_AARCH64_LDST128_LO12
5700 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5701 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5702 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5703 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5704 BFD_RELOC_AARCH64_NONE
5707 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5708 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5709 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5710 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5711 BFD_RELOC_AARCH64_NONE
5714 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5715 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5716 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5717 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5718 BFD_RELOC_AARCH64_NONE
5721 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5722 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5723 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5724 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5725 BFD_RELOC_AARCH64_NONE
5729 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5730 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5732 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5734 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5736 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5737 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
5738 || inst
.base
.opcode
->operands
[1] == AARCH64_OPND_CAPADDR_UIMM9
);
5740 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5742 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5744 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5746 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5747 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5748 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5749 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5750 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5751 gas_assert (logsz
<= 3);
5753 gas_assert (logsz
<= 4);
5755 /* In reloc.c, these pseudo relocation types should be defined in similar
5756 order as above reloc_ldst_lo12 array. Because the array index calculation
5757 below relies on this. */
5758 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5761 /* Check whether a register list REGINFO is valid. The registers must be
5762 numbered in increasing order (modulo 32), in increments of one or two.
5764 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5767 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5770 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5772 uint32_t i
, nb_regs
, prev_regno
, incr
;
5774 nb_regs
= 1 + (reginfo
& 0x3);
5776 prev_regno
= reginfo
& 0x1f;
5777 incr
= accept_alternate
? 2 : 1;
5779 for (i
= 1; i
< nb_regs
; ++i
)
5781 uint32_t curr_regno
;
5783 curr_regno
= reginfo
& 0x1f;
5784 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5786 prev_regno
= curr_regno
;
5793 parse_perms (char **str
, aarch64_opnd_info
*info
)
5797 aarch64_insn perms
= 0;
5799 /* Numeric value of permissions. */
5800 if (ISDIGIT (*p
) || (*p
== '#' && p
++))
5803 if (p
[1] > 0 || perms
> 7)
5805 set_syntax_error (_("invalid permission value"));
5812 /* Permission specifier mnemonics r, w and x, in that order. Do not accept
5813 jumbled up sequences such as rxw, wrx, etc. and also reject duplicate
5814 permissions such as rrxw. */
5815 while ((c
= *p
++) != '\0')
5817 aarch64_insn i
= get_perm_bit (c
);
5818 if (i
> 7 || i
& perms
|| (i
- 1) & perms
)
5820 set_syntax_error (_("invalid permissions"));
5832 /* Generic instruction operand parser. This does no encoding and no
5833 semantic validation; it merely squirrels values away in the inst
5834 structure. Returns TRUE or FALSE depending on whether the
5835 specified grammar matched. */
5838 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5841 char *backtrack_pos
= 0;
5842 const enum aarch64_opnd
*operands
= opcode
->operands
;
5843 aarch64_reg_type imm_reg_type
;
5846 skip_whitespace (str
);
5848 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5849 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5851 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5853 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5856 const reg_entry
*reg
;
5857 int comma_skipped_p
= 0;
5858 aarch64_reg_type rtype
;
5859 struct vector_type_el vectype
;
5860 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5861 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5862 aarch64_reg_type reg_type
;
5864 DEBUG_TRACE ("parse operand %d", i
);
5866 /* Assign the operand code. */
5867 info
->type
= operands
[i
];
5869 if (optional_operand_p (opcode
, i
))
5871 /* Remember where we are in case we need to backtrack. */
5872 gas_assert (!backtrack_pos
);
5873 backtrack_pos
= str
;
5876 /* Expect comma between operands; the backtrack mechanism will take
5877 care of cases of omitted optional operand. */
5878 if (i
> 0 && ! skip_past_char (&str
, ','))
5880 set_syntax_error (_("comma expected between operands"));
5884 comma_skipped_p
= 1;
5886 switch (operands
[i
])
5888 case AARCH64_OPND_Wt
:
5889 po_int_reg_or_fail (REG_TYPE_R_32
);
5892 case AARCH64_OPND_Rsz
:
5893 case AARCH64_OPND_Rsz2
:
5894 case AARCH64_OPND_Rd
:
5895 case AARCH64_OPND_Rn
:
5896 case AARCH64_OPND_Rm
:
5897 case AARCH64_OPND_Rt
:
5898 case AARCH64_OPND_Rt2
:
5899 case AARCH64_OPND_Rs
:
5900 case AARCH64_OPND_Ra
:
5901 case AARCH64_OPND_Rt_SYS
:
5902 case AARCH64_OPND_PAIRREG
:
5903 case AARCH64_OPND_SVE_Rm
:
5904 po_int_reg_or_fail (REG_TYPE_R_Z
);
5907 case AARCH64_OPND_Rd_SP
:
5908 case AARCH64_OPND_Rn_SP
:
5909 case AARCH64_OPND_Rt_SP
:
5910 case AARCH64_OPND_SVE_Rn_SP
:
5911 case AARCH64_OPND_Rm_SP
:
5912 po_int_reg_or_fail (REG_TYPE_R_SP
);
5915 case AARCH64_OPND_A64C_Rm_EXT
:
5916 case AARCH64_OPND_Rm_EXT
:
5917 case AARCH64_OPND_Rm_SFT
:
5918 po_misc_or_fail (parse_shifter_operand
5919 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_SFT
5921 : SHIFTED_ARITH_IMM
)));
5922 if (!info
->shifter
.operator_present
)
5924 /* Default to LSL if not present. Libopcodes prefers shifter
5925 kind to be explicit. */
5926 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5927 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5928 /* For Rm_EXT, libopcodes will carry out further check on whether
5929 or not stack pointer is used in the instruction (Recall that
5930 "the extend operator is not optional unless at least one of
5931 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5935 case AARCH64_OPND_Fsz
:
5936 case AARCH64_OPND_Fd
:
5937 case AARCH64_OPND_Fn
:
5938 case AARCH64_OPND_Fm
:
5939 case AARCH64_OPND_Fa
:
5940 case AARCH64_OPND_Ft
:
5941 case AARCH64_OPND_Ft2
:
5942 case AARCH64_OPND_Sd
:
5943 case AARCH64_OPND_Sn
:
5944 case AARCH64_OPND_Sm
:
5945 case AARCH64_OPND_St
:
5946 case AARCH64_OPND_SVE_VZn
:
5947 case AARCH64_OPND_SVE_Vd
:
5948 case AARCH64_OPND_SVE_Vm
:
5949 case AARCH64_OPND_SVE_Vn
:
5950 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5951 if (val
== PARSE_FAIL
)
5953 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5956 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5958 info
->reg
.regno
= val
;
5959 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5962 case AARCH64_OPND_SVE_Pd
:
5963 case AARCH64_OPND_SVE_Pg3
:
5964 case AARCH64_OPND_SVE_Pg4_5
:
5965 case AARCH64_OPND_SVE_Pg4_10
:
5966 case AARCH64_OPND_SVE_Pg4_16
:
5967 case AARCH64_OPND_SVE_Pm
:
5968 case AARCH64_OPND_SVE_Pn
:
5969 case AARCH64_OPND_SVE_Pt
:
5970 reg_type
= REG_TYPE_PN
;
5973 case AARCH64_OPND_SVE_Za_5
:
5974 case AARCH64_OPND_SVE_Za_16
:
5975 case AARCH64_OPND_SVE_Zd
:
5976 case AARCH64_OPND_SVE_Zm_5
:
5977 case AARCH64_OPND_SVE_Zm_16
:
5978 case AARCH64_OPND_SVE_Zn
:
5979 case AARCH64_OPND_SVE_Zt
:
5980 reg_type
= REG_TYPE_ZN
;
5983 case AARCH64_OPND_Va
:
5984 case AARCH64_OPND_Vd
:
5985 case AARCH64_OPND_Vn
:
5986 case AARCH64_OPND_Vm
:
5987 reg_type
= REG_TYPE_VN
;
5989 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5990 if (val
== PARSE_FAIL
)
5992 first_error (_(get_reg_expected_msg (reg_type
)));
5995 if (vectype
.defined
& NTA_HASINDEX
)
5998 info
->reg
.regno
= val
;
5999 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6000 && vectype
.type
== NT_invtype
)
6001 /* Unqualified Pn and Zn registers are allowed in certain
6002 contexts. Rely on F_STRICT qualifier checking to catch
6004 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6007 info
->qualifier
= vectype_to_qualifier (&vectype
);
6008 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6013 case AARCH64_OPND_VdD1
:
6014 case AARCH64_OPND_VnD1
:
6015 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6016 if (val
== PARSE_FAIL
)
6018 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6021 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6023 set_fatal_syntax_error
6024 (_("the top half of a 128-bit FP/SIMD register is expected"));
6027 info
->reg
.regno
= val
;
6028 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6029 here; it is correct for the purpose of encoding/decoding since
6030 only the register number is explicitly encoded in the related
6031 instructions, although this appears a bit hacky. */
6032 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6035 case AARCH64_OPND_SVE_Zm3_INDEX
:
6036 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6037 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6038 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6039 case AARCH64_OPND_SVE_Zm4_INDEX
:
6040 case AARCH64_OPND_SVE_Zn_INDEX
:
6041 reg_type
= REG_TYPE_ZN
;
6042 goto vector_reg_index
;
6044 case AARCH64_OPND_Ed
:
6045 case AARCH64_OPND_En
:
6046 case AARCH64_OPND_Em
:
6047 case AARCH64_OPND_Em16
:
6048 case AARCH64_OPND_SM3_IMM2
:
6049 reg_type
= REG_TYPE_VN
;
6051 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6052 if (val
== PARSE_FAIL
)
6054 first_error (_(get_reg_expected_msg (reg_type
)));
6057 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6060 info
->reglane
.regno
= val
;
6061 info
->reglane
.index
= vectype
.index
;
6062 info
->qualifier
= vectype_to_qualifier (&vectype
);
6063 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6067 case AARCH64_OPND_SVE_ZnxN
:
6068 case AARCH64_OPND_SVE_ZtxN
:
6069 reg_type
= REG_TYPE_ZN
;
6070 goto vector_reg_list
;
6072 case AARCH64_OPND_LVn
:
6073 case AARCH64_OPND_LVt
:
6074 case AARCH64_OPND_LVt_AL
:
6075 case AARCH64_OPND_LEt
:
6076 reg_type
= REG_TYPE_VN
;
6078 if (reg_type
== REG_TYPE_ZN
6079 && get_opcode_dependent_value (opcode
) == 1
6082 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6083 if (val
== PARSE_FAIL
)
6085 first_error (_(get_reg_expected_msg (reg_type
)));
6088 info
->reglist
.first_regno
= val
;
6089 info
->reglist
.num_regs
= 1;
6093 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6094 if (val
== PARSE_FAIL
)
6097 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6099 set_fatal_syntax_error (_("invalid register list"));
6103 if (vectype
.width
!= 0 && *str
!= ',')
6105 set_fatal_syntax_error
6106 (_("expected element type rather than vector type"));
6110 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6111 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6113 if (operands
[i
] == AARCH64_OPND_LEt
)
6115 if (!(vectype
.defined
& NTA_HASINDEX
))
6117 info
->reglist
.has_index
= 1;
6118 info
->reglist
.index
= vectype
.index
;
6122 if (vectype
.defined
& NTA_HASINDEX
)
6124 if (!(vectype
.defined
& NTA_HASTYPE
))
6126 if (reg_type
== REG_TYPE_ZN
)
6127 set_fatal_syntax_error (_("missing type suffix"));
6131 info
->qualifier
= vectype_to_qualifier (&vectype
);
6132 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6136 case AARCH64_OPND_Can
:
6137 case AARCH64_OPND_Cam
:
6138 case AARCH64_OPND_Cas
:
6139 case AARCH64_OPND_Cad
:
6140 case AARCH64_OPND_Cat
:
6141 case AARCH64_OPND_Cat2
:
6142 case AARCH64_OPND_Cat_SYS
:
6143 po_reg_or_fail (REG_TYPE_CA_N_Z
);
6144 if (opcode
->op
== OP_MOV_C_ZR
&& operands
[i
] == AARCH64_OPND_Can
6147 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CA_Z
)));
6152 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CA_N
)));
6155 info
->reg
.regno
= val
;
6156 info
->qualifier
= AARCH64_OPND_QLF_CA
;
6159 case AARCH64_OPND_A64C_CST_REG
:
6160 po_reg_or_fail (REG_TYPE_CA_N
);
6162 && (opcode
->iclass
== br_sealed
))
6164 set_fatal_syntax_error
6165 (_(N_ ("Capability register c29 expected")));
6168 info
->reg
.regno
= val
;
6169 info
->qualifier
= AARCH64_OPND_QLF_CA
;
6172 case AARCH64_OPND_Cam_SP
:
6173 case AARCH64_OPND_Can_SP
:
6174 case AARCH64_OPND_Cad_SP
:
6175 po_reg_or_fail (REG_TYPE_CA_N_SP
);
6176 info
->reg
.regno
= val
;
6177 info
->qualifier
= AARCH64_OPND_QLF_CA
;
6180 case AARCH64_OPND_CRn
:
6181 case AARCH64_OPND_CRm
:
6183 char prefix
= *(str
++);
6184 if (prefix
!= 'c' && prefix
!= 'C')
6187 po_imm_nc_or_fail ();
6190 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6193 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6194 info
->imm
.value
= val
;
6198 case AARCH64_OPND_SHLL_IMM
:
6199 case AARCH64_OPND_IMM_VLSR
:
6200 po_imm_or_fail (1, 64);
6201 info
->imm
.value
= val
;
6204 case AARCH64_OPND_A64C_IMM8
:
6205 case AARCH64_OPND_CCMP_IMM
:
6206 case AARCH64_OPND_SIMM5
:
6207 case AARCH64_OPND_FBITS
:
6208 case AARCH64_OPND_TME_UIMM16
:
6209 case AARCH64_OPND_UIMM4
:
6210 case AARCH64_OPND_UIMM4_ADDG
:
6211 case AARCH64_OPND_UIMM10
:
6212 case AARCH64_OPND_UIMM3_OP1
:
6213 case AARCH64_OPND_UIMM3_OP2
:
6214 case AARCH64_OPND_IMM_VLSL
:
6215 case AARCH64_OPND_IMM
:
6216 case AARCH64_OPND_IMM_2
:
6217 case AARCH64_OPND_WIDTH
:
6218 case AARCH64_OPND_SVE_INV_LIMM
:
6219 case AARCH64_OPND_SVE_LIMM
:
6220 case AARCH64_OPND_SVE_LIMM_MOV
:
6221 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6222 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6223 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6224 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6225 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6226 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6227 case AARCH64_OPND_SVE_SIMM5
:
6228 case AARCH64_OPND_SVE_SIMM5B
:
6229 case AARCH64_OPND_SVE_SIMM6
:
6230 case AARCH64_OPND_SVE_SIMM8
:
6231 case AARCH64_OPND_SVE_UIMM3
:
6232 case AARCH64_OPND_SVE_UIMM7
:
6233 case AARCH64_OPND_SVE_UIMM8
:
6234 case AARCH64_OPND_SVE_UIMM8_53
:
6235 case AARCH64_OPND_IMM_ROT1
:
6236 case AARCH64_OPND_IMM_ROT2
:
6237 case AARCH64_OPND_IMM_ROT3
:
6238 case AARCH64_OPND_SVE_IMM_ROT1
:
6239 case AARCH64_OPND_SVE_IMM_ROT2
:
6240 case AARCH64_OPND_SVE_IMM_ROT3
:
6241 po_imm_nc_or_fail ();
6242 info
->imm
.value
= val
;
6245 case AARCH64_OPND_SVE_AIMM
:
6246 case AARCH64_OPND_SVE_ASIMM
:
6247 po_imm_nc_or_fail ();
6248 info
->imm
.value
= val
;
6249 skip_whitespace (str
);
6250 if (skip_past_comma (&str
))
6251 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6253 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6256 case AARCH64_OPND_SVE_PATTERN
:
6257 po_enum_or_fail (aarch64_sve_pattern_array
);
6258 info
->imm
.value
= val
;
6261 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6262 po_enum_or_fail (aarch64_sve_pattern_array
);
6263 info
->imm
.value
= val
;
6264 if (skip_past_comma (&str
)
6265 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6267 if (!info
->shifter
.operator_present
)
6269 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6270 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6271 info
->shifter
.amount
= 1;
6275 case AARCH64_OPND_SVE_PRFOP
:
6276 po_enum_or_fail (aarch64_sve_prfop_array
);
6277 info
->imm
.value
= val
;
6280 case AARCH64_OPND_UIMM7
:
6281 po_imm_or_fail (0, 127);
6282 info
->imm
.value
= val
;
6285 case AARCH64_OPND_IDX
:
6286 case AARCH64_OPND_MASK
:
6287 case AARCH64_OPND_BIT_NUM
:
6288 case AARCH64_OPND_IMMR
:
6289 case AARCH64_OPND_IMMS
:
6290 po_imm_or_fail (0, 63);
6291 info
->imm
.value
= val
;
6294 case AARCH64_OPND_A64C_IMMV4
:
6295 po_imm_nc_or_fail ();
6298 set_fatal_syntax_error (_("immediate #4 expected"));
6301 info
->imm
.value
= 4;
6304 case AARCH64_OPND_IMM0
:
6305 po_imm_nc_or_fail ();
6308 set_fatal_syntax_error (_("immediate zero expected"));
6311 info
->imm
.value
= 0;
6314 case AARCH64_OPND_FPIMM0
:
6317 bfd_boolean res1
= FALSE
, res2
= FALSE
;
6318 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6319 it is probably not worth the effort to support it. */
6320 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
6323 || !(res2
= parse_constant_immediate (&str
, &val
,
6326 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6328 info
->imm
.value
= 0;
6329 info
->imm
.is_fp
= 1;
6332 set_fatal_syntax_error (_("immediate zero expected"));
6336 case AARCH64_OPND_IMM_MOV
:
6339 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6340 reg_name_p (str
, REG_TYPE_VN
))
6343 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6345 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6346 later. fix_mov_imm_insn will try to determine a machine
6347 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6348 message if the immediate cannot be moved by a single
6350 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6351 inst
.base
.operands
[i
].skip
= 1;
6355 case AARCH64_OPND_SIMD_IMM
:
6356 case AARCH64_OPND_SIMD_IMM_SFT
:
6357 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6359 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6361 /* need_libopcodes_p */ 1,
6364 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6365 shift, we don't check it here; we leave the checking to
6366 the libopcodes (operand_general_constraint_met_p). By
6367 doing this, we achieve better diagnostics. */
6368 if (skip_past_comma (&str
)
6369 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6371 if (!info
->shifter
.operator_present
6372 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6374 /* Default to LSL if not present. Libopcodes prefers shifter
6375 kind to be explicit. */
6376 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6377 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6381 case AARCH64_OPND_FPIMM
:
6382 case AARCH64_OPND_SIMD_FPIMM
:
6383 case AARCH64_OPND_SVE_FPIMM8
:
6388 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6389 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6390 || !aarch64_imm_float_p (qfloat
))
6393 set_fatal_syntax_error (_("invalid floating-point"
6397 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6398 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6402 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6403 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6404 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6409 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6410 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6413 set_fatal_syntax_error (_("invalid floating-point"
6417 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6418 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6422 case AARCH64_OPND_LIMM
:
6423 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6424 SHIFTED_LOGIC_IMM
));
6425 if (info
->shifter
.operator_present
)
6427 set_fatal_syntax_error
6428 (_("shift not allowed for bitmask immediate"));
6431 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6433 /* need_libopcodes_p */ 1,
6437 case AARCH64_OPND_A64C_IMM6_EXT
:
6438 po_misc_or_fail (parse_shifter_operand_imm (&str
, info
,
6439 SHIFTED_ARITH_IMM
));
6441 /* Try to coerce into shifted form if the immediate is out of
6443 if (inst
.reloc
.exp
.X_add_number
> 63 && (info
->imm
.value
& 16) == 0
6444 && (inst
.reloc
.exp
.X_add_number
>> 4) <= 64
6445 && info
->shifter
.amount
== 0)
6447 info
->shifter
.amount
= 4;
6448 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6449 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
>> 4;
6452 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6455 case AARCH64_OPND_AIMM
:
6456 case AARCH64_OPND_A64C_AIMM
:
6457 if (opcode
->op
== OP_ADD
|| opcode
->op
== OP_A64C_ADD
)
6458 /* ADD may have relocation types. */
6459 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6460 SHIFTED_ARITH_IMM
));
6462 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6463 SHIFTED_ARITH_IMM
));
6464 switch (inst
.reloc
.type
)
6466 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6467 info
->shifter
.amount
= 12;
6469 case BFD_RELOC_UNUSED
:
6470 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6471 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6472 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6473 inst
.reloc
.pc_rel
= 0;
6478 info
->imm
.value
= 0;
6479 if (!info
->shifter
.operator_present
)
6481 /* Default to LSL if not present. Libopcodes prefers shifter
6482 kind to be explicit. */
6483 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6484 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6488 case AARCH64_OPND_HALF
:
6490 /* #<imm16> or relocation. */
6491 int internal_fixup_p
;
6492 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6493 if (internal_fixup_p
)
6494 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6495 skip_whitespace (str
);
6496 if (skip_past_comma (&str
))
6498 /* {, LSL #<shift>} */
6499 if (! aarch64_gas_internal_fixup_p ())
6501 set_fatal_syntax_error (_("can't mix relocation modifier "
6502 "with explicit shift"));
6505 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6508 inst
.base
.operands
[i
].shifter
.amount
= 0;
6509 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6510 inst
.base
.operands
[i
].imm
.value
= 0;
6511 if (! process_movw_reloc_info ())
6516 case AARCH64_OPND_EXCEPTION
:
6517 case AARCH64_OPND_UNDEFINED
:
6518 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6520 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6522 /* need_libopcodes_p */ 0,
6526 case AARCH64_OPND_NZCV
:
6528 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6532 info
->imm
.value
= nzcv
->value
;
6535 po_imm_or_fail (0, 15);
6536 info
->imm
.value
= val
;
6540 case AARCH64_OPND_PERM
:
6541 po_misc_or_fail (parse_perms (&str
, info
));
6544 case AARCH64_OPND_FORM
:
6549 while (ISALPHA (*str
));
6550 info
->form
= get_form_from_str (start
, str
- start
);
6551 if (info
->form
== NULL
)
6553 set_syntax_error (_("invalid form"));
6559 case AARCH64_OPND_COND
:
6560 case AARCH64_OPND_COND1
:
6565 while (ISALPHA (*str
));
6566 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6567 if (info
->cond
== NULL
)
6569 set_syntax_error (_("invalid condition"));
6572 else if (operands
[i
] == AARCH64_OPND_COND1
6573 && (info
->cond
->value
& 0xe) == 0xe)
6575 /* Do not allow AL or NV. */
6576 set_default_error ();
6582 /* ADRP variants. Clear the value as operand needs to be
6584 case AARCH64_OPND_A64C_ADDR_ADRDP
:
6585 if (!AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
))
6587 as_bad (_("instruction not allowed on this processor"));
6590 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6592 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6594 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6595 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6596 if (info
->imm
.value
& 0xfff)
6599 info
->imm
.value
>>= 12;
6604 (_("20-bit 4K page aligned integer constant expected"));
6607 case AARCH64_OPND_ADDR_ADRP
:
6608 if (AARCH64_CPU_HAS_FEATURE (cpu_variant
, AARCH64_FEATURE_C64
))
6609 info
->imm
.value
= 1UL << 20;
6611 info
->imm
.value
= 0;
6613 po_misc_or_fail (parse_adrp (&str
));
6616 case AARCH64_OPND_ADDR_PCREL14
:
6617 case AARCH64_OPND_ADDR_PCREL17
:
6618 case AARCH64_OPND_ADDR_PCREL19
:
6619 case AARCH64_OPND_ADDR_PCREL21
:
6620 case AARCH64_OPND_ADDR_PCREL26
:
6621 po_misc_or_fail (parse_address (&str
, info
));
6622 if (!info
->addr
.pcrel
)
6624 set_syntax_error (_("invalid pc-relative address"));
6627 if (inst
.gen_lit_pool
6628 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6630 /* Only permit "=value" in the literal load instructions.
6631 The literal will be generated by programmer_friendly_fixup. */
6632 set_syntax_error (_("invalid use of \"=immediate\""));
6635 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6637 set_syntax_error (_("unrecognized relocation suffix"));
6640 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6642 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6643 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6647 bfd_boolean c64
= AARCH64_CPU_HAS_FEATURE (cpu_variant
,
6648 AARCH64_FEATURE_C64
);
6650 info
->imm
.value
= 0;
6651 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6652 switch (opcode
->iclass
)
6656 /* e.g. CBZ or B.COND */
6657 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6658 inst
.reloc
.type
= (c64
? BFD_RELOC_MORELLO_BRANCH19
6659 : BFD_RELOC_AARCH64_BRANCH19
);
6663 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6664 inst
.reloc
.type
= (c64
? BFD_RELOC_MORELLO_TSTBR14
6665 : BFD_RELOC_AARCH64_TSTBR14
);
6670 bfd_reloc_code_real_type jump
, call
;
6672 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6674 jump
= (c64
? BFD_RELOC_MORELLO_JUMP26
6675 : BFD_RELOC_AARCH64_JUMP26
);
6676 call
= (c64
? BFD_RELOC_MORELLO_CALL26
6677 : BFD_RELOC_AARCH64_CALL26
);
6679 inst
.reloc
.type
= opcode
->op
== OP_BL
? call
: jump
;
6683 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
6684 || operands
[i
] == AARCH64_OPND_ADDR_PCREL17
);
6685 inst
.reloc
.type
= (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
6686 ? BFD_RELOC_AARCH64_LD_LO19_PCREL
6687 : BFD_RELOC_MORELLO_LD_LO17_PCREL
);
6690 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6691 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6698 inst
.reloc
.flags
= FIXUP_F_C64
;
6699 inst
.reloc
.pc_rel
= 1;
6703 case AARCH64_OPND_ADDR_SIMPLE
:
6704 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6706 /* [<Xn|SP>{, #<simm>}] */
6708 /* First use the normal address-parsing routines, to get
6709 the usual syntax errors. */
6710 po_misc_or_fail (parse_address (&str
, info
));
6711 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6712 || !info
->addr
.preind
|| info
->addr
.postind
6713 || info
->addr
.writeback
)
6715 set_syntax_error (_("invalid addressing mode"));
6719 /* Then retry, matching the specific syntax of these addresses. */
6721 po_char_or_fail ('[');
6722 po_reg_or_fail (AARCH64_CPU_HAS_FEATURE (cpu_variant
,
6723 AARCH64_FEATURE_C64
)
6724 ? REG_TYPE_CA_N_SP
: REG_TYPE_R64_SP
);
6726 /* Accept optional ", #0". */
6727 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6728 && skip_past_char (&str
, ','))
6730 skip_past_char (&str
, '#');
6731 if (! skip_past_char (&str
, '0'))
6733 set_fatal_syntax_error
6734 (_("the optional immediate offset can only be 0"));
6738 po_char_or_fail (']');
6742 case AARCH64_OPND_CAPADDR_REGOFF
:
6743 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6746 case AARCH64_OPND_ADDR_REGOFF
:
6747 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6748 po_misc_or_fail (parse_address (&str
, info
));
6750 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6751 || !info
->addr
.preind
|| info
->addr
.postind
6752 || info
->addr
.writeback
)
6754 set_syntax_error (_("invalid addressing mode"));
6757 if (!info
->shifter
.operator_present
)
6759 /* Default to LSL if not present. Libopcodes prefers shifter
6760 kind to be explicit. */
6761 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6762 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6764 /* Qualifier to be deduced by libopcodes. */
6767 case AARCH64_OPND_CAPADDR_SIMPLE
:
6768 case AARCH64_OPND_CAPADDR_SIMM7
:
6770 /* A little hack to prevent the address parser from trying to
6771 pretend that a BLR with a register may be a BLR with an
6772 address. It fails the addressing mode test below, but still
6773 ends up adding a symbol with the name of the register. */
6775 po_char_or_fail ('[');
6778 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6779 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6780 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6781 || info
->addr
.writeback
)
6783 set_syntax_error (_("invalid addressing mode"));
6786 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6788 set_syntax_error (_("relocation not allowed"));
6791 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6792 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6795 set_syntax_error (_("Invalid offset constant"));
6798 if (info
->type
== AARCH64_OPND_CAPADDR_SIMPLE
6799 && info
->addr
.offset
.imm
!= 0)
6801 set_syntax_error (_("non-zero offset not allowed"));
6807 case AARCH64_OPND_A64C_ADDR_SIMM7
:
6808 case AARCH64_OPND_ADDR_SIMM7
:
6809 po_misc_or_fail (parse_address (&str
, info
));
6810 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6811 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6813 set_syntax_error (_("invalid addressing mode"));
6816 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6818 set_syntax_error (_("relocation not allowed"));
6821 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6823 /* need_libopcodes_p */ 1,
6827 case AARCH64_OPND_CAPADDR_SIMM9
:
6828 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6831 case AARCH64_OPND_A64C_ADDR_SIMM9
:
6832 case AARCH64_OPND_ADDR_SIMM9
:
6833 case AARCH64_OPND_ADDR_SIMM9_2
:
6834 case AARCH64_OPND_ADDR_SIMM11
:
6835 case AARCH64_OPND_ADDR_SIMM13
:
6836 po_misc_or_fail (parse_address (&str
, info
));
6838 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6839 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6840 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6841 && info
->addr
.writeback
))
6843 set_syntax_error (_("invalid addressing mode"));
6846 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6848 set_syntax_error (_("relocation not allowed"));
6851 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6853 /* need_libopcodes_p */ 1,
6857 case AARCH64_OPND_ADDR_SIMM10
:
6858 case AARCH64_OPND_ADDR_OFFSET
:
6859 po_misc_or_fail (parse_address (&str
, info
));
6860 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6861 || !info
->addr
.preind
|| info
->addr
.postind
)
6863 set_syntax_error (_("invalid addressing mode"));
6866 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6868 set_syntax_error (_("relocation not allowed"));
6871 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6873 /* need_libopcodes_p */ 1,
6877 case AARCH64_OPND_CAPADDR_UIMM9
:
6878 po_misc_or_fail (parse_cap_address (&str
, info
, opcode
->iclass
));
6881 case AARCH64_OPND_ADDR_UIMM12
:
6882 po_misc_or_fail (parse_address (&str
, info
));
6884 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6885 || !info
->addr
.preind
|| info
->addr
.writeback
)
6887 set_syntax_error (_("invalid addressing mode"));
6890 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6891 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6892 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6894 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6896 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6898 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6900 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6902 /* The altbase ldrb instruction does not have enough range to
6903 accommodate a LO12 relocation. */
6904 if (opcode
->flags
& F_NOSHIFT
&& opcode
->iclass
== ldst_altbase
)
6906 set_syntax_error (_("relocation not allowed"));
6910 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6912 else if ((inst
.reloc
.type
== BFD_RELOC_AARCH64_LD_GOT_LO12_NC
6913 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
)
6914 && inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_CA
)
6915 inst
.reloc
.flags
= FIXUP_F_C64
;
6917 /* Leave qualifier to be determined by libopcodes. */
6920 case AARCH64_OPND_SIMD_ADDR_POST
:
6921 /* [<Xn|SP>], <Xm|#<amount>> */
6922 po_misc_or_fail (parse_address (&str
, info
));
6923 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6925 set_syntax_error (_("invalid addressing mode"));
6928 if (!info
->addr
.offset
.is_reg
)
6930 if (inst
.reloc
.exp
.X_op
== O_constant
)
6931 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6934 set_fatal_syntax_error
6935 (_("writeback value must be an immediate constant"));
6942 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6943 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6944 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6945 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6946 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6947 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6948 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6949 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6950 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6951 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6952 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6953 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6954 /* [X<n>{, #imm, MUL VL}]
6956 but recognizing SVE registers. */
6957 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6958 &offset_qualifier
));
6959 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6961 set_syntax_error (_("invalid addressing mode"));
6965 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6966 || !info
->addr
.preind
|| info
->addr
.writeback
)
6968 set_syntax_error (_("invalid addressing mode"));
6971 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6972 || inst
.reloc
.exp
.X_op
!= O_constant
)
6974 /* Make sure this has priority over
6975 "invalid addressing mode". */
6976 set_fatal_syntax_error (_("constant offset required"));
6979 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6982 case AARCH64_OPND_SVE_ADDR_R
:
6983 /* [<Xn|SP>{, <R><m>}]
6984 but recognizing SVE registers. */
6985 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6986 &offset_qualifier
));
6987 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6989 offset_qualifier
= AARCH64_OPND_QLF_X
;
6990 info
->addr
.offset
.is_reg
= 1;
6991 info
->addr
.offset
.regno
= 31;
6993 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6994 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6996 set_syntax_error (_("invalid addressing mode"));
7001 case AARCH64_OPND_SVE_ADDR_RR
:
7002 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7003 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7004 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7005 case AARCH64_OPND_SVE_ADDR_RX
:
7006 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7007 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7008 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7009 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7010 but recognizing SVE registers. */
7011 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7012 &offset_qualifier
));
7013 if (base_qualifier
!= AARCH64_OPND_QLF_X
7014 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7016 set_syntax_error (_("invalid addressing mode"));
7021 case AARCH64_OPND_SVE_ADDR_RZ
:
7022 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7023 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7024 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7025 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7026 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7027 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7028 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7029 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7030 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7031 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7032 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7033 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7034 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7035 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7036 &offset_qualifier
));
7037 if (base_qualifier
!= AARCH64_OPND_QLF_X
7038 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7039 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7041 set_syntax_error (_("invalid addressing mode"));
7044 info
->qualifier
= offset_qualifier
;
7047 case AARCH64_OPND_SVE_ADDR_ZX
:
7048 /* [Zn.<T>{, <Xm>}]. */
7049 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7050 &offset_qualifier
));
7052 base_qualifier either S_S or S_D
7053 offset_qualifier must be X
7055 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7056 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7057 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7059 set_syntax_error (_("invalid addressing mode"));
7062 info
->qualifier
= base_qualifier
;
7063 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7064 || !info
->addr
.preind
|| info
->addr
.writeback
7065 || info
->shifter
.operator_present
!= 0)
7067 set_syntax_error (_("invalid addressing mode"));
7070 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7074 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7075 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7076 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7077 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7078 /* [Z<n>.<T>{, #imm}] */
7079 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7080 &offset_qualifier
));
7081 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7082 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7084 set_syntax_error (_("invalid addressing mode"));
7087 info
->qualifier
= base_qualifier
;
7090 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7091 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7092 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7093 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7094 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7098 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7100 here since we get better error messages by leaving it to
7101 the qualifier checking routines. */
7102 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7103 &offset_qualifier
));
7104 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7105 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7106 || offset_qualifier
!= base_qualifier
)
7108 set_syntax_error (_("invalid addressing mode"));
7111 info
->qualifier
= base_qualifier
;
7114 case AARCH64_OPND_SYSREG
:
7116 uint32_t sysreg_flags
;
7118 if ((val
= parse_sys_reg (opcode
, &str
, aarch64_sys_regs_hsh
, 1, 0,
7119 &sysreg_flags
)) == PARSE_FAIL
)
7121 set_syntax_error (_("unknown or missing system register name"));
7124 inst
.base
.operands
[i
].sysreg
.value
= val
;
7125 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7129 case AARCH64_OPND_PSTATEFIELD
:
7130 if ((val
= parse_sys_reg (opcode
, &str
, aarch64_pstatefield_hsh
, 0, 1,
7134 set_syntax_error (_("unknown or missing PSTATE field name"));
7137 inst
.base
.operands
[i
].pstatefield
= val
;
7140 case AARCH64_OPND_SYSREG_IC
:
7141 inst
.base
.operands
[i
].sysins_op
=
7142 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7145 case AARCH64_OPND_SYSREG_DC
:
7146 inst
.base
.operands
[i
].sysins_op
=
7147 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7150 case AARCH64_OPND_SYSREG_AT
:
7151 inst
.base
.operands
[i
].sysins_op
=
7152 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7155 case AARCH64_OPND_SYSREG_SR
:
7156 inst
.base
.operands
[i
].sysins_op
=
7157 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7160 case AARCH64_OPND_SYSREG_TLBI
:
7161 inst
.base
.operands
[i
].sysins_op
=
7162 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7164 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7166 set_fatal_syntax_error ( _("unknown or missing operation name"));
7171 case AARCH64_OPND_BARRIER
:
7172 case AARCH64_OPND_BARRIER_ISB
:
7173 val
= parse_barrier (&str
);
7174 if (val
!= PARSE_FAIL
7175 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7177 /* ISB only accepts options name 'sy'. */
7179 (_("the specified option is not accepted in ISB"));
7180 /* Turn off backtrack as this optional operand is present. */
7184 /* This is an extension to accept a 0..15 immediate. */
7185 if (val
== PARSE_FAIL
)
7186 po_imm_or_fail (0, 15);
7187 info
->barrier
= aarch64_barrier_options
+ val
;
7190 case AARCH64_OPND_PRFOP
:
7191 val
= parse_pldop (&str
);
7192 /* This is an extension to accept a 0..31 immediate. */
7193 if (val
== PARSE_FAIL
)
7194 po_imm_or_fail (0, 31);
7195 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7198 case AARCH64_OPND_BARRIER_PSB
:
7199 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7200 if (val
== PARSE_FAIL
)
7204 case AARCH64_OPND_BTI_TARGET
:
7205 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7206 if (val
== PARSE_FAIL
)
7211 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7214 /* If we get here, this operand was successfully parsed. */
7215 inst
.base
.operands
[i
].present
= 1;
7219 /* The parse routine should already have set the error, but in case
7220 not, set a default one here. */
7222 set_default_error ();
7224 if (! backtrack_pos
)
7225 goto parse_operands_return
;
7228 /* We reach here because this operand is marked as optional, and
7229 either no operand was supplied or the operand was supplied but it
7230 was syntactically incorrect. In the latter case we report an
7231 error. In the former case we perform a few more checks before
7232 dropping through to the code to insert the default operand. */
7234 char *tmp
= backtrack_pos
;
7235 char endchar
= END_OF_INSN
;
7237 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7239 skip_past_char (&tmp
, ',');
7241 if (*tmp
!= endchar
)
7242 /* The user has supplied an operand in the wrong format. */
7243 goto parse_operands_return
;
7245 /* Make sure there is not a comma before the optional operand.
7246 For example the fifth operand of 'sys' is optional:
7248 sys #0,c0,c0,#0, <--- wrong
7249 sys #0,c0,c0,#0 <--- correct. */
7250 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7252 set_fatal_syntax_error
7253 (_("unexpected comma before the omitted optional operand"));
7254 goto parse_operands_return
;
7258 /* Reaching here means we are dealing with an optional operand that is
7259 omitted from the assembly line. */
7260 gas_assert (optional_operand_p (opcode
, i
));
7262 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7264 /* Try again, skipping the optional operand at backtrack_pos. */
7265 str
= backtrack_pos
;
7268 /* Clear any error record after the omitted optional operand has been
7269 successfully handled. */
7273 /* Check if we have parsed all the operands. */
7274 if (*str
!= '\0' && ! error_p ())
7276 /* Set I to the index of the last present operand; this is
7277 for the purpose of diagnostics. */
7278 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7280 set_fatal_syntax_error
7281 (_("unexpected characters following instruction"));
7284 parse_operands_return
:
7288 DEBUG_TRACE ("parsing FAIL: %s - %s",
7289 operand_mismatch_kind_names
[get_error_kind ()],
7290 get_error_message ());
7291 /* Record the operand error properly; this is useful when there
7292 are multiple instruction templates for a mnemonic name, so that
7293 later on, we can select the error that most closely describes
7295 record_operand_error (opcode
, i
, get_error_kind (),
7296 get_error_message ());
7301 DEBUG_TRACE ("parsing SUCCESS");
7306 /* It does some fix-up to provide some programmer friendly feature while
7307 keeping the libopcodes happy, i.e. libopcodes only accepts
7308 the preferred architectural syntax.
7309 Return FALSE if there is any failure; otherwise return TRUE. */
7312 programmer_friendly_fixup (aarch64_instruction
*instr
)
7314 aarch64_inst
*base
= &instr
->base
;
7315 const aarch64_opcode
*opcode
= base
->opcode
;
7316 enum aarch64_op op
= opcode
->op
;
7317 aarch64_opnd_info
*operands
= base
->operands
;
7319 DEBUG_TRACE ("enter");
7321 switch (opcode
->iclass
)
7324 /* TBNZ Xn|Wn, #uimm6, label
7325 Test and Branch Not Zero: conditionally jumps to label if bit number
7326 uimm6 in register Xn is not zero. The bit number implies the width of
7327 the register, which may be written and should be disassembled as Wn if
7328 uimm is less than 32. */
7329 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7331 if (operands
[1].imm
.value
>= 32)
7333 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7337 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7341 /* LDR Wt, label | =value
7342 As a convenience assemblers will typically permit the notation
7343 "=value" in conjunction with the pc-relative literal load instructions
7344 to automatically place an immediate value or symbolic address in a
7345 nearby literal pool and generate a hidden label which references it.
7346 ISREG has been set to 0 in the case of =value. */
7347 if (instr
->gen_lit_pool
7348 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
7349 || op
== OP_LDR_LIT_2
))
7351 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7352 if (op
== OP_LDRSW_LIT
)
7354 if (instr
->reloc
.exp
.X_op
!= O_constant
7355 && instr
->reloc
.exp
.X_op
!= O_big
7356 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7358 record_operand_error (opcode
, 1,
7359 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7360 _("constant expression expected"));
7363 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7365 record_operand_error (opcode
, 1,
7366 AARCH64_OPDE_OTHER_ERROR
,
7367 _("literal pool insertion failed"));
7375 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7376 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7377 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7378 A programmer-friendly assembler should accept a destination Xd in
7379 place of Wd, however that is not the preferred form for disassembly.
7381 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7382 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7383 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7384 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7389 /* In the 64-bit form, the final register operand is written as Wm
7390 for all but the (possibly omitted) UXTX/LSL and SXTX
7392 As a programmer-friendly assembler, we accept e.g.
7393 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7394 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7395 int idx
= aarch64_operand_index (opcode
->operands
,
7396 AARCH64_OPND_Rm_EXT
);
7397 gas_assert (idx
== 1 || idx
== 2);
7398 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7399 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7400 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7401 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7402 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7403 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7411 DEBUG_TRACE ("exit with SUCCESS");
7415 /* Check for loads and stores that will cause unpredictable behavior. */
7418 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7420 aarch64_inst
*base
= &instr
->base
;
7421 const aarch64_opcode
*opcode
= base
->opcode
;
7422 const aarch64_opnd_info
*opnds
= base
->operands
;
7423 switch (opcode
->iclass
)
7430 /* Loading/storing the base register is unpredictable if writeback. */
7431 if ((aarch64_get_operand_class (opnds
[0].type
)
7432 == AARCH64_OPND_CLASS_INT_REG
)
7433 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7434 && opnds
[1].addr
.base_regno
!= REG_SP
7435 /* Exempt STG/STZG/ST2G/STZ2G. */
7436 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7437 && opnds
[1].addr
.writeback
)
7438 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7442 case ldstnapair_offs
:
7443 case ldstpair_indexed
:
7444 /* Loading/storing the base register is unpredictable if writeback. */
7445 if ((aarch64_get_operand_class (opnds
[0].type
)
7446 == AARCH64_OPND_CLASS_INT_REG
)
7447 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7448 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7449 && opnds
[2].addr
.base_regno
!= REG_SP
7451 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7452 && opnds
[2].addr
.writeback
)
7453 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7454 /* Load operations must load different registers. */
7455 if ((opcode
->opcode
& (1 << 22))
7456 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7457 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7461 /* It is unpredictable if the destination and status registers are the
7463 if ((aarch64_get_operand_class (opnds
[0].type
)
7464 == AARCH64_OPND_CLASS_INT_REG
)
7465 && (aarch64_get_operand_class (opnds
[1].type
)
7466 == AARCH64_OPND_CLASS_INT_REG
7467 || (aarch64_get_operand_class (opnds
[1].type
)
7468 == AARCH64_OPND_CLASS_CAP_REG
))
7469 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
7470 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
7471 as_warn (_("unpredictable: identical transfer and status registers"
7483 force_automatic_sequence_close (void)
7485 if (now_instr_sequence
.instr
)
7487 as_warn (_("previous `%s' sequence has not been closed"),
7488 now_instr_sequence
.instr
->opcode
->name
);
7489 init_insn_sequence (NULL
, &now_instr_sequence
);
7493 /* A wrapper function to interface with libopcodes on encoding and
7494 record the error message if there is any.
7496 Return TRUE on success; otherwise return FALSE. */
7499 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7502 aarch64_operand_error error_info
;
7503 memset (&error_info
, '\0', sizeof (error_info
));
7504 error_info
.kind
= AARCH64_OPDE_NIL
;
7505 if (aarch64_opcode_encode (cpu_variant
, opcode
, instr
, code
, NULL
,
7506 &error_info
, insn_sequence
)
7507 && !error_info
.non_fatal
)
7510 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7511 record_operand_error_info (opcode
, &error_info
);
7512 return error_info
.non_fatal
;
7515 #ifdef DEBUG_AARCH64
7517 dump_opcode_operands (const aarch64_opcode
*opcode
)
7520 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7522 aarch64_verbose ("\t\t opnd%d: %s", i
,
7523 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7524 ? aarch64_get_operand_name (opcode
->operands
[i
])
7525 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7529 #endif /* DEBUG_AARCH64 */
7531 /* This is the guts of the machine-dependent assembler. STR points to a
7532 machine dependent instruction. This function is supposed to emit
7533 the frags/bytes it assembles to. */
7536 md_assemble (char *str
)
7539 templates
*template;
7540 aarch64_opcode
*opcode
;
7541 aarch64_inst
*inst_base
;
7542 unsigned saved_cond
;
7544 /* Align the previous label if needed. */
7545 if (last_label_seen
!= NULL
)
7547 symbol_set_frag (last_label_seen
, frag_now
);
7548 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7549 S_SET_SEGMENT (last_label_seen
, now_seg
);
7552 /* Update the current insn_sequence from the segment. */
7553 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7555 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7557 DEBUG_TRACE ("\n\n");
7558 DEBUG_TRACE ("==============================");
7559 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7561 template = opcode_lookup (&p
);
7564 /* It wasn't an instruction, but it might be a register alias of
7565 the form alias .req reg directive. */
7566 if (!create_register_alias (str
, p
))
7567 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7572 skip_whitespace (p
);
7575 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7576 get_mnemonic_name (str
), str
);
7580 init_operand_error_report ();
7582 /* Sections are assumed to start aligned. In executable section, there is no
7583 MAP_DATA symbol pending. So we only align the address during
7584 MAP_DATA --> MAP_CUR_INSN transition.
7585 For other sections, this is not guaranteed. */
7586 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7587 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7588 frag_align_code (2, 0);
7590 saved_cond
= inst
.cond
;
7591 reset_aarch64_instruction (&inst
);
7592 inst
.cond
= saved_cond
;
7594 /* Iterate through all opcode entries with the same mnemonic name. */
7597 opcode
= template->opcode
;
7599 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7600 #ifdef DEBUG_AARCH64
7602 dump_opcode_operands (opcode
);
7603 #endif /* DEBUG_AARCH64 */
7605 mapping_state (MAP_CUR_INSN
);
7607 inst_base
= &inst
.base
;
7608 inst_base
->opcode
= opcode
;
7610 /* Truly conditionally executed instructions, e.g. b.cond. */
7611 if (opcode
->flags
& F_COND
)
7613 gas_assert (inst
.cond
!= COND_ALWAYS
);
7614 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7615 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7617 else if (inst
.cond
!= COND_ALWAYS
)
7619 /* It shouldn't arrive here, where the assembly looks like a
7620 conditional instruction but the found opcode is unconditional. */
7625 if (parse_operands (p
, opcode
)
7626 && programmer_friendly_fixup (&inst
)
7627 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7629 /* Check that this instruction is supported for this CPU. */
7630 if (!opcode
->avariant
7631 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7633 as_bad (_("selected processor does not support `%s'"), str
);
7637 warn_unpredictable_ldst (&inst
, str
);
7639 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7640 || !inst
.reloc
.need_libopcodes_p
)
7644 /* If there is relocation generated for the instruction,
7645 store the instruction information for the future fix-up. */
7646 struct aarch64_inst
*copy
;
7647 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7648 copy
= XNEW (struct aarch64_inst
);
7649 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7653 /* Issue non-fatal messages if any. */
7654 output_operand_error_report (str
, TRUE
);
7658 template = template->next
;
7659 if (template != NULL
)
7661 reset_aarch64_instruction (&inst
);
7662 inst
.cond
= saved_cond
;
7665 while (template != NULL
);
7667 /* Issue the error messages if any. */
7668 output_operand_error_report (str
, FALSE
);
7671 /* Various frobbings of labels and their addresses. */
7674 aarch64_start_line_hook (void)
7676 last_label_seen
= NULL
;
7680 aarch64_frob_label (symbolS
* sym
)
7682 last_label_seen
= sym
;
7684 AARCH64_SET_C64 (sym
, IS_C64
);
7685 if (AARCH64_IS_C64 (sym
) && S_IS_FUNCTION (sym
))
7687 gas_assert ((*symbol_X_add_number (sym
) & 1) == 0);
7688 *symbol_X_add_number (sym
) += 1;
7691 dwarf2_emit_label (sym
);
7695 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7697 /* Check to see if we have a block to close. */
7698 force_automatic_sequence_close ();
7702 aarch64_data_in_code (void)
7704 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7706 *input_line_pointer
= '/';
7707 input_line_pointer
+= 5;
7708 *input_line_pointer
= 0;
7716 aarch64_canonicalize_symbol_name (char *name
)
7720 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7721 *(name
+ len
- 5) = 0;
7726 /* Table of all register names defined by default. The user can
7727 define additional names with .req. Note that all register names
7728 should appear in both upper and lowercase variants. Some registers
7729 also have mixed-case names. */
7731 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7732 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7733 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7734 #define REGSET16(p,t) \
7735 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7736 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7737 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7738 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7739 #define REGSET31(p,t) \
7741 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7742 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7743 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7744 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7745 #define REGSET(p,t) \
7746 REGSET31(p,t), REGNUM(p,31,t)
7748 /* These go into aarch64_reg_hsh hash-table. */
7749 static const reg_entry reg_names
[] = {
7750 /* Integer registers. */
7751 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7752 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7754 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7755 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7756 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7757 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7758 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7759 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7761 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7762 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7764 /* Capability Registers. */
7765 REGSET31 (c
, CA_N
), REGSET31 (C
, CA_N
),
7766 REGDEF (csp
, 31, CA_SP
), REGDEF (CSP
, 31, CA_SP
),
7767 REGDEF (czr
, 31, CA_Z
), REGDEF (CZR
, 31, CA_Z
),
7768 REGDEF (ddc
, 33, CA_D
), REGDEF (DDC
, 33, CA_D
),
7769 REGDEF_ALIAS (clr
, 30, CA_N
), REGDEF_ALIAS (CLR
, 30, CA_N
),
7771 /* Floating-point single precision registers. */
7772 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7774 /* Floating-point double precision registers. */
7775 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7777 /* Floating-point half precision registers. */
7778 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7780 /* Floating-point byte precision registers. */
7781 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7783 /* Floating-point quad precision registers. */
7784 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7786 /* FP/SIMD registers. */
7787 REGSET (v
, VN
), REGSET (V
, VN
),
7789 /* SVE vector registers. */
7790 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7792 /* SVE predicate registers. */
7793 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7811 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7812 static const asm_nzcv nzcv_names
[] = {
7813 {"nzcv", B (n
, z
, c
, v
)},
7814 {"nzcV", B (n
, z
, c
, V
)},
7815 {"nzCv", B (n
, z
, C
, v
)},
7816 {"nzCV", B (n
, z
, C
, V
)},
7817 {"nZcv", B (n
, Z
, c
, v
)},
7818 {"nZcV", B (n
, Z
, c
, V
)},
7819 {"nZCv", B (n
, Z
, C
, v
)},
7820 {"nZCV", B (n
, Z
, C
, V
)},
7821 {"Nzcv", B (N
, z
, c
, v
)},
7822 {"NzcV", B (N
, z
, c
, V
)},
7823 {"NzCv", B (N
, z
, C
, v
)},
7824 {"NzCV", B (N
, z
, C
, V
)},
7825 {"NZcv", B (N
, Z
, c
, v
)},
7826 {"NZcV", B (N
, Z
, c
, V
)},
7827 {"NZCv", B (N
, Z
, C
, v
)},
7828 {"NZCV", B (N
, Z
, C
, V
)}
7841 /* MD interface: bits in the object file. */
7843 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7844 for use in the a.out file, and stores them in the array pointed to by buf.
7845 This knows about the endian-ness of the target machine and does
7846 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7847 2 (short) and 4 (long) Floating numbers are put out as a series of
7848 LITTLENUMS (shorts, here at least). */
7851 md_number_to_chars (char *buf
, valueT val
, int n
)
7853 if (target_big_endian
)
7854 number_to_chars_bigendian (buf
, val
, n
);
7856 number_to_chars_littleendian (buf
, val
, n
);
7859 /* MD interface: Sections. */
7861 /* Estimate the size of a frag before relaxing. Assume everything fits in
7865 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7871 /* Round up a section size to the appropriate boundary. */
7874 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7879 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7880 of an rs_align_code fragment.
7882 Here we fill the frag with the appropriate info for padding the
7883 output stream. The resulting frag will consist of a fixed (fr_fix)
7884 and of a repeating (fr_var) part.
7886 The fixed content is always emitted before the repeating content and
7887 these two parts are used as follows in constructing the output:
7888 - the fixed part will be used to align to a valid instruction word
7889 boundary, in case that we start at a misaligned address; as no
7890 executable instruction can live at the misaligned location, we
7891 simply fill with zeros;
7892 - the variable part will be used to cover the remaining padding and
7893 we fill using the AArch64 NOP instruction.
7895 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7896 enough storage space for up to 3 bytes for padding the back to a valid
7897 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7900 aarch64_handle_align (fragS
* fragP
)
7902 /* NOP = d503201f */
7903 /* AArch64 instructions are always little-endian. */
7904 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7906 int bytes
, fix
, noop_size
;
7909 if (fragP
->fr_type
!= rs_align_code
)
7912 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7913 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7916 gas_assert (fragP
->tc_frag_data
.recorded
);
7919 noop_size
= sizeof (aarch64_noop
);
7921 fix
= bytes
& (noop_size
- 1);
7925 insert_data_mapping_symbol (MAP_CUR_INSN
, fragP
->fr_fix
, fragP
, fix
);
7929 fragP
->fr_fix
+= fix
;
7933 memcpy (p
, aarch64_noop
, noop_size
);
7934 fragP
->fr_var
= noop_size
;
7937 /* Perform target specific initialisation of a frag.
7938 Note - despite the name this initialisation is not done when the frag
7939 is created, but only when its type is assigned. A frag can be created
7940 and used a long time before its type is set, so beware of assuming that
7941 this initialisation is performed first. */
7945 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7946 int max_chars ATTRIBUTE_UNUSED
)
7950 #else /* OBJ_ELF is defined. */
7952 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7954 /* Record a mapping symbol for alignment frags. We will delete this
7955 later if the alignment ends up empty. */
7956 if (!fragP
->tc_frag_data
.recorded
)
7957 fragP
->tc_frag_data
.recorded
= 1;
7959 /* PR 21809: Do not set a mapping state for debug sections
7960 - it just confuses other tools. */
7961 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7964 switch (fragP
->fr_type
)
7968 mapping_state_2 (MAP_DATA
, max_chars
);
7971 /* PR 20364: We can get alignment frags in code sections,
7972 so do not just assume that we should use the MAP_DATA state. */
7973 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_CUR_INSN
: MAP_DATA
, max_chars
);
7976 mapping_state_2 (MAP_CUR_INSN
, max_chars
);
7983 /* Initialize the DWARF-2 unwind information for this procedure. */
7986 tc_aarch64_frame_initial_instructions (void)
7990 cfi_set_return_column (REG_DW_CLR
);
7991 cfi_add_CFA_def_cfa (REG_DW_CSP
, 0);
7994 cfi_add_CFA_def_cfa (REG_SP
, 0);
7998 /* The extra initialisation steps needed by AArch64 in alloc_fde_entry.
7999 Currently only used to initialise the key used to sign the return
8002 tc_aarch64_fde_entry_init_extra(struct fde_entry
*fde
)
8004 fde
->entry_extras
.pauth_key
= AARCH64_PAUTH_KEY_A
;
8005 fde
->entry_extras
.c64
= IS_C64
;
8009 tc_aarch64_cfi_startproc_exp (const char *arg
)
8011 /* Allow purecap only for C64 functions. */
8012 if (!strcmp ("purecap", arg
) && IS_C64
)
8018 #endif /* OBJ_ELF */
8020 /* Convert REGNAME to a DWARF-2 register number. */
8023 tc_aarch64_regname_to_dw2regnum (char *regname
)
8025 const reg_entry
*reg
= parse_reg (®name
);
8031 case REG_TYPE_SP_32
:
8032 case REG_TYPE_SP_64
:
8042 return reg
->number
+ 64;
8045 case REG_TYPE_CA_SP
:
8047 return reg
->number
+ 198;
8055 /* Implement DWARF2_ADDR_SIZE. */
8058 aarch64_dwarf2_addr_size (void)
8060 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8064 return bfd_arch_bits_per_address (stdoutput
) / 8;
8067 /* MD interface: Symbol and relocation handling. */
8069 /* Return the address within the segment that a PC-relative fixup is
8070 relative to. For AArch64 PC-relative fixups applied to instructions
8071 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8074 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8076 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8078 /* If this is pc-relative and we are going to emit a relocation
8079 then we just want to put out any pipeline compensation that the linker
8080 will need. Otherwise we want to use the calculated base. */
8082 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8083 || aarch64_force_relocation (fixP
)))
8086 /* AArch64 should be consistent for all pc-relative relocations. */
8087 return base
+ AARCH64_PCREL_OFFSET
;
8090 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8091 Otherwise we have no need to default values of symbols. */
8094 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8097 if (name
[0] == '_' && name
[1] == 'G'
8098 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8102 if (symbol_find (name
))
8103 as_bad (_("GOT already in the symbol table"));
8105 GOT_symbol
= symbol_new (name
, undefined_section
,
8106 &zero_address_frag
, 0);
8116 /* Return non-zero if the indicated VALUE has overflowed the maximum
8117 range expressible by a unsigned number with the indicated number of
8121 unsigned_overflow (valueT value
, unsigned bits
)
8124 if (bits
>= sizeof (valueT
) * 8)
8126 lim
= (valueT
) 1 << bits
;
8127 return (value
>= lim
);
8131 /* Return non-zero if the indicated VALUE has overflowed the maximum
8132 range expressible by an signed number with the indicated number of
8136 signed_overflow (offsetT value
, unsigned bits
)
8139 if (bits
>= sizeof (offsetT
) * 8)
8141 lim
= (offsetT
) 1 << (bits
- 1);
8142 return (value
< -lim
|| value
>= lim
);
8145 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8146 unsigned immediate offset load/store instruction, try to encode it as
8147 an unscaled, 9-bit, signed immediate offset load/store instruction.
8148 Return TRUE if it is successful; otherwise return FALSE.
8150 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8151 in response to the standard LDR/STR mnemonics when the immediate offset is
8152 unambiguous, i.e. when it is negative or unaligned. */
8155 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8158 enum aarch64_op new_op
;
8159 const aarch64_opcode
*new_opcode
;
8160 enum aarch64_opnd target
;
8162 gas_assert (instr
->opcode
->iclass
== ldst_pos
8163 || instr
->opcode
->iclass
== ldst_altbase
);
8165 target
= (instr
->opcode
->iclass
== ldst_pos
? AARCH64_OPND_ADDR_SIMM9
8166 : AARCH64_OPND_CAPADDR_SIMM9
);
8168 switch (instr
->opcode
->op
)
8170 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8171 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8172 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8173 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8174 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8175 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8176 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8177 case OP_STR_POS
: new_op
= OP_STUR
; break;
8178 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8179 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8180 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8181 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8182 case OP_LDR_POS_C
: new_op
= OP_LDUR_C
; break;
8183 case OP_STR_POS_C
: new_op
= OP_STUR_C
; break;
8184 case OP_LDRB_POS_A
:new_op
= OP_LDURB_A
; break;
8185 case OP_STRB_POS_A
: new_op
= OP_STURB_A
; break;
8186 case OP_LDR_POS_AC
: new_op
= OP_LDUR_AC
; break;
8187 case OP_LDR_POS_AX
: new_op
= OP_LDUR_AX
; break;
8188 case OP_STR_POS_AC
: new_op
= OP_STUR_AC
; break;
8189 case OP_STR_POS_AX
: new_op
= OP_STUR_AX
; break;
8190 default: new_op
= OP_NIL
; break;
8193 if (new_op
== OP_NIL
)
8196 new_opcode
= aarch64_get_opcode (new_op
);
8197 gas_assert (new_opcode
!= NULL
);
8199 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8200 instr
->opcode
->op
, new_opcode
->op
);
8202 aarch64_replace_opcode (instr
, new_opcode
);
8204 /* Clear up the address operand's qualifier; otherwise the
8205 qualifier matching may fail because the out-of-date qualifier will
8206 prevent the operand being updated with a new and correct qualifier. */
8207 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8209 gas_assert (idx
== 1);
8210 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8212 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8214 if (!aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
, &instr
->value
,
8215 NULL
, NULL
, insn_sequence
))
8221 /* Called by fix_insn to fix a MOV immediate alias instruction.
8223 Operand for a generic move immediate instruction, which is an alias
8224 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8225 a 32-bit/64-bit immediate value into general register. An assembler error
8226 shall result if the immediate cannot be created by a single one of these
8227 instructions. If there is a choice, then to ensure reversability an
8228 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8231 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8233 const aarch64_opcode
*opcode
;
8235 /* Need to check if the destination is SP/ZR. The check has to be done
8236 before any aarch64_replace_opcode. */
8237 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8238 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8240 instr
->operands
[1].imm
.value
= value
;
8241 instr
->operands
[1].skip
= 0;
8245 /* Try the MOVZ alias. */
8246 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8247 aarch64_replace_opcode (instr
, opcode
);
8248 if (aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
,
8249 &instr
->value
, NULL
, NULL
, insn_sequence
))
8251 put_aarch64_insn (buf
, instr
->value
);
8254 /* Try the MOVK alias. */
8255 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8256 aarch64_replace_opcode (instr
, opcode
);
8257 if (aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
,
8258 &instr
->value
, NULL
, NULL
, insn_sequence
))
8260 put_aarch64_insn (buf
, instr
->value
);
8265 if (try_mov_bitmask_p
)
8267 /* Try the ORR alias. */
8268 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8269 aarch64_replace_opcode (instr
, opcode
);
8270 if (aarch64_opcode_encode (cpu_variant
, instr
->opcode
, instr
,
8271 &instr
->value
, NULL
, NULL
, insn_sequence
))
8273 put_aarch64_insn (buf
, instr
->value
);
8278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8279 _("immediate cannot be moved by a single instruction"));
8282 /* An instruction operand which is immediate related may have symbol used
8283 in the assembly, e.g.
8286 .set u32, 0x00ffff00
8288 At the time when the assembly instruction is parsed, a referenced symbol,
8289 like 'u32' in the above example may not have been seen; a fixS is created
8290 in such a case and is handled here after symbols have been resolved.
8291 Instruction is fixed up with VALUE using the information in *FIXP plus
8292 extra information in FLAGS.
8294 This function is called by md_apply_fix to fix up instructions that need
8295 a fix-up described above but does not involve any linker-time relocation. */
8298 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8302 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8303 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8304 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8308 /* Now the instruction is about to be fixed-up, so the operand that
8309 was previously marked as 'ignored' needs to be unmarked in order
8310 to get the encoding done properly. */
8311 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8312 new_inst
->operands
[idx
].skip
= 0;
8315 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8319 case AARCH64_OPND_EXCEPTION
:
8320 case AARCH64_OPND_UNDEFINED
:
8321 if (unsigned_overflow (value
, 16))
8322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8323 _("immediate out of range"));
8324 insn
= get_aarch64_insn (buf
);
8325 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8326 put_aarch64_insn (buf
, insn
);
8329 case AARCH64_OPND_AIMM
:
8330 case AARCH64_OPND_A64C_AIMM
:
8331 /* ADD or SUB with immediate.
8332 NOTE this assumes we come here with a add/sub shifted reg encoding
8333 3 322|2222|2 2 2 21111 111111
8334 1 098|7654|3 2 1 09876 543210 98765 43210
8335 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8336 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8337 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8338 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8340 3 322|2222|2 2 221111111111
8341 1 098|7654|3 2 109876543210 98765 43210
8342 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8343 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8344 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8345 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8346 Fields sf Rn Rd are already set. */
8347 insn
= get_aarch64_insn (buf
);
8351 insn
= reencode_addsub_switch_add_sub (insn
);
8355 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8356 && unsigned_overflow (value
, 12))
8358 /* Try to shift the value by 12 to make it fit. */
8359 if (((value
>> 12) << 12) == value
8360 && ! unsigned_overflow (value
, 12 + 12))
8363 insn
|= encode_addsub_imm_shift_amount (1);
8367 if (unsigned_overflow (value
, 12))
8368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8369 _("immediate out of range"));
8371 insn
|= encode_addsub_imm (value
);
8373 put_aarch64_insn (buf
, insn
);
8376 case AARCH64_OPND_SIMD_IMM
:
8377 case AARCH64_OPND_SIMD_IMM_SFT
:
8378 case AARCH64_OPND_LIMM
:
8379 /* Bit mask immediate. */
8380 gas_assert (new_inst
!= NULL
);
8381 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8382 new_inst
->operands
[idx
].imm
.value
= value
;
8383 if (aarch64_opcode_encode (cpu_variant
, new_inst
->opcode
, new_inst
,
8384 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8385 put_aarch64_insn (buf
, new_inst
->value
);
8387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8388 _("invalid immediate"));
8391 case AARCH64_OPND_HALF
:
8392 /* 16-bit unsigned immediate. */
8393 if (unsigned_overflow (value
, 16))
8394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8395 _("immediate out of range"));
8396 insn
= get_aarch64_insn (buf
);
8397 insn
|= encode_movw_imm (value
& 0xffff);
8398 put_aarch64_insn (buf
, insn
);
8401 case AARCH64_OPND_IMM_MOV
:
8402 /* Operand for a generic move immediate instruction, which is
8403 an alias instruction that generates a single MOVZ, MOVN or ORR
8404 instruction to loads a 32-bit/64-bit immediate value into general
8405 register. An assembler error shall result if the immediate cannot be
8406 created by a single one of these instructions. If there is a choice,
8407 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8408 and MOVZ or MOVN to ORR. */
8409 gas_assert (new_inst
!= NULL
);
8410 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8413 case AARCH64_OPND_CAPADDR_UIMM9
:
8414 case AARCH64_OPND_A64C_ADDR_SIMM9
:
8415 case AARCH64_OPND_A64C_ADDR_SIMM7
:
8416 case AARCH64_OPND_ADDR_SIMM7
:
8417 case AARCH64_OPND_ADDR_SIMM9
:
8418 case AARCH64_OPND_ADDR_SIMM9_2
:
8419 case AARCH64_OPND_ADDR_SIMM10
:
8420 case AARCH64_OPND_ADDR_UIMM12
:
8421 case AARCH64_OPND_ADDR_SIMM11
:
8422 case AARCH64_OPND_ADDR_SIMM13
:
8423 /* Immediate offset in an address. */
8424 insn
= get_aarch64_insn (buf
);
8426 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8427 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8428 || new_inst
->opcode
->operands
[2] == opnd
);
8430 /* Get the index of the address operand. */
8431 if (new_inst
->opcode
->operands
[1] == opnd
)
8432 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8435 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8438 /* Update the resolved offset value. */
8439 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8441 /* Encode/fix-up. */
8442 if (aarch64_opcode_encode (cpu_variant
, new_inst
->opcode
, new_inst
,
8443 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8445 put_aarch64_insn (buf
, new_inst
->value
);
8448 else if ((new_inst
->opcode
->iclass
== ldst_pos
8449 || new_inst
->opcode
->iclass
== ldst_altbase
)
8450 && try_to_encode_as_unscaled_ldst (new_inst
))
8452 put_aarch64_insn (buf
, new_inst
->value
);
8456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8457 _("immediate offset out of range"));
8462 as_fatal (_("unhandled operand code %d"), opnd
);
8466 /* Apply a fixup (fixP) to segment data, once it has been determined
8467 by our caller that we have all the info we need to fix it up.
8469 Parameter valP is the pointer to the value of the bits. */
8472 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8474 offsetT value
= *valP
;
8476 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8478 unsigned flags
= fixP
->fx_addnumber
;
8479 /* We check alignment for relocations of this kind. These relocations could
8480 be applied on a C64 STT_FUNC symbol and hence may have the LSB set on
8481 `*valP`, their AARCH64 counterparts can not be applied on such symbols and
8482 hence should never have the LSB set on their value. */
8483 valueT alignment_mask
= (fixP
->fx_r_type
== BFD_RELOC_MORELLO_BRANCH19
8484 || fixP
->fx_r_type
== BFD_RELOC_MORELLO_TSTBR14
8485 || fixP
->fx_r_type
== BFD_RELOC_MORELLO_CALL26
8486 || fixP
->fx_r_type
== BFD_RELOC_MORELLO_JUMP26
)
8489 DEBUG_TRACE ("\n\n");
8490 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8491 DEBUG_TRACE ("Enter md_apply_fix");
8493 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8495 /* Note whether this will delete the relocation. */
8497 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8500 /* Process the relocations. */
8501 switch (fixP
->fx_r_type
)
8503 case BFD_RELOC_NONE
:
8504 /* This will need to go in the object file. */
8509 case BFD_RELOC_8_PCREL
:
8510 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8511 md_number_to_chars (buf
, value
, 1);
8515 case BFD_RELOC_16_PCREL
:
8516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8517 md_number_to_chars (buf
, value
, 2);
8521 case BFD_RELOC_32_PCREL
:
8522 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8523 md_number_to_chars (buf
, value
, 4);
8527 case BFD_RELOC_64_PCREL
:
8528 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8529 md_number_to_chars (buf
, value
, 8);
8532 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8533 /* We claim that these fixups have been processed here, even if
8534 in fact we generate an error because we do not have a reloc
8535 for them, so tc_gen_reloc() will reject them. */
8537 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8540 _("undefined symbol %s used as an immediate value"),
8541 S_GET_NAME (fixP
->fx_addsy
));
8542 goto apply_fix_return
;
8544 fix_insn (fixP
, flags
, value
);
8547 case BFD_RELOC_MORELLO_LD_LO17_PCREL
:
8548 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8550 /* The LDR-immediate that uses LO17 aligns the address down to
8551 16-byte boundary to get the final address of the capability.
8552 Since the fixed up immediate also needs to be 16-byte aligned,
8553 align it up to the 16-byte boundary so that the downward alignment
8554 of the load literal instruction gets us the correct address. */
8555 value
= (value
+ 0xf) & ~(offsetT
) 0xf;
8557 if (signed_overflow (value
, 21))
8558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8559 _("pcc-relative load offset out of range"));
8560 insn
= get_aarch64_insn (buf
);
8561 insn
|= encode_ld_lit_ofs_17 (value
>> 4);
8562 put_aarch64_insn (buf
, insn
);
8566 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8567 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8571 _("pc-relative load offset not word aligned"));
8572 if (signed_overflow (value
, 21))
8573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8574 _("pc-relative load offset out of range"));
8575 insn
= get_aarch64_insn (buf
);
8576 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8577 put_aarch64_insn (buf
, insn
);
8581 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8582 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8584 if (signed_overflow (value
, 21))
8585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8586 _("pc-relative address offset out of range"));
8587 insn
= get_aarch64_insn (buf
);
8588 insn
|= encode_adr_imm (value
);
8589 put_aarch64_insn (buf
, insn
);
8593 case BFD_RELOC_AARCH64_BRANCH19
:
8594 case BFD_RELOC_MORELLO_BRANCH19
:
8595 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8597 if (value
& alignment_mask
)
8598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8599 _("conditional branch target not word aligned"));
8600 if (signed_overflow (value
, 21))
8601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8602 _("conditional branch out of range"));
8603 insn
= get_aarch64_insn (buf
);
8604 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8605 put_aarch64_insn (buf
, insn
);
8609 case BFD_RELOC_MORELLO_TSTBR14
:
8610 case BFD_RELOC_AARCH64_TSTBR14
:
8611 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8613 if (value
& alignment_mask
)
8614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8615 _("conditional branch target not word aligned"));
8616 if (signed_overflow (value
, 16))
8617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8618 _("conditional branch out of range"));
8619 insn
= get_aarch64_insn (buf
);
8620 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8621 put_aarch64_insn (buf
, insn
);
8625 case BFD_RELOC_MORELLO_CALL26
:
8626 case BFD_RELOC_MORELLO_JUMP26
:
8627 case BFD_RELOC_AARCH64_CALL26
:
8628 case BFD_RELOC_AARCH64_JUMP26
:
8629 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8631 if (value
& alignment_mask
)
8632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8633 _("branch target not word aligned"));
8634 if (signed_overflow (value
, 28))
8635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8636 _("branch out of range"));
8637 insn
= get_aarch64_insn (buf
);
8638 insn
|= encode_branch_ofs_26 (value
>> 2);
8639 put_aarch64_insn (buf
, insn
);
8643 case BFD_RELOC_AARCH64_MOVW_G0
:
8644 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8645 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8646 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8647 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8648 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8651 case BFD_RELOC_AARCH64_MOVW_G1
:
8652 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8653 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8654 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8655 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8656 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8659 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8661 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8662 /* Should always be exported to object file, see
8663 aarch64_force_relocation(). */
8664 gas_assert (!fixP
->fx_done
);
8665 gas_assert (seg
->use_rela_p
);
8667 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8669 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8670 /* Should always be exported to object file, see
8671 aarch64_force_relocation(). */
8672 gas_assert (!fixP
->fx_done
);
8673 gas_assert (seg
->use_rela_p
);
8675 case BFD_RELOC_AARCH64_MOVW_G2
:
8676 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8677 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8678 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8679 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8682 case BFD_RELOC_AARCH64_MOVW_G3
:
8683 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8686 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8688 insn
= get_aarch64_insn (buf
);
8692 /* REL signed addend must fit in 16 bits */
8693 if (signed_overflow (value
, 16))
8694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8695 _("offset out of range"));
8699 /* Check for overflow and scale. */
8700 switch (fixP
->fx_r_type
)
8702 case BFD_RELOC_AARCH64_MOVW_G0
:
8703 case BFD_RELOC_AARCH64_MOVW_G1
:
8704 case BFD_RELOC_AARCH64_MOVW_G2
:
8705 case BFD_RELOC_AARCH64_MOVW_G3
:
8706 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8707 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8708 if (unsigned_overflow (value
, scale
+ 16))
8709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8710 _("unsigned value out of range"));
8712 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8713 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8714 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8715 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8716 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8717 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8718 /* NOTE: We can only come here with movz or movn. */
8719 if (signed_overflow (value
, scale
+ 16))
8720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8721 _("signed value out of range"));
8724 /* Force use of MOVN. */
8726 insn
= reencode_movzn_to_movn (insn
);
8730 /* Force use of MOVZ. */
8731 insn
= reencode_movzn_to_movz (insn
);
8735 /* Unchecked relocations. */
8741 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8742 insn
|= encode_movw_imm (value
& 0xffff);
8744 put_aarch64_insn (buf
, insn
);
8748 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8749 fixP
->fx_r_type
= (ilp32_p
8750 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8751 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8752 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8753 /* Should always be exported to object file, see
8754 aarch64_force_relocation(). */
8755 gas_assert (!fixP
->fx_done
);
8756 gas_assert (seg
->use_rela_p
);
8759 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8760 if (fixP
->tc_fix_data
.c64
)
8761 fixP
->fx_r_type
= BFD_RELOC_MORELLO_TLSDESC_LD128_LO12
;
8763 fixP
->fx_r_type
= BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
;
8765 fixP
->fx_r_type
= BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
;
8766 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8767 /* Should always be exported to object file, see
8768 aarch64_force_relocation(). */
8769 gas_assert (!fixP
->fx_done
);
8770 gas_assert (seg
->use_rela_p
);
8773 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8774 case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20
:
8775 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8776 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8777 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8778 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8779 case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12
:
8780 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8781 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8782 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8783 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8784 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8785 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8786 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8787 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8788 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8789 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8790 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8791 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8792 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8793 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8794 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8795 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8796 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8797 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8798 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8799 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8800 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8801 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8802 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8803 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8804 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8805 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8806 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8807 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8808 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8809 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8810 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8811 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8812 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8813 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8814 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8815 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8816 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8817 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8818 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8819 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8820 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8821 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8822 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8823 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8824 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8825 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8826 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8827 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8828 /* Should always be exported to object file, see
8829 aarch64_force_relocation(). */
8830 gas_assert (!fixP
->fx_done
);
8831 gas_assert (seg
->use_rela_p
);
8834 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8835 /* Should always be exported to object file, see
8836 aarch64_force_relocation(). */
8837 if (fixP
->tc_fix_data
.c64
)
8838 fixP
->fx_r_type
= BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
;
8840 fixP
->fx_r_type
= BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
;
8842 fixP
->fx_r_type
= BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
;
8843 gas_assert (!fixP
->fx_done
);
8844 gas_assert (seg
->use_rela_p
);
8847 case BFD_RELOC_AARCH64_ADD_LO12
:
8848 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8849 case BFD_RELOC_MORELLO_ADR_GOT_PAGE
:
8850 case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
:
8851 case BFD_RELOC_MORELLO_ADR_HI20_PCREL
:
8852 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8853 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8854 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8855 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8856 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8857 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8858 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8859 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8860 case BFD_RELOC_AARCH64_LDST128_LO12
:
8861 case BFD_RELOC_AARCH64_LDST16_LO12
:
8862 case BFD_RELOC_AARCH64_LDST32_LO12
:
8863 case BFD_RELOC_AARCH64_LDST64_LO12
:
8864 case BFD_RELOC_AARCH64_LDST8_LO12
:
8865 case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
:
8866 /* Should always be exported to object file, see
8867 aarch64_force_relocation(). */
8868 gas_assert (!fixP
->fx_done
);
8869 gas_assert (seg
->use_rela_p
);
8872 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8873 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8874 case BFD_RELOC_MORELLO_TLSDESC_CALL
:
8875 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8876 case BFD_RELOC_MORELLO_CAPINIT
:
8879 case BFD_RELOC_UNUSED
:
8880 /* An error will already have been reported. */
8884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8885 _("unexpected %s fixup"),
8886 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8891 /* Free the allocated the struct aarch64_inst.
8892 N.B. currently there are very limited number of fix-up types actually use
8893 this field, so the impact on the performance should be minimal . */
8894 free (fixP
->tc_fix_data
.inst
);
8899 /* Translate internal representation of relocation info to BFD target
8903 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8906 bfd_reloc_code_real_type code
;
8908 reloc
= XNEW (arelent
);
8910 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8911 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8912 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8916 if (section
->use_rela_p
)
8917 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8919 fixp
->fx_offset
= reloc
->address
;
8921 reloc
->addend
= fixp
->fx_offset
;
8923 code
= fixp
->fx_r_type
;
8928 code
= BFD_RELOC_16_PCREL
;
8933 code
= BFD_RELOC_32_PCREL
;
8938 code
= BFD_RELOC_64_PCREL
;
8945 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8946 if (reloc
->howto
== NULL
)
8948 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8950 ("cannot represent %s relocation in this object file format"),
8951 bfd_get_reloc_code_name (code
));
8958 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8961 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8963 bfd_reloc_code_real_type type
;
8967 FIXME: @@ Should look at CPU word size. */
8974 type
= BFD_RELOC_16
;
8977 type
= BFD_RELOC_32
;
8980 type
= BFD_RELOC_64
;
8983 as_bad (_("cannot do %u-byte relocation"), size
);
8984 type
= BFD_RELOC_UNUSED
;
8988 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8992 aarch64_force_relocation (struct fix
*fixp
)
8994 switch (fixp
->fx_r_type
)
8996 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8997 /* Perform these "immediate" internal relocations
8998 even if the symbol is extern or weak. */
9001 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9002 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9003 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9004 /* Pseudo relocs that need to be fixed up according to
9008 case BFD_RELOC_AARCH64_ADD_LO12
:
9009 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9010 case BFD_RELOC_MORELLO_ADR_GOT_PAGE
:
9011 case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
:
9012 case BFD_RELOC_MORELLO_ADR_HI20_PCREL
:
9013 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9014 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9015 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9016 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9017 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9018 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9019 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9020 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9021 case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC
:
9022 case BFD_RELOC_AARCH64_LDST128_LO12
:
9023 case BFD_RELOC_AARCH64_LDST16_LO12
:
9024 case BFD_RELOC_AARCH64_LDST32_LO12
:
9025 case BFD_RELOC_AARCH64_LDST64_LO12
:
9026 case BFD_RELOC_AARCH64_LDST8_LO12
:
9027 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9028 case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20
:
9029 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9030 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9031 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9032 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9033 case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12
:
9034 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9035 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9036 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9037 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9038 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9039 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9040 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9041 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9042 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9043 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9044 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9045 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9046 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9047 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9048 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9049 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9050 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9051 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9052 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9053 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9054 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9055 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9056 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9057 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9058 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9059 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9060 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9061 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9062 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9063 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9064 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9065 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9066 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9067 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9068 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9069 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9070 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9071 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9072 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9073 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9074 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9075 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9076 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9077 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9078 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9079 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9080 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9081 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9082 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9083 /* Always leave these relocations for the linker. */
9086 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9087 case BFD_RELOC_MORELLO_BRANCH19
:
9088 case BFD_RELOC_MORELLO_TSTBR14
:
9089 case BFD_RELOC_AARCH64_BRANCH19
:
9090 case BFD_RELOC_AARCH64_TSTBR14
:
9091 case BFD_RELOC_MORELLO_CALL26
:
9092 case BFD_RELOC_MORELLO_JUMP26
:
9093 case BFD_RELOC_AARCH64_CALL26
:
9094 case BFD_RELOC_AARCH64_JUMP26
:
9095 gas_assert (fixp
->fx_addsy
!= NULL
);
9097 /* A jump/call destination will get adjusted to section+offset only
9098 if both caller and callee are of the same type. */
9099 if (symbol_section_p (fixp
->fx_addsy
))
9102 if ((fixp
->tc_fix_data
.c64
9103 && !AARCH64_IS_C64 (fixp
->fx_addsy
))
9104 || (!fixp
->tc_fix_data
.c64
9105 && AARCH64_IS_C64 (fixp
->fx_addsy
)))
9114 return generic_force_reloc (fixp
);
9119 /* Implement md_after_parse_args. This is the earliest time we need to decide
9120 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9123 aarch64_after_parse_args (void)
9125 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9128 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9129 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9130 aarch64_abi
= AARCH64_ABI_ILP32
;
9132 aarch64_abi
= AARCH64_ABI_LP64
;
9136 elf64_aarch64_target_format (void)
9139 /* FIXME: What to do for ilp32_p ? */
9140 if (target_big_endian
)
9141 return "elf64-bigaarch64-cloudabi";
9143 return "elf64-littleaarch64-cloudabi";
9145 if (target_big_endian
)
9146 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9148 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9153 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9155 elf_frob_symbol (symp
, puntp
);
9159 /* MD interface: Finalization. */
9161 /* A good place to do this, although this was probably not intended
9162 for this kind of use. We need to dump the literal pool before
9163 references are made to a null symbol pointer. */
9166 aarch64_cleanup (void)
9170 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9172 /* Put it at the end of the relevant section. */
9173 subseg_set (pool
->section
, pool
->sub_section
);
9179 /* Remove any excess mapping symbols generated for alignment frags in
9180 SEC. We may have created a mapping symbol before a zero byte
9181 alignment; remove it if there's a mapping symbol after the
9184 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9185 void *dummy ATTRIBUTE_UNUSED
)
9187 segment_info_type
*seginfo
= seg_info (sec
);
9190 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9193 for (fragp
= seginfo
->frchainP
->frch_root
;
9194 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9196 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9197 fragS
*next
= fragp
->fr_next
;
9199 /* Variable-sized frags have been converted to fixed size by
9200 this point. But if this was variable-sized to start with,
9201 there will be a fixed-size frag after it. So don't handle
9203 if (sym
== NULL
|| next
== NULL
)
9206 if (S_GET_VALUE (sym
) < next
->fr_address
)
9207 /* Not at the end of this frag. */
9209 know (S_GET_VALUE (sym
) == next
->fr_address
);
9213 if (next
->tc_frag_data
.first_map
!= NULL
)
9215 /* Next frag starts with a mapping symbol. Discard this
9217 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9221 if (next
->fr_next
== NULL
)
9223 /* This mapping symbol is at the end of the section. Discard
9225 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9226 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9230 /* As long as we have empty frags without any mapping symbols,
9232 /* If the next frag is non-empty and does not start with a
9233 mapping symbol, then this mapping symbol is required. */
9234 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9237 next
= next
->fr_next
;
9239 while (next
!= NULL
);
9244 /* Avoid relocations from using section symbols in some cases. */
9246 aarch64_fix_adjustable (struct fix
*fixP
)
9248 /* We need size information of the target symbols to initialise
9250 if (fixP
->fx_r_type
== BFD_RELOC_MORELLO_CAPINIT
)
9253 switch (fixP
->fx_r_type
)
9255 /* We need to retain symbol information when jumping between A64 and C64
9256 states or between two C64 functions. In the C64 -> C64 situation it's
9257 really only a corner case that breaks when symbols get replaced with
9258 section symbols; this is when the jump distance is longer than what a
9259 branch instruction can handle and we want to branch through a stub.
9260 In such a case, the linker needs to know the symbol types of the
9261 source and the destination and section symbols are an unreliable
9262 source of this information. */
9263 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9264 case BFD_RELOC_AARCH64_ADD_LO12
:
9265 case BFD_RELOC_AARCH64_BRANCH19
:
9266 case BFD_RELOC_AARCH64_TSTBR14
:
9267 case BFD_RELOC_AARCH64_JUMP26
:
9268 case BFD_RELOC_AARCH64_CALL26
:
9269 case BFD_RELOC_MORELLO_BRANCH19
:
9270 case BFD_RELOC_MORELLO_TSTBR14
:
9271 case BFD_RELOC_MORELLO_JUMP26
:
9272 case BFD_RELOC_MORELLO_CALL26
:
9273 if (fixP
->tc_fix_data
.c64
|| AARCH64_IS_C64 (fixP
->fx_addsy
))
9283 /* Adjust the symbol table. */
9286 aarch64_adjust_symtab (void)
9291 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
9293 if (AARCH64_IS_C64 (sym
)
9294 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
))
9296 elf_symbol_type
* elf_sym
;
9298 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
9300 if (!bfd_is_aarch64_special_symbol_name
9301 (elf_sym
->symbol
.name
, BFD_AARCH64_SPECIAL_SYM_TYPE_ANY
))
9302 elf_sym
->internal_elf_sym
.st_target_internal
= ST_BRANCH_TO_C64
;
9306 /* Remove any overlapping mapping symbols generated by alignment frags. */
9307 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9308 /* Now do generic ELF adjustments. */
9309 elf_adjust_symtab ();
9314 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9316 str_hash_insert (table
, key
, value
, 0);
9320 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9322 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9323 checked_hash_insert (table
, key
, value
);
9327 fill_instruction_hash_table (void)
9329 aarch64_opcode
*opcode
= aarch64_opcode_table
;
9331 while (opcode
->name
!= NULL
)
9333 templates
*templ
, *new_templ
;
9334 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9336 new_templ
= XNEW (templates
);
9337 new_templ
->opcode
= opcode
;
9338 new_templ
->next
= NULL
;
9341 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9344 new_templ
->next
= templ
->next
;
9345 templ
->next
= new_templ
;
9352 convert_to_upper (char *dst
, const char *src
, size_t num
)
9355 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9356 *dst
= TOUPPER (*src
);
9360 /* Assume STR point to a lower-case string, allocate, convert and return
9361 the corresponding upper-case string. */
9362 static inline const char*
9363 get_upper_str (const char *str
)
9366 size_t len
= strlen (str
);
9367 ret
= XNEWVEC (char, len
+ 1);
9368 convert_to_upper (ret
, str
, len
);
9372 /* MD interface: Initialization. */
9380 aarch64_ops_hsh
= str_htab_create ();
9381 aarch64_cond_hsh
= str_htab_create ();
9382 aarch64_shift_hsh
= str_htab_create ();
9383 aarch64_sys_regs_hsh
= str_htab_create ();
9384 aarch64_pstatefield_hsh
= str_htab_create ();
9385 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9386 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9387 aarch64_sys_regs_at_hsh
= str_htab_create ();
9388 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9389 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9390 aarch64_reg_hsh
= str_htab_create ();
9391 aarch64_barrier_opt_hsh
= str_htab_create ();
9392 aarch64_nzcv_hsh
= str_htab_create ();
9393 aarch64_pldop_hsh
= str_htab_create ();
9394 aarch64_hint_opt_hsh
= str_htab_create ();
9396 fill_instruction_hash_table ();
9398 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9399 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9400 (void *) (aarch64_sys_regs
+ i
));
9402 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9403 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9404 aarch64_pstatefields
[i
].name
,
9405 (void *) (aarch64_pstatefields
+ i
));
9407 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9408 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9409 aarch64_sys_regs_ic
[i
].name
,
9410 (void *) (aarch64_sys_regs_ic
+ i
));
9412 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9413 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9414 aarch64_sys_regs_dc
[i
].name
,
9415 (void *) (aarch64_sys_regs_dc
+ i
));
9417 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9418 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9419 aarch64_sys_regs_at
[i
].name
,
9420 (void *) (aarch64_sys_regs_at
+ i
));
9422 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9423 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9424 aarch64_sys_regs_tlbi
[i
].name
,
9425 (void *) (aarch64_sys_regs_tlbi
+ i
));
9427 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9428 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9429 aarch64_sys_regs_sr
[i
].name
,
9430 (void *) (aarch64_sys_regs_sr
+ i
));
9432 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9433 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9434 (void *) (reg_names
+ i
));
9436 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9437 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9438 (void *) (nzcv_names
+ i
));
9440 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9442 const char *name
= aarch64_operand_modifiers
[i
].name
;
9443 checked_hash_insert (aarch64_shift_hsh
, name
,
9444 (void *) (aarch64_operand_modifiers
+ i
));
9445 /* Also hash the name in the upper case. */
9446 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9447 (void *) (aarch64_operand_modifiers
+ i
));
9450 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9453 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9454 the same condition code. */
9455 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9457 const char *name
= aarch64_conds
[i
].names
[j
];
9460 checked_hash_insert (aarch64_cond_hsh
, name
,
9461 (void *) (aarch64_conds
+ i
));
9462 /* Also hash the name in the upper case. */
9463 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9464 (void *) (aarch64_conds
+ i
));
9468 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9470 const char *name
= aarch64_barrier_options
[i
].name
;
9471 /* Skip xx00 - the unallocated values of option. */
9474 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9475 (void *) (aarch64_barrier_options
+ i
));
9476 /* Also hash the name in the upper case. */
9477 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9478 (void *) (aarch64_barrier_options
+ i
));
9481 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9483 const char* name
= aarch64_prfops
[i
].name
;
9484 /* Skip the unallocated hint encodings. */
9487 checked_hash_insert (aarch64_pldop_hsh
, name
,
9488 (void *) (aarch64_prfops
+ i
));
9489 /* Also hash the name in the upper case. */
9490 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9491 (void *) (aarch64_prfops
+ i
));
9494 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9496 const char* name
= aarch64_hint_options
[i
].name
;
9497 const char* upper_name
= get_upper_str(name
);
9499 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9500 (void *) (aarch64_hint_options
+ i
));
9502 /* Also hash the name in the upper case if not the same. */
9503 if (strcmp (name
, upper_name
) != 0)
9504 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9505 (void *) (aarch64_hint_options
+ i
));
9508 /* Set the cpu variant based on the command-line options. */
9510 mcpu_cpu_opt
= march_cpu_opt
;
9513 mcpu_cpu_opt
= &cpu_default
;
9515 cpu_variant
= *mcpu_cpu_opt
;
9517 /* Record the CPU type. */
9518 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
9520 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9524 bfd_set_private_flags (stdoutput
, EF_AARCH64_CHERI_PURECAP
);
9528 /* Command line processing. */
9530 const char *md_shortopts
= "m:";
9532 #ifdef AARCH64_BI_ENDIAN
9533 #define OPTION_EB (OPTION_MD_BASE + 0)
9534 #define OPTION_EL (OPTION_MD_BASE + 1)
9536 #if TARGET_BYTES_BIG_ENDIAN
9537 #define OPTION_EB (OPTION_MD_BASE + 0)
9539 #define OPTION_EL (OPTION_MD_BASE + 1)
9543 struct option md_longopts
[] = {
9545 {"EB", no_argument
, NULL
, OPTION_EB
},
9548 {"EL", no_argument
, NULL
, OPTION_EL
},
9550 {NULL
, no_argument
, NULL
, 0}
9553 size_t md_longopts_size
= sizeof (md_longopts
);
9555 struct aarch64_option_table
9557 const char *option
; /* Option name to match. */
9558 const char *help
; /* Help information. */
9559 int *var
; /* Variable to change. */
9560 int value
; /* What to change it to. */
9561 char *deprecated
; /* If non-null, print this message. */
9564 static struct aarch64_option_table aarch64_opts
[] = {
9565 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9566 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9568 #ifdef DEBUG_AARCH64
9569 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9570 #endif /* DEBUG_AARCH64 */
9571 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9573 {"mno-verbose-error", N_("do not output verbose error messages"),
9574 &verbose_error_p
, 0, NULL
},
9575 {NULL
, NULL
, NULL
, 0, NULL
}
9578 struct aarch64_cpu_option_table
9581 const aarch64_feature_set value
;
9582 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9584 const char *canonical_name
;
9587 /* This list should, at a minimum, contain all the cpu names
9588 recognized by GCC. */
9589 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9590 {"all", AARCH64_ANY
, NULL
},
9591 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9592 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9593 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9594 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9595 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9596 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9597 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9598 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9599 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9600 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9601 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9602 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9603 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9604 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9606 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9607 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9609 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9610 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9612 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9613 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9614 | AARCH64_FEATURE_DOTPROD
9615 | AARCH64_FEATURE_SSBS
),
9617 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9618 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9619 | AARCH64_FEATURE_DOTPROD
9620 | AARCH64_FEATURE_SSBS
),
9622 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9623 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9624 | AARCH64_FEATURE_DOTPROD
9625 | AARCH64_FEATURE_SSBS
),
9627 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9628 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9629 | AARCH64_FEATURE_DOTPROD
9630 | AARCH64_FEATURE_SSBS
),
9632 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9634 | AARCH64_FEATURE_RCPC
9635 | AARCH64_FEATURE_DOTPROD
9636 | AARCH64_FEATURE_SSBS
9637 | AARCH64_FEATURE_PROFILE
),
9639 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9641 | AARCH64_FEATURE_RCPC
9642 | AARCH64_FEATURE_DOTPROD
9643 | AARCH64_FEATURE_SSBS
9644 | AARCH64_FEATURE_PROFILE
),
9646 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9647 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9648 | AARCH64_FEATURE_DOTPROD
9649 | AARCH64_FEATURE_PROFILE
),
9651 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9652 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9653 "Samsung Exynos M1"},
9654 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9655 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9656 | AARCH64_FEATURE_RDMA
),
9658 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9659 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9660 | AARCH64_FEATURE_DOTPROD
9661 | AARCH64_FEATURE_SSBS
),
9663 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9664 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9665 | AARCH64_FEATURE_DOTPROD
9666 | AARCH64_FEATURE_PROFILE
),
9668 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9669 AARCH64_FEATURE_BFLOAT16
9670 | AARCH64_FEATURE_I8MM
9671 | AARCH64_FEATURE_F16
9672 | AARCH64_FEATURE_SVE
9673 | AARCH64_FEATURE_SVE2
9674 | AARCH64_FEATURE_SVE2_BITPERM
9675 | AARCH64_FEATURE_MEMTAG
9676 | AARCH64_FEATURE_RNG
),
9678 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9679 AARCH64_FEATURE_PROFILE
9680 | AARCH64_FEATURE_CVADP
9681 | AARCH64_FEATURE_SVE
9682 | AARCH64_FEATURE_SSBS
9683 | AARCH64_FEATURE_RNG
9684 | AARCH64_FEATURE_F16
9685 | AARCH64_FEATURE_BFLOAT16
9686 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9687 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9688 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9689 | AARCH64_FEATURE_RDMA
),
9690 "Qualcomm QDF24XX"},
9691 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9692 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9693 "Qualcomm Saphira"},
9694 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9695 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9697 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9698 AARCH64_FEATURE_CRYPTO
),
9700 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9701 in earlier releases and is superseded by 'xgene1' in all
9703 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9704 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9705 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9706 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9707 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9708 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9710 | AARCH64_FEATURE_RCPC
9711 | AARCH64_FEATURE_DOTPROD
9712 | AARCH64_FEATURE_SSBS
9713 | AARCH64_FEATURE_PROFILE
),
9715 {"generic", AARCH64_ARCH_V8
, NULL
},
9717 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9720 struct aarch64_arch_option_table
9723 const aarch64_feature_set value
;
9726 /* This list should, at a minimum, contain all the architecture names
9727 recognized by GCC. */
9728 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9729 {"all", AARCH64_ANY
},
9730 {"armv8-a", AARCH64_ARCH_V8
},
9731 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9732 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9733 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9734 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9735 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9736 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9737 {"armv8-r", AARCH64_ARCH_V8_R
},
9738 {"morello", AARCH64_ARCH_MORELLO
},
9739 {NULL
, AARCH64_ARCH_NONE
}
9742 /* ISA extensions. */
9743 struct aarch64_option_cpu_value_table
9746 const aarch64_feature_set value
;
9747 const aarch64_feature_set require
; /* Feature dependencies. */
9750 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9751 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9753 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9754 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9755 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9757 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9759 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9760 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9761 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9763 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9765 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9767 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9768 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9769 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9770 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9771 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9772 AARCH64_FEATURE (AARCH64_FEATURE_FP
9773 | AARCH64_FEATURE_F16
, 0)},
9774 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9776 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9777 AARCH64_FEATURE (AARCH64_FEATURE_F16
9778 | AARCH64_FEATURE_SIMD
9779 | AARCH64_FEATURE_COMPNUM
, 0)},
9780 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9782 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9783 AARCH64_FEATURE (AARCH64_FEATURE_F16
9784 | AARCH64_FEATURE_SIMD
, 0)},
9785 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9787 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9789 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9791 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9793 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9795 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9797 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9799 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9800 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9801 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9803 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9805 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9807 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9808 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9809 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9810 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9811 | AARCH64_FEATURE_SM4
, 0)},
9812 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9813 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9814 | AARCH64_FEATURE_AES
, 0)},
9815 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9816 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9817 | AARCH64_FEATURE_SHA3
, 0)},
9818 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9819 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9820 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9822 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9824 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9825 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9826 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9827 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9828 {"a64c", AARCH64_FEATURE (AARCH64_FEATURE_A64C
, 0),
9830 {"c64", AARCH64_FEATURE (AARCH64_FEATURE_C64
, 0),
9831 AARCH64_FEATURE (AARCH64_FEATURE_A64C
, 0)},
9832 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9835 struct aarch64_long_option_table
9837 const char *option
; /* Substring to match. */
9838 const char *help
; /* Help information. */
9839 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9840 char *deprecated
; /* If non-null, print this message. */
9843 /* Transitive closure of features depending on set. */
9844 static aarch64_feature_set
9845 aarch64_feature_disable_set (aarch64_feature_set set
)
9847 const struct aarch64_option_cpu_value_table
*opt
;
9848 aarch64_feature_set prev
= 0;
9850 while (prev
!= set
) {
9852 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9853 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9854 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9859 /* Transitive closure of dependencies of set. */
9860 static aarch64_feature_set
9861 aarch64_feature_enable_set (aarch64_feature_set set
)
9863 const struct aarch64_option_cpu_value_table
*opt
;
9864 aarch64_feature_set prev
= 0;
9866 while (prev
!= set
) {
9868 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9869 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9870 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9876 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9877 bfd_boolean ext_only
)
9879 /* We insist on extensions being added before being removed. We achieve
9880 this by using the ADDING_VALUE variable to indicate whether we are
9881 adding an extension (1) or removing it (0) and only allowing it to
9882 change in the order -1 -> 1 -> 0. */
9883 int adding_value
= -1;
9884 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9886 /* Copy the feature set, so that we can modify it. */
9890 while (str
!= NULL
&& *str
!= 0)
9892 const struct aarch64_option_cpu_value_table
*opt
;
9893 const char *ext
= NULL
;
9900 as_bad (_("invalid architectural extension"));
9904 ext
= strchr (++str
, '+');
9910 optlen
= strlen (str
);
9912 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9914 if (adding_value
!= 0)
9919 else if (optlen
> 0)
9921 if (adding_value
== -1)
9923 else if (adding_value
!= 1)
9925 as_bad (_("must specify extensions to add before specifying "
9926 "those to remove"));
9933 as_bad (_("missing architectural extension"));
9937 gas_assert (adding_value
!= -1);
9939 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9940 if (strncmp (opt
->name
, str
, optlen
) == 0)
9942 aarch64_feature_set set
;
9944 /* Add or remove the extension. */
9947 set
= aarch64_feature_enable_set (opt
->value
);
9948 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9952 set
= aarch64_feature_disable_set (opt
->value
);
9953 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9958 if (opt
->name
== NULL
)
9960 as_bad (_("unknown architectural extension `%s'"), str
);
9971 aarch64_parse_cpu (const char *str
)
9973 const struct aarch64_cpu_option_table
*opt
;
9974 const char *ext
= strchr (str
, '+');
9980 optlen
= strlen (str
);
9984 as_bad (_("missing cpu name `%s'"), str
);
9988 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9989 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9991 mcpu_cpu_opt
= &opt
->value
;
9993 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9998 as_bad (_("unknown cpu `%s'"), str
);
10003 aarch64_parse_arch (const char *str
)
10005 const struct aarch64_arch_option_table
*opt
;
10006 const char *ext
= strchr (str
, '+');
10010 optlen
= ext
- str
;
10012 optlen
= strlen (str
);
10016 as_bad (_("missing architecture name `%s'"), str
);
10020 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10021 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10023 march_cpu_opt
= &opt
->value
;
10025 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
10030 as_bad (_("unknown architecture `%s'\n"), str
);
10035 struct aarch64_option_abi_value_table
10038 enum aarch64_abi_type value
;
10041 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10042 {"ilp32", AARCH64_ABI_ILP32
},
10043 {"lp64", AARCH64_ABI_LP64
},
10044 /* Note that these values are accepted since they are valid parameters to
10045 the -mabi argument for GCC. However we base no decision on them. */
10046 {"purecap", AARCH64_ABI_PURECAP
},
10047 {"hybrid", AARCH64_ABI_HYBRID
},
10051 aarch64_parse_abi (const char *str
)
10055 if (str
[0] == '\0')
10057 as_bad (_("missing abi name `%s'"), str
);
10061 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10062 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10064 aarch64_abi
= aarch64_abis
[i
].value
;
10068 as_bad (_("unknown abi `%s'\n"), str
);
10072 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10074 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10075 aarch64_parse_abi
, NULL
},
10076 #endif /* OBJ_ELF */
10077 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10078 aarch64_parse_cpu
, NULL
},
10079 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10080 aarch64_parse_arch
, NULL
},
10081 {NULL
, NULL
, 0, NULL
}
10085 md_parse_option (int c
, const char *arg
)
10087 struct aarch64_option_table
*opt
;
10088 struct aarch64_long_option_table
*lopt
;
10094 target_big_endian
= 1;
10100 target_big_endian
= 0;
10105 /* Listing option. Just ignore these, we don't support additional
10110 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10112 if (c
== opt
->option
[0]
10113 && ((arg
== NULL
&& opt
->option
[1] == 0)
10114 || streq (arg
, opt
->option
+ 1)))
10116 /* If the option is deprecated, tell the user. */
10117 if (opt
->deprecated
!= NULL
)
10118 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10119 arg
? arg
: "", _(opt
->deprecated
));
10121 if (opt
->var
!= NULL
)
10122 *opt
->var
= opt
->value
;
10128 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10130 /* These options are expected to have an argument. */
10131 if (c
== lopt
->option
[0]
10133 && strncmp (arg
, lopt
->option
+ 1,
10134 strlen (lopt
->option
+ 1)) == 0)
10136 /* If the option is deprecated, tell the user. */
10137 if (lopt
->deprecated
!= NULL
)
10138 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10139 _(lopt
->deprecated
));
10141 /* Call the sup-option parser. */
10142 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10153 md_show_usage (FILE * fp
)
10155 struct aarch64_option_table
*opt
;
10156 struct aarch64_long_option_table
*lopt
;
10158 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10160 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10161 if (opt
->help
!= NULL
)
10162 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10164 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10165 if (lopt
->help
!= NULL
)
10166 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10170 -EB assemble code for a big-endian cpu\n"));
10175 -EL assemble code for a little-endian cpu\n"));
10179 /* Parse a .cpu directive. */
10182 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10184 const struct aarch64_cpu_option_table
*opt
;
10190 name
= input_line_pointer
;
10191 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10192 input_line_pointer
++;
10193 saved_char
= *input_line_pointer
;
10194 *input_line_pointer
= 0;
10196 ext
= strchr (name
, '+');
10199 optlen
= ext
- name
;
10201 optlen
= strlen (name
);
10203 /* Skip the first "all" entry. */
10204 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10205 if (strlen (opt
->name
) == optlen
10206 && strncmp (name
, opt
->name
, optlen
) == 0)
10208 mcpu_cpu_opt
= &opt
->value
;
10210 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
10213 cpu_variant
= *mcpu_cpu_opt
;
10215 *input_line_pointer
= saved_char
;
10216 demand_empty_rest_of_line ();
10219 as_bad (_("unknown cpu `%s'"), name
);
10220 *input_line_pointer
= saved_char
;
10221 ignore_rest_of_line ();
10225 /* Parse a .arch directive. */
10228 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10230 const struct aarch64_arch_option_table
*opt
;
10236 name
= input_line_pointer
;
10237 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10238 input_line_pointer
++;
10239 saved_char
= *input_line_pointer
;
10240 *input_line_pointer
= 0;
10242 ext
= strchr (name
, '+');
10245 optlen
= ext
- name
;
10247 optlen
= strlen (name
);
10249 /* Skip the first "all" entry. */
10250 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10251 if (strlen (opt
->name
) == optlen
10252 && strncmp (name
, opt
->name
, optlen
) == 0)
10254 mcpu_cpu_opt
= &opt
->value
;
10256 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
10259 cpu_variant
= *mcpu_cpu_opt
;
10261 *input_line_pointer
= saved_char
;
10262 demand_empty_rest_of_line ();
10266 as_bad (_("unknown architecture `%s'\n"), name
);
10267 *input_line_pointer
= saved_char
;
10268 ignore_rest_of_line ();
10271 /* Parse a .arch_extension directive. */
10274 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10277 char *ext
= input_line_pointer
;;
10279 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10280 input_line_pointer
++;
10281 saved_char
= *input_line_pointer
;
10282 *input_line_pointer
= 0;
10284 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
10287 cpu_variant
= *mcpu_cpu_opt
;
10289 *input_line_pointer
= saved_char
;
10290 demand_empty_rest_of_line ();
10293 /* Copy symbol information. */
10296 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10298 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10302 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10303 This is needed so AArch64 specific st_other values can be independently
10304 specified for an IFUNC resolver (that is called by the dynamic linker)
10305 and the symbol it resolves (aliased to the resolver). In particular,
10306 if a function symbol has special st_other value set via directives,
10307 then attaching an IFUNC resolver to that symbol should not override
10308 the st_other setting. Requiring the directive on the IFUNC resolver
10309 symbol would be unexpected and problematic in C code, where the two
10310 symbols appear as two independent function declarations. */
10313 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10315 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10316 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10319 if (destelf
->size
== NULL
)
10320 destelf
->size
= XNEW (expressionS
);
10321 *destelf
->size
= *srcelf
->size
;
10325 free (destelf
->size
);
10326 destelf
->size
= NULL
;
10328 S_SET_SIZE (dest
, S_GET_SIZE (src
));