1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2024 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
34 #include "gen-sframe.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
38 #include "opcodes/i386-mnem.h"
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
46 #define DEFAULT_ARCH "i386"
51 #define INLINE __inline__
57 /* Prefixes will be emitted in the order defined below.
58 WAIT_PREFIX must be the first prefix since FWAIT is really is an
59 instruction, and so must come before any prefixes.
60 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
61 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
67 #define HLE_PREFIX REP_PREFIX
68 #define BND_PREFIX REP_PREFIX
70 #define REX_PREFIX 6 /* must come last. */
71 #define MAX_PREFIXES 7 /* max prefixes per opcode */
73 /* we define the syntax here (modulo base,index,scale syntax) */
74 #define REGISTER_PREFIX '%'
75 #define IMMEDIATE_PREFIX '$'
76 #define ABSOLUTE_PREFIX '*'
78 /* these are the instruction mnemonic suffixes in AT&T syntax or
79 memory operand size in Intel syntax. */
80 #define WORD_MNEM_SUFFIX 'w'
81 #define BYTE_MNEM_SUFFIX 'b'
82 #define SHORT_MNEM_SUFFIX 's'
83 #define LONG_MNEM_SUFFIX 'l'
84 #define QWORD_MNEM_SUFFIX 'q'
86 #define END_OF_INSN '\0'
88 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
90 /* This matches the C -> StaticRounding alias in the opcode table. */
91 #define commutative staticrounding
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
:8; /* arch string length */
133 bool skip
:1; /* show_arch should skip this. */
134 enum processor_type type
; /* arch type */
135 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
136 i386_cpu_flags enable
; /* cpu feature enable flags */
137 i386_cpu_flags disable
; /* cpu feature disable flags */
141 static void update_code_flag (int, int);
142 static void s_insn (int);
143 static void s_noopt (int);
144 static void set_code_flag (int);
145 static void set_16bit_gcc_code_flag (int);
146 static void set_intel_syntax (int);
147 static void set_intel_mnemonic (int);
148 static void set_allow_index_reg (int);
149 static void set_check (int);
150 static void set_cpu_arch (int);
152 static void pe_directive_secrel (int);
153 static void pe_directive_secidx (int);
155 static void signed_cons (int);
156 static char *output_invalid (int c
);
157 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
159 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
161 static int i386_att_operand (char *);
162 static int i386_intel_operand (char *, int);
163 static int i386_intel_simplify (expressionS
*);
164 static int i386_intel_parse_name (const char *, expressionS
*);
165 static const reg_entry
*parse_register (const char *, char **);
166 static const char *parse_insn (const char *, char *, bool);
167 static char *parse_operands (char *, const char *);
168 static void swap_operands (void);
169 static void swap_2_operands (unsigned int, unsigned int);
170 static enum i386_flag_code
i386_addressing_mode (void);
171 static void optimize_imm (void);
172 static bool optimize_disp (const insn_template
*t
);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const reg_entry
*build_modrm_byte (void);
183 static void output_insn (const struct last_insn
*);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used
;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used
;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
200 static const char *default_arch
= DEFAULT_ARCH
;
202 /* parse_register() returns this when a register alias cannot be used. */
203 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
204 { Dw2Inval
, Dw2Inval
} };
206 static const reg_entry
*reg_eax
;
207 static const reg_entry
*reg_ds
;
208 static const reg_entry
*reg_es
;
209 static const reg_entry
*reg_ss
;
210 static const reg_entry
*reg_st0
;
211 static const reg_entry
*reg_k0
;
216 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
217 unsigned char bytes
[4];
219 /* Destination or source register specifier. */
220 const reg_entry
*register_specifier
;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry
*regs
;
235 no_error
, /* Must be first. */
236 operand_size_mismatch
,
237 operand_type_mismatch
,
238 register_type_mismatch
,
239 number_of_operands_mismatch
,
240 invalid_instruction_suffix
,
242 unsupported_with_intel_mnemonic
,
244 unsupported_EGPR_for_addressing
,
251 invalid_vsib_address
,
252 invalid_vector_register_set
,
253 invalid_tmm_register_set
,
254 invalid_dest_and_src_register_set
,
255 invalid_dest_register_set
,
256 invalid_pseudo_prefix
,
257 unsupported_vector_index_register
,
258 unsupported_broadcast
,
261 mask_not_on_destination
,
264 unsupported_vector_size
,
265 unsupported_rsp_register
,
271 /* TM holds the template for the insn were currently assembling. */
274 /* SUFFIX holds the instruction size suffix for byte, word, dword
275 or qword, if given. */
278 /* OPCODE_LENGTH holds the number of base opcode bytes. */
279 unsigned char opcode_length
;
281 /* OPERANDS gives the number of given operands. */
282 unsigned int operands
;
284 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
285 of given register, displacement, memory operands and immediate
287 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
289 /* TYPES [i] is the type (see above #defines) which tells us how to
290 use OP[i] for the corresponding operand. */
291 i386_operand_type types
[MAX_OPERANDS
];
293 /* Displacement expression, immediate expression, or register for each
295 union i386_op op
[MAX_OPERANDS
];
297 /* Flags for operands. */
298 unsigned int flags
[MAX_OPERANDS
];
299 #define Operand_PCrel 1
300 #define Operand_Mem 2
301 #define Operand_Signed 4 /* .insn only */
303 /* Relocation type for operand */
304 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
306 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
307 the base index byte below. */
308 const reg_entry
*base_reg
;
309 const reg_entry
*index_reg
;
310 unsigned int log2_scale_factor
;
312 /* SEG gives the seg_entries of this insn. They are zero unless
313 explicit segment overrides are given. */
314 const reg_entry
*seg
[2];
316 /* PREFIX holds all the given prefix opcodes (usually null).
317 PREFIXES is the number of prefix opcodes. */
318 unsigned int prefixes
;
319 unsigned char prefix
[MAX_PREFIXES
];
321 /* .insn allows for reserved opcode spaces. */
322 unsigned char insn_opcode_space
;
324 /* .insn also allows (requires) specifying immediate size. */
325 unsigned char imm_bits
[MAX_OPERANDS
];
327 /* Register is in low 3 bits of opcode. */
330 /* The operand to a branch insn indicates an absolute branch. */
333 /* The operand to a branch insn indicates a far branch. */
336 /* There is a memory operand of (%dx) which should be only used
337 with input/output instructions. */
338 bool input_output_operand
;
340 /* Extended states. */
348 xstate_ymm
= 1 << 2 | xstate_xmm
,
350 xstate_zmm
= 1 << 3 | xstate_ymm
,
353 /* Use MASK state. */
357 /* Has GOTPC or TLS relocation. */
358 bool has_gotpc_tls_reloc
;
360 /* RM and SIB are the modrm byte and the sib byte where the
361 addressing modes of this insn are encoded. */
369 /* Masking attributes.
371 The struct describes masking, applied to OPERAND in the instruction.
372 REG is a pointer to the corresponding mask register. ZEROING tells
373 whether merging or zeroing mask is used. */
374 struct Mask_Operation
376 const reg_entry
*reg
;
377 unsigned int zeroing
;
378 /* The operand where this operation is associated. */
379 unsigned int operand
;
382 /* Rounding control and SAE attributes. */
394 /* In Intel syntax the operand modifier form is supposed to be used, but
395 we continue to accept the immediate forms as well. */
399 /* Broadcasting attributes.
401 The struct describes broadcasting, applied to OPERAND. TYPE is
402 expresses the broadcast factor. */
403 struct Broadcast_Operation
405 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
408 /* Index of broadcasted operand. */
409 unsigned int operand
;
411 /* Number of bytes to broadcast. */
415 /* Compressed disp8*N attribute. */
416 unsigned int memshift
;
418 /* Prefer load or store in encoding. */
421 dir_encoding_default
= 0,
427 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
430 disp_encoding_default
= 0,
436 /* Prefer the REX byte in encoding. */
439 /* Prefer the REX2 prefix in encoding. */
442 /* Disable instruction size optimization. */
445 /* How to encode instructions. */
448 encoding_default
= 0,
451 encoding_egpr
, /* REX2 or EVEX. */
458 const char *rep_prefix
;
461 const char *hle_prefix
;
463 /* Have BND prefix. */
464 const char *bnd_prefix
;
466 /* Have NOTRACK prefix. */
467 const char *notrack_prefix
;
470 enum i386_error error
;
473 typedef struct _i386_insn i386_insn
;
475 /* Link RC type with corresponding string, that'll be looked for in
484 static const struct RC_name RC_NamesTable
[] =
486 { rne
, STRING_COMMA_LEN ("rn-sae") },
487 { rd
, STRING_COMMA_LEN ("rd-sae") },
488 { ru
, STRING_COMMA_LEN ("ru-sae") },
489 { rz
, STRING_COMMA_LEN ("rz-sae") },
490 { saeonly
, STRING_COMMA_LEN ("sae") },
493 /* To be indexed by segment register number. */
494 static const unsigned char i386_seg_prefixes
[] = {
503 /* List of chars besides those in app.c:symbol_chars that can start an
504 operand. Used to prevent the scrubber eating vital white-space. */
505 const char extra_symbol_chars
[] = "*%-([{}"
514 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
515 && !defined (TE_GNU) \
516 && !defined (TE_LINUX) \
517 && !defined (TE_Haiku) \
518 && !defined (TE_FreeBSD) \
519 && !defined (TE_DragonFly) \
520 && !defined (TE_NetBSD))
521 /* This array holds the chars that always start a comment. If the
522 pre-processor is disabled, these aren't very useful. The option
523 --divide will remove '/' from this list. */
524 const char *i386_comment_chars
= "#/";
525 #define SVR4_COMMENT_CHARS 1
526 #define PREFIX_SEPARATOR '\\'
529 const char *i386_comment_chars
= "#";
530 #define PREFIX_SEPARATOR '/'
533 /* This array holds the chars that only start a comment at the beginning of
534 a line. If the line seems to have the form '# 123 filename'
535 .line and .file directives will appear in the pre-processed output.
536 Note that input_file.c hand checks for '#' at the beginning of the
537 first line of the input file. This is because the compiler outputs
538 #NO_APP at the beginning of its output.
539 Also note that comments started like this one will always work if
540 '/' isn't otherwise defined. */
541 const char line_comment_chars
[] = "#/";
543 const char line_separator_chars
[] = ";";
545 /* Chars that can be used to separate mant from exp in floating point
547 const char EXP_CHARS
[] = "eE";
549 /* Chars that mean this number is a floating point constant
552 const char FLT_CHARS
[] = "fFdDxXhHbB";
554 /* Tables for lexical analysis. */
555 static char mnemonic_chars
[256];
556 static char register_chars
[256];
557 static char operand_chars
[256];
559 /* Lexical macros. */
560 #define is_operand_char(x) (operand_chars[(unsigned char) x])
561 #define is_register_char(x) (register_chars[(unsigned char) x])
562 #define is_space_char(x) ((x) == ' ')
564 /* All non-digit non-letter characters that may occur in an operand and
565 which aren't already in extra_symbol_chars[]. */
566 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
568 /* md_assemble() always leaves the strings it's passed unaltered. To
569 effect this we maintain a stack of saved characters that we've smashed
570 with '\0's (indicating end of strings for various sub-fields of the
571 assembler instruction). */
572 static char save_stack
[32];
573 static char *save_stack_p
;
574 #define END_STRING_AND_SAVE(s) \
575 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
576 #define RESTORE_END_STRING(s) \
577 do { *(s) = *--save_stack_p; } while (0)
579 /* The instruction we're assembling. */
582 /* Possible templates for current insn. */
583 static templates current_templates
;
585 /* Per instruction expressionS buffers: max displacements & immediates. */
586 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
587 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
589 /* Current operand we are working on. */
590 static int this_operand
= -1;
592 /* Are we processing a .insn directive? */
593 #define dot_insn() (i.tm.mnem_off == MN__insn)
595 enum i386_flag_code i386_flag_code
;
596 #define flag_code i386_flag_code /* Permit to continue using original name. */
597 static unsigned int object_64bit
;
598 static unsigned int disallow_64bit_reloc
;
599 static int use_rela_relocations
= 0;
600 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
601 static const char *tls_get_addr
;
603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
605 /* The ELF ABI to use. */
613 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
616 #if defined (TE_PE) || defined (TE_PEP)
617 /* Use big object file format. */
618 static int use_big_obj
= 0;
621 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
622 /* 1 if generating code for a shared library. */
623 static int shared
= 0;
625 unsigned int x86_sframe_cfa_sp_reg
;
626 /* The other CFA base register for SFrame stack trace info. */
627 unsigned int x86_sframe_cfa_fp_reg
;
628 unsigned int x86_sframe_cfa_ra_reg
;
632 /* 1 for intel syntax,
634 static int intel_syntax
= 0;
636 static enum x86_64_isa
638 amd64
= 1, /* AMD64 ISA. */
639 intel64
/* Intel64 ISA. */
642 /* 1 for intel mnemonic,
643 0 if att mnemonic. */
644 static int intel_mnemonic
= !SYSV386_COMPAT
;
646 /* 1 if pseudo registers are permitted. */
647 static int allow_pseudo_reg
= 0;
649 /* 1 if register prefix % not required. */
650 static int allow_naked_reg
= 0;
652 /* 1 if the assembler should add BND prefix for all control-transferring
653 instructions supporting it, even if this prefix wasn't specified
655 static int add_bnd_prefix
= 0;
657 /* 1 if pseudo index register, eiz/riz, is allowed . */
658 static int allow_index_reg
= 0;
660 /* 1 if the assembler should ignore LOCK prefix, even if it was
661 specified explicitly. */
662 static int omit_lock_prefix
= 0;
664 /* 1 if the assembler should encode lfence, mfence, and sfence as
665 "lock addl $0, (%{re}sp)". */
666 static int avoid_fence
= 0;
668 /* 1 if lfence should be inserted after every load. */
669 static int lfence_after_load
= 0;
671 /* Non-zero if lfence should be inserted before indirect branch. */
672 static enum lfence_before_indirect_branch_kind
674 lfence_branch_none
= 0,
675 lfence_branch_register
,
676 lfence_branch_memory
,
679 lfence_before_indirect_branch
;
681 /* Non-zero if lfence should be inserted before ret. */
682 static enum lfence_before_ret_kind
684 lfence_before_ret_none
= 0,
685 lfence_before_ret_not
,
686 lfence_before_ret_or
,
687 lfence_before_ret_shl
691 /* 1 if the assembler should generate relax relocations. */
693 static int generate_relax_relocations
694 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
696 static enum check_kind
702 sse_check
, operand_check
= check_warning
;
704 /* Non-zero if branches should be aligned within power of 2 boundary. */
705 static int align_branch_power
= 0;
707 /* Types of branches to align. */
708 enum align_branch_kind
710 align_branch_none
= 0,
711 align_branch_jcc
= 1,
712 align_branch_fused
= 2,
713 align_branch_jmp
= 3,
714 align_branch_call
= 4,
715 align_branch_indirect
= 5,
719 /* Type bits of branches to align. */
720 enum align_branch_bit
722 align_branch_jcc_bit
= 1 << align_branch_jcc
,
723 align_branch_fused_bit
= 1 << align_branch_fused
,
724 align_branch_jmp_bit
= 1 << align_branch_jmp
,
725 align_branch_call_bit
= 1 << align_branch_call
,
726 align_branch_indirect_bit
= 1 << align_branch_indirect
,
727 align_branch_ret_bit
= 1 << align_branch_ret
730 static unsigned int align_branch
= (align_branch_jcc_bit
731 | align_branch_fused_bit
732 | align_branch_jmp_bit
);
734 /* Types of condition jump used by macro-fusion. */
737 mf_jcc_jo
= 0, /* base opcode 0x70 */
738 mf_jcc_jc
, /* base opcode 0x72 */
739 mf_jcc_je
, /* base opcode 0x74 */
740 mf_jcc_jna
, /* base opcode 0x76 */
741 mf_jcc_js
, /* base opcode 0x78 */
742 mf_jcc_jp
, /* base opcode 0x7a */
743 mf_jcc_jl
, /* base opcode 0x7c */
744 mf_jcc_jle
, /* base opcode 0x7e */
747 /* Types of compare flag-modifying insntructions used by macro-fusion. */
750 mf_cmp_test_and
, /* test/cmp */
751 mf_cmp_alu_cmp
, /* add/sub/cmp */
752 mf_cmp_incdec
/* inc/dec */
755 /* The maximum padding size for fused jcc. CMP like instruction can
756 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
758 #define MAX_FUSED_JCC_PADDING_SIZE 20
760 /* The maximum number of prefixes added for an instruction. */
761 static unsigned int align_branch_prefix_size
= 5;
764 1. Clear the REX_W bit with register operand if possible.
765 2. Above plus use 128bit vector instruction to clear the full vector
768 static int optimize
= 0;
771 1. Clear the REX_W bit with register operand if possible.
772 2. Above plus use 128bit vector instruction to clear the full vector
774 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
777 static int optimize_for_space
= 0;
779 /* Register prefix used for error message. */
780 static const char *register_prefix
= "%";
782 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
783 leave, push, and pop instructions so that gcc has the same stack
784 frame as in 32 bit mode. */
785 static char stackop_size
= '\0';
787 /* Non-zero to optimize code alignment. */
788 int optimize_align_code
= 1;
790 /* Non-zero to quieten some warnings. */
791 static int quiet_warnings
= 0;
793 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
794 static bool pre_386_16bit_warned
;
797 static const char *cpu_arch_name
= NULL
;
798 static char *cpu_sub_arch_name
= NULL
;
800 /* CPU feature flags. */
801 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
803 /* ISA extensions available in 64-bit mode only. */
804 static const i386_cpu_flags cpu_64_flags
= CPU_ANY_64_FLAGS
;
806 /* If we have selected a cpu we are generating instructions for. */
807 static int cpu_arch_tune_set
= 0;
809 /* Cpu we are generating instructions for. */
810 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
812 /* CPU instruction set architecture used. */
813 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
815 /* CPU feature flags of instruction set architecture used. */
816 i386_cpu_flags cpu_arch_isa_flags
;
818 /* If set, conditional jumps are not automatically promoted to handle
819 larger than a byte offset. */
820 static bool no_cond_jump_promotion
= false;
822 /* This will be set from an expression parser hook if there's any
823 applicable operator involved in an expression. */
826 expr_operator_present
,
830 /* Encode SSE instructions with VEX prefix. */
831 static unsigned int sse2avx
;
833 /* Encode aligned vector move as unaligned vector move. */
834 static unsigned int use_unaligned_vector_move
;
836 /* Maximum permitted vector size. */
840 #define VSZ_DEFAULT VSZ512
841 static unsigned int vector_size
= VSZ_DEFAULT
;
843 /* Encode scalar AVX instructions with specific vector length. */
850 /* Encode VEX WIG instructions with specific vex.w. */
857 /* Encode scalar EVEX LIG instructions with specific vector length. */
865 /* Encode EVEX WIG instructions with specific evex.w. */
872 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
873 static enum rc_type evexrcig
= rne
;
875 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
876 static symbolS
*GOT_symbol
;
878 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
879 unsigned int x86_dwarf2_return_column
;
881 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
882 int x86_cie_data_alignment
;
884 /* Interface to relax_segment.
885 There are 3 major relax states for 386 jump insns because the
886 different types of jumps add different sizes to frags when we're
887 figuring out what sort of jump to choose to reach a given label.
889 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
890 branches which are handled by md_estimate_size_before_relax() and
891 i386_generic_table_relax_frag(). */
894 #define UNCOND_JUMP 0
896 #define COND_JUMP86 2
897 #define BRANCH_PADDING 3
898 #define BRANCH_PREFIX 4
899 #define FUSED_JCC_PADDING 5
904 #define SMALL16 (SMALL | CODE16)
906 #define BIG16 (BIG | CODE16)
910 #define INLINE __inline__
916 #define ENCODE_RELAX_STATE(type, size) \
917 ((relax_substateT) (((type) << 2) | (size)))
918 #define TYPE_FROM_RELAX_STATE(s) \
920 #define DISP_SIZE_FROM_RELAX_STATE(s) \
921 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
923 /* This table is used by relax_frag to promote short jumps to long
924 ones where necessary. SMALL (short) jumps may be promoted to BIG
925 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
926 don't allow a short jump in a 32 bit code segment to be promoted to
927 a 16 bit offset jump because it's slower (requires data size
928 prefix), and doesn't work, unless the destination is in the bottom
929 64k of the code segment (The top 16 bits of eip are zeroed). */
931 const relax_typeS md_relax_table
[] =
934 1) most positive reach of this state,
935 2) most negative reach of this state,
936 3) how many bytes this mode will have in the variable part of the frag
937 4) which index into the table to try if we can't fit into this one. */
939 /* UNCOND_JUMP states. */
940 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
942 /* dword jmp adds 4 bytes to frag:
943 0 extra opcode bytes, 4 displacement bytes. */
945 /* word jmp adds 2 byte2 to frag:
946 0 extra opcode bytes, 2 displacement bytes. */
949 /* COND_JUMP states. */
950 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
952 /* dword conditionals adds 5 bytes to frag:
953 1 extra opcode byte, 4 displacement bytes. */
955 /* word conditionals add 3 bytes to frag:
956 1 extra opcode byte, 2 displacement bytes. */
959 /* COND_JUMP86 states. */
960 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
962 /* dword conditionals adds 5 bytes to frag:
963 1 extra opcode byte, 4 displacement bytes. */
965 /* word conditionals add 4 bytes to frag:
966 1 displacement byte and a 3 byte long branch insn. */
970 #define ARCH(n, t, f, s) \
971 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
973 #define SUBARCH(n, e, d, s) \
974 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
975 CPU_ ## d ## _FLAGS }
976 #define VECARCH(n, e, d, v) \
977 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
978 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
980 static const arch_entry cpu_arch
[] =
982 /* Do not replace the first two entries - i386_target_format() and
983 set_cpu_arch() rely on them being there in this order. */
984 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
985 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
986 ARCH (i8086
, UNKNOWN
, NONE
, false),
987 ARCH (i186
, UNKNOWN
, 186, false),
988 ARCH (i286
, UNKNOWN
, 286, false),
989 ARCH (i386
, I386
, 386, false),
990 ARCH (i486
, I486
, 486, false),
991 ARCH (i586
, PENTIUM
, 586, false),
992 ARCH (pentium
, PENTIUM
, 586, false),
993 ARCH (i686
, I686
, 686, false),
994 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
995 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
996 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
997 ARCH (pentium4
, PENTIUM4
, P4
, false),
998 ARCH (prescott
, NOCONA
, CORE
, false),
999 ARCH (nocona
, NOCONA
, NOCONA
, false),
1000 ARCH (yonah
, CORE
, CORE
, true),
1001 ARCH (core
, CORE
, CORE
, false),
1002 ARCH (merom
, CORE2
, CORE2
, true),
1003 ARCH (core2
, CORE2
, CORE2
, false),
1004 ARCH (corei7
, COREI7
, COREI7
, false),
1005 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1006 ARCH (k6
, K6
, K6
, false),
1007 ARCH (k6_2
, K6
, K6_2
, false),
1008 ARCH (athlon
, ATHLON
, ATHLON
, false),
1009 ARCH (sledgehammer
, K8
, K8
, true),
1010 ARCH (opteron
, K8
, K8
, false),
1011 ARCH (k8
, K8
, K8
, false),
1012 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1013 ARCH (bdver1
, BD
, BDVER1
, false),
1014 ARCH (bdver2
, BD
, BDVER2
, false),
1015 ARCH (bdver3
, BD
, BDVER3
, false),
1016 ARCH (bdver4
, BD
, BDVER4
, false),
1017 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1018 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1019 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1020 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1021 ARCH (znver5
, ZNVER
, ZNVER5
, false),
1022 ARCH (btver1
, BT
, BTVER1
, false),
1023 ARCH (btver2
, BT
, BTVER2
, false),
1025 SUBARCH (8087, 8087, ANY_8087
, false),
1026 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1027 SUBARCH (287, 287, ANY_287
, false),
1028 SUBARCH (387, 387, ANY_387
, false),
1029 SUBARCH (687, 687, ANY_687
, false),
1030 SUBARCH (cmov
, CMOV
, CMOV
, false),
1031 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1032 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1033 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1034 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1035 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1036 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1037 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1038 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1039 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1040 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1041 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1042 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1043 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1044 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1045 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1046 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1047 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1048 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1049 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1050 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1051 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1052 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1053 SUBARCH (smx
, SMX
, SMX
, false),
1054 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1055 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1056 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1057 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1058 SUBARCH (aes
, AES
, ANY_AES
, false),
1059 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1060 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1061 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1062 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1063 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1064 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1065 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1066 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1067 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1068 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1069 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1070 SUBARCH (cx16
, CX16
, CX16
, false),
1071 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1072 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1073 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1074 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1075 SUBARCH (hle
, HLE
, HLE
, false),
1076 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1077 SUBARCH (tsx
, TSX
, TSX
, false),
1078 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1079 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1080 SUBARCH (nop
, NOP
, NOP
, false),
1081 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1082 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1083 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1084 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1085 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1086 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1087 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1088 SUBARCH (abm
, ABM
, ABM
, false),
1089 SUBARCH (bmi
, BMI
, BMI
, false),
1090 SUBARCH (tbm
, TBM
, TBM
, false),
1091 SUBARCH (adx
, ADX
, ADX
, false),
1092 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1093 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1094 SUBARCH (smap
, SMAP
, SMAP
, false),
1095 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1096 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1097 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1098 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1099 SUBARCH (se1
, SE1
, SE1
, false),
1100 SUBARCH (clwb
, CLWB
, CLWB
, false),
1101 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1102 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1103 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1104 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1105 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1106 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1107 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1108 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1109 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1110 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1111 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1112 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1113 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1114 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1115 SUBARCH (ibt
, IBT
, IBT
, false),
1116 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1117 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1118 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1119 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1120 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1121 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1122 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1123 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1124 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1125 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1126 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1127 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1128 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1129 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1130 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1131 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1132 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1133 ANY_AVX512_VP2INTERSECT
, reset
),
1134 SUBARCH (tdx
, TDX
, TDX
, false),
1135 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1136 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1137 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1138 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1139 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1140 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1141 SUBARCH (kl
, KL
, ANY_KL
, false),
1142 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1143 SUBARCH (uintr
, UINTR
, UINTR
, false),
1144 SUBARCH (hreset
, HRESET
, HRESET
, false),
1145 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1146 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1147 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1148 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1149 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1150 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1151 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1152 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1153 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1154 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1155 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1156 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1157 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1158 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1159 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1160 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1161 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1162 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1163 SUBARCH (user_msr
, USER_MSR
, USER_MSR
, false),
1164 SUBARCH (apx_f
, APX_F
, APX_F
, false),
1171 /* Like s_lcomm_internal in gas/read.c but the alignment string
1172 is allowed to be optional. */
1175 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1182 && *input_line_pointer
== ',')
1184 align
= parse_align (needs_align
- 1);
1186 if (align
== (addressT
) -1)
1201 bss_alloc (symbolP
, size
, align
);
1206 pe_lcomm (int needs_align
)
1208 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1212 const pseudo_typeS md_pseudo_table
[] =
1214 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1215 {"align", s_align_bytes
, 0},
1217 {"align", s_align_ptwo
, 0},
1219 {"arch", set_cpu_arch
, 0},
1224 {"lcomm", pe_lcomm
, 1},
1226 {"ffloat", float_cons
, 'f'},
1227 {"dfloat", float_cons
, 'd'},
1228 {"tfloat", float_cons
, 'x'},
1229 {"hfloat", float_cons
, 'h'},
1230 {"bfloat16", float_cons
, 'b'},
1232 {"slong", signed_cons
, 4},
1233 {"insn", s_insn
, 0},
1234 {"noopt", s_noopt
, 0},
1235 {"optim", s_ignore
, 0},
1236 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1237 {"code16", set_code_flag
, CODE_16BIT
},
1238 {"code32", set_code_flag
, CODE_32BIT
},
1240 {"code64", set_code_flag
, CODE_64BIT
},
1242 {"intel_syntax", set_intel_syntax
, 1},
1243 {"att_syntax", set_intel_syntax
, 0},
1244 {"intel_mnemonic", set_intel_mnemonic
, 1},
1245 {"att_mnemonic", set_intel_mnemonic
, 0},
1246 {"allow_index_reg", set_allow_index_reg
, 1},
1247 {"disallow_index_reg", set_allow_index_reg
, 0},
1248 {"sse_check", set_check
, 0},
1249 {"operand_check", set_check
, 1},
1250 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1251 {"largecomm", handle_large_common
, 0},
1253 {"file", dwarf2_directive_file
, 0},
1254 {"loc", dwarf2_directive_loc
, 0},
1255 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1258 {"secrel32", pe_directive_secrel
, 0},
1259 {"secidx", pe_directive_secidx
, 0},
1264 /* For interface with expression (). */
1265 extern char *input_line_pointer
;
1267 /* Hash table for instruction mnemonic lookup. */
1268 static htab_t op_hash
;
1270 /* Hash table for register lookup. */
1271 static htab_t reg_hash
;
1273 /* Various efficient no-op patterns for aligning code labels.
1274 Note: Don't try to assemble the instructions in the comments.
1275 0L and 0w are not legal. */
1276 static const unsigned char f32_1
[] =
1278 static const unsigned char f32_2
[] =
1279 {0x66,0x90}; /* xchg %ax,%ax */
1280 static const unsigned char f32_3
[] =
1281 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1282 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1283 static const unsigned char f32_5
[] =
1284 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1285 static const unsigned char f32_6
[] =
1286 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1287 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1288 static const unsigned char f32_8
[] =
1289 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1290 static const unsigned char f64_3
[] =
1291 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1292 static const unsigned char f64_4
[] =
1293 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1294 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1295 static const unsigned char f64_6
[] =
1296 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1297 static const unsigned char f64_7
[] =
1298 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1299 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1300 static const unsigned char f64_9
[] =
1301 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1302 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1303 static const unsigned char f16_3
[] =
1304 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1305 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1306 static const unsigned char f16_5
[] =
1307 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1308 static const unsigned char jump_disp8
[] =
1309 {0xeb}; /* jmp disp8 */
1310 static const unsigned char jump32_disp32
[] =
1311 {0xe9}; /* jmp disp32 */
1312 static const unsigned char jump16_disp32
[] =
1313 {0x66,0xe9}; /* jmp disp32 */
1314 /* 32-bit NOPs patterns. */
1315 static const unsigned char *const f32_patt
[] = {
1316 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1318 /* 64-bit NOPs patterns. */
1319 static const unsigned char *const f64_patt
[] = {
1320 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1322 /* 16-bit NOPs patterns. */
1323 static const unsigned char *const f16_patt
[] = {
1324 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1326 /* nopl (%[re]ax) */
1327 static const unsigned char alt_3
[] =
1329 /* nopl 0(%[re]ax) */
1330 static const unsigned char alt_4
[] =
1331 {0x0f,0x1f,0x40,0x00};
1332 /* nopl 0(%[re]ax,%[re]ax,1) */
1333 #define alt_5 (alt_6 + 1)
1334 /* nopw 0(%[re]ax,%[re]ax,1) */
1335 static const unsigned char alt_6
[] =
1336 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1337 /* nopl 0L(%[re]ax) */
1338 static const unsigned char alt_7
[] =
1339 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1340 /* nopl 0L(%[re]ax,%[re]ax,1) */
1341 #define alt_8 (alt_9 + 1)
1342 /* nopw 0L(%[re]ax,%[re]ax,1) */
1343 static const unsigned char alt_9
[] =
1344 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1345 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1346 #define alt_10 (alt_11 + 1)
1347 /* data16 nopw %cs:0L(%eax,%eax,1) */
1348 static const unsigned char alt_11
[] =
1349 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1350 /* 32-bit and 64-bit NOPs patterns. */
1351 static const unsigned char *const alt_patt
[] = {
1352 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1353 alt_9
, alt_10
, alt_11
1356 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1357 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1360 i386_output_nops (char *where
, const unsigned char *const *patt
,
1361 int count
, int max_single_nop_size
)
1364 /* Place the longer NOP first. */
1367 const unsigned char *nops
;
1369 if (max_single_nop_size
< 1)
1371 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1372 max_single_nop_size
);
1376 nops
= patt
[max_single_nop_size
- 1];
1377 last
= count
% max_single_nop_size
;
1380 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1381 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1385 nops
= patt
[last
- 1];
1386 memcpy (where
+ offset
, nops
, last
);
1391 fits_in_imm7 (offsetT num
)
1393 return (num
& 0x7f) == num
;
1397 fits_in_imm31 (offsetT num
)
1399 return (num
& 0x7fffffff) == num
;
1402 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1403 single NOP instruction LIMIT. */
1406 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1408 const unsigned char *const *patt
= NULL
;
1409 int max_single_nop_size
;
1410 /* Maximum number of NOPs before switching to jump over NOPs. */
1411 int max_number_of_nops
;
1413 switch (fragP
->fr_type
)
1418 case rs_machine_dependent
:
1419 /* Allow NOP padding for jumps and calls. */
1420 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1421 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1428 /* We need to decide which NOP sequence to use for 32bit and
1429 64bit. When -mtune= is used:
1431 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1432 PROCESSOR_GENERIC32, f32_patt will be used.
1433 2. For the rest, alt_patt will be used.
1435 When -mtune= isn't used, alt_patt will be used if
1436 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1439 When -march= or .arch is used, we can't use anything beyond
1440 cpu_arch_isa_flags. */
1442 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1445 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1446 /* Limit number of NOPs to 2 in 16-bit mode. */
1447 max_number_of_nops
= 2;
1451 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1452 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1454 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1455 explicitly disabled. */
1456 switch (fragP
->tc_frag_data
.tune
)
1458 case PROCESSOR_UNKNOWN
:
1459 /* We use cpu_arch_isa_flags to check if we SHOULD
1460 optimize with nops. */
1461 if (fragP
->tc_frag_data
.isanop
)
1465 case PROCESSOR_PENTIUMPRO
:
1466 case PROCESSOR_PENTIUM4
:
1467 case PROCESSOR_NOCONA
:
1468 case PROCESSOR_CORE
:
1469 case PROCESSOR_CORE2
:
1470 case PROCESSOR_COREI7
:
1471 case PROCESSOR_GENERIC64
:
1473 case PROCESSOR_ATHLON
:
1475 case PROCESSOR_AMDFAM10
:
1477 case PROCESSOR_ZNVER
:
1479 if (fragP
->tc_frag_data
.cpunop
)
1483 case PROCESSOR_I386
:
1484 case PROCESSOR_I486
:
1485 case PROCESSOR_PENTIUM
:
1486 case PROCESSOR_I686
:
1487 case PROCESSOR_IAMCU
:
1488 case PROCESSOR_GENERIC32
:
1490 case PROCESSOR_NONE
:
1496 switch (fragP
->tc_frag_data
.tune
)
1498 case PROCESSOR_UNKNOWN
:
1499 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1500 PROCESSOR_UNKNOWN. */
1505 /* We use cpu_arch_isa_flags to check if we CAN optimize
1507 if (fragP
->tc_frag_data
.isanop
)
1511 case PROCESSOR_NONE
:
1516 if (patt
!= alt_patt
)
1518 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1519 : ARRAY_SIZE (f64_patt
);
1520 /* Limit number of NOPs to 2 for older processors. */
1521 max_number_of_nops
= 2;
1525 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1526 /* Limit number of NOPs to 7 for newer processors. */
1527 max_number_of_nops
= 7;
1532 limit
= max_single_nop_size
;
1534 if (fragP
->fr_type
== rs_fill_nop
)
1536 /* Output NOPs for .nop directive. */
1537 if (limit
> max_single_nop_size
)
1539 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1540 _("invalid single nop size: %d "
1541 "(expect within [0, %d])"),
1542 limit
, max_single_nop_size
);
1546 else if (fragP
->fr_type
!= rs_machine_dependent
)
1547 fragP
->fr_var
= count
;
1549 /* Emit a plain NOP first when the last thing we saw may not have been
1550 a proper instruction (e.g. a stand-alone prefix or .byte). */
1551 if (!fragP
->tc_frag_data
.last_insn_normal
)
1557 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1559 /* Generate jump over NOPs. */
1560 offsetT disp
= count
- 2;
1561 if (fits_in_imm7 (disp
))
1563 /* Use "jmp disp8" if possible. */
1565 where
[0] = jump_disp8
[0];
1571 unsigned int size_of_jump
;
1573 if (flag_code
== CODE_16BIT
)
1575 where
[0] = jump16_disp32
[0];
1576 where
[1] = jump16_disp32
[1];
1581 where
[0] = jump32_disp32
[0];
1585 count
-= size_of_jump
+ 4;
1586 if (!fits_in_imm31 (count
))
1588 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1589 _("jump over nop padding out of range"));
1593 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1594 where
+= size_of_jump
+ 4;
1598 /* Generate multiple NOPs. */
1599 i386_output_nops (where
, patt
, count
, limit
);
1603 operand_type_all_zero (const union i386_operand_type
*x
)
1605 switch (ARRAY_SIZE(x
->array
))
1616 return !x
->array
[0];
1623 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1625 switch (ARRAY_SIZE(x
->array
))
1641 x
->bitfield
.class = ClassNone
;
1642 x
->bitfield
.instance
= InstanceNone
;
1646 operand_type_equal (const union i386_operand_type
*x
,
1647 const union i386_operand_type
*y
)
1649 switch (ARRAY_SIZE(x
->array
))
1652 if (x
->array
[2] != y
->array
[2])
1656 if (x
->array
[1] != y
->array
[1])
1660 return x
->array
[0] == y
->array
[0];
1668 _is_cpu (const i386_cpu_attr
*a
, enum i386_cpu cpu
)
1672 case Cpu287
: return a
->bitfield
.cpu287
;
1673 case Cpu387
: return a
->bitfield
.cpu387
;
1674 case Cpu3dnow
: return a
->bitfield
.cpu3dnow
;
1675 case Cpu3dnowA
: return a
->bitfield
.cpu3dnowa
;
1676 case CpuAVX
: return a
->bitfield
.cpuavx
;
1677 case CpuHLE
: return a
->bitfield
.cpuhle
;
1678 case CpuAVX512F
: return a
->bitfield
.cpuavx512f
;
1679 case CpuAVX512VL
: return a
->bitfield
.cpuavx512vl
;
1680 case CpuAPX_F
: return a
->bitfield
.cpuapx_f
;
1681 case Cpu64
: return a
->bitfield
.cpu64
;
1682 case CpuNo64
: return a
->bitfield
.cpuno64
;
1684 gas_assert (cpu
< CpuAttrEnums
);
1686 return a
->bitfield
.isa
== cpu
+ 1u;
1690 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1692 return _is_cpu(&t
->cpu
, cpu
);
1696 maybe_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1698 return _is_cpu(&t
->cpu_any
, cpu
);
1701 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1703 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1704 i386_cpu_flags f
= { .array
[0] = 0 };
1706 switch (ARRAY_SIZE (a
.array
))
1709 f
.array
[CpuAttrEnums
/ bps
]
1710 #ifndef WORDS_BIGENDIAN
1711 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1713 |= (a
.array
[0] << CpuIsaBits
) >> (CpuAttrEnums
% bps
);
1715 if (CpuMax
/ bps
> CpuAttrEnums
/ bps
)
1716 f
.array
[CpuAttrEnums
/ bps
+ 1]
1717 #ifndef WORDS_BIGENDIAN
1718 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1720 = (a
.array
[0] << CpuIsaBits
) << (bps
- CpuAttrEnums
% bps
);
1729 #ifndef WORDS_BIGENDIAN
1730 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1732 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << (~(a
.bitfield
.isa
- 1) % bps
);
1739 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1741 switch (ARRAY_SIZE(x
->array
))
1760 return !x
->array
[0];
1767 cpu_flags_equal (const union i386_cpu_flags
*x
,
1768 const union i386_cpu_flags
*y
)
1770 switch (ARRAY_SIZE(x
->array
))
1773 if (x
->array
[4] != y
->array
[4])
1777 if (x
->array
[3] != y
->array
[3])
1781 if (x
->array
[2] != y
->array
[2])
1785 if (x
->array
[1] != y
->array
[1])
1789 return x
->array
[0] == y
->array
[0];
1797 cpu_flags_check_cpu64 (const insn_template
*t
)
1799 return flag_code
== CODE_64BIT
1800 ? !t
->cpu
.bitfield
.cpuno64
1801 : !t
->cpu
.bitfield
.cpu64
;
1804 static INLINE i386_cpu_flags
1805 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1807 switch (ARRAY_SIZE (x
.array
))
1810 x
.array
[4] &= y
.array
[4];
1813 x
.array
[3] &= y
.array
[3];
1816 x
.array
[2] &= y
.array
[2];
1819 x
.array
[1] &= y
.array
[1];
1822 x
.array
[0] &= y
.array
[0];
1830 static INLINE i386_cpu_flags
1831 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1833 switch (ARRAY_SIZE (x
.array
))
1836 x
.array
[4] |= y
.array
[4];
1839 x
.array
[3] |= y
.array
[3];
1842 x
.array
[2] |= y
.array
[2];
1845 x
.array
[1] |= y
.array
[1];
1848 x
.array
[0] |= y
.array
[0];
1856 static INLINE i386_cpu_flags
1857 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1859 switch (ARRAY_SIZE (x
.array
))
1862 x
.array
[4] &= ~y
.array
[4];
1865 x
.array
[3] &= ~y
.array
[3];
1868 x
.array
[2] &= ~y
.array
[2];
1871 x
.array
[1] &= ~y
.array
[1];
1874 x
.array
[0] &= ~y
.array
[0];
1882 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1884 static INLINE
bool need_evex_encoding (const insn_template
*t
)
1886 return i
.encoding
== encoding_evex
1887 || i
.encoding
== encoding_evex512
1888 || (t
->opcode_modifier
.vex
&& i
.encoding
== encoding_egpr
)
1892 #define CPU_FLAGS_ARCH_MATCH 0x1
1893 #define CPU_FLAGS_64BIT_MATCH 0x2
1895 #define CPU_FLAGS_PERFECT_MATCH \
1896 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1898 /* Return CPU flags match bits. */
1901 cpu_flags_match (const insn_template
*t
)
1903 i386_cpu_flags cpu
, active
, all
= cpu_flags_from_attr (t
->cpu
);
1904 i386_cpu_flags any
= cpu_flags_from_attr (t
->cpu_any
);
1905 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1907 all
.bitfield
.cpu64
= 0;
1908 all
.bitfield
.cpuno64
= 0;
1909 gas_assert (!any
.bitfield
.cpu64
);
1910 gas_assert (!any
.bitfield
.cpuno64
);
1912 if (cpu_flags_all_zero (&all
) && cpu_flags_all_zero (&any
))
1914 /* This instruction is available on all archs. */
1915 return match
| CPU_FLAGS_ARCH_MATCH
;
1918 /* This instruction is available only on some archs. */
1920 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1921 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1923 /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
1924 know that EVEX encoding will be needed. */
1925 if ((any
.bitfield
.cpuavx
|| any
.bitfield
.cpuavx2
|| any
.bitfield
.cpufma
)
1926 && (any
.bitfield
.cpuavx512f
|| any
.bitfield
.cpuavx512vl
))
1928 if (need_evex_encoding (t
))
1930 any
.bitfield
.cpuavx
= 0;
1931 any
.bitfield
.cpuavx2
= 0;
1932 any
.bitfield
.cpufma
= 0;
1934 /* need_evex_encoding(t) isn't reliable before operands were
1936 else if (i
.operands
)
1938 any
.bitfield
.cpuavx512f
= 0;
1939 any
.bitfield
.cpuavx512vl
= 0;
1943 /* Dual non-APX/APX templates need massaging from what APX_F() in the
1944 opcode table has produced. While the direct transformation of the
1945 incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F)
1946 respectively, it's cheaper to move to just cpuid / cpuid&APX_F
1948 if (any
.bitfield
.cpuapx_f
1949 && (any
.bitfield
.cpubmi
|| any
.bitfield
.cpubmi2
1950 || any
.bitfield
.cpuavx512f
|| any
.bitfield
.cpuavx512bw
1951 || any
.bitfield
.cpuavx512dq
|| any
.bitfield
.cpuamx_tile
1952 || any
.bitfield
.cpucmpccxadd
|| any
.bitfield
.cpuuser_msr
))
1954 /* These checks (verifying that APX_F() was properly used in the
1955 opcode table entry) make sure there's no need for an "else" to
1956 the "if()" below. */
1957 gas_assert (!cpu_flags_all_zero (&all
));
1958 cpu
= cpu_flags_and (all
, any
);
1959 gas_assert (cpu_flags_equal (&cpu
, &all
));
1961 if (need_evex_encoding (t
))
1964 memset (&any
, 0, sizeof (any
));
1968 if (flag_code
!= CODE_64BIT
)
1969 active
= cpu_flags_and_not (cpu_arch_flags
, cpu_64_flags
);
1971 active
= cpu_arch_flags
;
1972 cpu
= cpu_flags_and (all
, active
);
1973 if (cpu_flags_equal (&cpu
, &all
))
1975 /* AVX and AVX2 present at the same time express an operand size
1976 dependency - strip AVX2 for the purposes here. The operand size
1977 dependent check occurs in check_vecOperands(). */
1978 if (any
.bitfield
.cpuavx
&& any
.bitfield
.cpuavx2
)
1979 any
.bitfield
.cpuavx2
= 0;
1981 cpu
= cpu_flags_and (any
, active
);
1982 if (cpu_flags_all_zero (&any
) || !cpu_flags_all_zero (&cpu
))
1983 match
|= CPU_FLAGS_ARCH_MATCH
;
1988 static INLINE i386_operand_type
1989 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1991 if (x
.bitfield
.class != y
.bitfield
.class)
1992 x
.bitfield
.class = ClassNone
;
1993 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1994 x
.bitfield
.instance
= InstanceNone
;
1996 switch (ARRAY_SIZE (x
.array
))
1999 x
.array
[2] &= y
.array
[2];
2002 x
.array
[1] &= y
.array
[1];
2005 x
.array
[0] &= y
.array
[0];
2013 static INLINE i386_operand_type
2014 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2016 gas_assert (y
.bitfield
.class == ClassNone
);
2017 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2019 switch (ARRAY_SIZE (x
.array
))
2022 x
.array
[2] &= ~y
.array
[2];
2025 x
.array
[1] &= ~y
.array
[1];
2028 x
.array
[0] &= ~y
.array
[0];
2036 static INLINE i386_operand_type
2037 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2039 gas_assert (x
.bitfield
.class == ClassNone
||
2040 y
.bitfield
.class == ClassNone
||
2041 x
.bitfield
.class == y
.bitfield
.class);
2042 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2043 y
.bitfield
.instance
== InstanceNone
||
2044 x
.bitfield
.instance
== y
.bitfield
.instance
);
2046 switch (ARRAY_SIZE (x
.array
))
2049 x
.array
[2] |= y
.array
[2];
2052 x
.array
[1] |= y
.array
[1];
2055 x
.array
[0] |= y
.array
[0];
2063 static INLINE i386_operand_type
2064 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2066 gas_assert (y
.bitfield
.class == ClassNone
);
2067 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2069 switch (ARRAY_SIZE (x
.array
))
2072 x
.array
[2] ^= y
.array
[2];
2075 x
.array
[1] ^= y
.array
[1];
2078 x
.array
[0] ^= y
.array
[0];
2086 static const i386_operand_type anydisp
= {
2087 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2099 operand_type_check (i386_operand_type t
, enum operand_type c
)
2104 return t
.bitfield
.class == Reg
;
2107 return (t
.bitfield
.imm8
2111 || t
.bitfield
.imm32s
2112 || t
.bitfield
.imm64
);
2115 return (t
.bitfield
.disp8
2116 || t
.bitfield
.disp16
2117 || t
.bitfield
.disp32
2118 || t
.bitfield
.disp64
);
2121 return (t
.bitfield
.disp8
2122 || t
.bitfield
.disp16
2123 || t
.bitfield
.disp32
2124 || t
.bitfield
.disp64
2125 || t
.bitfield
.baseindex
);
2134 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2135 between operand GIVEN and opeand WANTED for instruction template T. */
2138 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2141 return !((i
.types
[given
].bitfield
.byte
2142 && !t
->operand_types
[wanted
].bitfield
.byte
)
2143 || (i
.types
[given
].bitfield
.word
2144 && !t
->operand_types
[wanted
].bitfield
.word
)
2145 || (i
.types
[given
].bitfield
.dword
2146 && !t
->operand_types
[wanted
].bitfield
.dword
)
2147 || (i
.types
[given
].bitfield
.qword
2148 && (!t
->operand_types
[wanted
].bitfield
.qword
2149 /* Don't allow 64-bit (memory) operands outside of 64-bit
2150 mode, when they're used where a 64-bit GPR could also
2151 be used. Checking is needed for Intel Syntax only. */
2153 && flag_code
!= CODE_64BIT
2154 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2155 || t
->operand_types
[wanted
].bitfield
.class == Accum
2156 || t
->opcode_modifier
.isstring
))))
2157 || (i
.types
[given
].bitfield
.tbyte
2158 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2161 /* Return 1 if there is no conflict in SIMD register between operand
2162 GIVEN and opeand WANTED for instruction template T. */
2165 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2168 return !((i
.types
[given
].bitfield
.xmmword
2169 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2170 || (i
.types
[given
].bitfield
.ymmword
2171 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2172 || (i
.types
[given
].bitfield
.zmmword
2173 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2174 || (i
.types
[given
].bitfield
.tmmword
2175 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2178 /* Return 1 if there is no conflict in any size between operand GIVEN
2179 and opeand WANTED for instruction template T. */
2182 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2185 return (match_operand_size (t
, wanted
, given
)
2186 && !((i
.types
[given
].bitfield
.unspecified
2187 && !i
.broadcast
.type
2188 && !i
.broadcast
.bytes
2189 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2190 || (i
.types
[given
].bitfield
.fword
2191 && !t
->operand_types
[wanted
].bitfield
.fword
)
2192 /* For scalar opcode templates to allow register and memory
2193 operands at the same time, some special casing is needed
2194 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2195 down-conversion vpmov*. */
2196 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2197 && t
->operand_types
[wanted
].bitfield
.byte
2198 + t
->operand_types
[wanted
].bitfield
.word
2199 + t
->operand_types
[wanted
].bitfield
.dword
2200 + t
->operand_types
[wanted
].bitfield
.qword
2201 > !!t
->opcode_modifier
.broadcast
)
2202 ? (i
.types
[given
].bitfield
.xmmword
2203 || i
.types
[given
].bitfield
.ymmword
2204 || i
.types
[given
].bitfield
.zmmword
)
2205 : !match_simd_size(t
, wanted
, given
))));
2208 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2209 operands for instruction template T, and it has MATCH_REVERSE set if there
2210 is no size conflict on any operands for the template with operands reversed
2211 (and the template allows for reversing in the first place). */
2213 #define MATCH_STRAIGHT 1
2214 #define MATCH_REVERSE 2
2216 static INLINE
unsigned int
2217 operand_size_match (const insn_template
*t
)
2219 unsigned int j
, match
= MATCH_STRAIGHT
;
2221 /* Don't check non-absolute jump instructions. */
2222 if (t
->opcode_modifier
.jump
2223 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2226 /* Check memory and accumulator operand size. */
2227 for (j
= 0; j
< i
.operands
; j
++)
2229 if (i
.types
[j
].bitfield
.class != Reg
2230 && i
.types
[j
].bitfield
.class != RegSIMD
2231 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2234 if (t
->operand_types
[j
].bitfield
.class == Reg
2235 && !match_operand_size (t
, j
, j
))
2241 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2242 && !match_simd_size (t
, j
, j
))
2248 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2249 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2255 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2262 if (!t
->opcode_modifier
.d
)
2265 /* Check reverse. */
2266 gas_assert (i
.operands
>= 2);
2268 for (j
= 0; j
< i
.operands
; j
++)
2270 unsigned int given
= i
.operands
- j
- 1;
2272 /* For FMA4 and XOP insns VEX.W controls just the first two
2273 register operands. And APX_F insns just swap the two source operands,
2274 with the 3rd one being the destination. */
2275 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
)
2276 || is_cpu (t
, CpuAPX_F
))
2277 given
= j
< 2 ? 1 - j
: j
;
2279 if (t
->operand_types
[j
].bitfield
.class == Reg
2280 && !match_operand_size (t
, j
, given
))
2283 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2284 && !match_simd_size (t
, j
, given
))
2287 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2288 && (!match_operand_size (t
, j
, given
)
2289 || !match_simd_size (t
, j
, given
)))
2292 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2296 return match
| MATCH_REVERSE
;
2300 operand_type_match (i386_operand_type overlap
,
2301 i386_operand_type given
)
2303 i386_operand_type temp
= overlap
;
2305 temp
.bitfield
.unspecified
= 0;
2306 temp
.bitfield
.byte
= 0;
2307 temp
.bitfield
.word
= 0;
2308 temp
.bitfield
.dword
= 0;
2309 temp
.bitfield
.fword
= 0;
2310 temp
.bitfield
.qword
= 0;
2311 temp
.bitfield
.tbyte
= 0;
2312 temp
.bitfield
.xmmword
= 0;
2313 temp
.bitfield
.ymmword
= 0;
2314 temp
.bitfield
.zmmword
= 0;
2315 temp
.bitfield
.tmmword
= 0;
2316 if (operand_type_all_zero (&temp
))
2319 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2323 i
.error
= operand_type_mismatch
;
2327 /* If given types g0 and g1 are registers they must be of the same type
2328 unless the expected operand type register overlap is null.
2329 Intel syntax sized memory operands are also checked here. */
2332 operand_type_register_match (i386_operand_type g0
,
2333 i386_operand_type t0
,
2334 i386_operand_type g1
,
2335 i386_operand_type t1
)
2337 if (g0
.bitfield
.class != Reg
2338 && g0
.bitfield
.class != RegSIMD
2339 && (g0
.bitfield
.unspecified
2340 || !operand_type_check (g0
, anymem
)))
2343 if (g1
.bitfield
.class != Reg
2344 && g1
.bitfield
.class != RegSIMD
2345 && (g1
.bitfield
.unspecified
2346 || !operand_type_check (g1
, anymem
)))
2349 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2350 && g0
.bitfield
.word
== g1
.bitfield
.word
2351 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2352 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2353 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2354 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2355 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2358 /* If expectations overlap in no more than a single size, all is fine. */
2359 g0
= operand_type_and (t0
, t1
);
2360 if (g0
.bitfield
.byte
2364 + g0
.bitfield
.xmmword
2365 + g0
.bitfield
.ymmword
2366 + g0
.bitfield
.zmmword
<= 1)
2369 i
.error
= register_type_mismatch
;
2374 static INLINE
unsigned int
2375 register_number (const reg_entry
*r
)
2377 unsigned int nr
= r
->reg_num
;
2379 if (r
->reg_flags
& RegRex
)
2382 if (r
->reg_flags
& (RegVRex
| RegRex2
))
2388 static INLINE
unsigned int
2389 mode_from_disp_size (i386_operand_type t
)
2391 if (t
.bitfield
.disp8
)
2393 else if (t
.bitfield
.disp16
2394 || t
.bitfield
.disp32
)
2401 fits_in_signed_byte (addressT num
)
2403 return num
+ 0x80 <= 0xff;
2407 fits_in_unsigned_byte (addressT num
)
2413 fits_in_unsigned_word (addressT num
)
2415 return num
<= 0xffff;
2419 fits_in_signed_word (addressT num
)
2421 return num
+ 0x8000 <= 0xffff;
2425 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2430 return num
+ 0x80000000 <= 0xffffffff;
2432 } /* fits_in_signed_long() */
2435 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2440 return num
<= 0xffffffff;
2442 } /* fits_in_unsigned_long() */
2444 static INLINE valueT
extend_to_32bit_address (addressT num
)
2447 if (fits_in_unsigned_long(num
))
2448 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2450 if (!fits_in_signed_long (num
))
2451 return num
& 0xffffffff;
2458 fits_in_disp8 (offsetT num
)
2460 int shift
= i
.memshift
;
2466 mask
= (1 << shift
) - 1;
2468 /* Return 0 if NUM isn't properly aligned. */
2472 /* Check if NUM will fit in 8bit after shift. */
2473 return fits_in_signed_byte (num
>> shift
);
2477 fits_in_imm4 (offsetT num
)
2479 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2480 return (num
& (i
.encoding
!= encoding_evex
2481 && i
.encoding
!= encoding_egpr
? 0xf : 7)) == num
;
2484 static i386_operand_type
2485 smallest_imm_type (offsetT num
)
2487 i386_operand_type t
;
2489 operand_type_set (&t
, 0);
2490 t
.bitfield
.imm64
= 1;
2492 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2494 /* This code is disabled on the 486 because all the Imm1 forms
2495 in the opcode table are slower on the i486. They're the
2496 versions with the implicitly specified single-position
2497 displacement, which has another syntax if you really want to
2499 t
.bitfield
.imm1
= 1;
2500 t
.bitfield
.imm8
= 1;
2501 t
.bitfield
.imm8s
= 1;
2502 t
.bitfield
.imm16
= 1;
2503 t
.bitfield
.imm32
= 1;
2504 t
.bitfield
.imm32s
= 1;
2506 else if (fits_in_signed_byte (num
))
2508 if (fits_in_unsigned_byte (num
))
2509 t
.bitfield
.imm8
= 1;
2510 t
.bitfield
.imm8s
= 1;
2511 t
.bitfield
.imm16
= 1;
2512 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2513 t
.bitfield
.imm32
= 1;
2514 t
.bitfield
.imm32s
= 1;
2516 else if (fits_in_unsigned_byte (num
))
2518 t
.bitfield
.imm8
= 1;
2519 t
.bitfield
.imm16
= 1;
2520 t
.bitfield
.imm32
= 1;
2521 t
.bitfield
.imm32s
= 1;
2523 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2525 t
.bitfield
.imm16
= 1;
2526 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2527 t
.bitfield
.imm32
= 1;
2528 t
.bitfield
.imm32s
= 1;
2530 else if (fits_in_signed_long (num
))
2532 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2533 t
.bitfield
.imm32
= 1;
2534 t
.bitfield
.imm32s
= 1;
2536 else if (fits_in_unsigned_long (num
))
2537 t
.bitfield
.imm32
= 1;
2543 offset_in_range (offsetT val
, int size
)
2549 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2550 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2552 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2554 case sizeof (val
): return val
;
2558 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2559 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2560 (uint64_t) val
, (uint64_t) (val
& mask
));
2565 static INLINE
const char *insn_name (const insn_template
*t
)
2567 return &i386_mnemonics
[t
->mnem_off
];
2580 a. PREFIX_EXIST if attempting to add a prefix where one from the
2581 same class already exists.
2582 b. PREFIX_LOCK if lock prefix is added.
2583 c. PREFIX_REP if rep/repne prefix is added.
2584 d. PREFIX_DS if ds prefix is added.
2585 e. PREFIX_OTHER if other prefix is added.
2588 static enum PREFIX_GROUP
2589 add_prefix (unsigned int prefix
)
2591 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2594 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2595 && flag_code
== CODE_64BIT
)
2597 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2598 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2599 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2600 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2611 case DS_PREFIX_OPCODE
:
2614 case CS_PREFIX_OPCODE
:
2615 case ES_PREFIX_OPCODE
:
2616 case FS_PREFIX_OPCODE
:
2617 case GS_PREFIX_OPCODE
:
2618 case SS_PREFIX_OPCODE
:
2622 case REPNE_PREFIX_OPCODE
:
2623 case REPE_PREFIX_OPCODE
:
2628 case LOCK_PREFIX_OPCODE
:
2637 case ADDR_PREFIX_OPCODE
:
2641 case DATA_PREFIX_OPCODE
:
2645 if (i
.prefix
[q
] != 0)
2653 i
.prefix
[q
] |= prefix
;
2656 as_bad (_("same type of prefix used twice"));
2662 update_code_flag (int value
, int check
)
2664 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2666 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2668 as_error (_("64bit mode not supported on `%s'."),
2669 cpu_arch_name
? cpu_arch_name
: default_arch
);
2673 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2675 as_error (_("32bit mode not supported on `%s'."),
2676 cpu_arch_name
? cpu_arch_name
: default_arch
);
2680 flag_code
= (enum flag_code
) value
;
2682 stackop_size
= '\0';
2686 set_code_flag (int value
)
2688 update_code_flag (value
, 0);
2692 set_16bit_gcc_code_flag (int new_code_flag
)
2694 flag_code
= (enum flag_code
) new_code_flag
;
2695 if (flag_code
!= CODE_16BIT
)
2697 stackop_size
= LONG_MNEM_SUFFIX
;
2701 _set_intel_syntax (int syntax_flag
)
2703 intel_syntax
= syntax_flag
;
2705 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2707 register_prefix
= allow_naked_reg
? "" : "%";
2711 set_intel_syntax (int syntax_flag
)
2713 /* Find out if register prefixing is specified. */
2714 int ask_naked_reg
= 0;
2717 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2720 int e
= get_symbol_name (&string
);
2722 if (strcmp (string
, "prefix") == 0)
2724 else if (strcmp (string
, "noprefix") == 0)
2727 as_bad (_("bad argument to syntax directive."));
2728 (void) restore_line_pointer (e
);
2730 demand_empty_rest_of_line ();
2732 if (ask_naked_reg
== 0)
2733 allow_naked_reg
= (syntax_flag
2734 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2736 allow_naked_reg
= (ask_naked_reg
< 0);
2738 _set_intel_syntax (syntax_flag
);
2742 set_intel_mnemonic (int mnemonic_flag
)
2744 intel_mnemonic
= mnemonic_flag
;
2748 set_allow_index_reg (int flag
)
2750 allow_index_reg
= flag
;
2754 set_check (int what
)
2756 enum check_kind
*kind
;
2761 kind
= &operand_check
;
2772 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2775 int e
= get_symbol_name (&string
);
2777 if (strcmp (string
, "none") == 0)
2779 else if (strcmp (string
, "warning") == 0)
2780 *kind
= check_warning
;
2781 else if (strcmp (string
, "error") == 0)
2782 *kind
= check_error
;
2784 as_bad (_("bad argument to %s_check directive."), str
);
2785 (void) restore_line_pointer (e
);
2788 as_bad (_("missing argument for %s_check directive"), str
);
2790 demand_empty_rest_of_line ();
2794 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2795 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2798 static const char *arch
;
2800 /* Intel MCU is only supported on ELF. */
2806 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2807 use default_arch. */
2808 arch
= cpu_arch_name
;
2810 arch
= default_arch
;
2813 /* If we are targeting Intel MCU, we must enable it. */
2814 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2815 == new_flag
.bitfield
.cpuiamcu
)
2818 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2823 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2825 if (cpu_sub_arch_name
)
2826 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2827 pfx
, name
, (const char *) NULL
);
2829 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2832 static void isa_enable (unsigned int idx
)
2834 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2836 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2838 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2839 cpu_arch_flags
= flags
;
2842 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2845 static void isa_disable (unsigned int idx
)
2847 i386_cpu_flags flags
2848 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2850 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2852 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2853 cpu_arch_flags
= flags
;
2857 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2861 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2863 typedef struct arch_stack_entry
2865 const struct arch_stack_entry
*prev
;
2868 i386_cpu_flags flags
;
2869 i386_cpu_flags isa_flags
;
2870 enum processor_type isa
;
2871 enum flag_code flag_code
;
2872 unsigned int vector_size
;
2874 bool no_cond_jump_promotion
;
2876 static const arch_stack_entry
*arch_stack_top
;
2884 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2886 as_bad (_("missing cpu architecture"));
2887 input_line_pointer
++;
2891 e
= get_symbol_name (&s
);
2894 if (strcmp (string
, "push") == 0)
2896 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2898 top
->name
= cpu_arch_name
;
2899 if (cpu_sub_arch_name
)
2900 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2902 top
->sub_name
= NULL
;
2903 top
->flags
= cpu_arch_flags
;
2904 top
->isa
= cpu_arch_isa
;
2905 top
->isa_flags
= cpu_arch_isa_flags
;
2906 top
->flag_code
= flag_code
;
2907 top
->vector_size
= vector_size
;
2908 top
->stackop_size
= stackop_size
;
2909 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2911 top
->prev
= arch_stack_top
;
2912 arch_stack_top
= top
;
2914 (void) restore_line_pointer (e
);
2915 demand_empty_rest_of_line ();
2919 if (strcmp (string
, "pop") == 0)
2921 const arch_stack_entry
*top
= arch_stack_top
;
2924 as_bad (_(".arch stack is empty"));
2925 else if (top
->flag_code
!= flag_code
2926 || top
->stackop_size
!= stackop_size
)
2928 static const unsigned int bits
[] = {
2934 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2935 bits
[top
->flag_code
],
2936 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2940 arch_stack_top
= top
->prev
;
2942 cpu_arch_name
= top
->name
;
2943 free (cpu_sub_arch_name
);
2944 cpu_sub_arch_name
= top
->sub_name
;
2945 cpu_arch_flags
= top
->flags
;
2946 cpu_arch_isa
= top
->isa
;
2947 cpu_arch_isa_flags
= top
->isa_flags
;
2948 vector_size
= top
->vector_size
;
2949 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2954 (void) restore_line_pointer (e
);
2955 demand_empty_rest_of_line ();
2959 if (strcmp (string
, "default") == 0)
2961 if (strcmp (default_arch
, "iamcu") == 0)
2962 string
= default_arch
;
2965 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2967 cpu_arch_name
= NULL
;
2968 free (cpu_sub_arch_name
);
2969 cpu_sub_arch_name
= NULL
;
2970 cpu_arch_flags
= cpu_unknown_flags
;
2971 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2972 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2973 if (!cpu_arch_tune_set
)
2974 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2976 vector_size
= VSZ_DEFAULT
;
2978 j
= ARRAY_SIZE (cpu_arch
) + 1;
2982 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2984 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2985 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2989 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2991 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2993 as_bad (_("64bit mode not supported on `%s'."),
2995 (void) restore_line_pointer (e
);
2996 ignore_rest_of_line ();
3000 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
3002 as_bad (_("32bit mode not supported on `%s'."),
3004 (void) restore_line_pointer (e
);
3005 ignore_rest_of_line ();
3009 cpu_arch_name
= cpu_arch
[j
].name
;
3010 free (cpu_sub_arch_name
);
3011 cpu_sub_arch_name
= NULL
;
3012 cpu_arch_flags
= cpu_arch
[j
].enable
;
3013 cpu_arch_isa
= cpu_arch
[j
].type
;
3014 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
3015 if (!cpu_arch_tune_set
)
3016 cpu_arch_tune
= cpu_arch_isa
;
3018 vector_size
= VSZ_DEFAULT
;
3020 pre_386_16bit_warned
= false;
3024 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
3029 (void) restore_line_pointer (e
);
3031 switch (cpu_arch
[j
].vsz
)
3037 #ifdef SVR4_COMMENT_CHARS
3038 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3040 if (*input_line_pointer
== '/')
3043 ++input_line_pointer
;
3044 switch (get_absolute_expression ())
3046 case 512: vector_size
= VSZ512
; break;
3047 case 256: vector_size
= VSZ256
; break;
3048 case 128: vector_size
= VSZ128
; break;
3050 as_bad (_("Unrecognized vector size specifier"));
3051 ignore_rest_of_line ();
3058 vector_size
= VSZ_DEFAULT
;
3062 demand_empty_rest_of_line ();
3067 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3069 /* Disable an ISA extension. */
3070 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3071 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3072 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3076 if (cpu_arch
[j
].vsz
== vsz_set
)
3077 vector_size
= VSZ_DEFAULT
;
3079 (void) restore_line_pointer (e
);
3080 demand_empty_rest_of_line ();
3085 if (j
== ARRAY_SIZE (cpu_arch
))
3086 as_bad (_("no such architecture: `%s'"), string
);
3088 *input_line_pointer
= e
;
3090 no_cond_jump_promotion
= 0;
3091 if (*input_line_pointer
== ','
3092 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3094 ++input_line_pointer
;
3095 e
= get_symbol_name (&s
);
3098 if (strcmp (string
, "nojumps") == 0)
3099 no_cond_jump_promotion
= 1;
3100 else if (strcmp (string
, "jumps") == 0)
3103 as_bad (_("no such architecture modifier: `%s'"), string
);
3105 (void) restore_line_pointer (e
);
3108 demand_empty_rest_of_line ();
3111 enum bfd_architecture
3114 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3116 if (!IS_ELF
|| flag_code
== CODE_64BIT
)
3117 as_fatal (_("Intel MCU is 32bit ELF only"));
3118 return bfd_arch_iamcu
;
3121 return bfd_arch_i386
;
3127 if (startswith (default_arch
, "x86_64"))
3129 if (default_arch
[6] == '\0')
3130 return bfd_mach_x86_64
;
3132 return bfd_mach_x64_32
;
3134 else if (!strcmp (default_arch
, "i386")
3135 || !strcmp (default_arch
, "iamcu"))
3137 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3140 as_fatal (_("Intel MCU is 32bit ELF only"));
3141 return bfd_mach_i386_iamcu
;
3144 return bfd_mach_i386_i386
;
3147 as_fatal (_("unknown architecture"));
3150 #include "opcodes/i386-tbl.h"
3153 op_lookup (const char *mnemonic
)
3155 i386_op_off_t
*pos
= str_hash_find (op_hash
, mnemonic
);
3159 current_templates
.start
= &i386_optab
[pos
[0]];
3160 current_templates
.end
= &i386_optab
[pos
[1]];
3163 current_templates
.end
= current_templates
.start
= NULL
;
3169 /* Support pseudo prefixes like {disp32}. */
3170 lex_type
['{'] = LEX_BEGIN_NAME
;
3172 /* Initialize op_hash hash table. */
3173 op_hash
= str_htab_create ();
3176 const i386_op_off_t
*cur
= i386_op_sets
;
3177 const i386_op_off_t
*end
= cur
+ ARRAY_SIZE (i386_op_sets
) - 1;
3179 for (; cur
< end
; ++cur
)
3180 if (str_hash_insert (op_hash
, insn_name (&i386_optab
[*cur
]), cur
, 0))
3181 as_fatal (_("duplicate %s"), insn_name (&i386_optab
[*cur
]));
3184 /* Initialize reg_hash hash table. */
3185 reg_hash
= str_htab_create ();
3187 const reg_entry
*regtab
;
3188 unsigned int regtab_size
= i386_regtab_size
;
3190 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3192 switch (regtab
->reg_type
.bitfield
.class)
3195 if (regtab
->reg_type
.bitfield
.dword
)
3197 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3200 else if (regtab
->reg_type
.bitfield
.tbyte
)
3202 /* There's no point inserting st(<N>) in the hash table, as
3203 parentheses aren't included in register_chars[] anyway. */
3204 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3211 switch (regtab
->reg_num
)
3213 case 0: reg_es
= regtab
; break;
3214 case 2: reg_ss
= regtab
; break;
3215 case 3: reg_ds
= regtab
; break;
3220 if (!regtab
->reg_num
)
3225 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3226 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3230 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3235 for (c
= 0; c
< 256; c
++)
3237 if (ISDIGIT (c
) || ISLOWER (c
))
3239 mnemonic_chars
[c
] = c
;
3240 register_chars
[c
] = c
;
3241 operand_chars
[c
] = c
;
3243 else if (ISUPPER (c
))
3245 mnemonic_chars
[c
] = TOLOWER (c
);
3246 register_chars
[c
] = mnemonic_chars
[c
];
3247 operand_chars
[c
] = c
;
3249 #ifdef SVR4_COMMENT_CHARS
3250 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3251 operand_chars
[c
] = c
;
3255 operand_chars
[c
] = c
;
3258 mnemonic_chars
['_'] = '_';
3259 mnemonic_chars
['-'] = '-';
3260 mnemonic_chars
['.'] = '.';
3262 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3263 operand_chars
[(unsigned char) *p
] = *p
;
3264 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3265 operand_chars
[(unsigned char) *p
] = *p
;
3270 #if defined (OBJ_COFF) && defined (TE_PE)
3271 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3274 x86_dwarf2_return_column
= 16;
3276 x86_cie_data_alignment
= -8;
3277 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3278 x86_sframe_cfa_sp_reg
= REG_SP
;
3279 x86_sframe_cfa_fp_reg
= REG_FP
;
3284 x86_dwarf2_return_column
= 8;
3285 x86_cie_data_alignment
= -4;
3288 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3289 can be turned into BRANCH_PREFIX frag. */
3290 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3295 i386_print_statistics (FILE *file
)
3297 htab_print_statistics (file
, "i386 opcode", op_hash
);
3298 htab_print_statistics (file
, "i386 register", reg_hash
);
3304 htab_delete (op_hash
);
3305 htab_delete (reg_hash
);
3310 /* Debugging routines for md_assemble. */
3311 static void pte (insn_template
*);
3312 static void pt (i386_operand_type
);
3313 static void pe (expressionS
*);
3314 static void ps (symbolS
*);
3317 pi (const char *line
, i386_insn
*x
)
3321 fprintf (stdout
, "%s: template ", line
);
3323 fprintf (stdout
, " address: base %s index %s scale %x\n",
3324 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3325 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3326 x
->log2_scale_factor
);
3327 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3328 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3329 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3330 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3331 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3332 (x
->rex
& REX_W
) != 0,
3333 (x
->rex
& REX_R
) != 0,
3334 (x
->rex
& REX_X
) != 0,
3335 (x
->rex
& REX_B
) != 0);
3336 for (j
= 0; j
< x
->operands
; j
++)
3338 fprintf (stdout
, " #%d: ", j
+ 1);
3340 fprintf (stdout
, "\n");
3341 if (x
->types
[j
].bitfield
.class == Reg
3342 || x
->types
[j
].bitfield
.class == RegMMX
3343 || x
->types
[j
].bitfield
.class == RegSIMD
3344 || x
->types
[j
].bitfield
.class == RegMask
3345 || x
->types
[j
].bitfield
.class == SReg
3346 || x
->types
[j
].bitfield
.class == RegCR
3347 || x
->types
[j
].bitfield
.class == RegDR
3348 || x
->types
[j
].bitfield
.class == RegTR
3349 || x
->types
[j
].bitfield
.class == RegBND
)
3350 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3351 if (operand_type_check (x
->types
[j
], imm
))
3353 if (operand_type_check (x
->types
[j
], disp
))
3354 pe (x
->op
[j
].disps
);
3359 pte (insn_template
*t
)
3361 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3362 static const char *const opc_spc
[] = {
3363 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3364 "XOP08", "XOP09", "XOP0A",
3368 fprintf (stdout
, " %d operands ", t
->operands
);
3369 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3370 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3371 if (opc_spc
[t
->opcode_space
])
3372 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3373 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3374 if (t
->extension_opcode
!= None
)
3375 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3376 if (t
->opcode_modifier
.d
)
3377 fprintf (stdout
, "D");
3378 if (t
->opcode_modifier
.w
)
3379 fprintf (stdout
, "W");
3380 fprintf (stdout
, "\n");
3381 for (j
= 0; j
< t
->operands
; j
++)
3383 fprintf (stdout
, " #%d type ", j
+ 1);
3384 pt (t
->operand_types
[j
]);
3385 fprintf (stdout
, "\n");
3392 fprintf (stdout
, " operation %d\n", e
->X_op
);
3393 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3394 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3395 if (e
->X_add_symbol
)
3397 fprintf (stdout
, " add_symbol ");
3398 ps (e
->X_add_symbol
);
3399 fprintf (stdout
, "\n");
3403 fprintf (stdout
, " op_symbol ");
3404 ps (e
->X_op_symbol
);
3405 fprintf (stdout
, "\n");
3412 fprintf (stdout
, "%s type %s%s",
3414 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3415 segment_name (S_GET_SEGMENT (s
)));
3418 static struct type_name
3420 i386_operand_type mask
;
3423 const type_names
[] =
3425 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3426 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3427 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3428 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3429 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3430 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3431 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3432 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3433 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3434 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3435 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3436 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3437 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3438 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3439 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3440 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3441 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3442 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3443 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3444 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3445 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3446 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3447 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3448 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3449 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3450 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3451 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3452 { { .bitfield
= { .class = SReg
} }, "SReg" },
3453 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3454 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3455 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3456 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3457 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3458 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3462 pt (i386_operand_type t
)
3465 i386_operand_type a
;
3467 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3469 a
= operand_type_and (t
, type_names
[j
].mask
);
3470 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3471 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3476 #endif /* DEBUG386 */
3478 static bfd_reloc_code_real_type
3479 reloc (unsigned int size
,
3482 bfd_reloc_code_real_type other
)
3484 if (other
!= NO_RELOC
)
3486 reloc_howto_type
*rel
;
3491 case BFD_RELOC_X86_64_GOT32
:
3492 return BFD_RELOC_X86_64_GOT64
;
3494 case BFD_RELOC_X86_64_GOTPLT64
:
3495 return BFD_RELOC_X86_64_GOTPLT64
;
3497 case BFD_RELOC_X86_64_PLTOFF64
:
3498 return BFD_RELOC_X86_64_PLTOFF64
;
3500 case BFD_RELOC_X86_64_GOTPC32
:
3501 other
= BFD_RELOC_X86_64_GOTPC64
;
3503 case BFD_RELOC_X86_64_GOTPCREL
:
3504 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3506 case BFD_RELOC_X86_64_TPOFF32
:
3507 other
= BFD_RELOC_X86_64_TPOFF64
;
3509 case BFD_RELOC_X86_64_DTPOFF32
:
3510 other
= BFD_RELOC_X86_64_DTPOFF64
;
3516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3517 if (other
== BFD_RELOC_SIZE32
)
3520 other
= BFD_RELOC_SIZE64
;
3523 as_bad (_("there are no pc-relative size relocations"));
3529 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3530 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3533 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3535 as_bad (_("unknown relocation (%u)"), other
);
3536 else if (size
!= bfd_get_reloc_size (rel
))
3537 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3538 bfd_get_reloc_size (rel
),
3540 else if (pcrel
&& !rel
->pc_relative
)
3541 as_bad (_("non-pc-relative relocation for pc-relative field"));
3542 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3544 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3546 as_bad (_("relocated field and relocation type differ in signedness"));
3555 as_bad (_("there are no unsigned pc-relative relocations"));
3558 case 1: return BFD_RELOC_8_PCREL
;
3559 case 2: return BFD_RELOC_16_PCREL
;
3560 case 4: return BFD_RELOC_32_PCREL
;
3561 case 8: return BFD_RELOC_64_PCREL
;
3563 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3570 case 4: return BFD_RELOC_X86_64_32S
;
3575 case 1: return BFD_RELOC_8
;
3576 case 2: return BFD_RELOC_16
;
3577 case 4: return BFD_RELOC_32
;
3578 case 8: return BFD_RELOC_64
;
3580 as_bad (_("cannot do %s %u byte relocation"),
3581 sign
> 0 ? "signed" : "unsigned", size
);
3587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3588 /* Here we decide which fixups can be adjusted to make them relative to
3589 the beginning of the section instead of the symbol. Basically we need
3590 to make sure that the dynamic relocations are done correctly, so in
3591 some cases we force the original symbol to be used. */
3594 tc_i386_fix_adjustable (fixS
*fixP
)
3599 /* Don't adjust pc-relative references to merge sections in 64-bit
3601 if (use_rela_relocations
3602 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3606 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3607 and changed later by validate_fix. */
3608 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3609 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3612 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3613 for size relocations. */
3614 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3615 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3616 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3617 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3618 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3619 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3620 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3621 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3622 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3623 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3624 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3625 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3626 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3627 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3628 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3629 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3630 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3631 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3632 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3633 || fixP
->fx_r_type
== BFD_RELOC_X86_64_CODE_4_GOTPCRELX
3634 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3635 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3636 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3637 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3638 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3639 || fixP
->fx_r_type
== BFD_RELOC_X86_64_CODE_4_GOTTPOFF
3640 || fixP
->fx_r_type
== BFD_RELOC_X86_64_CODE_6_GOTTPOFF
3641 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3642 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3643 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3644 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3645 || fixP
->fx_r_type
== BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
3646 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3647 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3648 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3655 want_disp32 (const insn_template
*t
)
3657 return flag_code
!= CODE_64BIT
3658 || i
.prefix
[ADDR_PREFIX
]
3659 || (t
->mnem_off
== MN_lea
3660 && (!i
.types
[1].bitfield
.qword
3661 || t
->opcode_modifier
.size
== SIZE32
));
3665 intel_float_operand (const char *mnemonic
)
3667 /* Note that the value returned is meaningful only for opcodes with (memory)
3668 operands, hence the code here is free to improperly handle opcodes that
3669 have no operands (for better performance and smaller code). */
3671 if (mnemonic
[0] != 'f')
3672 return 0; /* non-math */
3674 switch (mnemonic
[1])
3676 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3677 the fs segment override prefix not currently handled because no
3678 call path can make opcodes without operands get here */
3680 return 2 /* integer op */;
3682 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3683 return 3; /* fldcw/fldenv */
3686 if (mnemonic
[2] != 'o' /* fnop */)
3687 return 3; /* non-waiting control op */
3690 if (mnemonic
[2] == 's')
3691 return 3; /* frstor/frstpm */
3694 if (mnemonic
[2] == 'a')
3695 return 3; /* fsave */
3696 if (mnemonic
[2] == 't')
3698 switch (mnemonic
[3])
3700 case 'c': /* fstcw */
3701 case 'd': /* fstdw */
3702 case 'e': /* fstenv */
3703 case 's': /* fsts[gw] */
3709 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3710 return 0; /* fxsave/fxrstor are not really math ops */
3718 install_template (const insn_template
*t
)
3724 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3725 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3727 if ((maybe_cpu (t
, CpuAVX
) || maybe_cpu (t
, CpuAVX2
)
3728 || maybe_cpu (t
, CpuFMA
))
3729 && (maybe_cpu (t
, CpuAVX512F
) || maybe_cpu (t
, CpuAVX512VL
)))
3731 if (need_evex_encoding (t
))
3733 i
.tm
.opcode_modifier
.vex
= 0;
3734 i
.tm
.cpu
.bitfield
.cpuavx512f
= i
.tm
.cpu_any
.bitfield
.cpuavx512f
;
3735 i
.tm
.cpu
.bitfield
.cpuavx512vl
= i
.tm
.cpu_any
.bitfield
.cpuavx512vl
;
3739 i
.tm
.opcode_modifier
.evex
= 0;
3740 if (i
.tm
.cpu_any
.bitfield
.cpuavx
)
3741 i
.tm
.cpu
.bitfield
.cpuavx
= 1;
3742 else if (!i
.tm
.cpu
.bitfield
.isa
)
3743 i
.tm
.cpu
.bitfield
.isa
= i
.tm
.cpu_any
.bitfield
.isa
;
3745 gas_assert (i
.tm
.cpu
.bitfield
.isa
== i
.tm
.cpu_any
.bitfield
.isa
);
3749 if ((maybe_cpu (t
, CpuCMPCCXADD
) || maybe_cpu (t
, CpuAMX_TILE
)
3750 || maybe_cpu (t
, CpuAVX512F
) || maybe_cpu (t
, CpuAVX512DQ
)
3751 || maybe_cpu (t
, CpuAVX512BW
) || maybe_cpu (t
, CpuBMI
)
3752 || maybe_cpu (t
, CpuBMI2
) || maybe_cpu (t
, CpuUSER_MSR
))
3753 && maybe_cpu (t
, CpuAPX_F
))
3755 if (need_evex_encoding (t
))
3756 i
.tm
.opcode_modifier
.vex
= 0;
3758 i
.tm
.opcode_modifier
.evex
= 0;
3762 /* Note that for pseudo prefixes this produces a length of 1. But for them
3763 the length isn't interesting at all. */
3764 for (l
= 1; l
< 4; ++l
)
3765 if (!(t
->base_opcode
>> (8 * l
)))
3768 i
.opcode_length
= l
;
3771 /* Build the VEX prefix. */
3774 build_vex_prefix (const insn_template
*t
)
3776 unsigned int register_specifier
;
3777 unsigned int vector_length
;
3780 /* Check register specifier. */
3781 if (i
.vex
.register_specifier
)
3783 register_specifier
=
3784 ~register_number (i
.vex
.register_specifier
) & 0xf;
3785 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3788 register_specifier
= 0xf;
3790 /* Use 2-byte VEX prefix by swapping destination and source operand
3791 if there are more than 1 register operand. */
3792 if (i
.reg_operands
> 1
3793 && i
.encoding
!= encoding_vex3
3794 && i
.dir_encoding
== dir_encoding_default
3795 && i
.operands
== i
.reg_operands
3796 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3797 && i
.tm
.opcode_space
== SPACE_0F
3798 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3803 swap_2_operands (0, i
.operands
- 1);
3805 gas_assert (i
.rm
.mode
== 3);
3809 i
.rm
.regmem
= i
.rm
.reg
;
3812 if (i
.tm
.opcode_modifier
.d
)
3813 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3814 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3815 else /* Use the next insn. */
3816 install_template (&t
[1]);
3819 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3820 are no memory operands and at least 3 register ones. */
3821 if (i
.reg_operands
>= 3
3822 && i
.encoding
!= encoding_vex3
3823 && i
.reg_operands
== i
.operands
- i
.imm_operands
3824 && i
.tm
.opcode_modifier
.vex
3825 && i
.tm
.opcode_modifier
.commutative
3826 /* .commutative aliases .staticrounding; disambiguate. */
3827 && !i
.tm
.opcode_modifier
.sae
3828 && (i
.tm
.opcode_modifier
.sse2avx
3829 || (optimize
> 1 && !i
.no_optimize
))
3831 && i
.vex
.register_specifier
3832 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3834 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3836 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3837 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3838 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3839 &i
.types
[i
.operands
- 3]));
3840 gas_assert (i
.rm
.mode
== 3);
3842 swap_2_operands (xchg
, xchg
+ 1);
3845 xchg
= i
.rm
.regmem
| 8;
3846 i
.rm
.regmem
= ~register_specifier
& 0xf;
3847 gas_assert (!(i
.rm
.regmem
& 8));
3848 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3849 register_specifier
= ~xchg
& 0xf;
3852 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3853 vector_length
= avxscalar
;
3854 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3856 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3862 /* Determine vector length from the last multi-length vector
3865 for (op
= t
->operands
; op
--;)
3866 if (t
->operand_types
[op
].bitfield
.xmmword
3867 && t
->operand_types
[op
].bitfield
.ymmword
3868 && i
.types
[op
].bitfield
.ymmword
)
3875 /* Check the REX.W bit and VEXW. */
3876 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3877 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3878 else if (i
.tm
.opcode_modifier
.vexw
&& !(i
.rex
& REX_W
))
3879 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3881 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3883 /* Use 2-byte VEX prefix if possible. */
3885 && i
.encoding
!= encoding_vex3
3886 && i
.tm
.opcode_space
== SPACE_0F
3887 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3889 /* 2-byte VEX prefix. */
3893 i
.vex
.bytes
[0] = 0xc5;
3895 /* Check the REX.R bit. */
3896 r
= (i
.rex
& REX_R
) ? 0 : 1;
3897 i
.vex
.bytes
[1] = (r
<< 7
3898 | register_specifier
<< 3
3899 | vector_length
<< 2
3900 | i
.tm
.opcode_modifier
.opcodeprefix
);
3904 /* 3-byte VEX prefix. */
3907 switch (i
.tm
.opcode_space
)
3913 i
.vex
.bytes
[0] = 0xc4;
3918 i
.vex
.bytes
[0] = 0x8f;
3924 /* The high 3 bits of the second VEX byte are 1's compliment
3925 of RXB bits from REX. */
3926 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3927 | (!dot_insn () ? i
.tm
.opcode_space
3928 : i
.insn_opcode_space
);
3930 i
.vex
.bytes
[2] = (w
<< 7
3931 | register_specifier
<< 3
3932 | vector_length
<< 2
3933 | i
.tm
.opcode_modifier
.opcodeprefix
);
3938 is_any_vex_encoding (const insn_template
*t
)
3940 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.evex
;
3943 /* We can use this function only when the current encoding is evex. */
3945 is_apx_evex_encoding (void)
3947 return i
.rex2
|| i
.tm
.opcode_space
== SPACE_EVEXMAP4
3948 || (i
.vex
.register_specifier
3949 && (i
.vex
.register_specifier
->reg_flags
& RegRex2
));
3953 is_apx_rex2_encoding (void)
3955 return i
.rex2
|| i
.rex2_encoding
3956 || i
.tm
.opcode_modifier
.rex2
;
3960 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3962 unsigned int op
, bytes
;
3963 const i386_operand_type
*types
;
3965 if (i
.broadcast
.type
)
3966 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3968 gas_assert (intel_syntax
);
3970 for (op
= 0; op
< t
->operands
; ++op
)
3971 if (t
->operand_types
[op
].bitfield
.baseindex
)
3974 gas_assert (op
< t
->operands
);
3976 if (t
->opcode_modifier
.evex
!= EVEXDYN
)
3977 switch (i
.broadcast
.bytes
)
3980 if (t
->operand_types
[op
].bitfield
.word
)
3984 if (t
->operand_types
[op
].bitfield
.dword
)
3988 if (t
->operand_types
[op
].bitfield
.qword
)
3992 if (t
->operand_types
[op
].bitfield
.xmmword
)
3994 if (t
->operand_types
[op
].bitfield
.ymmword
)
3996 if (t
->operand_types
[op
].bitfield
.zmmword
)
4003 gas_assert (op
+ 1 < t
->operands
);
4005 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
4006 + t
->operand_types
[op
+ 1].bitfield
.ymmword
4007 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
4009 types
= &i
.types
[op
+ 1];
4012 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
4013 types
= &t
->operand_types
[op
];
4015 if (types
->bitfield
.zmmword
)
4017 else if (types
->bitfield
.ymmword
)
4023 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
4024 insn_name (t
), bytes
* 8);
4029 /* Build the EVEX prefix. */
4032 build_evex_prefix (void)
4034 unsigned int register_specifier
, w
;
4035 rex_byte vrex_used
= 0;
4037 /* Check register specifier. */
4038 if (i
.vex
.register_specifier
)
4040 gas_assert ((i
.vrex
& REX_X
) == 0);
4042 register_specifier
= i
.vex
.register_specifier
->reg_num
;
4043 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
4044 register_specifier
+= 8;
4045 /* The upper 16 registers are encoded in the fourth byte of the
4047 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
4048 i
.vex
.bytes
[3] = 0x8;
4049 register_specifier
= ~register_specifier
& 0xf;
4053 register_specifier
= 0xf;
4055 /* Encode upper 16 vector index register in the fourth byte of
4057 if (!(i
.vrex
& REX_X
))
4058 i
.vex
.bytes
[3] = 0x8;
4063 /* 4 byte EVEX prefix. */
4065 i
.vex
.bytes
[0] = 0x62;
4067 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4069 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
4070 gas_assert (i
.tm
.opcode_space
<= SPACE_VEXMAP7
);
4071 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
4072 | (!dot_insn () ? i
.tm
.opcode_space
4073 : i
.insn_opcode_space
);
4075 /* The fifth bit of the second EVEX byte is 1's compliment of the
4076 REX_R bit in VREX. */
4077 if (!(i
.vrex
& REX_R
))
4078 i
.vex
.bytes
[1] |= 0x10;
4082 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4084 /* When all operands are registers, the REX_X bit in REX is not
4085 used. We reuse it to encode the upper 16 registers, which is
4086 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4087 as 1's compliment. */
4088 if ((i
.vrex
& REX_B
))
4091 i
.vex
.bytes
[1] &= ~0x40;
4095 /* EVEX instructions shouldn't need the REX prefix. */
4096 i
.vrex
&= ~vrex_used
;
4097 gas_assert (i
.vrex
== 0);
4099 /* Check the REX.W bit and VEXW. */
4100 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4101 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4102 else if (i
.tm
.opcode_modifier
.vexw
)
4103 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4105 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4107 /* The third byte of the EVEX prefix. */
4108 i
.vex
.bytes
[2] = ((w
<< 7)
4109 | (register_specifier
<< 3)
4110 | 4 /* Encode the U bit. */
4111 | i
.tm
.opcode_modifier
.opcodeprefix
);
4113 /* The fourth byte of the EVEX prefix. */
4114 /* The zeroing-masking bit. */
4115 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4116 i
.vex
.bytes
[3] |= 0x80;
4118 /* Don't always set the broadcast bit if there is no RC. */
4119 if (i
.rounding
.type
== rc_none
)
4121 /* Encode the vector length. */
4122 unsigned int vec_length
;
4124 if (i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4128 /* Determine vector length from the last multi-length vector
4130 for (op
= i
.operands
; op
--;)
4131 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4132 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4133 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4135 if (i
.types
[op
].bitfield
.zmmword
)
4137 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4140 else if (i
.types
[op
].bitfield
.ymmword
)
4142 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4145 else if (i
.types
[op
].bitfield
.xmmword
)
4147 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4150 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4151 && op
== i
.broadcast
.operand
)
4153 switch (get_broadcast_bytes (&i
.tm
, true))
4156 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4159 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4162 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4171 if (op
>= MAX_OPERANDS
)
4175 switch (i
.tm
.opcode_modifier
.evex
)
4177 case EVEXLIG
: /* LL' is ignored */
4178 vec_length
= evexlig
<< 5;
4181 vec_length
= 0 << 5;
4184 vec_length
= 1 << 5;
4187 vec_length
= 2 << 5;
4192 vec_length
= 3 << 5;
4200 i
.vex
.bytes
[3] |= vec_length
;
4201 /* Encode the broadcast bit. */
4202 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4203 i
.vex
.bytes
[3] |= 0x10;
4205 else if (i
.rounding
.type
!= saeonly
)
4206 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4208 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4211 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4214 /* Build (2 bytes) rex2 prefix.
4216 | m | R4 X4 B4 | W R X B |
4218 Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes.
4221 build_rex2_prefix (void)
4224 i
.vex
.bytes
[0] = 0xd5;
4225 /* For the W R X B bits, the variables of rex prefix will be reused. */
4226 i
.vex
.bytes
[1] = ((i
.tm
.opcode_space
<< 7)
4227 | (i
.rex2
<< 4) | i
.rex
);
4230 /* Build the EVEX prefix (4-byte) for evex insn
4232 | `R`X`B`R' | B'mmm |
4233 | W | v`v`v`v | `x' | pp |
4234 | z| L'L | b | `v | aaa |
4237 build_apx_evex_prefix (void)
4239 build_evex_prefix ();
4241 i
.vex
.bytes
[1] &= ~0x10;
4243 i
.vex
.bytes
[1] |= 0x08;
4245 i
.vex
.bytes
[2] &= ~0x04;
4246 if (i
.vex
.register_specifier
4247 && i
.vex
.register_specifier
->reg_flags
& RegRex2
)
4248 i
.vex
.bytes
[3] &= ~0x08;
4250 /* Encode the NDD bit of the instruction promoted from the legacy
4252 if (i
.vex
.register_specifier
&& i
.tm
.opcode_space
== SPACE_EVEXMAP4
)
4253 i
.vex
.bytes
[3] |= 0x10;
4256 static void establish_rex (void)
4258 /* Note that legacy encodings have at most 2 non-immediate operands. */
4259 unsigned int first
= i
.imm_operands
;
4260 unsigned int last
= i
.operands
> first
? i
.operands
- first
- 1 : first
;
4262 /* Respect a user-specified REX prefix. */
4263 i
.rex
|= i
.prefix
[REX_PREFIX
] & REX_OPCODE
;
4265 /* For 8 bit registers we need an empty rex prefix. Also if the
4266 instruction already has a prefix, we need to convert old
4267 registers to new ones. */
4269 if ((i
.types
[first
].bitfield
.class == Reg
&& i
.types
[first
].bitfield
.byte
4270 && ((i
.op
[first
].regs
->reg_flags
& RegRex64
) != 0 || i
.rex
!= 0
4272 || (i
.types
[last
].bitfield
.class == Reg
&& i
.types
[last
].bitfield
.byte
4273 && ((i
.op
[last
].regs
->reg_flags
& RegRex64
) != 0 || i
.rex
!= 0
4278 if (!is_apx_rex2_encoding () && !is_any_vex_encoding(&i
.tm
))
4279 i
.rex
|= REX_OPCODE
;
4280 for (x
= first
; x
<= last
; x
++)
4282 /* Look for 8 bit operand that uses old registers. */
4283 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4284 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4286 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4287 /* In case it is "hi" register, give up. */
4288 if (i
.op
[x
].regs
->reg_num
> 3)
4289 as_bad (_("can't encode register '%s%s' in an "
4290 "instruction requiring REX/REX2 prefix"),
4291 register_prefix
, i
.op
[x
].regs
->reg_name
);
4293 /* Otherwise it is equivalent to the extended register.
4294 Since the encoding doesn't change this is merely
4295 cosmetic cleanup for debug output. */
4301 if (i
.rex
== 0 && i
.rex2
== 0 && (i
.rex_encoding
|| i
.rex2_encoding
))
4303 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4304 that uses legacy register. If it is "hi" register, don't add
4305 rex and rex2 prefix. */
4308 for (x
= first
; x
<= last
; x
++)
4309 if (i
.types
[x
].bitfield
.class == Reg
4310 && i
.types
[x
].bitfield
.byte
4311 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4312 && i
.op
[x
].regs
->reg_num
> 3)
4314 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4315 i
.rex_encoding
= false;
4316 i
.rex2_encoding
= false;
4324 if (is_apx_rex2_encoding ())
4326 build_rex2_prefix ();
4327 /* The individual REX.RXBW bits got consumed. */
4328 i
.rex
&= REX_OPCODE
;
4330 else if (i
.rex
!= 0)
4331 add_prefix (REX_OPCODE
| i
.rex
);
4335 process_immext (void)
4339 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4340 which is coded in the same place as an 8-bit immediate field
4341 would be. Here we fake an 8-bit immediate operand from the
4342 opcode suffix stored in tm.extension_opcode.
4344 AVX instructions also use this encoding, for some of
4345 3 argument instructions. */
4347 gas_assert (i
.imm_operands
<= 1
4349 || (is_any_vex_encoding (&i
.tm
)
4350 && i
.operands
<= 4)));
4352 exp
= &im_expressions
[i
.imm_operands
++];
4353 i
.op
[i
.operands
].imms
= exp
;
4354 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4356 exp
->X_op
= O_constant
;
4357 exp
->X_add_number
= i
.tm
.extension_opcode
;
4358 i
.tm
.extension_opcode
= None
;
4365 switch (i
.tm
.opcode_modifier
.prefixok
)
4373 as_bad (_("invalid instruction `%s' after `%s'"),
4374 insn_name (&i
.tm
), i
.hle_prefix
);
4377 if (i
.prefix
[LOCK_PREFIX
])
4379 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4383 case PrefixHLERelease
:
4384 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4386 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4390 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4392 as_bad (_("memory destination needed for instruction `%s'"
4393 " after `xrelease'"), insn_name (&i
.tm
));
4400 /* Encode aligned vector move as unaligned vector move. */
4403 encode_with_unaligned_vector_move (void)
4405 switch (i
.tm
.base_opcode
)
4407 case 0x28: /* Load instructions. */
4408 case 0x29: /* Store instructions. */
4409 /* movaps/movapd/vmovaps/vmovapd. */
4410 if (i
.tm
.opcode_space
== SPACE_0F
4411 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4412 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4414 case 0x6f: /* Load instructions. */
4415 case 0x7f: /* Store instructions. */
4416 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4417 if (i
.tm
.opcode_space
== SPACE_0F
4418 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4419 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4426 /* Try the shortest encoding by shortening operand size. */
4429 optimize_encoding (void)
4433 if (i
.tm
.mnem_off
== MN_lea
)
4436 lea symbol, %rN -> mov $symbol, %rN
4437 lea (%rM), %rN -> mov %rM, %rN
4438 lea (,%rM,1), %rN -> mov %rM, %rN
4440 and in 32-bit mode for 16-bit addressing
4442 lea (%rM), %rN -> movzx %rM, %rN
4444 and in 64-bit mode zap 32-bit addressing in favor of using a
4445 32-bit (or less) destination.
4447 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4449 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4450 i
.tm
.opcode_modifier
.size
= SIZE32
;
4451 i
.prefix
[ADDR_PREFIX
] = 0;
4454 if (!i
.index_reg
&& !i
.base_reg
)
4457 lea symbol, %rN -> mov $symbol, %rN
4459 if (flag_code
== CODE_64BIT
)
4461 /* Don't transform a relocation to a 16-bit one. */
4463 && i
.op
[0].disps
->X_op
!= O_constant
4464 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4467 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4468 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4470 i
.tm
.base_opcode
= 0xb8;
4471 i
.tm
.opcode_modifier
.modrm
= 0;
4472 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4473 i
.types
[0].bitfield
.imm32
= 1;
4476 i
.tm
.opcode_modifier
.size
= SIZE16
;
4477 i
.types
[0].bitfield
.imm16
= 1;
4482 /* Subject to further optimization below. */
4483 i
.tm
.base_opcode
= 0xc7;
4484 i
.tm
.extension_opcode
= 0;
4485 i
.types
[0].bitfield
.imm32s
= 1;
4486 i
.types
[0].bitfield
.baseindex
= 0;
4489 /* Outside of 64-bit mode address and operand sizes have to match if
4490 a relocation is involved, as otherwise we wouldn't (currently) or
4491 even couldn't express the relocation correctly. */
4492 else if (i
.op
[0].disps
4493 && i
.op
[0].disps
->X_op
!= O_constant
4494 && ((!i
.prefix
[ADDR_PREFIX
])
4495 != (flag_code
== CODE_32BIT
4496 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4497 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4499 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4500 destination is going to grow encoding size. */
4501 else if (flag_code
== CODE_16BIT
4502 && (optimize
<= 1 || optimize_for_space
)
4503 && !i
.prefix
[ADDR_PREFIX
]
4504 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4508 i
.tm
.base_opcode
= 0xb8;
4509 i
.tm
.opcode_modifier
.modrm
= 0;
4510 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4511 i
.types
[0].bitfield
.imm32
= 1;
4513 i
.types
[0].bitfield
.imm16
= 1;
4516 && i
.op
[0].disps
->X_op
== O_constant
4517 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4518 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4520 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4521 i
.op
[0].disps
->X_add_number
&= 0xffff;
4524 i
.tm
.operand_types
[0] = i
.types
[0];
4528 i
.op
[0].imms
= &im_expressions
[0];
4529 i
.op
[0].imms
->X_op
= O_absent
;
4532 else if (i
.op
[0].disps
4533 && (i
.op
[0].disps
->X_op
!= O_constant
4534 || i
.op
[0].disps
->X_add_number
))
4539 lea (%rM), %rN -> mov %rM, %rN
4540 lea (,%rM,1), %rN -> mov %rM, %rN
4541 lea (%rM), %rN -> movzx %rM, %rN
4543 const reg_entry
*addr_reg
;
4545 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4546 addr_reg
= i
.base_reg
;
4547 else if (!i
.base_reg
4548 && i
.index_reg
->reg_num
!= RegIZ
4549 && !i
.log2_scale_factor
)
4550 addr_reg
= i
.index_reg
;
4554 if (addr_reg
->reg_type
.bitfield
.word
4555 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4557 if (flag_code
!= CODE_32BIT
)
4559 i
.tm
.opcode_space
= SPACE_0F
;
4560 i
.tm
.base_opcode
= 0xb7;
4563 i
.tm
.base_opcode
= 0x8b;
4565 if (addr_reg
->reg_type
.bitfield
.dword
4566 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4567 i
.tm
.opcode_modifier
.size
= SIZE32
;
4569 i
.op
[0].regs
= addr_reg
;
4574 i
.disp_operands
= 0;
4575 i
.prefix
[ADDR_PREFIX
] = 0;
4576 i
.prefix
[SEG_PREFIX
] = 0;
4580 if (optimize_for_space
4581 && i
.tm
.mnem_off
== MN_test
4582 && i
.reg_operands
== 1
4583 && i
.imm_operands
== 1
4584 && !i
.types
[1].bitfield
.byte
4585 && i
.op
[0].imms
->X_op
== O_constant
4586 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4589 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4591 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4592 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4594 i
.types
[1].bitfield
.byte
= 1;
4595 /* Ignore the suffix. */
4597 /* Convert to byte registers. 8-bit registers are special,
4598 RegRex64 and non-RegRex64 each have 8 registers. */
4599 if (i
.types
[1].bitfield
.word
)
4600 /* 32 (or 40) 8-bit registers. */
4602 else if (i
.types
[1].bitfield
.dword
)
4603 /* 32 (or 40) 8-bit registers + 32 16-bit registers. */
4606 /* 32 (or 40) 8-bit registers + 32 16-bit registers
4607 + 32 32-bit registers. */
4610 /* In 64-bit mode, the following byte registers cannot be accessed
4611 if using the Rex and Rex2 prefix: AH, BH, CH, DH */
4612 if (!(i
.op
[1].regs
->reg_flags
& (RegRex
| RegRex2
)) && base_regnum
< 4)
4617 else if (flag_code
== CODE_64BIT
4618 && i
.tm
.opcode_space
== SPACE_BASE
4619 && ((i
.types
[1].bitfield
.qword
4620 && i
.reg_operands
== 1
4621 && i
.imm_operands
== 1
4622 && i
.op
[0].imms
->X_op
== O_constant
4623 && ((i
.tm
.base_opcode
== 0xb8
4624 && i
.tm
.extension_opcode
== None
4625 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4626 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4627 && (i
.tm
.base_opcode
== 0x24
4628 || (i
.tm
.base_opcode
== 0x80
4629 && i
.tm
.extension_opcode
== 0x4)
4630 || i
.tm
.mnem_off
== MN_test
4631 || ((i
.tm
.base_opcode
| 1) == 0xc7
4632 && i
.tm
.extension_opcode
== 0x0)))
4633 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4634 && i
.tm
.base_opcode
== 0x83
4635 && i
.tm
.extension_opcode
== 0x4)))
4636 || (i
.types
[0].bitfield
.qword
4637 && ((i
.reg_operands
== 2
4638 && i
.op
[0].regs
== i
.op
[1].regs
4639 && (i
.tm
.mnem_off
== MN_xor
4640 || i
.tm
.mnem_off
== MN_sub
))
4641 || i
.tm
.mnem_off
== MN_clr
))))
4644 andq $imm31, %r64 -> andl $imm31, %r32
4645 andq $imm7, %r64 -> andl $imm7, %r32
4646 testq $imm31, %r64 -> testl $imm31, %r32
4647 xorq %r64, %r64 -> xorl %r32, %r32
4648 subq %r64, %r64 -> subl %r32, %r32
4649 movq $imm31, %r64 -> movl $imm31, %r32
4650 movq $imm32, %r64 -> movl $imm32, %r32
4652 i
.tm
.opcode_modifier
.size
= SIZE32
;
4655 i
.types
[0].bitfield
.imm32
= 1;
4656 i
.types
[0].bitfield
.imm32s
= 0;
4657 i
.types
[0].bitfield
.imm64
= 0;
4661 i
.types
[0].bitfield
.dword
= 1;
4662 i
.types
[0].bitfield
.qword
= 0;
4664 i
.types
[1].bitfield
.dword
= 1;
4665 i
.types
[1].bitfield
.qword
= 0;
4666 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4669 movq $imm31, %r64 -> movl $imm31, %r32
4670 movq $imm32, %r64 -> movl $imm32, %r32
4672 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4673 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4674 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4675 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4678 movq $imm31, %r64 -> movl $imm31, %r32
4680 i
.tm
.base_opcode
= 0xb8;
4681 i
.tm
.extension_opcode
= None
;
4682 i
.tm
.opcode_modifier
.w
= 0;
4683 i
.tm
.opcode_modifier
.modrm
= 0;
4687 else if (i
.reg_operands
== 3
4688 && i
.op
[0].regs
== i
.op
[1].regs
4689 && i
.encoding
!= encoding_evex
4690 && (i
.tm
.mnem_off
== MN_xor
4691 || i
.tm
.mnem_off
== MN_sub
))
4694 xorb %rNb, %rNb, %rMb -> xorl %rMd, %rMd
4695 xorw %rNw, %rNw, %rMw -> xorl %rMd, %rMd
4696 xorl %rNd, %rNd, %rMd -> xorl %rMd, %rMd
4697 xorq %rN, %rN, %rM -> xorl %rMd, %rMd
4698 subb %rNb, %rNb, %rMb -> subl %rMd, %rMd
4699 subw %rNw, %rNw, %rMw -> subl %rMd, %rMd
4700 subl %rNd, %rNd, %rMd -> subl %rMd, %rMd
4701 subq %rN, %rN, %rM -> subl %rMd, %rMd
4703 i
.tm
.opcode_space
= SPACE_BASE
;
4704 i
.tm
.opcode_modifier
.evex
= 0;
4705 i
.tm
.opcode_modifier
.size
= SIZE32
;
4706 i
.types
[0].bitfield
.byte
= 0;
4707 i
.types
[0].bitfield
.word
= 0;
4708 i
.types
[0].bitfield
.dword
= 1;
4709 i
.types
[0].bitfield
.qword
= 0;
4710 i
.op
[0].regs
= i
.op
[2].regs
;
4711 i
.types
[1] = i
.types
[0];
4712 i
.op
[1].regs
= i
.op
[2].regs
;
4715 else if (optimize
> 1
4716 && !optimize_for_space
4717 && i
.reg_operands
== 2
4718 && i
.op
[0].regs
== i
.op
[1].regs
4719 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4720 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4723 andb %rN, %rN -> testb %rN, %rN
4724 andw %rN, %rN -> testw %rN, %rN
4725 andq %rN, %rN -> testq %rN, %rN
4726 orb %rN, %rN -> testb %rN, %rN
4727 orw %rN, %rN -> testw %rN, %rN
4728 orq %rN, %rN -> testq %rN, %rN
4730 and outside of 64-bit mode
4732 andl %rN, %rN -> testl %rN, %rN
4733 orl %rN, %rN -> testl %rN, %rN
4735 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4737 else if (i
.tm
.base_opcode
== 0xba
4738 && i
.tm
.opcode_space
== SPACE_0F
4739 && i
.reg_operands
== 1
4740 && i
.op
[0].imms
->X_op
== O_constant
4741 && i
.op
[0].imms
->X_add_number
>= 0)
4744 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4745 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4746 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4748 With <BT> one of bts, btr, and bts also:
4749 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4750 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4755 if (i
.tm
.extension_opcode
!= 4)
4757 if (i
.types
[1].bitfield
.qword
4758 && i
.op
[0].imms
->X_add_number
< 32
4759 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4760 i
.tm
.opcode_modifier
.size
= SIZE32
;
4763 if (i
.types
[1].bitfield
.word
4764 && i
.op
[0].imms
->X_add_number
< 16)
4765 i
.tm
.opcode_modifier
.size
= SIZE32
;
4768 if (i
.op
[0].imms
->X_add_number
< 16)
4769 i
.tm
.opcode_modifier
.size
= SIZE16
;
4773 else if (i
.reg_operands
== 3
4774 && i
.op
[0].regs
== i
.op
[1].regs
4775 && !i
.types
[2].bitfield
.xmmword
4776 && (i
.tm
.opcode_modifier
.vex
4777 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4778 && i
.tm
.opcode_modifier
.evex
4779 && (i
.encoding
!= encoding_evex
4780 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4781 || is_cpu (&i
.tm
, CpuAVX512VL
)
4782 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4783 && i
.types
[2].bitfield
.ymmword
))))
4784 && i
.tm
.opcode_space
== SPACE_0F
4785 && ((i
.tm
.base_opcode
| 2) == 0x57
4786 || i
.tm
.base_opcode
== 0xdf
4787 || i
.tm
.base_opcode
== 0xef
4788 || (i
.tm
.base_opcode
| 3) == 0xfb
4789 || i
.tm
.base_opcode
== 0x42
4790 || i
.tm
.base_opcode
== 0x47))
4793 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4795 EVEX VOP %zmmM, %zmmM, %zmmN
4796 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4797 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4798 EVEX VOP %ymmM, %ymmM, %ymmN
4799 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4800 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4801 VEX VOP %ymmM, %ymmM, %ymmN
4802 -> VEX VOP %xmmM, %xmmM, %xmmN
4803 VOP, one of vpandn and vpxor:
4804 VEX VOP %ymmM, %ymmM, %ymmN
4805 -> VEX VOP %xmmM, %xmmM, %xmmN
4806 VOP, one of vpandnd and vpandnq:
4807 EVEX VOP %zmmM, %zmmM, %zmmN
4808 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4809 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4810 EVEX VOP %ymmM, %ymmM, %ymmN
4811 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4812 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4813 VOP, one of vpxord and vpxorq:
4814 EVEX VOP %zmmM, %zmmM, %zmmN
4815 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4816 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4817 EVEX VOP %ymmM, %ymmM, %ymmN
4818 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4819 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4820 VOP, one of kxord and kxorq:
4821 VEX VOP %kM, %kM, %kN
4822 -> VEX kxorw %kM, %kM, %kN
4823 VOP, one of kandnd and kandnq:
4824 VEX VOP %kM, %kM, %kN
4825 -> VEX kandnw %kM, %kM, %kN
4827 if (i
.tm
.opcode_modifier
.evex
)
4829 if (i
.encoding
!= encoding_evex
)
4831 i
.tm
.opcode_modifier
.vex
= VEX128
;
4832 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4833 i
.tm
.opcode_modifier
.evex
= 0;
4834 i
.encoding
= encoding_vex
;
4837 else if (optimize
> 1)
4838 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4842 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4844 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4845 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4848 i
.tm
.opcode_modifier
.vex
= VEX128
;
4850 if (i
.tm
.opcode_modifier
.vex
)
4851 for (j
= 0; j
< 3; j
++)
4853 i
.types
[j
].bitfield
.xmmword
= 1;
4854 i
.types
[j
].bitfield
.ymmword
= 0;
4857 else if (i
.encoding
!= encoding_evex
4858 && i
.encoding
!= encoding_egpr
4859 && !i
.types
[0].bitfield
.zmmword
4860 && !i
.types
[1].bitfield
.zmmword
4862 && !i
.broadcast
.type
4863 && !i
.broadcast
.bytes
4864 && i
.tm
.opcode_modifier
.evex
4865 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4866 || (i
.tm
.base_opcode
& ~4) == 0xdb
4867 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4868 && i
.tm
.extension_opcode
== None
)
4871 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4872 vmovdqu32 and vmovdqu64:
4873 EVEX VOP %xmmM, %xmmN
4874 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4875 EVEX VOP %ymmM, %ymmN
4876 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4878 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4880 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4882 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4884 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4885 VOP, one of vpand, vpandn, vpor, vpxor:
4886 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4887 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4888 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4889 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4890 EVEX VOP{d,q} mem, %xmmM, %xmmN
4891 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4892 EVEX VOP{d,q} mem, %ymmM, %ymmN
4893 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4895 for (j
= 0; j
< i
.operands
; j
++)
4896 if (operand_type_check (i
.types
[j
], disp
)
4897 && i
.op
[j
].disps
->X_op
== O_constant
)
4899 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4900 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4901 bytes, we choose EVEX Disp8 over VEX Disp32. */
4902 int evex_disp8
, vex_disp8
;
4903 unsigned int memshift
= i
.memshift
;
4904 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4906 evex_disp8
= fits_in_disp8 (n
);
4908 vex_disp8
= fits_in_disp8 (n
);
4909 if (evex_disp8
!= vex_disp8
)
4911 i
.memshift
= memshift
;
4915 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4918 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4919 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4920 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4921 i
.tm
.opcode_modifier
.vex
4922 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4923 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4924 /* VPAND, VPOR, and VPXOR are commutative. */
4925 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4926 i
.tm
.opcode_modifier
.commutative
= 1;
4927 i
.tm
.opcode_modifier
.evex
= 0;
4928 i
.tm
.opcode_modifier
.masking
= 0;
4929 i
.tm
.opcode_modifier
.broadcast
= 0;
4930 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4933 i
.types
[j
].bitfield
.disp8
4934 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4936 else if (optimize_for_space
4937 && i
.tm
.base_opcode
== 0x29
4938 && i
.tm
.opcode_space
== SPACE_0F38
4939 && i
.operands
== i
.reg_operands
4940 && i
.op
[0].regs
== i
.op
[1].regs
4941 && (!i
.tm
.opcode_modifier
.vex
4942 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4943 && !i
.tm
.opcode_modifier
.evex
)
4946 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4947 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4948 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4950 i
.tm
.opcode_space
= SPACE_0F
;
4951 i
.tm
.base_opcode
= 0x76;
4953 else if (((i
.tm
.base_opcode
>= 0x64
4954 && i
.tm
.base_opcode
<= 0x66
4955 && i
.tm
.opcode_space
== SPACE_0F
)
4956 || (i
.tm
.base_opcode
== 0x37
4957 && i
.tm
.opcode_space
== SPACE_0F38
))
4958 && i
.operands
== i
.reg_operands
4959 && i
.op
[0].regs
== i
.op
[1].regs
4960 && !i
.tm
.opcode_modifier
.evex
)
4963 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4964 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4965 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4966 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4967 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4968 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4970 i
.tm
.opcode_space
= SPACE_0F
;
4971 i
.tm
.base_opcode
= 0xef;
4972 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4974 if (i
.operands
== 2)
4976 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4982 i
.op
[2].regs
= i
.op
[0].regs
;
4983 i
.types
[2] = i
.types
[0];
4984 i
.flags
[2] = i
.flags
[0];
4985 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4987 i
.tm
.opcode_modifier
.sse2avx
= 0;
4989 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4990 i
.op
[1].regs
= i
.op
[0].regs
;
4993 else if (optimize_for_space
4994 && i
.tm
.base_opcode
== 0x59
4995 && i
.tm
.opcode_space
== SPACE_0F38
4996 && i
.operands
== i
.reg_operands
4997 && i
.tm
.opcode_modifier
.vex
4998 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4999 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
5000 && i
.encoding
!= encoding_vex3
)
5003 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
5005 i
.tm
.opcode_space
= SPACE_0F
;
5006 i
.tm
.base_opcode
= 0x6c;
5007 i
.tm
.opcode_modifier
.vexvvvv
= 1;
5013 i
.op
[2].regs
= i
.op
[0].regs
;
5014 i
.types
[2] = i
.types
[0];
5015 i
.flags
[2] = i
.flags
[0];
5016 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
5018 swap_2_operands (1, 2);
5023 s_noopt (int dummy ATTRIBUTE_UNUSED
)
5025 if (!is_it_end_of_statement ())
5026 as_warn (_("`.noopt' arguments ignored"));
5029 optimize_for_space
= 0;
5031 ignore_rest_of_line ();
5034 /* Return non-zero for load instruction. */
5040 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
5041 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
5045 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
5046 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
5047 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
5051 if (i
.tm
.mnem_off
== MN_pop
)
5055 if (i
.tm
.opcode_space
== SPACE_BASE
)
5058 if (i
.tm
.base_opcode
== 0x9d
5059 || i
.tm
.base_opcode
== 0x61)
5062 /* movs, cmps, lods, scas. */
5063 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
5067 if (base_opcode
== 0x6f
5068 || i
.tm
.base_opcode
== 0xd7)
5070 /* NB: For AMD-specific insns with implicit memory operands,
5071 they're intentionally not covered. */
5074 /* No memory operand. */
5075 if (!i
.mem_operands
)
5080 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
5083 else if (i
.tm
.opcode_space
== SPACE_BASE
)
5085 /* test, not, neg, mul, imul, div, idiv. */
5086 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
5090 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
5093 /* add, or, adc, sbb, and, sub, xor, cmp. */
5094 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
5097 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
5098 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
5099 && i
.tm
.extension_opcode
!= 6)
5102 /* Check for x87 instructions. */
5103 if ((base_opcode
| 6) == 0xdf)
5105 /* Skip fst, fstp, fstenv, fstcw. */
5106 if (i
.tm
.base_opcode
== 0xd9
5107 && (i
.tm
.extension_opcode
== 2
5108 || i
.tm
.extension_opcode
== 3
5109 || i
.tm
.extension_opcode
== 6
5110 || i
.tm
.extension_opcode
== 7))
5113 /* Skip fisttp, fist, fistp, fstp. */
5114 if (i
.tm
.base_opcode
== 0xdb
5115 && (i
.tm
.extension_opcode
== 1
5116 || i
.tm
.extension_opcode
== 2
5117 || i
.tm
.extension_opcode
== 3
5118 || i
.tm
.extension_opcode
== 7))
5121 /* Skip fisttp, fst, fstp, fsave, fstsw. */
5122 if (i
.tm
.base_opcode
== 0xdd
5123 && (i
.tm
.extension_opcode
== 1
5124 || i
.tm
.extension_opcode
== 2
5125 || i
.tm
.extension_opcode
== 3
5126 || i
.tm
.extension_opcode
== 6
5127 || i
.tm
.extension_opcode
== 7))
5130 /* Skip fisttp, fist, fistp, fbstp, fistp. */
5131 if (i
.tm
.base_opcode
== 0xdf
5132 && (i
.tm
.extension_opcode
== 1
5133 || i
.tm
.extension_opcode
== 2
5134 || i
.tm
.extension_opcode
== 3
5135 || i
.tm
.extension_opcode
== 6
5136 || i
.tm
.extension_opcode
== 7))
5142 else if (i
.tm
.opcode_space
== SPACE_0F
)
5144 /* bt, bts, btr, btc. */
5145 if (i
.tm
.base_opcode
== 0xba
5146 && (i
.tm
.extension_opcode
| 3) == 7)
5149 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
5150 if (i
.tm
.base_opcode
== 0xc7
5151 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
5152 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
5153 || i
.tm
.extension_opcode
== 6))
5156 /* fxrstor, ldmxcsr, xrstor. */
5157 if (i
.tm
.base_opcode
== 0xae
5158 && (i
.tm
.extension_opcode
== 1
5159 || i
.tm
.extension_opcode
== 2
5160 || i
.tm
.extension_opcode
== 5))
5163 /* lgdt, lidt, lmsw. */
5164 if (i
.tm
.base_opcode
== 0x01
5165 && (i
.tm
.extension_opcode
== 2
5166 || i
.tm
.extension_opcode
== 3
5167 || i
.tm
.extension_opcode
== 6))
5171 dest
= i
.operands
- 1;
5173 /* Check fake imm8 operand and 3 source operands. */
5174 if ((i
.tm
.opcode_modifier
.immext
5175 || i
.reg_operands
+ i
.mem_operands
== 4)
5176 && i
.types
[dest
].bitfield
.imm8
)
5179 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
5180 if (i
.tm
.opcode_space
== SPACE_BASE
5181 && ((base_opcode
| 0x38) == 0x39
5182 || (base_opcode
| 2) == 0x87))
5185 if (i
.tm
.mnem_off
== MN_xadd
)
5188 /* Check for load instruction. */
5189 return (i
.types
[dest
].bitfield
.class != ClassNone
5190 || i
.types
[dest
].bitfield
.instance
== Accum
);
5193 /* Output lfence, 0xfaee8, after instruction. */
5196 insert_lfence_after (void)
5198 if (lfence_after_load
&& load_insn_p ())
5200 /* There are also two REP string instructions that require
5201 special treatment. Specifically, the compare string (CMPS)
5202 and scan string (SCAS) instructions set EFLAGS in a manner
5203 that depends on the data being compared/scanned. When used
5204 with a REP prefix, the number of iterations may therefore
5205 vary depending on this data. If the data is a program secret
5206 chosen by the adversary using an LVI method,
5207 then this data-dependent behavior may leak some aspect
5209 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
5210 && i
.prefix
[REP_PREFIX
])
5212 as_warn (_("`%s` changes flags which would affect control flow behavior"),
5215 char *p
= frag_more (3);
5222 /* Output lfence, 0xfaee8, before instruction. */
5225 insert_lfence_before (const struct last_insn
*last_insn
)
5229 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5232 if (i
.tm
.base_opcode
== 0xff
5233 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
5235 /* Insert lfence before indirect branch if needed. */
5237 if (lfence_before_indirect_branch
== lfence_branch_none
)
5240 if (i
.operands
!= 1)
5243 if (i
.reg_operands
== 1)
5245 /* Indirect branch via register. Don't insert lfence with
5246 -mlfence-after-load=yes. */
5247 if (lfence_after_load
5248 || lfence_before_indirect_branch
== lfence_branch_memory
)
5251 else if (i
.mem_operands
== 1
5252 && lfence_before_indirect_branch
!= lfence_branch_register
)
5254 as_warn (_("indirect `%s` with memory operand should be avoided"),
5261 if (last_insn
->kind
!= last_insn_other
)
5263 as_warn_where (last_insn
->file
, last_insn
->line
,
5264 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5265 last_insn
->name
, insn_name (&i
.tm
));
5276 /* Output or/not/shl and lfence before near ret. */
5277 if (lfence_before_ret
!= lfence_before_ret_none
5278 && (i
.tm
.base_opcode
| 1) == 0xc3)
5280 if (last_insn
->kind
!= last_insn_other
)
5282 as_warn_where (last_insn
->file
, last_insn
->line
,
5283 _("`%s` skips -mlfence-before-ret on `%s`"),
5284 last_insn
->name
, insn_name (&i
.tm
));
5288 /* Near ret ingore operand size override under CPU64. */
5289 char prefix
= flag_code
== CODE_64BIT
5291 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5293 if (lfence_before_ret
== lfence_before_ret_not
)
5295 /* not: 0xf71424, may add prefix
5296 for operand size override or 64-bit code. */
5297 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5311 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5314 if (lfence_before_ret
== lfence_before_ret_or
)
5316 /* or: 0x830c2400, may add prefix
5317 for operand size override or 64-bit code. */
5323 /* shl: 0xc1242400, may add prefix
5324 for operand size override or 64-bit code. */
5339 /* Shared helper for md_assemble() and s_insn(). */
5340 static void init_globals (void)
5344 memset (&i
, '\0', sizeof (i
));
5345 i
.rounding
.type
= rc_none
;
5346 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5347 i
.reloc
[j
] = NO_RELOC
;
5348 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5349 memset (im_expressions
, '\0', sizeof (im_expressions
));
5350 save_stack_p
= save_stack
;
5353 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5354 parsing pass. Instead of introducing a rarely use new insn attribute this
5355 utilizes a common pattern between affected templates. It is deemed
5356 acceptable that this will lead to unnecessary pass 2 preparations in a
5357 limited set of cases. */
5358 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5360 return t
->opcode_modifier
.sse2avx
5361 /* Note that all SSE2AVX templates have at least one operand. */
5362 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5363 : (t
->opcode_space
== SPACE_0F
5364 && (t
->base_opcode
| 1) == 0xbf)
5365 || (t
->opcode_space
== SPACE_BASE
5366 && t
->base_opcode
== 0x63);
5369 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5371 /* DWARF register number for EFLAGS. Used for pushf/popf insns. */
5372 #define GINSN_DW2_REGNUM_EFLAGS 49
5373 /* DWARF register number for RSI. Used as dummy value when RegIP/RegIZ. */
5374 #define GINSN_DW2_REGNUM_RSI_DUMMY 4
5376 /* Identify the callee-saved registers in System V AMD64 ABI. */
5379 x86_scfi_callee_saved_p (unsigned int dw2reg_num
)
5381 if (dw2reg_num
== 3 /* rbx. */
5382 || dw2reg_num
== REG_FP
/* rbp. */
5383 || dw2reg_num
== REG_SP
/* rsp. */
5384 || (dw2reg_num
>= 12 && dw2reg_num
<= 15) /* r12 - r15. */)
5390 /* Check whether an instruction prefix which affects operation size
5391 accompanies. For insns in the legacy space, setting REX.W takes precedence
5392 over the operand-size prefix (66H) when both are used.
5394 The current users of this API are in the handlers for PUSH, POP or other
5395 instructions which affect the stack pointer implicitly: the operation size
5396 (16, 32, or 64 bits) determines the amount by which the stack pointer is
5397 incremented / decremented (2, 4 or 8). */
5400 ginsn_opsize_prefix_p (void)
5402 return (!(i
.prefix
[REX_PREFIX
] & REX_W
) && i
.prefix
[DATA_PREFIX
]);
5405 /* Get the DWARF register number for the given register entry.
5406 For specific byte/word/dword register accesses like al, cl, ah, ch, r8d,
5407 r20w etc., we need to identify the DWARF register number for the
5408 corresponding 8-byte GPR.
5410 This function is a hack - it relies on relative ordering of reg entries in
5411 the i386_regtab. FIXME - it will be good to allow a more direct way to get
5412 this information. */
5415 ginsn_dw2_regnum (const reg_entry
*ireg
)
5417 const reg_entry
*temp
= ireg
;
5418 unsigned int dwarf_reg
= Dw2Inval
, idx
= 0;
5420 /* ginsn creation is available for AMD64 abi only ATM. Other flag_code
5421 are not expected. */
5422 gas_assert (ireg
&& flag_code
== CODE_64BIT
);
5424 /* Watch out for RegIP, RegIZ. These are expected to appear only with
5425 base/index addressing modes. Although creating inaccurate data
5426 dependencies, using a dummy value (lets say volatile register rsi) will
5427 not hurt SCFI. TBD_GINSN_GEN_NOT_SCFI. */
5428 if (ireg
->reg_num
== RegIP
|| ireg
->reg_num
== RegIZ
)
5429 return GINSN_DW2_REGNUM_RSI_DUMMY
;
5431 dwarf_reg
= ireg
->dw2_regnum
[object_64bit
];
5433 if (dwarf_reg
== Dw2Inval
)
5435 if (ireg
<= &i386_regtab
[3])
5436 /* For al, cl, dl, bl, bump over to axl, cxl, dxl, bxl respectively by
5439 else if (ireg
<= &i386_regtab
[7])
5440 /* For ah, ch, dh, bh, bump over to axl, cxl, dxl, bxl respectively by
5445 /* The code relies on the relative ordering of the reg entries in
5446 i386_regtab. There are 32 register entries between axl-r31b,
5447 ax-r31w etc. The assertions here ensures the code does not
5448 recurse indefinitely. */
5449 gas_assert ((temp
- &i386_regtab
[0]) >= 0);
5450 idx
= temp
- &i386_regtab
[0];
5451 gas_assert (idx
+ 32 < i386_regtab_size
- 1);
5456 dwarf_reg
= ginsn_dw2_regnum (temp
);
5459 /* Sanity check - failure may indicate state corruption, bad ginsn or
5460 perhaps the i386-reg table and the current function got out of sync. */
5461 gas_assert (dwarf_reg
< Dw2Inval
);
5467 x86_ginsn_addsub_reg_mem (const symbolS
*insn_end_sym
)
5469 unsigned int dw2_regnum
;
5470 unsigned int src1_dw2_regnum
;
5471 ginsnS
*ginsn
= NULL
;
5472 ginsnS
* (*ginsn_func
) (const symbolS
*, bool,
5473 enum ginsn_src_type
, unsigned int, offsetT
,
5474 enum ginsn_src_type
, unsigned int, offsetT
,
5475 enum ginsn_dst_type
, unsigned int, offsetT
);
5476 uint16_t opcode
= i
.tm
.base_opcode
;
5478 gas_assert (i
.tm
.opcode_space
== SPACE_BASE
5479 && (opcode
== 0x1 || opcode
== 0x29));
5480 ginsn_func
= (opcode
== 0x1) ? ginsn_new_add
: ginsn_new_sub
;
5482 /* op %reg, symbol or even other cases where destination involves indirect
5483 access are unnecessary for SCFI correctness. TBD_GINSN_GEN_NOT_SCFI. */
5487 /* Skip detection of 8/16/32-bit op size; 'add/sub reg, reg/mem' ops always
5488 make the dest reg untraceable for SCFI. */
5490 /* op reg, reg/mem. */
5491 src1_dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
5492 /* Of interest only when second opnd is not memory. */
5493 if (i
.reg_operands
== 2)
5495 dw2_regnum
= ginsn_dw2_regnum (i
.op
[1].regs
);
5496 ginsn
= ginsn_func (insn_end_sym
, true,
5497 GINSN_SRC_REG
, src1_dw2_regnum
, 0,
5498 GINSN_SRC_REG
, dw2_regnum
, 0,
5499 GINSN_DST_REG
, dw2_regnum
, 0);
5500 ginsn_set_where (ginsn
);
5507 x86_ginsn_addsub_mem_reg (const symbolS
*insn_end_sym
)
5509 unsigned int dw2_regnum
;
5510 unsigned int src1_dw2_regnum
;
5511 const reg_entry
*mem_reg
;
5513 ginsnS
*ginsn
= NULL
;
5514 ginsnS
* (*ginsn_func
) (const symbolS
*, bool,
5515 enum ginsn_src_type
, unsigned int, offsetT
,
5516 enum ginsn_src_type
, unsigned int, offsetT
,
5517 enum ginsn_dst_type
, unsigned int, offsetT
);
5518 uint16_t opcode
= i
.tm
.base_opcode
;
5520 gas_assert (i
.tm
.opcode_space
== SPACE_BASE
5521 && (opcode
== 0x3 || opcode
== 0x2b));
5522 ginsn_func
= (opcode
== 0x3) ? ginsn_new_add
: ginsn_new_sub
;
5524 /* op symbol, %reg. */
5525 if (i
.mem_operands
&& !i
.base_reg
&& !i
.index_reg
)
5528 /* Skip detection of 8/16/32-bit op size; 'add/sub reg/mem, reg' ops always
5529 make the dest reg untraceable for SCFI. */
5531 /* op reg/mem, %reg. */
5532 dw2_regnum
= ginsn_dw2_regnum (i
.op
[1].regs
);
5534 if (i
.reg_operands
== 2)
5536 src1_dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
5537 ginsn
= ginsn_func (insn_end_sym
, true,
5538 GINSN_SRC_REG
, src1_dw2_regnum
, 0,
5539 GINSN_SRC_REG
, dw2_regnum
, 0,
5540 GINSN_DST_REG
, dw2_regnum
, 0);
5541 ginsn_set_where (ginsn
);
5543 else if (i
.mem_operands
)
5545 mem_reg
= (i
.base_reg
) ? i
.base_reg
: i
.index_reg
;
5546 src1_dw2_regnum
= ginsn_dw2_regnum (mem_reg
);
5547 if (i
.disp_operands
== 1)
5548 gdisp
= i
.op
[0].disps
->X_add_number
;
5549 ginsn
= ginsn_func (insn_end_sym
, true,
5550 GINSN_SRC_INDIRECT
, src1_dw2_regnum
, gdisp
,
5551 GINSN_SRC_REG
, dw2_regnum
, 0,
5552 GINSN_DST_REG
, dw2_regnum
, 0);
5553 ginsn_set_where (ginsn
);
5560 x86_ginsn_alu_imm (const symbolS
*insn_end_sym
)
5563 unsigned int dw2_regnum
;
5564 ginsnS
*ginsn
= NULL
;
5565 enum ginsn_src_type src_type
= GINSN_SRC_REG
;
5566 enum ginsn_dst_type dst_type
= GINSN_DST_REG
;
5568 ginsnS
* (*ginsn_func
) (const symbolS
*, bool,
5569 enum ginsn_src_type
, unsigned int, offsetT
,
5570 enum ginsn_src_type
, unsigned int, offsetT
,
5571 enum ginsn_dst_type
, unsigned int, offsetT
);
5573 /* FIXME - create ginsn where dest is REG_SP / REG_FP only ? */
5574 /* Map for insn.tm.extension_opcode
5580 /* add/sub/and imm, %reg only at this time for SCFI.
5581 Although all three ('and', 'or' , 'xor') make the destination reg
5582 untraceable, 'and' op is handled but not 'or' / 'xor' because we will look
5583 into supporting the DRAP pattern at some point. Other opcodes ('adc',
5584 'sbb' and 'cmp') are not generated here either. The ginsn representation
5585 does not have support for the latter three opcodes; GINSN_TYPE_OTHER may
5586 be added for these after x86_ginsn_unhandled () invocation if the
5587 destination register is REG_SP or REG_FP. */
5588 if (i
.tm
.extension_opcode
== 5)
5589 ginsn_func
= ginsn_new_sub
;
5590 else if (i
.tm
.extension_opcode
== 4)
5591 ginsn_func
= ginsn_new_and
;
5592 else if (i
.tm
.extension_opcode
== 0)
5593 ginsn_func
= ginsn_new_add
;
5597 /* TBD_GINSN_REPRESENTATION_LIMIT: There is no representation for when a
5598 symbol is used as an operand, like so:
5599 addq $simd_cmp_op+8, %rdx
5600 Skip generating any ginsn for this. */
5601 if (i
.imm_operands
== 1
5602 && i
.op
[0].imms
->X_op
!= O_constant
)
5607 These are not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */
5608 if (i
.mem_operands
== 1)
5611 /* 8/16/32-bit op size makes the destination reg untraceable for SCFI.
5612 Deal with this via the x86_ginsn_unhandled () code path. */
5613 if (i
.suffix
!= QWORD_MNEM_SUFFIX
)
5616 gas_assert (i
.imm_operands
== 1);
5617 src_imm
= i
.op
[0].imms
->X_add_number
;
5618 /* The second operand may be a register or indirect access. For SCFI, only
5619 the case when the second opnd is a register is interesting. Revisit this
5620 if generating ginsns for a different gen mode TBD_GINSN_GEN_NOT_SCFI. */
5621 if (i
.reg_operands
== 1)
5623 dw2_regnum
= ginsn_dw2_regnum (i
.op
[1].regs
);
5624 /* For ginsn, keep the imm as second src operand. */
5625 ginsn
= ginsn_func (insn_end_sym
, true,
5626 src_type
, dw2_regnum
, 0,
5627 GINSN_SRC_IMM
, 0, src_imm
,
5628 dst_type
, dw2_regnum
, 0);
5630 ginsn_set_where (ginsn
);
5636 /* Create ginsn(s) for MOV operations.
5638 The generated ginsns corresponding to mov with indirect access to memory
5639 (src or dest) suffer with loss of information: when both index and base
5640 registers are at play, only base register gets conveyed in ginsn. Note
5641 this TBD_GINSN_GEN_NOT_SCFI. */
5644 x86_ginsn_move (const symbolS
*insn_end_sym
)
5646 ginsnS
*ginsn
= NULL
;
5647 unsigned int dst_reg
;
5648 unsigned int src_reg
;
5649 offsetT src_disp
= 0;
5650 offsetT dst_disp
= 0;
5651 const reg_entry
*dst
= NULL
;
5652 const reg_entry
*src
= NULL
;
5653 uint16_t opcode
= i
.tm
.base_opcode
;
5654 enum ginsn_src_type src_type
= GINSN_SRC_REG
;
5655 enum ginsn_dst_type dst_type
= GINSN_DST_REG
;
5657 /* mov %reg, symbol or mov symbol, %reg.
5658 Not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */
5659 if (i
.mem_operands
== 1 && !i
.base_reg
&& !i
.index_reg
)
5662 /* 8/16/32-bit op size makes the destination reg untraceable for SCFI.
5663 Handle mov reg, reg only. mov to or from a memory operand will make
5664 dest reg, when present, untraceable, irrespective of the op size. */
5665 if (i
.reg_operands
== 2 && i
.suffix
!= QWORD_MNEM_SUFFIX
)
5668 gas_assert (i
.tm
.opcode_space
== SPACE_BASE
);
5669 if (opcode
== 0x8b || opcode
== 0x8a)
5671 /* mov disp(%reg), %reg. */
5674 src
= (i
.base_reg
) ? i
.base_reg
: i
.index_reg
;
5675 if (i
.disp_operands
== 1)
5676 src_disp
= i
.op
[0].disps
->X_add_number
;
5677 src_type
= GINSN_SRC_INDIRECT
;
5684 else if (opcode
== 0x89 || opcode
== 0x88)
5686 /* mov %reg, disp(%reg). */
5690 dst
= (i
.base_reg
) ? i
.base_reg
: i
.index_reg
;
5691 if (i
.disp_operands
== 1)
5692 dst_disp
= i
.op
[1].disps
->X_add_number
;
5693 dst_type
= GINSN_DST_INDIRECT
;
5699 src_reg
= ginsn_dw2_regnum (src
);
5700 dst_reg
= ginsn_dw2_regnum (dst
);
5702 ginsn
= ginsn_new_mov (insn_end_sym
, true,
5703 src_type
, src_reg
, src_disp
,
5704 dst_type
, dst_reg
, dst_disp
);
5705 ginsn_set_where (ginsn
);
5710 /* Generate appropriate ginsn for lea.
5712 Unhandled sub-cases (marked with TBD_GINSN_GEN_NOT_SCFI) also suffer with
5713 some loss of information in the final ginsn chosen eventually (type
5714 GINSN_TYPE_OTHER). But this is fine for now for GINSN_GEN_SCFI generation
5718 x86_ginsn_lea (const symbolS
*insn_end_sym
)
5720 offsetT src_disp
= 0;
5721 ginsnS
*ginsn
= NULL
;
5722 unsigned int src1_reg
;
5723 const reg_entry
*src1
;
5724 offsetT index_scale
;
5725 unsigned int dst_reg
;
5728 if ((!i
.base_reg
) != (!i
.index_reg
|| i
.index_reg
->reg_num
== RegIZ
))
5730 /* lea disp(%base), %dst or lea disp(,%index,imm), %dst.
5731 Either index_reg or base_reg exists, but not both. Further, as per
5732 above, the case when just %index exists but is equal to RegIZ is
5733 excluded. If not excluded, a GINSN_TYPE_MOV of %rsi
5734 (GINSN_DW2_REGNUM_RSI_DUMMY) to %dst will be generated by this block.
5735 Such a mov ginsn is imprecise; so, exclude now and generate
5736 GINSN_TYPE_OTHER instead later via the x86_ginsn_unhandled ().
5737 Excluding other cases is required due to
5738 TBD_GINSN_REPRESENTATION_LIMIT. */
5740 index_scale
= i
.log2_scale_factor
;
5741 index_regiz_p
= i
.index_reg
&& i
.index_reg
->reg_num
== RegIZ
;
5742 src1
= i
.base_reg
? i
.base_reg
: i
.index_reg
;
5743 src1_reg
= ginsn_dw2_regnum (src1
);
5744 dst_reg
= ginsn_dw2_regnum (i
.op
[1].regs
);
5745 /* It makes sense to represent a scale factor of 1 precisely here
5746 (i.e., not using GINSN_TYPE_OTHER, but rather similar to the
5747 base-without-index case). A non-zero scale factor is still OK if
5748 the index reg is zero reg.
5749 However, skip from here the case when disp has a symbol instead.
5750 TBD_GINSN_REPRESENTATION_LIMIT. */
5751 if ((!index_scale
|| index_regiz_p
)
5752 && (!i
.disp_operands
|| i
.op
[0].disps
->X_op
== O_constant
))
5754 if (i
.disp_operands
)
5755 src_disp
= i
.op
[0].disps
->X_add_number
;
5758 /* Generate an ADD ginsn. */
5759 ginsn
= ginsn_new_add (insn_end_sym
, true,
5760 GINSN_SRC_REG
, src1_reg
, 0,
5761 GINSN_SRC_IMM
, 0, src_disp
,
5762 GINSN_DST_REG
, dst_reg
, 0);
5764 /* Generate a MOV ginsn. */
5765 ginsn
= ginsn_new_mov (insn_end_sym
, true,
5766 GINSN_SRC_REG
, src1_reg
, 0,
5767 GINSN_DST_REG
, dst_reg
, 0);
5769 ginsn_set_where (ginsn
);
5772 /* Skip handling other cases here,
5773 - when (i.index_reg && i.base_reg) is true,
5774 e.g., lea disp(%base,%index,imm), %dst
5775 We do not have a ginsn representation for multiply.
5776 - or, when (!i.index_reg && !i.base_reg) is true,
5777 e.g., lea symbol, %dst
5778 Not a frequent pattern. If %dst is a register of interest, the user is
5779 likely to use a MOV op anyway.
5780 Deal with these via the x86_ginsn_unhandled () code path to generate
5781 GINSN_TYPE_OTHER when necessary. TBD_GINSN_GEN_NOT_SCFI. */
5787 x86_ginsn_jump (const symbolS
*insn_end_sym
, bool cond_p
)
5789 ginsnS
*ginsn
= NULL
;
5790 const symbolS
*src_symbol
;
5791 ginsnS
* (*ginsn_func
) (const symbolS
*sym
, bool real_p
,
5792 enum ginsn_src_type src_type
, unsigned int src_reg
,
5793 const symbolS
*src_ginsn_sym
);
5795 gas_assert (i
.disp_operands
== 1);
5797 ginsn_func
= cond_p
? ginsn_new_jump_cond
: ginsn_new_jump
;
5798 if (i
.op
[0].disps
->X_op
== O_symbol
&& !i
.op
[0].disps
->X_add_number
)
5800 src_symbol
= i
.op
[0].disps
->X_add_symbol
;
5801 ginsn
= ginsn_func (insn_end_sym
, true,
5802 GINSN_SRC_SYMBOL
, 0, src_symbol
);
5804 ginsn_set_where (ginsn
);
5808 /* A non-zero addend in jump/JCC target makes control-flow tracking
5809 difficult. Skip SCFI for now. */
5810 as_bad (_("SCFI: `%s' insn with non-zero addend to sym not supported"),
5811 cond_p
? "JCC" : "jmp");
5819 x86_ginsn_enter (const symbolS
*insn_end_sym
)
5821 ginsnS
*ginsn
= NULL
;
5822 ginsnS
*ginsn_next
= NULL
;
5823 ginsnS
*ginsn_last
= NULL
;
5824 /* In 64-bit mode, the default stack update size is 8 bytes. */
5825 int stack_opnd_size
= 8;
5827 gas_assert (i
.imm_operands
== 2);
5829 /* For non-zero size operands, bail out as untraceable for SCFI. */
5830 if (i
.op
[0].imms
->X_op
!= O_constant
|| i
.op
[0].imms
->X_add_symbol
!= 0
5831 || i
.op
[1].imms
->X_op
!= O_constant
|| i
.op
[1].imms
->X_add_symbol
!= 0)
5833 as_bad ("SCFI: enter insn with non-zero operand not supported");
5837 /* Check if this is a 16-bit op. */
5838 if (ginsn_opsize_prefix_p ())
5839 stack_opnd_size
= 2;
5841 /* If the nesting level is 0, the processor pushes the frame pointer from
5842 the BP/EBP/RBP register onto the stack, copies the current stack
5843 pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and
5844 loads the SP/ESP/RSP register with the current stack-pointer value
5845 minus the value in the size operand. */
5846 ginsn
= ginsn_new_sub (insn_end_sym
, false,
5847 GINSN_SRC_REG
, REG_SP
, 0,
5848 GINSN_SRC_IMM
, 0, stack_opnd_size
,
5849 GINSN_DST_REG
, REG_SP
, 0);
5850 ginsn_set_where (ginsn
);
5851 ginsn_next
= ginsn_new_store (insn_end_sym
, false,
5852 GINSN_SRC_REG
, REG_FP
,
5853 GINSN_DST_INDIRECT
, REG_SP
, 0);
5854 ginsn_set_where (ginsn_next
);
5855 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
5856 ginsn_last
= ginsn_new_mov (insn_end_sym
, false,
5857 GINSN_SRC_REG
, REG_SP
, 0,
5858 GINSN_DST_REG
, REG_FP
, 0);
5859 ginsn_set_where (ginsn_last
);
5860 gas_assert (!ginsn_link_next (ginsn_next
, ginsn_last
));
5866 x86_ginsn_leave (const symbolS
*insn_end_sym
)
5868 ginsnS
*ginsn
= NULL
;
5869 ginsnS
*ginsn_next
= NULL
;
5870 ginsnS
*ginsn_last
= NULL
;
5871 /* In 64-bit mode, the default stack update size is 8 bytes. */
5872 int stack_opnd_size
= 8;
5874 /* Check if this is a 16-bit op. */
5875 if (ginsn_opsize_prefix_p ())
5876 stack_opnd_size
= 2;
5878 /* The 'leave' instruction copies the contents of the RBP register
5879 into the RSP register to release all stack space allocated to the
5881 ginsn
= ginsn_new_mov (insn_end_sym
, false,
5882 GINSN_SRC_REG
, REG_FP
, 0,
5883 GINSN_DST_REG
, REG_SP
, 0);
5884 ginsn_set_where (ginsn
);
5885 /* Then it restores the old value of the RBP register from the stack. */
5886 ginsn_next
= ginsn_new_load (insn_end_sym
, false,
5887 GINSN_SRC_INDIRECT
, REG_SP
, 0,
5888 GINSN_DST_REG
, REG_FP
);
5889 ginsn_set_where (ginsn_next
);
5890 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
5891 ginsn_last
= ginsn_new_add (insn_end_sym
, false,
5892 GINSN_SRC_REG
, REG_SP
, 0,
5893 GINSN_SRC_IMM
, 0, stack_opnd_size
,
5894 GINSN_DST_REG
, REG_SP
, 0);
5895 ginsn_set_where (ginsn_next
);
5896 gas_assert (!ginsn_link_next (ginsn_next
, ginsn_last
));
5901 /* Check if an instruction is whitelisted.
5903 Some instructions may appear with REG_SP or REG_FP as destination, because
5904 which they are deemed 'interesting' for SCFI. Whitelist them here if they
5905 do not affect SCFI correctness. */
5908 x86_ginsn_safe_to_skip_p (void)
5910 bool skip_p
= false;
5911 uint16_t opcode
= i
.tm
.base_opcode
;
5918 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5920 /* cmp imm, reg/rem. */
5921 if (i
.tm
.extension_opcode
== 7)
5929 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5931 /* cmp imm/reg/mem, reg/rem. */
5939 /* test imm/reg/mem, reg/mem. */
5940 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5952 #define X86_GINSN_UNHANDLED_NONE 0
5953 #define X86_GINSN_UNHANDLED_DEST_REG 1
5954 #define X86_GINSN_UNHANDLED_CFG 2
5955 #define X86_GINSN_UNHANDLED_STACKOP 3
5956 #define X86_GINSN_UNHANDLED_UNEXPECTED 4
5958 /* Check the input insn for its impact on the correctness of the synthesized
5959 CFI. Returns an error code to the caller. */
5962 x86_ginsn_unhandled (void)
5964 int err
= X86_GINSN_UNHANDLED_NONE
;
5965 const reg_entry
*reg_op
;
5966 unsigned int dw2_regnum
;
5968 /* Keep an eye out for instructions affecting control flow. */
5969 if (i
.tm
.opcode_modifier
.jump
)
5970 err
= X86_GINSN_UNHANDLED_CFG
;
5971 /* Also, for any instructions involving an implicit update to the stack
5973 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_STACK_OP
)
5974 err
= X86_GINSN_UNHANDLED_STACKOP
;
5975 /* Finally, also check if the missed instructions are affecting REG_SP or
5976 REG_FP. The destination operand is the last at all stages of assembly
5977 (due to following AT&T syntax layout in the internal representation). In
5978 case of Intel syntax input, this still remains true as swap_operands ()
5980 PS: These checks do not involve index / base reg, as indirect memory
5981 accesses via REG_SP or REG_FP do not affect SCFI correctness.
5982 (Also note these instructions are candidates for other ginsn generation
5983 modes in future. TBD_GINSN_GEN_NOT_SCFI.) */
5984 else if (i
.operands
&& i
.reg_operands
5985 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
5987 reg_op
= i
.op
[i
.operands
- 1].regs
;
5990 dw2_regnum
= ginsn_dw2_regnum (reg_op
);
5991 if (dw2_regnum
== REG_SP
|| dw2_regnum
== REG_FP
)
5992 err
= X86_GINSN_UNHANDLED_DEST_REG
;
5995 /* Something unexpected. Indicate to caller. */
5996 err
= X86_GINSN_UNHANDLED_UNEXPECTED
;
6002 /* Generate one or more generic GAS instructions, a.k.a, ginsns for the current
6003 machine instruction.
6005 Returns the head of linked list of ginsn(s) added, if success; Returns NULL
6008 The input ginsn_gen_mode GMODE determines the set of minimal necessary
6009 ginsns necessary for correctness of any passes applicable for that mode.
6010 For supporting the GINSN_GEN_SCFI generation mode, following is the list of
6011 machine instructions that must be translated into the corresponding ginsns
6012 to ensure correctness of SCFI:
6013 - All instructions affecting the two registers that could potentially
6014 be used as the base register for CFA tracking. For SCFI, the base
6015 register for CFA tracking is limited to REG_SP and REG_FP only for
6017 - All change of flow instructions: conditional and unconditional branches,
6018 call and return from functions.
6019 - All instructions that can potentially be a register save / restore
6021 - All instructions that perform stack manipulation implicitly: the CALL,
6022 RET, PUSH, POP, ENTER, and LEAVE instructions.
6024 The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
6025 To support other generation modes will require work on this target-specific
6026 process of creation of ginsns:
6027 - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
6028 possible starting points.
6029 - Also note that ginsn representation may need enhancements. Specifically,
6030 note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
6034 x86_ginsn_new (const symbolS
*insn_end_sym
, enum ginsn_gen_mode gmode
)
6038 unsigned int dw2_regnum
;
6039 const reg_entry
*mem_reg
;
6040 ginsnS
*ginsn
= NULL
;
6041 ginsnS
*ginsn_next
= NULL
;
6042 /* In 64-bit mode, the default stack update size is 8 bytes. */
6043 int stack_opnd_size
= 8;
6045 /* Currently supports generation of selected ginsns, sufficient for
6046 the use-case of SCFI only. */
6047 if (gmode
!= GINSN_GEN_SCFI
)
6050 opcode
= i
.tm
.base_opcode
;
6052 /* Until it is clear how to handle APX NDD and other new opcodes, disallow
6054 if (is_apx_rex2_encoding ()
6055 || (i
.tm
.opcode_modifier
.evex
&& is_apx_evex_encoding ()))
6057 as_bad (_("SCFI: unsupported APX op %#x may cause incorrect CFI"),
6065 /* Add opcodes 0x0/0x2 and sub opcodes 0x28/0x2a (with opcode_space
6066 SPACE_BASE) are 8-bit ops. While they are relevant for SCFI
6067 correctness, skip handling them here and use the x86_ginsn_unhandled
6068 code path to generate GINSN_TYPE_OTHER when necessary. */
6070 case 0x1: /* add reg, reg/mem. */
6071 case 0x29: /* sub reg, reg/mem. */
6072 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6074 ginsn
= x86_ginsn_addsub_reg_mem (insn_end_sym
);
6077 case 0x3: /* add reg/mem, reg. */
6078 case 0x2b: /* sub reg/mem, reg. */
6079 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6081 ginsn
= x86_ginsn_addsub_mem_reg (insn_end_sym
);
6084 case 0xa0: /* push fs. */
6085 case 0xa8: /* push gs. */
6086 /* push fs / push gs have opcode_space == SPACE_0F. */
6087 if (i
.tm
.opcode_space
!= SPACE_0F
)
6089 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6090 /* Check if operation size is 16-bit. */
6091 if (ginsn_opsize_prefix_p ())
6092 stack_opnd_size
= 2;
6093 ginsn
= ginsn_new_sub (insn_end_sym
, false,
6094 GINSN_SRC_REG
, REG_SP
, 0,
6095 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6096 GINSN_DST_REG
, REG_SP
, 0);
6097 ginsn_set_where (ginsn
);
6098 ginsn_next
= ginsn_new_store (insn_end_sym
, false,
6099 GINSN_SRC_REG
, dw2_regnum
,
6100 GINSN_DST_INDIRECT
, REG_SP
, 0);
6101 ginsn_set_where (ginsn_next
);
6102 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6105 case 0xa1: /* pop fs. */
6106 case 0xa9: /* pop gs. */
6107 /* pop fs / pop gs have opcode_space == SPACE_0F. */
6108 if (i
.tm
.opcode_space
!= SPACE_0F
)
6110 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6111 /* Check if operation size is 16-bit. */
6112 if (ginsn_opsize_prefix_p ())
6113 stack_opnd_size
= 2;
6114 ginsn
= ginsn_new_load (insn_end_sym
, false,
6115 GINSN_SRC_INDIRECT
, REG_SP
, 0,
6116 GINSN_DST_REG
, dw2_regnum
);
6117 ginsn_set_where (ginsn
);
6118 ginsn_next
= ginsn_new_add (insn_end_sym
, false,
6119 GINSN_SRC_REG
, REG_SP
, 0,
6120 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6121 GINSN_DST_REG
, REG_SP
, 0);
6122 ginsn_set_where (ginsn_next
);
6123 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6127 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6130 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6131 /* Check if operation size is 16-bit. */
6132 if (ginsn_opsize_prefix_p ())
6133 stack_opnd_size
= 2;
6134 ginsn
= ginsn_new_sub (insn_end_sym
, false,
6135 GINSN_SRC_REG
, REG_SP
, 0,
6136 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6137 GINSN_DST_REG
, REG_SP
, 0);
6138 ginsn_set_where (ginsn
);
6139 ginsn_next
= ginsn_new_store (insn_end_sym
, false,
6140 GINSN_SRC_REG
, dw2_regnum
,
6141 GINSN_DST_INDIRECT
, REG_SP
, 0);
6142 ginsn_set_where (ginsn_next
);
6143 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6147 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6150 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6151 ginsn
= ginsn_new_load (insn_end_sym
, false,
6152 GINSN_SRC_INDIRECT
, REG_SP
, 0,
6153 GINSN_DST_REG
, dw2_regnum
);
6154 ginsn_set_where (ginsn
);
6155 /* Check if operation size is 16-bit. */
6156 if (ginsn_opsize_prefix_p ())
6157 stack_opnd_size
= 2;
6158 ginsn_next
= ginsn_new_add (insn_end_sym
, false,
6159 GINSN_SRC_REG
, REG_SP
, 0,
6160 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6161 GINSN_DST_REG
, REG_SP
, 0);
6162 ginsn_set_where (ginsn_next
);
6163 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6166 case 0x6a: /* push imm8. */
6167 case 0x68: /* push imm16/imm32. */
6168 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6170 /* Check if operation size is 16-bit. */
6171 if (ginsn_opsize_prefix_p ())
6172 stack_opnd_size
= 2;
6173 /* Skip getting the value of imm from machine instruction
6174 because this is not important for SCFI. */
6175 ginsn
= ginsn_new_sub (insn_end_sym
, false,
6176 GINSN_SRC_REG
, REG_SP
, 0,
6177 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6178 GINSN_DST_REG
, REG_SP
, 0);
6179 ginsn_set_where (ginsn
);
6180 ginsn_next
= ginsn_new_store (insn_end_sym
, false,
6182 GINSN_DST_INDIRECT
, REG_SP
, 0);
6183 ginsn_set_where (ginsn_next
);
6184 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6187 /* PS: Opcodes 0x80 ... 0x8f with opcode_space SPACE_0F are present
6188 only after relaxation. They do not need to be handled for ginsn
6191 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6193 ginsn
= x86_ginsn_jump (insn_end_sym
, true);
6199 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6201 ginsn
= x86_ginsn_alu_imm (insn_end_sym
);
6204 case 0x8a: /* mov r/m8, r8. */
6205 case 0x8b: /* mov r/m(16/32/64), r(16/32/64). */
6206 case 0x88: /* mov r8, r/m8. */
6207 case 0x89: /* mov r(16/32/64), r/m(16/32/64). */
6208 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6210 ginsn
= x86_ginsn_move (insn_end_sym
);
6214 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6216 /* lea disp(%base,%index,imm), %dst. */
6217 ginsn
= x86_ginsn_lea (insn_end_sym
);
6221 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6223 /* pop to reg/mem. */
6226 mem_reg
= (i
.base_reg
) ? i
.base_reg
: i
.index_reg
;
6227 /* Use dummy register if no base or index. Unlike other opcodes,
6228 ginsns must be generated as this affect stack pointer. */
6229 dw2_regnum
= (mem_reg
6230 ? ginsn_dw2_regnum (mem_reg
)
6231 : GINSN_DW2_REGNUM_RSI_DUMMY
);
6234 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6235 ginsn
= ginsn_new_load (insn_end_sym
, false,
6236 GINSN_SRC_INDIRECT
, REG_SP
, 0,
6237 GINSN_DST_INDIRECT
, dw2_regnum
);
6238 ginsn_set_where (ginsn
);
6239 /* Check if operation size is 16-bit. */
6240 if (ginsn_opsize_prefix_p ())
6241 stack_opnd_size
= 2;
6242 ginsn_next
= ginsn_new_add (insn_end_sym
, false,
6243 GINSN_SRC_REG
, REG_SP
, 0,
6244 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6245 GINSN_DST_REG
, REG_SP
, 0);
6246 ginsn_set_where (ginsn_next
);
6247 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6251 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6253 /* pushf / pushfq. */
6254 /* Check if operation size is 16-bit. */
6255 if (ginsn_opsize_prefix_p ())
6256 stack_opnd_size
= 2;
6257 ginsn
= ginsn_new_sub (insn_end_sym
, false,
6258 GINSN_SRC_REG
, REG_SP
, 0,
6259 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6260 GINSN_DST_REG
, REG_SP
, 0);
6261 ginsn_set_where (ginsn
);
6262 /* FIXME - hardcode the actual DWARF reg number value. As for SCFI
6263 correctness, although this behaves simply a placeholder value; its
6264 just clearer if the value is correct. */
6265 dw2_regnum
= GINSN_DW2_REGNUM_EFLAGS
;
6266 ginsn_next
= ginsn_new_store (insn_end_sym
, false,
6267 GINSN_SRC_REG
, dw2_regnum
,
6268 GINSN_DST_INDIRECT
, REG_SP
, 0);
6269 ginsn_set_where (ginsn_next
);
6270 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6274 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6277 /* Check if operation size is 16-bit. */
6278 if (ginsn_opsize_prefix_p ())
6279 stack_opnd_size
= 2;
6280 /* FIXME - hardcode the actual DWARF reg number value. As for SCFI
6281 correctness, although this behaves simply a placeholder value; its
6282 just clearer if the value is correct. */
6283 dw2_regnum
= GINSN_DW2_REGNUM_EFLAGS
;
6284 ginsn
= ginsn_new_load (insn_end_sym
, false,
6285 GINSN_SRC_INDIRECT
, REG_SP
, 0,
6286 GINSN_DST_REG
, dw2_regnum
);
6287 ginsn_set_where (ginsn
);
6288 ginsn_next
= ginsn_new_add (insn_end_sym
, false,
6289 GINSN_SRC_REG
, REG_SP
, 0,
6290 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6291 GINSN_DST_REG
, REG_SP
, 0);
6292 ginsn_set_where (ginsn_next
);
6293 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6297 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6299 /* push from reg/mem. */
6300 if (i
.tm
.extension_opcode
== 6)
6302 /* Check if operation size is 16-bit. */
6303 if (ginsn_opsize_prefix_p ())
6304 stack_opnd_size
= 2;
6305 ginsn
= ginsn_new_sub (insn_end_sym
, false,
6306 GINSN_SRC_REG
, REG_SP
, 0,
6307 GINSN_SRC_IMM
, 0, stack_opnd_size
,
6308 GINSN_DST_REG
, REG_SP
, 0);
6309 ginsn_set_where (ginsn
);
6312 mem_reg
= (i
.base_reg
) ? i
.base_reg
: i
.index_reg
;
6313 /* Use dummy register if no base or index. Unlike other opcodes,
6314 ginsns must be generated as this affect stack pointer. */
6315 dw2_regnum
= (mem_reg
6316 ? ginsn_dw2_regnum (mem_reg
)
6317 : GINSN_DW2_REGNUM_RSI_DUMMY
);
6320 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6321 ginsn_next
= ginsn_new_store (insn_end_sym
, false,
6322 GINSN_SRC_INDIRECT
, dw2_regnum
,
6323 GINSN_DST_INDIRECT
, REG_SP
, 0);
6324 ginsn_set_where (ginsn_next
);
6325 gas_assert (!ginsn_link_next (ginsn
, ginsn_next
));
6327 else if (i
.tm
.extension_opcode
== 4)
6329 /* jmp r/m. E.g., notrack jmp *%rax. */
6332 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6333 ginsn
= ginsn_new_jump (insn_end_sym
, true,
6334 GINSN_SRC_REG
, dw2_regnum
, NULL
);
6335 ginsn_set_where (ginsn
);
6337 else if (i
.mem_operands
&& i
.index_reg
)
6339 /* jmp *0x0(,%rax,8). */
6340 dw2_regnum
= ginsn_dw2_regnum (i
.index_reg
);
6341 ginsn
= ginsn_new_jump (insn_end_sym
, true,
6342 GINSN_SRC_REG
, dw2_regnum
, NULL
);
6343 ginsn_set_where (ginsn
);
6345 else if (i
.mem_operands
&& i
.base_reg
)
6347 dw2_regnum
= ginsn_dw2_regnum (i
.base_reg
);
6348 ginsn
= ginsn_new_jump (insn_end_sym
, true,
6349 GINSN_SRC_REG
, dw2_regnum
, NULL
);
6350 ginsn_set_where (ginsn
);
6353 else if (i
.tm
.extension_opcode
== 2)
6355 /* 0xFF /2 (call). */
6358 dw2_regnum
= ginsn_dw2_regnum (i
.op
[0].regs
);
6359 ginsn
= ginsn_new_call (insn_end_sym
, true,
6360 GINSN_SRC_REG
, dw2_regnum
, NULL
);
6361 ginsn_set_where (ginsn
);
6363 else if (i
.mem_operands
&& i
.base_reg
)
6365 dw2_regnum
= ginsn_dw2_regnum (i
.base_reg
);
6366 ginsn
= ginsn_new_call (insn_end_sym
, true,
6367 GINSN_SRC_REG
, dw2_regnum
, NULL
);
6368 ginsn_set_where (ginsn
);
6373 case 0xc2: /* ret imm16. */
6374 case 0xc3: /* ret. */
6375 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6378 ginsn
= ginsn_new_return (insn_end_sym
, true);
6379 ginsn_set_where (ginsn
);
6383 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6386 ginsn
= x86_ginsn_enter (insn_end_sym
);
6390 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6393 ginsn
= x86_ginsn_leave (insn_end_sym
);
6396 case 0xe0 ... 0xe2: /* loop / loope / loopne. */
6397 case 0xe3: /* jecxz / jrcxz. */
6398 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6400 ginsn
= x86_ginsn_jump (insn_end_sym
, true);
6401 ginsn_set_where (ginsn
);
6405 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6407 /* PS: SCFI machinery does not care about which func is being
6408 called. OK to skip that info. */
6409 ginsn
= ginsn_new_call (insn_end_sym
, true,
6410 GINSN_SRC_SYMBOL
, 0, NULL
);
6411 ginsn_set_where (ginsn
);
6414 /* PS: opcode 0xe9 appears only after relaxation. Skip here. */
6416 /* If opcode_space != SPACE_BASE, this is not a jmp insn. Skip it
6417 for GINSN_GEN_SCFI. */
6418 if (i
.tm
.opcode_space
!= SPACE_BASE
)
6420 /* Unconditional jmp. */
6421 ginsn
= x86_ginsn_jump (insn_end_sym
, false);
6422 ginsn_set_where (ginsn
);
6426 /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
6427 GINSN_GEN_SCFI mode. */
6431 if (!ginsn
&& !x86_ginsn_safe_to_skip_p ())
6433 /* For all unhandled insns that are not whitelisted, check that they do
6434 not impact SCFI correctness. */
6435 err
= x86_ginsn_unhandled ();
6438 case X86_GINSN_UNHANDLED_NONE
:
6440 case X86_GINSN_UNHANDLED_DEST_REG
:
6441 /* Not all writes to REG_FP are harmful in context of SCFI. Simply
6442 generate a GINSN_TYPE_OTHER with destination set to the
6443 appropriate register. The SCFI machinery will bail out if this
6444 ginsn affects SCFI correctness. */
6445 dw2_regnum
= ginsn_dw2_regnum (i
.op
[i
.operands
- 1].regs
);
6446 ginsn
= ginsn_new_other (insn_end_sym
, true,
6449 GINSN_DST_REG
, dw2_regnum
);
6450 ginsn_set_where (ginsn
);
6452 case X86_GINSN_UNHANDLED_CFG
:
6453 case X86_GINSN_UNHANDLED_STACKOP
:
6454 as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"), opcode
);
6456 case X86_GINSN_UNHANDLED_UNEXPECTED
:
6457 as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
6471 /* This is the guts of the machine-dependent assembler. LINE points to a
6472 machine dependent instruction. This function is supposed to emit
6473 the frags/bytes it assembles to. */
6476 md_assemble (char *line
)
6479 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
6480 const char *end
, *pass1_mnem
= NULL
;
6481 enum i386_error pass1_err
= 0;
6482 const insn_template
*t
;
6483 struct last_insn
*last_insn
6484 = &seg_info(now_seg
)->tc_segment_info_data
.last_insn
;
6486 /* Initialize globals. */
6487 current_templates
.end
= current_templates
.start
= NULL
;
6491 /* Suppress optimization when the last thing we saw may not have been
6492 a proper instruction (e.g. a stand-alone prefix or .byte). */
6493 if (last_insn
->kind
!= last_insn_other
)
6494 i
.no_optimize
= true;
6496 /* First parse an instruction mnemonic & call i386_operand for the operands.
6497 We assume that the scrubber has arranged it so that line[0] is the valid
6498 start of a (possibly prefixed) mnemonic. */
6500 end
= parse_insn (line
, mnemonic
, false);
6503 if (pass1_mnem
!= NULL
)
6505 if (i
.error
!= no_error
)
6507 gas_assert (current_templates
.start
!= NULL
);
6508 if (may_need_pass2 (current_templates
.start
) && !i
.suffix
)
6510 /* No point in trying a 2nd pass - it'll only find the same suffix
6512 mnem_suffix
= i
.suffix
;
6517 t
= current_templates
.start
;
6518 if (may_need_pass2 (t
))
6520 /* Make a copy of the full line in case we need to retry. */
6521 copy
= xstrdup (line
);
6524 mnem_suffix
= i
.suffix
;
6526 line
= parse_operands (line
, mnemonic
);
6534 /* Now we've parsed the mnemonic into a set of templates, and have the
6535 operands at hand. */
6537 /* All Intel opcodes have reversed operands except for "bound", "enter",
6538 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
6539 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
6540 intersegment "jmp" and "call" instructions with 2 immediate operands so
6541 that the immediate segment precedes the offset consistently in Intel and
6545 && (t
->mnem_off
!= MN_bound
)
6546 && !startswith (mnemonic
, "invlpg")
6547 && !startswith (mnemonic
, "monitor")
6548 && !startswith (mnemonic
, "mwait")
6549 && (t
->mnem_off
!= MN_pvalidate
)
6550 && !startswith (mnemonic
, "rmp")
6551 && (t
->mnem_off
!= MN_tpause
)
6552 && (t
->mnem_off
!= MN_umwait
)
6553 && !(i
.operands
== 2
6554 && operand_type_check (i
.types
[0], imm
)
6555 && operand_type_check (i
.types
[1], imm
)))
6558 /* The order of the immediates should be reversed for 2-immediates EXTRQ
6559 and INSERTQ instructions. Also UWRMSR wants its immediate to be in the
6560 "canonical" place (first), despite it appearing last (in AT&T syntax, or
6561 because of the swapping above) in the incoming set of operands. */
6562 if ((i
.imm_operands
== 2
6563 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
6564 || (t
->mnem_off
== MN_uwrmsr
&& i
.imm_operands
6565 && i
.operands
> i
.imm_operands
))
6566 swap_2_operands (0, 1);
6570 /* For USER_MSR instructions, imm32 stands for the name of an model specific
6571 register (MSR). That's an unsigned quantity, whereas all other insns with
6572 32-bit immediate and 64-bit operand size use sign-extended
6573 immediates (imm32s). Therefore these insns are special-cased, bypassing
6574 the normal handling of immediates here. */
6575 if (is_cpu(current_templates
.start
, CpuUSER_MSR
))
6577 for (j
= 0; j
< i
.operands
; j
++)
6579 if (operand_type_check(i
.types
[j
], imm
))
6580 i
.types
[j
] = smallest_imm_type (i
.op
[j
].imms
->X_add_number
);
6587 if (i
.disp_operands
&& !optimize_disp (t
))
6590 /* Next, we find a template that matches the given insn,
6591 making sure the overlap of the given operands types is consistent
6592 with the template operand types. */
6594 if (!(t
= match_template (mnem_suffix
)))
6596 const char *err_msg
;
6598 if (copy
&& !mnem_suffix
)
6603 pass1_err
= i
.error
;
6604 pass1_mnem
= insn_name (current_templates
.start
);
6608 /* If a non-/only-64bit template (group) was found in pass 1, and if
6609 _some_ template (group) was found in pass 2, squash pass 1's
6611 if (pass1_err
== unsupported_64bit
)
6617 switch (pass1_mnem
? pass1_err
: i
.error
)
6621 case operand_size_mismatch
:
6622 err_msg
= _("operand size mismatch");
6624 case operand_type_mismatch
:
6625 err_msg
= _("operand type mismatch");
6627 case register_type_mismatch
:
6628 err_msg
= _("register type mismatch");
6630 case number_of_operands_mismatch
:
6631 err_msg
= _("number of operands mismatch");
6633 case invalid_instruction_suffix
:
6634 err_msg
= _("invalid instruction suffix");
6637 err_msg
= _("constant doesn't fit in 4 bits");
6639 case unsupported_with_intel_mnemonic
:
6640 err_msg
= _("unsupported with Intel mnemonic");
6642 case unsupported_syntax
:
6643 err_msg
= _("unsupported syntax");
6645 case unsupported_EGPR_for_addressing
:
6646 err_msg
= _("extended GPR cannot be used as base/index");
6649 as_bad (_("unsupported instruction `%s'"),
6650 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
));
6652 case unsupported_on_arch
:
6653 as_bad (_("`%s' is not supported on `%s%s'"),
6654 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
),
6655 cpu_arch_name
? cpu_arch_name
: default_arch
,
6656 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
6658 case unsupported_64bit
:
6659 if (ISLOWER (mnem_suffix
))
6661 if (flag_code
== CODE_64BIT
)
6662 as_bad (_("`%s%c' is not supported in 64-bit mode"),
6663 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
),
6666 as_bad (_("`%s%c' is only supported in 64-bit mode"),
6667 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
),
6672 if (flag_code
== CODE_64BIT
)
6673 as_bad (_("`%s' is not supported in 64-bit mode"),
6674 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
));
6676 as_bad (_("`%s' is only supported in 64-bit mode"),
6677 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
));
6680 case no_vex_encoding
:
6681 err_msg
= _("no VEX/XOP encoding");
6683 case no_evex_encoding
:
6684 err_msg
= _("no EVEX encoding");
6686 case invalid_sib_address
:
6687 err_msg
= _("invalid SIB address");
6689 case invalid_vsib_address
:
6690 err_msg
= _("invalid VSIB address");
6692 case invalid_vector_register_set
:
6693 err_msg
= _("mask, index, and destination registers must be distinct");
6695 case invalid_tmm_register_set
:
6696 err_msg
= _("all tmm registers must be distinct");
6698 case invalid_dest_and_src_register_set
:
6699 err_msg
= _("destination and source registers must be distinct");
6701 case invalid_dest_register_set
:
6702 err_msg
= _("two dest registers must be distinct");
6704 case invalid_pseudo_prefix
:
6705 err_msg
= _("rex2 pseudo prefix cannot be used");
6707 case unsupported_vector_index_register
:
6708 err_msg
= _("unsupported vector index register");
6710 case unsupported_broadcast
:
6711 err_msg
= _("unsupported broadcast");
6713 case broadcast_needed
:
6714 err_msg
= _("broadcast is needed for operand of such type");
6716 case unsupported_masking
:
6717 err_msg
= _("unsupported masking");
6719 case mask_not_on_destination
:
6720 err_msg
= _("mask not on destination operand");
6722 case no_default_mask
:
6723 err_msg
= _("default mask isn't allowed");
6725 case unsupported_rc_sae
:
6726 err_msg
= _("unsupported static rounding/sae");
6728 case unsupported_vector_size
:
6729 as_bad (_("vector size above %u required for `%s'"), 128u << vector_size
,
6730 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
));
6732 case unsupported_rsp_register
:
6733 err_msg
= _("'rsp' register cannot be used");
6735 case internal_error
:
6736 err_msg
= _("internal error");
6739 as_bad (_("%s for `%s'"), err_msg
,
6740 pass1_mnem
? pass1_mnem
: insn_name (current_templates
.start
));
6746 if (sse_check
!= check_none
6747 /* The opcode space check isn't strictly needed; it's there only to
6748 bypass the logic below when easily possible. */
6749 && t
->opcode_space
>= SPACE_0F
6750 && t
->opcode_space
<= SPACE_0F3A
6751 && !is_cpu (&i
.tm
, CpuSSE4a
)
6752 && !is_any_vex_encoding (t
))
6754 /* Some KL and all WideKL insns have only implicit %xmm operands. */
6755 bool simd
= is_cpu (t
, CpuKL
) || is_cpu (t
, CpuWideKL
);
6757 for (j
= 0; j
< t
->operands
; ++j
)
6759 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
6761 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
6765 if (j
>= t
->operands
&& simd
)
6766 (sse_check
== check_warning
6768 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
6771 if (i
.tm
.opcode_modifier
.fwait
)
6772 if (!add_prefix (FWAIT_OPCODE
))
6775 /* Check if REP prefix is OK. */
6776 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
6778 as_bad (_("invalid instruction `%s' after `%s'"),
6779 insn_name (&i
.tm
), i
.rep_prefix
);
6783 /* Check for lock without a lockable instruction. Destination operand
6784 must be memory unless it is xchg (0x86). */
6785 if (i
.prefix
[LOCK_PREFIX
])
6787 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
6788 || i
.mem_operands
== 0
6789 || (i
.tm
.base_opcode
!= 0x86
6790 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
6792 as_bad (_("expecting lockable instruction after `lock'"));
6796 /* Zap the redundant prefix from XCHG when optimizing. */
6797 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
6798 i
.prefix
[LOCK_PREFIX
] = 0;
6801 if (is_any_vex_encoding (&i
.tm
)
6802 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
6803 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
6805 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
6806 if (i
.prefix
[DATA_PREFIX
])
6808 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
6812 /* Don't allow e.g. KMOV in TLS code sequences. */
6813 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
6816 case BFD_RELOC_X86_64_GOTTPOFF
:
6817 if (i
.tm
.mnem_off
== MN_add
6818 && i
.tm
.opcode_space
== SPACE_EVEXMAP4
6819 && i
.mem_operands
== 1
6821 && i
.base_reg
->reg_num
== RegIP
6822 && i
.tm
.operand_types
[0].bitfield
.class == Reg
6823 && i
.tm
.operand_types
[2].bitfield
.class == Reg
)
6824 /* Allow APX: add %reg1, foo@gottpoff(%rip), %reg2. */
6827 case BFD_RELOC_386_TLS_GOTIE
:
6828 case BFD_RELOC_386_TLS_LE_32
:
6829 case BFD_RELOC_X86_64_TLSLD
:
6830 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
6837 /* Check if HLE prefix is OK. */
6838 if (i
.hle_prefix
&& !check_hle ())
6841 /* Check BND prefix. */
6842 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
6843 as_bad (_("expecting valid branch instruction after `bnd'"));
6845 /* Check NOTRACK prefix. */
6846 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
6847 as_bad (_("expecting indirect branch instruction after `notrack'"));
6849 if (is_cpu (&i
.tm
, CpuMPX
))
6851 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
6852 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
6853 else if (flag_code
!= CODE_16BIT
6854 ? i
.prefix
[ADDR_PREFIX
]
6855 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6856 as_bad (_("16-bit address isn't allowed in MPX instructions"));
6859 /* Insert BND prefix. */
6860 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
6862 if (!i
.prefix
[BND_PREFIX
])
6863 add_prefix (BND_PREFIX_OPCODE
);
6864 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
6866 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
6867 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
6871 /* Check string instruction segment overrides. */
6872 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
6874 gas_assert (i
.mem_operands
);
6875 if (!check_string ())
6877 i
.disp_operands
= 0;
6880 /* The memory operand of (%dx) should be only used with input/output
6881 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
6882 if (i
.input_output_operand
6883 && ((i
.tm
.base_opcode
| 0x82) != 0xee
6884 || i
.tm
.opcode_space
!= SPACE_BASE
))
6886 as_bad (_("input/output port address isn't allowed with `%s'"),
6891 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
6892 optimize_encoding ();
6894 /* Past optimization there's no need to distinguish encoding_evex,
6895 encoding_evex512, and encoding_egpr anymore. */
6896 if (i
.encoding
== encoding_evex512
)
6897 i
.encoding
= encoding_evex
;
6898 else if (i
.encoding
== encoding_egpr
)
6899 i
.encoding
= is_any_vex_encoding (&i
.tm
) ? encoding_evex
6902 if (use_unaligned_vector_move
)
6903 encode_with_unaligned_vector_move ();
6905 if (!process_suffix ())
6908 /* Check if IP-relative addressing requirements can be satisfied. */
6909 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
6910 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
6911 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
6913 /* Update operand types and check extended states. */
6914 for (j
= 0; j
< i
.operands
; j
++)
6916 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
6917 switch (i
.tm
.operand_types
[j
].bitfield
.class)
6922 i
.xstate
|= xstate_mmx
;
6925 i
.xstate
|= xstate_mask
;
6928 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
6929 i
.xstate
|= xstate_tmm
;
6930 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
6931 && !i
.tm
.opcode_modifier
.vex
6932 && vector_size
>= VSZ512
)
6933 i
.xstate
|= xstate_zmm
;
6934 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
6935 && vector_size
>= VSZ256
)
6936 i
.xstate
|= xstate_ymm
;
6937 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
6938 i
.xstate
|= xstate_xmm
;
6943 /* Make still unresolved immediate matches conform to size of immediate
6944 given in i.suffix. */
6945 if (!finalize_imm ())
6948 if (i
.types
[0].bitfield
.imm1
)
6949 i
.imm_operands
= 0; /* kludge for shift insns. */
6951 /* For insns with operands there are more diddles to do to the opcode. */
6954 if (!process_operands ())
6957 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
6959 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
6960 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
6963 if (is_any_vex_encoding (&i
.tm
))
6965 if (!cpu_arch_flags
.bitfield
.cpui286
)
6967 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
6972 /* Check for explicit REX prefix. */
6973 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
6975 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
6979 /* Check for explicit REX2 prefix. */
6980 if (i
.rex2_encoding
)
6982 as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i
.tm
));
6986 if (is_apx_evex_encoding ())
6987 build_apx_evex_prefix ();
6988 else if (i
.tm
.opcode_modifier
.vex
)
6989 build_vex_prefix (t
);
6991 build_evex_prefix ();
6993 /* The individual REX.RXBW bits got consumed. */
6994 i
.rex
&= REX_OPCODE
;
6996 /* The rex2 bits got consumed. */
7000 /* Handle conversion of 'int $3' --> special int3 insn. */
7001 if (i
.tm
.mnem_off
== MN_int
7002 && i
.op
[0].imms
->X_add_number
== 3)
7004 i
.tm
.base_opcode
= INT3_OPCODE
;
7008 if ((i
.tm
.opcode_modifier
.jump
== JUMP
7009 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7010 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
7011 && i
.op
[0].disps
->X_op
== O_constant
)
7013 /* Convert "jmp constant" (and "call constant") to a jump (call) to
7014 the absolute address given by the constant. Since ix86 jumps and
7015 calls are pc relative, we need to generate a reloc. */
7016 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
7017 i
.op
[0].disps
->X_op
= O_symbol
;
7022 insert_lfence_before (last_insn
);
7024 /* We are ready to output the insn. */
7025 output_insn (last_insn
);
7027 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7028 /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been
7029 performed in i386_target_format. */
7030 if (IS_ELF
&& flag_synth_cfi
)
7033 ginsn
= x86_ginsn_new (symbol_temp_new_now (), frch_ginsn_gen_mode ());
7034 frch_ginsn_data_append (ginsn
);
7038 insert_lfence_after ();
7040 if (i
.tm
.opcode_modifier
.isprefix
)
7042 last_insn
->kind
= last_insn_prefix
;
7043 last_insn
->name
= insn_name (&i
.tm
);
7044 last_insn
->file
= as_where (&last_insn
->line
);
7047 last_insn
->kind
= last_insn_other
;
7050 /* The Q suffix is generally valid only in 64-bit mode, with very few
7051 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
7052 and fisttp only one of their two templates is matched below: That's
7053 sufficient since other relevant attributes are the same between both
7054 respective templates. */
7055 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
7057 return flag_code
== CODE_64BIT
7058 || (t
->opcode_space
== SPACE_BASE
7059 && t
->base_opcode
== 0xdf
7060 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
7061 || t
->mnem_off
== MN_cmpxchg8b
;
7065 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
7067 const char *l
= line
, *token_start
= l
;
7069 bool pass1
= !current_templates
.start
;
7071 const insn_template
*t
;
7077 /* Pseudo-prefixes start with an opening figure brace. */
7078 if ((*mnem_p
= *l
) == '{')
7083 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
7088 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
7091 as_bad (_("no such instruction: `%s'"), token_start
);
7096 /* Pseudo-prefixes end with a closing figure brace. */
7097 if (*mnemonic
== '{' && *l
== '}')
7100 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
7104 /* Point l at the closing brace if there's no other separator. */
7105 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
7106 && *l
!= PREFIX_SEPARATOR
)
7109 else if (!is_space_char (*l
)
7110 && *l
!= END_OF_INSN
7112 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
7116 as_bad (_("invalid character %s in mnemonic"),
7117 output_invalid (*l
));
7120 if (token_start
== l
)
7122 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
7123 as_bad (_("expecting prefix; got nothing"));
7125 as_bad (_("expecting mnemonic; got nothing"));
7129 /* Look up instruction (or prefix) via hash table. */
7130 op_lookup (mnemonic
);
7132 if (*l
!= END_OF_INSN
7133 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
7134 && current_templates
.start
7135 && current_templates
.start
->opcode_modifier
.isprefix
)
7137 supported
= cpu_flags_match (current_templates
.start
);
7138 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
7140 as_bad ((flag_code
!= CODE_64BIT
7141 ? _("`%s' is only supported in 64-bit mode")
7142 : _("`%s' is not supported in 64-bit mode")),
7143 insn_name (current_templates
.start
));
7146 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
7148 as_bad (_("`%s' is not supported on `%s%s'"),
7149 insn_name (current_templates
.start
),
7150 cpu_arch_name
? cpu_arch_name
: default_arch
,
7151 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
7154 /* If we are in 16-bit mode, do not allow addr16 or data16.
7155 Similarly, in 32-bit mode, do not allow addr32 or data32. */
7156 if ((current_templates
.start
->opcode_modifier
.size
== SIZE16
7157 || current_templates
.start
->opcode_modifier
.size
== SIZE32
)
7158 && flag_code
!= CODE_64BIT
7159 && ((current_templates
.start
->opcode_modifier
.size
== SIZE32
)
7160 ^ (flag_code
== CODE_16BIT
)))
7162 as_bad (_("redundant %s prefix"),
7163 insn_name (current_templates
.start
));
7167 if (current_templates
.start
->base_opcode
== PSEUDO_PREFIX
)
7169 /* Handle pseudo prefixes. */
7170 switch (current_templates
.start
->extension_opcode
)
7174 i
.disp_encoding
= disp_encoding_8bit
;
7178 i
.disp_encoding
= disp_encoding_16bit
;
7182 i
.disp_encoding
= disp_encoding_32bit
;
7186 i
.dir_encoding
= dir_encoding_load
;
7190 i
.dir_encoding
= dir_encoding_store
;
7194 i
.encoding
= encoding_vex
;
7198 i
.encoding
= encoding_vex3
;
7202 i
.encoding
= encoding_evex
;
7206 i
.rex_encoding
= true;
7210 i
.rex2_encoding
= true;
7212 case Prefix_NoOptimize
:
7214 i
.no_optimize
= true;
7222 /* Add prefix, checking for repeated prefixes. */
7223 switch (add_prefix (current_templates
.start
->base_opcode
))
7228 if (is_cpu (current_templates
.start
, CpuIBT
))
7229 i
.notrack_prefix
= insn_name (current_templates
.start
);
7232 if (is_cpu (current_templates
.start
, CpuHLE
))
7233 i
.hle_prefix
= insn_name (current_templates
.start
);
7234 else if (is_cpu (current_templates
.start
, CpuMPX
))
7235 i
.bnd_prefix
= insn_name (current_templates
.start
);
7237 i
.rep_prefix
= insn_name (current_templates
.start
);
7243 /* Skip past PREFIX_SEPARATOR and reset token_start. */
7253 if (!current_templates
.start
)
7255 /* Deprecated functionality (new code should use pseudo-prefixes instead):
7256 Check if we should swap operand or force 32bit displacement in
7258 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
7260 if (i
.dir_encoding
== dir_encoding_default
)
7261 i
.dir_encoding
= dir_encoding_swap
;
7263 as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"),
7264 i
.dir_encoding
== dir_encoding_load
? "load" : "store");
7266 else if (mnem_p
- 3 == dot_p
7270 if (i
.disp_encoding
== disp_encoding_default
)
7271 i
.disp_encoding
= disp_encoding_8bit
;
7272 else if (i
.disp_encoding
!= disp_encoding_8bit
)
7273 as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'"));
7275 else if (mnem_p
- 4 == dot_p
7280 if (i
.disp_encoding
== disp_encoding_default
)
7281 i
.disp_encoding
= disp_encoding_32bit
;
7282 else if (i
.disp_encoding
!= disp_encoding_32bit
)
7283 as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'"));
7289 op_lookup (mnemonic
);
7292 if (!current_templates
.start
|| !pass1
)
7294 current_templates
.start
= NULL
;
7297 if (mnem_p
> mnemonic
)
7299 /* See if we can get a match by trimming off a suffix. */
7302 case WORD_MNEM_SUFFIX
:
7303 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
7304 i
.suffix
= SHORT_MNEM_SUFFIX
;
7307 case BYTE_MNEM_SUFFIX
:
7308 case QWORD_MNEM_SUFFIX
:
7309 i
.suffix
= mnem_p
[-1];
7311 op_lookup (mnemonic
);
7313 case SHORT_MNEM_SUFFIX
:
7314 case LONG_MNEM_SUFFIX
:
7317 i
.suffix
= mnem_p
[-1];
7319 op_lookup (mnemonic
);
7327 if (intel_float_operand (mnemonic
) == 1)
7328 i
.suffix
= SHORT_MNEM_SUFFIX
;
7330 i
.suffix
= LONG_MNEM_SUFFIX
;
7332 op_lookup (mnemonic
);
7334 /* For compatibility reasons accept MOVSD and CMPSD without
7335 operands even in AT&T mode. */
7336 else if (*l
== END_OF_INSN
7337 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
7340 op_lookup (mnemonic
);
7341 if (current_templates
.start
!= NULL
7343 && (current_templates
.start
->base_opcode
| 2) == 0xa6
7344 && current_templates
.start
->opcode_space
7346 && mnem_p
[-2] == 's')
7348 as_warn (_("found `%sd'; assuming `%sl' was meant"),
7349 mnemonic
, mnemonic
);
7350 i
.suffix
= LONG_MNEM_SUFFIX
;
7354 current_templates
.start
= NULL
;
7362 if (!current_templates
.start
)
7365 as_bad (_("no such instruction: `%s'"), token_start
);
7370 if (current_templates
.start
->opcode_modifier
.jump
== JUMP
7371 || current_templates
.start
->opcode_modifier
.jump
== JUMP_BYTE
)
7373 /* Check for a branch hint. We allow ",pt" and ",pn" for
7374 predict taken and predict not taken respectively.
7375 I'm not sure that branch hints actually do anything on loop
7376 and jcxz insns (JumpByte) for current Pentium4 chips. They
7377 may work in the future and it doesn't hurt to accept them
7379 if (l
[0] == ',' && l
[1] == 'p')
7383 if (!add_prefix (DS_PREFIX_OPCODE
))
7387 else if (l
[2] == 'n')
7389 if (!add_prefix (CS_PREFIX_OPCODE
))
7395 /* Any other comma loses. */
7398 as_bad (_("invalid character %s in mnemonic"),
7399 output_invalid (*l
));
7403 /* Check if instruction is supported on specified architecture. */
7405 for (t
= current_templates
.start
; t
< current_templates
.end
; ++t
)
7407 supported
|= cpu_flags_match (t
);
7409 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
7410 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
7412 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
7418 if (supported
& CPU_FLAGS_64BIT_MATCH
)
7419 i
.error
= unsupported_on_arch
;
7421 i
.error
= unsupported_64bit
;
7428 parse_operands (char *l
, const char *mnemonic
)
7432 /* 1 if operand is pending after ','. */
7433 unsigned int expecting_operand
= 0;
7435 while (*l
!= END_OF_INSN
)
7437 /* Non-zero if operand parens not balanced. */
7438 unsigned int paren_not_balanced
= 0;
7439 /* True if inside double quotes. */
7440 bool in_quotes
= false;
7442 /* Skip optional white space before operand. */
7443 if (is_space_char (*l
))
7445 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
7447 as_bad (_("invalid character %s before operand %d"),
7448 output_invalid (*l
),
7452 token_start
= l
; /* After white space. */
7453 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
7455 if (*l
== END_OF_INSN
)
7459 as_bad (_("unbalanced double quotes in operand %d."),
7463 if (paren_not_balanced
)
7465 know (!intel_syntax
);
7466 as_bad (_("unbalanced parenthesis in operand %d."),
7471 break; /* we are done */
7473 else if (*l
== '\\' && l
[1] == '"')
7476 in_quotes
= !in_quotes
;
7477 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
7479 as_bad (_("invalid character %s in operand %d"),
7480 output_invalid (*l
),
7484 if (!intel_syntax
&& !in_quotes
)
7487 ++paren_not_balanced
;
7489 --paren_not_balanced
;
7493 if (l
!= token_start
)
7494 { /* Yes, we've read in another operand. */
7495 unsigned int operand_ok
;
7496 this_operand
= i
.operands
++;
7497 if (i
.operands
> MAX_OPERANDS
)
7499 as_bad (_("spurious operands; (%d operands/instruction max)"),
7503 i
.types
[this_operand
].bitfield
.unspecified
= 1;
7504 /* Now parse operand adding info to 'i' as we go along. */
7505 END_STRING_AND_SAVE (l
);
7507 if (i
.mem_operands
> 1)
7509 as_bad (_("too many memory references for `%s'"),
7516 i386_intel_operand (token_start
,
7517 intel_float_operand (mnemonic
));
7519 operand_ok
= i386_att_operand (token_start
);
7521 RESTORE_END_STRING (l
);
7527 if (expecting_operand
)
7529 expecting_operand_after_comma
:
7530 as_bad (_("expecting operand after ','; got nothing"));
7535 as_bad (_("expecting operand before ','; got nothing"));
7540 /* Now *l must be either ',' or END_OF_INSN. */
7543 if (*++l
== END_OF_INSN
)
7545 /* Just skip it, if it's \n complain. */
7546 goto expecting_operand_after_comma
;
7548 expecting_operand
= 1;
7555 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
7557 union i386_op temp_op
;
7558 i386_operand_type temp_type
;
7559 unsigned int temp_flags
;
7560 enum bfd_reloc_code_real temp_reloc
;
7562 temp_type
= i
.types
[xchg2
];
7563 i
.types
[xchg2
] = i
.types
[xchg1
];
7564 i
.types
[xchg1
] = temp_type
;
7566 temp_flags
= i
.flags
[xchg2
];
7567 i
.flags
[xchg2
] = i
.flags
[xchg1
];
7568 i
.flags
[xchg1
] = temp_flags
;
7570 temp_op
= i
.op
[xchg2
];
7571 i
.op
[xchg2
] = i
.op
[xchg1
];
7572 i
.op
[xchg1
] = temp_op
;
7574 temp_reloc
= i
.reloc
[xchg2
];
7575 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
7576 i
.reloc
[xchg1
] = temp_reloc
;
7578 temp_flags
= i
.imm_bits
[xchg2
];
7579 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
7580 i
.imm_bits
[xchg1
] = temp_flags
;
7584 if (i
.mask
.operand
== xchg1
)
7585 i
.mask
.operand
= xchg2
;
7586 else if (i
.mask
.operand
== xchg2
)
7587 i
.mask
.operand
= xchg1
;
7589 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7591 if (i
.broadcast
.operand
== xchg1
)
7592 i
.broadcast
.operand
= xchg2
;
7593 else if (i
.broadcast
.operand
== xchg2
)
7594 i
.broadcast
.operand
= xchg1
;
7599 swap_operands (void)
7605 swap_2_operands (1, i
.operands
- 2);
7609 swap_2_operands (0, i
.operands
- 1);
7615 if (i
.mem_operands
== 2)
7617 const reg_entry
*temp_seg
;
7618 temp_seg
= i
.seg
[0];
7619 i
.seg
[0] = i
.seg
[1];
7620 i
.seg
[1] = temp_seg
;
7624 /* Try to ensure constant immediates are represented in the smallest
7629 char guess_suffix
= 0;
7633 guess_suffix
= i
.suffix
;
7634 else if (i
.reg_operands
)
7636 /* Figure out a suffix from the last register operand specified.
7637 We can't do this properly yet, i.e. excluding special register
7638 instances, but the following works for instructions with
7639 immediates. In any case, we can't set i.suffix yet. */
7640 for (op
= i
.operands
; --op
>= 0;)
7641 if (i
.types
[op
].bitfield
.class != Reg
)
7643 else if (i
.types
[op
].bitfield
.byte
)
7645 guess_suffix
= BYTE_MNEM_SUFFIX
;
7648 else if (i
.types
[op
].bitfield
.word
)
7650 guess_suffix
= WORD_MNEM_SUFFIX
;
7653 else if (i
.types
[op
].bitfield
.dword
)
7655 guess_suffix
= LONG_MNEM_SUFFIX
;
7658 else if (i
.types
[op
].bitfield
.qword
)
7660 guess_suffix
= QWORD_MNEM_SUFFIX
;
7664 else if ((flag_code
== CODE_16BIT
)
7665 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
7666 guess_suffix
= WORD_MNEM_SUFFIX
;
7667 else if (flag_code
!= CODE_64BIT
7668 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
7669 /* A more generic (but also more involved) way of dealing
7670 with the special case(s) would be to go look for
7671 DefaultSize attributes on any of the templates. */
7672 && current_templates
.start
->mnem_off
!= MN_push
))
7673 guess_suffix
= LONG_MNEM_SUFFIX
;
7675 for (op
= i
.operands
; --op
>= 0;)
7676 if (operand_type_check (i
.types
[op
], imm
))
7678 switch (i
.op
[op
].imms
->X_op
)
7681 /* If a suffix is given, this operand may be shortened. */
7682 switch (guess_suffix
)
7684 case LONG_MNEM_SUFFIX
:
7685 i
.types
[op
].bitfield
.imm32
= 1;
7686 i
.types
[op
].bitfield
.imm64
= 1;
7688 case WORD_MNEM_SUFFIX
:
7689 i
.types
[op
].bitfield
.imm16
= 1;
7690 i
.types
[op
].bitfield
.imm32
= 1;
7691 i
.types
[op
].bitfield
.imm32s
= 1;
7692 i
.types
[op
].bitfield
.imm64
= 1;
7694 case BYTE_MNEM_SUFFIX
:
7695 i
.types
[op
].bitfield
.imm8
= 1;
7696 i
.types
[op
].bitfield
.imm8s
= 1;
7697 i
.types
[op
].bitfield
.imm16
= 1;
7698 i
.types
[op
].bitfield
.imm32
= 1;
7699 i
.types
[op
].bitfield
.imm32s
= 1;
7700 i
.types
[op
].bitfield
.imm64
= 1;
7704 /* If this operand is at most 16 bits, convert it
7705 to a signed 16 bit number before trying to see
7706 whether it will fit in an even smaller size.
7707 This allows a 16-bit operand such as $0xffe0 to
7708 be recognised as within Imm8S range. */
7709 if ((i
.types
[op
].bitfield
.imm16
)
7710 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
7712 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
7713 ^ 0x8000) - 0x8000);
7716 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
7717 if ((i
.types
[op
].bitfield
.imm32
)
7718 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
7720 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
7721 ^ ((offsetT
) 1 << 31))
7722 - ((offsetT
) 1 << 31));
7726 = operand_type_or (i
.types
[op
],
7727 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
7729 /* We must avoid matching of Imm32 templates when 64bit
7730 only immediate is available. */
7731 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
7732 i
.types
[op
].bitfield
.imm32
= 0;
7739 /* Symbols and expressions. */
7741 /* Convert symbolic operand to proper sizes for matching, but don't
7742 prevent matching a set of insns that only supports sizes other
7743 than those matching the insn suffix. */
7745 i386_operand_type mask
, allowed
;
7746 const insn_template
*t
= current_templates
.start
;
7748 operand_type_set (&mask
, 0);
7749 switch (guess_suffix
)
7751 case QWORD_MNEM_SUFFIX
:
7752 mask
.bitfield
.imm64
= 1;
7753 mask
.bitfield
.imm32s
= 1;
7755 case LONG_MNEM_SUFFIX
:
7756 mask
.bitfield
.imm32
= 1;
7758 case WORD_MNEM_SUFFIX
:
7759 mask
.bitfield
.imm16
= 1;
7761 case BYTE_MNEM_SUFFIX
:
7762 mask
.bitfield
.imm8
= 1;
7768 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
7769 while (++t
< current_templates
.end
)
7771 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
7772 allowed
= operand_type_and (allowed
, mask
);
7775 if (!operand_type_all_zero (&allowed
))
7776 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
7783 /* Try to use the smallest displacement type too. */
7785 optimize_disp (const insn_template
*t
)
7789 if (!want_disp32 (t
)
7790 && (!t
->opcode_modifier
.jump
7791 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
7793 for (op
= 0; op
< i
.operands
; ++op
)
7795 const expressionS
*exp
= i
.op
[op
].disps
;
7797 if (!operand_type_check (i
.types
[op
], disp
))
7800 if (exp
->X_op
!= O_constant
)
7803 /* Since displacement is signed extended to 64bit, don't allow
7804 disp32 if it is out of range. */
7805 if (fits_in_signed_long (exp
->X_add_number
))
7808 i
.types
[op
].bitfield
.disp32
= 0;
7809 if (i
.types
[op
].bitfield
.baseindex
)
7811 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
7812 (uint64_t) exp
->X_add_number
);
7818 /* Don't optimize displacement for movabs since it only takes 64bit
7820 if (i
.disp_encoding
> disp_encoding_8bit
7821 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
7824 for (op
= i
.operands
; op
-- > 0;)
7825 if (operand_type_check (i
.types
[op
], disp
))
7827 if (i
.op
[op
].disps
->X_op
== O_constant
)
7829 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
7831 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
7833 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7834 i
.op
[op
].disps
= NULL
;
7839 if (i
.types
[op
].bitfield
.disp16
7840 && fits_in_unsigned_word (op_disp
))
7842 /* If this operand is at most 16 bits, convert
7843 to a signed 16 bit number and don't use 64bit
7845 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
7846 i
.types
[op
].bitfield
.disp64
= 0;
7850 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
7851 if ((flag_code
!= CODE_64BIT
7852 ? i
.types
[op
].bitfield
.disp32
7854 && (!t
->opcode_modifier
.jump
7855 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
7856 && fits_in_unsigned_long (op_disp
))
7858 /* If this operand is at most 32 bits, convert
7859 to a signed 32 bit number and don't use 64bit
7861 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
7862 i
.types
[op
].bitfield
.disp64
= 0;
7863 i
.types
[op
].bitfield
.disp32
= 1;
7866 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
7868 i
.types
[op
].bitfield
.disp64
= 0;
7869 i
.types
[op
].bitfield
.disp32
= 1;
7872 if ((i
.types
[op
].bitfield
.disp32
7873 || i
.types
[op
].bitfield
.disp16
)
7874 && fits_in_disp8 (op_disp
))
7875 i
.types
[op
].bitfield
.disp8
= 1;
7877 i
.op
[op
].disps
->X_add_number
= op_disp
;
7879 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7880 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
7882 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
7883 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
7884 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7887 /* We only support 64bit displacement on constants. */
7888 i
.types
[op
].bitfield
.disp64
= 0;
7894 /* Return 1 if there is a match in broadcast bytes between operand
7895 GIVEN and instruction template T. */
7898 match_broadcast_size (const insn_template
*t
, unsigned int given
)
7900 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
7901 && i
.types
[given
].bitfield
.byte
)
7902 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
7903 && i
.types
[given
].bitfield
.word
)
7904 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
7905 && i
.types
[given
].bitfield
.dword
)
7906 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
7907 && i
.types
[given
].bitfield
.qword
));
7910 /* Check if operands are valid for the instruction. */
7913 check_VecOperands (const insn_template
*t
)
7918 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
7919 any one operand are implicity requiring AVX512VL support if the actual
7920 operand size is YMMword or XMMword. Since this function runs after
7921 template matching, there's no need to check for YMMword/XMMword in
7923 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
7924 if (!cpu_flags_all_zero (&cpu
)
7925 && !is_cpu (t
, CpuAVX512VL
)
7926 && !cpu_arch_flags
.bitfield
.cpuavx512vl
7927 && (!t
->opcode_modifier
.vex
|| need_evex_encoding (t
)))
7929 for (op
= 0; op
< t
->operands
; ++op
)
7931 if (t
->operand_types
[op
].bitfield
.zmmword
7932 && (i
.types
[op
].bitfield
.ymmword
7933 || i
.types
[op
].bitfield
.xmmword
))
7935 i
.error
= operand_size_mismatch
;
7941 /* Somewhat similarly, templates specifying both AVX and AVX2 are
7942 requiring AVX2 support if the actual operand size is YMMword. */
7943 if (maybe_cpu (t
, CpuAVX
) && maybe_cpu (t
, CpuAVX2
)
7944 && !cpu_arch_flags
.bitfield
.cpuavx2
)
7946 for (op
= 0; op
< t
->operands
; ++op
)
7948 if (t
->operand_types
[op
].bitfield
.xmmword
7949 && i
.types
[op
].bitfield
.ymmword
)
7951 i
.error
= operand_size_mismatch
;
7957 /* Without VSIB byte, we can't have a vector register for index. */
7958 if (!t
->opcode_modifier
.sib
7960 && (i
.index_reg
->reg_type
.bitfield
.xmmword
7961 || i
.index_reg
->reg_type
.bitfield
.ymmword
7962 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
7964 i
.error
= unsupported_vector_index_register
;
7968 /* Check if default mask is allowed. */
7969 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
7970 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
7972 i
.error
= no_default_mask
;
7976 /* For VSIB byte, we need a vector register for index, and all vector
7977 registers must be distinct. */
7978 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
7981 || !((t
->opcode_modifier
.sib
== VECSIB128
7982 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
7983 || (t
->opcode_modifier
.sib
== VECSIB256
7984 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
7985 || (t
->opcode_modifier
.sib
== VECSIB512
7986 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
7988 i
.error
= invalid_vsib_address
;
7992 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
7993 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
7995 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
7996 gas_assert (i
.types
[0].bitfield
.xmmword
7997 || i
.types
[0].bitfield
.ymmword
);
7998 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
7999 gas_assert (i
.types
[2].bitfield
.xmmword
8000 || i
.types
[2].bitfield
.ymmword
);
8001 if (operand_check
== check_none
)
8003 if (register_number (i
.op
[0].regs
)
8004 != register_number (i
.index_reg
)
8005 && register_number (i
.op
[2].regs
)
8006 != register_number (i
.index_reg
)
8007 && register_number (i
.op
[0].regs
)
8008 != register_number (i
.op
[2].regs
))
8010 if (operand_check
== check_error
)
8012 i
.error
= invalid_vector_register_set
;
8015 as_warn (_("mask, index, and destination registers should be distinct"));
8017 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
8019 if (i
.types
[1].bitfield
.class == RegSIMD
8020 && (i
.types
[1].bitfield
.xmmword
8021 || i
.types
[1].bitfield
.ymmword
8022 || i
.types
[1].bitfield
.zmmword
)
8023 && (register_number (i
.op
[1].regs
)
8024 == register_number (i
.index_reg
)))
8026 if (operand_check
== check_error
)
8028 i
.error
= invalid_vector_register_set
;
8031 if (operand_check
!= check_none
)
8032 as_warn (_("index and destination registers should be distinct"));
8037 /* For AMX instructions with 3 TMM register operands, all operands
8038 must be distinct. */
8039 if (i
.reg_operands
== 3
8040 && t
->operand_types
[0].bitfield
.tmmword
8041 && (i
.op
[0].regs
== i
.op
[1].regs
8042 || i
.op
[0].regs
== i
.op
[2].regs
8043 || i
.op
[1].regs
== i
.op
[2].regs
))
8045 i
.error
= invalid_tmm_register_set
;
8049 /* For some special instructions require that destination must be distinct
8050 from source registers. */
8051 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
8053 unsigned int dest_reg
= i
.operands
- 1;
8055 know (i
.operands
>= 3);
8057 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
8058 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
8059 || (i
.reg_operands
> 2
8060 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
8062 i
.error
= invalid_dest_and_src_register_set
;
8067 /* Check if broadcast is supported by the instruction and is applied
8068 to the memory operand. */
8069 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
8071 i386_operand_type type
, overlap
;
8073 /* Check if specified broadcast is supported in this instruction,
8074 and its broadcast bytes match the memory operand. */
8075 op
= i
.broadcast
.operand
;
8076 if (!t
->opcode_modifier
.broadcast
8077 || !(i
.flags
[op
] & Operand_Mem
)
8078 || (!i
.types
[op
].bitfield
.unspecified
8079 && !match_broadcast_size (t
, op
)))
8082 i
.error
= unsupported_broadcast
;
8086 operand_type_set (&type
, 0);
8087 switch (get_broadcast_bytes (t
, false))
8090 type
.bitfield
.word
= 1;
8093 type
.bitfield
.dword
= 1;
8096 type
.bitfield
.qword
= 1;
8099 type
.bitfield
.xmmword
= 1;
8102 if (vector_size
< VSZ256
)
8104 type
.bitfield
.ymmword
= 1;
8107 if (vector_size
< VSZ512
)
8109 type
.bitfield
.zmmword
= 1;
8115 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
8116 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
8117 && t
->operand_types
[op
].bitfield
.byte
8118 + t
->operand_types
[op
].bitfield
.word
8119 + t
->operand_types
[op
].bitfield
.dword
8120 + t
->operand_types
[op
].bitfield
.qword
> 1)
8122 overlap
.bitfield
.xmmword
= 0;
8123 overlap
.bitfield
.ymmword
= 0;
8124 overlap
.bitfield
.zmmword
= 0;
8126 if (operand_type_all_zero (&overlap
))
8129 if (t
->opcode_modifier
.checkoperandsize
)
8133 type
.bitfield
.baseindex
= 1;
8134 for (j
= 0; j
< i
.operands
; ++j
)
8137 && !operand_type_register_match(i
.types
[j
],
8138 t
->operand_types
[j
],
8140 t
->operand_types
[op
]))
8145 /* If broadcast is supported in this instruction, we need to check if
8146 operand of one-element size isn't specified without broadcast. */
8147 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
8149 /* Find memory operand. */
8150 for (op
= 0; op
< i
.operands
; op
++)
8151 if (i
.flags
[op
] & Operand_Mem
)
8153 gas_assert (op
< i
.operands
);
8154 /* Check size of the memory operand. */
8155 if (match_broadcast_size (t
, op
))
8157 i
.error
= broadcast_needed
;
8162 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
8164 /* Check if requested masking is supported. */
8167 if (!t
->opcode_modifier
.masking
)
8169 i
.error
= unsupported_masking
;
8173 /* Common rules for masking:
8174 - mask register destinations permit only zeroing-masking, without
8175 that actually being expressed by a {z} operand suffix or EVEX.z,
8176 - memory destinations allow only merging-masking,
8177 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
8180 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
8181 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
8182 || t
->opcode_modifier
.sib
))
8184 i
.error
= unsupported_masking
;
8189 /* Check if masking is applied to dest operand. */
8190 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
8192 i
.error
= mask_not_on_destination
;
8197 if (i
.rounding
.type
!= rc_none
)
8199 if (!t
->opcode_modifier
.sae
8200 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
8203 i
.error
= unsupported_rc_sae
;
8207 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
8209 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
8211 for (op
= 0; op
< t
->operands
; ++op
)
8212 if (i
.types
[op
].bitfield
.zmmword
)
8214 if (op
>= t
->operands
)
8216 i
.error
= operand_size_mismatch
;
8222 /* Check the special Imm4 cases; must be the first operand. */
8223 if ((is_cpu (t
, CpuXOP
) && t
->operands
== 5)
8224 || (t
->opcode_space
== SPACE_0F3A
8225 && (t
->base_opcode
| 3) == 0x0b
8226 && is_cpu (t
, CpuAPX_F
)))
8228 if (i
.op
[0].imms
->X_op
!= O_constant
8229 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
8235 /* Turn off Imm<N> so that update_imm won't complain. */
8236 if (t
->operands
== 5)
8237 operand_type_set (&i
.types
[0], 0);
8240 /* Check vector Disp8 operand. */
8241 if (t
->opcode_modifier
.disp8memshift
8242 && (!t
->opcode_modifier
.vex
8243 || need_evex_encoding (t
))
8244 && i
.disp_encoding
<= disp_encoding_8bit
)
8246 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
8247 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
8248 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
8249 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
8252 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
8255 for (op
= 0; op
< i
.operands
; op
++)
8256 if (i
.flags
[op
] & Operand_Mem
)
8258 if (t
->opcode_modifier
.evex
== EVEXLIG
)
8259 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
8260 else if (t
->operand_types
[op
].bitfield
.xmmword
8261 + t
->operand_types
[op
].bitfield
.ymmword
8262 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
8263 type
= &t
->operand_types
[op
];
8264 else if (!i
.types
[op
].bitfield
.unspecified
)
8265 type
= &i
.types
[op
];
8266 else /* Ambiguities get resolved elsewhere. */
8267 fallback
= &t
->operand_types
[op
];
8269 else if (i
.types
[op
].bitfield
.class == RegSIMD
8270 && t
->opcode_modifier
.evex
!= EVEXLIG
)
8272 if (i
.types
[op
].bitfield
.zmmword
)
8274 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
8276 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
8280 if (!type
&& !i
.memshift
)
8284 if (type
->bitfield
.zmmword
)
8286 else if (type
->bitfield
.ymmword
)
8288 else if (type
->bitfield
.xmmword
)
8292 /* For the check in fits_in_disp8(). */
8293 if (i
.memshift
== 0)
8297 for (op
= 0; op
< i
.operands
; op
++)
8298 if (operand_type_check (i
.types
[op
], disp
)
8299 && i
.op
[op
].disps
->X_op
== O_constant
)
8301 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
8303 i
.types
[op
].bitfield
.disp8
= 1;
8306 i
.types
[op
].bitfield
.disp8
= 0;
8315 /* Check if encoding requirements are met by the instruction. */
8318 VEX_check_encoding (const insn_template
*t
)
8320 if (i
.encoding
== encoding_error
)
8322 i
.error
= unsupported
;
8326 /* Vector size restrictions. */
8327 if ((vector_size
< VSZ512
8328 && t
->opcode_modifier
.evex
== EVEX512
)
8329 || (vector_size
< VSZ256
8330 && (t
->opcode_modifier
.evex
== EVEX256
8331 || t
->opcode_modifier
.vex
== VEX256
)))
8333 i
.error
= unsupported_vector_size
;
8339 case encoding_default
:
8344 /* This instruction must be encoded with VEX prefix. */
8345 if (!t
->opcode_modifier
.vex
)
8347 i
.error
= no_vex_encoding
;
8353 case encoding_evex512
:
8354 /* This instruction must be encoded with EVEX prefix. */
8355 if (!t
->opcode_modifier
.evex
)
8357 i
.error
= no_evex_encoding
;
8363 /* This instruction must be encoded with REX2 or EVEX prefix. */
8364 if (t
->opcode_modifier
.vex
&& !t
->opcode_modifier
.evex
)
8366 i
.error
= no_evex_encoding
;
8378 /* Check if Egprs operands are valid for the instruction. */
8381 check_EgprOperands (const insn_template
*t
)
8383 if (!t
->opcode_modifier
.noegpr
)
8386 for (unsigned int op
= 0; op
< i
.operands
; op
++)
8388 if (i
.types
[op
].bitfield
.class != Reg
)
8391 if (i
.op
[op
].regs
->reg_flags
& RegRex2
)
8393 i
.error
= register_type_mismatch
;
8398 if ((i
.index_reg
&& (i
.index_reg
->reg_flags
& RegRex2
))
8399 || (i
.base_reg
&& (i
.base_reg
->reg_flags
& RegRex2
)))
8401 i
.error
= unsupported_EGPR_for_addressing
;
8405 /* Check if pseudo prefix {rex2} is valid. */
8406 if (i
.rex2_encoding
&& !t
->opcode_modifier
.sse2avx
)
8408 i
.error
= invalid_pseudo_prefix
;
8415 /* Check if APX operands are valid for the instruction. */
8417 check_APX_operands (const insn_template
*t
)
8419 /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
8421 switch (t
->mnem_off
)
8425 if (register_number (i
.op
[0].regs
) == register_number (i
.op
[1].regs
))
8427 i
.error
= invalid_dest_register_set
;
8433 if (register_number (i
.op
[0].regs
) == 4
8434 || register_number (i
.op
[1].regs
) == 4)
8436 i
.error
= unsupported_rsp_register
;
8444 /* Check if the instruction use the REX registers or REX prefix. */
8446 check_Rex_required (void)
8448 for (unsigned int op
= 0; op
< i
.operands
; op
++)
8450 if (i
.types
[op
].bitfield
.class != Reg
)
8453 if (i
.op
[op
].regs
->reg_flags
& (RegRex
| RegRex64
))
8457 if ((i
.index_reg
&& (i
.index_reg
->reg_flags
& (RegRex
| RegRex64
)))
8458 || (i
.base_reg
&& (i
.base_reg
->reg_flags
& (RegRex
| RegRex64
))))
8461 /* Check pseudo prefix {rex} are valid. */
8462 return i
.rex_encoding
;
8465 /* Optimize APX NDD insns to legacy insns. */
8467 can_convert_NDD_to_legacy (const insn_template
*t
)
8469 unsigned int match_dest_op
= ~0;
8471 if (!i
.tm
.opcode_modifier
.nf
8472 && i
.reg_operands
>= 2)
8474 unsigned int dest
= i
.operands
- 1;
8475 unsigned int src1
= i
.operands
- 2;
8476 unsigned int src2
= (i
.operands
> 3) ? i
.operands
- 3 : 0;
8478 if (i
.types
[src1
].bitfield
.class == Reg
8479 && i
.op
[src1
].regs
== i
.op
[dest
].regs
)
8480 match_dest_op
= src1
;
8481 /* If the first operand is the same as the third operand,
8482 these instructions need to support the ability to commutative
8483 the first two operands and still not change the semantics in order
8485 else if (optimize
> 1
8486 && t
->opcode_modifier
.commutative
8487 && i
.types
[src2
].bitfield
.class == Reg
8488 && i
.op
[src2
].regs
== i
.op
[dest
].regs
)
8489 match_dest_op
= src2
;
8491 return match_dest_op
;
8494 /* Helper function for the progress() macro in match_template(). */
8495 static INLINE
enum i386_error
progress (enum i386_error
new,
8496 enum i386_error last
,
8497 unsigned int line
, unsigned int *line_p
)
8499 if (line
<= *line_p
)
8505 static const insn_template
*
8506 match_template (char mnem_suffix
)
8508 /* Points to template once we've found it. */
8509 const insn_template
*t
;
8510 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
8511 i386_operand_type overlap4
;
8512 unsigned int found_reverse_match
;
8513 i386_operand_type operand_types
[MAX_OPERANDS
];
8514 int addr_prefix_disp
;
8515 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
8516 enum i386_error specific_error
= number_of_operands_mismatch
;
8517 #define progress(err) progress (err, specific_error, __LINE__, &errline)
8519 #if MAX_OPERANDS != 5
8520 # error "MAX_OPERANDS must be 5."
8523 found_reverse_match
= 0;
8524 addr_prefix_disp
= -1;
8526 for (t
= current_templates
.start
; t
< current_templates
.end
; t
++)
8528 addr_prefix_disp
= -1;
8529 found_reverse_match
= 0;
8531 /* Must have right number of operands. */
8532 if (i
.operands
!= t
->operands
)
8535 /* Skip SSE2AVX templates when inapplicable. */
8536 if (t
->opcode_modifier
.sse2avx
8537 && (!sse2avx
|| i
.prefix
[DATA_PREFIX
]))
8539 /* Another non-SSE2AVX template has to follow. */
8540 gas_assert (t
+ 1 < current_templates
.end
);
8544 /* Check processor support. */
8545 specific_error
= progress (unsupported
);
8546 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
8549 /* Check AT&T mnemonic. */
8550 specific_error
= progress (unsupported_with_intel_mnemonic
);
8551 if (!intel_syntax
&& intel_mnemonic
8552 && t
->opcode_modifier
.dialect
== ATT_MNEMONIC
)
8555 /* Check AT&T/Intel syntax. */
8556 specific_error
= progress (unsupported_syntax
);
8558 ? t
->opcode_modifier
.dialect
>= ATT_SYNTAX
8559 : t
->opcode_modifier
.dialect
== INTEL_SYNTAX
)
8562 /* Check Intel64/AMD64 ISA. */
8566 /* Default: Don't accept Intel64. */
8567 if (t
->opcode_modifier
.isa64
== INTEL64
)
8571 /* -mamd64: Don't accept Intel64 and Intel64 only. */
8572 if (t
->opcode_modifier
.isa64
>= INTEL64
)
8576 /* -mintel64: Don't accept AMD64. */
8577 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
8582 /* Check the suffix. */
8583 specific_error
= progress (invalid_instruction_suffix
);
8584 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
8585 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
8586 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
8587 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
8588 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
8591 specific_error
= progress (operand_size_mismatch
);
8592 size_match
= operand_size_match (t
);
8596 /* This is intentionally not
8598 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
8600 as the case of a missing * on the operand is accepted (perhaps with
8601 a warning, issued further down). */
8602 specific_error
= progress (operand_type_mismatch
);
8603 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
8606 /* In Intel syntax, normally we can check for memory operand size when
8607 there is no mnemonic suffix. But jmp and call have 2 different
8608 encodings with Dword memory operand size. Skip the "near" one
8609 (permitting a register operand) when "far" was requested. */
8611 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
8612 && t
->operand_types
[0].bitfield
.class == Reg
)
8615 for (j
= 0; j
< MAX_OPERANDS
; j
++)
8616 operand_types
[j
] = t
->operand_types
[j
];
8618 /* In general, don't allow 32-bit operands on pre-386. */
8619 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
8620 : operand_size_mismatch
);
8621 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
8622 if (i
.suffix
== LONG_MNEM_SUFFIX
8623 && !cpu_arch_flags
.bitfield
.cpui386
8625 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
8626 && !intel_float_operand (insn_name (t
)))
8627 : intel_float_operand (insn_name (t
)) != 2)
8628 && (t
->operands
== i
.imm_operands
8629 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
8630 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
8631 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
8632 || (operand_types
[j
].bitfield
.class != RegMMX
8633 && operand_types
[j
].bitfield
.class != RegSIMD
8634 && operand_types
[j
].bitfield
.class != RegMask
))
8635 && !t
->opcode_modifier
.sib
)
8638 /* Do not verify operands when there are none. */
8641 if (VEX_check_encoding (t
))
8643 specific_error
= progress (i
.error
);
8647 /* Check if pseudo prefix {rex2} is valid. */
8648 if (t
->opcode_modifier
.noegpr
&& i
.rex2_encoding
)
8650 specific_error
= progress (invalid_pseudo_prefix
);
8654 /* We've found a match; break out of loop. */
8658 if (!t
->opcode_modifier
.jump
8659 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
8661 /* There should be only one Disp operand. */
8662 for (j
= 0; j
< MAX_OPERANDS
; j
++)
8663 if (operand_type_check (operand_types
[j
], disp
))
8665 if (j
< MAX_OPERANDS
)
8667 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8669 addr_prefix_disp
= j
;
8671 /* Address size prefix will turn Disp64 operand into Disp32 and
8672 Disp32/Disp16 one into Disp16/Disp32 respectively. */
8676 override
= !override
;
8679 if (operand_types
[j
].bitfield
.disp32
8680 && operand_types
[j
].bitfield
.disp16
)
8682 operand_types
[j
].bitfield
.disp16
= override
;
8683 operand_types
[j
].bitfield
.disp32
= !override
;
8685 gas_assert (!operand_types
[j
].bitfield
.disp64
);
8689 if (operand_types
[j
].bitfield
.disp64
)
8691 gas_assert (!operand_types
[j
].bitfield
.disp32
);
8692 operand_types
[j
].bitfield
.disp32
= override
;
8693 operand_types
[j
].bitfield
.disp64
= !override
;
8695 operand_types
[j
].bitfield
.disp16
= 0;
8701 /* We check register size if needed. */
8702 if (t
->opcode_modifier
.checkoperandsize
)
8704 check_register
= (1 << t
->operands
) - 1;
8705 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
8706 check_register
&= ~(1 << i
.broadcast
.operand
);
8711 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
8712 switch (t
->operands
)
8715 if (!operand_type_match (overlap0
, i
.types
[0]))
8718 /* Allow the ModR/M encoding to be requested by using the {load} or
8719 {store} pseudo prefix on an applicable insn. */
8720 if (!t
->opcode_modifier
.modrm
8721 && i
.reg_operands
== 1
8722 && ((i
.dir_encoding
== dir_encoding_load
8723 && t
->mnem_off
!= MN_pop
)
8724 || (i
.dir_encoding
== dir_encoding_store
8725 && t
->mnem_off
!= MN_push
))
8727 && t
->mnem_off
!= MN_bswap
)
8732 /* xchg %eax, %eax is a special case. It is an alias for nop
8733 only in 32bit mode and we can use opcode 0x90. In 64bit
8734 mode, we can't use 0x90 for xchg %eax, %eax since it should
8735 zero-extend %eax to %rax. */
8736 if (t
->base_opcode
== 0x90
8737 && t
->opcode_space
== SPACE_BASE
)
8739 if (flag_code
== CODE_64BIT
8740 && i
.types
[0].bitfield
.instance
== Accum
8741 && i
.types
[0].bitfield
.dword
8742 && i
.types
[1].bitfield
.instance
== Accum
)
8745 /* Allow the ModR/M encoding to be requested by using the
8746 {load} or {store} pseudo prefix. */
8747 if (i
.dir_encoding
== dir_encoding_load
8748 || i
.dir_encoding
== dir_encoding_store
)
8752 if (t
->base_opcode
== MOV_AX_DISP32
8753 && t
->opcode_space
== SPACE_BASE
8754 && t
->mnem_off
!= MN_movabs
)
8756 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
8757 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
8760 /* xrelease mov %eax, <disp> is another special case. It must not
8761 match the accumulator-only encoding of mov. */
8765 /* Allow the ModR/M encoding to be requested by using a suitable
8766 {load} or {store} pseudo prefix. */
8767 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
8768 ? dir_encoding_store
8769 : dir_encoding_load
)
8770 && !i
.types
[0].bitfield
.disp64
8771 && !i
.types
[1].bitfield
.disp64
)
8775 /* Allow the ModR/M encoding to be requested by using the {load} or
8776 {store} pseudo prefix on an applicable insn. */
8777 if (!t
->opcode_modifier
.modrm
8778 && i
.reg_operands
== 1
8779 && i
.imm_operands
== 1
8780 && (i
.dir_encoding
== dir_encoding_load
8781 || i
.dir_encoding
== dir_encoding_store
)
8782 && t
->opcode_space
== SPACE_BASE
)
8784 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
8785 && i
.dir_encoding
== dir_encoding_store
)
8788 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
8789 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
8790 || i
.dir_encoding
== dir_encoding_load
))
8793 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
8794 && i
.dir_encoding
== dir_encoding_load
)
8800 if (!(size_match
& MATCH_STRAIGHT
))
8802 /* Reverse direction of operands if swapping is possible in the first
8803 place (operands need to be symmetric) and
8804 - the load form is requested, and the template is a store form,
8805 - the store form is requested, and the template is a load form,
8806 - the non-default (swapped) form is requested. */
8807 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
8809 j
= i
.operands
- 1 - (t
->opcode_space
== SPACE_EVEXMAP4
8810 && t
->opcode_modifier
.vexvvvv
);
8812 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
8813 && !operand_type_all_zero (&overlap1
))
8814 switch (i
.dir_encoding
)
8816 case dir_encoding_load
:
8817 if (operand_type_check (operand_types
[j
], anymem
)
8818 || t
->opcode_modifier
.regmem
)
8822 case dir_encoding_store
:
8823 if (!operand_type_check (operand_types
[j
], anymem
)
8824 && !t
->opcode_modifier
.regmem
)
8828 case dir_encoding_swap
:
8831 case dir_encoding_default
:
8835 /* If we want store form, we skip the current load. */
8836 if ((i
.dir_encoding
== dir_encoding_store
8837 || i
.dir_encoding
== dir_encoding_swap
)
8838 && i
.mem_operands
== 0
8839 && t
->opcode_modifier
.load
)
8844 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
8845 if (!operand_type_match (overlap0
, i
.types
[0])
8846 || !operand_type_match (overlap1
, i
.types
[1])
8847 || ((check_register
& 3) == 3
8848 && !operand_type_register_match (i
.types
[0],
8853 specific_error
= progress (i
.error
);
8855 /* Check if other direction is valid ... */
8856 if (!t
->opcode_modifier
.d
)
8860 if (!(size_match
& MATCH_REVERSE
))
8862 /* Try reversing direction of operands. */
8863 j
= is_cpu (t
, CpuFMA4
)
8864 || is_cpu (t
, CpuXOP
)
8865 || is_cpu (t
, CpuAPX_F
) ? 1 : i
.operands
- 1;
8866 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
8867 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
8868 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
8869 gas_assert (t
->operands
!= 3 || !check_register
8870 || is_cpu (t
, CpuAPX_F
));
8871 if (!operand_type_match (overlap0
, i
.types
[0])
8872 || !operand_type_match (overlap1
, i
.types
[j
])
8873 || (t
->operands
== 3
8874 && !operand_type_match (overlap2
, i
.types
[1]))
8876 && !operand_type_register_match (i
.types
[0],
8881 /* Does not match either direction. */
8882 specific_error
= progress (i
.error
);
8885 /* found_reverse_match holds which variant of D
8887 if (!t
->opcode_modifier
.d
)
8888 found_reverse_match
= 0;
8889 else if (operand_types
[0].bitfield
.tbyte
)
8891 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
8892 found_reverse_match
= Opcode_FloatD
;
8894 found_reverse_match
= ~0;
8895 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
8896 if ((t
->extension_opcode
& 4)
8897 && (intel_syntax
|| intel_mnemonic
))
8898 found_reverse_match
|= Opcode_FloatR
;
8900 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
8902 found_reverse_match
= Opcode_VexW
;
8903 goto check_operands_345
;
8905 else if (is_cpu (t
, CpuAPX_F
) && i
.operands
== 3)
8907 found_reverse_match
= Opcode_D
;
8908 goto check_operands_345
;
8910 else if (t
->opcode_space
!= SPACE_BASE
8911 && (t
->opcode_space
!= SPACE_0F
8912 /* MOV to/from CR/DR/TR, as an exception, follow
8913 the base opcode space encoding model. */
8914 || (t
->base_opcode
| 7) != 0x27))
8915 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
8916 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
8917 else if (!t
->opcode_modifier
.commutative
)
8918 found_reverse_match
= Opcode_D
;
8920 found_reverse_match
= ~0;
8924 /* Found a forward 2 operand match here. */
8926 switch (t
->operands
)
8929 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
8930 if (!operand_type_match (overlap4
, i
.types
[4])
8931 || !operand_type_register_match (i
.types
[3],
8936 specific_error
= progress (i
.error
);
8941 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
8942 if (!operand_type_match (overlap3
, i
.types
[3])
8943 || ((check_register
& 0xa) == 0xa
8944 && !operand_type_register_match (i
.types
[1],
8948 || ((check_register
& 0xc) == 0xc
8949 && !operand_type_register_match (i
.types
[2],
8954 specific_error
= progress (i
.error
);
8959 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
8960 if (!operand_type_match (overlap2
, i
.types
[2])
8961 || ((check_register
& 5) == 5
8962 && !operand_type_register_match (i
.types
[0],
8966 || ((check_register
& 6) == 6
8967 && !operand_type_register_match (i
.types
[1],
8972 specific_error
= progress (i
.error
);
8978 /* Found either forward/reverse 2, 3 or 4 operand match here:
8979 slip through to break. */
8982 /* Check if VEX/EVEX encoding requirements can be satisfied. */
8983 if (VEX_check_encoding (t
))
8985 specific_error
= progress (i
.error
);
8989 /* Check if EGPR operands(r16-r31) are valid. */
8990 if (check_EgprOperands (t
))
8992 specific_error
= progress (i
.error
);
8996 /* Check if vector operands are valid. */
8997 if (check_VecOperands (t
))
8999 specific_error
= progress (i
.error
);
9003 /* Check if APX operands are valid. */
9004 if (check_APX_operands (t
))
9006 specific_error
= progress (i
.error
);
9010 /* Check whether to use the shorter VEX encoding for certain insns where
9011 the EVEX encoding comes first in the table. This requires the respective
9012 AVX-* feature to be explicitly enabled.
9014 Most of the respective insns have just a single EVEX and a single VEX
9015 template. The one that's presently different is generated using the
9016 Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter
9017 two of which may fall back to their two corresponding VEX forms. */
9018 j
= t
->mnem_off
!= MN_vcvtneps2bf16
? 1 : 2;
9019 if ((t
== current_templates
.start
|| j
> 1)
9020 && t
->opcode_modifier
.disp8memshift
9021 && !t
->opcode_modifier
.vex
9022 && !need_evex_encoding (t
)
9023 && t
+ j
< current_templates
.end
9024 && t
[j
].opcode_modifier
.vex
)
9027 unsigned int memshift
= i
.memshift
;
9030 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[j
].cpu
),
9031 cpu_arch_isa_flags
);
9032 if (!cpu_flags_all_zero (&cpu
)
9033 && (!i
.types
[0].bitfield
.disp8
9034 || !operand_type_check (i
.types
[0], disp
)
9035 || i
.op
[0].disps
->X_op
!= O_constant
9036 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
9038 specific_error
= progress (internal_error
);
9042 i
.memshift
= memshift
;
9045 /* If we can optimize a NDD insn to legacy insn, like
9046 add %r16, %r8, %r8 -> add %r16, %r8,
9047 add %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
9048 Note that the semantics have not been changed. */
9051 && i
.encoding
!= encoding_evex
9052 && ((t
+ 1 < current_templates
.end
9053 && !t
[1].opcode_modifier
.evex
9054 && t
[1].opcode_space
<= SPACE_0F38
9055 && t
->opcode_modifier
.vexvvvv
== VexVVVV_DST
)
9056 || t
->mnem_off
== MN_movbe
)
9057 && (i
.types
[i
.operands
- 1].bitfield
.dword
9058 || i
.types
[i
.operands
- 1].bitfield
.qword
))
9060 unsigned int match_dest_op
= can_convert_NDD_to_legacy (t
);
9062 if (match_dest_op
!= (unsigned int) ~0)
9065 /* We ensure that the next template has the same input
9066 operands as the original matching template by the first
9067 opernd (ATT). To avoid someone support new NDD insns and
9068 put it in the wrong position. */
9069 overlap0
= operand_type_and (i
.types
[0],
9070 t
[1].operand_types
[0]);
9071 if (t
->opcode_modifier
.d
)
9072 overlap1
= operand_type_and (i
.types
[0],
9073 t
[1].operand_types
[1]);
9074 if (!operand_type_match (overlap0
, i
.types
[0])
9075 && (!t
->opcode_modifier
.d
9076 || !operand_type_match (overlap1
, i
.types
[0])))
9080 && (t
[1].opcode_space
<= SPACE_0F
9081 /* Some non-legacy-map0/1 insns can be shorter when
9082 legacy-encoded and when no REX prefix is required. */
9083 || (!check_EgprOperands (t
+ 1)
9084 && !check_Rex_required ()
9085 && !i
.op
[i
.operands
- 1].regs
->reg_type
.bitfield
.qword
)))
9087 if (i
.operands
> 2 && match_dest_op
== i
.operands
- 3)
9088 swap_2_operands (match_dest_op
, i
.operands
- 2);
9093 if (t
->mnem_off
== MN_movbe
)
9095 gas_assert (t
[1].mnem_off
== MN_bswap
);
9096 ++current_templates
.end
;
9099 specific_error
= progress (internal_error
);
9106 /* We've found a match; break out of loop. */
9112 if (t
== current_templates
.end
)
9114 /* We found no match. */
9115 i
.error
= specific_error
;
9119 if (!quiet_warnings
)
9122 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
9123 as_warn (_("indirect %s without `*'"), insn_name (t
));
9125 if (t
->opcode_modifier
.isprefix
9126 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
9128 /* Warn them that a data or address size prefix doesn't
9129 affect assembly of the next line of code. */
9130 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
9134 /* Copy the template we found. */
9135 install_template (t
);
9137 if (addr_prefix_disp
!= -1)
9138 i
.tm
.operand_types
[addr_prefix_disp
]
9139 = operand_types
[addr_prefix_disp
];
9141 /* APX insns acting on byte operands are WIG, yet that can't be expressed
9142 in the templates (they're also covering word/dword/qword operands). */
9143 if (t
->opcode_space
== SPACE_EVEXMAP4
&& !t
->opcode_modifier
.vexw
&&
9144 i
.types
[i
.operands
- 1].bitfield
.byte
)
9146 gas_assert (t
->opcode_modifier
.w
);
9147 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
9150 switch (found_reverse_match
)
9156 case Opcode_FloatR
| Opcode_FloatD
:
9157 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
9158 found_reverse_match
&= Opcode_FloatD
;
9162 /* If we found a reverse match we must alter the opcode direction
9163 bit and clear/flip the regmem modifier one. found_reverse_match
9164 holds bits to change (different for int & float insns). */
9166 i
.tm
.base_opcode
^= found_reverse_match
;
9168 if (i
.tm
.opcode_space
== SPACE_EVEXMAP4
)
9171 /* Certain SIMD insns have their load forms specified in the opcode
9172 table, and hence we need to _set_ RegMem instead of clearing it.
9173 We need to avoid setting the bit though on insns like KMOVW. */
9174 i
.tm
.opcode_modifier
.regmem
9175 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
9176 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
9177 && !i
.tm
.opcode_modifier
.regmem
;
9181 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
9182 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
9186 /* Only the first two register operands need reversing, alongside
9188 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
9191 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
9192 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
9193 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
9203 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
9204 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
9206 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
9208 as_bad (_("`%s' operand %u must use `%ses' segment"),
9210 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
9215 /* There's only ever one segment override allowed per instruction.
9216 This instruction possibly has a legal segment override on the
9217 second operand, so copy the segment to where non-string
9218 instructions store it, allowing common code. */
9219 i
.seg
[op
] = i
.seg
[1];
9225 process_suffix (void)
9227 bool is_movx
= false;
9229 /* If matched instruction specifies an explicit instruction mnemonic
9231 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
9232 i
.suffix
= WORD_MNEM_SUFFIX
;
9233 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
9234 i
.suffix
= LONG_MNEM_SUFFIX
;
9235 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
9236 i
.suffix
= QWORD_MNEM_SUFFIX
;
9237 else if (i
.reg_operands
9238 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
9239 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
9241 unsigned int numop
= i
.operands
;
9244 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
9245 && (i
.tm
.base_opcode
| 8) == 0xbe)
9246 || (i
.tm
.opcode_space
== SPACE_BASE
9247 && i
.tm
.base_opcode
== 0x63
9248 && is_cpu (&i
.tm
, Cpu64
));
9250 /* movsx/movzx want only their source operand considered here, for the
9251 ambiguity checking below. The suffix will be replaced afterwards
9252 to represent the destination (register). */
9253 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
9256 /* crc32 needs REX.W set regardless of suffix / source operand size. */
9257 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
9260 /* If there's no instruction mnemonic suffix we try to invent one
9261 based on GPR operands. */
9264 /* We take i.suffix from the last register operand specified,
9265 Destination register type is more significant than source
9266 register type. crc32 in SSE4.2 prefers source register
9268 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
9271 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
9272 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9274 if (i
.types
[op
].bitfield
.class != Reg
)
9276 if (i
.types
[op
].bitfield
.byte
)
9277 i
.suffix
= BYTE_MNEM_SUFFIX
;
9278 else if (i
.types
[op
].bitfield
.word
)
9279 i
.suffix
= WORD_MNEM_SUFFIX
;
9280 else if (i
.types
[op
].bitfield
.dword
)
9281 i
.suffix
= LONG_MNEM_SUFFIX
;
9282 else if (i
.types
[op
].bitfield
.qword
)
9283 i
.suffix
= QWORD_MNEM_SUFFIX
;
9289 /* As an exception, movsx/movzx silently default to a byte source
9291 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
9292 i
.suffix
= BYTE_MNEM_SUFFIX
;
9294 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
9296 if (!check_byte_reg ())
9299 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
9301 if (!check_long_reg ())
9304 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
9306 if (!check_qword_reg ())
9309 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
9311 if (!check_word_reg ())
9314 else if (intel_syntax
9315 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
9316 /* Do nothing if the instruction is going to ignore the prefix. */
9321 /* Undo the movsx/movzx change done above. */
9324 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
9327 i
.suffix
= stackop_size
;
9328 if (stackop_size
== LONG_MNEM_SUFFIX
)
9330 /* stackop_size is set to LONG_MNEM_SUFFIX for the
9331 .code16gcc directive to support 16-bit mode with
9332 32-bit address. For IRET without a suffix, generate
9333 16-bit IRET (opcode 0xcf) to return from an interrupt
9335 if (i
.tm
.base_opcode
== 0xcf)
9337 i
.suffix
= WORD_MNEM_SUFFIX
;
9338 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
9340 /* Warn about changed behavior for segment register push/pop. */
9341 else if ((i
.tm
.base_opcode
| 1) == 0x07)
9342 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
9347 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
9348 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9349 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
9350 || (i
.tm
.opcode_space
== SPACE_0F
9351 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
9352 && i
.tm
.extension_opcode
<= 3)))
9357 if (!i
.tm
.opcode_modifier
.no_qsuf
)
9359 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9360 || i
.tm
.opcode_modifier
.no_lsuf
)
9361 i
.suffix
= QWORD_MNEM_SUFFIX
;
9366 if (!i
.tm
.opcode_modifier
.no_lsuf
)
9367 i
.suffix
= LONG_MNEM_SUFFIX
;
9370 if (!i
.tm
.opcode_modifier
.no_wsuf
)
9371 i
.suffix
= WORD_MNEM_SUFFIX
;
9377 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
9378 /* Also cover lret/retf/iret in 64-bit mode. */
9379 || (flag_code
== CODE_64BIT
9380 && !i
.tm
.opcode_modifier
.no_lsuf
9381 && !i
.tm
.opcode_modifier
.no_qsuf
))
9382 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
9383 /* Explicit sizing prefixes are assumed to disambiguate insns. */
9384 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
9385 /* Accept FLDENV et al without suffix. */
9386 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
9388 unsigned int suffixes
, evex
= 0;
9390 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
9391 if (!i
.tm
.opcode_modifier
.no_wsuf
)
9393 if (!i
.tm
.opcode_modifier
.no_lsuf
)
9395 if (!i
.tm
.opcode_modifier
.no_ssuf
)
9397 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
9400 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
9401 also suitable for AT&T syntax mode, it was requested that this be
9402 restricted to just Intel syntax. */
9403 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
9404 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
9408 for (op
= 0; op
< i
.tm
.operands
; ++op
)
9410 if (vector_size
< VSZ512
)
9412 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
9413 if (vector_size
< VSZ256
)
9415 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
9416 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
9417 && i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
9418 i
.tm
.opcode_modifier
.evex
= EVEX128
;
9420 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
9421 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
9422 && i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
9423 i
.tm
.opcode_modifier
.evex
= EVEX256
;
9425 else if (i
.tm
.opcode_modifier
.evex
9426 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
9428 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
9429 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
9430 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
9431 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
9432 if (i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
9433 i
.tm
.opcode_modifier
.evex
= EVEX512
;
9436 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
9437 + i
.tm
.operand_types
[op
].bitfield
.ymmword
9438 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
9441 /* Any properly sized operand disambiguates the insn. */
9442 if (i
.types
[op
].bitfield
.xmmword
9443 || i
.types
[op
].bitfield
.ymmword
9444 || i
.types
[op
].bitfield
.zmmword
)
9446 suffixes
&= ~(7 << 6);
9451 if ((i
.flags
[op
] & Operand_Mem
)
9452 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
9454 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
9456 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
9458 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
9460 if (i
.tm
.opcode_modifier
.evex
)
9466 /* Are multiple suffixes / operand sizes allowed? */
9467 if (suffixes
& (suffixes
- 1))
9470 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
9471 || operand_check
== check_error
))
9473 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
9476 if (operand_check
== check_error
)
9478 as_bad (_("no instruction mnemonic suffix given and "
9479 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
9482 if (operand_check
== check_warning
)
9483 as_warn (_("%s; using default for `%s'"),
9485 ? _("ambiguous operand size")
9486 : _("no instruction mnemonic suffix given and "
9487 "no register operands"),
9490 if (i
.tm
.opcode_modifier
.floatmf
)
9491 i
.suffix
= SHORT_MNEM_SUFFIX
;
9493 /* handled below */;
9495 i
.tm
.opcode_modifier
.evex
= evex
;
9496 else if (flag_code
== CODE_16BIT
)
9497 i
.suffix
= WORD_MNEM_SUFFIX
;
9498 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
9499 i
.suffix
= LONG_MNEM_SUFFIX
;
9501 i
.suffix
= QWORD_MNEM_SUFFIX
;
9507 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
9508 In AT&T syntax, if there is no suffix (warned about above), the default
9509 will be byte extension. */
9510 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
9511 i
.tm
.base_opcode
|= 1;
9513 /* For further processing, the suffix should represent the destination
9514 (register). This is already the case when one was used with
9515 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
9516 no suffix to begin with. */
9517 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
9519 if (i
.types
[1].bitfield
.word
)
9520 i
.suffix
= WORD_MNEM_SUFFIX
;
9521 else if (i
.types
[1].bitfield
.qword
)
9522 i
.suffix
= QWORD_MNEM_SUFFIX
;
9524 i
.suffix
= LONG_MNEM_SUFFIX
;
9526 i
.tm
.opcode_modifier
.w
= 0;
9530 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
9531 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
9532 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
9534 /* Change the opcode based on the operand size given by i.suffix. */
9537 /* Size floating point instruction. */
9538 case LONG_MNEM_SUFFIX
:
9539 if (i
.tm
.opcode_modifier
.floatmf
)
9541 i
.tm
.base_opcode
^= 4;
9545 case WORD_MNEM_SUFFIX
:
9546 case QWORD_MNEM_SUFFIX
:
9547 /* It's not a byte, select word/dword operation. */
9548 if (i
.tm
.opcode_modifier
.w
)
9551 i
.tm
.base_opcode
|= 8;
9553 i
.tm
.base_opcode
|= 1;
9556 /* Set mode64 for an operand. */
9557 if (i
.suffix
== QWORD_MNEM_SUFFIX
)
9559 if (flag_code
== CODE_64BIT
9560 && !i
.tm
.opcode_modifier
.norex64
9561 && !i
.tm
.opcode_modifier
.vexw
9562 /* Special case for xchg %rax,%rax. It is NOP and doesn't
9564 && ! (i
.operands
== 2
9565 && i
.tm
.base_opcode
== 0x90
9566 && i
.tm
.opcode_space
== SPACE_BASE
9567 && i
.types
[0].bitfield
.instance
== Accum
9568 && i
.types
[1].bitfield
.instance
== Accum
))
9575 case SHORT_MNEM_SUFFIX
:
9576 /* Now select between word & dword operations via the operand
9577 size prefix, except for instructions that will ignore this
9579 if (i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
9580 && !i
.tm
.opcode_modifier
.floatmf
9581 && (!is_any_vex_encoding (&i
.tm
)
9582 || i
.tm
.opcode_space
== SPACE_EVEXMAP4
)
9583 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
9584 || (flag_code
== CODE_64BIT
9585 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
9587 unsigned int prefix
= DATA_PREFIX_OPCODE
;
9589 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
9590 prefix
= ADDR_PREFIX_OPCODE
;
9592 /* The DATA PREFIX of EVEX promoted from legacy APX instructions
9593 needs to be adjusted. */
9594 if (i
.tm
.opcode_space
== SPACE_EVEXMAP4
)
9596 gas_assert (!i
.tm
.opcode_modifier
.opcodeprefix
);
9597 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
9599 else if (!add_prefix (prefix
))
9606 /* Select word/dword/qword operation with explicit data sizing prefix
9607 when there are no suitable register operands. */
9608 if (i
.tm
.opcode_modifier
.w
9609 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
9611 || (i
.reg_operands
== 1
9613 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
9615 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
9616 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
9617 || i
.tm
.mnem_off
== MN_crc32
))))
9618 i
.tm
.base_opcode
|= 1;
9622 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
9624 gas_assert (!i
.suffix
);
9625 gas_assert (i
.reg_operands
);
9627 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
9630 /* The address size override prefix changes the size of the
9632 if (flag_code
== CODE_64BIT
9633 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
9635 as_bad (_("16-bit addressing unavailable for `%s'"),
9640 if ((flag_code
== CODE_32BIT
9641 ? i
.op
[0].regs
->reg_type
.bitfield
.word
9642 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
9643 && !add_prefix (ADDR_PREFIX_OPCODE
))
9648 /* Check invalid register operand when the address size override
9649 prefix changes the size of register operands. */
9651 enum { need_word
, need_dword
, need_qword
} need
;
9653 /* Check the register operand for the address size prefix if
9654 the memory operand has no real registers, like symbol, DISP
9655 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
9656 if (i
.mem_operands
== 1
9657 && i
.reg_operands
== 1
9659 && i
.types
[1].bitfield
.class == Reg
9660 && (flag_code
== CODE_32BIT
9661 ? i
.op
[1].regs
->reg_type
.bitfield
.word
9662 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
9663 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
9664 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9665 || (x86_elf_abi
== X86_64_X32_ABI
9667 && i
.base_reg
->reg_num
== RegIP
9668 && i
.base_reg
->reg_type
.bitfield
.qword
))
9672 && !add_prefix (ADDR_PREFIX_OPCODE
))
9675 if (flag_code
== CODE_32BIT
)
9676 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
9677 else if (i
.prefix
[ADDR_PREFIX
])
9680 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
9682 for (op
= 0; op
< i
.operands
; op
++)
9684 if (i
.types
[op
].bitfield
.class != Reg
)
9690 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
9694 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
9698 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
9703 as_bad (_("invalid register operand size for `%s'"),
9714 check_byte_reg (void)
9718 for (op
= i
.operands
; --op
>= 0;)
9720 /* Skip non-register operands. */
9721 if (i
.types
[op
].bitfield
.class != Reg
)
9724 /* If this is an eight bit register, it's OK. If it's the 16 or
9725 32 bit version of an eight bit register, we will just use the
9726 low portion, and that's OK too. */
9727 if (i
.types
[op
].bitfield
.byte
)
9730 /* I/O port address operands are OK too. */
9731 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
9732 && i
.tm
.operand_types
[op
].bitfield
.word
)
9735 /* crc32 only wants its source operand checked here. */
9736 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
9739 /* Any other register is bad. */
9740 as_bad (_("`%s%s' not allowed with `%s%c'"),
9741 register_prefix
, i
.op
[op
].regs
->reg_name
,
9742 insn_name (&i
.tm
), i
.suffix
);
9749 check_long_reg (void)
9753 for (op
= i
.operands
; --op
>= 0;)
9754 /* Skip non-register operands. */
9755 if (i
.types
[op
].bitfield
.class != Reg
)
9757 /* Reject eight bit registers, except where the template requires
9758 them. (eg. movzb) */
9759 else if (i
.types
[op
].bitfield
.byte
9760 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
9761 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9762 && (i
.tm
.operand_types
[op
].bitfield
.word
9763 || i
.tm
.operand_types
[op
].bitfield
.dword
))
9765 as_bad (_("`%s%s' not allowed with `%s%c'"),
9767 i
.op
[op
].regs
->reg_name
,
9772 /* Error if the e prefix on a general reg is missing, or if the r
9773 prefix on a general reg is present. */
9774 else if ((i
.types
[op
].bitfield
.word
9775 || i
.types
[op
].bitfield
.qword
)
9776 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
9777 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9778 && i
.tm
.operand_types
[op
].bitfield
.dword
)
9780 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9781 register_prefix
, i
.op
[op
].regs
->reg_name
,
9789 check_qword_reg (void)
9793 for (op
= i
.operands
; --op
>= 0; )
9794 /* Skip non-register operands. */
9795 if (i
.types
[op
].bitfield
.class != Reg
)
9797 /* Reject eight bit registers, except where the template requires
9798 them. (eg. movzb) */
9799 else if (i
.types
[op
].bitfield
.byte
9800 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
9801 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9802 && (i
.tm
.operand_types
[op
].bitfield
.word
9803 || i
.tm
.operand_types
[op
].bitfield
.dword
9804 || i
.tm
.operand_types
[op
].bitfield
.qword
))
9806 as_bad (_("`%s%s' not allowed with `%s%c'"),
9808 i
.op
[op
].regs
->reg_name
,
9813 /* Error if the r prefix on a general reg is missing. */
9814 else if ((i
.types
[op
].bitfield
.word
9815 || i
.types
[op
].bitfield
.dword
)
9816 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
9817 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9818 && i
.tm
.operand_types
[op
].bitfield
.qword
)
9820 /* Prohibit these changes in the 64bit mode, since the
9821 lowering is more complicated. */
9822 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9823 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
9830 check_word_reg (void)
9833 for (op
= i
.operands
; --op
>= 0;)
9834 /* Skip non-register operands. */
9835 if (i
.types
[op
].bitfield
.class != Reg
)
9837 /* Reject eight bit registers, except where the template requires
9838 them. (eg. movzb) */
9839 else if (i
.types
[op
].bitfield
.byte
9840 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
9841 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9842 && (i
.tm
.operand_types
[op
].bitfield
.word
9843 || i
.tm
.operand_types
[op
].bitfield
.dword
))
9845 as_bad (_("`%s%s' not allowed with `%s%c'"),
9847 i
.op
[op
].regs
->reg_name
,
9852 /* Error if the e or r prefix on a general reg is present. */
9853 else if ((i
.types
[op
].bitfield
.dword
9854 || i
.types
[op
].bitfield
.qword
)
9855 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
9856 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
9857 && i
.tm
.operand_types
[op
].bitfield
.word
)
9859 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9860 register_prefix
, i
.op
[op
].regs
->reg_name
,
9868 update_imm (unsigned int j
)
9870 i386_operand_type overlap
= i
.types
[j
];
9872 if (i
.tm
.operand_types
[j
].bitfield
.imm8
9873 && i
.tm
.operand_types
[j
].bitfield
.imm8s
9874 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
9876 /* This combination is used on 8-bit immediates where e.g. $~0 is
9877 desirable to permit. We're past operand type matching, so simply
9878 put things back in the shape they were before introducing the
9879 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
9880 overlap
.bitfield
.imm8s
= 0;
9883 if (overlap
.bitfield
.imm8
9884 + overlap
.bitfield
.imm8s
9885 + overlap
.bitfield
.imm16
9886 + overlap
.bitfield
.imm32
9887 + overlap
.bitfield
.imm32s
9888 + overlap
.bitfield
.imm64
> 1)
9890 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
9891 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
9892 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
9893 static const i386_operand_type imm16_32
= { .bitfield
=
9894 { .imm16
= 1, .imm32
= 1 }
9896 static const i386_operand_type imm16_32s
= { .bitfield
=
9897 { .imm16
= 1, .imm32s
= 1 }
9899 static const i386_operand_type imm16_32_32s
= { .bitfield
=
9900 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
9905 i386_operand_type temp
;
9907 operand_type_set (&temp
, 0);
9908 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
9910 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
9911 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
9913 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
9914 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
9915 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
9917 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
9918 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
9921 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
9924 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
9925 || operand_type_equal (&overlap
, &imm16_32
)
9926 || operand_type_equal (&overlap
, &imm16_32s
))
9928 if ((flag_code
== CODE_16BIT
)
9929 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
9934 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
9935 overlap
= operand_type_and (overlap
, imm32s
);
9936 else if (i
.prefix
[DATA_PREFIX
])
9937 overlap
= operand_type_and (overlap
,
9938 flag_code
!= CODE_16BIT
? imm16
: imm32
);
9939 if (overlap
.bitfield
.imm8
9940 + overlap
.bitfield
.imm8s
9941 + overlap
.bitfield
.imm16
9942 + overlap
.bitfield
.imm32
9943 + overlap
.bitfield
.imm32s
9944 + overlap
.bitfield
.imm64
!= 1)
9946 as_bad (_("no instruction mnemonic suffix given; "
9947 "can't determine immediate size"));
9951 i
.types
[j
] = overlap
;
9961 /* Update the first 2 immediate operands. */
9962 n
= i
.operands
> 2 ? 2 : i
.operands
;
9965 for (j
= 0; j
< n
; j
++)
9966 if (update_imm (j
) == 0)
9969 /* The 3rd operand can't be immediate operand. */
9970 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
9976 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
9979 if (r
->reg_flags
& RegRex
)
9981 if (i
.rex
& rex_bit
)
9982 as_bad (_("same type of prefix used twice"));
9985 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
9987 gas_assert (i
.vex
.register_specifier
== r
);
9988 i
.vex
.register_specifier
+= 8;
9991 if (r
->reg_flags
& RegVRex
)
9994 if (r
->reg_flags
& RegRex2
)
9999 set_rex_rex2 (const reg_entry
*r
, unsigned int rex_bit
)
10001 if ((r
->reg_flags
& RegRex
) != 0)
10003 if ((r
->reg_flags
& RegRex2
) != 0)
10008 process_operands (void)
10010 /* Default segment register this instruction will use for memory
10011 accesses. 0 means unknown. This is only for optimizing out
10012 unnecessary segment overrides. */
10013 const reg_entry
*default_seg
= NULL
;
10015 for (unsigned int j
= 0; j
< i
.operands
; j
++)
10016 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
10018 else if (i
.tm
.opcode_space
== SPACE_EVEXMAP4
10019 && i
.types
[j
].bitfield
.class == RegSIMD
10020 && (i
.op
[j
].regs
->reg_flags
& RegVRex
)
10022 /* Just raise an error, but continue processing. */
10023 as_bad (_("`%s%s' cannot be used with `%s'"),
10024 register_prefix
, i
.op
[j
].regs
->reg_name
, insn_name (&i
.tm
));
10026 if (i
.tm
.opcode_modifier
.sse2avx
)
10028 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
10029 need converting. */
10030 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
10031 i
.prefix
[REX_PREFIX
] = 0;
10032 i
.rex_encoding
= 0;
10033 i
.rex2_encoding
= 0;
10035 /* ImmExt should be processed after SSE2AVX. */
10036 else if (i
.tm
.opcode_modifier
.immext
)
10039 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
10040 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
10041 new destination operand here, while converting the source one to register
10043 if (i
.tm
.mnem_off
== MN_tilezero
)
10045 i
.op
[1].regs
= i
.op
[0].regs
;
10046 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
10047 i
.types
[1] = i
.types
[0];
10048 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
10049 i
.flags
[1] = i
.flags
[0];
10055 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
10057 static const i386_operand_type regxmm
= {
10058 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
10060 unsigned int dupl
= i
.operands
;
10061 unsigned int dest
= dupl
- 1;
10064 /* The destination must be an xmm register. */
10065 gas_assert (i
.reg_operands
10066 && MAX_OPERANDS
> dupl
10067 && operand_type_equal (&i
.types
[dest
], ®xmm
));
10069 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
10070 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
10072 /* Keep xmm0 for instructions with VEX prefix and 3
10074 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
10075 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
10080 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
10082 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
10084 /* Add the implicit xmm0 for instructions with VEX prefix
10086 for (j
= i
.operands
; j
> 0; j
--)
10088 i
.op
[j
] = i
.op
[j
- 1];
10089 i
.types
[j
] = i
.types
[j
- 1];
10090 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
10091 i
.flags
[j
] = i
.flags
[j
- 1];
10094 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
10095 i
.types
[0] = regxmm
;
10096 i
.tm
.operand_types
[0] = regxmm
;
10099 i
.reg_operands
+= 2;
10100 i
.tm
.operands
+= 2;
10104 i
.op
[dupl
] = i
.op
[dest
];
10105 i
.types
[dupl
] = i
.types
[dest
];
10106 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
10107 i
.flags
[dupl
] = i
.flags
[dest
];
10116 i
.op
[dupl
] = i
.op
[dest
];
10117 i
.types
[dupl
] = i
.types
[dest
];
10118 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
10119 i
.flags
[dupl
] = i
.flags
[dest
];
10122 if (i
.tm
.opcode_modifier
.immext
)
10125 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
10126 && i
.tm
.opcode_modifier
.modrm
)
10130 for (j
= 1; j
< i
.operands
; j
++)
10132 i
.op
[j
- 1] = i
.op
[j
];
10133 i
.types
[j
- 1] = i
.types
[j
];
10135 /* We need to adjust fields in i.tm since they are used by
10136 build_modrm_byte. */
10137 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
10139 i
.flags
[j
- 1] = i
.flags
[j
];
10142 /* No adjustment to i.reg_operands: This was already done at the top
10143 of the function. */
10147 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
10149 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
10151 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10152 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
10153 regnum
= register_number (i
.op
[1].regs
);
10154 first_reg_in_group
= regnum
& ~3;
10155 last_reg_in_group
= first_reg_in_group
+ 3;
10156 if (regnum
!= first_reg_in_group
)
10157 as_warn (_("source register `%s%s' implicitly denotes"
10158 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
10159 register_prefix
, i
.op
[1].regs
->reg_name
,
10160 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
10161 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
10162 insn_name (&i
.tm
));
10164 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
10166 /* The imul $imm, %reg instruction is converted into
10167 imul $imm, %reg, %reg, and the clr %reg instruction
10168 is converted into xor %reg, %reg. */
10170 unsigned int first_reg_op
;
10172 if (operand_type_check (i
.types
[0], reg
))
10176 /* Pretend we saw the extra register operand. */
10177 gas_assert (i
.reg_operands
== 1
10178 && i
.op
[first_reg_op
+ 1].regs
== 0);
10179 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
10180 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
10185 if (i
.tm
.opcode_modifier
.modrm
)
10187 /* The opcode is completed (modulo i.tm.extension_opcode which
10188 must be put into the modrm byte). Now, we make the modrm and
10189 index base bytes based on all the info we've collected. */
10191 default_seg
= build_modrm_byte ();
10193 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
10195 /* Warn about some common errors, but press on regardless. */
10196 if (i
.operands
== 2)
10198 /* Reversed arguments on faddp or fmulp. */
10199 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
10200 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
10201 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
10203 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
10205 /* Extraneous `l' suffix on fp insn. */
10206 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
10207 register_prefix
, i
.op
[0].regs
->reg_name
);
10211 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
10213 if (flag_code
!= CODE_64BIT
10214 ? i
.tm
.base_opcode
== POP_SEG_SHORT
10215 && i
.op
[0].regs
->reg_num
== 1
10216 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
10217 && i
.op
[0].regs
->reg_num
< 4)
10219 as_bad (_("you can't `%s %s%s'"),
10220 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
10223 if (i
.op
[0].regs
->reg_num
> 3
10224 && i
.tm
.opcode_space
== SPACE_BASE
)
10226 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
10227 i
.tm
.opcode_space
= SPACE_0F
;
10229 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
10231 else if (i
.tm
.opcode_space
== SPACE_BASE
10232 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
10234 default_seg
= reg_ds
;
10236 else if (i
.tm
.opcode_modifier
.isstring
)
10238 /* For the string instructions that allow a segment override
10239 on one of their operands, the default segment is ds. */
10240 default_seg
= reg_ds
;
10242 else if (i
.short_form
)
10244 /* The register operand is in the 1st or 2nd non-immediate operand. */
10245 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
10248 && r
->reg_type
.bitfield
.instance
== Accum
10249 && i
.op
[i
.imm_operands
+ 1].regs
)
10250 r
= i
.op
[i
.imm_operands
+ 1].regs
;
10251 /* Register goes in low 3 bits of opcode. */
10252 i
.tm
.base_opcode
|= r
->reg_num
;
10253 set_rex_vrex (r
, REX_B
, false);
10255 if (dot_insn () && i
.reg_operands
== 2)
10257 gas_assert (is_any_vex_encoding (&i
.tm
)
10258 || i
.encoding
!= encoding_default
);
10259 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
10262 else if (i
.reg_operands
== 1
10263 && !i
.flags
[i
.operands
- 1]
10264 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
10267 gas_assert (is_any_vex_encoding (&i
.tm
)
10268 || i
.encoding
!= encoding_default
);
10269 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
10272 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
10273 && i
.tm
.mnem_off
== MN_lea
)
10275 if (!quiet_warnings
)
10276 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
10277 if (optimize
&& !i
.no_optimize
)
10280 i
.prefix
[SEG_PREFIX
] = 0;
10284 /* If a segment was explicitly specified, and the specified segment
10285 is neither the default nor the one already recorded from a prefix,
10286 use an opcode prefix to select it. If we never figured out what
10287 the default segment is, then default_seg will be zero at this
10288 point, and the specified segment prefix will always be used. */
10290 && i
.seg
[0] != default_seg
10291 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
10293 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
10299 static const reg_entry
*
10300 build_modrm_byte (void)
10302 const reg_entry
*default_seg
= NULL
;
10303 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
10304 /* Compensate for kludge in md_assemble(). */
10305 + i
.tm
.operand_types
[0].bitfield
.imm1
;
10306 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
10307 unsigned int v
, op
, reg_slot
= ~0;
10309 /* Accumulator (in particular %st), shift count (%cl), and alike need
10310 to be skipped just like immediate operands do. */
10311 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
10313 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
10316 for (op
= source
; op
< i
.operands
; ++op
)
10317 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
10320 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
10324 /* There are 2 kinds of instructions:
10325 1. 5 operands: 4 register operands or 3 register operands
10326 plus 1 memory operand plus one Imm4 operand, VexXDS, and
10327 VexW0 or VexW1. The destination must be either XMM, YMM or
10329 2. 4 operands: 4 register operands or 3 register operands
10330 plus 1 memory operand, with VexXDS.
10331 3. Other equivalent combinations when coming from s_insn(). */
10332 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
10333 && i
.tm
.opcode_modifier
.vexw
);
10334 gas_assert (dot_insn ()
10335 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
10337 /* Of the first two non-immediate operands the one with the template
10338 not allowing for a memory one is encoded in the immediate operand. */
10340 reg_slot
= source
+ 1;
10342 reg_slot
= source
++;
10346 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
10347 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
10350 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
10352 if (i
.imm_operands
== 0)
10354 /* When there is no immediate operand, generate an 8bit
10355 immediate operand to encode the first operand. */
10356 exp
= &im_expressions
[i
.imm_operands
++];
10357 i
.op
[i
.operands
].imms
= exp
;
10358 i
.types
[i
.operands
].bitfield
.imm8
= 1;
10361 exp
->X_op
= O_constant
;
10365 gas_assert (i
.imm_operands
== 1);
10366 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
10367 gas_assert (!i
.tm
.opcode_modifier
.immext
);
10369 /* Turn on Imm8 again so that output_imm will generate it. */
10370 i
.types
[0].bitfield
.imm8
= 1;
10372 exp
= i
.op
[0].imms
;
10374 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
10375 << (3 + !(i
.tm
.opcode_modifier
.evex
10376 || i
.encoding
== encoding_evex
));
10379 if (i
.tm
.opcode_modifier
.vexvvvv
== VexVVVV_DST
)
10386 for (v
= source
+ 1; v
< dest
; ++v
)
10392 if (i
.tm
.extension_opcode
!= None
)
10394 if (dest
!= source
)
10398 gas_assert (source
< dest
);
10399 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
10402 unsigned int tmp
= source
;
10408 if (v
< MAX_OPERANDS
)
10410 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
10411 i
.vex
.register_specifier
= i
.op
[v
].regs
;
10414 if (op
< i
.operands
)
10416 if (i
.mem_operands
)
10418 unsigned int fake_zero_displacement
= 0;
10420 gas_assert (i
.flags
[op
] & Operand_Mem
);
10422 if (i
.tm
.opcode_modifier
.sib
)
10424 /* The index register of VSIB shouldn't be RegIZ. */
10425 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
10426 && i
.index_reg
->reg_num
== RegIZ
)
10429 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
10432 i
.sib
.base
= NO_BASE_REGISTER
;
10433 i
.sib
.scale
= i
.log2_scale_factor
;
10434 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
10435 i
.types
[op
].bitfield
.disp32
= 1;
10438 /* Since the mandatory SIB always has index register, so
10439 the code logic remains unchanged. The non-mandatory SIB
10440 without index register is allowed and will be handled
10444 if (i
.index_reg
->reg_num
== RegIZ
)
10445 i
.sib
.index
= NO_INDEX_REGISTER
;
10447 i
.sib
.index
= i
.index_reg
->reg_num
;
10448 set_rex_vrex (i
.index_reg
, REX_X
, false);
10452 default_seg
= reg_ds
;
10454 if (i
.base_reg
== 0)
10457 if (!i
.disp_operands
)
10458 fake_zero_displacement
= 1;
10459 if (i
.index_reg
== 0)
10461 /* Both check for VSIB and mandatory non-vector SIB. */
10462 gas_assert (!i
.tm
.opcode_modifier
.sib
10463 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
10464 /* Operand is just <disp> */
10465 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
10466 if (flag_code
== CODE_64BIT
)
10468 /* 64bit mode overwrites the 32bit absolute
10469 addressing by RIP relative addressing and
10470 absolute addressing is encoded by one of the
10471 redundant SIB forms. */
10472 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
10473 i
.sib
.base
= NO_BASE_REGISTER
;
10474 i
.sib
.index
= NO_INDEX_REGISTER
;
10475 i
.types
[op
].bitfield
.disp32
= 1;
10477 else if ((flag_code
== CODE_16BIT
)
10478 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
10480 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
10481 i
.types
[op
].bitfield
.disp16
= 1;
10485 i
.rm
.regmem
= NO_BASE_REGISTER
;
10486 i
.types
[op
].bitfield
.disp32
= 1;
10489 else if (!i
.tm
.opcode_modifier
.sib
)
10491 /* !i.base_reg && i.index_reg */
10492 if (i
.index_reg
->reg_num
== RegIZ
)
10493 i
.sib
.index
= NO_INDEX_REGISTER
;
10495 i
.sib
.index
= i
.index_reg
->reg_num
;
10496 i
.sib
.base
= NO_BASE_REGISTER
;
10497 i
.sib
.scale
= i
.log2_scale_factor
;
10498 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
10499 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
10500 i
.types
[op
].bitfield
.disp32
= 1;
10501 set_rex_rex2 (i
.index_reg
, REX_X
);
10504 /* RIP addressing for 64bit mode. */
10505 else if (i
.base_reg
->reg_num
== RegIP
)
10507 gas_assert (!i
.tm
.opcode_modifier
.sib
);
10508 i
.rm
.regmem
= NO_BASE_REGISTER
;
10509 i
.types
[op
].bitfield
.disp8
= 0;
10510 i
.types
[op
].bitfield
.disp16
= 0;
10511 i
.types
[op
].bitfield
.disp32
= 1;
10512 i
.types
[op
].bitfield
.disp64
= 0;
10513 i
.flags
[op
] |= Operand_PCrel
;
10514 if (! i
.disp_operands
)
10515 fake_zero_displacement
= 1;
10517 else if (i
.base_reg
->reg_type
.bitfield
.word
)
10519 gas_assert (!i
.tm
.opcode_modifier
.sib
);
10520 switch (i
.base_reg
->reg_num
)
10522 case 3: /* (%bx) */
10523 if (i
.index_reg
== 0)
10525 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
10526 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
10528 case 5: /* (%bp) */
10529 default_seg
= reg_ss
;
10530 if (i
.index_reg
== 0)
10533 if (operand_type_check (i
.types
[op
], disp
) == 0)
10535 /* fake (%bp) into 0(%bp) */
10536 if (i
.disp_encoding
== disp_encoding_16bit
)
10537 i
.types
[op
].bitfield
.disp16
= 1;
10539 i
.types
[op
].bitfield
.disp8
= 1;
10540 fake_zero_displacement
= 1;
10543 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
10544 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
10546 default: /* (%si) -> 4 or (%di) -> 5 */
10547 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
10549 if (!fake_zero_displacement
10550 && !i
.disp_operands
10551 && i
.disp_encoding
)
10553 fake_zero_displacement
= 1;
10554 if (i
.disp_encoding
== disp_encoding_8bit
)
10555 i
.types
[op
].bitfield
.disp8
= 1;
10557 i
.types
[op
].bitfield
.disp16
= 1;
10559 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
10561 else /* i.base_reg and 32/64 bit mode */
10563 if (operand_type_check (i
.types
[op
], disp
))
10565 i
.types
[op
].bitfield
.disp16
= 0;
10566 i
.types
[op
].bitfield
.disp64
= 0;
10567 i
.types
[op
].bitfield
.disp32
= 1;
10570 if (!i
.tm
.opcode_modifier
.sib
)
10571 i
.rm
.regmem
= i
.base_reg
->reg_num
;
10572 set_rex_rex2 (i
.base_reg
, REX_B
);
10573 i
.sib
.base
= i
.base_reg
->reg_num
;
10574 /* x86-64 ignores REX prefix bit here to avoid decoder
10576 if (!(i
.base_reg
->reg_flags
& RegRex
)
10577 && (i
.base_reg
->reg_num
== EBP_REG_NUM
10578 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
10579 default_seg
= reg_ss
;
10580 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
10582 fake_zero_displacement
= 1;
10583 if (i
.disp_encoding
== disp_encoding_32bit
)
10584 i
.types
[op
].bitfield
.disp32
= 1;
10586 i
.types
[op
].bitfield
.disp8
= 1;
10588 i
.sib
.scale
= i
.log2_scale_factor
;
10589 if (i
.index_reg
== 0)
10591 /* Only check for VSIB. */
10592 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
10593 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
10594 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
10596 /* <disp>(%esp) becomes two byte modrm with no index
10597 register. We've already stored the code for esp
10598 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
10599 Any base register besides %esp will not use the
10600 extra modrm byte. */
10601 i
.sib
.index
= NO_INDEX_REGISTER
;
10603 else if (!i
.tm
.opcode_modifier
.sib
)
10605 if (i
.index_reg
->reg_num
== RegIZ
)
10606 i
.sib
.index
= NO_INDEX_REGISTER
;
10608 i
.sib
.index
= i
.index_reg
->reg_num
;
10609 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
10610 set_rex_rex2 (i
.index_reg
, REX_X
);
10613 if (i
.disp_operands
10614 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
10615 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
10619 if (!fake_zero_displacement
10620 && !i
.disp_operands
10621 && i
.disp_encoding
)
10623 fake_zero_displacement
= 1;
10624 if (i
.disp_encoding
== disp_encoding_8bit
)
10625 i
.types
[op
].bitfield
.disp8
= 1;
10627 i
.types
[op
].bitfield
.disp32
= 1;
10629 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
10633 if (fake_zero_displacement
)
10635 /* Fakes a zero displacement assuming that i.types[op]
10636 holds the correct displacement size. */
10639 gas_assert (i
.op
[op
].disps
== 0);
10640 exp
= &disp_expressions
[i
.disp_operands
++];
10641 i
.op
[op
].disps
= exp
;
10642 exp
->X_op
= O_constant
;
10643 exp
->X_add_number
= 0;
10644 exp
->X_add_symbol
= (symbolS
*) 0;
10645 exp
->X_op_symbol
= (symbolS
*) 0;
10651 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
10652 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
10663 if (!i
.tm
.opcode_modifier
.regmem
)
10665 gas_assert (source
< MAX_OPERANDS
);
10666 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
10667 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
10668 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
10673 gas_assert (dest
< MAX_OPERANDS
);
10674 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
10675 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
10680 /* Fill in i.rm.reg field with extension opcode (if any) or the
10681 appropriate register. */
10682 if (i
.tm
.extension_opcode
!= None
)
10683 i
.rm
.reg
= i
.tm
.extension_opcode
;
10684 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
10686 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
10687 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
10691 gas_assert (source
< MAX_OPERANDS
);
10692 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
10693 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
10696 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
10698 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
10700 add_prefix (LOCK_PREFIX_OPCODE
);
10703 return default_seg
;
10707 frag_opcode_byte (unsigned char byte
)
10709 if (now_seg
!= absolute_section
)
10710 FRAG_APPEND_1_CHAR (byte
);
10712 ++abs_section_offset
;
10715 static unsigned int
10716 flip_code16 (unsigned int code16
)
10718 gas_assert (i
.tm
.operands
== 1);
10720 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
10721 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
10722 : i
.tm
.operand_types
[0].bitfield
.disp16
)
10727 output_branch (void)
10733 relax_substateT subtype
;
10737 if (now_seg
== absolute_section
)
10739 as_bad (_("relaxable branches not supported in absolute section"));
10743 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
10744 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
10747 if (i
.prefix
[DATA_PREFIX
] != 0)
10751 code16
^= flip_code16(code16
);
10753 /* Pentium4 branch hints. */
10754 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
10755 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
10760 if (i
.prefix
[REX_PREFIX
] != 0)
10766 /* BND prefixed jump. */
10767 if (i
.prefix
[BND_PREFIX
] != 0)
10773 if (i
.prefixes
!= 0)
10774 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
10776 /* It's always a symbol; End frag & setup for relax.
10777 Make sure there is enough room in this frag for the largest
10778 instruction we may generate in md_convert_frag. This is 2
10779 bytes for the opcode and room for the prefix and largest
10781 frag_grow (prefix
+ 2 + 4);
10782 /* Prefix and 1 opcode byte go in fr_fix. */
10783 p
= frag_more (prefix
+ 1);
10784 if (i
.prefix
[DATA_PREFIX
] != 0)
10785 *p
++ = DATA_PREFIX_OPCODE
;
10786 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
10787 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
10788 *p
++ = i
.prefix
[SEG_PREFIX
];
10789 if (i
.prefix
[BND_PREFIX
] != 0)
10790 *p
++ = BND_PREFIX_OPCODE
;
10791 if (i
.prefix
[REX_PREFIX
] != 0)
10792 *p
++ = i
.prefix
[REX_PREFIX
];
10793 *p
= i
.tm
.base_opcode
;
10795 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
10796 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
10797 else if (cpu_arch_flags
.bitfield
.cpui386
)
10798 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
10800 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
10803 sym
= i
.op
[0].disps
->X_add_symbol
;
10804 off
= i
.op
[0].disps
->X_add_number
;
10806 if (i
.op
[0].disps
->X_op
!= O_constant
10807 && i
.op
[0].disps
->X_op
!= O_symbol
)
10809 /* Handle complex expressions. */
10810 sym
= make_expr_symbol (i
.op
[0].disps
);
10814 /* 1 possible extra opcode + 4 byte displacement go in var part.
10815 Pass reloc in fr_var. */
10816 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
10819 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10820 /* Return TRUE iff PLT32 relocation should be used for branching to
10824 need_plt32_p (symbolS
*s
)
10826 /* PLT32 relocation is ELF only. */
10831 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
10832 krtld support it. */
10836 /* Since there is no need to prepare for PLT branch on x86-64, we
10837 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
10838 be used as a marker for 32-bit PC-relative branches. */
10845 /* Weak or undefined symbol need PLT32 relocation. */
10846 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
10849 /* Non-global symbol doesn't need PLT32 relocation. */
10850 if (! S_IS_EXTERNAL (s
))
10853 /* Other global symbols need PLT32 relocation. NB: Symbol with
10854 non-default visibilities are treated as normal global symbol
10855 so that PLT32 relocation can be used as a marker for 32-bit
10856 PC-relative branches. It is useful for linker relaxation. */
10867 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
10869 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
10871 /* This is a loop or jecxz type instruction. */
10873 if (i
.prefix
[ADDR_PREFIX
] != 0)
10875 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
10878 /* Pentium4 branch hints. */
10879 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
10880 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
10882 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
10891 if (flag_code
== CODE_16BIT
)
10894 if (i
.prefix
[DATA_PREFIX
] != 0)
10896 frag_opcode_byte (DATA_PREFIX_OPCODE
);
10898 code16
^= flip_code16(code16
);
10906 /* BND prefixed jump. */
10907 if (i
.prefix
[BND_PREFIX
] != 0)
10909 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
10913 if (i
.prefix
[REX_PREFIX
] != 0)
10915 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
10919 if (i
.prefixes
!= 0)
10920 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
10922 if (now_seg
== absolute_section
)
10924 abs_section_offset
+= i
.opcode_length
+ size
;
10928 p
= frag_more (i
.opcode_length
+ size
);
10929 switch (i
.opcode_length
)
10932 *p
++ = i
.tm
.base_opcode
>> 8;
10933 /* Fall through. */
10935 *p
++ = i
.tm
.base_opcode
;
10941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10942 if (flag_code
== CODE_64BIT
&& size
== 4
10943 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
10944 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
10945 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
10948 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
10950 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10951 i
.op
[0].disps
, 1, jump_reloc
);
10953 /* All jumps handled here are signed, but don't unconditionally use a
10954 signed limit check for 32 and 16 bit jumps as we want to allow wrap
10955 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
10960 fixP
->fx_signed
= 1;
10964 if (i
.tm
.mnem_off
== MN_xbegin
)
10965 fixP
->fx_signed
= 1;
10969 if (flag_code
== CODE_64BIT
)
10970 fixP
->fx_signed
= 1;
10976 output_interseg_jump (void)
10984 if (flag_code
== CODE_16BIT
)
10988 if (i
.prefix
[DATA_PREFIX
] != 0)
10995 gas_assert (!i
.prefix
[REX_PREFIX
]);
11001 if (i
.prefixes
!= 0)
11002 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
11004 if (now_seg
== absolute_section
)
11006 abs_section_offset
+= prefix
+ 1 + 2 + size
;
11010 /* 1 opcode; 2 segment; offset */
11011 p
= frag_more (prefix
+ 1 + 2 + size
);
11013 if (i
.prefix
[DATA_PREFIX
] != 0)
11014 *p
++ = DATA_PREFIX_OPCODE
;
11016 if (i
.prefix
[REX_PREFIX
] != 0)
11017 *p
++ = i
.prefix
[REX_PREFIX
];
11019 *p
++ = i
.tm
.base_opcode
;
11020 if (i
.op
[1].imms
->X_op
== O_constant
)
11022 offsetT n
= i
.op
[1].imms
->X_add_number
;
11025 && !fits_in_unsigned_word (n
)
11026 && !fits_in_signed_word (n
))
11028 as_bad (_("16-bit jump out of range"));
11031 md_number_to_chars (p
, n
, size
);
11034 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
11035 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
11038 if (i
.op
[0].imms
->X_op
== O_constant
)
11039 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
11041 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
11042 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
11045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11050 asection
*seg
= now_seg
;
11051 subsegT subseg
= now_subseg
;
11053 unsigned int alignment
, align_size_1
;
11054 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
11055 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
11056 unsigned int padding
;
11058 if (!IS_ELF
|| !x86_used_note
)
11061 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
11063 /* The .note.gnu.property section layout:
11065 Field Length Contents
11068 n_descsz 4 The note descriptor size
11069 n_type 4 NT_GNU_PROPERTY_TYPE_0
11071 n_desc n_descsz The program property array
11075 /* Create the .note.gnu.property section. */
11076 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
11077 bfd_set_section_flags (sec
,
11084 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
11095 bfd_set_section_alignment (sec
, alignment
);
11096 elf_section_type (sec
) = SHT_NOTE
;
11098 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
11100 isa_1_descsz_raw
= 4 + 4 + 4;
11101 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
11102 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
11104 feature_2_descsz_raw
= isa_1_descsz
;
11105 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
11107 feature_2_descsz_raw
+= 4 + 4 + 4;
11108 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
11109 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
11112 descsz
= feature_2_descsz
;
11113 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
11114 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
11116 /* Write n_namsz. */
11117 md_number_to_chars (p
, (valueT
) 4, 4);
11119 /* Write n_descsz. */
11120 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
11122 /* Write n_type. */
11123 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
11125 /* Write n_name. */
11126 memcpy (p
+ 4 * 3, "GNU", 4);
11128 /* Write 4-byte type. */
11129 md_number_to_chars (p
+ 4 * 4,
11130 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
11132 /* Write 4-byte data size. */
11133 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
11135 /* Write 4-byte data. */
11136 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
11138 /* Zero out paddings. */
11139 padding
= isa_1_descsz
- isa_1_descsz_raw
;
11141 memset (p
+ 4 * 7, 0, padding
);
11143 /* Write 4-byte type. */
11144 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
11145 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
11147 /* Write 4-byte data size. */
11148 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
11150 /* Write 4-byte data. */
11151 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
11152 (valueT
) x86_feature_2_used
, 4);
11154 /* Zero out paddings. */
11155 padding
= feature_2_descsz
- feature_2_descsz_raw
;
11157 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
11159 /* We probably can't restore the current segment, for there likely
11160 isn't one yet... */
11162 subseg_set (seg
, subseg
);
11166 x86_support_sframe_p (void)
11168 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
11169 return (x86_elf_abi
== X86_64_ABI
);
11173 x86_sframe_ra_tracking_p (void)
11175 /* In AMD64, return address is always stored on the stack at a fixed offset
11176 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
11177 Do not track explicitly via an SFrame Frame Row Entry. */
11182 x86_sframe_cfa_ra_offset (void)
11184 gas_assert (x86_elf_abi
== X86_64_ABI
);
11185 return (offsetT
) -8;
11189 x86_sframe_get_abi_arch (void)
11191 unsigned char sframe_abi_arch
= 0;
11193 if (x86_support_sframe_p ())
11195 gas_assert (!target_big_endian
);
11196 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
11199 return sframe_abi_arch
;
11204 static unsigned int
11205 encoding_length (const fragS
*start_frag
, offsetT start_off
,
11206 const char *frag_now_ptr
)
11208 unsigned int len
= 0;
11210 if (start_frag
!= frag_now
)
11212 const fragS
*fr
= start_frag
;
11217 } while (fr
&& fr
!= frag_now
);
11220 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
11223 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
11224 be macro-fused with conditional jumps.
11225 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
11226 or is one of the following format:
11236 it is unfusible. */
11239 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
11241 /* No RIP address. */
11242 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11245 /* No opcodes outside of base encoding space. */
11246 if (i
.tm
.opcode_space
!= SPACE_BASE
)
11249 /* add, sub without add/sub m, imm. */
11250 if (i
.tm
.base_opcode
<= 5
11251 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
11252 || ((i
.tm
.base_opcode
| 3) == 0x83
11253 && (i
.tm
.extension_opcode
== 0x5
11254 || i
.tm
.extension_opcode
== 0x0)))
11256 *mf_cmp_p
= mf_cmp_alu_cmp
;
11257 return !(i
.mem_operands
&& i
.imm_operands
);
11260 /* and without and m, imm. */
11261 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
11262 || ((i
.tm
.base_opcode
| 3) == 0x83
11263 && i
.tm
.extension_opcode
== 0x4))
11265 *mf_cmp_p
= mf_cmp_test_and
;
11266 return !(i
.mem_operands
&& i
.imm_operands
);
11269 /* test without test m imm. */
11270 if ((i
.tm
.base_opcode
| 1) == 0x85
11271 || (i
.tm
.base_opcode
| 1) == 0xa9
11272 || ((i
.tm
.base_opcode
| 1) == 0xf7
11273 && i
.tm
.extension_opcode
== 0))
11275 *mf_cmp_p
= mf_cmp_test_and
;
11276 return !(i
.mem_operands
&& i
.imm_operands
);
11279 /* cmp without cmp m, imm. */
11280 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
11281 || ((i
.tm
.base_opcode
| 3) == 0x83
11282 && (i
.tm
.extension_opcode
== 0x7)))
11284 *mf_cmp_p
= mf_cmp_alu_cmp
;
11285 return !(i
.mem_operands
&& i
.imm_operands
);
11288 /* inc, dec without inc/dec m. */
11289 if ((is_cpu (&i
.tm
, CpuNo64
)
11290 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
11291 || ((i
.tm
.base_opcode
| 1) == 0xff
11292 && i
.tm
.extension_opcode
<= 0x1))
11294 *mf_cmp_p
= mf_cmp_incdec
;
11295 return !i
.mem_operands
;
11301 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
11304 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
*mf_cmp_p
,
11305 const struct last_insn
*last_insn
)
11307 /* NB: Don't work with COND_JUMP86 without i386. */
11308 if (!align_branch_power
11309 || now_seg
== absolute_section
11310 || !cpu_arch_flags
.bitfield
.cpui386
11311 || !(align_branch
& align_branch_fused_bit
))
11314 if (maybe_fused_with_jcc_p (mf_cmp_p
))
11316 if (last_insn
->kind
== last_insn_other
)
11319 as_warn_where (last_insn
->file
, last_insn
->line
,
11320 _("`%s` skips -malign-branch-boundary on `%s`"),
11321 last_insn
->name
, insn_name (&i
.tm
));
11327 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
11330 add_branch_prefix_frag_p (const struct last_insn
*last_insn
)
11332 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
11333 to PadLock instructions since they include prefixes in opcode. */
11334 if (!align_branch_power
11335 || !align_branch_prefix_size
11336 || now_seg
== absolute_section
11337 || is_cpu (&i
.tm
, CpuPadLock
)
11338 || !cpu_arch_flags
.bitfield
.cpui386
)
11341 /* Don't add prefix if it is a prefix or there is no operand in case
11342 that segment prefix is special. */
11343 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
11346 if (last_insn
->kind
== last_insn_other
)
11350 as_warn_where (last_insn
->file
, last_insn
->line
,
11351 _("`%s` skips -malign-branch-boundary on `%s`"),
11352 last_insn
->name
, insn_name (&i
.tm
));
11357 /* Return 1 if a BRANCH_PADDING frag should be generated. */
11360 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
11361 enum mf_jcc_kind
*mf_jcc_p
,
11362 const struct last_insn
*last_insn
)
11366 /* NB: Don't work with COND_JUMP86 without i386. */
11367 if (!align_branch_power
11368 || now_seg
== absolute_section
11369 || !cpu_arch_flags
.bitfield
.cpui386
11370 || i
.tm
.opcode_space
!= SPACE_BASE
)
11375 /* Check for jcc and direct jmp. */
11376 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
11378 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
11380 *branch_p
= align_branch_jmp
;
11381 add_padding
= align_branch
& align_branch_jmp_bit
;
11385 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
11386 igore the lowest bit. */
11387 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
11388 *branch_p
= align_branch_jcc
;
11389 if ((align_branch
& align_branch_jcc_bit
))
11393 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
11396 *branch_p
= align_branch_ret
;
11397 if ((align_branch
& align_branch_ret_bit
))
11402 /* Check for indirect jmp, direct and indirect calls. */
11403 if (i
.tm
.base_opcode
== 0xe8)
11406 *branch_p
= align_branch_call
;
11407 if ((align_branch
& align_branch_call_bit
))
11410 else if (i
.tm
.base_opcode
== 0xff
11411 && (i
.tm
.extension_opcode
== 2
11412 || i
.tm
.extension_opcode
== 4))
11414 /* Indirect call and jmp. */
11415 *branch_p
= align_branch_indirect
;
11416 if ((align_branch
& align_branch_indirect_bit
))
11423 && (i
.op
[0].disps
->X_op
== O_symbol
11424 || (i
.op
[0].disps
->X_op
== O_subtract
11425 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
11427 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
11428 /* No padding to call to global or undefined tls_get_addr. */
11429 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
11430 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
11436 && last_insn
->kind
!= last_insn_other
)
11439 as_warn_where (last_insn
->file
, last_insn
->line
,
11440 _("`%s` skips -malign-branch-boundary on `%s`"),
11441 last_insn
->name
, insn_name (&i
.tm
));
11445 return add_padding
;
11449 output_insn (const struct last_insn
*last_insn
)
11451 fragS
*insn_start_frag
;
11452 offsetT insn_start_off
;
11453 fragS
*fragP
= NULL
;
11454 enum align_branch_kind branch
= align_branch_none
;
11455 /* The initializer is arbitrary just to avoid uninitialized error.
11456 it's actually either assigned in add_branch_padding_frag_p
11457 or never be used. */
11458 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
11460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11461 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
11463 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
11464 || is_cpu (&i
.tm
, CpuAMX_TILE
))
11465 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
11467 if (is_cpu (&i
.tm
, Cpu8087
)
11468 || is_cpu (&i
.tm
, Cpu287
)
11469 || is_cpu (&i
.tm
, Cpu387
)
11470 || is_cpu (&i
.tm
, Cpu687
)
11471 || is_cpu (&i
.tm
, CpuFISTTP
))
11472 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
11474 if ((i
.xstate
& xstate_mmx
)
11475 || i
.tm
.mnem_off
== MN_emms
11476 || i
.tm
.mnem_off
== MN_femms
)
11477 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
11481 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
11482 i
.xstate
|= xstate_zmm
;
11483 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
11484 i
.xstate
|= xstate_ymm
;
11485 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
11486 i
.xstate
|= xstate_xmm
;
11489 /* vzeroall / vzeroupper */
11490 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
11491 i
.xstate
|= xstate_ymm
;
11493 if ((i
.xstate
& xstate_xmm
)
11494 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
11495 || (i
.tm
.base_opcode
== 0xae
11496 && (is_cpu (&i
.tm
, CpuSSE
)
11497 || is_cpu (&i
.tm
, CpuAVX
)))
11498 || is_cpu (&i
.tm
, CpuWideKL
)
11499 || is_cpu (&i
.tm
, CpuKL
))
11500 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
11502 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
11503 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
11504 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
11505 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
11506 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
11507 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
11508 if (is_cpu (&i
.tm
, CpuFXSR
))
11509 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
11510 if (is_cpu (&i
.tm
, CpuXsave
))
11511 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
11512 if (is_cpu (&i
.tm
, CpuXsaveopt
))
11513 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
11514 if (is_cpu (&i
.tm
, CpuXSAVEC
))
11515 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
11517 if (x86_feature_2_used
11518 || is_cpu (&i
.tm
, CpuCMOV
)
11519 || is_cpu (&i
.tm
, CpuSYSCALL
)
11520 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
11521 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
11522 if (is_cpu (&i
.tm
, CpuSSE3
)
11523 || is_cpu (&i
.tm
, CpuSSSE3
)
11524 || is_cpu (&i
.tm
, CpuSSE4_1
)
11525 || is_cpu (&i
.tm
, CpuSSE4_2
)
11526 || is_cpu (&i
.tm
, CpuCX16
)
11527 || is_cpu (&i
.tm
, CpuPOPCNT
)
11528 /* LAHF-SAHF insns in 64-bit mode. */
11529 || (flag_code
== CODE_64BIT
11530 && (i
.tm
.base_opcode
| 1) == 0x9f
11531 && i
.tm
.opcode_space
== SPACE_BASE
))
11532 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
11533 if (is_cpu (&i
.tm
, CpuAVX
)
11534 || is_cpu (&i
.tm
, CpuAVX2
)
11535 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
11536 XOP, FMA4, LPW, TBM, and AMX. */
11537 || (i
.tm
.opcode_modifier
.vex
11538 && !is_cpu (&i
.tm
, CpuAVX512F
)
11539 && !is_cpu (&i
.tm
, CpuAVX512BW
)
11540 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
11541 && !is_cpu (&i
.tm
, CpuXOP
)
11542 && !is_cpu (&i
.tm
, CpuFMA4
)
11543 && !is_cpu (&i
.tm
, CpuLWP
)
11544 && !is_cpu (&i
.tm
, CpuTBM
)
11545 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
11546 || is_cpu (&i
.tm
, CpuF16C
)
11547 || is_cpu (&i
.tm
, CpuFMA
)
11548 || is_cpu (&i
.tm
, CpuLZCNT
)
11549 || is_cpu (&i
.tm
, CpuMovbe
)
11550 || is_cpu (&i
.tm
, CpuXSAVES
)
11551 || (x86_feature_2_used
11552 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
11553 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
11554 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
11555 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
11556 if (is_cpu (&i
.tm
, CpuAVX512F
)
11557 || is_cpu (&i
.tm
, CpuAVX512BW
)
11558 || is_cpu (&i
.tm
, CpuAVX512DQ
)
11559 || is_cpu (&i
.tm
, CpuAVX512VL
)
11560 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
11561 AVX512-4FMAPS, and AVX512-4VNNIW. */
11562 || (i
.tm
.opcode_modifier
.evex
11563 && !is_cpu (&i
.tm
, CpuAVX512ER
)
11564 && !is_cpu (&i
.tm
, CpuAVX512PF
)
11565 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
11566 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
11567 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
11571 /* Tie dwarf2 debug info to the address at the start of the insn.
11572 We can't do this after the insn has been output as the current
11573 frag may have been closed off. eg. by frag_var. */
11574 dwarf2_emit_insn (0);
11576 insn_start_frag
= frag_now
;
11577 insn_start_off
= frag_now_fix ();
11579 if (add_branch_padding_frag_p (&branch
, &mf_jcc
, last_insn
))
11582 /* Branch can be 8 bytes. Leave some room for prefixes. */
11583 unsigned int max_branch_padding_size
= 14;
11585 /* Align section to boundary. */
11586 record_alignment (now_seg
, align_branch_power
);
11588 /* Make room for padding. */
11589 frag_grow (max_branch_padding_size
);
11591 /* Start of the padding. */
11596 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
11597 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
11600 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
11601 fragP
->tc_frag_data
.branch_type
= branch
;
11602 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
11605 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
11606 && !pre_386_16bit_warned
)
11608 as_warn (_("use .code16 to ensure correct addressing mode"));
11609 pre_386_16bit_warned
= true;
11612 /* Output jumps. */
11613 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
11615 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
11616 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
11618 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
11619 output_interseg_jump ();
11622 /* Output normal instructions here. */
11626 enum mf_cmp_kind mf_cmp
;
11629 && (i
.tm
.base_opcode
== 0xaee8
11630 || i
.tm
.base_opcode
== 0xaef0
11631 || i
.tm
.base_opcode
== 0xaef8))
11633 /* Encode lfence, mfence, and sfence as
11634 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
11635 if (flag_code
== CODE_16BIT
)
11636 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
11637 else if (omit_lock_prefix
)
11638 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
11639 insn_name (&i
.tm
));
11640 else if (now_seg
!= absolute_section
)
11642 offsetT val
= 0x240483f0ULL
;
11645 md_number_to_chars (p
, val
, 5);
11648 abs_section_offset
+= 5;
11652 /* Some processors fail on LOCK prefix. This options makes
11653 assembler ignore LOCK prefix and serves as a workaround. */
11654 if (omit_lock_prefix
)
11656 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
11657 && i
.tm
.opcode_modifier
.isprefix
)
11659 i
.prefix
[LOCK_PREFIX
] = 0;
11663 /* Skip if this is a branch. */
11665 else if (add_fused_jcc_padding_frag_p (&mf_cmp
, last_insn
))
11667 /* Make room for padding. */
11668 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
11673 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
11674 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
11677 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
11678 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
11679 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
11681 else if (add_branch_prefix_frag_p (last_insn
))
11683 unsigned int max_prefix_size
= align_branch_prefix_size
;
11685 /* Make room for padding. */
11686 frag_grow (max_prefix_size
);
11691 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
11692 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
11695 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
11698 /* Since the VEX/EVEX prefix contains the implicit prefix, we
11699 don't need the explicit prefix. */
11700 if (!is_any_vex_encoding (&i
.tm
))
11702 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
11711 if (!is_cpu (&i
.tm
, CpuPadLock
)
11712 || (i
.prefix
[REP_PREFIX
] != 0xf3))
11716 switch (i
.opcode_length
)
11721 /* Check for pseudo prefixes. */
11722 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
11724 as_bad_where (insn_start_frag
->fr_file
,
11725 insn_start_frag
->fr_line
,
11726 _("pseudo prefix without instruction"));
11736 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11737 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
11738 R_X86_64_GOTTPOFF relocation so that linker can safely
11739 perform IE->LE optimization. A dummy REX_OPCODE prefix
11740 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
11741 relocation for GDesc -> IE/LE optimization. */
11742 if (x86_elf_abi
== X86_64_X32_ABI
11743 && !is_apx_rex2_encoding ()
11745 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
11746 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
11747 && i
.prefix
[REX_PREFIX
] == 0)
11748 add_prefix (REX_OPCODE
);
11751 /* The prefix bytes. */
11752 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
11754 frag_opcode_byte (*q
);
11756 if (is_apx_rex2_encoding ())
11758 frag_opcode_byte (i
.vex
.bytes
[0]);
11759 frag_opcode_byte (i
.vex
.bytes
[1]);
11764 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
11770 frag_opcode_byte (*q
);
11773 /* There should be no other prefixes for instructions
11774 with VEX prefix. */
11778 /* For EVEX instructions i.vrex should become 0 after
11779 build_evex_prefix. For VEX instructions upper 16 registers
11780 aren't available, so VREX should be 0. */
11783 /* Now the VEX prefix. */
11784 if (now_seg
!= absolute_section
)
11786 p
= frag_more (i
.vex
.length
);
11787 for (j
= 0; j
< i
.vex
.length
; j
++)
11788 p
[j
] = i
.vex
.bytes
[j
];
11791 abs_section_offset
+= i
.vex
.length
;
11794 /* Now the opcode; be careful about word order here! */
11795 j
= i
.opcode_length
;
11797 switch (i
.tm
.opcode_space
)
11812 if (now_seg
== absolute_section
)
11813 abs_section_offset
+= j
;
11816 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
11822 && i
.tm
.opcode_space
!= SPACE_BASE
)
11825 if (i
.tm
.opcode_space
!= SPACE_0F
)
11826 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
11830 switch (i
.opcode_length
)
11833 /* Put out high byte first: can't use md_number_to_chars! */
11834 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
11835 /* Fall through. */
11837 *p
= i
.tm
.base_opcode
& 0xff;
11846 /* Now the modrm byte and sib byte (if present). */
11847 if (i
.tm
.opcode_modifier
.modrm
)
11849 frag_opcode_byte ((i
.rm
.regmem
<< 0)
11851 | (i
.rm
.mode
<< 6));
11852 /* If i.rm.regmem == ESP (4)
11853 && i.rm.mode != (Register mode)
11855 ==> need second modrm byte. */
11856 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
11858 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
11859 frag_opcode_byte ((i
.sib
.base
<< 0)
11860 | (i
.sib
.index
<< 3)
11861 | (i
.sib
.scale
<< 6));
11864 if (i
.disp_operands
)
11865 output_disp (insn_start_frag
, insn_start_off
);
11867 if (i
.imm_operands
)
11868 output_imm (insn_start_frag
, insn_start_off
);
11871 * frag_now_fix () returning plain abs_section_offset when we're in the
11872 * absolute section, and abs_section_offset not getting updated as data
11873 * gets added to the frag breaks the logic below.
11875 if (now_seg
!= absolute_section
)
11877 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
11881 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
11884 as_bad (_("instruction length of %u bytes exceeds the limit of 15"),
11889 /* NB: Don't add prefix with GOTPC relocation since
11890 output_disp() above depends on the fixed encoding
11891 length. Can't add prefix with TLS relocation since
11892 it breaks TLS linker optimization. */
11893 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
11894 /* Prefix count on the current instruction. */
11895 unsigned int count
= i
.vex
.length
;
11897 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
11898 /* REX byte is encoded in VEX/EVEX prefix. */
11899 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
11902 /* Count prefixes for extended opcode maps. */
11904 switch (i
.tm
.opcode_space
)
11919 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11922 /* Set the maximum prefix size in BRANCH_PREFIX
11924 if (fragP
->tc_frag_data
.max_bytes
> max
)
11925 fragP
->tc_frag_data
.max_bytes
= max
;
11926 if (fragP
->tc_frag_data
.max_bytes
> count
)
11927 fragP
->tc_frag_data
.max_bytes
-= count
;
11929 fragP
->tc_frag_data
.max_bytes
= 0;
11933 /* Remember the maximum prefix size in FUSED_JCC_PADDING
11935 unsigned int max_prefix_size
;
11936 if (align_branch_prefix_size
> max
)
11937 max_prefix_size
= max
;
11939 max_prefix_size
= align_branch_prefix_size
;
11940 if (max_prefix_size
> count
)
11941 fragP
->tc_frag_data
.max_prefix_length
11942 = max_prefix_size
- count
;
11945 /* Use existing segment prefix if possible. Use CS
11946 segment prefix in 64-bit mode. In 32-bit mode, use SS
11947 segment prefix with ESP/EBP base register and use DS
11948 segment prefix without ESP/EBP base register. */
11949 if (i
.prefix
[SEG_PREFIX
])
11950 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
11951 else if (flag_code
== CODE_64BIT
)
11952 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
11953 else if (i
.base_reg
11954 && (i
.base_reg
->reg_num
== 4
11955 || i
.base_reg
->reg_num
== 5))
11956 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
11958 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
11963 /* NB: Don't work with COND_JUMP86 without i386. */
11964 if (align_branch_power
11965 && now_seg
!= absolute_section
11966 && cpu_arch_flags
.bitfield
.cpui386
)
11968 /* Terminate each frag so that we can add prefix and check for
11970 frag_wane (frag_now
);
11977 pi ("" /*line*/, &i
);
11979 #endif /* DEBUG386 */
11982 /* Return the size of the displacement operand N. */
11985 disp_size (unsigned int n
)
11989 if (i
.types
[n
].bitfield
.disp64
)
11991 else if (i
.types
[n
].bitfield
.disp8
)
11993 else if (i
.types
[n
].bitfield
.disp16
)
11998 /* Return the size of the immediate operand N. */
12001 imm_size (unsigned int n
)
12004 if (i
.types
[n
].bitfield
.imm64
)
12006 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
12008 else if (i
.types
[n
].bitfield
.imm16
)
12014 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
12019 for (n
= 0; n
< i
.operands
; n
++)
12021 if (operand_type_check (i
.types
[n
], disp
))
12023 int size
= disp_size (n
);
12025 if (now_seg
== absolute_section
)
12026 abs_section_offset
+= size
;
12027 else if (i
.op
[n
].disps
->X_op
== O_constant
)
12029 offsetT val
= i
.op
[n
].disps
->X_add_number
;
12031 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
12033 p
= frag_more (size
);
12034 md_number_to_chars (p
, val
, size
);
12038 enum bfd_reloc_code_real reloc_type
;
12039 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
12040 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
12041 && (!want_disp32 (&i
.tm
)
12042 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
12043 && !i
.types
[n
].bitfield
.baseindex
)))
12047 /* We can't have 8 bit displacement here. */
12048 gas_assert (!i
.types
[n
].bitfield
.disp8
);
12050 /* The PC relative address is computed relative
12051 to the instruction boundary, so in case immediate
12052 fields follows, we need to adjust the value. */
12053 if (pcrel
&& i
.imm_operands
)
12058 for (n1
= 0; n1
< i
.operands
; n1
++)
12059 if (operand_type_check (i
.types
[n1
], imm
))
12061 /* Only one immediate is allowed for PC
12062 relative address, except with .insn. */
12063 gas_assert (sz
== 0 || dot_insn ());
12064 sz
+= imm_size (n1
);
12066 /* We should find at least one immediate. */
12067 gas_assert (sz
!= 0);
12068 i
.op
[n
].disps
->X_add_number
-= sz
;
12071 p
= frag_more (size
);
12072 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
12074 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
12075 && (((reloc_type
== BFD_RELOC_32
12076 || reloc_type
== BFD_RELOC_X86_64_32S
12077 || (reloc_type
== BFD_RELOC_64
12079 && (i
.op
[n
].disps
->X_op
== O_symbol
12080 || (i
.op
[n
].disps
->X_op
== O_add
12081 && ((symbol_get_value_expression
12082 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
12084 || reloc_type
== BFD_RELOC_32_PCREL
))
12088 reloc_type
= BFD_RELOC_386_GOTPC
;
12089 i
.has_gotpc_tls_reloc
= true;
12090 i
.op
[n
].disps
->X_add_number
+=
12091 encoding_length (insn_start_frag
, insn_start_off
, p
);
12093 else if (reloc_type
== BFD_RELOC_64
)
12094 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
12096 /* Don't do the adjustment for x86-64, as there
12097 the pcrel addressing is relative to the _next_
12098 insn, and that is taken care of in other code. */
12099 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
12101 else if (align_branch_power
)
12103 switch (reloc_type
)
12105 case BFD_RELOC_386_TLS_GD
:
12106 case BFD_RELOC_386_TLS_LDM
:
12107 case BFD_RELOC_386_TLS_IE
:
12108 case BFD_RELOC_386_TLS_IE_32
:
12109 case BFD_RELOC_386_TLS_GOTIE
:
12110 case BFD_RELOC_386_TLS_GOTDESC
:
12111 case BFD_RELOC_386_TLS_DESC_CALL
:
12112 case BFD_RELOC_X86_64_TLSGD
:
12113 case BFD_RELOC_X86_64_TLSLD
:
12114 case BFD_RELOC_X86_64_GOTTPOFF
:
12115 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF
:
12116 case BFD_RELOC_X86_64_CODE_6_GOTTPOFF
:
12117 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12118 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
:
12119 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12120 i
.has_gotpc_tls_reloc
= true;
12125 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
12126 size
, i
.op
[n
].disps
, pcrel
,
12129 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
12130 && !i
.prefix
[ADDR_PREFIX
])
12131 fixP
->fx_signed
= 1;
12133 if (reloc_type
== BFD_RELOC_X86_64_GOTTPOFF
12134 && i
.tm
.opcode_space
== SPACE_EVEXMAP4
)
12136 /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is
12137 allowed in md_assemble. Set fx_tcbit2 for EVEX
12139 fixP
->fx_tcbit2
= 1;
12143 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12145 if (reloc_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
12147 /* Set fx_tcbit for REX2 prefix. */
12148 if (is_apx_rex2_encoding ())
12149 fixP
->fx_tcbit
= 1;
12153 /* In 64-bit, i386_validate_fix updates only (%rip)
12155 else if (object_64bit
)
12158 /* Check for "call/jmp *mem", "mov mem, %reg",
12159 "test %reg, mem" and "binop mem, %reg" where binop
12160 is one of adc, add, and, cmp, or, sbb, sub, xor
12161 instructions without data prefix. Always generate
12162 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
12163 if (i
.prefix
[DATA_PREFIX
] == 0
12165 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
12166 && i
.tm
.opcode_space
== SPACE_BASE
12167 && ((i
.operands
== 1
12168 && i
.tm
.base_opcode
== 0xff
12169 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
12170 || (i
.operands
== 2
12171 && (i
.tm
.base_opcode
== 0x8b
12172 || i
.tm
.base_opcode
== 0x85
12173 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
12177 if (reloc_type
== BFD_RELOC_X86_64_GOTTPOFF
)
12179 /* Set fx_tcbit for REX2 prefix. */
12180 if (is_apx_rex2_encoding ())
12181 fixP
->fx_tcbit
= 1;
12183 else if (generate_relax_relocations
)
12185 /* Set fx_tcbit3 for REX2 prefix. */
12186 if (is_apx_rex2_encoding ())
12187 fixP
->fx_tcbit3
= 1;
12189 fixP
->fx_tcbit2
= 1;
12191 fixP
->fx_tcbit
= 1;
12194 else if (generate_relax_relocations
12195 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
12196 fixP
->fx_tcbit2
= 1;
12204 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
12209 for (n
= 0; n
< i
.operands
; n
++)
12211 if (operand_type_check (i
.types
[n
], imm
))
12213 int size
= imm_size (n
);
12215 if (now_seg
== absolute_section
)
12216 abs_section_offset
+= size
;
12217 else if (i
.op
[n
].imms
->X_op
== O_constant
)
12221 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
12223 p
= frag_more (size
);
12224 md_number_to_chars (p
, val
, size
);
12228 /* Not absolute_section.
12229 Need a 32-bit fixup (don't support 8bit
12230 non-absolute imms). Try to support other
12232 enum bfd_reloc_code_real reloc_type
;
12235 if (i
.types
[n
].bitfield
.imm32s
12236 && (i
.suffix
== QWORD_MNEM_SUFFIX
12237 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
12238 || (i
.prefix
[REX_PREFIX
] & REX_W
)
12244 p
= frag_more (size
);
12245 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
12247 /* This is tough to explain. We end up with this one if we
12248 * have operands that look like
12249 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
12250 * obtain the absolute address of the GOT, and it is strongly
12251 * preferable from a performance point of view to avoid using
12252 * a runtime relocation for this. The actual sequence of
12253 * instructions often look something like:
12258 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
12260 * The call and pop essentially return the absolute address
12261 * of the label .L66 and store it in %ebx. The linker itself
12262 * will ultimately change the first operand of the addl so
12263 * that %ebx points to the GOT, but to keep things simple, the
12264 * .o file must have this operand set so that it generates not
12265 * the absolute address of .L66, but the absolute address of
12266 * itself. This allows the linker itself simply treat a GOTPC
12267 * relocation as asking for a pcrel offset to the GOT to be
12268 * added in, and the addend of the relocation is stored in the
12269 * operand field for the instruction itself.
12271 * Our job here is to fix the operand so that it would add
12272 * the correct offset so that %ebx would point to itself. The
12273 * thing that is tricky is that .-.L66 will point to the
12274 * beginning of the instruction, so we need to further modify
12275 * the operand so that it will point to itself. There are
12276 * other cases where you have something like:
12278 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
12280 * and here no correction would be required. Internally in
12281 * the assembler we treat operands of this form as not being
12282 * pcrel since the '.' is explicitly mentioned, and I wonder
12283 * whether it would simplify matters to do it this way. Who
12284 * knows. In earlier versions of the PIC patches, the
12285 * pcrel_adjust field was used to store the correction, but
12286 * since the expression is not pcrel, I felt it would be
12287 * confusing to do it this way. */
12289 if ((reloc_type
== BFD_RELOC_32
12290 || reloc_type
== BFD_RELOC_X86_64_32S
12291 || reloc_type
== BFD_RELOC_64
)
12293 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
12294 && (i
.op
[n
].imms
->X_op
== O_symbol
12295 || (i
.op
[n
].imms
->X_op
== O_add
12296 && ((symbol_get_value_expression
12297 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
12301 reloc_type
= BFD_RELOC_386_GOTPC
;
12302 else if (size
== 4)
12303 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
12304 else if (size
== 8)
12305 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
12306 i
.has_gotpc_tls_reloc
= true;
12307 i
.op
[n
].imms
->X_add_number
+=
12308 encoding_length (insn_start_frag
, insn_start_off
, p
);
12310 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
12311 i
.op
[n
].imms
, 0, reloc_type
);
12317 /* x86_cons_fix_new is called via the expression parsing code when a
12318 reloc is needed. We use this hook to get the correct .got reloc. */
12319 static int cons_sign
= -1;
12322 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
12323 expressionS
*exp
, bfd_reloc_code_real_type r
)
12325 r
= reloc (len
, 0, cons_sign
, r
);
12328 if (exp
->X_op
== O_secrel
)
12330 exp
->X_op
= O_symbol
;
12331 r
= BFD_RELOC_32_SECREL
;
12333 else if (exp
->X_op
== O_secidx
)
12334 r
= BFD_RELOC_16_SECIDX
;
12337 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
12340 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
12341 purpose of the `.dc.a' internal pseudo-op. */
12344 x86_address_bytes (void)
12346 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
12348 return stdoutput
->arch_info
->bits_per_address
/ 8;
12351 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
12352 || defined (LEX_AT)) && !defined (TE_PE)
12353 # define lex_got(reloc, adjust, types) NULL
12355 /* Parse operands of the form
12356 <symbol>@GOTOFF+<nnn>
12357 and similar .plt or .got references.
12359 If we find one, set up the correct relocation in RELOC and copy the
12360 input string, minus the `@GOTOFF' into a malloc'd buffer for
12361 parsing by the calling routine. Return this buffer, and if ADJUST
12362 is non-null set it to the length of the string we removed from the
12363 input line. Otherwise return NULL. */
12365 lex_got (enum bfd_reloc_code_real
*rel
,
12367 i386_operand_type
*types
)
12369 /* Some of the relocations depend on the size of what field is to
12370 be relocated. But in our callers i386_immediate and i386_displacement
12371 we don't yet know the operand size (this will be set by insn
12372 matching). Hence we record the word32 relocation here,
12373 and adjust the reloc according to the real size in reloc(). */
12374 static const struct
12378 const enum bfd_reloc_code_real rel
[2];
12379 const i386_operand_type types64
;
12380 bool need_GOT_symbol
;
12385 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
12386 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
12387 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
12388 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
12389 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
12390 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
12391 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
12392 { .imm64 = 1, .disp64 = 1 } }
12395 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12396 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
12397 BFD_RELOC_SIZE32
},
12398 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
12400 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
12401 BFD_RELOC_X86_64_PLTOFF64
},
12402 { .bitfield
= { .imm64
= 1 } }, true },
12403 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
12404 BFD_RELOC_X86_64_PLT32
},
12405 OPERAND_TYPE_IMM32_32S_DISP32
, false },
12406 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
12407 BFD_RELOC_X86_64_GOTPLT64
},
12408 OPERAND_TYPE_IMM64_DISP64
, true },
12409 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
12410 BFD_RELOC_X86_64_GOTOFF64
},
12411 OPERAND_TYPE_IMM64_DISP64
, true },
12412 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
12413 BFD_RELOC_X86_64_GOTPCREL
},
12414 OPERAND_TYPE_IMM32_32S_DISP32
, true },
12415 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
12416 BFD_RELOC_X86_64_TLSGD
},
12417 OPERAND_TYPE_IMM32_32S_DISP32
, true },
12418 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
12419 _dummy_first_bfd_reloc_code_real
},
12420 OPERAND_TYPE_NONE
, true },
12421 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
12422 BFD_RELOC_X86_64_TLSLD
},
12423 OPERAND_TYPE_IMM32_32S_DISP32
, true },
12424 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
12425 BFD_RELOC_X86_64_GOTTPOFF
},
12426 OPERAND_TYPE_IMM32_32S_DISP32
, true },
12427 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
12428 BFD_RELOC_X86_64_TPOFF32
},
12429 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
12430 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
12431 _dummy_first_bfd_reloc_code_real
},
12432 OPERAND_TYPE_NONE
, true },
12433 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
12434 BFD_RELOC_X86_64_DTPOFF32
},
12435 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
12436 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
12437 _dummy_first_bfd_reloc_code_real
},
12438 OPERAND_TYPE_NONE
, true },
12439 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
12440 _dummy_first_bfd_reloc_code_real
},
12441 OPERAND_TYPE_NONE
, true },
12442 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
12443 BFD_RELOC_X86_64_GOT32
},
12444 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
12445 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
12446 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
12447 OPERAND_TYPE_IMM32_32S_DISP32
, true },
12448 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
12449 BFD_RELOC_X86_64_TLSDESC_CALL
},
12450 OPERAND_TYPE_IMM32_32S_DISP32
, true },
12452 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
12453 BFD_RELOC_32_SECREL
},
12454 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
12457 #undef OPERAND_TYPE_IMM32_32S_DISP32
12458 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
12459 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
12460 #undef OPERAND_TYPE_IMM64_DISP64
12466 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
12471 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
12472 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
12475 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
12477 int len
= gotrel
[j
].len
;
12478 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
12480 if (gotrel
[j
].rel
[object_64bit
] != 0)
12483 char *tmpbuf
, *past_reloc
;
12485 *rel
= gotrel
[j
].rel
[object_64bit
];
12489 if (flag_code
!= CODE_64BIT
)
12491 types
->bitfield
.imm32
= 1;
12492 types
->bitfield
.disp32
= 1;
12495 *types
= gotrel
[j
].types64
;
12498 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
12499 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
12501 /* The length of the first part of our input line. */
12502 first
= cp
- input_line_pointer
;
12504 /* The second part goes from after the reloc token until
12505 (and including) an end_of_line char or comma. */
12506 past_reloc
= cp
+ 1 + len
;
12508 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
12510 second
= cp
+ 1 - past_reloc
;
12512 /* Allocate and copy string. The trailing NUL shouldn't
12513 be necessary, but be safe. */
12514 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
12515 memcpy (tmpbuf
, input_line_pointer
, first
);
12516 if (second
!= 0 && *past_reloc
!= ' ')
12517 /* Replace the relocation token with ' ', so that
12518 errors like foo@GOTOFF1 will be detected. */
12519 tmpbuf
[first
++] = ' ';
12521 /* Increment length by 1 if the relocation token is
12526 memcpy (tmpbuf
+ first
, past_reloc
, second
);
12527 tmpbuf
[first
+ second
] = '\0';
12531 as_bad (_("@%s reloc is not supported with %d-bit output format"),
12532 gotrel
[j
].str
, 1 << (5 + object_64bit
));
12537 /* Might be a symbol version string. Don't as_bad here. */
12542 bfd_reloc_code_real_type
12543 x86_cons (expressionS
*exp
, int size
)
12545 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
12547 intel_syntax
= -intel_syntax
;
12549 expr_mode
= expr_operator_none
;
12551 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
12552 && !defined (LEX_AT)) \
12554 if (size
== 4 || (object_64bit
&& size
== 8))
12556 /* Handle @GOTOFF and the like in an expression. */
12558 char *gotfree_input_line
;
12561 save
= input_line_pointer
;
12562 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
12563 if (gotfree_input_line
)
12564 input_line_pointer
= gotfree_input_line
;
12568 if (gotfree_input_line
)
12570 /* expression () has merrily parsed up to the end of line,
12571 or a comma - in the wrong buffer. Transfer how far
12572 input_line_pointer has moved to the right buffer. */
12573 input_line_pointer
= (save
12574 + (input_line_pointer
- gotfree_input_line
)
12576 free (gotfree_input_line
);
12577 if (exp
->X_op
== O_constant
12578 || exp
->X_op
== O_absent
12579 || exp
->X_op
== O_illegal
12580 || exp
->X_op
== O_register
12581 || exp
->X_op
== O_big
)
12583 char c
= *input_line_pointer
;
12584 *input_line_pointer
= 0;
12585 as_bad (_("missing or invalid expression `%s'"), save
);
12586 *input_line_pointer
= c
;
12588 else if ((got_reloc
== BFD_RELOC_386_PLT32
12589 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
12590 && exp
->X_op
!= O_symbol
)
12592 char c
= *input_line_pointer
;
12593 *input_line_pointer
= 0;
12594 as_bad (_("invalid PLT expression `%s'"), save
);
12595 *input_line_pointer
= c
;
12603 intel_syntax
= -intel_syntax
;
12606 i386_intel_simplify (exp
);
12608 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12609 if (size
<= 4 && expr_mode
== expr_operator_present
12610 && exp
->X_op
== O_constant
&& !object_64bit
)
12611 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12617 signed_cons (int size
)
12626 s_insn (int dummy ATTRIBUTE_UNUSED
)
12628 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
12629 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
12633 bool vex
= false, xop
= false, evex
= false;
12634 struct last_insn
*last_insn
;
12638 saved_char
= *saved_ilp
;
12641 end
= parse_insn (line
, mnemonic
, true);
12645 *saved_ilp
= saved_char
;
12646 ignore_rest_of_line ();
12650 line
+= end
- line
;
12652 current_templates
.start
= &i
.tm
;
12653 current_templates
.end
= &i
.tm
+ 1;
12654 i
.tm
.mnem_off
= MN__insn
;
12655 i
.tm
.extension_opcode
= None
;
12657 if (startswith (line
, "VEX")
12658 && (line
[3] == '.' || is_space_char (line
[3])))
12663 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
12666 unsigned long n
= strtoul (line
+ 3, &e
, 16);
12668 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
12669 && (*e
== '.' || is_space_char (*e
)))
12672 /* Arrange for build_vex_prefix() to emit 0x8f. */
12673 i
.tm
.opcode_space
= SPACE_XOP08
;
12674 i
.insn_opcode_space
= n
;
12678 else if (startswith (line
, "EVEX")
12679 && (line
[4] == '.' || is_space_char (line
[4])))
12686 ? i
.encoding
== encoding_evex
12688 ? i
.encoding
== encoding_vex
12689 || i
.encoding
== encoding_vex3
12690 : i
.encoding
!= encoding_default
)
12692 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
12696 if (line
> end
&& i
.encoding
== encoding_default
)
12697 i
.encoding
= evex
? encoding_evex
: encoding_vex
;
12699 if (i
.encoding
!= encoding_default
)
12701 /* Only address size and segment override prefixes are permitted with
12702 VEX/XOP/EVEX encodings. */
12703 const unsigned char *p
= i
.prefix
;
12705 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
12716 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
12722 if (line
> end
&& *line
== '.')
12724 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
12732 i
.tm
.opcode_modifier
.evex
= EVEX128
;
12734 i
.tm
.opcode_modifier
.vex
= VEX128
;
12739 i
.tm
.opcode_modifier
.evex
= EVEX256
;
12741 i
.tm
.opcode_modifier
.vex
= VEX256
;
12746 i
.tm
.opcode_modifier
.evex
= EVEX512
;
12751 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
12755 if (line
[3] == 'G')
12758 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
12760 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
12766 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
12771 if (line
[2] == '2' && line
[3] == '8')
12774 i
.tm
.opcode_modifier
.evex
= EVEX128
;
12776 i
.tm
.opcode_modifier
.vex
= VEX128
;
12782 if (line
[2] == '5' && line
[3] == '6')
12785 i
.tm
.opcode_modifier
.evex
= EVEX256
;
12787 i
.tm
.opcode_modifier
.vex
= VEX256
;
12793 if (evex
&& line
[2] == '1' && line
[3] == '2')
12795 i
.tm
.opcode_modifier
.evex
= EVEX512
;
12802 if (line
> end
&& *line
== '.')
12804 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
12808 if (line
[2] == 'P')
12813 if (line
[2] == '6')
12815 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
12820 case 'F': case 'f':
12821 if (line
[2] == '3')
12823 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
12826 else if (line
[2] == '2')
12828 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
12835 if (line
> end
&& !xop
&& *line
== '.')
12837 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
12841 if (TOUPPER (line
[2]) != 'F')
12843 if (line
[3] == '.' || is_space_char (line
[3]))
12845 i
.insn_opcode_space
= SPACE_0F
;
12848 else if (line
[3] == '3'
12849 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
12850 && (line
[5] == '.' || is_space_char (line
[5])))
12852 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
12858 if (ISDIGIT (line
[2]) && line
[2] != '0')
12861 unsigned long n
= strtoul (line
+ 2, &e
, 10);
12863 if (n
<= (evex
? 15 : 31)
12864 && (*e
== '.' || is_space_char (*e
)))
12866 i
.insn_opcode_space
= n
;
12874 if (line
> end
&& *line
== '.' && line
[1] == 'W')
12876 /* VEX.W, XOP.W, EVEX.W */
12880 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
12884 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
12888 if (line
[3] == 'G')
12890 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
12896 if (i
.tm
.opcode_modifier
.vexw
)
12900 if (line
> end
&& *line
&& !is_space_char (*line
))
12902 /* Improve diagnostic a little. */
12903 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
12908 /* Before processing the opcode expression, find trailing "+r" or
12909 "/<digit>" specifiers. */
12910 for (ptr
= line
; ; ++ptr
)
12915 ptr
= strpbrk (ptr
, "+/,");
12916 if (ptr
== NULL
|| *ptr
== ',')
12919 if (*ptr
== '+' && ptr
[1] == 'r'
12920 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
12924 i
.short_form
= true;
12928 if (*ptr
== '/' && ISDIGIT (ptr
[1])
12929 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
12931 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
12935 i
.tm
.extension_opcode
= n
;
12936 i
.tm
.opcode_modifier
.modrm
= 1;
12941 input_line_pointer
= line
;
12942 val
= get_absolute_expression ();
12943 line
= input_line_pointer
;
12945 if (i
.short_form
&& (val
& 7))
12946 as_warn ("`+r' assumes low three opcode bits to be clear");
12948 for (j
= 1; j
< sizeof(val
); ++j
)
12949 if (!(val
>> (j
* 8)))
12952 /* Trim off a prefix if present. */
12953 if (j
> 1 && !vex
&& !xop
&& !evex
)
12955 uint8_t byte
= val
>> ((j
- 1) * 8);
12959 case DATA_PREFIX_OPCODE
:
12960 case REPE_PREFIX_OPCODE
:
12961 case REPNE_PREFIX_OPCODE
:
12962 if (!add_prefix (byte
))
12964 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
12969 /* Parse operands, if any, before evaluating encoding space. */
12974 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
12982 as_bad (_("expecting operand after ','; got nothing"));
12986 if (i
.mem_operands
> 1)
12988 as_bad (_("too many memory references for `%s'"),
12989 &i386_mnemonics
[MN__insn
]);
12993 /* No need to distinguish encoding_evex and encoding_evex512. */
12994 if (i
.encoding
== encoding_evex512
)
12995 i
.encoding
= encoding_evex
;
12998 /* Trim off encoding space. */
12999 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
13001 uint8_t byte
= val
>> ((--j
- 1) * 8);
13003 i
.insn_opcode_space
= SPACE_0F
;
13004 switch (byte
& -(j
> 1 && !i
.rex2_encoding
13005 && (i
.encoding
!= encoding_egpr
|| evex
)))
13008 i
.insn_opcode_space
= SPACE_0F38
;
13012 i
.insn_opcode_space
= SPACE_0F3A
;
13016 i
.tm
.opcode_space
= i
.insn_opcode_space
;
13017 val
&= ((uint64_t)1 << (j
* 8)) - 1;
13019 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
13020 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
13021 Also avoid hitting abort() there or in build_evex_prefix(). */
13022 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
13027 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
13030 i
.opcode_length
= j
;
13032 /* Handle operands, if any. */
13035 i386_operand_type combined
;
13036 expressionS
*disp_exp
= NULL
;
13039 if (i
.encoding
== encoding_egpr
)
13043 as_bad (_("eGPR use conflicts with encoding specifier"));
13047 i
.encoding
= encoding_evex
;
13049 i
.encoding
= encoding_default
;
13052 /* Are we to emit ModR/M encoding? */
13055 || i
.reg_operands
> (i
.encoding
!= encoding_default
)
13056 || i
.tm
.extension_opcode
!= None
))
13057 i
.tm
.opcode_modifier
.modrm
= 1;
13059 if (!i
.tm
.opcode_modifier
.modrm
13061 > i
.short_form
+ 0U + (i
.encoding
!= encoding_default
)
13062 || i
.mem_operands
))
13064 as_bad (_("too many register/memory operands"));
13068 /* Enforce certain constraints on operands. */
13069 switch (i
.reg_operands
+ i
.mem_operands
13070 + (i
.tm
.extension_opcode
!= None
))
13075 as_bad (_("too few register/memory operands"));
13078 /* Fall through. */
13080 if (i
.tm
.opcode_modifier
.modrm
)
13082 as_bad (_("too few register/memory operands"));
13092 && (i
.op
[0].imms
->X_op
!= O_constant
13093 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
13095 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
13098 /* Fall through. */
13100 if (i
.encoding
!= encoding_default
)
13102 i
.tm
.opcode_modifier
.vexvvvv
= 1;
13105 /* Fall through. */
13107 as_bad (_("too many register/memory operands"));
13111 /* Bring operands into canonical order (imm, mem, reg). */
13116 for (j
= 1; j
< i
.operands
; ++j
)
13118 if ((!operand_type_check (i
.types
[j
- 1], imm
)
13119 && operand_type_check (i
.types
[j
], imm
))
13120 || (i
.types
[j
- 1].bitfield
.class != ClassNone
13121 && i
.types
[j
].bitfield
.class == ClassNone
))
13123 swap_2_operands (j
- 1, j
);
13130 /* For Intel syntax swap the order of register operands. */
13132 switch (i
.reg_operands
)
13139 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
13140 /* Fall through. */
13143 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
13150 /* Enforce constraints when using VSIB. */
13152 && (i
.index_reg
->reg_type
.bitfield
.xmmword
13153 || i
.index_reg
->reg_type
.bitfield
.ymmword
13154 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
13156 if (i
.encoding
== encoding_default
)
13158 as_bad (_("VSIB unavailable with legacy encoding"));
13162 if (i
.encoding
== encoding_evex
13163 && i
.reg_operands
> 1)
13165 /* We could allow two register operands, encoding the 2nd one in
13166 an 8-bit immediate like for 4-register-operand insns, but that
13167 would require ugly fiddling with process_operands() and/or
13168 build_modrm_byte(). */
13169 as_bad (_("too many register operands with VSIB"));
13173 i
.tm
.opcode_modifier
.sib
= 1;
13176 /* Establish operand size encoding. */
13177 operand_type_set (&combined
, 0);
13179 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
13181 /* Look for 8-bit operands that use old registers. */
13182 if (i
.encoding
!= encoding_default
13183 && flag_code
== CODE_64BIT
13184 && i
.types
[j
].bitfield
.class == Reg
13185 && i
.types
[j
].bitfield
.byte
13186 && !(i
.op
[j
].regs
->reg_flags
& RegRex64
)
13187 && i
.op
[j
].regs
->reg_num
> 3)
13188 as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"),
13189 register_prefix
, i
.op
[j
].regs
->reg_name
);
13191 i
.types
[j
].bitfield
.instance
= InstanceNone
;
13193 if (operand_type_check (i
.types
[j
], disp
))
13195 i
.types
[j
].bitfield
.baseindex
= 1;
13196 disp_exp
= i
.op
[j
].disps
;
13199 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
13201 unsigned int n
= i
.memshift
;
13203 if (i
.types
[j
].bitfield
.byte
)
13205 else if (i
.types
[j
].bitfield
.word
)
13207 else if (i
.types
[j
].bitfield
.dword
)
13209 else if (i
.types
[j
].bitfield
.qword
)
13211 else if (i
.types
[j
].bitfield
.xmmword
)
13213 else if (i
.types
[j
].bitfield
.ymmword
)
13215 else if (i
.types
[j
].bitfield
.zmmword
)
13218 if (i
.memshift
< 32 && n
!= i
.memshift
)
13219 as_warn ("conflicting memory operand size specifiers");
13223 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
13224 && j
== i
.broadcast
.operand
)
13227 combined
= operand_type_or (combined
, i
.types
[j
]);
13228 combined
.bitfield
.class = ClassNone
;
13231 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
13232 << (i
.memshift
< 32 ? i
.memshift
: 0))
13234 case 64: combined
.bitfield
.zmmword
= 1; break;
13235 case 32: combined
.bitfield
.ymmword
= 1; break;
13236 case 16: combined
.bitfield
.xmmword
= 1; break;
13237 case 8: combined
.bitfield
.qword
= 1; break;
13238 case 4: combined
.bitfield
.dword
= 1; break;
13241 if (i
.encoding
== encoding_default
)
13243 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
13245 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
13246 : combined
.bitfield
.word
)
13247 && !add_prefix (DATA_PREFIX_OPCODE
))
13250 else if (!i
.tm
.opcode_modifier
.vexw
)
13252 if (flag_code
== CODE_64BIT
)
13254 if (combined
.bitfield
.qword
)
13255 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
13256 else if (combined
.bitfield
.dword
)
13257 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
13260 if (!i
.tm
.opcode_modifier
.vexw
)
13261 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
13266 if (!i
.tm
.opcode_modifier
.vex
)
13268 if (combined
.bitfield
.ymmword
)
13269 i
.tm
.opcode_modifier
.vex
= VEX256
;
13270 else if (combined
.bitfield
.xmmword
)
13271 i
.tm
.opcode_modifier
.vex
= VEX128
;
13276 if (!i
.tm
.opcode_modifier
.evex
)
13278 /* Do _not_ consider AVX512VL here. */
13279 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
13280 i
.tm
.opcode_modifier
.evex
= EVEX512
;
13281 else if (combined
.bitfield
.ymmword
)
13282 i
.tm
.opcode_modifier
.evex
= EVEX256
;
13283 else if (combined
.bitfield
.xmmword
)
13284 i
.tm
.opcode_modifier
.evex
= EVEX128
;
13287 if (i
.memshift
>= 32)
13289 unsigned int n
= 0;
13291 switch (i
.tm
.opcode_modifier
.evex
)
13293 case EVEX512
: n
= 64; break;
13294 case EVEX256
: n
= 32; break;
13295 case EVEX128
: n
= 16; break;
13298 if (i
.broadcast
.type
)
13299 n
/= i
.broadcast
.type
;
13302 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
13304 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
13305 && disp_exp
->X_add_number
!= 0
13306 && i
.disp_encoding
!= disp_encoding_32bit
)
13308 if (!quiet_warnings
)
13309 as_warn ("cannot determine memory operand size");
13310 i
.disp_encoding
= disp_encoding_32bit
;
13315 if (i
.memshift
>= 32)
13318 i
.encoding
= encoding_error
;
13320 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
13323 /* Establish size for immediate operands. */
13324 for (j
= 0; j
< i
.imm_operands
; ++j
)
13326 expressionS
*expP
= i
.op
[j
].imms
;
13328 gas_assert (operand_type_check (i
.types
[j
], imm
));
13329 operand_type_set (&i
.types
[j
], 0);
13331 if (i
.imm_bits
[j
] > 32)
13332 i
.types
[j
].bitfield
.imm64
= 1;
13333 else if (i
.imm_bits
[j
] > 16)
13335 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
13336 i
.types
[j
].bitfield
.imm32s
= 1;
13338 i
.types
[j
].bitfield
.imm32
= 1;
13340 else if (i
.imm_bits
[j
] > 8)
13341 i
.types
[j
].bitfield
.imm16
= 1;
13342 else if (i
.imm_bits
[j
] > 0)
13344 if (i
.flags
[j
] & Operand_Signed
)
13345 i
.types
[j
].bitfield
.imm8s
= 1;
13347 i
.types
[j
].bitfield
.imm8
= 1;
13349 else if (expP
->X_op
== O_constant
)
13351 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
13352 i
.types
[j
].bitfield
.imm1
= 0;
13353 /* Oddly enough imm_size() checks imm64 first, so the bit needs
13354 zapping since smallest_imm_type() sets it unconditionally. */
13355 if (flag_code
!= CODE_64BIT
)
13357 i
.types
[j
].bitfield
.imm64
= 0;
13358 i
.types
[j
].bitfield
.imm32s
= 0;
13359 i
.types
[j
].bitfield
.imm32
= 1;
13361 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
13362 i
.types
[j
].bitfield
.imm64
= 0;
13365 /* Non-constant expressions are sized heuristically. */
13368 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
13369 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
13370 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
13374 for (j
= 0; j
< i
.operands
; ++j
)
13375 i
.tm
.operand_types
[j
] = i
.types
[j
];
13377 process_operands ();
13380 /* Don't set opcode until after processing operands, to avoid any
13381 potential special casing there. */
13382 i
.tm
.base_opcode
|= val
;
13384 if (i
.encoding
== encoding_error
13385 || (i
.encoding
!= encoding_evex
13386 ? i
.broadcast
.type
|| i
.broadcast
.bytes
13387 || i
.rounding
.type
!= rc_none
13389 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
13390 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
13391 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
13393 as_bad (_("conflicting .insn operands"));
13399 if (!i
.tm
.opcode_modifier
.vex
)
13400 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
13402 build_vex_prefix (NULL
);
13403 i
.rex
&= REX_OPCODE
;
13407 if (!i
.tm
.opcode_modifier
.evex
)
13408 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
13410 build_evex_prefix ();
13411 i
.rex
&= REX_OPCODE
;
13416 last_insn
= &seg_info(now_seg
)->tc_segment_info_data
.last_insn
;
13417 output_insn (last_insn
);
13418 last_insn
->kind
= last_insn_directive
;
13419 last_insn
->name
= ".insn directive";
13420 last_insn
->file
= as_where (&last_insn
->line
);
13422 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13423 /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been
13424 performed in i386_target_format. */
13425 if (IS_ELF
&& flag_synth_cfi
)
13426 as_bad (_("SCFI: hand-crafting instructions not supported"));
13430 *saved_ilp
= saved_char
;
13431 input_line_pointer
= line
;
13433 demand_empty_rest_of_line ();
13435 /* Make sure dot_insn() won't yield "true" anymore. */
13441 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
13448 if (exp
.X_op
== O_symbol
)
13449 exp
.X_op
= O_secrel
;
13451 emit_expr (&exp
, 4);
13453 while (*input_line_pointer
++ == ',');
13455 input_line_pointer
--;
13456 demand_empty_rest_of_line ();
13460 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
13467 if (exp
.X_op
== O_symbol
)
13468 exp
.X_op
= O_secidx
;
13470 emit_expr (&exp
, 2);
13472 while (*input_line_pointer
++ == ',');
13474 input_line_pointer
--;
13475 demand_empty_rest_of_line ();
13479 /* Handle Rounding Control / SAE specifiers. */
13482 RC_SAE_specifier (const char *pstr
)
13486 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
13488 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
13490 if (i
.rounding
.type
!= rc_none
)
13492 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
13496 switch (i
.encoding
)
13498 case encoding_default
:
13499 case encoding_egpr
:
13500 i
.encoding
= encoding_evex512
;
13502 case encoding_evex
:
13503 case encoding_evex512
:
13509 i
.rounding
.type
= RC_NamesTable
[j
].type
;
13511 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
13518 /* Handle Vector operations. */
13521 check_VecOperations (char *op_string
)
13523 const reg_entry
*mask
;
13530 if (*op_string
== '{')
13534 /* Check broadcasts. */
13535 if (startswith (op_string
, "1to"))
13537 unsigned int bcst_type
;
13539 if (i
.broadcast
.type
)
13540 goto duplicated_vec_op
;
13543 if (*op_string
== '8')
13545 else if (*op_string
== '4')
13547 else if (*op_string
== '2')
13549 else if (*op_string
== '1'
13550 && *(op_string
+1) == '6')
13555 else if (*op_string
== '3'
13556 && *(op_string
+1) == '2')
13563 as_bad (_("Unsupported broadcast: `%s'"), saved
);
13568 switch (i
.encoding
)
13570 case encoding_default
:
13571 case encoding_egpr
:
13572 i
.encoding
= encoding_evex
;
13574 case encoding_evex
:
13575 case encoding_evex512
:
13578 goto unknown_vec_op
;
13581 i
.broadcast
.type
= bcst_type
;
13582 i
.broadcast
.operand
= this_operand
;
13584 /* For .insn a data size specifier may be appended. */
13585 if (dot_insn () && *op_string
== ':')
13586 goto dot_insn_modifier
;
13588 /* Check .insn special cases. */
13589 else if (dot_insn () && *op_string
== ':')
13592 switch (op_string
[1])
13597 if (i
.memshift
< 32)
13598 goto duplicated_vec_op
;
13600 n
= strtoul (op_string
+ 2, &end_op
, 0);
13602 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
13604 if (i
.memshift
< 32 && n
== 1)
13605 op_string
= end_op
;
13608 case 's': case 'u':
13609 /* This isn't really a "vector" operation, but a sign/size
13610 specifier for immediate operands of .insn. Note that AT&T
13611 syntax handles the same in i386_immediate(). */
13615 if (i
.imm_bits
[this_operand
])
13616 goto duplicated_vec_op
;
13618 n
= strtoul (op_string
+ 2, &end_op
, 0);
13619 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
13621 i
.imm_bits
[this_operand
] = n
;
13622 if (op_string
[1] == 's')
13623 i
.flags
[this_operand
] |= Operand_Signed
;
13624 op_string
= end_op
;
13629 /* Check masking operation. */
13630 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
13632 if (mask
== &bad_reg
)
13635 /* k0 can't be used for write mask. */
13636 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
13638 as_bad (_("`%s%s' can't be used for write mask"),
13639 register_prefix
, mask
->reg_name
);
13646 i
.mask
.operand
= this_operand
;
13648 else if (i
.mask
.reg
->reg_num
)
13649 goto duplicated_vec_op
;
13654 /* Only "{z}" is allowed here. No need to check
13655 zeroing mask explicitly. */
13656 if (i
.mask
.operand
!= (unsigned int) this_operand
)
13658 as_bad (_("invalid write mask `%s'"), saved
);
13663 op_string
= end_op
;
13665 /* Check zeroing-flag for masking operation. */
13666 else if (*op_string
== 'z')
13670 i
.mask
.reg
= reg_k0
;
13671 i
.mask
.zeroing
= 1;
13672 i
.mask
.operand
= this_operand
;
13676 if (i
.mask
.zeroing
)
13679 as_bad (_("duplicated `%s'"), saved
);
13683 i
.mask
.zeroing
= 1;
13685 /* Only "{%k}" is allowed here. No need to check mask
13686 register explicitly. */
13687 if (i
.mask
.operand
!= (unsigned int) this_operand
)
13689 as_bad (_("invalid zeroing-masking `%s'"),
13697 else if (intel_syntax
13698 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
13699 i
.rounding
.modifier
= true;
13701 goto unknown_vec_op
;
13703 if (*op_string
!= '}')
13705 as_bad (_("missing `}' in `%s'"), saved
);
13710 /* Strip whitespace since the addition of pseudo prefixes
13711 changed how the scrubber treats '{'. */
13712 if (is_space_char (*op_string
))
13718 /* We don't know this one. */
13719 as_bad (_("unknown vector operation: `%s'"), saved
);
13723 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
13725 as_bad (_("zeroing-masking only allowed with write mask"));
13733 i386_immediate (char *imm_start
)
13735 char *save_input_line_pointer
;
13736 char *gotfree_input_line
;
13739 i386_operand_type types
;
13741 operand_type_set (&types
, ~0);
13743 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
13745 as_bad (_("at most %d immediate operands are allowed"),
13746 MAX_IMMEDIATE_OPERANDS
);
13750 exp
= &im_expressions
[i
.imm_operands
++];
13751 i
.op
[this_operand
].imms
= exp
;
13753 if (is_space_char (*imm_start
))
13756 save_input_line_pointer
= input_line_pointer
;
13757 input_line_pointer
= imm_start
;
13759 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
13760 if (gotfree_input_line
)
13761 input_line_pointer
= gotfree_input_line
;
13763 expr_mode
= expr_operator_none
;
13764 exp_seg
= expression (exp
);
13766 /* For .insn immediates there may be a size specifier. */
13767 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
13768 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
13771 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
13773 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
13775 i
.imm_bits
[this_operand
] = n
;
13776 if (input_line_pointer
[2] == 's')
13777 i
.flags
[this_operand
] |= Operand_Signed
;
13778 input_line_pointer
= e
+ 1;
13782 SKIP_WHITESPACE ();
13783 if (*input_line_pointer
)
13784 as_bad (_("junk `%s' after expression"), input_line_pointer
);
13786 input_line_pointer
= save_input_line_pointer
;
13787 if (gotfree_input_line
)
13789 free (gotfree_input_line
);
13791 if (exp
->X_op
== O_constant
)
13792 exp
->X_op
= O_illegal
;
13795 if (exp_seg
== reg_section
)
13797 as_bad (_("illegal immediate register operand %s"), imm_start
);
13801 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
13805 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
13806 i386_operand_type types
, const char *imm_start
)
13808 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
13811 as_bad (_("missing or invalid immediate expression `%s'"),
13815 else if (exp
->X_op
== O_constant
)
13817 /* Size it properly later. */
13818 i
.types
[this_operand
].bitfield
.imm64
= 1;
13820 /* If not 64bit, sign/zero extend val, to account for wraparound
13822 if (expr_mode
== expr_operator_present
13823 && flag_code
!= CODE_64BIT
&& !object_64bit
)
13824 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
13826 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13827 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
13828 && exp_seg
!= absolute_section
13829 && exp_seg
!= text_section
13830 && exp_seg
!= data_section
13831 && exp_seg
!= bss_section
13832 && exp_seg
!= undefined_section
13833 && !bfd_is_com_section (exp_seg
))
13835 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
13841 /* This is an address. The size of the address will be
13842 determined later, depending on destination register,
13843 suffix, or the default for the section. */
13844 i
.types
[this_operand
].bitfield
.imm8
= 1;
13845 i
.types
[this_operand
].bitfield
.imm16
= 1;
13846 i
.types
[this_operand
].bitfield
.imm32
= 1;
13847 i
.types
[this_operand
].bitfield
.imm32s
= 1;
13848 i
.types
[this_operand
].bitfield
.imm64
= 1;
13849 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
13857 i386_scale (char *scale
)
13860 char *save
= input_line_pointer
;
13862 input_line_pointer
= scale
;
13863 val
= get_absolute_expression ();
13868 i
.log2_scale_factor
= 0;
13871 i
.log2_scale_factor
= 1;
13874 i
.log2_scale_factor
= 2;
13877 i
.log2_scale_factor
= 3;
13881 char sep
= *input_line_pointer
;
13883 *input_line_pointer
= '\0';
13884 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
13886 *input_line_pointer
= sep
;
13887 input_line_pointer
= save
;
13891 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
13893 as_warn (_("scale factor of %d without an index register"),
13894 1 << i
.log2_scale_factor
);
13895 i
.log2_scale_factor
= 0;
13897 scale
= input_line_pointer
;
13898 input_line_pointer
= save
;
13903 i386_displacement (char *disp_start
, char *disp_end
)
13907 char *save_input_line_pointer
;
13908 char *gotfree_input_line
;
13910 i386_operand_type bigdisp
, types
= anydisp
;
13913 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
13915 as_bad (_("at most %d displacement operands are allowed"),
13916 MAX_MEMORY_OPERANDS
);
13920 operand_type_set (&bigdisp
, 0);
13922 || i
.types
[this_operand
].bitfield
.baseindex
13923 || (current_templates
.start
->opcode_modifier
.jump
!= JUMP
13924 && current_templates
.start
->opcode_modifier
.jump
!= JUMP_DWORD
))
13926 i386_addressing_mode ();
13927 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
13928 if (flag_code
== CODE_64BIT
)
13930 bigdisp
.bitfield
.disp32
= 1;
13932 bigdisp
.bitfield
.disp64
= 1;
13934 else if ((flag_code
== CODE_16BIT
) ^ override
)
13935 bigdisp
.bitfield
.disp16
= 1;
13937 bigdisp
.bitfield
.disp32
= 1;
13941 /* For PC-relative branches, the width of the displacement may be
13942 dependent upon data size, but is never dependent upon address size.
13943 Also make sure to not unintentionally match against a non-PC-relative
13944 branch template. */
13945 const insn_template
*t
= current_templates
.start
;
13946 bool has_intel64
= false;
13948 while (++t
< current_templates
.end
)
13950 if (t
->opcode_modifier
.jump
13951 != current_templates
.start
->opcode_modifier
.jump
)
13953 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
13954 has_intel64
= true;
13956 current_templates
.end
= t
;
13958 override
= (i
.prefix
[DATA_PREFIX
] != 0);
13959 if (flag_code
== CODE_64BIT
)
13961 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
13962 && (!intel64
|| !has_intel64
))
13963 bigdisp
.bitfield
.disp16
= 1;
13965 bigdisp
.bitfield
.disp32
= 1;
13970 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
13972 : LONG_MNEM_SUFFIX
));
13973 bigdisp
.bitfield
.disp32
= 1;
13974 if ((flag_code
== CODE_16BIT
) ^ override
)
13976 bigdisp
.bitfield
.disp32
= 0;
13977 bigdisp
.bitfield
.disp16
= 1;
13981 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
13984 exp
= &disp_expressions
[i
.disp_operands
];
13985 i
.op
[this_operand
].disps
= exp
;
13987 save_input_line_pointer
= input_line_pointer
;
13988 input_line_pointer
= disp_start
;
13989 END_STRING_AND_SAVE (disp_end
);
13991 #ifndef GCC_ASM_O_HACK
13992 #define GCC_ASM_O_HACK 0
13995 END_STRING_AND_SAVE (disp_end
+ 1);
13996 if (i
.types
[this_operand
].bitfield
.baseIndex
13997 && displacement_string_end
[-1] == '+')
13999 /* This hack is to avoid a warning when using the "o"
14000 constraint within gcc asm statements.
14003 #define _set_tssldt_desc(n,addr,limit,type) \
14004 __asm__ __volatile__ ( \
14005 "movw %w2,%0\n\t" \
14006 "movw %w1,2+%0\n\t" \
14007 "rorl $16,%1\n\t" \
14008 "movb %b1,4+%0\n\t" \
14009 "movb %4,5+%0\n\t" \
14010 "movb $0,6+%0\n\t" \
14011 "movb %h1,7+%0\n\t" \
14013 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
14015 This works great except that the output assembler ends
14016 up looking a bit weird if it turns out that there is
14017 no offset. You end up producing code that looks like:
14030 So here we provide the missing zero. */
14032 *displacement_string_end
= '0';
14035 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
14036 if (gotfree_input_line
)
14037 input_line_pointer
= gotfree_input_line
;
14039 expr_mode
= expr_operator_none
;
14040 exp_seg
= expression (exp
);
14042 SKIP_WHITESPACE ();
14043 if (*input_line_pointer
)
14044 as_bad (_("junk `%s' after expression"), input_line_pointer
);
14046 RESTORE_END_STRING (disp_end
+ 1);
14048 input_line_pointer
= save_input_line_pointer
;
14049 if (gotfree_input_line
)
14051 free (gotfree_input_line
);
14053 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
14054 exp
->X_op
= O_illegal
;
14057 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
14059 RESTORE_END_STRING (disp_end
);
14065 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
14066 i386_operand_type types
, const char *disp_start
)
14070 /* We do this to make sure that the section symbol is in
14071 the symbol table. We will ultimately change the relocation
14072 to be relative to the beginning of the section. */
14073 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
14074 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
14075 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
14077 if (exp
->X_op
!= O_symbol
)
14080 if (S_IS_LOCAL (exp
->X_add_symbol
)
14081 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
14082 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
14083 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
14084 exp
->X_op
= O_subtract
;
14085 exp
->X_op_symbol
= GOT_symbol
;
14086 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
14087 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
14088 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
14089 i
.reloc
[this_operand
] = BFD_RELOC_64
;
14091 i
.reloc
[this_operand
] = BFD_RELOC_32
;
14094 else if (exp
->X_op
== O_absent
14095 || exp
->X_op
== O_illegal
14096 || exp
->X_op
== O_big
)
14099 as_bad (_("missing or invalid displacement expression `%s'"),
14104 else if (exp
->X_op
== O_constant
)
14106 /* Sizing gets taken care of by optimize_disp().
14108 If not 64bit, sign/zero extend val, to account for wraparound
14110 if (expr_mode
== expr_operator_present
14111 && flag_code
!= CODE_64BIT
&& !object_64bit
)
14112 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
14115 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14116 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
14117 && exp_seg
!= absolute_section
14118 && exp_seg
!= text_section
14119 && exp_seg
!= data_section
14120 && exp_seg
!= bss_section
14121 && exp_seg
!= undefined_section
14122 && !bfd_is_com_section (exp_seg
))
14124 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
14129 else if (current_templates
.start
->opcode_modifier
.jump
== JUMP_BYTE
)
14130 i
.types
[this_operand
].bitfield
.disp8
= 1;
14132 /* Check if this is a displacement only operand. */
14133 if (!i
.types
[this_operand
].bitfield
.baseindex
)
14134 i
.types
[this_operand
] =
14135 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
14136 operand_type_and (i
.types
[this_operand
], types
));
14141 /* Return the active addressing mode, taking address override and
14142 registers forming the address into consideration. Update the
14143 address override prefix if necessary. */
14145 static enum flag_code
14146 i386_addressing_mode (void)
14148 enum flag_code addr_mode
;
14150 if (i
.prefix
[ADDR_PREFIX
])
14151 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
14152 else if (flag_code
== CODE_16BIT
14153 && is_cpu (current_templates
.start
, CpuMPX
)
14154 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
14155 from md_assemble() by "is not a valid base/index expression"
14156 when there is a base and/or index. */
14157 && !i
.types
[this_operand
].bitfield
.baseindex
)
14159 /* MPX insn memory operands with neither base nor index must be forced
14160 to use 32-bit addressing in 16-bit mode. */
14161 addr_mode
= CODE_32BIT
;
14162 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
14164 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
14165 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
14169 addr_mode
= flag_code
;
14171 #if INFER_ADDR_PREFIX
14172 if (i
.mem_operands
== 0)
14174 /* Infer address prefix from the first memory operand. */
14175 const reg_entry
*addr_reg
= i
.base_reg
;
14177 if (addr_reg
== NULL
)
14178 addr_reg
= i
.index_reg
;
14182 if (addr_reg
->reg_type
.bitfield
.dword
)
14183 addr_mode
= CODE_32BIT
;
14184 else if (flag_code
!= CODE_64BIT
14185 && addr_reg
->reg_type
.bitfield
.word
)
14186 addr_mode
= CODE_16BIT
;
14188 if (addr_mode
!= flag_code
)
14190 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
14192 /* Change the size of any displacement too. At most one
14193 of Disp16 or Disp32 is set.
14194 FIXME. There doesn't seem to be any real need for
14195 separate Disp16 and Disp32 flags. The same goes for
14196 Imm16 and Imm32. Removing them would probably clean
14197 up the code quite a lot. */
14198 if (flag_code
!= CODE_64BIT
14199 && (i
.types
[this_operand
].bitfield
.disp16
14200 || i
.types
[this_operand
].bitfield
.disp32
))
14202 static const i386_operand_type disp16_32
= {
14203 .bitfield
= { .disp16
= 1, .disp32
= 1 }
14206 i
.types
[this_operand
]
14207 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
14218 /* Make sure the memory operand we've been dealt is valid.
14219 Return 1 on success, 0 on a failure. */
14222 i386_index_check (const char *operand_string
)
14224 const char *kind
= "base/index";
14225 enum flag_code addr_mode
= i386_addressing_mode ();
14226 const insn_template
*t
= current_templates
.end
- 1;
14228 if (t
->opcode_modifier
.isstring
)
14230 /* Memory operands of string insns are special in that they only allow
14231 a single register (rDI, rSI, or rBX) as their memory address. */
14232 const reg_entry
*expected_reg
;
14233 static const char di_si
[][2][4] =
14239 static const char bx
[][4] = { "ebx", "bx", "rbx" };
14241 kind
= "string address";
14243 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
14245 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
14248 if (!t
->operand_types
[0].bitfield
.baseindex
14249 || ((!i
.mem_operands
!= !intel_syntax
)
14250 && t
->operand_types
[1].bitfield
.baseindex
))
14253 = (const reg_entry
*) str_hash_find (reg_hash
,
14254 di_si
[addr_mode
][op
== es_op
]);
14258 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
14260 if (i
.base_reg
!= expected_reg
14262 || operand_type_check (i
.types
[this_operand
], disp
))
14264 /* The second memory operand must have the same size as
14268 && !((addr_mode
== CODE_64BIT
14269 && i
.base_reg
->reg_type
.bitfield
.qword
)
14270 || (addr_mode
== CODE_32BIT
14271 ? i
.base_reg
->reg_type
.bitfield
.dword
14272 : i
.base_reg
->reg_type
.bitfield
.word
)))
14275 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
14277 intel_syntax
? '[' : '(',
14279 expected_reg
->reg_name
,
14280 intel_syntax
? ']' : ')');
14287 as_bad (_("`%s' is not a valid %s expression"),
14288 operand_string
, kind
);
14293 t
= current_templates
.start
;
14295 if (addr_mode
!= CODE_16BIT
)
14297 /* 32-bit/64-bit checks. */
14298 if (i
.disp_encoding
== disp_encoding_16bit
)
14301 as_bad (_("invalid `%s' prefix"),
14302 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
14307 && ((addr_mode
== CODE_64BIT
14308 ? !i
.base_reg
->reg_type
.bitfield
.qword
14309 : !i
.base_reg
->reg_type
.bitfield
.dword
)
14310 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
14311 || i
.base_reg
->reg_num
== RegIZ
))
14313 && !i
.index_reg
->reg_type
.bitfield
.xmmword
14314 && !i
.index_reg
->reg_type
.bitfield
.ymmword
14315 && !i
.index_reg
->reg_type
.bitfield
.zmmword
14316 && ((addr_mode
== CODE_64BIT
14317 ? !i
.index_reg
->reg_type
.bitfield
.qword
14318 : !i
.index_reg
->reg_type
.bitfield
.dword
)
14319 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
14322 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
14323 if (t
->mnem_off
== MN_bndmk
14324 || t
->mnem_off
== MN_bndldx
14325 || t
->mnem_off
== MN_bndstx
14326 || t
->opcode_modifier
.sib
== SIBMEM
)
14328 /* They cannot use RIP-relative addressing. */
14329 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
14331 as_bad (_("`%s' cannot be used here"), operand_string
);
14335 /* bndldx and bndstx ignore their scale factor. */
14336 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
14337 && i
.log2_scale_factor
)
14338 as_warn (_("register scaling is being ignored here"));
14343 /* 16-bit checks. */
14344 if (i
.disp_encoding
== disp_encoding_32bit
)
14348 && (!i
.base_reg
->reg_type
.bitfield
.word
14349 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
14351 && (!i
.index_reg
->reg_type
.bitfield
.word
14352 || !i
.index_reg
->reg_type
.bitfield
.baseindex
14354 && i
.base_reg
->reg_num
< 6
14355 && i
.index_reg
->reg_num
>= 6
14356 && i
.log2_scale_factor
== 0))))
14363 /* Handle vector immediates. */
14366 RC_SAE_immediate (const char *imm_start
)
14368 const char *pstr
= imm_start
;
14373 pstr
= RC_SAE_specifier (pstr
+ 1);
14377 if (*pstr
++ != '}')
14379 as_bad (_("Missing '}': '%s'"), imm_start
);
14382 /* RC/SAE immediate string should contain nothing more. */;
14385 as_bad (_("Junk after '}': '%s'"), imm_start
);
14389 /* Internally this doesn't count as an operand. */
14395 static INLINE
bool starts_memory_operand (char c
)
14398 || is_name_beginner (c
)
14399 || strchr ("([\"+-!~", c
);
14402 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
14406 i386_att_operand (char *operand_string
)
14408 const reg_entry
*r
;
14410 char *op_string
= operand_string
;
14412 if (is_space_char (*op_string
))
14415 /* We check for an absolute prefix (differentiating,
14416 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
14417 if (*op_string
== ABSOLUTE_PREFIX
14418 && current_templates
.start
->opcode_modifier
.jump
)
14421 if (is_space_char (*op_string
))
14423 i
.jumpabsolute
= true;
14426 /* Check if operand is a register. */
14427 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
14429 i386_operand_type temp
;
14434 /* Check for a segment override by searching for ':' after a
14435 segment register. */
14436 op_string
= end_op
;
14437 if (is_space_char (*op_string
))
14439 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
14441 i
.seg
[i
.mem_operands
] = r
;
14443 /* Skip the ':' and whitespace. */
14445 if (is_space_char (*op_string
))
14448 /* Handle case of %es:*foo. */
14449 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
14450 && current_templates
.start
->opcode_modifier
.jump
)
14453 if (is_space_char (*op_string
))
14455 i
.jumpabsolute
= true;
14458 if (!starts_memory_operand (*op_string
))
14460 as_bad (_("bad memory operand `%s'"), op_string
);
14463 goto do_memory_reference
;
14466 /* Handle vector operations. */
14467 if (*op_string
== '{')
14469 op_string
= check_VecOperations (op_string
);
14470 if (op_string
== NULL
)
14476 as_bad (_("junk `%s' after register"), op_string
);
14480 /* Reject pseudo registers for .insn. */
14481 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
14483 as_bad (_("`%s%s' cannot be used here"),
14484 register_prefix
, r
->reg_name
);
14488 temp
= r
->reg_type
;
14489 temp
.bitfield
.baseindex
= 0;
14490 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
14492 i
.types
[this_operand
].bitfield
.unspecified
= 0;
14493 i
.op
[this_operand
].regs
= r
;
14496 /* A GPR may follow an RC or SAE immediate only if a (vector) register
14497 operand was also present earlier on. */
14498 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
14499 && i
.reg_operands
== 1)
14503 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
14504 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
14506 as_bad (_("`%s': misplaced `{%s}'"),
14507 insn_name (current_templates
.start
), RC_NamesTable
[j
].name
);
14511 else if (*op_string
== REGISTER_PREFIX
)
14513 as_bad (_("bad register name `%s'"), op_string
);
14516 else if (*op_string
== IMMEDIATE_PREFIX
)
14519 if (i
.jumpabsolute
)
14521 as_bad (_("immediate operand illegal with absolute jump"));
14524 if (!i386_immediate (op_string
))
14526 if (i
.rounding
.type
!= rc_none
)
14528 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
14529 insn_name (current_templates
.start
));
14533 else if (RC_SAE_immediate (operand_string
))
14535 /* If it is a RC or SAE immediate, do the necessary placement check:
14536 Only another immediate or a GPR may precede it. */
14537 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
14538 || (i
.reg_operands
== 1
14539 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
14541 as_bad (_("`%s': misplaced `%s'"),
14542 insn_name (current_templates
.start
), operand_string
);
14546 else if (starts_memory_operand (*op_string
))
14548 /* This is a memory reference of some sort. */
14551 /* Start and end of displacement string expression (if found). */
14552 char *displacement_string_start
;
14553 char *displacement_string_end
;
14555 do_memory_reference
:
14556 /* Check for base index form. We detect the base index form by
14557 looking for an ')' at the end of the operand, searching
14558 for the '(' matching it, and finding a REGISTER_PREFIX or ','
14560 base_string
= op_string
+ strlen (op_string
);
14562 /* Handle vector operations. */
14564 if (is_space_char (*base_string
))
14567 if (*base_string
== '}')
14569 char *vop_start
= NULL
;
14571 while (base_string
-- > op_string
)
14573 if (*base_string
== '"')
14575 if (*base_string
!= '{')
14578 vop_start
= base_string
;
14581 if (is_space_char (*base_string
))
14584 if (*base_string
!= '}')
14592 as_bad (_("unbalanced figure braces"));
14596 if (check_VecOperations (vop_start
) == NULL
)
14600 /* If we only have a displacement, set-up for it to be parsed later. */
14601 displacement_string_start
= op_string
;
14602 displacement_string_end
= base_string
+ 1;
14604 if (*base_string
== ')')
14607 unsigned int parens_not_balanced
= 0;
14608 bool in_quotes
= false;
14610 /* We've already checked that the number of left & right ()'s are
14611 equal, and that there's a matching set of double quotes. */
14612 end_op
= base_string
;
14613 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
14615 if (*temp_string
== '\\' && temp_string
[1] == '"')
14617 else if (*temp_string
== '"')
14618 in_quotes
= !in_quotes
;
14619 else if (!in_quotes
)
14621 if (*temp_string
== '(' && !parens_not_balanced
++)
14622 base_string
= temp_string
;
14623 if (*temp_string
== ')')
14624 --parens_not_balanced
;
14628 temp_string
= base_string
;
14630 /* Skip past '(' and whitespace. */
14631 gas_assert (*base_string
== '(');
14633 if (is_space_char (*base_string
))
14636 if (*base_string
== ','
14637 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
14640 displacement_string_end
= temp_string
;
14642 i
.types
[this_operand
].bitfield
.baseindex
= 1;
14646 if (i
.base_reg
== &bad_reg
)
14648 base_string
= end_op
;
14649 if (is_space_char (*base_string
))
14653 /* There may be an index reg or scale factor here. */
14654 if (*base_string
== ',')
14657 if (is_space_char (*base_string
))
14660 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
14663 if (i
.index_reg
== &bad_reg
)
14665 base_string
= end_op
;
14666 if (is_space_char (*base_string
))
14668 if (*base_string
== ',')
14671 if (is_space_char (*base_string
))
14674 else if (*base_string
!= ')')
14676 as_bad (_("expecting `,' or `)' "
14677 "after index register in `%s'"),
14682 else if (*base_string
== REGISTER_PREFIX
)
14684 end_op
= strchr (base_string
, ',');
14687 as_bad (_("bad register name `%s'"), base_string
);
14691 /* Check for scale factor. */
14692 if (*base_string
!= ')')
14694 char *end_scale
= i386_scale (base_string
);
14699 base_string
= end_scale
;
14700 if (is_space_char (*base_string
))
14702 if (*base_string
!= ')')
14704 as_bad (_("expecting `)' "
14705 "after scale factor in `%s'"),
14710 else if (!i
.index_reg
)
14712 as_bad (_("expecting index register or scale factor "
14713 "after `,'; got '%c'"),
14718 else if (*base_string
!= ')')
14720 as_bad (_("expecting `,' or `)' "
14721 "after base register in `%s'"),
14726 else if (*base_string
== REGISTER_PREFIX
)
14728 end_op
= strchr (base_string
, ',');
14731 as_bad (_("bad register name `%s'"), base_string
);
14736 /* If there's an expression beginning the operand, parse it,
14737 assuming displacement_string_start and
14738 displacement_string_end are meaningful. */
14739 if (displacement_string_start
!= displacement_string_end
)
14741 if (!i386_displacement (displacement_string_start
,
14742 displacement_string_end
))
14746 /* Special case for (%dx) while doing input/output op. */
14748 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
14749 && i
.base_reg
->reg_type
.bitfield
.word
14750 && i
.index_reg
== 0
14751 && i
.log2_scale_factor
== 0
14752 && i
.seg
[i
.mem_operands
] == 0
14753 && !operand_type_check (i
.types
[this_operand
], disp
))
14755 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
14756 i
.op
[this_operand
].regs
= i
.base_reg
;
14758 i
.input_output_operand
= true;
14762 if (i386_index_check (operand_string
) == 0)
14764 i
.flags
[this_operand
] |= Operand_Mem
;
14769 /* It's not a memory operand; argh! */
14770 as_bad (_("invalid char %s beginning operand %d `%s'"),
14771 output_invalid (*op_string
),
14776 return 1; /* Normal return. */
14779 /* Calculate the maximum variable size (i.e., excluding fr_fix)
14780 that an rs_machine_dependent frag may reach. */
14783 i386_frag_max_var (fragS
*frag
)
14785 /* The only relaxable frags are for jumps.
14786 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
14787 gas_assert (frag
->fr_type
== rs_machine_dependent
);
14788 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
14791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14793 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
14795 /* STT_GNU_IFUNC symbol must go through PLT. */
14796 if ((symbol_get_bfdsym (fr_symbol
)->flags
14797 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
14800 if (!S_IS_EXTERNAL (fr_symbol
))
14801 /* Symbol may be weak or local. */
14802 return !S_IS_WEAK (fr_symbol
);
14804 /* Global symbols with non-default visibility can't be preempted. */
14805 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
14808 if (fr_var
!= NO_RELOC
)
14809 switch ((enum bfd_reloc_code_real
) fr_var
)
14811 case BFD_RELOC_386_PLT32
:
14812 case BFD_RELOC_X86_64_PLT32
:
14813 /* Symbol with PLT relocation may be preempted. */
14819 /* Global symbols with default visibility in a shared library may be
14820 preempted by another definition. */
14825 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
14826 Note also work for Skylake and Cascadelake.
14827 ---------------------------------------------------------------------
14828 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
14829 | ------ | ----------- | ------- | -------- |
14831 | Jno | N | N | Y |
14832 | Jc/Jb | Y | N | Y |
14833 | Jae/Jnb | Y | N | Y |
14834 | Je/Jz | Y | Y | Y |
14835 | Jne/Jnz | Y | Y | Y |
14836 | Jna/Jbe | Y | N | Y |
14837 | Ja/Jnbe | Y | N | Y |
14839 | Jns | N | N | Y |
14840 | Jp/Jpe | N | N | Y |
14841 | Jnp/Jpo | N | N | Y |
14842 | Jl/Jnge | Y | Y | Y |
14843 | Jge/Jnl | Y | Y | Y |
14844 | Jle/Jng | Y | Y | Y |
14845 | Jg/Jnle | Y | Y | Y |
14846 --------------------------------------------------------------------- */
14848 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
14850 if (mf_cmp
== mf_cmp_alu_cmp
)
14851 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
14852 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
14853 if (mf_cmp
== mf_cmp_incdec
)
14854 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
14855 || mf_jcc
== mf_jcc_jle
);
14856 if (mf_cmp
== mf_cmp_test_and
)
14861 /* Return the next non-empty frag. */
14864 i386_next_non_empty_frag (fragS
*fragP
)
14866 /* There may be a frag with a ".fill 0" when there is no room in
14867 the current frag for frag_grow in output_insn. */
14868 for (fragP
= fragP
->fr_next
;
14870 && fragP
->fr_type
== rs_fill
14871 && fragP
->fr_fix
== 0);
14872 fragP
= fragP
->fr_next
)
14877 /* Return the next jcc frag after BRANCH_PADDING. */
14880 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
14882 fragS
*branch_fragP
;
14886 if (pad_fragP
->fr_type
== rs_machine_dependent
14887 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
14888 == BRANCH_PADDING
))
14890 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
14891 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
14893 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
14894 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
14895 pad_fragP
->tc_frag_data
.mf_type
))
14896 return branch_fragP
;
14902 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
14905 i386_classify_machine_dependent_frag (fragS
*fragP
)
14909 fragS
*branch_fragP
;
14911 unsigned int max_prefix_length
;
14913 if (fragP
->tc_frag_data
.classified
)
14916 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
14917 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
14918 for (next_fragP
= fragP
;
14919 next_fragP
!= NULL
;
14920 next_fragP
= next_fragP
->fr_next
)
14922 next_fragP
->tc_frag_data
.classified
= 1;
14923 if (next_fragP
->fr_type
== rs_machine_dependent
)
14924 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
14926 case BRANCH_PADDING
:
14927 /* The BRANCH_PADDING frag must be followed by a branch
14929 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
14930 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
14932 case FUSED_JCC_PADDING
:
14933 /* Check if this is a fused jcc:
14935 CMP like instruction
14939 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
14940 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
14941 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
14944 /* The BRANCH_PADDING frag is merged with the
14945 FUSED_JCC_PADDING frag. */
14946 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
14947 /* CMP like instruction size. */
14948 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
14949 frag_wane (pad_fragP
);
14950 /* Skip to branch_fragP. */
14951 next_fragP
= branch_fragP
;
14953 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
14955 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
14957 next_fragP
->fr_subtype
14958 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
14959 next_fragP
->tc_frag_data
.max_bytes
14960 = next_fragP
->tc_frag_data
.max_prefix_length
;
14961 /* This will be updated in the BRANCH_PREFIX scan. */
14962 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
14965 frag_wane (next_fragP
);
14970 /* Stop if there is no BRANCH_PREFIX. */
14971 if (!align_branch_prefix_size
)
14974 /* Scan for BRANCH_PREFIX. */
14975 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
14977 if (fragP
->fr_type
!= rs_machine_dependent
14978 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
14982 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
14983 COND_JUMP_PREFIX. */
14984 max_prefix_length
= 0;
14985 for (next_fragP
= fragP
;
14986 next_fragP
!= NULL
;
14987 next_fragP
= next_fragP
->fr_next
)
14989 if (next_fragP
->fr_type
== rs_fill
)
14990 /* Skip rs_fill frags. */
14992 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
14993 /* Stop for all other frags. */
14996 /* rs_machine_dependent frags. */
14997 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
15000 /* Count BRANCH_PREFIX frags. */
15001 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
15003 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
15004 frag_wane (next_fragP
);
15008 += next_fragP
->tc_frag_data
.max_bytes
;
15010 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
15012 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
15013 == FUSED_JCC_PADDING
))
15015 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
15016 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
15020 /* Stop for other rs_machine_dependent frags. */
15024 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
15026 /* Skip to the next frag. */
15027 fragP
= next_fragP
;
15031 /* Compute padding size for
15034 CMP like instruction
15036 COND_JUMP/UNCOND_JUMP
15041 COND_JUMP/UNCOND_JUMP
15045 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
15047 unsigned int offset
, size
, padding_size
;
15048 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
15050 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
15052 address
= fragP
->fr_address
;
15053 address
+= fragP
->fr_fix
;
15055 /* CMP like instrunction size. */
15056 size
= fragP
->tc_frag_data
.cmp_size
;
15058 /* The base size of the branch frag. */
15059 size
+= branch_fragP
->fr_fix
;
15061 /* Add opcode and displacement bytes for the rs_machine_dependent
15063 if (branch_fragP
->fr_type
== rs_machine_dependent
)
15064 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
15066 /* Check if branch is within boundary and doesn't end at the last
15068 offset
= address
& ((1U << align_branch_power
) - 1);
15069 if ((offset
+ size
) >= (1U << align_branch_power
))
15070 /* Padding needed to avoid crossing boundary. */
15071 padding_size
= (1U << align_branch_power
) - offset
;
15073 /* No padding needed. */
15076 /* The return value may be saved in tc_frag_data.length which is
15078 if (!fits_in_unsigned_byte (padding_size
))
15081 return padding_size
;
15084 /* i386_generic_table_relax_frag()
15086 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
15087 grow/shrink padding to align branch frags. Hand others to
15091 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
15093 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
15094 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
15096 long padding_size
= i386_branch_padding_size (fragP
, 0);
15097 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
15099 /* When the BRANCH_PREFIX frag is used, the computed address
15100 must match the actual address and there should be no padding. */
15101 if (fragP
->tc_frag_data
.padding_address
15102 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
15106 /* Update the padding size. */
15108 fragP
->tc_frag_data
.length
= padding_size
;
15112 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
15114 fragS
*padding_fragP
, *next_fragP
;
15115 long padding_size
, left_size
, last_size
;
15117 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
15118 if (!padding_fragP
)
15119 /* Use the padding set by the leading BRANCH_PREFIX frag. */
15120 return (fragP
->tc_frag_data
.length
15121 - fragP
->tc_frag_data
.last_length
);
15123 /* Compute the relative address of the padding frag in the very
15124 first time where the BRANCH_PREFIX frag sizes are zero. */
15125 if (!fragP
->tc_frag_data
.padding_address
)
15126 fragP
->tc_frag_data
.padding_address
15127 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
15129 /* First update the last length from the previous interation. */
15130 left_size
= fragP
->tc_frag_data
.prefix_length
;
15131 for (next_fragP
= fragP
;
15132 next_fragP
!= padding_fragP
;
15133 next_fragP
= next_fragP
->fr_next
)
15134 if (next_fragP
->fr_type
== rs_machine_dependent
15135 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
15140 int max
= next_fragP
->tc_frag_data
.max_bytes
;
15144 if (max
> left_size
)
15149 next_fragP
->tc_frag_data
.last_length
= size
;
15153 next_fragP
->tc_frag_data
.last_length
= 0;
15156 /* Check the padding size for the padding frag. */
15157 padding_size
= i386_branch_padding_size
15158 (padding_fragP
, (fragP
->fr_address
15159 + fragP
->tc_frag_data
.padding_address
));
15161 last_size
= fragP
->tc_frag_data
.prefix_length
;
15162 /* Check if there is change from the last interation. */
15163 if (padding_size
== last_size
)
15165 /* Update the expected address of the padding frag. */
15166 padding_fragP
->tc_frag_data
.padding_address
15167 = (fragP
->fr_address
+ padding_size
15168 + fragP
->tc_frag_data
.padding_address
);
15172 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
15174 /* No padding if there is no sufficient room. Clear the
15175 expected address of the padding frag. */
15176 padding_fragP
->tc_frag_data
.padding_address
= 0;
15180 /* Store the expected address of the padding frag. */
15181 padding_fragP
->tc_frag_data
.padding_address
15182 = (fragP
->fr_address
+ padding_size
15183 + fragP
->tc_frag_data
.padding_address
);
15185 fragP
->tc_frag_data
.prefix_length
= padding_size
;
15187 /* Update the length for the current interation. */
15188 left_size
= padding_size
;
15189 for (next_fragP
= fragP
;
15190 next_fragP
!= padding_fragP
;
15191 next_fragP
= next_fragP
->fr_next
)
15192 if (next_fragP
->fr_type
== rs_machine_dependent
15193 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
15198 int max
= next_fragP
->tc_frag_data
.max_bytes
;
15202 if (max
> left_size
)
15207 next_fragP
->tc_frag_data
.length
= size
;
15211 next_fragP
->tc_frag_data
.length
= 0;
15214 return (fragP
->tc_frag_data
.length
15215 - fragP
->tc_frag_data
.last_length
);
15217 return relax_frag (segment
, fragP
, stretch
);
15220 /* md_estimate_size_before_relax()
15222 Called just before relax() for rs_machine_dependent frags. The x86
15223 assembler uses these frags to handle variable size jump
15226 Any symbol that is now undefined will not become defined.
15227 Return the correct fr_subtype in the frag.
15228 Return the initial "guess for variable size of frag" to caller.
15229 The guess is actually the growth beyond the fixed part. Whatever
15230 we do to grow the fixed or variable part contributes to our
15234 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
15236 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
15237 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
15238 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
15240 i386_classify_machine_dependent_frag (fragP
);
15241 return fragP
->tc_frag_data
.length
;
15244 /* We've already got fragP->fr_subtype right; all we have to do is
15245 check for un-relaxable symbols. On an ELF system, we can't relax
15246 an externally visible symbol, because it may be overridden by a
15248 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
15249 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15251 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
15254 #if defined (OBJ_COFF) && defined (TE_PE)
15255 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
15256 && S_IS_WEAK (fragP
->fr_symbol
))
15260 /* Symbol is undefined in this segment, or we need to keep a
15261 reloc so that weak symbols can be overridden. */
15262 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
15263 enum bfd_reloc_code_real reloc_type
;
15264 unsigned char *opcode
;
15268 if (fragP
->fr_var
!= NO_RELOC
)
15269 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
15270 else if (size
== 2)
15271 reloc_type
= BFD_RELOC_16_PCREL
;
15272 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15273 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
15274 && fragP
->fr_offset
== 0
15275 && need_plt32_p (fragP
->fr_symbol
))
15276 reloc_type
= BFD_RELOC_X86_64_PLT32
;
15279 reloc_type
= BFD_RELOC_32_PCREL
;
15281 old_fr_fix
= fragP
->fr_fix
;
15282 opcode
= (unsigned char *) fragP
->fr_opcode
;
15284 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
15287 /* Make jmp (0xeb) a (d)word displacement jump. */
15289 fragP
->fr_fix
+= size
;
15290 fixP
= fix_new (fragP
, old_fr_fix
, size
,
15292 fragP
->fr_offset
, 1,
15298 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
15300 /* Negate the condition, and branch past an
15301 unconditional jump. */
15304 /* Insert an unconditional jump. */
15306 /* We added two extra opcode bytes, and have a two byte
15308 fragP
->fr_fix
+= 2 + 2;
15309 fix_new (fragP
, old_fr_fix
+ 2, 2,
15311 fragP
->fr_offset
, 1,
15315 /* Fall through. */
15318 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
15320 fragP
->fr_fix
+= 1;
15321 fixP
= fix_new (fragP
, old_fr_fix
, 1,
15323 fragP
->fr_offset
, 1,
15324 BFD_RELOC_8_PCREL
);
15325 fixP
->fx_signed
= 1;
15329 /* This changes the byte-displacement jump 0x7N
15330 to the (d)word-displacement jump 0x0f,0x8N. */
15331 opcode
[1] = opcode
[0] + 0x10;
15332 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
15333 /* We've added an opcode byte. */
15334 fragP
->fr_fix
+= 1 + size
;
15335 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
15337 fragP
->fr_offset
, 1,
15342 BAD_CASE (fragP
->fr_subtype
);
15346 /* All jumps handled here are signed, but don't unconditionally use a
15347 signed limit check for 32 and 16 bit jumps as we want to allow wrap
15348 around at 4G (outside of 64-bit mode) and 64k. */
15349 if (size
== 4 && flag_code
== CODE_64BIT
)
15350 fixP
->fx_signed
= 1;
15353 return fragP
->fr_fix
- old_fr_fix
;
15356 /* Guess size depending on current relax state. Initially the relax
15357 state will correspond to a short jump and we return 1, because
15358 the variable part of the frag (the branch offset) is one byte
15359 long. However, we can relax a section more than once and in that
15360 case we must either set fr_subtype back to the unrelaxed state,
15361 or return the value for the appropriate branch. */
15362 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
15365 /* Called after relax() is finished.
15367 In: Address of frag.
15368 fr_type == rs_machine_dependent.
15369 fr_subtype is what the address relaxed to.
15371 Out: Any fixSs and constants are set up.
15372 Caller will turn frag into a ".space 0". */
15375 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
15378 unsigned char *opcode
;
15379 unsigned char *where_to_put_displacement
= NULL
;
15380 offsetT target_address
;
15381 offsetT opcode_address
;
15382 unsigned int extension
= 0;
15383 offsetT displacement_from_opcode_start
;
15385 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
15386 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
15387 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
15389 /* Generate nop padding. */
15390 unsigned int size
= fragP
->tc_frag_data
.length
;
15393 if (size
> fragP
->tc_frag_data
.max_bytes
)
15399 const char *branch
= "branch";
15400 const char *prefix
= "";
15401 fragS
*padding_fragP
;
15402 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
15405 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
15406 switch (fragP
->tc_frag_data
.default_prefix
)
15411 case CS_PREFIX_OPCODE
:
15414 case DS_PREFIX_OPCODE
:
15417 case ES_PREFIX_OPCODE
:
15420 case FS_PREFIX_OPCODE
:
15423 case GS_PREFIX_OPCODE
:
15426 case SS_PREFIX_OPCODE
:
15431 msg
= _("%s:%u: add %d%s at 0x%llx to align "
15432 "%s within %d-byte boundary\n");
15434 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
15435 "align %s within %d-byte boundary\n");
15439 padding_fragP
= fragP
;
15440 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
15441 "%s within %d-byte boundary\n");
15445 switch (padding_fragP
->tc_frag_data
.branch_type
)
15447 case align_branch_jcc
:
15450 case align_branch_fused
:
15451 branch
= "fused jcc";
15453 case align_branch_jmp
:
15456 case align_branch_call
:
15459 case align_branch_indirect
:
15460 branch
= "indiret branch";
15462 case align_branch_ret
:
15469 fprintf (stdout
, msg
,
15470 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
15471 (long long) fragP
->fr_address
, branch
,
15472 1 << align_branch_power
);
15474 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
15475 memset (fragP
->fr_opcode
,
15476 fragP
->tc_frag_data
.default_prefix
, size
);
15478 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
15480 fragP
->fr_fix
+= size
;
15485 opcode
= (unsigned char *) fragP
->fr_opcode
;
15487 /* Address we want to reach in file space. */
15488 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
15490 /* Address opcode resides at in file space. */
15491 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
15493 /* Displacement from opcode start to fill into instruction. */
15494 displacement_from_opcode_start
= target_address
- opcode_address
;
15496 if ((fragP
->fr_subtype
& BIG
) == 0)
15498 /* Don't have to change opcode. */
15499 extension
= 1; /* 1 opcode + 1 displacement */
15500 where_to_put_displacement
= &opcode
[1];
15504 if (no_cond_jump_promotion
15505 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
15506 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
15507 _("long jump required"));
15509 switch (fragP
->fr_subtype
)
15511 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
15512 extension
= 4; /* 1 opcode + 4 displacement */
15514 where_to_put_displacement
= &opcode
[1];
15517 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
15518 extension
= 2; /* 1 opcode + 2 displacement */
15520 where_to_put_displacement
= &opcode
[1];
15523 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
15524 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
15525 extension
= 5; /* 2 opcode + 4 displacement */
15526 opcode
[1] = opcode
[0] + 0x10;
15527 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
15528 where_to_put_displacement
= &opcode
[2];
15531 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
15532 extension
= 3; /* 2 opcode + 2 displacement */
15533 opcode
[1] = opcode
[0] + 0x10;
15534 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
15535 where_to_put_displacement
= &opcode
[2];
15538 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
15543 where_to_put_displacement
= &opcode
[3];
15547 BAD_CASE (fragP
->fr_subtype
);
15552 /* If size if less then four we are sure that the operand fits,
15553 but if it's 4, then it could be that the displacement is larger
15555 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
15557 && ((addressT
) (displacement_from_opcode_start
- extension
15558 + ((addressT
) 1 << 31))
15559 > (((addressT
) 2 << 31) - 1)))
15561 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
15562 _("jump target out of range"));
15563 /* Make us emit 0. */
15564 displacement_from_opcode_start
= extension
;
15566 /* Now put displacement after opcode. */
15567 md_number_to_chars ((char *) where_to_put_displacement
,
15568 (valueT
) (displacement_from_opcode_start
- extension
),
15569 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
15570 fragP
->fr_fix
+= extension
;
15573 /* Apply a fixup (fixP) to segment data, once it has been determined
15574 by our caller that we have all the info we need to fix it up.
15576 Parameter valP is the pointer to the value of the bits.
15578 On the 386, immediates, displacements, and data pointers are all in
15579 the same (little-endian) format, so we don't need to care about which
15580 we are handling. */
15583 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15585 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
15586 valueT value
= *valP
;
15588 #if !defined (TE_Mach)
15589 if (fixP
->fx_pcrel
)
15591 switch (fixP
->fx_r_type
)
15597 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
15600 case BFD_RELOC_X86_64_32S
:
15601 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15604 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
15607 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
15612 if (fixP
->fx_addsy
!= NULL
15613 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
15614 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
15615 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
15616 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
15617 && !use_rela_relocations
)
15619 /* This is a hack. There should be a better way to handle this.
15620 This covers for the fact that bfd_install_relocation will
15621 subtract the current location (for partial_inplace, PC relative
15622 relocations); see more below. */
15626 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
15629 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15631 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15634 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
15636 if ((sym_seg
== seg
15637 || (symbol_section_p (fixP
->fx_addsy
)
15638 && sym_seg
!= absolute_section
))
15639 && !generic_force_reloc (fixP
))
15641 /* Yes, we add the values in twice. This is because
15642 bfd_install_relocation subtracts them out again. I think
15643 bfd_install_relocation is broken, but I don't dare change
15645 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15649 #if defined (OBJ_COFF) && defined (TE_PE)
15650 /* For some reason, the PE format does not store a
15651 section address offset for a PC relative symbol. */
15652 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
15653 || S_IS_WEAK (fixP
->fx_addsy
))
15654 value
+= md_pcrel_from (fixP
);
15657 #if defined (OBJ_COFF) && defined (TE_PE)
15658 if (fixP
->fx_addsy
!= NULL
15659 && S_IS_WEAK (fixP
->fx_addsy
)
15660 /* PR 16858: Do not modify weak function references. */
15661 && ! fixP
->fx_pcrel
)
15663 #if !defined (TE_PEP)
15664 /* For x86 PE weak function symbols are neither PC-relative
15665 nor do they set S_IS_FUNCTION. So the only reliable way
15666 to detect them is to check the flags of their containing
15668 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
15669 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
15673 value
-= S_GET_VALUE (fixP
->fx_addsy
);
15677 /* Fix a few things - the dynamic linker expects certain values here,
15678 and we must not disappoint it. */
15679 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15680 if (IS_ELF
&& fixP
->fx_addsy
)
15681 switch (fixP
->fx_r_type
)
15683 case BFD_RELOC_386_PLT32
:
15684 case BFD_RELOC_X86_64_PLT32
:
15685 /* Make the jump instruction point to the address of the operand.
15686 At runtime we merely add the offset to the actual PLT entry.
15687 NB: Subtract the offset size only for jump instructions. */
15688 if (fixP
->fx_pcrel
)
15692 case BFD_RELOC_386_TLS_GD
:
15693 case BFD_RELOC_386_TLS_LDM
:
15694 case BFD_RELOC_386_TLS_IE_32
:
15695 case BFD_RELOC_386_TLS_IE
:
15696 case BFD_RELOC_386_TLS_GOTIE
:
15697 case BFD_RELOC_386_TLS_GOTDESC
:
15698 case BFD_RELOC_X86_64_TLSGD
:
15699 case BFD_RELOC_X86_64_TLSLD
:
15700 case BFD_RELOC_X86_64_GOTTPOFF
:
15701 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF
:
15702 case BFD_RELOC_X86_64_CODE_6_GOTTPOFF
:
15703 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15704 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
:
15705 value
= 0; /* Fully resolved at runtime. No addend. */
15707 case BFD_RELOC_386_TLS_LE
:
15708 case BFD_RELOC_386_TLS_LDO_32
:
15709 case BFD_RELOC_386_TLS_LE_32
:
15710 case BFD_RELOC_X86_64_DTPOFF32
:
15711 case BFD_RELOC_X86_64_DTPOFF64
:
15712 case BFD_RELOC_X86_64_TPOFF32
:
15713 case BFD_RELOC_X86_64_TPOFF64
:
15714 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15717 case BFD_RELOC_386_TLS_DESC_CALL
:
15718 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15719 value
= 0; /* Fully resolved at runtime. No addend. */
15720 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15724 case BFD_RELOC_VTABLE_INHERIT
:
15725 case BFD_RELOC_VTABLE_ENTRY
:
15732 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
15734 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
15736 value
= extend_to_32bit_address (value
);
15739 #endif /* !defined (TE_Mach) */
15741 /* Are we finished with this relocation now? */
15742 if (fixP
->fx_addsy
== NULL
)
15745 switch (fixP
->fx_r_type
)
15747 case BFD_RELOC_X86_64_32S
:
15748 fixP
->fx_signed
= 1;
15755 #if defined (OBJ_COFF) && defined (TE_PE)
15756 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
15759 /* Remember value for tc_gen_reloc. */
15760 fixP
->fx_addnumber
= value
;
15761 /* Clear out the frag for now. */
15765 else if (use_rela_relocations
)
15767 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
15768 fixP
->fx_no_overflow
= 1;
15769 /* Remember value for tc_gen_reloc. */
15770 fixP
->fx_addnumber
= value
;
15774 md_number_to_chars (p
, value
, fixP
->fx_size
);
15778 md_atof (int type
, char *litP
, int *sizeP
)
15780 /* This outputs the LITTLENUMs in REVERSE order;
15781 in accord with the bigendian 386. */
15782 return ieee_md_atof (type
, litP
, sizeP
, false);
15785 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
15788 output_invalid (int c
)
15791 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
15794 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
15795 "(0x%x)", (unsigned char) c
);
15796 return output_invalid_buf
;
15799 /* Verify that @r can be used in the current context. */
15801 static bool check_register (const reg_entry
*r
)
15803 if (allow_pseudo_reg
)
15806 if (operand_type_all_zero (&r
->reg_type
))
15809 if ((r
->reg_type
.bitfield
.dword
15810 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
15811 || r
->reg_type
.bitfield
.class == RegCR
15812 || r
->reg_type
.bitfield
.class == RegDR
)
15813 && !cpu_arch_flags
.bitfield
.cpui386
)
15816 if (r
->reg_type
.bitfield
.class == RegTR
15817 && (flag_code
== CODE_64BIT
15818 || !cpu_arch_flags
.bitfield
.cpui386
15819 || cpu_arch_isa_flags
.bitfield
.cpui586
15820 || cpu_arch_isa_flags
.bitfield
.cpui686
))
15823 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
15826 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
15828 if (r
->reg_type
.bitfield
.zmmword
15829 || r
->reg_type
.bitfield
.class == RegMask
)
15832 if (!cpu_arch_flags
.bitfield
.cpuavx
)
15834 if (r
->reg_type
.bitfield
.ymmword
)
15837 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
15842 if (r
->reg_type
.bitfield
.zmmword
)
15844 if (vector_size
< VSZ512
)
15847 switch (i
.encoding
)
15849 case encoding_default
:
15850 case encoding_egpr
:
15851 i
.encoding
= encoding_evex512
;
15853 case encoding_evex
:
15854 case encoding_evex512
:
15857 i
.encoding
= encoding_error
;
15862 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
15865 if (r
->reg_type
.bitfield
.tmmword
15866 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
15867 || flag_code
!= CODE_64BIT
))
15870 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
15873 /* Don't allow fake index register unless allow_index_reg isn't 0. */
15874 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
15877 /* Upper 16 vector registers are only available with VREX in 64bit
15878 mode, and require EVEX encoding. */
15879 if (r
->reg_flags
& RegVRex
)
15881 if (!cpu_arch_flags
.bitfield
.cpuavx512f
15882 || flag_code
!= CODE_64BIT
)
15885 switch (i
.encoding
)
15887 case encoding_default
:
15888 case encoding_egpr
:
15889 case encoding_evex512
:
15890 i
.encoding
= encoding_evex
;
15892 case encoding_evex
:
15895 i
.encoding
= encoding_error
;
15900 if (r
->reg_flags
& RegRex2
)
15902 if (!cpu_arch_flags
.bitfield
.cpuapx_f
15903 || flag_code
!= CODE_64BIT
)
15906 switch (i
.encoding
)
15908 case encoding_default
:
15909 i
.encoding
= encoding_egpr
;
15911 case encoding_egpr
:
15912 case encoding_evex
:
15913 case encoding_evex512
:
15916 i
.encoding
= encoding_error
;
15921 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
15922 && (!cpu_arch_flags
.bitfield
.cpu64
15923 || r
->reg_type
.bitfield
.class != RegCR
15925 && flag_code
!= CODE_64BIT
)
15928 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
15935 /* REG_STRING starts *before* REGISTER_PREFIX. */
15937 static const reg_entry
*
15938 parse_real_register (const char *reg_string
, char **end_op
)
15940 const char *s
= reg_string
;
15942 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
15943 const reg_entry
*r
;
15945 /* Skip possible REGISTER_PREFIX and possible whitespace. */
15946 if (*s
== REGISTER_PREFIX
)
15949 if (is_space_char (*s
))
15952 p
= reg_name_given
;
15953 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
15955 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
15956 return (const reg_entry
*) NULL
;
15960 if (is_part_of_name (*s
))
15961 return (const reg_entry
*) NULL
;
15963 *end_op
= (char *) s
;
15965 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
15967 /* Handle floating point regs, allowing spaces in the (i) part. */
15970 if (!cpu_arch_flags
.bitfield
.cpu8087
15971 && !cpu_arch_flags
.bitfield
.cpu287
15972 && !cpu_arch_flags
.bitfield
.cpu387
15973 && !allow_pseudo_reg
)
15974 return (const reg_entry
*) NULL
;
15976 if (is_space_char (*s
))
15981 if (is_space_char (*s
))
15983 if (*s
>= '0' && *s
<= '7')
15985 int fpr
= *s
- '0';
15987 if (is_space_char (*s
))
15991 *end_op
= (char *) s
+ 1;
15992 know (r
[fpr
].reg_num
== fpr
);
15996 /* We have "%st(" then garbage. */
15997 return (const reg_entry
*) NULL
;
16001 return r
&& check_register (r
) ? r
: NULL
;
16004 /* REG_STRING starts *before* REGISTER_PREFIX. */
16006 static const reg_entry
*
16007 parse_register (const char *reg_string
, char **end_op
)
16009 const reg_entry
*r
;
16011 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
16012 r
= parse_real_register (reg_string
, end_op
);
16017 char *save
= input_line_pointer
;
16018 char *buf
= xstrdup (reg_string
), *name
;
16021 input_line_pointer
= buf
;
16022 get_symbol_name (&name
);
16023 symbolP
= symbol_find (name
);
16024 while (symbolP
&& symbol_equated_p (symbolP
))
16026 const expressionS
*e
= symbol_get_value_expression(symbolP
);
16028 if (e
->X_add_number
)
16030 symbolP
= e
->X_add_symbol
;
16032 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
16034 const expressionS
*e
= symbol_get_value_expression (symbolP
);
16036 if (e
->X_op
== O_register
)
16038 know (e
->X_add_number
>= 0
16039 && (valueT
) e
->X_add_number
< i386_regtab_size
);
16040 r
= i386_regtab
+ e
->X_add_number
;
16041 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
16043 if (r
&& !check_register (r
))
16045 as_bad (_("register '%s%s' cannot be used here"),
16046 register_prefix
, r
->reg_name
);
16050 input_line_pointer
= save
;
16057 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
16059 const reg_entry
*r
= NULL
;
16060 char *end
= input_line_pointer
;
16062 /* We only know the terminating character here. It being double quote could
16063 be the closing one of a quoted symbol name, or an opening one from a
16064 following string (or another quoted symbol name). Since the latter can't
16065 be valid syntax for anything, bailing in either case is good enough. */
16066 if (*nextcharP
== '"')
16070 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
16071 r
= parse_real_register (name
, &input_line_pointer
);
16072 if (r
&& end
<= input_line_pointer
)
16074 *nextcharP
= *input_line_pointer
;
16075 *input_line_pointer
= 0;
16076 e
->X_op
= O_register
;
16077 e
->X_add_number
= r
- i386_regtab
;
16080 input_line_pointer
= end
;
16082 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
16086 md_operand (expressionS
*e
)
16089 const reg_entry
*r
;
16091 switch (*input_line_pointer
)
16093 case REGISTER_PREFIX
:
16094 r
= parse_real_register (input_line_pointer
, &end
);
16097 e
->X_op
= O_register
;
16098 e
->X_add_number
= r
- i386_regtab
;
16099 input_line_pointer
= end
;
16104 gas_assert (intel_syntax
);
16105 end
= input_line_pointer
++;
16107 if (*input_line_pointer
== ']')
16109 ++input_line_pointer
;
16110 e
->X_op_symbol
= make_expr_symbol (e
);
16111 e
->X_add_symbol
= NULL
;
16112 e
->X_add_number
= 0;
16117 e
->X_op
= O_absent
;
16118 input_line_pointer
= end
;
16125 /* To maintain consistency with !BFD64 builds of gas record, whether any
16126 (binary) operator was involved in an expression. As expressions are
16127 evaluated in only 32 bits when !BFD64, we use this to decide whether to
16128 truncate results. */
16129 bool i386_record_operator (operatorT op
,
16130 const expressionS
*left
,
16131 const expressionS
*right
)
16133 if (op
== O_absent
)
16138 /* Since the expression parser applies unary operators fine to bignum
16139 operands, we don't need to be concerned of respective operands not
16140 fitting in 32 bits. */
16141 if (right
->X_op
== O_constant
&& right
->X_unsigned
16142 && !fits_in_unsigned_long (right
->X_add_number
))
16145 /* This isn't entirely right: The pattern can also result when constant
16146 expressions are folded (e.g. 0xffffffff + 1). */
16147 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
16148 && !fits_in_unsigned_long (left
->X_add_number
))
16149 || (right
->X_op
== O_constant
&& right
->X_unsigned
16150 && !fits_in_unsigned_long (right
->X_add_number
)))
16151 expr_mode
= expr_large_value
;
16153 if (expr_mode
!= expr_large_value
)
16154 expr_mode
= expr_operator_present
;
16160 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16161 const char *md_shortopts
= "kVQ:sqnO::";
16163 const char *md_shortopts
= "qnO::";
16166 #define OPTION_32 (OPTION_MD_BASE + 0)
16167 #define OPTION_64 (OPTION_MD_BASE + 1)
16168 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
16169 #define OPTION_MARCH (OPTION_MD_BASE + 3)
16170 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
16171 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
16172 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
16173 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
16174 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
16175 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
16176 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
16177 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
16178 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
16179 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
16180 #define OPTION_X32 (OPTION_MD_BASE + 14)
16181 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
16182 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
16183 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
16184 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
16185 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
16186 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
16187 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
16188 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
16189 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
16190 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
16191 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
16192 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
16193 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
16194 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
16195 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
16196 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
16197 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
16198 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
16199 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
16200 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
16202 struct option md_longopts
[] =
16204 {"32", no_argument
, NULL
, OPTION_32
},
16205 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
16206 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
16207 {"64", no_argument
, NULL
, OPTION_64
},
16209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16210 {"x32", no_argument
, NULL
, OPTION_X32
},
16211 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
16212 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
16214 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
16215 {"march", required_argument
, NULL
, OPTION_MARCH
},
16216 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
16217 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
16218 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
16219 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
16220 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
16221 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
16222 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
16223 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
16224 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
16225 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
16226 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
16227 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
16228 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
16229 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
16230 # if defined (TE_PE) || defined (TE_PEP)
16231 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
16233 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
16234 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
16235 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
16236 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
16237 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
16238 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
16239 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
16240 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
16241 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
16242 {"mlfence-before-indirect-branch", required_argument
, NULL
,
16243 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
16244 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
16245 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
16246 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
16247 {NULL
, no_argument
, NULL
, 0}
16249 size_t md_longopts_size
= sizeof (md_longopts
);
16252 md_parse_option (int c
, const char *arg
)
16255 char *arch
, *next
, *saved
, *type
;
16260 optimize_align_code
= 0;
16264 quiet_warnings
= 1;
16267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16268 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
16269 should be emitted or not. FIXME: Not implemented. */
16271 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
16275 /* -V: SVR4 argument to print version ID. */
16277 print_version_id ();
16280 /* -k: Ignore for FreeBSD compatibility. */
16285 /* -s: On i386 Solaris, this tells the native assembler to use
16286 .stab instead of .stab.excl. We always use .stab anyhow. */
16289 case OPTION_MSHARED
:
16293 case OPTION_X86_USED_NOTE
:
16294 if (strcasecmp (arg
, "yes") == 0)
16296 else if (strcasecmp (arg
, "no") == 0)
16299 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
16304 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
16305 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
16308 const char **list
, **l
;
16310 list
= bfd_target_list ();
16311 for (l
= list
; *l
!= NULL
; l
++)
16312 if (startswith (*l
, "elf64-x86-64")
16313 || strcmp (*l
, "coff-x86-64") == 0
16314 || strcmp (*l
, "pe-x86-64") == 0
16315 || strcmp (*l
, "pei-x86-64") == 0
16316 || strcmp (*l
, "mach-o-x86-64") == 0)
16318 default_arch
= "x86_64";
16322 as_fatal (_("no compiled in support for x86_64"));
16328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16332 const char **list
, **l
;
16334 list
= bfd_target_list ();
16335 for (l
= list
; *l
!= NULL
; l
++)
16336 if (startswith (*l
, "elf32-x86-64"))
16338 default_arch
= "x86_64:32";
16342 as_fatal (_("no compiled in support for 32bit x86_64"));
16346 as_fatal (_("32bit x86_64 is only supported for ELF"));
16352 const char **list
, **l
;
16354 list
= bfd_target_list ();
16355 for (l
= list
; *l
!= NULL
; l
++)
16356 if (strstr (*l
, "-i386")
16357 || strstr (*l
, "-go32"))
16359 default_arch
= "i386";
16363 as_fatal (_("no compiled in support for ix86"));
16368 case OPTION_DIVIDE
:
16369 #ifdef SVR4_COMMENT_CHARS
16374 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
16376 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
16380 i386_comment_chars
= n
;
16386 saved
= xstrdup (arg
);
16388 /* Allow -march=+nosse. */
16396 as_fatal (_("invalid -march= option: `%s'"), arg
);
16397 next
= strchr (arch
, '+');
16400 vsz
= strchr (arch
, '/');
16403 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
16405 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
16408 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
16409 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
16412 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
16415 cpu_arch_name
= cpu_arch
[j
].name
;
16416 free (cpu_sub_arch_name
);
16417 cpu_sub_arch_name
= NULL
;
16418 cpu_arch_flags
= cpu_arch
[j
].enable
;
16419 cpu_arch_isa
= cpu_arch
[j
].type
;
16420 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
16421 if (!cpu_arch_tune_set
)
16422 cpu_arch_tune
= cpu_arch_isa
;
16423 vector_size
= VSZ_DEFAULT
;
16426 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
16427 && strcmp (arch
, cpu_arch
[j
].name
) == 0
16428 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
16430 /* ISA extension. */
16433 switch (cpu_arch
[j
].vsz
)
16442 unsigned long val
= strtoul (vsz
, &end
, 0);
16448 case 512: vector_size
= VSZ512
; break;
16449 case 256: vector_size
= VSZ256
; break;
16450 case 128: vector_size
= VSZ128
; break;
16452 as_warn (_("Unrecognized vector size specifier ignored"));
16457 /* Fall through. */
16459 vector_size
= VSZ_DEFAULT
;
16467 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
16469 /* Disable an ISA extension. */
16470 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
16471 if (cpu_arch
[j
].type
== PROCESSOR_NONE
16472 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
16475 if (cpu_arch
[j
].vsz
== vsz_set
)
16476 vector_size
= VSZ_DEFAULT
;
16481 if (j
>= ARRAY_SIZE (cpu_arch
))
16482 as_fatal (_("invalid -march= option: `%s'"), arg
);
16486 while (next
!= NULL
);
16492 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
16493 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
16495 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
16496 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
16498 cpu_arch_tune_set
= 1;
16499 cpu_arch_tune
= cpu_arch
[j
].type
;
16503 if (j
>= ARRAY_SIZE (cpu_arch
))
16504 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
16507 case OPTION_MMNEMONIC
:
16508 if (strcasecmp (arg
, "att") == 0)
16509 intel_mnemonic
= 0;
16510 else if (strcasecmp (arg
, "intel") == 0)
16511 intel_mnemonic
= 1;
16513 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
16516 case OPTION_MSYNTAX
:
16517 if (strcasecmp (arg
, "att") == 0)
16518 _set_intel_syntax (0);
16519 else if (strcasecmp (arg
, "intel") == 0)
16520 _set_intel_syntax (1);
16522 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
16525 case OPTION_MINDEX_REG
:
16526 allow_index_reg
= 1;
16529 case OPTION_MNAKED_REG
:
16530 allow_naked_reg
= 1;
16531 register_prefix
= "";
16534 case OPTION_MSSE2AVX
:
16538 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
16539 use_unaligned_vector_move
= 1;
16542 case OPTION_MSSE_CHECK
:
16543 if (strcasecmp (arg
, "error") == 0)
16544 sse_check
= check_error
;
16545 else if (strcasecmp (arg
, "warning") == 0)
16546 sse_check
= check_warning
;
16547 else if (strcasecmp (arg
, "none") == 0)
16548 sse_check
= check_none
;
16550 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
16553 case OPTION_MOPERAND_CHECK
:
16554 if (strcasecmp (arg
, "error") == 0)
16555 operand_check
= check_error
;
16556 else if (strcasecmp (arg
, "warning") == 0)
16557 operand_check
= check_warning
;
16558 else if (strcasecmp (arg
, "none") == 0)
16559 operand_check
= check_none
;
16561 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
16564 case OPTION_MAVXSCALAR
:
16565 if (strcasecmp (arg
, "128") == 0)
16566 avxscalar
= vex128
;
16567 else if (strcasecmp (arg
, "256") == 0)
16568 avxscalar
= vex256
;
16570 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
16573 case OPTION_MVEXWIG
:
16574 if (strcmp (arg
, "0") == 0)
16576 else if (strcmp (arg
, "1") == 0)
16579 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
16582 case OPTION_MADD_BND_PREFIX
:
16583 add_bnd_prefix
= 1;
16586 case OPTION_MEVEXLIG
:
16587 if (strcmp (arg
, "128") == 0)
16588 evexlig
= evexl128
;
16589 else if (strcmp (arg
, "256") == 0)
16590 evexlig
= evexl256
;
16591 else if (strcmp (arg
, "512") == 0)
16592 evexlig
= evexl512
;
16594 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
16597 case OPTION_MEVEXRCIG
:
16598 if (strcmp (arg
, "rne") == 0)
16600 else if (strcmp (arg
, "rd") == 0)
16602 else if (strcmp (arg
, "ru") == 0)
16604 else if (strcmp (arg
, "rz") == 0)
16607 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
16610 case OPTION_MEVEXWIG
:
16611 if (strcmp (arg
, "0") == 0)
16613 else if (strcmp (arg
, "1") == 0)
16616 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
16619 # if defined (TE_PE) || defined (TE_PEP)
16620 case OPTION_MBIG_OBJ
:
16625 case OPTION_MOMIT_LOCK_PREFIX
:
16626 if (strcasecmp (arg
, "yes") == 0)
16627 omit_lock_prefix
= 1;
16628 else if (strcasecmp (arg
, "no") == 0)
16629 omit_lock_prefix
= 0;
16631 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
16634 case OPTION_MFENCE_AS_LOCK_ADD
:
16635 if (strcasecmp (arg
, "yes") == 0)
16637 else if (strcasecmp (arg
, "no") == 0)
16640 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
16643 case OPTION_MLFENCE_AFTER_LOAD
:
16644 if (strcasecmp (arg
, "yes") == 0)
16645 lfence_after_load
= 1;
16646 else if (strcasecmp (arg
, "no") == 0)
16647 lfence_after_load
= 0;
16649 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
16652 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
16653 if (strcasecmp (arg
, "all") == 0)
16655 lfence_before_indirect_branch
= lfence_branch_all
;
16656 if (lfence_before_ret
== lfence_before_ret_none
)
16657 lfence_before_ret
= lfence_before_ret_shl
;
16659 else if (strcasecmp (arg
, "memory") == 0)
16660 lfence_before_indirect_branch
= lfence_branch_memory
;
16661 else if (strcasecmp (arg
, "register") == 0)
16662 lfence_before_indirect_branch
= lfence_branch_register
;
16663 else if (strcasecmp (arg
, "none") == 0)
16664 lfence_before_indirect_branch
= lfence_branch_none
;
16666 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
16670 case OPTION_MLFENCE_BEFORE_RET
:
16671 if (strcasecmp (arg
, "or") == 0)
16672 lfence_before_ret
= lfence_before_ret_or
;
16673 else if (strcasecmp (arg
, "not") == 0)
16674 lfence_before_ret
= lfence_before_ret_not
;
16675 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
16676 lfence_before_ret
= lfence_before_ret_shl
;
16677 else if (strcasecmp (arg
, "none") == 0)
16678 lfence_before_ret
= lfence_before_ret_none
;
16680 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
16684 case OPTION_MRELAX_RELOCATIONS
:
16685 if (strcasecmp (arg
, "yes") == 0)
16686 generate_relax_relocations
= 1;
16687 else if (strcasecmp (arg
, "no") == 0)
16688 generate_relax_relocations
= 0;
16690 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
16693 case OPTION_MALIGN_BRANCH_BOUNDARY
:
16696 long int align
= strtoul (arg
, &end
, 0);
16701 align_branch_power
= 0;
16704 else if (align
>= 16)
16707 for (align_power
= 0;
16709 align
>>= 1, align_power
++)
16711 /* Limit alignment power to 31. */
16712 if (align
== 1 && align_power
< 32)
16714 align_branch_power
= align_power
;
16719 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
16723 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
16726 int align
= strtoul (arg
, &end
, 0);
16727 /* Some processors only support 5 prefixes. */
16728 if (*end
== '\0' && align
>= 0 && align
< 6)
16730 align_branch_prefix_size
= align
;
16733 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
16738 case OPTION_MALIGN_BRANCH
:
16740 saved
= xstrdup (arg
);
16744 next
= strchr (type
, '+');
16747 if (strcasecmp (type
, "jcc") == 0)
16748 align_branch
|= align_branch_jcc_bit
;
16749 else if (strcasecmp (type
, "fused") == 0)
16750 align_branch
|= align_branch_fused_bit
;
16751 else if (strcasecmp (type
, "jmp") == 0)
16752 align_branch
|= align_branch_jmp_bit
;
16753 else if (strcasecmp (type
, "call") == 0)
16754 align_branch
|= align_branch_call_bit
;
16755 else if (strcasecmp (type
, "ret") == 0)
16756 align_branch
|= align_branch_ret_bit
;
16757 else if (strcasecmp (type
, "indirect") == 0)
16758 align_branch
|= align_branch_indirect_bit
;
16760 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
16763 while (next
!= NULL
);
16767 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
16768 align_branch_power
= 5;
16769 align_branch_prefix_size
= 5;
16770 align_branch
= (align_branch_jcc_bit
16771 | align_branch_fused_bit
16772 | align_branch_jmp_bit
);
16775 case OPTION_MAMD64
:
16779 case OPTION_MINTEL64
:
16787 /* Turn off -Os. */
16788 optimize_for_space
= 0;
16790 else if (*arg
== 's')
16792 optimize_for_space
= 1;
16793 /* Turn on all encoding optimizations. */
16794 optimize
= INT_MAX
;
16798 optimize
= atoi (arg
);
16799 /* Turn off -Os. */
16800 optimize_for_space
= 0;
16810 #define MESSAGE_TEMPLATE \
16814 output_message (FILE *stream
, char *p
, char *message
, char *start
,
16815 int *left_p
, const char *name
, int len
)
16817 int size
= sizeof (MESSAGE_TEMPLATE
);
16818 int left
= *left_p
;
16820 /* Reserve 2 spaces for ", " or ",\0" */
16823 /* Check if there is any room. */
16831 p
= mempcpy (p
, name
, len
);
16835 /* Output the current message now and start a new one. */
16838 fprintf (stream
, "%s\n", message
);
16840 left
= size
- (start
- message
) - len
- 2;
16842 gas_assert (left
>= 0);
16844 p
= mempcpy (p
, name
, len
);
16852 show_arch (FILE *stream
, int ext
, int check
)
16854 static char message
[] = MESSAGE_TEMPLATE
;
16855 char *start
= message
+ 27;
16857 int size
= sizeof (MESSAGE_TEMPLATE
);
16864 left
= size
- (start
- message
);
16868 p
= output_message (stream
, p
, message
, start
, &left
,
16869 STRING_COMMA_LEN ("default"));
16870 p
= output_message (stream
, p
, message
, start
, &left
,
16871 STRING_COMMA_LEN ("push"));
16872 p
= output_message (stream
, p
, message
, start
, &left
,
16873 STRING_COMMA_LEN ("pop"));
16876 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
16878 /* Should it be skipped? */
16879 if (cpu_arch
[j
].skip
)
16882 name
= cpu_arch
[j
].name
;
16883 len
= cpu_arch
[j
].len
;
16884 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
16886 /* It is an extension. Skip if we aren't asked to show it. */
16887 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
16892 /* It is an processor. Skip if we show only extension. */
16895 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
16897 /* It is an impossible processor - skip. */
16901 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
16904 /* Display disabled extensions. */
16906 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
16910 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
16911 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
16913 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
16914 p
= output_message (stream
, p
, message
, start
, &left
, str
,
16920 fprintf (stream
, "%s\n", message
);
16924 md_show_usage (FILE *stream
)
16926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16927 fprintf (stream
, _("\
16928 -Qy, -Qn ignored\n\
16929 -V print assembler version number\n\
16932 fprintf (stream
, _("\
16933 -n do not optimize code alignment\n\
16934 -O{012s} attempt some code optimizations\n\
16935 -q quieten some warnings\n"));
16936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16937 fprintf (stream
, _("\
16941 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16942 fprintf (stream
, _("\
16943 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
16944 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
16945 fprintf (stream
, _("\
16946 --32/--64 generate 32bit/64bit object\n"));
16949 #ifdef SVR4_COMMENT_CHARS
16950 fprintf (stream
, _("\
16951 --divide do not treat `/' as a comment character\n"));
16953 fprintf (stream
, _("\
16954 --divide ignored\n"));
16956 fprintf (stream
, _("\
16957 -march=CPU[,+EXTENSION...]\n\
16958 generate code for CPU and EXTENSION, CPU is one of:\n"));
16959 show_arch (stream
, 0, 1);
16960 fprintf (stream
, _("\
16961 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
16962 show_arch (stream
, 1, 0);
16963 fprintf (stream
, _("\
16964 -mtune=CPU optimize for CPU, CPU is one of:\n"));
16965 show_arch (stream
, 0, 0);
16966 fprintf (stream
, _("\
16967 -msse2avx encode SSE instructions with VEX prefix\n"));
16968 fprintf (stream
, _("\
16969 -muse-unaligned-vector-move\n\
16970 encode aligned vector move as unaligned vector move\n"));
16971 fprintf (stream
, _("\
16972 -msse-check=[none|error|warning] (default: none)\n\
16973 check SSE instructions\n"));
16974 fprintf (stream
, _("\
16975 -moperand-check=[none|error|warning] (default: warning)\n\
16976 check operand combinations for validity\n"));
16977 fprintf (stream
, _("\
16978 -mavxscalar=[128|256] (default: 128)\n\
16979 encode scalar AVX instructions with specific vector\n\
16981 fprintf (stream
, _("\
16982 -mvexwig=[0|1] (default: 0)\n\
16983 encode VEX instructions with specific VEX.W value\n\
16984 for VEX.W bit ignored instructions\n"));
16985 fprintf (stream
, _("\
16986 -mevexlig=[128|256|512] (default: 128)\n\
16987 encode scalar EVEX instructions with specific vector\n\
16989 fprintf (stream
, _("\
16990 -mevexwig=[0|1] (default: 0)\n\
16991 encode EVEX instructions with specific EVEX.W value\n\
16992 for EVEX.W bit ignored instructions\n"));
16993 fprintf (stream
, _("\
16994 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
16995 encode EVEX instructions with specific EVEX.RC value\n\
16996 for SAE-only ignored instructions\n"));
16997 fprintf (stream
, _("\
16998 -mmnemonic=[att|intel] "));
16999 if (SYSV386_COMPAT
)
17000 fprintf (stream
, _("(default: att)\n"));
17002 fprintf (stream
, _("(default: intel)\n"));
17003 fprintf (stream
, _("\
17004 use AT&T/Intel mnemonic (AT&T syntax only)\n"));
17005 fprintf (stream
, _("\
17006 -msyntax=[att|intel] (default: att)\n\
17007 use AT&T/Intel syntax\n"));
17008 fprintf (stream
, _("\
17009 -mindex-reg support pseudo index registers\n"));
17010 fprintf (stream
, _("\
17011 -mnaked-reg don't require `%%' prefix for registers\n"));
17012 fprintf (stream
, _("\
17013 -madd-bnd-prefix add BND prefix for all valid branches\n"));
17014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17015 fprintf (stream
, _("\
17016 -mshared disable branch optimization for shared code\n"));
17017 fprintf (stream
, _("\
17018 -mx86-used-note=[no|yes] "));
17019 if (DEFAULT_X86_USED_NOTE
)
17020 fprintf (stream
, _("(default: yes)\n"));
17022 fprintf (stream
, _("(default: no)\n"));
17023 fprintf (stream
, _("\
17024 generate x86 used ISA and feature properties\n"));
17026 #if defined (TE_PE) || defined (TE_PEP)
17027 fprintf (stream
, _("\
17028 -mbig-obj generate big object files\n"));
17030 fprintf (stream
, _("\
17031 -momit-lock-prefix=[no|yes] (default: no)\n\
17032 strip all lock prefixes\n"));
17033 fprintf (stream
, _("\
17034 -mfence-as-lock-add=[no|yes] (default: no)\n\
17035 encode lfence, mfence and sfence as\n\
17036 lock addl $0x0, (%%{re}sp)\n"));
17037 fprintf (stream
, _("\
17038 -mrelax-relocations=[no|yes] "));
17039 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
17040 fprintf (stream
, _("(default: yes)\n"));
17042 fprintf (stream
, _("(default: no)\n"));
17043 fprintf (stream
, _("\
17044 generate relax relocations\n"));
17045 fprintf (stream
, _("\
17046 -malign-branch-boundary=NUM (default: 0)\n\
17047 align branches within NUM byte boundary\n"));
17048 fprintf (stream
, _("\
17049 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
17050 TYPE is combination of jcc, fused, jmp, call, ret,\n\
17052 specify types of branches to align\n"));
17053 fprintf (stream
, _("\
17054 -malign-branch-prefix-size=NUM (default: 5)\n\
17055 align branches with NUM prefixes per instruction\n"));
17056 fprintf (stream
, _("\
17057 -mbranches-within-32B-boundaries\n\
17058 align branches within 32 byte boundary\n"));
17059 fprintf (stream
, _("\
17060 -mlfence-after-load=[no|yes] (default: no)\n\
17061 generate lfence after load\n"));
17062 fprintf (stream
, _("\
17063 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
17064 generate lfence before indirect near branch\n"));
17065 fprintf (stream
, _("\
17066 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
17067 generate lfence before ret\n"));
17068 fprintf (stream
, _("\
17069 -mamd64 accept only AMD64 ISA [default]\n"));
17070 fprintf (stream
, _("\
17071 -mintel64 accept only Intel64 ISA\n"));
17074 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
17075 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
17076 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
17078 /* Pick the target format to use. */
17081 i386_target_format (void)
17083 if (startswith (default_arch
, "x86_64"))
17085 update_code_flag (CODE_64BIT
, 1);
17086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17087 if (default_arch
[6] == '\0')
17088 x86_elf_abi
= X86_64_ABI
;
17090 x86_elf_abi
= X86_64_X32_ABI
;
17093 else if (!strcmp (default_arch
, "i386"))
17094 update_code_flag (CODE_32BIT
, 1);
17095 else if (!strcmp (default_arch
, "iamcu"))
17097 update_code_flag (CODE_32BIT
, 1);
17098 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
17100 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
17101 cpu_arch_name
= "iamcu";
17102 free (cpu_sub_arch_name
);
17103 cpu_sub_arch_name
= NULL
;
17104 cpu_arch_flags
= iamcu_flags
;
17105 cpu_arch_isa
= PROCESSOR_IAMCU
;
17106 cpu_arch_isa_flags
= iamcu_flags
;
17107 if (!cpu_arch_tune_set
)
17108 cpu_arch_tune
= PROCESSOR_IAMCU
;
17110 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
17111 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
17115 as_fatal (_("unknown architecture"));
17117 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17118 if (IS_ELF
&& flag_synth_cfi
&& x86_elf_abi
!= X86_64_ABI
)
17119 as_fatal (_("SCFI is not supported for this ABI"));
17122 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
17123 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
17125 switch (OUTPUT_FLAVOR
)
17127 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
17128 case bfd_target_aout_flavour
:
17129 return AOUT_TARGET_FORMAT
;
17131 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
17132 # if defined (TE_PE) || defined (TE_PEP)
17133 case bfd_target_coff_flavour
:
17134 if (flag_code
== CODE_64BIT
)
17137 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
17139 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
17140 # elif defined (TE_GO32)
17141 case bfd_target_coff_flavour
:
17142 return "coff-go32";
17144 case bfd_target_coff_flavour
:
17145 return "coff-i386";
17148 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
17149 case bfd_target_elf_flavour
:
17151 const char *format
;
17153 switch (x86_elf_abi
)
17156 format
= ELF_TARGET_FORMAT
;
17158 tls_get_addr
= "___tls_get_addr";
17162 use_rela_relocations
= 1;
17165 tls_get_addr
= "__tls_get_addr";
17167 format
= ELF_TARGET_FORMAT64
;
17169 case X86_64_X32_ABI
:
17170 use_rela_relocations
= 1;
17173 tls_get_addr
= "__tls_get_addr";
17175 disallow_64bit_reloc
= 1;
17176 format
= ELF_TARGET_FORMAT32
;
17179 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
17181 if (x86_elf_abi
!= I386_ABI
)
17182 as_fatal (_("Intel MCU is 32bit only"));
17183 return ELF_TARGET_IAMCU_FORMAT
;
17189 #if defined (OBJ_MACH_O)
17190 case bfd_target_mach_o_flavour
:
17191 if (flag_code
== CODE_64BIT
)
17193 use_rela_relocations
= 1;
17195 return "mach-o-x86-64";
17198 return "mach-o-i386";
17206 #endif /* OBJ_MAYBE_ more than one */
17209 md_undefined_symbol (char *name
)
17211 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
17212 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
17213 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
17214 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
17218 if (symbol_find (name
))
17219 as_bad (_("GOT already in symbol table"));
17220 GOT_symbol
= symbol_new (name
, undefined_section
,
17221 &zero_address_frag
, 0);
17228 #if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)
17229 /* Round up a section size to the appropriate boundary. */
17232 md_section_align (segT segment
, valueT size
)
17234 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17236 /* For a.out, force the section size to be aligned. If we don't do
17237 this, BFD will align it for us, but it will not write out the
17238 final bytes of the section. This may be a bug in BFD, but it is
17239 easier to fix it here since that is how the other a.out targets
17243 align
= bfd_section_alignment (segment
);
17244 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
17251 /* On the i386, PC-relative offsets are relative to the start of the
17252 next instruction. That is, the address of the offset, plus its
17253 size, since the offset is always the last part of the insn. */
17256 md_pcrel_from (fixS
*fixP
)
17258 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17264 s_bss (int ignore ATTRIBUTE_UNUSED
)
17268 temp
= get_absolute_expression ();
17269 subseg_set (bss_section
, (subsegT
) temp
);
17270 demand_empty_rest_of_line ();
17275 /* Remember constant directive. */
17278 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
17280 struct last_insn
*last_insn
17281 = &seg_info(now_seg
)->tc_segment_info_data
.last_insn
;
17283 if (bfd_section_flags (now_seg
) & SEC_CODE
)
17285 last_insn
->kind
= last_insn_directive
;
17286 last_insn
->name
= "constant directive";
17287 last_insn
->file
= as_where (&last_insn
->line
);
17292 i386_validate_fix (fixS
*fixp
)
17294 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
17296 reloc_howto_type
*howto
;
17298 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
17299 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17300 _("invalid %s relocation against register"),
17301 howto
? howto
->name
: "<unknown>");
17305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17306 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
17307 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
17308 return IS_ELF
&& fixp
->fx_addsy
17309 && (!S_IS_DEFINED (fixp
->fx_addsy
)
17310 || S_IS_EXTERNAL (fixp
->fx_addsy
));
17312 /* BFD_RELOC_X86_64_GOTTPOFF:
17313 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF
17314 2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF
17315 BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17316 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
17317 BFD_RELOC_32_PCREL:
17318 1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX
17319 2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX
17320 3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX
17321 4. else -> BFD_RELOC_X86_64_GOTPCREL
17323 if (fixp
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
)
17325 if (fixp
->fx_tcbit
)
17326 fixp
->fx_r_type
= BFD_RELOC_X86_64_CODE_4_GOTTPOFF
;
17327 else if (fixp
->fx_tcbit2
)
17328 fixp
->fx_r_type
= BFD_RELOC_X86_64_CODE_6_GOTTPOFF
;
17330 else if (fixp
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
17332 fixp
->fx_r_type
= BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
;
17335 if (fixp
->fx_subsy
)
17337 if (fixp
->fx_subsy
== GOT_symbol
)
17339 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17343 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17344 if (fixp
->fx_tcbit
)
17345 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCRELX
;
17346 else if (fixp
->fx_tcbit2
)
17347 fixp
->fx_r_type
= BFD_RELOC_X86_64_REX_GOTPCRELX
;
17348 else if (fixp
->fx_tcbit3
)
17349 fixp
->fx_r_type
= BFD_RELOC_X86_64_CODE_4_GOTPCRELX
;
17352 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
17357 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
17359 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
17361 fixp
->fx_subsy
= 0;
17364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17367 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
17368 to section. Since PLT32 relocation must be against symbols,
17369 turn such PLT32 relocation into PC32 relocation. */
17371 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
17372 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
17373 && symbol_section_p (fixp
->fx_addsy
))
17374 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
17377 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
17378 && fixp
->fx_tcbit2
)
17379 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
17388 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17391 bfd_reloc_code_real_type code
;
17393 switch (fixp
->fx_r_type
)
17395 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17398 case BFD_RELOC_SIZE32
:
17399 case BFD_RELOC_SIZE64
:
17401 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
17402 && (!fixp
->fx_subsy
17403 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
17404 sym
= fixp
->fx_addsy
;
17405 else if (fixp
->fx_subsy
17406 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
17407 && (!fixp
->fx_addsy
17408 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
17409 sym
= fixp
->fx_subsy
;
17412 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
17414 /* Resolve size relocation against local symbol to size of
17415 the symbol plus addend. */
17416 valueT value
= S_GET_SIZE (sym
);
17418 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
17419 value
= bfd_section_size (S_GET_SEGMENT (sym
));
17420 if (sym
== fixp
->fx_subsy
)
17423 if (fixp
->fx_addsy
)
17424 value
+= S_GET_VALUE (fixp
->fx_addsy
);
17426 else if (fixp
->fx_subsy
)
17427 value
-= S_GET_VALUE (fixp
->fx_subsy
);
17428 value
+= fixp
->fx_offset
;
17429 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
17431 && !fits_in_unsigned_long (value
))
17432 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17433 _("symbol size computation overflow"));
17434 fixp
->fx_addsy
= NULL
;
17435 fixp
->fx_subsy
= NULL
;
17436 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
17439 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
17441 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17442 "unsupported expression involving @size");
17446 /* Fall through. */
17448 case BFD_RELOC_X86_64_PLT32
:
17449 case BFD_RELOC_X86_64_GOT32
:
17450 case BFD_RELOC_X86_64_GOTPCREL
:
17451 case BFD_RELOC_X86_64_GOTPCRELX
:
17452 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
17453 case BFD_RELOC_X86_64_CODE_4_GOTPCRELX
:
17454 case BFD_RELOC_386_PLT32
:
17455 case BFD_RELOC_386_GOT32
:
17456 case BFD_RELOC_386_GOT32X
:
17457 case BFD_RELOC_386_GOTOFF
:
17458 case BFD_RELOC_386_GOTPC
:
17459 case BFD_RELOC_386_TLS_GD
:
17460 case BFD_RELOC_386_TLS_LDM
:
17461 case BFD_RELOC_386_TLS_LDO_32
:
17462 case BFD_RELOC_386_TLS_IE_32
:
17463 case BFD_RELOC_386_TLS_IE
:
17464 case BFD_RELOC_386_TLS_GOTIE
:
17465 case BFD_RELOC_386_TLS_LE_32
:
17466 case BFD_RELOC_386_TLS_LE
:
17467 case BFD_RELOC_386_TLS_GOTDESC
:
17468 case BFD_RELOC_386_TLS_DESC_CALL
:
17469 case BFD_RELOC_X86_64_TLSGD
:
17470 case BFD_RELOC_X86_64_TLSLD
:
17471 case BFD_RELOC_X86_64_DTPOFF32
:
17472 case BFD_RELOC_X86_64_DTPOFF64
:
17473 case BFD_RELOC_X86_64_GOTTPOFF
:
17474 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF
:
17475 case BFD_RELOC_X86_64_CODE_6_GOTTPOFF
:
17476 case BFD_RELOC_X86_64_TPOFF32
:
17477 case BFD_RELOC_X86_64_TPOFF64
:
17478 case BFD_RELOC_X86_64_GOTOFF64
:
17479 case BFD_RELOC_X86_64_GOTPC32
:
17480 case BFD_RELOC_X86_64_GOT64
:
17481 case BFD_RELOC_X86_64_GOTPCREL64
:
17482 case BFD_RELOC_X86_64_GOTPC64
:
17483 case BFD_RELOC_X86_64_GOTPLT64
:
17484 case BFD_RELOC_X86_64_PLTOFF64
:
17485 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
17486 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
:
17487 case BFD_RELOC_X86_64_TLSDESC_CALL
:
17488 case BFD_RELOC_RVA
:
17489 case BFD_RELOC_VTABLE_ENTRY
:
17490 case BFD_RELOC_VTABLE_INHERIT
:
17492 case BFD_RELOC_32_SECREL
:
17493 case BFD_RELOC_16_SECIDX
:
17495 code
= fixp
->fx_r_type
;
17497 case BFD_RELOC_X86_64_32S
:
17498 if (!fixp
->fx_pcrel
)
17500 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
17501 code
= fixp
->fx_r_type
;
17504 /* Fall through. */
17506 if (fixp
->fx_pcrel
)
17508 switch (fixp
->fx_size
)
17511 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17512 _("can not do %d byte pc-relative relocation"),
17514 code
= BFD_RELOC_32_PCREL
;
17516 case 1: code
= BFD_RELOC_8_PCREL
; break;
17517 case 2: code
= BFD_RELOC_16_PCREL
; break;
17518 case 4: code
= BFD_RELOC_32_PCREL
; break;
17520 case 8: code
= BFD_RELOC_64_PCREL
; break;
17526 switch (fixp
->fx_size
)
17529 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17530 _("can not do %d byte relocation"),
17532 code
= BFD_RELOC_32
;
17534 case 1: code
= BFD_RELOC_8
; break;
17535 case 2: code
= BFD_RELOC_16
; break;
17536 case 4: code
= BFD_RELOC_32
; break;
17538 case 8: code
= BFD_RELOC_64
; break;
17545 if ((code
== BFD_RELOC_32
17546 || code
== BFD_RELOC_32_PCREL
17547 || code
== BFD_RELOC_X86_64_32S
)
17549 && fixp
->fx_addsy
== GOT_symbol
)
17552 code
= BFD_RELOC_386_GOTPC
;
17554 code
= BFD_RELOC_X86_64_GOTPC32
;
17556 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
17558 && fixp
->fx_addsy
== GOT_symbol
)
17560 code
= BFD_RELOC_X86_64_GOTPC64
;
17563 rel
= XNEW (arelent
);
17564 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
17565 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17567 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17569 if (!use_rela_relocations
)
17571 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
17572 vtable entry to be used in the relocation's section offset. */
17573 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17574 rel
->address
= fixp
->fx_offset
;
17575 #if defined (OBJ_COFF) && defined (TE_PE)
17576 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
17577 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
17582 /* Use the rela in 64bit mode. */
17585 if (disallow_64bit_reloc
)
17588 case BFD_RELOC_X86_64_DTPOFF64
:
17589 case BFD_RELOC_X86_64_TPOFF64
:
17590 case BFD_RELOC_64_PCREL
:
17591 case BFD_RELOC_X86_64_GOTOFF64
:
17592 case BFD_RELOC_X86_64_GOT64
:
17593 case BFD_RELOC_X86_64_GOTPCREL64
:
17594 case BFD_RELOC_X86_64_GOTPC64
:
17595 case BFD_RELOC_X86_64_GOTPLT64
:
17596 case BFD_RELOC_X86_64_PLTOFF64
:
17597 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17598 _("cannot represent relocation type %s in x32 mode"),
17599 bfd_get_reloc_code_name (code
));
17605 if (!fixp
->fx_pcrel
)
17606 rel
->addend
= fixp
->fx_offset
;
17610 case BFD_RELOC_X86_64_PLT32
:
17611 case BFD_RELOC_X86_64_GOT32
:
17612 case BFD_RELOC_X86_64_GOTPCREL
:
17613 case BFD_RELOC_X86_64_GOTPCRELX
:
17614 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
17615 case BFD_RELOC_X86_64_CODE_4_GOTPCRELX
:
17616 case BFD_RELOC_X86_64_TLSGD
:
17617 case BFD_RELOC_X86_64_TLSLD
:
17618 case BFD_RELOC_X86_64_GOTTPOFF
:
17619 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF
:
17620 case BFD_RELOC_X86_64_CODE_6_GOTTPOFF
:
17621 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
17622 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
:
17623 case BFD_RELOC_X86_64_TLSDESC_CALL
:
17624 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
17627 rel
->addend
= (section
->vma
17629 + fixp
->fx_addnumber
17630 + md_pcrel_from (fixp
));
17635 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17636 if (rel
->howto
== NULL
)
17638 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17639 _("cannot represent relocation type %s"),
17640 bfd_get_reloc_code_name (code
));
17641 /* Set howto to a garbage value so that we can keep going. */
17642 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
17643 gas_assert (rel
->howto
!= NULL
);
17649 #include "tc-i386-intel.c"
17652 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
17654 int saved_naked_reg
;
17655 char saved_register_dot
;
17657 saved_naked_reg
= allow_naked_reg
;
17658 allow_naked_reg
= 1;
17659 saved_register_dot
= register_chars
['.'];
17660 register_chars
['.'] = '.';
17661 allow_pseudo_reg
= 1;
17662 expression_and_evaluate (exp
);
17663 allow_pseudo_reg
= 0;
17664 register_chars
['.'] = saved_register_dot
;
17665 allow_naked_reg
= saved_naked_reg
;
17667 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
17669 exp
->X_op
= O_illegal
;
17670 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
17672 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
17673 .dw2_regnum
[object_64bit
];
17674 if (exp
->X_add_number
!= Dw2Inval
)
17675 exp
->X_op
= O_constant
;
17681 tc_x86_frame_initial_instructions (void)
17683 cfi_add_CFA_def_cfa (object_64bit
? REG_SP
: 4, -x86_cie_data_alignment
);
17684 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
17688 x86_dwarf2_addr_size (void)
17690 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
17691 if (x86_elf_abi
== X86_64_X32_ABI
)
17694 return bfd_arch_bits_per_address (stdoutput
) / 8;
17699 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17703 exp
.X_op
= O_secrel
;
17704 exp
.X_add_symbol
= symbol
;
17705 exp
.X_add_number
= 0;
17706 emit_expr (&exp
, size
);
17710 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17712 i386_elf_section_type (const char *str
, size_t len
)
17714 if (flag_code
== CODE_64BIT
17715 && len
== sizeof ("unwind") - 1
17716 && startswith (str
, "unwind"))
17717 return SHT_X86_64_UNWIND
;
17723 i386_elf_section_change_hook (void)
17725 struct i386_segment_info
*info
= &seg_info(now_seg
)->tc_segment_info_data
;
17726 struct i386_segment_info
*curr
, *prev
;
17728 if (info
->subseg
== now_subseg
)
17731 /* Find the (or make a) list entry to save state into. */
17732 for (prev
= info
; (curr
= prev
->next
) != NULL
; prev
= curr
)
17733 if (curr
->subseg
== info
->subseg
)
17737 curr
= notes_alloc (sizeof (*curr
));
17738 curr
->subseg
= info
->subseg
;
17742 curr
->last_insn
= info
->last_insn
;
17744 /* Find the list entry to load state from. */
17745 for (curr
= info
->next
; curr
; curr
= curr
->next
)
17746 if (curr
->subseg
== now_subseg
)
17749 info
->last_insn
= curr
->last_insn
;
17751 memset (&info
->last_insn
, 0, sizeof (info
->last_insn
));
17752 info
->subseg
= now_subseg
;
17757 i386_solaris_fix_up_eh_frame (segT sec
)
17759 if (flag_code
== CODE_64BIT
)
17760 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
17764 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
17767 x86_64_section_letter (int letter
, const char **ptr_msg
)
17769 if (flag_code
== CODE_64BIT
)
17772 return SHF_X86_64_LARGE
;
17774 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
17777 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
17782 handle_large_common (int small ATTRIBUTE_UNUSED
)
17784 if (flag_code
!= CODE_64BIT
)
17786 s_comm_internal (0, elf_common_parse
);
17787 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
17791 static segT lbss_section
;
17792 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
17793 asection
*saved_bss_section
= bss_section
;
17795 if (lbss_section
== NULL
)
17797 flagword applicable
;
17798 segT seg
= now_seg
;
17799 subsegT subseg
= now_subseg
;
17801 /* The .lbss section is for local .largecomm symbols. */
17802 lbss_section
= subseg_new (".lbss", 0);
17803 applicable
= bfd_applicable_section_flags (stdoutput
);
17804 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
17805 seg_info (lbss_section
)->bss
= 1;
17807 subseg_set (seg
, subseg
);
17810 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
17811 bss_section
= lbss_section
;
17813 s_comm_internal (0, elf_common_parse
);
17815 elf_com_section_ptr
= saved_com_section_ptr
;
17816 bss_section
= saved_bss_section
;
17819 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */