1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
75 #include "nat/gdb_ptrace.h"
78 #ifndef PTRACE_GET_THREAD_AREA
79 #define PTRACE_GET_THREAD_AREA 25
82 /* This definition comes from prctl.h, but some kernels may not have it. */
83 #ifndef PTRACE_ARCH_PRCTL
84 #define PTRACE_ARCH_PRCTL 30
87 /* The following definitions come from prctl.h, but may be absent
88 for certain configurations. */
90 #define ARCH_SET_GS 0x1001
91 #define ARCH_SET_FS 0x1002
92 #define ARCH_GET_FS 0x1003
93 #define ARCH_GET_GS 0x1004
96 /* Per-process arch-specific data we want to keep. */
98 struct arch_process_info
100 struct x86_debug_reg_state debug_reg_state
;
105 /* Mapping between the general-purpose registers in `struct user'
106 format and GDB's register array layout.
107 Note that the transfer layout uses 64-bit regs. */
108 static /*const*/ int i386_regmap
[] =
110 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
111 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
112 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
113 DS
* 8, ES
* 8, FS
* 8, GS
* 8
116 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
118 /* So code below doesn't have to care, i386 or amd64. */
119 #define ORIG_EAX ORIG_RAX
122 static const int x86_64_regmap
[] =
124 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
125 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
126 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
127 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
128 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
129 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
130 -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1,
132 -1, -1, -1, -1, -1, -1, -1, -1,
134 -1, -1, -1, -1, -1, -1, -1, -1,
136 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
137 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
138 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
139 -1, -1, -1, -1, -1, -1, -1, -1,
140 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
141 -1, -1, -1, -1, -1, -1, -1, -1,
142 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
143 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
144 -1, -1, -1, -1, -1, -1, -1, -1,
145 -1, -1, -1, -1, -1, -1, -1, -1,
146 -1, -1, -1, -1, -1, -1, -1, -1
149 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
150 #define X86_64_USER_REGS (GS + 1)
152 #else /* ! __x86_64__ */
154 /* Mapping between the general-purpose registers in `struct user'
155 format and GDB's register array layout. */
156 static /*const*/ int i386_regmap
[] =
158 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
159 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
160 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
161 DS
* 4, ES
* 4, FS
* 4, GS
* 4
164 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
172 /* Returns true if the current inferior belongs to a x86-64 process,
176 is_64bit_tdesc (void)
178 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
180 return register_size (regcache
->tdesc
, 0) == 8;
186 /* Called by libthread_db. */
189 ps_get_thread_area (const struct ps_prochandle
*ph
,
190 lwpid_t lwpid
, int idx
, void **base
)
193 int use_64bit
= is_64bit_tdesc ();
200 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
204 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
215 unsigned int desc
[4];
217 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
218 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
221 /* Ensure we properly extend the value to 64-bits for x86_64. */
222 *base
= (void *) (uintptr_t) desc
[1];
227 /* Get the thread area address. This is used to recognize which
228 thread is which when tracing with the in-process agent library. We
229 don't read anything from the address, and treat it as opaque; it's
230 the address itself that we assume is unique per-thread. */
233 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
236 int use_64bit
= is_64bit_tdesc ();
241 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
243 *addr
= (CORE_ADDR
) (uintptr_t) base
;
252 struct lwp_info
*lwp
= find_lwp_pid (pid_to_ptid (lwpid
));
253 struct thread_info
*thr
= get_lwp_thread (lwp
);
254 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
255 unsigned int desc
[4];
257 const int reg_thread_area
= 3; /* bits to scale down register value. */
260 collect_register_by_name (regcache
, "gs", &gs
);
262 idx
= gs
>> reg_thread_area
;
264 if (ptrace (PTRACE_GET_THREAD_AREA
,
266 (void *) (long) idx
, (unsigned long) &desc
) < 0)
277 x86_cannot_store_register (int regno
)
280 if (is_64bit_tdesc ())
284 return regno
>= I386_NUM_REGS
;
288 x86_cannot_fetch_register (int regno
)
291 if (is_64bit_tdesc ())
295 return regno
>= I386_NUM_REGS
;
299 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
304 if (register_size (regcache
->tdesc
, 0) == 8)
306 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
307 if (x86_64_regmap
[i
] != -1)
308 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
312 /* 32-bit inferior registers need to be zero-extended.
313 Callers would read uninitialized memory otherwise. */
314 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
317 for (i
= 0; i
< I386_NUM_REGS
; i
++)
318 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
320 collect_register_by_name (regcache
, "orig_eax",
321 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
325 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
330 if (register_size (regcache
->tdesc
, 0) == 8)
332 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
333 if (x86_64_regmap
[i
] != -1)
334 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
339 for (i
= 0; i
< I386_NUM_REGS
; i
++)
340 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
342 supply_register_by_name (regcache
, "orig_eax",
343 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
347 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
350 i387_cache_to_fxsave (regcache
, buf
);
352 i387_cache_to_fsave (regcache
, buf
);
357 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
360 i387_fxsave_to_cache (regcache
, buf
);
362 i387_fsave_to_cache (regcache
, buf
);
369 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
371 i387_cache_to_fxsave (regcache
, buf
);
375 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
377 i387_fxsave_to_cache (regcache
, buf
);
383 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
385 i387_cache_to_xsave (regcache
, buf
);
389 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
391 i387_xsave_to_cache (regcache
, buf
);
394 /* ??? The non-biarch i386 case stores all the i387 regs twice.
395 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
396 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
397 doesn't work. IWBN to avoid the duplication in the case where it
398 does work. Maybe the arch_setup routine could check whether it works
399 and update the supported regsets accordingly. */
401 static struct regset_info x86_regsets
[] =
403 #ifdef HAVE_PTRACE_GETREGS
404 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
406 x86_fill_gregset
, x86_store_gregset
},
407 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
408 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
410 # ifdef HAVE_PTRACE_GETFPXREGS
411 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
413 x86_fill_fpxregset
, x86_store_fpxregset
},
416 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
418 x86_fill_fpregset
, x86_store_fpregset
},
419 #endif /* HAVE_PTRACE_GETREGS */
424 x86_get_pc (struct regcache
*regcache
)
426 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
431 collect_register_by_name (regcache
, "rip", &pc
);
432 return (CORE_ADDR
) pc
;
437 collect_register_by_name (regcache
, "eip", &pc
);
438 return (CORE_ADDR
) pc
;
443 x86_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
445 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
449 unsigned long newpc
= pc
;
450 supply_register_by_name (regcache
, "rip", &newpc
);
454 unsigned int newpc
= pc
;
455 supply_register_by_name (regcache
, "eip", &newpc
);
459 static const gdb_byte x86_breakpoint
[] = { 0xCC };
460 #define x86_breakpoint_len 1
463 x86_breakpoint_at (CORE_ADDR pc
)
467 (*the_target
->read_memory
) (pc
, &c
, 1);
474 /* Low-level function vector. */
475 struct x86_dr_low_type x86_dr_low
=
477 x86_linux_dr_set_control
,
478 x86_linux_dr_set_addr
,
479 x86_linux_dr_get_addr
,
480 x86_linux_dr_get_status
,
481 x86_linux_dr_get_control
,
485 /* Breakpoint/Watchpoint support. */
488 x86_supports_z_point_type (char z_type
)
494 case Z_PACKET_WRITE_WP
:
495 case Z_PACKET_ACCESS_WP
:
503 x86_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
504 int size
, struct raw_breakpoint
*bp
)
506 struct process_info
*proc
= current_process ();
510 case raw_bkpt_type_hw
:
511 case raw_bkpt_type_write_wp
:
512 case raw_bkpt_type_access_wp
:
514 enum target_hw_bp_type hw_type
515 = raw_bkpt_type_to_target_hw_bp_type (type
);
516 struct x86_debug_reg_state
*state
517 = &proc
->priv
->arch_private
->debug_reg_state
;
519 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
529 x86_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
530 int size
, struct raw_breakpoint
*bp
)
532 struct process_info
*proc
= current_process ();
536 case raw_bkpt_type_hw
:
537 case raw_bkpt_type_write_wp
:
538 case raw_bkpt_type_access_wp
:
540 enum target_hw_bp_type hw_type
541 = raw_bkpt_type_to_target_hw_bp_type (type
);
542 struct x86_debug_reg_state
*state
543 = &proc
->priv
->arch_private
->debug_reg_state
;
545 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
554 x86_stopped_by_watchpoint (void)
556 struct process_info
*proc
= current_process ();
557 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
561 x86_stopped_data_address (void)
563 struct process_info
*proc
= current_process ();
565 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
571 /* Called when a new process is created. */
573 static struct arch_process_info
*
574 x86_linux_new_process (void)
576 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
578 x86_low_init_dregs (&info
->debug_reg_state
);
583 /* Target routine for linux_new_fork. */
586 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
588 /* These are allocated by linux_add_process. */
589 gdb_assert (parent
->priv
!= NULL
590 && parent
->priv
->arch_private
!= NULL
);
591 gdb_assert (child
->priv
!= NULL
592 && child
->priv
->arch_private
!= NULL
);
594 /* Linux kernel before 2.6.33 commit
595 72f674d203cd230426437cdcf7dd6f681dad8b0d
596 will inherit hardware debug registers from parent
597 on fork/vfork/clone. Newer Linux kernels create such tasks with
598 zeroed debug registers.
600 GDB core assumes the child inherits the watchpoints/hw
601 breakpoints of the parent, and will remove them all from the
602 forked off process. Copy the debug registers mirrors into the
603 new process so that all breakpoints and watchpoints can be
604 removed together. The debug registers mirror will become zeroed
605 in the end before detaching the forked off process, thus making
606 this compatible with older Linux kernels too. */
608 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
611 /* See nat/x86-dregs.h. */
613 struct x86_debug_reg_state
*
614 x86_debug_reg_state (pid_t pid
)
616 struct process_info
*proc
= find_process_pid (pid
);
618 return &proc
->priv
->arch_private
->debug_reg_state
;
621 /* When GDBSERVER is built as a 64-bit application on linux, the
622 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
623 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
624 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
625 conversion in-place ourselves. */
627 /* Convert a native/host siginfo object, into/from the siginfo in the
628 layout of the inferiors' architecture. Returns true if any
629 conversion was done; false otherwise. If DIRECTION is 1, then copy
630 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
634 x86_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
, int direction
)
637 unsigned int machine
;
638 int tid
= lwpid_of (current_thread
);
639 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
641 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
642 if (!is_64bit_tdesc ())
643 return amd64_linux_siginfo_fixup_common (native
, inf
, direction
,
645 /* No fixup for native x32 GDB. */
646 else if (!is_elf64
&& sizeof (void *) == 8)
647 return amd64_linux_siginfo_fixup_common (native
, inf
, direction
,
656 /* Format of XSAVE extended state is:
660 sw_usable_bytes[464..511]
661 xstate_hdr_bytes[512..575]
666 Same memory layout will be used for the coredump NT_X86_XSTATE
667 representing the XSAVE extended state registers.
669 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
670 extended state mask, which is the same as the extended control register
671 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
672 together with the mask saved in the xstate_hdr_bytes to determine what
673 states the processor/OS supports and what state, used or initialized,
674 the process/thread is in. */
675 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
677 /* Does the current host support the GETFPXREGS request? The header
678 file may or may not define it, and even if it is defined, the
679 kernel will return EIO if it's running on a pre-SSE processor. */
680 int have_ptrace_getfpxregs
=
681 #ifdef HAVE_PTRACE_GETFPXREGS
688 /* Get Linux/x86 target description from running target. */
690 static const struct target_desc
*
691 x86_linux_read_description (void)
693 unsigned int machine
;
697 static uint64_t xcr0
;
698 struct regset_info
*regset
;
700 tid
= lwpid_of (current_thread
);
702 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
704 if (sizeof (void *) == 4)
707 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
709 else if (machine
== EM_X86_64
)
710 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
714 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
715 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
717 elf_fpxregset_t fpxregs
;
719 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
721 have_ptrace_getfpxregs
= 0;
722 have_ptrace_getregset
= 0;
723 return tdesc_i386_mmx_linux
;
726 have_ptrace_getfpxregs
= 1;
732 x86_xcr0
= X86_XSTATE_SSE_MASK
;
736 if (machine
== EM_X86_64
)
737 return tdesc_amd64_linux_no_xml
;
740 return tdesc_i386_linux_no_xml
;
743 if (have_ptrace_getregset
== -1)
745 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
748 iov
.iov_base
= xstateregs
;
749 iov
.iov_len
= sizeof (xstateregs
);
751 /* Check if PTRACE_GETREGSET works. */
752 if (ptrace (PTRACE_GETREGSET
, tid
,
753 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
754 have_ptrace_getregset
= 0;
757 have_ptrace_getregset
= 1;
759 /* Get XCR0 from XSAVE extended state. */
760 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
761 / sizeof (uint64_t))];
763 /* Use PTRACE_GETREGSET if it is available. */
764 for (regset
= x86_regsets
;
765 regset
->fill_function
!= NULL
; regset
++)
766 if (regset
->get_request
== PTRACE_GETREGSET
)
767 regset
->size
= X86_XSTATE_SIZE (xcr0
);
768 else if (regset
->type
!= GENERAL_REGS
)
773 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
774 xcr0_features
= (have_ptrace_getregset
775 && (xcr0
& X86_XSTATE_ALL_MASK
));
780 if (machine
== EM_X86_64
)
787 switch (xcr0
& X86_XSTATE_ALL_MASK
)
789 case X86_XSTATE_AVX512_MASK
:
790 return tdesc_amd64_avx512_linux
;
792 case X86_XSTATE_AVX_MPX_MASK
:
793 return tdesc_amd64_avx_mpx_linux
;
795 case X86_XSTATE_MPX_MASK
:
796 return tdesc_amd64_mpx_linux
;
798 case X86_XSTATE_AVX_MASK
:
799 return tdesc_amd64_avx_linux
;
802 return tdesc_amd64_linux
;
806 return tdesc_amd64_linux
;
812 switch (xcr0
& X86_XSTATE_ALL_MASK
)
814 case X86_XSTATE_AVX512_MASK
:
815 return tdesc_x32_avx512_linux
;
817 case X86_XSTATE_MPX_MASK
: /* No MPX on x32. */
818 case X86_XSTATE_AVX_MASK
:
819 return tdesc_x32_avx_linux
;
822 return tdesc_x32_linux
;
826 return tdesc_x32_linux
;
834 switch (xcr0
& X86_XSTATE_ALL_MASK
)
836 case (X86_XSTATE_AVX512_MASK
):
837 return tdesc_i386_avx512_linux
;
839 case (X86_XSTATE_MPX_MASK
):
840 return tdesc_i386_mpx_linux
;
842 case (X86_XSTATE_AVX_MPX_MASK
):
843 return tdesc_i386_avx_mpx_linux
;
845 case (X86_XSTATE_AVX_MASK
):
846 return tdesc_i386_avx_linux
;
849 return tdesc_i386_linux
;
853 return tdesc_i386_linux
;
856 gdb_assert_not_reached ("failed to return tdesc");
859 /* Callback for find_inferior. Stops iteration when a thread with a
860 given PID is found. */
863 same_process_callback (struct inferior_list_entry
*entry
, void *data
)
865 int pid
= *(int *) data
;
867 return (ptid_get_pid (entry
->id
) == pid
);
870 /* Callback for for_each_inferior. Calls the arch_setup routine for
874 x86_arch_setup_process_callback (struct inferior_list_entry
*entry
)
876 int pid
= ptid_get_pid (entry
->id
);
878 /* Look up any thread of this processes. */
880 = (struct thread_info
*) find_inferior (&all_threads
,
881 same_process_callback
, &pid
);
883 the_low_target
.arch_setup ();
886 /* Update all the target description of all processes; a new GDB
887 connected, and it may or not support xml target descriptions. */
890 x86_linux_update_xmltarget (void)
892 struct thread_info
*saved_thread
= current_thread
;
894 /* Before changing the register cache's internal layout, flush the
895 contents of the current valid caches back to the threads, and
896 release the current regcache objects. */
899 for_each_inferior (&all_processes
, x86_arch_setup_process_callback
);
901 current_thread
= saved_thread
;
904 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
908 x86_linux_process_qsupported (char **features
, int count
)
912 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
913 with "i386" in qSupported query, it supports x86 XML target
916 for (i
= 0; i
< count
; i
++)
918 const char *feature
= features
[i
];
920 if (startswith (feature
, "xmlRegisters="))
922 char *copy
= xstrdup (feature
+ 13);
925 for (p
= strtok (copy
, ","); p
!= NULL
; p
= strtok (NULL
, ","))
927 if (strcmp (p
, "i386") == 0)
937 x86_linux_update_xmltarget ();
940 /* Common for x86/x86-64. */
942 static struct regsets_info x86_regsets_info
=
944 x86_regsets
, /* regsets */
946 NULL
, /* disabled_regsets */
950 static struct regs_info amd64_linux_regs_info
=
952 NULL
, /* regset_bitmap */
953 NULL
, /* usrregs_info */
957 static struct usrregs_info i386_linux_usrregs_info
=
963 static struct regs_info i386_linux_regs_info
=
965 NULL
, /* regset_bitmap */
966 &i386_linux_usrregs_info
,
970 const struct regs_info
*
971 x86_linux_regs_info (void)
974 if (is_64bit_tdesc ())
975 return &amd64_linux_regs_info
;
978 return &i386_linux_regs_info
;
981 /* Initialize the target description for the architecture of the
985 x86_arch_setup (void)
987 current_process ()->tdesc
= x86_linux_read_description ();
990 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
991 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
994 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
, int *sysret
)
996 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1003 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1004 collect_register_by_name (regcache
, "rax", &l_sysret
);
1005 *sysno
= (int) l_sysno
;
1006 *sysret
= (int) l_sysret
;
1010 collect_register_by_name (regcache
, "orig_eax", sysno
);
1011 collect_register_by_name (regcache
, "eax", sysret
);
1016 x86_supports_tracepoints (void)
1022 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1024 write_inferior_memory (*to
, buf
, len
);
1029 push_opcode (unsigned char *buf
, char *op
)
1031 unsigned char *buf_org
= buf
;
1036 unsigned long ul
= strtoul (op
, &endptr
, 16);
1045 return buf
- buf_org
;
1050 /* Build a jump pad that saves registers and calls a collection
1051 function. Writes a jump instruction to the jump pad to
1052 JJUMPAD_INSN. The caller is responsible to write it in at the
1053 tracepoint address. */
1056 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1057 CORE_ADDR collector
,
1060 CORE_ADDR
*jump_entry
,
1061 CORE_ADDR
*trampoline
,
1062 ULONGEST
*trampoline_size
,
1063 unsigned char *jjump_pad_insn
,
1064 ULONGEST
*jjump_pad_insn_size
,
1065 CORE_ADDR
*adjusted_insn_addr
,
1066 CORE_ADDR
*adjusted_insn_addr_end
,
1069 unsigned char buf
[40];
1073 CORE_ADDR buildaddr
= *jump_entry
;
1075 /* Build the jump pad. */
1077 /* First, do tracepoint data collection. Save registers. */
1079 /* Need to ensure stack pointer saved first. */
1080 buf
[i
++] = 0x54; /* push %rsp */
1081 buf
[i
++] = 0x55; /* push %rbp */
1082 buf
[i
++] = 0x57; /* push %rdi */
1083 buf
[i
++] = 0x56; /* push %rsi */
1084 buf
[i
++] = 0x52; /* push %rdx */
1085 buf
[i
++] = 0x51; /* push %rcx */
1086 buf
[i
++] = 0x53; /* push %rbx */
1087 buf
[i
++] = 0x50; /* push %rax */
1088 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1089 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1090 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1091 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1092 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1093 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1094 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1095 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1096 buf
[i
++] = 0x9c; /* pushfq */
1097 buf
[i
++] = 0x48; /* movl <addr>,%rdi */
1099 *((unsigned long *)(buf
+ i
)) = (unsigned long) tpaddr
;
1100 i
+= sizeof (unsigned long);
1101 buf
[i
++] = 0x57; /* push %rdi */
1102 append_insns (&buildaddr
, i
, buf
);
1104 /* Stack space for the collecting_t object. */
1106 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1107 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1108 memcpy (buf
+ i
, &tpoint
, 8);
1110 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1111 i
+= push_opcode (&buf
[i
],
1112 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1113 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1114 append_insns (&buildaddr
, i
, buf
);
1118 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1119 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1121 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1122 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1123 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1124 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1125 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1126 append_insns (&buildaddr
, i
, buf
);
1128 /* Set up the gdb_collect call. */
1129 /* At this point, (stack pointer + 0x18) is the base of our saved
1133 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1134 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1136 /* tpoint address may be 64-bit wide. */
1137 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1138 memcpy (buf
+ i
, &tpoint
, 8);
1140 append_insns (&buildaddr
, i
, buf
);
1142 /* The collector function being in the shared library, may be
1143 >31-bits away off the jump pad. */
1145 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1146 memcpy (buf
+ i
, &collector
, 8);
1148 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1149 append_insns (&buildaddr
, i
, buf
);
1151 /* Clear the spin-lock. */
1153 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1154 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1155 memcpy (buf
+ i
, &lockaddr
, 8);
1157 append_insns (&buildaddr
, i
, buf
);
1159 /* Remove stack that had been used for the collect_t object. */
1161 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1162 append_insns (&buildaddr
, i
, buf
);
1164 /* Restore register state. */
1166 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1170 buf
[i
++] = 0x9d; /* popfq */
1171 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1172 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1173 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1174 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1175 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1176 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1177 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1178 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1179 buf
[i
++] = 0x58; /* pop %rax */
1180 buf
[i
++] = 0x5b; /* pop %rbx */
1181 buf
[i
++] = 0x59; /* pop %rcx */
1182 buf
[i
++] = 0x5a; /* pop %rdx */
1183 buf
[i
++] = 0x5e; /* pop %rsi */
1184 buf
[i
++] = 0x5f; /* pop %rdi */
1185 buf
[i
++] = 0x5d; /* pop %rbp */
1186 buf
[i
++] = 0x5c; /* pop %rsp */
1187 append_insns (&buildaddr
, i
, buf
);
1189 /* Now, adjust the original instruction to execute in the jump
1191 *adjusted_insn_addr
= buildaddr
;
1192 relocate_instruction (&buildaddr
, tpaddr
);
1193 *adjusted_insn_addr_end
= buildaddr
;
1195 /* Finally, write a jump back to the program. */
1197 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1198 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1201 "E.Jump back from jump pad too far from tracepoint "
1202 "(offset 0x%" PRIx64
" > int32).", loffset
);
1206 offset
= (int) loffset
;
1207 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1208 memcpy (buf
+ 1, &offset
, 4);
1209 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1211 /* The jump pad is now built. Wire in a jump to our jump pad. This
1212 is always done last (by our caller actually), so that we can
1213 install fast tracepoints with threads running. This relies on
1214 the agent's atomic write support. */
1215 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1216 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1219 "E.Jump pad too far from tracepoint "
1220 "(offset 0x%" PRIx64
" > int32).", loffset
);
1224 offset
= (int) loffset
;
1226 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1227 memcpy (buf
+ 1, &offset
, 4);
1228 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1229 *jjump_pad_insn_size
= sizeof (jump_insn
);
1231 /* Return the end address of our pad. */
1232 *jump_entry
= buildaddr
;
1237 #endif /* __x86_64__ */
1239 /* Build a jump pad that saves registers and calls a collection
1240 function. Writes a jump instruction to the jump pad to
1241 JJUMPAD_INSN. The caller is responsible to write it in at the
1242 tracepoint address. */
1245 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1246 CORE_ADDR collector
,
1249 CORE_ADDR
*jump_entry
,
1250 CORE_ADDR
*trampoline
,
1251 ULONGEST
*trampoline_size
,
1252 unsigned char *jjump_pad_insn
,
1253 ULONGEST
*jjump_pad_insn_size
,
1254 CORE_ADDR
*adjusted_insn_addr
,
1255 CORE_ADDR
*adjusted_insn_addr_end
,
1258 unsigned char buf
[0x100];
1260 CORE_ADDR buildaddr
= *jump_entry
;
1262 /* Build the jump pad. */
1264 /* First, do tracepoint data collection. Save registers. */
1266 buf
[i
++] = 0x60; /* pushad */
1267 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1268 *((int *)(buf
+ i
)) = (int) tpaddr
;
1270 buf
[i
++] = 0x9c; /* pushf */
1271 buf
[i
++] = 0x1e; /* push %ds */
1272 buf
[i
++] = 0x06; /* push %es */
1273 buf
[i
++] = 0x0f; /* push %fs */
1275 buf
[i
++] = 0x0f; /* push %gs */
1277 buf
[i
++] = 0x16; /* push %ss */
1278 buf
[i
++] = 0x0e; /* push %cs */
1279 append_insns (&buildaddr
, i
, buf
);
1281 /* Stack space for the collecting_t object. */
1283 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1285 /* Build the object. */
1286 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1287 memcpy (buf
+ i
, &tpoint
, 4);
1289 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1291 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1292 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1293 append_insns (&buildaddr
, i
, buf
);
1295 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1296 If we cared for it, this could be using xchg alternatively. */
1299 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1300 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1302 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1304 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1305 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1306 append_insns (&buildaddr
, i
, buf
);
1309 /* Set up arguments to the gdb_collect call. */
1311 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1312 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1313 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1314 append_insns (&buildaddr
, i
, buf
);
1317 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1318 append_insns (&buildaddr
, i
, buf
);
1321 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1322 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1324 append_insns (&buildaddr
, i
, buf
);
1326 buf
[0] = 0xe8; /* call <reladdr> */
1327 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1328 memcpy (buf
+ 1, &offset
, 4);
1329 append_insns (&buildaddr
, 5, buf
);
1330 /* Clean up after the call. */
1331 buf
[0] = 0x83; /* add $0x8,%esp */
1334 append_insns (&buildaddr
, 3, buf
);
1337 /* Clear the spin-lock. This would need the LOCK prefix on older
1340 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1341 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1342 memcpy (buf
+ i
, &lockaddr
, 4);
1344 append_insns (&buildaddr
, i
, buf
);
1347 /* Remove stack that had been used for the collect_t object. */
1349 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1350 append_insns (&buildaddr
, i
, buf
);
1353 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1356 buf
[i
++] = 0x17; /* pop %ss */
1357 buf
[i
++] = 0x0f; /* pop %gs */
1359 buf
[i
++] = 0x0f; /* pop %fs */
1361 buf
[i
++] = 0x07; /* pop %es */
1362 buf
[i
++] = 0x1f; /* pop %ds */
1363 buf
[i
++] = 0x9d; /* popf */
1364 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1367 buf
[i
++] = 0x61; /* popad */
1368 append_insns (&buildaddr
, i
, buf
);
1370 /* Now, adjust the original instruction to execute in the jump
1372 *adjusted_insn_addr
= buildaddr
;
1373 relocate_instruction (&buildaddr
, tpaddr
);
1374 *adjusted_insn_addr_end
= buildaddr
;
1376 /* Write the jump back to the program. */
1377 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1378 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1379 memcpy (buf
+ 1, &offset
, 4);
1380 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1382 /* The jump pad is now built. Wire in a jump to our jump pad. This
1383 is always done last (by our caller actually), so that we can
1384 install fast tracepoints with threads running. This relies on
1385 the agent's atomic write support. */
1388 /* Create a trampoline. */
1389 *trampoline_size
= sizeof (jump_insn
);
1390 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1392 /* No trampoline space available. */
1394 "E.Cannot allocate trampoline space needed for fast "
1395 "tracepoints on 4-byte instructions.");
1399 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1400 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1401 memcpy (buf
+ 1, &offset
, 4);
1402 write_inferior_memory (*trampoline
, buf
, sizeof (jump_insn
));
1404 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1405 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1406 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1407 memcpy (buf
+ 2, &offset
, 2);
1408 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1409 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1413 /* Else use a 32-bit relative jump instruction. */
1414 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1415 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1416 memcpy (buf
+ 1, &offset
, 4);
1417 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1418 *jjump_pad_insn_size
= sizeof (jump_insn
);
1421 /* Return the end address of our pad. */
1422 *jump_entry
= buildaddr
;
1428 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1429 CORE_ADDR collector
,
1432 CORE_ADDR
*jump_entry
,
1433 CORE_ADDR
*trampoline
,
1434 ULONGEST
*trampoline_size
,
1435 unsigned char *jjump_pad_insn
,
1436 ULONGEST
*jjump_pad_insn_size
,
1437 CORE_ADDR
*adjusted_insn_addr
,
1438 CORE_ADDR
*adjusted_insn_addr_end
,
1442 if (is_64bit_tdesc ())
1443 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1444 collector
, lockaddr
,
1445 orig_size
, jump_entry
,
1446 trampoline
, trampoline_size
,
1448 jjump_pad_insn_size
,
1450 adjusted_insn_addr_end
,
1454 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1455 collector
, lockaddr
,
1456 orig_size
, jump_entry
,
1457 trampoline
, trampoline_size
,
1459 jjump_pad_insn_size
,
1461 adjusted_insn_addr_end
,
1465 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1469 x86_get_min_fast_tracepoint_insn_len (void)
1471 static int warned_about_fast_tracepoints
= 0;
1474 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1475 used for fast tracepoints. */
1476 if (is_64bit_tdesc ())
1480 if (agent_loaded_p ())
1482 char errbuf
[IPA_BUFSIZ
];
1486 /* On x86, if trampolines are available, then 4-byte jump instructions
1487 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1488 with a 4-byte offset are used instead. */
1489 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1493 /* GDB has no channel to explain to user why a shorter fast
1494 tracepoint is not possible, but at least make GDBserver
1495 mention that something has gone awry. */
1496 if (!warned_about_fast_tracepoints
)
1498 warning ("4-byte fast tracepoints not available; %s\n", errbuf
);
1499 warned_about_fast_tracepoints
= 1;
1506 /* Indicate that the minimum length is currently unknown since the IPA
1507 has not loaded yet. */
1513 add_insns (unsigned char *start
, int len
)
1515 CORE_ADDR buildaddr
= current_insn_ptr
;
1518 debug_printf ("Adding %d bytes of insn at %s\n",
1519 len
, paddress (buildaddr
));
1521 append_insns (&buildaddr
, len
, start
);
1522 current_insn_ptr
= buildaddr
;
1525 /* Our general strategy for emitting code is to avoid specifying raw
1526 bytes whenever possible, and instead copy a block of inline asm
1527 that is embedded in the function. This is a little messy, because
1528 we need to keep the compiler from discarding what looks like dead
1529 code, plus suppress various warnings. */
1531 #define EMIT_ASM(NAME, INSNS) \
1534 extern unsigned char start_ ## NAME, end_ ## NAME; \
1535 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1536 __asm__ ("jmp end_" #NAME "\n" \
1537 "\t" "start_" #NAME ":" \
1539 "\t" "end_" #NAME ":"); \
1544 #define EMIT_ASM32(NAME,INSNS) \
1547 extern unsigned char start_ ## NAME, end_ ## NAME; \
1548 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1549 __asm__ (".code32\n" \
1550 "\t" "jmp end_" #NAME "\n" \
1551 "\t" "start_" #NAME ":\n" \
1553 "\t" "end_" #NAME ":\n" \
1559 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1566 amd64_emit_prologue (void)
1568 EMIT_ASM (amd64_prologue
,
1570 "movq %rsp,%rbp\n\t"
1571 "sub $0x20,%rsp\n\t"
1572 "movq %rdi,-8(%rbp)\n\t"
1573 "movq %rsi,-16(%rbp)");
1578 amd64_emit_epilogue (void)
1580 EMIT_ASM (amd64_epilogue
,
1581 "movq -16(%rbp),%rdi\n\t"
1582 "movq %rax,(%rdi)\n\t"
1589 amd64_emit_add (void)
1591 EMIT_ASM (amd64_add
,
1592 "add (%rsp),%rax\n\t"
1593 "lea 0x8(%rsp),%rsp");
1597 amd64_emit_sub (void)
1599 EMIT_ASM (amd64_sub
,
1600 "sub %rax,(%rsp)\n\t"
1605 amd64_emit_mul (void)
1611 amd64_emit_lsh (void)
1617 amd64_emit_rsh_signed (void)
1623 amd64_emit_rsh_unsigned (void)
1629 amd64_emit_ext (int arg
)
1634 EMIT_ASM (amd64_ext_8
,
1640 EMIT_ASM (amd64_ext_16
,
1645 EMIT_ASM (amd64_ext_32
,
1654 amd64_emit_log_not (void)
1656 EMIT_ASM (amd64_log_not
,
1657 "test %rax,%rax\n\t"
1663 amd64_emit_bit_and (void)
1665 EMIT_ASM (amd64_and
,
1666 "and (%rsp),%rax\n\t"
1667 "lea 0x8(%rsp),%rsp");
1671 amd64_emit_bit_or (void)
1674 "or (%rsp),%rax\n\t"
1675 "lea 0x8(%rsp),%rsp");
1679 amd64_emit_bit_xor (void)
1681 EMIT_ASM (amd64_xor
,
1682 "xor (%rsp),%rax\n\t"
1683 "lea 0x8(%rsp),%rsp");
1687 amd64_emit_bit_not (void)
1689 EMIT_ASM (amd64_bit_not
,
1690 "xorq $0xffffffffffffffff,%rax");
1694 amd64_emit_equal (void)
1696 EMIT_ASM (amd64_equal
,
1697 "cmp %rax,(%rsp)\n\t"
1698 "je .Lamd64_equal_true\n\t"
1700 "jmp .Lamd64_equal_end\n\t"
1701 ".Lamd64_equal_true:\n\t"
1703 ".Lamd64_equal_end:\n\t"
1704 "lea 0x8(%rsp),%rsp");
1708 amd64_emit_less_signed (void)
1710 EMIT_ASM (amd64_less_signed
,
1711 "cmp %rax,(%rsp)\n\t"
1712 "jl .Lamd64_less_signed_true\n\t"
1714 "jmp .Lamd64_less_signed_end\n\t"
1715 ".Lamd64_less_signed_true:\n\t"
1717 ".Lamd64_less_signed_end:\n\t"
1718 "lea 0x8(%rsp),%rsp");
1722 amd64_emit_less_unsigned (void)
1724 EMIT_ASM (amd64_less_unsigned
,
1725 "cmp %rax,(%rsp)\n\t"
1726 "jb .Lamd64_less_unsigned_true\n\t"
1728 "jmp .Lamd64_less_unsigned_end\n\t"
1729 ".Lamd64_less_unsigned_true:\n\t"
1731 ".Lamd64_less_unsigned_end:\n\t"
1732 "lea 0x8(%rsp),%rsp");
1736 amd64_emit_ref (int size
)
1741 EMIT_ASM (amd64_ref1
,
1745 EMIT_ASM (amd64_ref2
,
1749 EMIT_ASM (amd64_ref4
,
1750 "movl (%rax),%eax");
1753 EMIT_ASM (amd64_ref8
,
1754 "movq (%rax),%rax");
1760 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1762 EMIT_ASM (amd64_if_goto
,
1766 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1774 amd64_emit_goto (int *offset_p
, int *size_p
)
1776 EMIT_ASM (amd64_goto
,
1777 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1785 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1787 int diff
= (to
- (from
+ size
));
1788 unsigned char buf
[sizeof (int)];
1796 memcpy (buf
, &diff
, sizeof (int));
1797 write_inferior_memory (from
, buf
, sizeof (int));
1801 amd64_emit_const (LONGEST num
)
1803 unsigned char buf
[16];
1805 CORE_ADDR buildaddr
= current_insn_ptr
;
1808 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1809 memcpy (&buf
[i
], &num
, sizeof (num
));
1811 append_insns (&buildaddr
, i
, buf
);
1812 current_insn_ptr
= buildaddr
;
1816 amd64_emit_call (CORE_ADDR fn
)
1818 unsigned char buf
[16];
1820 CORE_ADDR buildaddr
;
1823 /* The destination function being in the shared library, may be
1824 >31-bits away off the compiled code pad. */
1826 buildaddr
= current_insn_ptr
;
1828 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1832 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1834 /* Offset is too large for a call. Use callq, but that requires
1835 a register, so avoid it if possible. Use r10, since it is
1836 call-clobbered, we don't have to push/pop it. */
1837 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1839 memcpy (buf
+ i
, &fn
, 8);
1841 buf
[i
++] = 0xff; /* callq *%r10 */
1846 int offset32
= offset64
; /* we know we can't overflow here. */
1847 memcpy (buf
+ i
, &offset32
, 4);
1851 append_insns (&buildaddr
, i
, buf
);
1852 current_insn_ptr
= buildaddr
;
1856 amd64_emit_reg (int reg
)
1858 unsigned char buf
[16];
1860 CORE_ADDR buildaddr
;
1862 /* Assume raw_regs is still in %rdi. */
1863 buildaddr
= current_insn_ptr
;
1865 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1866 memcpy (&buf
[i
], ®
, sizeof (reg
));
1868 append_insns (&buildaddr
, i
, buf
);
1869 current_insn_ptr
= buildaddr
;
1870 amd64_emit_call (get_raw_reg_func_addr ());
1874 amd64_emit_pop (void)
1876 EMIT_ASM (amd64_pop
,
1881 amd64_emit_stack_flush (void)
1883 EMIT_ASM (amd64_stack_flush
,
1888 amd64_emit_zero_ext (int arg
)
1893 EMIT_ASM (amd64_zero_ext_8
,
1897 EMIT_ASM (amd64_zero_ext_16
,
1898 "and $0xffff,%rax");
1901 EMIT_ASM (amd64_zero_ext_32
,
1902 "mov $0xffffffff,%rcx\n\t"
1911 amd64_emit_swap (void)
1913 EMIT_ASM (amd64_swap
,
1920 amd64_emit_stack_adjust (int n
)
1922 unsigned char buf
[16];
1924 CORE_ADDR buildaddr
= current_insn_ptr
;
1927 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1931 /* This only handles adjustments up to 16, but we don't expect any more. */
1933 append_insns (&buildaddr
, i
, buf
);
1934 current_insn_ptr
= buildaddr
;
1937 /* FN's prototype is `LONGEST(*fn)(int)'. */
1940 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1942 unsigned char buf
[16];
1944 CORE_ADDR buildaddr
;
1946 buildaddr
= current_insn_ptr
;
1948 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1949 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1951 append_insns (&buildaddr
, i
, buf
);
1952 current_insn_ptr
= buildaddr
;
1953 amd64_emit_call (fn
);
1956 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
1959 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
1961 unsigned char buf
[16];
1963 CORE_ADDR buildaddr
;
1965 buildaddr
= current_insn_ptr
;
1967 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1968 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1970 append_insns (&buildaddr
, i
, buf
);
1971 current_insn_ptr
= buildaddr
;
1972 EMIT_ASM (amd64_void_call_2_a
,
1973 /* Save away a copy of the stack top. */
1975 /* Also pass top as the second argument. */
1977 amd64_emit_call (fn
);
1978 EMIT_ASM (amd64_void_call_2_b
,
1979 /* Restore the stack top, %rax may have been trashed. */
1984 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
1987 "cmp %rax,(%rsp)\n\t"
1988 "jne .Lamd64_eq_fallthru\n\t"
1989 "lea 0x8(%rsp),%rsp\n\t"
1991 /* jmp, but don't trust the assembler to choose the right jump */
1992 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
1993 ".Lamd64_eq_fallthru:\n\t"
1994 "lea 0x8(%rsp),%rsp\n\t"
2004 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2007 "cmp %rax,(%rsp)\n\t"
2008 "je .Lamd64_ne_fallthru\n\t"
2009 "lea 0x8(%rsp),%rsp\n\t"
2011 /* jmp, but don't trust the assembler to choose the right jump */
2012 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2013 ".Lamd64_ne_fallthru:\n\t"
2014 "lea 0x8(%rsp),%rsp\n\t"
2024 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2027 "cmp %rax,(%rsp)\n\t"
2028 "jnl .Lamd64_lt_fallthru\n\t"
2029 "lea 0x8(%rsp),%rsp\n\t"
2031 /* jmp, but don't trust the assembler to choose the right jump */
2032 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2033 ".Lamd64_lt_fallthru:\n\t"
2034 "lea 0x8(%rsp),%rsp\n\t"
2044 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2047 "cmp %rax,(%rsp)\n\t"
2048 "jnle .Lamd64_le_fallthru\n\t"
2049 "lea 0x8(%rsp),%rsp\n\t"
2051 /* jmp, but don't trust the assembler to choose the right jump */
2052 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2053 ".Lamd64_le_fallthru:\n\t"
2054 "lea 0x8(%rsp),%rsp\n\t"
2064 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2067 "cmp %rax,(%rsp)\n\t"
2068 "jng .Lamd64_gt_fallthru\n\t"
2069 "lea 0x8(%rsp),%rsp\n\t"
2071 /* jmp, but don't trust the assembler to choose the right jump */
2072 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2073 ".Lamd64_gt_fallthru:\n\t"
2074 "lea 0x8(%rsp),%rsp\n\t"
2084 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2087 "cmp %rax,(%rsp)\n\t"
2088 "jnge .Lamd64_ge_fallthru\n\t"
2089 ".Lamd64_ge_jump:\n\t"
2090 "lea 0x8(%rsp),%rsp\n\t"
2092 /* jmp, but don't trust the assembler to choose the right jump */
2093 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2094 ".Lamd64_ge_fallthru:\n\t"
2095 "lea 0x8(%rsp),%rsp\n\t"
2104 struct emit_ops amd64_emit_ops
=
2106 amd64_emit_prologue
,
2107 amd64_emit_epilogue
,
2112 amd64_emit_rsh_signed
,
2113 amd64_emit_rsh_unsigned
,
2121 amd64_emit_less_signed
,
2122 amd64_emit_less_unsigned
,
2126 amd64_write_goto_address
,
2131 amd64_emit_stack_flush
,
2132 amd64_emit_zero_ext
,
2134 amd64_emit_stack_adjust
,
2135 amd64_emit_int_call_1
,
2136 amd64_emit_void_call_2
,
2145 #endif /* __x86_64__ */
2148 i386_emit_prologue (void)
2150 EMIT_ASM32 (i386_prologue
,
2154 /* At this point, the raw regs base address is at 8(%ebp), and the
2155 value pointer is at 12(%ebp). */
2159 i386_emit_epilogue (void)
2161 EMIT_ASM32 (i386_epilogue
,
2162 "mov 12(%ebp),%ecx\n\t"
2163 "mov %eax,(%ecx)\n\t"
2164 "mov %ebx,0x4(%ecx)\n\t"
2172 i386_emit_add (void)
2174 EMIT_ASM32 (i386_add
,
2175 "add (%esp),%eax\n\t"
2176 "adc 0x4(%esp),%ebx\n\t"
2177 "lea 0x8(%esp),%esp");
2181 i386_emit_sub (void)
2183 EMIT_ASM32 (i386_sub
,
2184 "subl %eax,(%esp)\n\t"
2185 "sbbl %ebx,4(%esp)\n\t"
2191 i386_emit_mul (void)
2197 i386_emit_lsh (void)
2203 i386_emit_rsh_signed (void)
2209 i386_emit_rsh_unsigned (void)
2215 i386_emit_ext (int arg
)
2220 EMIT_ASM32 (i386_ext_8
,
2223 "movl %eax,%ebx\n\t"
2227 EMIT_ASM32 (i386_ext_16
,
2229 "movl %eax,%ebx\n\t"
2233 EMIT_ASM32 (i386_ext_32
,
2234 "movl %eax,%ebx\n\t"
2243 i386_emit_log_not (void)
2245 EMIT_ASM32 (i386_log_not
,
2247 "test %eax,%eax\n\t"
2254 i386_emit_bit_and (void)
2256 EMIT_ASM32 (i386_and
,
2257 "and (%esp),%eax\n\t"
2258 "and 0x4(%esp),%ebx\n\t"
2259 "lea 0x8(%esp),%esp");
2263 i386_emit_bit_or (void)
2265 EMIT_ASM32 (i386_or
,
2266 "or (%esp),%eax\n\t"
2267 "or 0x4(%esp),%ebx\n\t"
2268 "lea 0x8(%esp),%esp");
2272 i386_emit_bit_xor (void)
2274 EMIT_ASM32 (i386_xor
,
2275 "xor (%esp),%eax\n\t"
2276 "xor 0x4(%esp),%ebx\n\t"
2277 "lea 0x8(%esp),%esp");
2281 i386_emit_bit_not (void)
2283 EMIT_ASM32 (i386_bit_not
,
2284 "xor $0xffffffff,%eax\n\t"
2285 "xor $0xffffffff,%ebx\n\t");
2289 i386_emit_equal (void)
2291 EMIT_ASM32 (i386_equal
,
2292 "cmpl %ebx,4(%esp)\n\t"
2293 "jne .Li386_equal_false\n\t"
2294 "cmpl %eax,(%esp)\n\t"
2295 "je .Li386_equal_true\n\t"
2296 ".Li386_equal_false:\n\t"
2298 "jmp .Li386_equal_end\n\t"
2299 ".Li386_equal_true:\n\t"
2301 ".Li386_equal_end:\n\t"
2303 "lea 0x8(%esp),%esp");
2307 i386_emit_less_signed (void)
2309 EMIT_ASM32 (i386_less_signed
,
2310 "cmpl %ebx,4(%esp)\n\t"
2311 "jl .Li386_less_signed_true\n\t"
2312 "jne .Li386_less_signed_false\n\t"
2313 "cmpl %eax,(%esp)\n\t"
2314 "jl .Li386_less_signed_true\n\t"
2315 ".Li386_less_signed_false:\n\t"
2317 "jmp .Li386_less_signed_end\n\t"
2318 ".Li386_less_signed_true:\n\t"
2320 ".Li386_less_signed_end:\n\t"
2322 "lea 0x8(%esp),%esp");
2326 i386_emit_less_unsigned (void)
2328 EMIT_ASM32 (i386_less_unsigned
,
2329 "cmpl %ebx,4(%esp)\n\t"
2330 "jb .Li386_less_unsigned_true\n\t"
2331 "jne .Li386_less_unsigned_false\n\t"
2332 "cmpl %eax,(%esp)\n\t"
2333 "jb .Li386_less_unsigned_true\n\t"
2334 ".Li386_less_unsigned_false:\n\t"
2336 "jmp .Li386_less_unsigned_end\n\t"
2337 ".Li386_less_unsigned_true:\n\t"
2339 ".Li386_less_unsigned_end:\n\t"
2341 "lea 0x8(%esp),%esp");
2345 i386_emit_ref (int size
)
2350 EMIT_ASM32 (i386_ref1
,
2354 EMIT_ASM32 (i386_ref2
,
2358 EMIT_ASM32 (i386_ref4
,
2359 "movl (%eax),%eax");
2362 EMIT_ASM32 (i386_ref8
,
2363 "movl 4(%eax),%ebx\n\t"
2364 "movl (%eax),%eax");
2370 i386_emit_if_goto (int *offset_p
, int *size_p
)
2372 EMIT_ASM32 (i386_if_goto
,
2378 /* Don't trust the assembler to choose the right jump */
2379 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2382 *offset_p
= 11; /* be sure that this matches the sequence above */
2388 i386_emit_goto (int *offset_p
, int *size_p
)
2390 EMIT_ASM32 (i386_goto
,
2391 /* Don't trust the assembler to choose the right jump */
2392 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2400 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2402 int diff
= (to
- (from
+ size
));
2403 unsigned char buf
[sizeof (int)];
2405 /* We're only doing 4-byte sizes at the moment. */
2412 memcpy (buf
, &diff
, sizeof (int));
2413 write_inferior_memory (from
, buf
, sizeof (int));
2417 i386_emit_const (LONGEST num
)
2419 unsigned char buf
[16];
2421 CORE_ADDR buildaddr
= current_insn_ptr
;
2424 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2425 lo
= num
& 0xffffffff;
2426 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2428 hi
= ((num
>> 32) & 0xffffffff);
2431 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2432 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2437 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2439 append_insns (&buildaddr
, i
, buf
);
2440 current_insn_ptr
= buildaddr
;
2444 i386_emit_call (CORE_ADDR fn
)
2446 unsigned char buf
[16];
2448 CORE_ADDR buildaddr
;
2450 buildaddr
= current_insn_ptr
;
2452 buf
[i
++] = 0xe8; /* call <reladdr> */
2453 offset
= ((int) fn
) - (buildaddr
+ 5);
2454 memcpy (buf
+ 1, &offset
, 4);
2455 append_insns (&buildaddr
, 5, buf
);
2456 current_insn_ptr
= buildaddr
;
2460 i386_emit_reg (int reg
)
2462 unsigned char buf
[16];
2464 CORE_ADDR buildaddr
;
2466 EMIT_ASM32 (i386_reg_a
,
2468 buildaddr
= current_insn_ptr
;
2470 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2471 memcpy (&buf
[i
], ®
, sizeof (reg
));
2473 append_insns (&buildaddr
, i
, buf
);
2474 current_insn_ptr
= buildaddr
;
2475 EMIT_ASM32 (i386_reg_b
,
2476 "mov %eax,4(%esp)\n\t"
2477 "mov 8(%ebp),%eax\n\t"
2479 i386_emit_call (get_raw_reg_func_addr ());
2480 EMIT_ASM32 (i386_reg_c
,
2482 "lea 0x8(%esp),%esp");
2486 i386_emit_pop (void)
2488 EMIT_ASM32 (i386_pop
,
2494 i386_emit_stack_flush (void)
2496 EMIT_ASM32 (i386_stack_flush
,
2502 i386_emit_zero_ext (int arg
)
2507 EMIT_ASM32 (i386_zero_ext_8
,
2508 "and $0xff,%eax\n\t"
2512 EMIT_ASM32 (i386_zero_ext_16
,
2513 "and $0xffff,%eax\n\t"
2517 EMIT_ASM32 (i386_zero_ext_32
,
2526 i386_emit_swap (void)
2528 EMIT_ASM32 (i386_swap
,
2538 i386_emit_stack_adjust (int n
)
2540 unsigned char buf
[16];
2542 CORE_ADDR buildaddr
= current_insn_ptr
;
2545 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2549 append_insns (&buildaddr
, i
, buf
);
2550 current_insn_ptr
= buildaddr
;
2553 /* FN's prototype is `LONGEST(*fn)(int)'. */
2556 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2558 unsigned char buf
[16];
2560 CORE_ADDR buildaddr
;
2562 EMIT_ASM32 (i386_int_call_1_a
,
2563 /* Reserve a bit of stack space. */
2565 /* Put the one argument on the stack. */
2566 buildaddr
= current_insn_ptr
;
2568 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2571 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2573 append_insns (&buildaddr
, i
, buf
);
2574 current_insn_ptr
= buildaddr
;
2575 i386_emit_call (fn
);
2576 EMIT_ASM32 (i386_int_call_1_c
,
2578 "lea 0x8(%esp),%esp");
2581 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2584 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2586 unsigned char buf
[16];
2588 CORE_ADDR buildaddr
;
2590 EMIT_ASM32 (i386_void_call_2_a
,
2591 /* Preserve %eax only; we don't have to worry about %ebx. */
2593 /* Reserve a bit of stack space for arguments. */
2594 "sub $0x10,%esp\n\t"
2595 /* Copy "top" to the second argument position. (Note that
2596 we can't assume function won't scribble on its
2597 arguments, so don't try to restore from this.) */
2598 "mov %eax,4(%esp)\n\t"
2599 "mov %ebx,8(%esp)");
2600 /* Put the first argument on the stack. */
2601 buildaddr
= current_insn_ptr
;
2603 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2606 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2608 append_insns (&buildaddr
, i
, buf
);
2609 current_insn_ptr
= buildaddr
;
2610 i386_emit_call (fn
);
2611 EMIT_ASM32 (i386_void_call_2_b
,
2612 "lea 0x10(%esp),%esp\n\t"
2613 /* Restore original stack top. */
2619 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2622 /* Check low half first, more likely to be decider */
2623 "cmpl %eax,(%esp)\n\t"
2624 "jne .Leq_fallthru\n\t"
2625 "cmpl %ebx,4(%esp)\n\t"
2626 "jne .Leq_fallthru\n\t"
2627 "lea 0x8(%esp),%esp\n\t"
2630 /* jmp, but don't trust the assembler to choose the right jump */
2631 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2632 ".Leq_fallthru:\n\t"
2633 "lea 0x8(%esp),%esp\n\t"
2644 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2647 /* Check low half first, more likely to be decider */
2648 "cmpl %eax,(%esp)\n\t"
2650 "cmpl %ebx,4(%esp)\n\t"
2651 "je .Lne_fallthru\n\t"
2653 "lea 0x8(%esp),%esp\n\t"
2656 /* jmp, but don't trust the assembler to choose the right jump */
2657 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2658 ".Lne_fallthru:\n\t"
2659 "lea 0x8(%esp),%esp\n\t"
2670 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2673 "cmpl %ebx,4(%esp)\n\t"
2675 "jne .Llt_fallthru\n\t"
2676 "cmpl %eax,(%esp)\n\t"
2677 "jnl .Llt_fallthru\n\t"
2679 "lea 0x8(%esp),%esp\n\t"
2682 /* jmp, but don't trust the assembler to choose the right jump */
2683 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2684 ".Llt_fallthru:\n\t"
2685 "lea 0x8(%esp),%esp\n\t"
2696 i386_emit_le_goto (int *offset_p
, int *size_p
)
2699 "cmpl %ebx,4(%esp)\n\t"
2701 "jne .Lle_fallthru\n\t"
2702 "cmpl %eax,(%esp)\n\t"
2703 "jnle .Lle_fallthru\n\t"
2705 "lea 0x8(%esp),%esp\n\t"
2708 /* jmp, but don't trust the assembler to choose the right jump */
2709 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2710 ".Lle_fallthru:\n\t"
2711 "lea 0x8(%esp),%esp\n\t"
2722 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2725 "cmpl %ebx,4(%esp)\n\t"
2727 "jne .Lgt_fallthru\n\t"
2728 "cmpl %eax,(%esp)\n\t"
2729 "jng .Lgt_fallthru\n\t"
2731 "lea 0x8(%esp),%esp\n\t"
2734 /* jmp, but don't trust the assembler to choose the right jump */
2735 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2736 ".Lgt_fallthru:\n\t"
2737 "lea 0x8(%esp),%esp\n\t"
2748 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2751 "cmpl %ebx,4(%esp)\n\t"
2753 "jne .Lge_fallthru\n\t"
2754 "cmpl %eax,(%esp)\n\t"
2755 "jnge .Lge_fallthru\n\t"
2757 "lea 0x8(%esp),%esp\n\t"
2760 /* jmp, but don't trust the assembler to choose the right jump */
2761 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2762 ".Lge_fallthru:\n\t"
2763 "lea 0x8(%esp),%esp\n\t"
2773 struct emit_ops i386_emit_ops
=
2781 i386_emit_rsh_signed
,
2782 i386_emit_rsh_unsigned
,
2790 i386_emit_less_signed
,
2791 i386_emit_less_unsigned
,
2795 i386_write_goto_address
,
2800 i386_emit_stack_flush
,
2803 i386_emit_stack_adjust
,
2804 i386_emit_int_call_1
,
2805 i386_emit_void_call_2
,
2815 static struct emit_ops
*
2819 if (is_64bit_tdesc ())
2820 return &amd64_emit_ops
;
2823 return &i386_emit_ops
;
2826 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2828 static const gdb_byte
*
2829 x86_sw_breakpoint_from_kind (int kind
, int *size
)
2831 *size
= x86_breakpoint_len
;
2832 return x86_breakpoint
;
2836 x86_supports_range_stepping (void)
2841 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2845 x86_supports_hardware_single_step (void)
2851 x86_get_ipa_tdesc_idx (void)
2853 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2854 const struct target_desc
*tdesc
= regcache
->tdesc
;
2857 if (tdesc
== tdesc_amd64_linux
|| tdesc
== tdesc_amd64_linux_no_xml
2858 || tdesc
== tdesc_x32_linux
)
2859 return X86_TDESC_SSE
;
2860 if (tdesc
== tdesc_amd64_avx_linux
|| tdesc
== tdesc_x32_avx_linux
)
2861 return X86_TDESC_AVX
;
2862 if (tdesc
== tdesc_amd64_mpx_linux
)
2863 return X86_TDESC_MPX
;
2864 if (tdesc
== tdesc_amd64_avx_mpx_linux
)
2865 return X86_TDESC_AVX_MPX
;
2866 if (tdesc
== tdesc_amd64_avx512_linux
|| tdesc
== tdesc_x32_avx512_linux
)
2867 return X86_TDESC_AVX512
;
2870 if (tdesc
== tdesc_i386_mmx_linux
)
2871 return X86_TDESC_MMX
;
2872 if (tdesc
== tdesc_i386_linux
|| tdesc
== tdesc_i386_linux_no_xml
)
2873 return X86_TDESC_SSE
;
2874 if (tdesc
== tdesc_i386_avx_linux
)
2875 return X86_TDESC_AVX
;
2876 if (tdesc
== tdesc_i386_mpx_linux
)
2877 return X86_TDESC_MPX
;
2878 if (tdesc
== tdesc_i386_avx_mpx_linux
)
2879 return X86_TDESC_AVX_MPX
;
2880 if (tdesc
== tdesc_i386_avx512_linux
)
2881 return X86_TDESC_AVX512
;
2886 /* This is initialized assuming an amd64 target.
2887 x86_arch_setup will correct it for i386 or amd64 targets. */
2889 struct linux_target_ops the_low_target
=
2892 x86_linux_regs_info
,
2893 x86_cannot_fetch_register
,
2894 x86_cannot_store_register
,
2895 NULL
, /* fetch_register */
2898 NULL
, /* breakpoint_kind_from_pc */
2899 x86_sw_breakpoint_from_kind
,
2903 x86_supports_z_point_type
,
2906 x86_stopped_by_watchpoint
,
2907 x86_stopped_data_address
,
2908 /* collect_ptrace_register/supply_ptrace_register are not needed in the
2909 native i386 case (no registers smaller than an xfer unit), and are not
2910 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
2913 /* need to fix up i386 siginfo if host is amd64 */
2915 x86_linux_new_process
,
2916 x86_linux_new_thread
,
2918 x86_linux_prepare_to_resume
,
2919 x86_linux_process_qsupported
,
2920 x86_supports_tracepoints
,
2921 x86_get_thread_area
,
2922 x86_install_fast_tracepoint_jump_pad
,
2924 x86_get_min_fast_tracepoint_insn_len
,
2925 x86_supports_range_stepping
,
2926 NULL
, /* breakpoint_kind_from_current_state */
2927 x86_supports_hardware_single_step
,
2928 x86_get_syscall_trapinfo
,
2929 x86_get_ipa_tdesc_idx
,
2933 initialize_low_arch (void)
2935 /* Initialize the Linux target descriptions. */
2937 init_registers_amd64_linux ();
2938 init_registers_amd64_avx_linux ();
2939 init_registers_amd64_avx512_linux ();
2940 init_registers_amd64_mpx_linux ();
2941 init_registers_amd64_avx_mpx_linux ();
2943 init_registers_x32_linux ();
2944 init_registers_x32_avx_linux ();
2945 init_registers_x32_avx512_linux ();
2947 tdesc_amd64_linux_no_xml
= XNEW (struct target_desc
);
2948 copy_target_description (tdesc_amd64_linux_no_xml
, tdesc_amd64_linux
);
2949 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2951 init_registers_i386_linux ();
2952 init_registers_i386_mmx_linux ();
2953 init_registers_i386_avx_linux ();
2954 init_registers_i386_avx512_linux ();
2955 init_registers_i386_mpx_linux ();
2956 init_registers_i386_avx_mpx_linux ();
2958 tdesc_i386_linux_no_xml
= XNEW (struct target_desc
);
2959 copy_target_description (tdesc_i386_linux_no_xml
, tdesc_i386_linux
);
2960 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2962 initialize_regsets_info (&x86_regsets_info
);