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[thirdparty/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2024 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "frame.h"
22 #include "gdbcore.h"
23 #include "inferior.h"
24 #include "language.h"
25 #include "regcache.h"
26 #include "target-float.h"
27 #include "value.h"
28
29 #include "i386-tdep.h"
30 #include "i387-tdep.h"
31 #include "gdbsupport/x86-xstate.h"
32
33 /* Print the floating point number specified by RAW. */
34
35 static void
36 print_i387_value (struct gdbarch *gdbarch,
37 const gdb_byte *raw, struct ui_file *file)
38 {
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct type *type = i387_ext_type (gdbarch);
44 std::string str = target_float_to_string (raw, type, " %-+27.19g");
45 gdb_printf (file, "%s", str.c_str ());
46 }
47
48 /* Print the classification for the register contents RAW. */
49
50 static void
51 print_i387_ext (struct gdbarch *gdbarch,
52 const gdb_byte *raw, struct ui_file *file)
53 {
54 int sign;
55 int integer;
56 unsigned int exponent;
57 unsigned long fraction[2];
58
59 sign = raw[9] & 0x80;
60 integer = raw[7] & 0x80;
61 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
62 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
63 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
64 | (raw[5] << 8) | raw[4]);
65
66 if (exponent == 0x7fff && integer)
67 {
68 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
69 /* Infinity. */
70 gdb_printf (file, " %cInf", (sign ? '-' : '+'));
71 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
72 /* Real Indefinite (QNaN). */
73 gdb_puts (" Real Indefinite (QNaN)", file);
74 else if (fraction[1] & 0x40000000)
75 /* QNaN. */
76 gdb_puts (" QNaN", file);
77 else
78 /* SNaN. */
79 gdb_puts (" SNaN", file);
80 }
81 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
82 /* Normal. */
83 print_i387_value (gdbarch, raw, file);
84 else if (exponent == 0x0000)
85 {
86 /* Denormal or zero. */
87 print_i387_value (gdbarch, raw, file);
88
89 if (integer)
90 /* Pseudo-denormal. */
91 gdb_puts (" Pseudo-denormal", file);
92 else if (fraction[0] || fraction[1])
93 /* Denormal. */
94 gdb_puts (" Denormal", file);
95 }
96 else
97 /* Unsupported. */
98 gdb_puts (" Unsupported", file);
99 }
100
101 /* Print the status word STATUS. If STATUS_P is false, then STATUS
102 was unavailable. */
103
104 static void
105 print_i387_status_word (int status_p,
106 unsigned int status, struct ui_file *file)
107 {
108 gdb_printf (file, "Status Word: ");
109 if (!status_p)
110 {
111 gdb_printf (file, "%s\n", _("<unavailable>"));
112 return;
113 }
114
115 gdb_printf (file, "%s", hex_string_custom (status, 4));
116 gdb_puts (" ", file);
117 gdb_printf (file, " %s", (status & 0x0001) ? "IE" : " ");
118 gdb_printf (file, " %s", (status & 0x0002) ? "DE" : " ");
119 gdb_printf (file, " %s", (status & 0x0004) ? "ZE" : " ");
120 gdb_printf (file, " %s", (status & 0x0008) ? "OE" : " ");
121 gdb_printf (file, " %s", (status & 0x0010) ? "UE" : " ");
122 gdb_printf (file, " %s", (status & 0x0020) ? "PE" : " ");
123 gdb_puts (" ", file);
124 gdb_printf (file, " %s", (status & 0x0080) ? "ES" : " ");
125 gdb_puts (" ", file);
126 gdb_printf (file, " %s", (status & 0x0040) ? "SF" : " ");
127 gdb_puts (" ", file);
128 gdb_printf (file, " %s", (status & 0x0100) ? "C0" : " ");
129 gdb_printf (file, " %s", (status & 0x0200) ? "C1" : " ");
130 gdb_printf (file, " %s", (status & 0x0400) ? "C2" : " ");
131 gdb_printf (file, " %s", (status & 0x4000) ? "C3" : " ");
132
133 gdb_puts ("\n", file);
134
135 gdb_printf (file,
136 " TOP: %d\n", ((status >> 11) & 7));
137 }
138
139 /* Print the control word CONTROL. If CONTROL_P is false, then
140 CONTROL was unavailable. */
141
142 static void
143 print_i387_control_word (int control_p,
144 unsigned int control, struct ui_file *file)
145 {
146 gdb_printf (file, "Control Word: ");
147 if (!control_p)
148 {
149 gdb_printf (file, "%s\n", _("<unavailable>"));
150 return;
151 }
152
153 gdb_printf (file, "%s", hex_string_custom (control, 4));
154 gdb_puts (" ", file);
155 gdb_printf (file, " %s", (control & 0x0001) ? "IM" : " ");
156 gdb_printf (file, " %s", (control & 0x0002) ? "DM" : " ");
157 gdb_printf (file, " %s", (control & 0x0004) ? "ZM" : " ");
158 gdb_printf (file, " %s", (control & 0x0008) ? "OM" : " ");
159 gdb_printf (file, " %s", (control & 0x0010) ? "UM" : " ");
160 gdb_printf (file, " %s", (control & 0x0020) ? "PM" : " ");
161
162 gdb_puts ("\n", file);
163
164 gdb_puts (" PC: ", file);
165 switch ((control >> 8) & 3)
166 {
167 case 0:
168 gdb_puts ("Single Precision (24-bits)\n", file);
169 break;
170 case 1:
171 gdb_puts ("Reserved\n", file);
172 break;
173 case 2:
174 gdb_puts ("Double Precision (53-bits)\n", file);
175 break;
176 case 3:
177 gdb_puts ("Extended Precision (64-bits)\n", file);
178 break;
179 }
180
181 gdb_puts (" RC: ", file);
182 switch ((control >> 10) & 3)
183 {
184 case 0:
185 gdb_puts ("Round to nearest\n", file);
186 break;
187 case 1:
188 gdb_puts ("Round down\n", file);
189 break;
190 case 2:
191 gdb_puts ("Round up\n", file);
192 break;
193 case 3:
194 gdb_puts ("Round toward zero\n", file);
195 break;
196 }
197 }
198
199 /* Print out the i387 floating point state. Note that we ignore FRAME
200 in the code below. That's OK since floating-point registers are
201 never saved on the stack. */
202
203 void
204 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
205 const frame_info_ptr &frame, const char *args)
206 {
207 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
208 ULONGEST fctrl;
209 int fctrl_p;
210 ULONGEST fstat;
211 int fstat_p;
212 ULONGEST ftag;
213 int ftag_p;
214 ULONGEST fiseg;
215 int fiseg_p;
216 ULONGEST fioff;
217 int fioff_p;
218 ULONGEST foseg;
219 int foseg_p;
220 ULONGEST fooff;
221 int fooff_p;
222 ULONGEST fop;
223 int fop_p;
224 int fpreg;
225 int top;
226
227 gdb_assert (gdbarch == get_frame_arch (frame));
228
229 fctrl_p = read_frame_register_unsigned (frame,
230 I387_FCTRL_REGNUM (tdep), &fctrl);
231 fstat_p = read_frame_register_unsigned (frame,
232 I387_FSTAT_REGNUM (tdep), &fstat);
233 ftag_p = read_frame_register_unsigned (frame,
234 I387_FTAG_REGNUM (tdep), &ftag);
235 fiseg_p = read_frame_register_unsigned (frame,
236 I387_FISEG_REGNUM (tdep), &fiseg);
237 fioff_p = read_frame_register_unsigned (frame,
238 I387_FIOFF_REGNUM (tdep), &fioff);
239 foseg_p = read_frame_register_unsigned (frame,
240 I387_FOSEG_REGNUM (tdep), &foseg);
241 fooff_p = read_frame_register_unsigned (frame,
242 I387_FOOFF_REGNUM (tdep), &fooff);
243 fop_p = read_frame_register_unsigned (frame,
244 I387_FOP_REGNUM (tdep), &fop);
245
246 if (fstat_p)
247 {
248 top = ((fstat >> 11) & 7);
249
250 for (fpreg = 7; fpreg >= 0; fpreg--)
251 {
252 struct value *regval;
253 int regnum;
254 int i;
255 int tag = -1;
256
257 gdb_printf (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
258
259 if (ftag_p)
260 {
261 tag = (ftag >> (fpreg * 2)) & 3;
262
263 switch (tag)
264 {
265 case 0:
266 gdb_puts ("Valid ", file);
267 break;
268 case 1:
269 gdb_puts ("Zero ", file);
270 break;
271 case 2:
272 gdb_puts ("Special ", file);
273 break;
274 case 3:
275 gdb_puts ("Empty ", file);
276 break;
277 }
278 }
279 else
280 gdb_puts ("Unknown ", file);
281
282 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
283 regval = get_frame_register_value (frame, regnum);
284
285 if (regval->entirely_available ())
286 {
287 const gdb_byte *raw = regval->contents ().data ();
288
289 gdb_puts ("0x", file);
290 for (i = 9; i >= 0; i--)
291 gdb_printf (file, "%02x", raw[i]);
292
293 if (tag != -1 && tag != 3)
294 print_i387_ext (gdbarch, raw, file);
295 }
296 else
297 gdb_printf (file, "%s", _("<unavailable>"));
298
299 gdb_puts ("\n", file);
300 }
301 }
302
303 gdb_puts ("\n", file);
304 print_i387_status_word (fstat_p, fstat, file);
305 print_i387_control_word (fctrl_p, fctrl, file);
306 gdb_printf (file, "Tag Word: %s\n",
307 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
308 gdb_printf (file, "Instruction Pointer: %s:",
309 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
310 gdb_printf (file, "%s\n",
311 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
312 gdb_printf (file, "Operand Pointer: %s:",
313 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
314 gdb_printf (file, "%s\n",
315 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
316 gdb_printf (file, "Opcode: %s\n",
317 fop_p
318 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
319 : _("<unavailable>"));
320 }
321 \f
322
323 /* Return nonzero if a value of type TYPE stored in register REGNUM
324 needs any special handling. */
325
326 int
327 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
328 struct type *type)
329 {
330 if (i386_fp_regnum_p (gdbarch, regnum))
331 {
332 /* Floating point registers must be converted unless we are
333 accessing them in their hardware type or TYPE is not float. */
334 if (type == i387_ext_type (gdbarch)
335 || type->code () != TYPE_CODE_FLT)
336 return 0;
337 else
338 return 1;
339 }
340
341 return 0;
342 }
343
344 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
345 return its contents in TO. */
346
347 int
348 i387_register_to_value (const frame_info_ptr &frame, int regnum,
349 struct type *type, gdb_byte *to,
350 int *optimizedp, int *unavailablep)
351 {
352 struct gdbarch *gdbarch = get_frame_arch (frame);
353 gdb_byte from[I386_MAX_REGISTER_SIZE];
354
355 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
356
357 /* We only support floating-point values. */
358 if (type->code () != TYPE_CODE_FLT)
359 {
360 warning (_("Cannot convert floating-point register value "
361 "to non-floating-point type."));
362 *optimizedp = *unavailablep = 0;
363 return 0;
364 }
365
366 /* Convert to TYPE. */
367 auto from_view
368 = gdb::make_array_view (from, register_size (gdbarch, regnum));
369 frame_info_ptr next_frame = get_next_frame_sentinel_okay (frame);
370 if (!get_frame_register_bytes (next_frame, regnum, 0, from_view, optimizedp,
371 unavailablep))
372 return 0;
373
374 target_float_convert (from, i387_ext_type (gdbarch), to, type);
375 *optimizedp = *unavailablep = 0;
376 return 1;
377 }
378
379 /* Write the contents FROM of a value of type TYPE into register
380 REGNUM in frame FRAME. */
381
382 void
383 i387_value_to_register (const frame_info_ptr &frame, int regnum,
384 struct type *type, const gdb_byte *from)
385 {
386 struct gdbarch *gdbarch = get_frame_arch (frame);
387 gdb_byte to[I386_MAX_REGISTER_SIZE];
388
389 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
390
391 /* We only support floating-point values. */
392 if (type->code () != TYPE_CODE_FLT)
393 {
394 warning (_("Cannot convert non-floating-point type "
395 "to floating-point register value."));
396 return;
397 }
398
399 /* Convert from TYPE. */
400 struct type *to_type = i387_ext_type (gdbarch);
401 target_float_convert (from, type, to, to_type);
402 auto to_view = gdb::make_array_view (to, to_type->length ());
403 put_frame_register (get_next_frame_sentinel_okay (frame), regnum, to_view);
404 }
405 \f
406
407 /* Handle FSAVE and FXSAVE formats. */
408
409 /* At fsave_offset[REGNUM] you'll find the offset to the location in
410 the data structure used by the "fsave" instruction where GDB
411 register REGNUM is stored. */
412
413 static int fsave_offset[] =
414 {
415 28 + 0 * 10, /* %st(0) ... */
416 28 + 1 * 10,
417 28 + 2 * 10,
418 28 + 3 * 10,
419 28 + 4 * 10,
420 28 + 5 * 10,
421 28 + 6 * 10,
422 28 + 7 * 10, /* ... %st(7). */
423 0, /* `fctrl' (16 bits). */
424 4, /* `fstat' (16 bits). */
425 8, /* `ftag' (16 bits). */
426 16, /* `fiseg' (16 bits). */
427 12, /* `fioff'. */
428 24, /* `foseg' (16 bits). */
429 20, /* `fooff'. */
430 18 /* `fop' (bottom 11 bits). */
431 };
432
433 #define FSAVE_ADDR(tdep, fsave, regnum) \
434 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
435 \f
436
437 /* Fill register REGNUM in REGCACHE with the appropriate value from
438 *FSAVE. This function masks off any of the reserved bits in
439 *FSAVE. */
440
441 void
442 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
443 {
444 struct gdbarch *gdbarch = regcache->arch ();
445 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
446 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
447 const gdb_byte *regs = (const gdb_byte *) fsave;
448 int i;
449
450 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
451
452 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
453 if (regnum == -1 || regnum == i)
454 {
455 if (fsave == NULL)
456 {
457 regcache->raw_supply (i, NULL);
458 continue;
459 }
460
461 /* Most of the FPU control registers occupy only 16 bits in the
462 fsave area. Give those a special treatment. */
463 if (i >= I387_FCTRL_REGNUM (tdep)
464 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
465 {
466 gdb_byte val[4];
467
468 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
469 val[2] = val[3] = 0;
470 if (i == I387_FOP_REGNUM (tdep))
471 val[1] &= ((1 << 3) - 1);
472 regcache->raw_supply (i, val);
473 }
474 else
475 regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i));
476 }
477
478 /* Provide dummy values for the SSE registers. */
479 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
480 if (regnum == -1 || regnum == i)
481 regcache->raw_supply (i, NULL);
482 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
483 {
484 gdb_byte buf[4];
485
486 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
487 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
488 }
489 }
490
491 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
492 with the value from REGCACHE. If REGNUM is -1, do this for all
493 registers. This function doesn't touch any of the reserved bits in
494 *FSAVE. */
495
496 void
497 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
498 {
499 gdbarch *arch = regcache->arch ();
500 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
501 gdb_byte *regs = (gdb_byte *) fsave;
502 int i;
503
504 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
505
506 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
507 if (regnum == -1 || regnum == i)
508 {
509 /* Most of the FPU control registers occupy only 16 bits in
510 the fsave area. Give those a special treatment. */
511 if (i >= I387_FCTRL_REGNUM (tdep)
512 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
513 {
514 gdb_byte buf[4];
515
516 regcache->raw_collect (i, buf);
517
518 if (i == I387_FOP_REGNUM (tdep))
519 {
520 /* The opcode occupies only 11 bits. Make sure we
521 don't touch the other bits. */
522 buf[1] &= ((1 << 3) - 1);
523 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
524 }
525 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
526 }
527 else
528 regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i));
529 }
530 }
531 \f
532
533 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
534 the data structure used by the "fxsave" instruction where GDB
535 register REGNUM is stored. */
536
537 static int fxsave_offset[] =
538 {
539 32, /* %st(0) through ... */
540 48,
541 64,
542 80,
543 96,
544 112,
545 128,
546 144, /* ... %st(7) (80 bits each). */
547 0, /* `fctrl' (16 bits). */
548 2, /* `fstat' (16 bits). */
549 4, /* `ftag' (16 bits). */
550 12, /* `fiseg' (16 bits). */
551 8, /* `fioff'. */
552 20, /* `foseg' (16 bits). */
553 16, /* `fooff'. */
554 6, /* `fop' (bottom 11 bits). */
555 160 + 0 * 16, /* %xmm0 through ... */
556 160 + 1 * 16,
557 160 + 2 * 16,
558 160 + 3 * 16,
559 160 + 4 * 16,
560 160 + 5 * 16,
561 160 + 6 * 16,
562 160 + 7 * 16,
563 160 + 8 * 16,
564 160 + 9 * 16,
565 160 + 10 * 16,
566 160 + 11 * 16,
567 160 + 12 * 16,
568 160 + 13 * 16,
569 160 + 14 * 16,
570 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
571 };
572
573 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
574 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
575
576 /* We made an unfortunate choice in putting %mxcsr after the SSE
577 registers %xmm0-%xmm7 instead of before, since it makes supporting
578 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
579 don't include the offset for %mxcsr here above. */
580
581 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
582
583 static int i387_tag (const gdb_byte *raw);
584 \f
585
586 /* Fill register REGNUM in REGCACHE with the appropriate
587 floating-point or SSE register value from *FXSAVE. This function
588 masks off any of the reserved bits in *FXSAVE. */
589
590 void
591 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
592 {
593 gdbarch *arch = regcache->arch ();
594 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
595 const gdb_byte *regs = (const gdb_byte *) fxsave;
596 int i;
597
598 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
599 gdb_assert (tdep->num_xmm_regs > 0);
600
601 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
602 if (regnum == -1 || regnum == i)
603 {
604 if (regs == NULL)
605 {
606 regcache->raw_supply (i, NULL);
607 continue;
608 }
609
610 /* Most of the FPU control registers occupy only 16 bits in
611 the fxsave area. Give those a special treatment. */
612 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
613 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
614 {
615 gdb_byte val[4];
616
617 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
618 val[2] = val[3] = 0;
619 if (i == I387_FOP_REGNUM (tdep))
620 val[1] &= ((1 << 3) - 1);
621 else if (i== I387_FTAG_REGNUM (tdep))
622 {
623 /* The fxsave area contains a simplified version of
624 the tag word. We have to look at the actual 80-bit
625 FP data to recreate the traditional i387 tag word. */
626
627 unsigned long ftag = 0;
628 int fpreg;
629 int top;
630
631 top = ((FXSAVE_ADDR (tdep, regs,
632 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
633 top &= 0x7;
634
635 for (fpreg = 7; fpreg >= 0; fpreg--)
636 {
637 int tag;
638
639 if (val[0] & (1 << fpreg))
640 {
641 int thisreg = (fpreg + 8 - top) % 8
642 + I387_ST0_REGNUM (tdep);
643 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
644 }
645 else
646 tag = 3; /* Empty */
647
648 ftag |= tag << (2 * fpreg);
649 }
650 val[0] = ftag & 0xff;
651 val[1] = (ftag >> 8) & 0xff;
652 }
653 regcache->raw_supply (i, val);
654 }
655 else
656 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
657 }
658
659 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
660 {
661 if (regs == NULL)
662 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL);
663 else
664 regcache->raw_supply (I387_MXCSR_REGNUM (tdep),
665 FXSAVE_MXCSR_ADDR (regs));
666 }
667 }
668
669 /* Fill register REGNUM (if it is a floating-point or SSE register) in
670 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
671 all registers. This function doesn't touch any of the reserved
672 bits in *FXSAVE. */
673
674 void
675 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
676 {
677 gdbarch *arch = regcache->arch ();
678 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
679 gdb_byte *regs = (gdb_byte *) fxsave;
680 int i;
681
682 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
683 gdb_assert (tdep->num_xmm_regs > 0);
684
685 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
686 if (regnum == -1 || regnum == i)
687 {
688 /* Most of the FPU control registers occupy only 16 bits in
689 the fxsave area. Give those a special treatment. */
690 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
691 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
692 {
693 gdb_byte buf[4];
694
695 regcache->raw_collect (i, buf);
696
697 if (i == I387_FOP_REGNUM (tdep))
698 {
699 /* The opcode occupies only 11 bits. Make sure we
700 don't touch the other bits. */
701 buf[1] &= ((1 << 3) - 1);
702 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
703 }
704 else if (i == I387_FTAG_REGNUM (tdep))
705 {
706 /* Converting back is much easier. */
707
708 unsigned short ftag;
709 int fpreg;
710
711 ftag = (buf[1] << 8) | buf[0];
712 buf[0] = 0;
713 buf[1] = 0;
714
715 for (fpreg = 7; fpreg >= 0; fpreg--)
716 {
717 int tag = (ftag >> (fpreg * 2)) & 3;
718
719 if (tag != 3)
720 buf[0] |= (1 << fpreg);
721 }
722 }
723 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
724 }
725 else
726 regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i));
727 }
728
729 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
730 regcache->raw_collect (I387_MXCSR_REGNUM (tdep),
731 FXSAVE_MXCSR_ADDR (regs));
732 }
733
734 /* `xstate_bv' is at byte offset 512. */
735 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
736
737 /* At xsave_avxh_offset[REGNUM] you'll find the relative offset within
738 the AVX region of the XSAVE extended state where the upper 128bits
739 of GDB register YMM0 + REGNUM is stored. */
740
741 static int xsave_avxh_offset[] =
742 {
743 0 * 16, /* Upper 128bit of %ymm0 through ... */
744 1 * 16,
745 2 * 16,
746 3 * 16,
747 4 * 16,
748 5 * 16,
749 6 * 16,
750 7 * 16,
751 8 * 16,
752 9 * 16,
753 10 * 16,
754 11 * 16,
755 12 * 16,
756 13 * 16,
757 14 * 16,
758 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
759 };
760
761 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
762 (xsave + (tdep)->xsave_layout.avx_offset \
763 + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
764
765 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset
766 within the ZMM region of the XSAVE extended state where the second
767 128bits of GDB register YMM16 + REGNUM is stored. */
768
769 static int xsave_ymm_avx512_offset[] =
770 {
771 16 + 0 * 64, /* %ymm16 through... */
772 16 + 1 * 64,
773 16 + 2 * 64,
774 16 + 3 * 64,
775 16 + 4 * 64,
776 16 + 5 * 64,
777 16 + 6 * 64,
778 16 + 7 * 64,
779 16 + 8 * 64,
780 16 + 9 * 64,
781 16 + 10 * 64,
782 16 + 11 * 64,
783 16 + 12 * 64,
784 16 + 13 * 64,
785 16 + 14 * 64,
786 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
787 };
788
789 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
790 (xsave + (tdep)->xsave_layout.zmm_offset \
791 + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
792
793 /* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset
794 within the ZMM region of the XSAVE extended state where the first
795 128bits of GDB register XMM16 + REGNUM is stored. */
796
797 static int xsave_xmm_avx512_offset[] =
798 {
799 0 * 64, /* %xmm16 through... */
800 1 * 64,
801 2 * 64,
802 3 * 64,
803 4 * 64,
804 5 * 64,
805 6 * 64,
806 7 * 64,
807 8 * 64,
808 9 * 64,
809 10 * 64,
810 11 * 64,
811 12 * 64,
812 13 * 64,
813 14 * 64,
814 15 * 64 /* ... %xmm31 (128 bits each). */
815 };
816
817 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
818 (xsave + (tdep)->xsave_layout.zmm_offset \
819 + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
820
821 /* At xsave_bndregs_offset[REGNUM] you'll find the relative offset
822 within the BNDREGS region of the XSAVE extended state where the GDB
823 register BND0R + REGNUM is stored. */
824
825 static int xsave_bndregs_offset[] = {
826 0 * 16, /* bnd0r...bnd3r registers. */
827 1 * 16,
828 2 * 16,
829 3 * 16
830 };
831
832 #define XSAVE_BNDREGS_ADDR(tdep, xsave, regnum) \
833 (xsave + (tdep)->xsave_layout.bndregs_offset \
834 + xsave_bndregs_offset[regnum - I387_BND0R_REGNUM (tdep)])
835
836 static int xsave_bndcfg_offset[] = {
837 0 * 8, /* bndcfg ... bndstatus. */
838 1 * 8,
839 };
840
841 #define XSAVE_BNDCFG_ADDR(tdep, xsave, regnum) \
842 (xsave + (tdep)->xsave_layout.bndcfg_offset \
843 + xsave_bndcfg_offset[regnum - I387_BNDCFGU_REGNUM (tdep)])
844
845 /* At xsave_avx512_k_offset[REGNUM] you'll find the relative offset
846 within the K region of the XSAVE extended state where the AVX512
847 opmask register K0 + REGNUM is stored. */
848
849 static int xsave_avx512_k_offset[] =
850 {
851 0 * 8, /* %k0 through... */
852 1 * 8,
853 2 * 8,
854 3 * 8,
855 4 * 8,
856 5 * 8,
857 6 * 8,
858 7 * 8 /* %k7 (64 bits each). */
859 };
860
861 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
862 (xsave + (tdep)->xsave_layout.k_offset \
863 + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
864
865
866 /* At xsave_avx512_zmm0_h_offset[REGNUM] you find the relative offset
867 within the ZMM_H region of the XSAVE extended state where the upper
868 256bits of the GDB register ZMM0 + REGNUM is stored. */
869
870 static int xsave_avx512_zmm0_h_offset[] =
871 {
872 0 * 32, /* Upper 256bit of %zmmh0 through... */
873 1 * 32,
874 2 * 32,
875 3 * 32,
876 4 * 32,
877 5 * 32,
878 6 * 32,
879 7 * 32,
880 8 * 32,
881 9 * 32,
882 10 * 32,
883 11 * 32,
884 12 * 32,
885 13 * 32,
886 14 * 32,
887 15 * 32 /* Upper 256bit of... %zmmh15 (256 bits each). */
888 };
889
890 #define XSAVE_AVX512_ZMM0_H_ADDR(tdep, xsave, regnum) \
891 (xsave + (tdep)->xsave_layout.zmm_h_offset \
892 + xsave_avx512_zmm0_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
893
894 /* At xsave_avx512_zmm16_h_offset[REGNUM] you find the relative offset
895 within the ZMM_H region of the XSAVE extended state where the upper
896 256bits of the GDB register ZMM16 + REGNUM is stored. */
897
898 static int xsave_avx512_zmm16_h_offset[] =
899 {
900 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
901 32 + 1 * 64,
902 32 + 2 * 64,
903 32 + 3 * 64,
904 32 + 4 * 64,
905 32 + 5 * 64,
906 32 + 6 * 64,
907 32 + 7 * 64,
908 32 + 8 * 64,
909 32 + 9 * 64,
910 32 + 10 * 64,
911 32 + 11 * 64,
912 32 + 12 * 64,
913 32 + 13 * 64,
914 32 + 14 * 64,
915 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
916 };
917
918 #define XSAVE_AVX512_ZMM16_H_ADDR(tdep, xsave, regnum) \
919 (xsave + (tdep)->xsave_layout.zmm_offset \
920 + xsave_avx512_zmm16_h_offset[regnum - I387_ZMM16H_REGNUM (tdep)])
921
922 /* At xsave_pkeys_offset[REGNUM] you'll find the relative offset
923 within the PKEYS region of the XSAVE extended state where the PKRU
924 register is stored. */
925
926 static int xsave_pkeys_offset[] =
927 {
928 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
929 instructions and applications). */
930 };
931
932 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
933 (xsave + (tdep)->xsave_layout.pkru_offset \
934 + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
935
936
937 /* See i387-tdep.h. */
938
939 bool
940 i387_guess_xsave_layout (uint64_t xcr0, size_t xsave_size,
941 x86_xsave_layout &layout)
942 {
943 if (HAS_PKRU (xcr0) && xsave_size == 2696)
944 {
945 /* Intel CPUs supporting PKRU. */
946 layout.avx_offset = 576;
947 layout.bndregs_offset = 960;
948 layout.bndcfg_offset = 1024;
949 layout.k_offset = 1088;
950 layout.zmm_h_offset = 1152;
951 layout.zmm_offset = 1664;
952 layout.pkru_offset = 2688;
953 }
954 else if (HAS_PKRU (xcr0) && xsave_size == 2440)
955 {
956 /* AMD CPUs supporting PKRU. */
957 layout.avx_offset = 576;
958 layout.k_offset = 832;
959 layout.zmm_h_offset = 896;
960 layout.zmm_offset = 1408;
961 layout.pkru_offset = 2432;
962 }
963 else if (HAS_AVX512 (xcr0) && xsave_size == 2688)
964 {
965 /* Intel CPUs supporting AVX512. */
966 layout.avx_offset = 576;
967 layout.bndregs_offset = 960;
968 layout.bndcfg_offset = 1024;
969 layout.k_offset = 1088;
970 layout.zmm_h_offset = 1152;
971 layout.zmm_offset = 1664;
972 }
973 else if (HAS_MPX (xcr0) && xsave_size == 1088)
974 {
975 /* Intel CPUs supporting MPX. */
976 layout.avx_offset = 576;
977 layout.bndregs_offset = 960;
978 layout.bndcfg_offset = 1024;
979 }
980 else if (HAS_AVX (xcr0) && xsave_size == 832)
981 {
982 /* Intel and AMD CPUs supporting AVX. */
983 layout.avx_offset = 576;
984 }
985 else
986 return false;
987
988 layout.sizeof_xsave = xsave_size;
989 return true;
990 }
991
992 /* See i387-tdep.h. */
993
994 x86_xsave_layout
995 i387_fallback_xsave_layout (uint64_t xcr0)
996 {
997 x86_xsave_layout layout;
998
999 if (HAS_PKRU (xcr0))
1000 {
1001 /* Intel CPUs supporting PKRU. */
1002 layout.avx_offset = 576;
1003 layout.bndregs_offset = 960;
1004 layout.bndcfg_offset = 1024;
1005 layout.k_offset = 1088;
1006 layout.zmm_h_offset = 1152;
1007 layout.zmm_offset = 1664;
1008 layout.pkru_offset = 2688;
1009 layout.sizeof_xsave = 2696;
1010 }
1011 else if (HAS_AVX512 (xcr0))
1012 {
1013 /* Intel CPUs supporting AVX512. */
1014 layout.avx_offset = 576;
1015 layout.bndregs_offset = 960;
1016 layout.bndcfg_offset = 1024;
1017 layout.k_offset = 1088;
1018 layout.zmm_h_offset = 1152;
1019 layout.zmm_offset = 1664;
1020 layout.sizeof_xsave = 2688;
1021 }
1022 else if (HAS_MPX (xcr0))
1023 {
1024 /* Intel CPUs supporting MPX. */
1025 layout.avx_offset = 576;
1026 layout.bndregs_offset = 960;
1027 layout.bndcfg_offset = 1024;
1028 layout.sizeof_xsave = 1088;
1029 }
1030 else if (HAS_AVX (xcr0))
1031 {
1032 /* Intel and AMD CPUs supporting AVX. */
1033 layout.avx_offset = 576;
1034 layout.sizeof_xsave = 832;
1035 }
1036
1037 return layout;
1038 }
1039
1040 /* Extract from XSAVE a bitset of the features that are available on the
1041 target, but which have not yet been enabled. */
1042
1043 ULONGEST
1044 i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave)
1045 {
1046 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1047 const gdb_byte *regs = (const gdb_byte *) xsave;
1048 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1049
1050 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
1051 ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1052 8, byte_order);
1053
1054 /* Clear part in vector registers if its bit in xstat_bv is zero. */
1055 ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0;
1056
1057 return clear_bv;
1058 }
1059
1060 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
1061
1062 void
1063 i387_supply_xsave (struct regcache *regcache, int regnum,
1064 const void *xsave)
1065 {
1066 struct gdbarch *gdbarch = regcache->arch ();
1067 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1068 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1069 const gdb_byte *regs = (const gdb_byte *) xsave;
1070 int i;
1071 /* In 64-bit mode the split between "low" and "high" ZMM registers is at
1072 ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all.
1073 Precalculate the number to be used for the split point, with the all
1074 registers in the "low" portion outside of 64-bit mode. */
1075 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1076 + std::min (tdep->num_zmm_regs, 16);
1077 ULONGEST clear_bv;
1078 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
1079 enum
1080 {
1081 none = 0x0,
1082 x87 = 0x1,
1083 sse = 0x2,
1084 avxh = 0x4,
1085 bndregs = 0x8,
1086 bndcfg = 0x10,
1087 avx512_k = 0x20,
1088 avx512_zmm0_h = 0x40,
1089 avx512_zmm16_h = 0x80,
1090 avx512_ymmh_avx512 = 0x100,
1091 avx512_xmm_avx512 = 0x200,
1092 pkeys = 0x400,
1093 all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h
1094 | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1095 } regclass;
1096
1097 gdb_assert (regs != NULL);
1098 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1099 gdb_assert (tdep->num_xmm_regs > 0);
1100
1101 if (regnum == -1)
1102 regclass = all;
1103 else if (regnum >= I387_PKRU_REGNUM (tdep)
1104 && regnum < I387_PKEYSEND_REGNUM (tdep))
1105 regclass = pkeys;
1106 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1107 && regnum < I387_ZMM16H_REGNUM (tdep))
1108 regclass = avx512_zmm0_h;
1109 else if (regnum >= I387_ZMM16H_REGNUM (tdep)
1110 && regnum < I387_ZMMENDH_REGNUM (tdep))
1111 regclass = avx512_zmm16_h;
1112 else if (regnum >= I387_K0_REGNUM (tdep)
1113 && regnum < I387_KEND_REGNUM (tdep))
1114 regclass = avx512_k;
1115 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1116 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1117 regclass = avx512_ymmh_avx512;
1118 else if (regnum >= I387_XMM16_REGNUM (tdep)
1119 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1120 regclass = avx512_xmm_avx512;
1121 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1122 && regnum < I387_YMMENDH_REGNUM (tdep))
1123 regclass = avxh;
1124 else if (regnum >= I387_BND0R_REGNUM (tdep)
1125 && regnum < I387_BNDCFGU_REGNUM (tdep))
1126 regclass = bndregs;
1127 else if (regnum >= I387_BNDCFGU_REGNUM (tdep)
1128 && regnum < I387_MPXEND_REGNUM (tdep))
1129 regclass = bndcfg;
1130 else if (regnum >= I387_XMM0_REGNUM (tdep)
1131 && regnum < I387_MXCSR_REGNUM (tdep))
1132 regclass = sse;
1133 else if (regnum >= I387_ST0_REGNUM (tdep)
1134 && regnum < I387_FCTRL_REGNUM (tdep))
1135 regclass = x87;
1136 else
1137 regclass = none;
1138
1139 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
1140
1141 /* With the delayed xsave mechanism, in between the program
1142 starting, and the program accessing the vector registers for the
1143 first time, the register's values are invalid. The kernel
1144 initializes register states to zero when they are set the first
1145 time in a program. This means that from the user-space programs'
1146 perspective, it's the same as if the registers have always been
1147 zero from the start of the program. Therefore, the debugger
1148 should provide the same illusion to the user. */
1149
1150 switch (regclass)
1151 {
1152 case none:
1153 break;
1154
1155 case pkeys:
1156 if ((clear_bv & X86_XSTATE_PKRU))
1157 regcache->raw_supply (regnum, zero);
1158 else
1159 regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum));
1160 return;
1161
1162 case avx512_zmm0_h:
1163 if ((clear_bv & X86_XSTATE_ZMM_H))
1164 regcache->raw_supply (regnum, zero);
1165 else
1166 regcache->raw_supply (regnum,
1167 XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum));
1168 return;
1169
1170 case avx512_zmm16_h:
1171 if ((clear_bv & X86_XSTATE_ZMM))
1172 regcache->raw_supply (regnum, zero);
1173 else
1174 regcache->raw_supply (regnum,
1175 XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum));
1176 return;
1177
1178 case avx512_k:
1179 if ((clear_bv & X86_XSTATE_K))
1180 regcache->raw_supply (regnum, zero);
1181 else
1182 regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
1183 return;
1184
1185 case avx512_ymmh_avx512:
1186 if ((clear_bv & X86_XSTATE_ZMM))
1187 regcache->raw_supply (regnum, zero);
1188 else
1189 regcache->raw_supply (regnum,
1190 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1191 return;
1192
1193 case avx512_xmm_avx512:
1194 if ((clear_bv & X86_XSTATE_ZMM))
1195 regcache->raw_supply (regnum, zero);
1196 else
1197 regcache->raw_supply (regnum,
1198 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1199 return;
1200
1201 case avxh:
1202 if ((clear_bv & X86_XSTATE_AVX))
1203 regcache->raw_supply (regnum, zero);
1204 else
1205 regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum));
1206 return;
1207
1208 case bndcfg:
1209 if ((clear_bv & X86_XSTATE_BNDCFG))
1210 regcache->raw_supply (regnum, zero);
1211 else
1212 regcache->raw_supply (regnum, XSAVE_BNDCFG_ADDR (tdep, regs, regnum));
1213 return;
1214
1215 case bndregs:
1216 if ((clear_bv & X86_XSTATE_BNDREGS))
1217 regcache->raw_supply (regnum, zero);
1218 else
1219 regcache->raw_supply (regnum, XSAVE_BNDREGS_ADDR (tdep, regs, regnum));
1220 return;
1221
1222 case sse:
1223 if ((clear_bv & X86_XSTATE_SSE))
1224 regcache->raw_supply (regnum, zero);
1225 else
1226 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1227 return;
1228
1229 case x87:
1230 if ((clear_bv & X86_XSTATE_X87))
1231 regcache->raw_supply (regnum, zero);
1232 else
1233 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1234 return;
1235
1236 case all:
1237 /* Handle PKEYS registers. */
1238 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1239 {
1240 if ((clear_bv & X86_XSTATE_PKRU))
1241 {
1242 for (i = I387_PKRU_REGNUM (tdep);
1243 i < I387_PKEYSEND_REGNUM (tdep);
1244 i++)
1245 regcache->raw_supply (i, zero);
1246 }
1247 else
1248 {
1249 for (i = I387_PKRU_REGNUM (tdep);
1250 i < I387_PKEYSEND_REGNUM (tdep);
1251 i++)
1252 regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i));
1253 }
1254 }
1255
1256 /* Handle the upper halves of the low 8/16 ZMM registers. */
1257 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1258 {
1259 if ((clear_bv & X86_XSTATE_ZMM_H))
1260 {
1261 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1262 regcache->raw_supply (i, zero);
1263 }
1264 else
1265 {
1266 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1267 regcache->raw_supply (i,
1268 XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i));
1269 }
1270 }
1271
1272 /* Handle AVX512 OpMask registers. */
1273 if ((tdep->xcr0 & X86_XSTATE_K))
1274 {
1275 if ((clear_bv & X86_XSTATE_K))
1276 {
1277 for (i = I387_K0_REGNUM (tdep);
1278 i < I387_KEND_REGNUM (tdep);
1279 i++)
1280 regcache->raw_supply (i, zero);
1281 }
1282 else
1283 {
1284 for (i = I387_K0_REGNUM (tdep);
1285 i < I387_KEND_REGNUM (tdep);
1286 i++)
1287 regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i));
1288 }
1289 }
1290
1291 /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */
1292 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1293 {
1294 if ((clear_bv & X86_XSTATE_ZMM))
1295 {
1296 for (i = I387_ZMM16H_REGNUM (tdep);
1297 i < I387_ZMMENDH_REGNUM (tdep); i++)
1298 regcache->raw_supply (i, zero);
1299 for (i = I387_YMM16H_REGNUM (tdep);
1300 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1301 i++)
1302 regcache->raw_supply (i, zero);
1303 for (i = I387_XMM16_REGNUM (tdep);
1304 i < I387_XMM_AVX512_END_REGNUM (tdep);
1305 i++)
1306 regcache->raw_supply (i, zero);
1307 }
1308 else
1309 {
1310 for (i = I387_ZMM16H_REGNUM (tdep);
1311 i < I387_ZMMENDH_REGNUM (tdep); i++)
1312 regcache->raw_supply (i,
1313 XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i));
1314 for (i = I387_YMM16H_REGNUM (tdep);
1315 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1316 i++)
1317 regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1318 for (i = I387_XMM16_REGNUM (tdep);
1319 i < I387_XMM_AVX512_END_REGNUM (tdep);
1320 i++)
1321 regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1322 }
1323 }
1324 /* Handle the upper YMM registers. */
1325 if ((tdep->xcr0 & X86_XSTATE_AVX))
1326 {
1327 if ((clear_bv & X86_XSTATE_AVX))
1328 {
1329 for (i = I387_YMM0H_REGNUM (tdep);
1330 i < I387_YMMENDH_REGNUM (tdep);
1331 i++)
1332 regcache->raw_supply (i, zero);
1333 }
1334 else
1335 {
1336 for (i = I387_YMM0H_REGNUM (tdep);
1337 i < I387_YMMENDH_REGNUM (tdep);
1338 i++)
1339 regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i));
1340 }
1341 }
1342
1343 /* Handle the MPX registers. */
1344 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1345 {
1346 if (clear_bv & X86_XSTATE_BNDREGS)
1347 {
1348 for (i = I387_BND0R_REGNUM (tdep);
1349 i < I387_BNDCFGU_REGNUM (tdep); i++)
1350 regcache->raw_supply (i, zero);
1351 }
1352 else
1353 {
1354 for (i = I387_BND0R_REGNUM (tdep);
1355 i < I387_BNDCFGU_REGNUM (tdep); i++)
1356 regcache->raw_supply (i, XSAVE_BNDREGS_ADDR (tdep, regs, i));
1357 }
1358 }
1359
1360 /* Handle the MPX registers. */
1361 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1362 {
1363 if (clear_bv & X86_XSTATE_BNDCFG)
1364 {
1365 for (i = I387_BNDCFGU_REGNUM (tdep);
1366 i < I387_MPXEND_REGNUM (tdep); i++)
1367 regcache->raw_supply (i, zero);
1368 }
1369 else
1370 {
1371 for (i = I387_BNDCFGU_REGNUM (tdep);
1372 i < I387_MPXEND_REGNUM (tdep); i++)
1373 regcache->raw_supply (i, XSAVE_BNDCFG_ADDR (tdep, regs, i));
1374 }
1375 }
1376
1377 /* Handle the XMM registers. */
1378 if ((tdep->xcr0 & X86_XSTATE_SSE))
1379 {
1380 if ((clear_bv & X86_XSTATE_SSE))
1381 {
1382 for (i = I387_XMM0_REGNUM (tdep);
1383 i < I387_MXCSR_REGNUM (tdep);
1384 i++)
1385 regcache->raw_supply (i, zero);
1386 }
1387 else
1388 {
1389 for (i = I387_XMM0_REGNUM (tdep);
1390 i < I387_MXCSR_REGNUM (tdep); i++)
1391 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1392 }
1393 }
1394
1395 /* Handle the x87 registers. */
1396 if ((tdep->xcr0 & X86_XSTATE_X87))
1397 {
1398 if ((clear_bv & X86_XSTATE_X87))
1399 {
1400 for (i = I387_ST0_REGNUM (tdep);
1401 i < I387_FCTRL_REGNUM (tdep);
1402 i++)
1403 regcache->raw_supply (i, zero);
1404 }
1405 else
1406 {
1407 for (i = I387_ST0_REGNUM (tdep);
1408 i < I387_FCTRL_REGNUM (tdep);
1409 i++)
1410 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1411 }
1412 }
1413 break;
1414 }
1415
1416 /* Only handle x87 control registers. */
1417 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1418 if (regnum == -1 || regnum == i)
1419 {
1420 if (clear_bv & X86_XSTATE_X87)
1421 {
1422 if (i == I387_FCTRL_REGNUM (tdep))
1423 {
1424 gdb_byte buf[4];
1425
1426 store_unsigned_integer (buf, 4, byte_order,
1427 I387_FCTRL_INIT_VAL);
1428 regcache->raw_supply (i, buf);
1429 }
1430 else if (i == I387_FTAG_REGNUM (tdep))
1431 {
1432 gdb_byte buf[4];
1433
1434 store_unsigned_integer (buf, 4, byte_order, 0xffff);
1435 regcache->raw_supply (i, buf);
1436 }
1437 else
1438 regcache->raw_supply (i, zero);
1439 }
1440 /* Most of the FPU control registers occupy only 16 bits in
1441 the xsave extended state. Give those a special treatment. */
1442 else if (i != I387_FIOFF_REGNUM (tdep)
1443 && i != I387_FOOFF_REGNUM (tdep))
1444 {
1445 gdb_byte val[4];
1446
1447 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1448 val[2] = val[3] = 0;
1449 if (i == I387_FOP_REGNUM (tdep))
1450 val[1] &= ((1 << 3) - 1);
1451 else if (i == I387_FTAG_REGNUM (tdep))
1452 {
1453 /* The fxsave area contains a simplified version of
1454 the tag word. We have to look at the actual 80-bit
1455 FP data to recreate the traditional i387 tag word. */
1456
1457 unsigned long ftag = 0;
1458 int fpreg;
1459 int top;
1460
1461 top = ((FXSAVE_ADDR (tdep, regs,
1462 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1463 top &= 0x7;
1464
1465 for (fpreg = 7; fpreg >= 0; fpreg--)
1466 {
1467 int tag;
1468
1469 if (val[0] & (1 << fpreg))
1470 {
1471 int thisreg = (fpreg + 8 - top) % 8
1472 + I387_ST0_REGNUM (tdep);
1473 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1474 }
1475 else
1476 tag = 3; /* Empty */
1477
1478 ftag |= tag << (2 * fpreg);
1479 }
1480 val[0] = ftag & 0xff;
1481 val[1] = (ftag >> 8) & 0xff;
1482 }
1483 regcache->raw_supply (i, val);
1484 }
1485 else
1486 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1487 }
1488
1489 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1490 {
1491 /* The MXCSR register is placed into the xsave buffer if either the
1492 AVX or SSE features are enabled. */
1493 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1494 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1495 {
1496 gdb_byte buf[4];
1497
1498 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
1499 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
1500 }
1501 else
1502 regcache->raw_supply (I387_MXCSR_REGNUM (tdep),
1503 FXSAVE_MXCSR_ADDR (regs));
1504 }
1505 }
1506
1507 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1508
1509 void
1510 i387_collect_xsave (const struct regcache *regcache, int regnum,
1511 void *xsave, int gcore)
1512 {
1513 struct gdbarch *gdbarch = regcache->arch ();
1514 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1515 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1516 gdb_byte *p, *regs = (gdb_byte *) xsave;
1517 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1518 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1519 unsigned int i;
1520 /* See the comment in i387_supply_xsave(). */
1521 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1522 + std::min (tdep->num_zmm_regs, 16);
1523 enum
1524 {
1525 x87_ctrl_or_mxcsr = 0x1,
1526 x87 = 0x2,
1527 sse = 0x4,
1528 avxh = 0x8,
1529 bndregs = 0x10,
1530 bndcfg = 0x20,
1531 avx512_k = 0x40,
1532 avx512_zmm0_h = 0x80,
1533 avx512_zmm16_h = 0x100,
1534 avx512_ymmh_avx512 = 0x200,
1535 avx512_xmm_avx512 = 0x400,
1536 pkeys = 0x800,
1537 all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h
1538 | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1539 } regclass;
1540
1541 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1542 gdb_assert (tdep->num_xmm_regs > 0);
1543
1544 if (regnum == -1)
1545 regclass = all;
1546 else if (regnum >= I387_PKRU_REGNUM (tdep)
1547 && regnum < I387_PKEYSEND_REGNUM (tdep))
1548 regclass = pkeys;
1549 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1550 && regnum < I387_ZMM16H_REGNUM (tdep))
1551 regclass = avx512_zmm0_h;
1552 else if (regnum >= I387_ZMM16H_REGNUM (tdep)
1553 && regnum < I387_ZMMENDH_REGNUM (tdep))
1554 regclass = avx512_zmm16_h;
1555 else if (regnum >= I387_K0_REGNUM (tdep)
1556 && regnum < I387_KEND_REGNUM (tdep))
1557 regclass = avx512_k;
1558 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1559 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1560 regclass = avx512_ymmh_avx512;
1561 else if (regnum >= I387_XMM16_REGNUM (tdep)
1562 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1563 regclass = avx512_xmm_avx512;
1564 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1565 && regnum < I387_YMMENDH_REGNUM (tdep))
1566 regclass = avxh;
1567 else if (regnum >= I387_BND0R_REGNUM (tdep)
1568 && regnum < I387_BNDCFGU_REGNUM (tdep))
1569 regclass = bndregs;
1570 else if (regnum >= I387_BNDCFGU_REGNUM (tdep)
1571 && regnum < I387_MPXEND_REGNUM (tdep))
1572 regclass = bndcfg;
1573 else if (regnum >= I387_XMM0_REGNUM (tdep)
1574 && regnum < I387_MXCSR_REGNUM (tdep))
1575 regclass = sse;
1576 else if (regnum >= I387_ST0_REGNUM (tdep)
1577 && regnum < I387_FCTRL_REGNUM (tdep))
1578 regclass = x87;
1579 else if ((regnum >= I387_FCTRL_REGNUM (tdep)
1580 && regnum < I387_XMM0_REGNUM (tdep))
1581 || regnum == I387_MXCSR_REGNUM (tdep))
1582 regclass = x87_ctrl_or_mxcsr;
1583 else
1584 internal_error (_("invalid i387 regnum %d"), regnum);
1585
1586 if (gcore)
1587 {
1588 /* Clear XSAVE extended state. */
1589 memset (regs, 0, tdep->xsave_layout.sizeof_xsave);
1590
1591 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1592 if (tdep->xsave_xcr0_offset != -1)
1593 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1594 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1595 }
1596
1597 /* The supported bits in `xstat_bv' are 8 bytes. */
1598 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1599 8, byte_order);
1600 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1601
1602 /* The XSAVE buffer was filled lazily by the kernel. Only those
1603 features that are enabled were written into the buffer, disabled
1604 features left the buffer uninitialised. In order to identify if any
1605 registers have changed we will be comparing the register cache
1606 version to the version in the XSAVE buffer, it is important then that
1607 at this point we initialise to the default values any features in
1608 XSAVE that are not yet initialised.
1609
1610 This could be made more efficient, we know which features (from
1611 REGNUM) we will be potentially updating, and could limit ourselves to
1612 only clearing that feature. However, the extra complexity does not
1613 seem justified at this point. */
1614 if (clear_bv)
1615 {
1616 if ((clear_bv & X86_XSTATE_PKRU))
1617 for (i = I387_PKRU_REGNUM (tdep);
1618 i < I387_PKEYSEND_REGNUM (tdep); i++)
1619 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1620
1621 if ((clear_bv & X86_XSTATE_BNDREGS))
1622 for (i = I387_BND0R_REGNUM (tdep);
1623 i < I387_BNDCFGU_REGNUM (tdep); i++)
1624 memset (XSAVE_BNDREGS_ADDR (tdep, regs, i), 0, 16);
1625
1626 if ((clear_bv & X86_XSTATE_BNDCFG))
1627 for (i = I387_BNDCFGU_REGNUM (tdep);
1628 i < I387_MPXEND_REGNUM (tdep); i++)
1629 memset (XSAVE_BNDCFG_ADDR (tdep, regs, i), 0, 8);
1630
1631 if ((clear_bv & X86_XSTATE_ZMM_H))
1632 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1633 memset (XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i), 0, 32);
1634
1635 if ((clear_bv & X86_XSTATE_K))
1636 for (i = I387_K0_REGNUM (tdep);
1637 i < I387_KEND_REGNUM (tdep); i++)
1638 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1639
1640 if ((clear_bv & X86_XSTATE_ZMM))
1641 {
1642 for (i = I387_ZMM16H_REGNUM (tdep); i < I387_ZMMENDH_REGNUM (tdep);
1643 i++)
1644 memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32);
1645 for (i = I387_YMM16H_REGNUM (tdep);
1646 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1647 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1648 for (i = I387_XMM16_REGNUM (tdep);
1649 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1650 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1651 }
1652
1653 if ((clear_bv & X86_XSTATE_AVX))
1654 for (i = I387_YMM0H_REGNUM (tdep);
1655 i < I387_YMMENDH_REGNUM (tdep); i++)
1656 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1657
1658 if ((clear_bv & X86_XSTATE_SSE))
1659 for (i = I387_XMM0_REGNUM (tdep);
1660 i < I387_MXCSR_REGNUM (tdep); i++)
1661 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1662
1663 /* The mxcsr register is written into the xsave buffer if either AVX
1664 or SSE is enabled, so only clear it if both of those features
1665 require clearing. */
1666 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1667 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1668 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order,
1669 I387_MXCSR_INIT_VAL);
1670
1671 if ((clear_bv & X86_XSTATE_X87))
1672 {
1673 for (i = I387_ST0_REGNUM (tdep);
1674 i < I387_FCTRL_REGNUM (tdep); i++)
1675 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1676
1677 for (i = I387_FCTRL_REGNUM (tdep);
1678 i < I387_XMM0_REGNUM (tdep); i++)
1679 {
1680 if (i == I387_FCTRL_REGNUM (tdep))
1681 store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2,
1682 byte_order, I387_FCTRL_INIT_VAL);
1683 else
1684 memset (FXSAVE_ADDR (tdep, regs, i), 0,
1685 regcache_register_size (regcache, i));
1686 }
1687 }
1688 }
1689
1690 if (regclass == all)
1691 {
1692 /* Check if any PKEYS registers are changed. */
1693 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1694 for (i = I387_PKRU_REGNUM (tdep);
1695 i < I387_PKEYSEND_REGNUM (tdep); i++)
1696 {
1697 regcache->raw_collect (i, raw);
1698 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1699 if (memcmp (raw, p, 4) != 0)
1700 {
1701 xstate_bv |= X86_XSTATE_PKRU;
1702 memcpy (p, raw, 4);
1703 }
1704 }
1705
1706 /* Check if any ZMMH registers are changed. */
1707 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1708 for (i = I387_ZMM16H_REGNUM (tdep);
1709 i < I387_ZMMENDH_REGNUM (tdep); i++)
1710 {
1711 regcache->raw_collect (i, raw);
1712 p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i);
1713 if (memcmp (raw, p, 32) != 0)
1714 {
1715 xstate_bv |= X86_XSTATE_ZMM;
1716 memcpy (p, raw, 32);
1717 }
1718 }
1719
1720 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1721 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1722 {
1723 regcache->raw_collect (i, raw);
1724 p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i);
1725 if (memcmp (raw, p, 32) != 0)
1726 {
1727 xstate_bv |= X86_XSTATE_ZMM_H;
1728 memcpy (p, raw, 32);
1729 }
1730 }
1731
1732 /* Check if any K registers are changed. */
1733 if ((tdep->xcr0 & X86_XSTATE_K))
1734 for (i = I387_K0_REGNUM (tdep);
1735 i < I387_KEND_REGNUM (tdep); i++)
1736 {
1737 regcache->raw_collect (i, raw);
1738 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1739 if (memcmp (raw, p, 8) != 0)
1740 {
1741 xstate_bv |= X86_XSTATE_K;
1742 memcpy (p, raw, 8);
1743 }
1744 }
1745
1746 /* Check if any XMM or upper YMM registers are changed. */
1747 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1748 {
1749 for (i = I387_YMM16H_REGNUM (tdep);
1750 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1751 {
1752 regcache->raw_collect (i, raw);
1753 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1754 if (memcmp (raw, p, 16) != 0)
1755 {
1756 xstate_bv |= X86_XSTATE_ZMM;
1757 memcpy (p, raw, 16);
1758 }
1759 }
1760 for (i = I387_XMM16_REGNUM (tdep);
1761 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1762 {
1763 regcache->raw_collect (i, raw);
1764 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1765 if (memcmp (raw, p, 16) != 0)
1766 {
1767 xstate_bv |= X86_XSTATE_ZMM;
1768 memcpy (p, raw, 16);
1769 }
1770 }
1771 }
1772
1773 /* Check if any upper MPX registers are changed. */
1774 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1775 for (i = I387_BND0R_REGNUM (tdep);
1776 i < I387_BNDCFGU_REGNUM (tdep); i++)
1777 {
1778 regcache->raw_collect (i, raw);
1779 p = XSAVE_BNDREGS_ADDR (tdep, regs, i);
1780 if (memcmp (raw, p, 16))
1781 {
1782 xstate_bv |= X86_XSTATE_BNDREGS;
1783 memcpy (p, raw, 16);
1784 }
1785 }
1786
1787 /* Check if any upper MPX registers are changed. */
1788 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1789 for (i = I387_BNDCFGU_REGNUM (tdep);
1790 i < I387_MPXEND_REGNUM (tdep); i++)
1791 {
1792 regcache->raw_collect (i, raw);
1793 p = XSAVE_BNDCFG_ADDR (tdep, regs, i);
1794 if (memcmp (raw, p, 8))
1795 {
1796 xstate_bv |= X86_XSTATE_BNDCFG;
1797 memcpy (p, raw, 8);
1798 }
1799 }
1800
1801 /* Check if any upper YMM registers are changed. */
1802 if ((tdep->xcr0 & X86_XSTATE_AVX))
1803 for (i = I387_YMM0H_REGNUM (tdep);
1804 i < I387_YMMENDH_REGNUM (tdep); i++)
1805 {
1806 regcache->raw_collect (i, raw);
1807 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1808 if (memcmp (raw, p, 16))
1809 {
1810 xstate_bv |= X86_XSTATE_AVX;
1811 memcpy (p, raw, 16);
1812 }
1813 }
1814
1815 /* Check if any SSE registers are changed. */
1816 if ((tdep->xcr0 & X86_XSTATE_SSE))
1817 for (i = I387_XMM0_REGNUM (tdep);
1818 i < I387_MXCSR_REGNUM (tdep); i++)
1819 {
1820 regcache->raw_collect (i, raw);
1821 p = FXSAVE_ADDR (tdep, regs, i);
1822 if (memcmp (raw, p, 16))
1823 {
1824 xstate_bv |= X86_XSTATE_SSE;
1825 memcpy (p, raw, 16);
1826 }
1827 }
1828
1829 if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE))
1830 {
1831 i = I387_MXCSR_REGNUM (tdep);
1832 regcache->raw_collect (i, raw);
1833 p = FXSAVE_MXCSR_ADDR (regs);
1834 if (memcmp (raw, p, 4))
1835 {
1836 /* Now, we need to mark one of either SSE of AVX as enabled.
1837 We could pick either. What we do is check to see if one
1838 of the features is already enabled, if it is then we leave
1839 it at that, otherwise we pick SSE. */
1840 if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0)
1841 xstate_bv |= X86_XSTATE_SSE;
1842 memcpy (p, raw, 4);
1843 }
1844 }
1845
1846 /* Check if any X87 registers are changed. Only the non-control
1847 registers are handled here, the control registers are all handled
1848 later on in this function. */
1849 if ((tdep->xcr0 & X86_XSTATE_X87))
1850 for (i = I387_ST0_REGNUM (tdep);
1851 i < I387_FCTRL_REGNUM (tdep); i++)
1852 {
1853 regcache->raw_collect (i, raw);
1854 p = FXSAVE_ADDR (tdep, regs, i);
1855 if (memcmp (raw, p, 10))
1856 {
1857 xstate_bv |= X86_XSTATE_X87;
1858 memcpy (p, raw, 10);
1859 }
1860 }
1861 }
1862 else
1863 {
1864 /* Check if REGNUM is changed. */
1865 regcache->raw_collect (regnum, raw);
1866
1867 switch (regclass)
1868 {
1869 default:
1870 internal_error (_("invalid i387 regclass"));
1871
1872 case pkeys:
1873 /* This is a PKEYS register. */
1874 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1875 if (memcmp (raw, p, 4) != 0)
1876 {
1877 xstate_bv |= X86_XSTATE_PKRU;
1878 memcpy (p, raw, 4);
1879 }
1880 break;
1881
1882 case avx512_zmm16_h:
1883 /* This is a ZMM16-31 register. */
1884 p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum);
1885 if (memcmp (raw, p, 32) != 0)
1886 {
1887 xstate_bv |= X86_XSTATE_ZMM;
1888 memcpy (p, raw, 32);
1889 }
1890 break;
1891
1892 case avx512_zmm0_h:
1893 /* This is a ZMM0-15 register. */
1894 p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum);
1895 if (memcmp (raw, p, 32) != 0)
1896 {
1897 xstate_bv |= X86_XSTATE_ZMM_H;
1898 memcpy (p, raw, 32);
1899 }
1900 break;
1901
1902 case avx512_k:
1903 /* This is a AVX512 mask register. */
1904 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1905 if (memcmp (raw, p, 8) != 0)
1906 {
1907 xstate_bv |= X86_XSTATE_K;
1908 memcpy (p, raw, 8);
1909 }
1910 break;
1911
1912 case avx512_ymmh_avx512:
1913 /* This is an upper YMM16-31 register. */
1914 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1915 if (memcmp (raw, p, 16) != 0)
1916 {
1917 xstate_bv |= X86_XSTATE_ZMM;
1918 memcpy (p, raw, 16);
1919 }
1920 break;
1921
1922 case avx512_xmm_avx512:
1923 /* This is an upper XMM16-31 register. */
1924 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1925 if (memcmp (raw, p, 16) != 0)
1926 {
1927 xstate_bv |= X86_XSTATE_ZMM;
1928 memcpy (p, raw, 16);
1929 }
1930 break;
1931
1932 case avxh:
1933 /* This is an upper YMM register. */
1934 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1935 if (memcmp (raw, p, 16))
1936 {
1937 xstate_bv |= X86_XSTATE_AVX;
1938 memcpy (p, raw, 16);
1939 }
1940 break;
1941
1942 case bndregs:
1943 regcache->raw_collect (regnum, raw);
1944 p = XSAVE_BNDREGS_ADDR (tdep, regs, regnum);
1945 if (memcmp (raw, p, 16))
1946 {
1947 xstate_bv |= X86_XSTATE_BNDREGS;
1948 memcpy (p, raw, 16);
1949 }
1950 break;
1951
1952 case bndcfg:
1953 p = XSAVE_BNDCFG_ADDR (tdep, regs, regnum);
1954 xstate_bv |= X86_XSTATE_BNDCFG;
1955 memcpy (p, raw, 8);
1956 break;
1957
1958 case sse:
1959 /* This is an SSE register. */
1960 p = FXSAVE_ADDR (tdep, regs, regnum);
1961 if (memcmp (raw, p, 16))
1962 {
1963 xstate_bv |= X86_XSTATE_SSE;
1964 memcpy (p, raw, 16);
1965 }
1966 break;
1967
1968 case x87:
1969 /* This is an x87 register. */
1970 p = FXSAVE_ADDR (tdep, regs, regnum);
1971 if (memcmp (raw, p, 10))
1972 {
1973 xstate_bv |= X86_XSTATE_X87;
1974 memcpy (p, raw, 10);
1975 }
1976 break;
1977
1978 case x87_ctrl_or_mxcsr:
1979 /* We only handle MXCSR here. All other x87 control registers
1980 are handled separately below. */
1981 if (regnum == I387_MXCSR_REGNUM (tdep))
1982 {
1983 p = FXSAVE_MXCSR_ADDR (regs);
1984 if (memcmp (raw, p, 2))
1985 {
1986 /* We're only setting MXCSR, so check the initial state
1987 to see if either of AVX or SSE are already enabled.
1988 If they are then we'll attribute this changed MXCSR to
1989 that feature. If neither feature is enabled, then
1990 we'll attribute this change to the SSE feature. */
1991 xstate_bv |= (initial_xstate_bv
1992 & (X86_XSTATE_AVX | X86_XSTATE_SSE));
1993 if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0)
1994 xstate_bv |= X86_XSTATE_SSE;
1995 memcpy (p, raw, 2);
1996 }
1997 }
1998 }
1999 }
2000
2001 /* Only handle x87 control registers. */
2002 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
2003 if (regnum == -1 || regnum == i)
2004 {
2005 /* Most of the FPU control registers occupy only 16 bits in
2006 the xsave extended state. Give those a special treatment. */
2007 if (i != I387_FIOFF_REGNUM (tdep)
2008 && i != I387_FOOFF_REGNUM (tdep))
2009 {
2010 gdb_byte buf[4];
2011
2012 regcache->raw_collect (i, buf);
2013
2014 if (i == I387_FOP_REGNUM (tdep))
2015 {
2016 /* The opcode occupies only 11 bits. Make sure we
2017 don't touch the other bits. */
2018 buf[1] &= ((1 << 3) - 1);
2019 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
2020 }
2021 else if (i == I387_FTAG_REGNUM (tdep))
2022 {
2023 /* Converting back is much easier. */
2024
2025 unsigned short ftag;
2026 int fpreg;
2027
2028 ftag = (buf[1] << 8) | buf[0];
2029 buf[0] = 0;
2030 buf[1] = 0;
2031
2032 for (fpreg = 7; fpreg >= 0; fpreg--)
2033 {
2034 int tag = (ftag >> (fpreg * 2)) & 3;
2035
2036 if (tag != 3)
2037 buf[0] |= (1 << fpreg);
2038 }
2039 }
2040 p = FXSAVE_ADDR (tdep, regs, i);
2041 if (memcmp (p, buf, 2))
2042 {
2043 xstate_bv |= X86_XSTATE_X87;
2044 memcpy (p, buf, 2);
2045 }
2046 }
2047 else
2048 {
2049 int regsize;
2050
2051 regcache->raw_collect (i, raw);
2052 regsize = regcache_register_size (regcache, i);
2053 p = FXSAVE_ADDR (tdep, regs, i);
2054 if (memcmp (raw, p, regsize))
2055 {
2056 xstate_bv |= X86_XSTATE_X87;
2057 memcpy (p, raw, regsize);
2058 }
2059 }
2060 }
2061
2062 /* Update the corresponding bits in `xstate_bv' if any
2063 registers are changed. */
2064 if (xstate_bv)
2065 {
2066 /* The supported bits in `xstat_bv' are 8 bytes. */
2067 initial_xstate_bv |= xstate_bv;
2068 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
2069 8, byte_order,
2070 initial_xstate_bv);
2071 }
2072 }
2073
2074 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
2075 *RAW. */
2076
2077 static int
2078 i387_tag (const gdb_byte *raw)
2079 {
2080 int integer;
2081 unsigned int exponent;
2082 unsigned long fraction[2];
2083
2084 integer = raw[7] & 0x80;
2085 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
2086 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
2087 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
2088 | (raw[5] << 8) | raw[4]);
2089
2090 if (exponent == 0x7fff)
2091 {
2092 /* Special. */
2093 return (2);
2094 }
2095 else if (exponent == 0x0000)
2096 {
2097 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
2098 {
2099 /* Zero. */
2100 return (1);
2101 }
2102 else
2103 {
2104 /* Special. */
2105 return (2);
2106 }
2107 }
2108 else
2109 {
2110 if (integer)
2111 {
2112 /* Valid. */
2113 return (0);
2114 }
2115 else
2116 {
2117 /* Special. */
2118 return (2);
2119 }
2120 }
2121 }
2122
2123 /* Prepare the FPU stack in REGCACHE for a function return. */
2124
2125 void
2126 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
2127 {
2128 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2129 ULONGEST fstat;
2130
2131 /* Set the top of the floating-point register stack to 7. The
2132 actual value doesn't really matter, but 7 is what a normal
2133 function return would end up with if the program started out with
2134 a freshly initialized FPU. */
2135 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2136 fstat |= (7 << 11);
2137 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2138
2139 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
2140 floating-point register stack to 7, the appropriate value for the
2141 tag word is 0x3fff. */
2142 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2143
2144 }
2145
2146 /* See i387-tdep.h. */
2147
2148 void
2149 i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache)
2150 {
2151 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2152
2153 if (I387_BND0R_REGNUM (tdep) > 0)
2154 {
2155 gdb_byte bnd_buf[16];
2156
2157 memset (bnd_buf, 0, 16);
2158 for (int i = 0; i < I387_NUM_BND_REGS; i++)
2159 regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf);
2160 }
2161 }
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