gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "gdb/sim-lm32.h"
  31 #include "gdb/callback.h"
  32 #include "gdb/remote-sim.h"
  33 #include "sim-regno.h"
  34 #include "arch-utils.h"
  35 #include "regcache.h"
  36 #include "trad-frame.h"
  37 #include "reggroups.h"
  38 #include "../opcodes/lm32-desc.h"
  39 #include <algorithm>
  40
  41 /* Macros to extract fields from an instruction.  */
  42 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  43 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  44 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  45 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  46 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  47
  48 struct gdbarch_tdep
  49 {
  50   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  51 };
  52
  53 struct lm32_frame_cache
  54 {
  55   /* The frame's base.  Used when constructing a frame ID.  */
  56   CORE_ADDR base;
  57   CORE_ADDR pc;
  58   /* Size of frame.  */
  59   int size;
  60   /* Table indicating the location of each and every register.  */
  61   struct trad_frame_saved_reg *saved_regs;
  62 };
  63
  64 /* Add the available register groups.  */
  65
  66 static void
  67 lm32_add_reggroups (struct gdbarch *gdbarch)
  68 {
  69   reggroup_add (gdbarch, general_reggroup);
  70   reggroup_add (gdbarch, all_reggroup);
  71   reggroup_add (gdbarch, system_reggroup);
  72 }
  73
  74 /* Return whether a given register is in a given group.  */
  75
  76 static int
  77 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  78                           struct reggroup *group)
  79 {
  80   if (group == general_reggroup)
  81     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  82       || (regnum == SIM_LM32_PC_REGNUM);
  83   else if (group == system_reggroup)
  84     return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
  85       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  86   return default_register_reggroup_p (gdbarch, regnum, group);
  87 }
  88
  89 /* Return a name that corresponds to the given register number.  */
  90
  91 static const char *
  92 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  93 {
  94   static const char *register_names[] = {
  95     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  96     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  97     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  98     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
  99     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
 100   };
 101
 102   if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
 103     return NULL;
 104   else
 105     return register_names[reg_nr];
 106 }
 107
 108 /* Return type of register.  */
 109
 110 static struct type *
 111 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 112 {
 113   return builtin_type (gdbarch)->builtin_int32;
 114 }
 115
 116 /* Return non-zero if a register can't be written.  */
 117
 118 static int
 119 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 120 {
 121   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 122 }
 123
 124 /* Analyze a function's prologue.  */
 125
 126 static CORE_ADDR
 127 lm32_analyze_prologue (struct gdbarch *gdbarch,
 128                        CORE_ADDR pc, CORE_ADDR limit,
 129                        struct lm32_frame_cache *info)
 130 {
 131   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 132   unsigned long instruction;
 133
 134   /* Keep reading though instructions, until we come across an instruction
 135      that isn't likely to be part of the prologue.  */
 136   info->size = 0;
 137   for (; pc < limit; pc += 4)
 138     {
 139
 140       /* Read an instruction.  */
 141       instruction = read_memory_integer (pc, 4, byte_order);
 142
 143       if ((LM32_OPCODE (instruction) == OP_SW)
 144           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 145         {
 146           /* Any stack displaced store is likely part of the prologue.
 147              Record that the register is being saved, and the offset
 148              into the stack.  */
 149           info->saved_regs[LM32_REG1 (instruction)].addr =
 150             LM32_IMM16 (instruction);
 151         }
 152       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 153                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 154         {
 155           /* An add to the SP is likely to be part of the prologue.
 156              Adjust stack size by whatever the instruction adds to the sp.  */
 157           info->size -= LM32_IMM16 (instruction);
 158         }
 159       else if (                 /* add fp,fp,sp */
 160                 ((LM32_OPCODE (instruction) == OP_ADD)
 161                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 162                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 163                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 164                 /* mv fp,imm */
 165                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 166                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 167                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 168         {
 169           /* Likely to be in the prologue for functions that require
 170              a frame pointer.  */
 171         }
 172       else
 173         {
 174           /* Any other instruction is likely not to be part of the
 175              prologue.  */
 176           break;
 177         }
 178     }
 179
 180   return pc;
 181 }
 182
 183 /* Return PC of first non prologue instruction, for the function at the
 184    specified address.  */
 185
 186 static CORE_ADDR
 187 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 188 {
 189   CORE_ADDR func_addr, limit_pc;
 190   struct lm32_frame_cache frame_info;
 191   struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 192
 193   /* See if we can determine the end of the prologue via the symbol table.
 194      If so, then return either PC, or the PC after the prologue, whichever
 195      is greater.  */
 196   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 197     {
 198       CORE_ADDR post_prologue_pc
 199         = skip_prologue_using_sal (gdbarch, func_addr);
 200       if (post_prologue_pc != 0)
 201         return std::max (pc, post_prologue_pc);
 202     }
 203
 204   /* Can't determine prologue from the symbol table, need to examine
 205      instructions.  */
 206
 207   /* Find an upper limit on the function prologue using the debug
 208      information.  If the debug information could not be used to provide
 209      that bound, then use an arbitrary large number as the upper bound.  */
 210   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 211   if (limit_pc == 0)
 212     limit_pc = pc + 100;        /* Magic.  */
 213
 214   frame_info.saved_regs = saved_regs;
 215   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 216 }
 217
 218 /* Create a breakpoint instruction.  */
 219 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
 220
 221 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
 222
 223
 224 /* Setup registers and stack for faking a call to a function in the
 225    inferior.  */
 226
 227 static CORE_ADDR
 228 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 229                       struct regcache *regcache, CORE_ADDR bp_addr,
 230                       int nargs, struct value **args, CORE_ADDR sp,
 231                       function_call_return_method return_method,
 232                       CORE_ADDR struct_addr)
 233 {
 234   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 235   int first_arg_reg = SIM_LM32_R1_REGNUM;
 236   int num_arg_regs = 8;
 237   int i;
 238
 239   /* Set the return address.  */
 240   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 241
 242   /* If we're returning a large struct, a pointer to the address to
 243      store it at is passed as a first hidden parameter.  */
 244   if (return_method == return_method_struct)
 245     {
 246       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 247       first_arg_reg++;
 248       num_arg_regs--;
 249       sp -= 4;
 250     }
 251
 252   /* Setup parameters.  */
 253   for (i = 0; i < nargs; i++)
 254     {
 255       struct value *arg = args[i];
 256       struct type *arg_type = check_typedef (value_type (arg));
 257       gdb_byte *contents;
 258       ULONGEST val;
 259
 260       /* Promote small integer types to int.  */
 261       switch (TYPE_CODE (arg_type))
 262         {
 263         case TYPE_CODE_INT:
 264         case TYPE_CODE_BOOL:
 265         case TYPE_CODE_CHAR:
 266         case TYPE_CODE_RANGE:
 267         case TYPE_CODE_ENUM:
 268           if (TYPE_LENGTH (arg_type) < 4)
 269             {
 270               arg_type = builtin_type (gdbarch)->builtin_int32;
 271               arg = value_cast (arg_type, arg);
 272             }
 273           break;
 274         }
 275
 276       /* FIXME: Handle structures.  */
 277
 278       contents = (gdb_byte *) value_contents (arg);
 279       val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type),
 280                                       byte_order);
 281
 282       /* First num_arg_regs parameters are passed by registers,
 283          and the rest are passed on the stack.  */
 284       if (i < num_arg_regs)
 285         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 286       else
 287         {
 288           write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order,
 289                                          val);
 290           sp -= 4;
 291         }
 292     }
 293
 294   /* Update stack pointer.  */
 295   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 296
 297   /* Return adjusted stack pointer.  */
 298   return sp;
 299 }
 300
 301 /* Extract return value after calling a function in the inferior.  */
 302
 303 static void
 304 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 305                            gdb_byte *valbuf)
 306 {
 307   struct gdbarch *gdbarch = regcache->arch ();
 308   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 309   ULONGEST l;
 310   CORE_ADDR return_buffer;
 311
 312   if (TYPE_CODE (type) != TYPE_CODE_STRUCT
 313       && TYPE_CODE (type) != TYPE_CODE_UNION
 314       && TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
 315     {
 316       /* Return value is returned in a single register.  */
 317       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 318       store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
 319     }
 320   else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
 321     {
 322       /* 64-bit values are returned in a register pair.  */
 323       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 324       memcpy (valbuf, &l, 4);
 325       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 326       memcpy (valbuf + 4, &l, 4);
 327     }
 328   else
 329     {
 330       /* Aggregate types greater than a single register are returned
 331          in memory.  FIXME: Unless they are only 2 regs?.  */
 332       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 333       return_buffer = l;
 334       read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
 335     }
 336 }
 337
 338 /* Write into appropriate registers a function return value of type
 339    TYPE, given in virtual format.  */
 340 static void
 341 lm32_store_return_value (struct type *type, struct regcache *regcache,
 342                          const gdb_byte *valbuf)
 343 {
 344   struct gdbarch *gdbarch = regcache->arch ();
 345   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 346   ULONGEST val;
 347   int len = TYPE_LENGTH (type);
 348
 349   if (len <= 4)
 350     {
 351       val = extract_unsigned_integer (valbuf, len, byte_order);
 352       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 353     }
 354   else if (len <= 8)
 355     {
 356       val = extract_unsigned_integer (valbuf, 4, byte_order);
 357       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 358       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 359       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 360     }
 361   else
 362     error (_("lm32_store_return_value: type length too large."));
 363 }
 364
 365 /* Determine whether a functions return value is in a register or memory.  */
 366 static enum return_value_convention
 367 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
 368                    struct type *valtype, struct regcache *regcache,
 369                    gdb_byte *readbuf, const gdb_byte *writebuf)
 370 {
 371   enum type_code code = TYPE_CODE (valtype);
 372
 373   if (code == TYPE_CODE_STRUCT
 374       || code == TYPE_CODE_UNION
 375       || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
 376     return RETURN_VALUE_STRUCT_CONVENTION;
 377
 378   if (readbuf)
 379     lm32_extract_return_value (valtype, regcache, readbuf);
 380   if (writebuf)
 381     lm32_store_return_value (valtype, regcache, writebuf);
 382
 383   return RETURN_VALUE_REGISTER_CONVENTION;
 384 }
 385
 386 static CORE_ADDR
 387 lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 388 {
 389   return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
 390 }
 391
 392 static CORE_ADDR
 393 lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
 394 {
 395   return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
 396 }
 397
 398 static struct frame_id
 399 lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
 400 {
 401   CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 402
 403   return frame_id_build (sp, get_frame_pc (this_frame));
 404 }
 405
 406 /* Put here the code to store, into fi->saved_regs, the addresses of
 407    the saved registers of frame described by FRAME_INFO.  This
 408    includes special registers such as pc and fp saved in special ways
 409    in the stack frame.  sp is even more special: the address we return
 410    for it IS the sp for the next frame.  */
 411
 412 static struct lm32_frame_cache *
 413 lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
 414 {
 415   CORE_ADDR current_pc;
 416   ULONGEST prev_sp;
 417   ULONGEST this_base;
 418   struct lm32_frame_cache *info;
 419   int i;
 420
 421   if ((*this_prologue_cache))
 422     return (struct lm32_frame_cache *) (*this_prologue_cache);
 423
 424   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 425   (*this_prologue_cache) = info;
 426   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 427
 428   info->pc = get_frame_func (this_frame);
 429   current_pc = get_frame_pc (this_frame);
 430   lm32_analyze_prologue (get_frame_arch (this_frame),
 431                          info->pc, current_pc, info);
 432
 433   /* Compute the frame's base, and the previous frame's SP.  */
 434   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 435   prev_sp = this_base + info->size;
 436   info->base = this_base;
 437
 438   /* Convert callee save offsets into addresses.  */
 439   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 440     {
 441       if (trad_frame_addr_p (info->saved_regs, i))
 442         info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
 443     }
 444
 445   /* The call instruction moves the caller's PC in the callee's RA register.
 446      Since this is an unwind, do the reverse.  Copy the location of RA register
 447      into PC (the address / regnum) so that a request for PC will be
 448      converted into a request for the RA register.  */
 449   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 450
 451   /* The previous frame's SP needed to be computed.  Save the computed
 452      value.  */
 453   trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
 454
 455   return info;
 456 }
 457
 458 static void
 459 lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
 460                     struct frame_id *this_id)
 461 {
 462   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 463
 464   /* This marks the outermost frame.  */
 465   if (cache->base == 0)
 466     return;
 467
 468   (*this_id) = frame_id_build (cache->base, cache->pc);
 469 }
 470
 471 static struct value *
 472 lm32_frame_prev_register (struct frame_info *this_frame,
 473                           void **this_prologue_cache, int regnum)
 474 {
 475   struct lm32_frame_cache *info;
 476
 477   info = lm32_frame_cache (this_frame, this_prologue_cache);
 478   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 479 }
 480
 481 static const struct frame_unwind lm32_frame_unwind = {
 482   NORMAL_FRAME,
 483   default_frame_unwind_stop_reason,
 484   lm32_frame_this_id,
 485   lm32_frame_prev_register,
 486   NULL,
 487   default_frame_sniffer
 488 };
 489
 490 static CORE_ADDR
 491 lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
 492 {
 493   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 494
 495   return info->base;
 496 }
 497
 498 static const struct frame_base lm32_frame_base = {
 499   &lm32_frame_unwind,
 500   lm32_frame_base_address,
 501   lm32_frame_base_address,
 502   lm32_frame_base_address
 503 };
 504
 505 static CORE_ADDR
 506 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 507 {
 508   /* Align to the size of an instruction (so that they can safely be
 509      pushed onto the stack.  */
 510   return sp & ~3;
 511 }
 512
 513 static struct gdbarch *
 514 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 515 {
 516   struct gdbarch *gdbarch;
 517   struct gdbarch_tdep *tdep;
 518
 519   /* If there is already a candidate, use it.  */
 520   arches = gdbarch_list_lookup_by_info (arches, &info);
 521   if (arches != NULL)
 522     return arches->gdbarch;
 523
 524   /* None found, create a new architecture from the information provided.  */
 525   tdep = XCNEW (struct gdbarch_tdep);
 526   gdbarch = gdbarch_alloc (&info, tdep);
 527
 528   /* Type sizes.  */
 529   set_gdbarch_short_bit (gdbarch, 16);
 530   set_gdbarch_int_bit (gdbarch, 32);
 531   set_gdbarch_long_bit (gdbarch, 32);
 532   set_gdbarch_long_long_bit (gdbarch, 64);
 533   set_gdbarch_float_bit (gdbarch, 32);
 534   set_gdbarch_double_bit (gdbarch, 64);
 535   set_gdbarch_long_double_bit (gdbarch, 64);
 536   set_gdbarch_ptr_bit (gdbarch, 32);
 537
 538   /* Register info.  */
 539   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 540   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 541   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 542   set_gdbarch_register_name (gdbarch, lm32_register_name);
 543   set_gdbarch_register_type (gdbarch, lm32_register_type);
 544   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 545
 546   /* Frame info.  */
 547   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 548   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 549   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 550   set_gdbarch_frame_args_skip (gdbarch, 0);
 551
 552   /* Frame unwinding.  */
 553   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 554   frame_base_set_default (gdbarch, &lm32_frame_base);
 555   set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
 556   set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
 557   set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
 558   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 559
 560   /* Breakpoints.  */
 561   set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
 562   set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
 563   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 564
 565   /* Calling functions in the inferior.  */
 566   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 567   set_gdbarch_return_value (gdbarch, lm32_return_value);
 568
 569   lm32_add_reggroups (gdbarch);
 570   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 571
 572   return gdbarch;
 573 }
 574
 575 void
 576 _initialize_lm32_tdep (void)
 577 {
 578   register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
 579 }