gdb/riscv-linux-tdep.c

   1 /* Target-dependent code for GNU/Linux on RISC-V processors.
   2    Copyright (C) 2018-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "defs.h"
  20 #include "riscv-tdep.h"
  21 #include "osabi.h"
  22 #include "glibc-tdep.h"
  23 #include "linux-tdep.h"
  24 #include "solib-svr4.h"
  25 #include "regset.h"
  26 #include "tramp-frame.h"
  27 #include "trad-frame.h"
  28 #include "gdbarch.h"
  29
  30 /* Define the general register mapping.  The kernel puts the PC at offset 0,
  31    gdb puts it at offset 32.  Register x0 is always 0 and can be ignored.
  32    Registers x1 to x31 are in the same place.  */
  33
  34 static const struct regcache_map_entry riscv_linux_gregmap[] =
  35 {
  36   { 1,  RISCV_PC_REGNUM, 0 },
  37   { 31, RISCV_RA_REGNUM, 0 }, /* x1 to x31 */
  38   { 0 }
  39 };
  40
  41 /* Define the FP register mapping.  The kernel puts the 32 FP regs first, and
  42    then FCSR.  */
  43
  44 static const struct regcache_map_entry riscv_linux_fregmap[] =
  45 {
  46   { 32, RISCV_FIRST_FP_REGNUM, 0 },
  47   { 1, RISCV_CSR_FCSR_REGNUM, 0 },
  48   { 0 }
  49 };
  50
  51 /* Define the general register regset.  */
  52
  53 static const struct regset riscv_linux_gregset =
  54 {
  55   riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset
  56 };
  57
  58 /* Define the FP register regset.  */
  59
  60 static const struct regset riscv_linux_fregset =
  61 {
  62   riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset
  63 };
  64
  65 /* Define hook for core file support.  */
  66
  67 static void
  68 riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
  69                                           iterate_over_regset_sections_cb *cb,
  70                                           void *cb_data,
  71                                           const struct regcache *regcache)
  72 {
  73   cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),
  74       &riscv_linux_gregset, NULL, cb_data);
  75   /* The kernel is adding 8 bytes for FCSR.  */
  76   cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,
  77       (32 * riscv_isa_flen (gdbarch)) + 8,
  78       &riscv_linux_fregset, NULL, cb_data);
  79 }
  80
  81 /* Signal trampoline support.  */
  82
  83 static void riscv_linux_sigframe_init (const struct tramp_frame *self,
  84                                        struct frame_info *this_frame,
  85                                        struct trad_frame_cache *this_cache,
  86                                        CORE_ADDR func);
  87
  88 #define RISCV_INST_LI_A7_SIGRETURN      0x08b00893
  89 #define RISCV_INST_ECALL                0x00000073
  90
  91 static const struct tramp_frame riscv_linux_sigframe = {
  92   SIGTRAMP_FRAME,
  93   4,
  94   {
  95     { RISCV_INST_LI_A7_SIGRETURN, ULONGEST_MAX },
  96     { RISCV_INST_ECALL, ULONGEST_MAX },
  97     { TRAMP_SENTINEL_INSN }
  98   },
  99   riscv_linux_sigframe_init,
 100   NULL
 101 };
 102
 103 /* Runtime signal frames look like this:
 104    struct rt_sigframe {
 105      struct siginfo info;
 106      struct ucontext uc;
 107    };
 108
 109    struct ucontext {
 110      unsigned long __uc_flags;
 111      struct ucontext *uclink;
 112      stack_t uc_stack;
 113      sigset_t uc_sigmask;
 114      char __glibc_reserved[1024 / 8 - sizeof (sigset_t)];
 115      mcontext_t uc_mcontext;
 116    }; */
 117
 118 #define SIGFRAME_SIGINFO_SIZE           128
 119 #define UCONTEXT_MCONTEXT_OFFSET        176
 120
 121 static void
 122 riscv_linux_sigframe_init (const struct tramp_frame *self,
 123                            struct frame_info *this_frame,
 124                            struct trad_frame_cache *this_cache,
 125                            CORE_ADDR func)
 126 {
 127   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 128   int xlen = riscv_isa_xlen (gdbarch);
 129   int flen = riscv_isa_flen (gdbarch);
 130   CORE_ADDR frame_sp = get_frame_sp (this_frame);
 131   CORE_ADDR mcontext_base;
 132   CORE_ADDR regs_base;
 133
 134   mcontext_base = frame_sp + SIGFRAME_SIGINFO_SIZE + UCONTEXT_MCONTEXT_OFFSET;
 135
 136   /* Handle the integer registers.  The first one is PC, followed by x1
 137      through x31.  */
 138   regs_base = mcontext_base;
 139   trad_frame_set_reg_addr (this_cache, RISCV_PC_REGNUM, regs_base);
 140   for (int i = 1; i < 32; i++)
 141     trad_frame_set_reg_addr (this_cache, RISCV_ZERO_REGNUM + i,
 142                              regs_base + (i * xlen));
 143
 144   /* Handle the FP registers.  First comes the 32 FP registers, followed by
 145      fcsr.  */
 146   regs_base += 32 * xlen;
 147   for (int i = 0; i < 32; i++)
 148     trad_frame_set_reg_addr (this_cache, RISCV_FIRST_FP_REGNUM + i,
 149                              regs_base + (i * flen));
 150   regs_base += 32 * flen;
 151   trad_frame_set_reg_addr (this_cache, RISCV_CSR_FCSR_REGNUM, regs_base);
 152
 153   /* Choice of the bottom of the sigframe is somewhat arbitrary.  */
 154   trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
 155 }
 156
 157 /* Initialize RISC-V Linux ABI info.  */
 158
 159 static void
 160 riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 161 {
 162   linux_init_abi (info, gdbarch);
 163
 164   set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
 165
 166   set_solib_svr4_fetch_link_map_offsets (gdbarch,
 167                                          (riscv_isa_xlen (gdbarch) == 4
 168                                           ? svr4_ilp32_fetch_link_map_offsets
 169                                           : svr4_lp64_fetch_link_map_offsets));
 170
 171   /* GNU/Linux uses SVR4-style shared libraries.  */
 172   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
 173
 174   /* GNU/Linux uses the dynamic linker included in the GNU C Library.  */
 175   set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
 176
 177   /* Enable TLS support.  */
 178   set_gdbarch_fetch_tls_load_module_address (gdbarch,
 179                                              svr4_fetch_objfile_link_map);
 180
 181   set_gdbarch_iterate_over_regset_sections
 182     (gdbarch, riscv_linux_iterate_over_regset_sections);
 183
 184   tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
 185 }
 186
 187 /* Initialize RISC-V Linux target support.  */
 188
 189 void _initialize_riscv_linux_tdep ();
 190 void
 191 _initialize_riscv_linux_tdep ()
 192 {
 193   gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
 194                           riscv_linux_init_abi);
 195 }