1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Cached information about a frame. */
78 struct riscv_unwind_cache
80 /* The register from which we can calculate the frame base. This is
81 usually $sp or $fp. */
84 /* The offset from the current value in register FRAME_BASE_REG to the
85 actual frame base address. */
86 int frame_base_offset
;
88 /* Information about previous register values. */
89 struct trad_frame_saved_reg
*regs
;
91 /* The id for this frame. */
92 struct frame_id this_id
;
94 /* The base (stack) address for this frame. This is the stack pointer
95 value on entry to this frame before any adjustments are made. */
99 /* RISC-V specific register group for CSRs. */
101 static reggroup
*csr_reggroup
= NULL
;
103 /* A set of registers that we expect to find in a tdesc_feature. These
104 are use in RISCV_GDBARCH_INIT when processing the target description. */
106 struct riscv_register_feature
108 /* Information for a single register. */
111 /* The GDB register number for this register. */
114 /* List of names for this register. The first name in this list is the
115 preferred name, the name GDB should use when describing this
117 std::vector
<const char *> names
;
119 /* When true this register is required in this feature set. */
123 /* The name for this feature. This is the name used to find this feature
124 within the target description. */
127 /* List of all the registers that we expect that we might find in this
129 std::vector
<struct register_info
> registers
;
132 /* The general x-registers feature set. */
134 static const struct riscv_register_feature riscv_xreg_feature
=
136 "org.gnu.gdb.riscv.cpu",
138 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" }, true },
139 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" }, true },
140 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" }, true },
141 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" }, true },
142 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" }, true },
143 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" }, true },
144 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" }, true },
145 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" }, true },
146 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" }, true },
147 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" }, true },
148 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" }, true },
149 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" }, true },
150 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" }, true },
151 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" }, true },
152 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" }, true },
153 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" }, true },
154 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" }, true },
155 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" }, true },
156 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" }, true },
157 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" }, true },
158 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" }, true },
159 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" }, true },
160 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" }, true },
161 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" }, true },
162 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" }, true },
163 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" }, true },
164 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" }, true },
165 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" }, true },
166 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" }, true },
167 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" }, true },
168 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" }, true },
169 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" }, true },
170 { RISCV_ZERO_REGNUM
+ 32, { "pc" }, true }
174 /* The f-registers feature set. */
176 static const struct riscv_register_feature riscv_freg_feature
=
178 "org.gnu.gdb.riscv.fpu",
180 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" }, true },
181 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" }, true },
182 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" }, true },
183 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" }, true },
184 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" }, true },
185 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" }, true },
186 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" }, true },
187 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" }, true },
188 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" }, true },
189 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" }, true },
190 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" }, true },
191 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" }, true },
192 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" }, true },
193 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" }, true },
194 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" }, true },
195 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" }, true },
196 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" }, true },
197 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" }, true },
198 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" }, true },
199 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" }, true },
200 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" }, true },
201 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" }, true },
202 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" }, true },
203 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" }, true },
204 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" }, true },
205 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" }, true },
206 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" }, true },
207 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" }, true },
208 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" }, true },
209 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" }, true },
210 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" }, true },
211 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" }, true },
213 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags" }, true },
214 { RISCV_CSR_FRM_REGNUM
, { "frm" }, true },
215 { RISCV_CSR_FCSR_REGNUM
, { "fcsr" }, true },
220 /* Set of virtual registers. These are not physical registers on the
221 hardware, but might be available from the target. These are not pseudo
222 registers, reading these really does result in a register read from the
223 target, it is just that there might not be a physical register backing
226 static const struct riscv_register_feature riscv_virtual_feature
=
228 "org.gnu.gdb.riscv.virtual",
230 { RISCV_PRIV_REGNUM
, { "priv" }, false }
234 /* Feature set for CSRs. This set is NOT constant as the register names
235 list for each register is not complete. The aliases are computed
236 during RISCV_CREATE_CSR_ALIASES. */
238 static struct riscv_register_feature riscv_csr_feature
=
240 "org.gnu.gdb.riscv.csr",
242 #define DECLARE_CSR(NAME,VALUE) \
243 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
244 #include "opcode/riscv-opc.h"
249 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
250 to the name list for each register. */
253 riscv_create_csr_aliases ()
255 for (auto ®
: riscv_csr_feature
.registers
)
257 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
258 const char *alias
= xstrprintf ("csr%d", csr_num
);
259 reg
.names
.push_back (alias
);
263 /* Controls whether we place compressed breakpoints or not. When in auto
264 mode GDB tries to determine if the target supports compressed
265 breakpoints, and uses them if it does. */
267 static enum auto_boolean use_compressed_breakpoints
;
269 /* The show callback for 'show riscv use-compressed-breakpoints'. */
272 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("Debugger's use of compressed breakpoints is set "
281 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
283 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
284 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
286 /* The show callback for the 'show riscv' prefix command. */
289 show_riscv_command (const char *args
, int from_tty
)
291 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
294 /* The set callback for the 'set riscv' prefix command. */
297 set_riscv_command (const char *args
, int from_tty
)
300 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
301 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
304 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
306 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
307 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
309 /* The show callback for the 'show debug riscv' prefix command. */
312 show_debug_riscv_command (const char *args
, int from_tty
)
314 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
317 /* The set callback for the 'set debug riscv' prefix command. */
320 set_debug_riscv_command (const char *args
, int from_tty
)
323 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
324 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
327 /* The show callback for all 'show debug riscv VARNAME' variables. */
330 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
331 struct cmd_list_element
*c
,
334 fprintf_filtered (file
,
335 _("RiscV debug variable `%s' is set to: %s\n"),
339 /* When this is set to non-zero debugging information about breakpoint
340 kinds will be printed. */
342 static unsigned int riscv_debug_breakpoints
= 0;
344 /* When this is set to non-zero debugging information about inferior calls
347 static unsigned int riscv_debug_infcall
= 0;
349 /* When this is set to non-zero debugging information about stack unwinding
352 static unsigned int riscv_debug_unwinder
= 0;
354 /* When this is set to non-zero debugging information about gdbarch
355 initialisation will be printed. */
357 static unsigned int riscv_debug_gdbarch
= 0;
359 /* See riscv-tdep.h. */
362 riscv_isa_xlen (struct gdbarch
*gdbarch
)
364 return gdbarch_tdep (gdbarch
)->isa_features
.xlen
;
367 /* See riscv-tdep.h. */
370 riscv_abi_xlen (struct gdbarch
*gdbarch
)
372 return gdbarch_tdep (gdbarch
)->abi_features
.xlen
;
375 /* See riscv-tdep.h. */
378 riscv_isa_flen (struct gdbarch
*gdbarch
)
380 return gdbarch_tdep (gdbarch
)->isa_features
.flen
;
383 /* See riscv-tdep.h. */
386 riscv_abi_flen (struct gdbarch
*gdbarch
)
388 return gdbarch_tdep (gdbarch
)->abi_features
.flen
;
391 /* Return true if the target for GDBARCH has floating point hardware. */
394 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
396 return (riscv_isa_flen (gdbarch
) > 0);
399 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
402 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
404 return gdbarch_tdep (gdbarch
)->abi_features
.flen
> 0;
407 /* Return true if REGNO is a floating pointer register. */
410 riscv_is_fp_regno_p (int regno
)
412 return (regno
>= RISCV_FIRST_FP_REGNUM
413 && regno
<= RISCV_LAST_FP_REGNUM
);
416 /* Implement the breakpoint_kind_from_pc gdbarch method. */
419 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
421 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
423 bool unaligned_p
= false;
426 /* Some targets don't support unaligned reads. The address can only
427 be unaligned if the C extension is supported. So it is safe to
428 use a compressed breakpoint in this case. */
433 /* Read the opcode byte to determine the instruction length. */
434 read_code (*pcptr
, buf
, 1);
437 if (riscv_debug_breakpoints
)
439 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
440 ? "C.EBREAK" : "EBREAK");
442 fprintf_unfiltered (gdb_stdlog
, "Using %s for breakpoint at %s ",
443 bp
, paddress (gdbarch
, *pcptr
));
445 fprintf_unfiltered (gdb_stdlog
, "(unaligned address)\n");
447 fprintf_unfiltered (gdb_stdlog
, "(instruction length %d)\n",
448 riscv_insn_length (buf
[0]));
450 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
455 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
461 /* Implement the sw_breakpoint_from_kind gdbarch method. */
463 static const gdb_byte
*
464 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
466 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
467 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
477 gdb_assert_not_reached (_("unhandled breakpoint kind"));
481 /* Callback function for user_reg_add. */
483 static struct value
*
484 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
486 const int *reg_p
= (const int *) baton
;
487 return value_of_register (*reg_p
, frame
);
490 /* Implement the register_name gdbarch method. This is used instead of
491 the function supplied by calling TDESC_USE_REGISTERS so that we can
492 ensure the preferred names are offered. */
495 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
497 /* Lookup the name through the target description. If we get back NULL
498 then this is an unknown register. If we do get a name back then we
499 look up the registers preferred name below. */
500 const char *name
= tdesc_register_name (gdbarch
, regnum
);
501 if (name
== NULL
|| name
[0] == '\0')
504 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
506 gdb_assert (regnum
< riscv_xreg_feature
.registers
.size ());
507 return riscv_xreg_feature
.registers
[regnum
].names
[0];
510 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
512 if (riscv_has_fp_regs (gdbarch
))
514 regnum
-= RISCV_FIRST_FP_REGNUM
;
515 gdb_assert (regnum
< riscv_freg_feature
.registers
.size ());
516 return riscv_freg_feature
.registers
[regnum
].names
[0];
522 /* Check that there's no gap between the set of registers handled above,
523 and the set of registers handled next. */
524 gdb_assert ((RISCV_LAST_FP_REGNUM
+ 1) == RISCV_FIRST_CSR_REGNUM
);
526 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
528 #define DECLARE_CSR(NAME,VALUE) \
529 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
533 #include "opcode/riscv-opc.h"
538 if (regnum
== RISCV_PRIV_REGNUM
)
541 /* It is possible that that the target provides some registers that GDB
542 is unaware of, in that case just return the NAME from the target
547 /* Construct a type for 64-bit FP registers. */
550 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
552 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
554 if (tdep
->riscv_fpreg_d_type
== nullptr)
556 const struct builtin_type
*bt
= builtin_type (gdbarch
);
558 /* The type we're building is this: */
560 union __gdb_builtin_type_fpreg_d
569 t
= arch_composite_type (gdbarch
,
570 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
571 append_composite_type_field (t
, "float", bt
->builtin_float
);
572 append_composite_type_field (t
, "double", bt
->builtin_double
);
574 TYPE_NAME (t
) = "builtin_type_fpreg_d";
575 tdep
->riscv_fpreg_d_type
= t
;
578 return tdep
->riscv_fpreg_d_type
;
581 /* Implement the register_type gdbarch method. This is installed as an
582 for the override setup by TDESC_USE_REGISTERS, for most registers we
583 delegate the type choice to the target description, but for a few
584 registers we try to improve the types if the target description has
585 taken a simplistic approach. */
588 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
590 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
591 int xlen
= riscv_isa_xlen (gdbarch
);
593 /* We want to perform some specific type "fixes" in cases where we feel
594 that we really can do better than the target description. For all
595 other cases we just return what the target description says. */
596 if (riscv_is_fp_regno_p (regnum
))
598 /* This spots the case for RV64 where the double is defined as
599 either 'ieee_double' or 'float' (which is the generic name that
600 converts to 'double' on 64-bit). In these cases its better to
601 present the registers using a union type. */
602 int flen
= riscv_isa_flen (gdbarch
);
604 && TYPE_CODE (type
) == TYPE_CODE_FLT
605 && TYPE_LENGTH (type
) == flen
606 && (strcmp (TYPE_NAME (type
), "builtin_type_ieee_double") == 0
607 || strcmp (TYPE_NAME (type
), "double") == 0))
608 type
= riscv_fpreg_d_type (gdbarch
);
611 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
612 || regnum
== RISCV_RA_REGNUM
613 || regnum
== RISCV_FP_REGNUM
614 || regnum
== RISCV_SP_REGNUM
615 || regnum
== RISCV_GP_REGNUM
616 || regnum
== RISCV_TP_REGNUM
)
617 && TYPE_CODE (type
) == TYPE_CODE_INT
618 && TYPE_LENGTH (type
) == xlen
)
620 /* This spots the case where some interesting registers are defined
621 as simple integers of the expected size, we force these registers
622 to be pointers as we believe that is more useful. */
623 if (regnum
== gdbarch_pc_regnum (gdbarch
)
624 || regnum
== RISCV_RA_REGNUM
)
625 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
626 else if (regnum
== RISCV_FP_REGNUM
627 || regnum
== RISCV_SP_REGNUM
628 || regnum
== RISCV_GP_REGNUM
629 || regnum
== RISCV_TP_REGNUM
)
630 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
636 /* Helper for riscv_print_registers_info, prints info for a single register
640 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
641 struct ui_file
*file
,
642 struct frame_info
*frame
,
645 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
647 struct type
*regtype
;
648 int print_raw_format
;
649 enum tab_stops
{ value_column_1
= 15 };
651 fputs_filtered (name
, file
);
652 print_spaces_filtered (value_column_1
- strlen (name
), file
);
656 val
= value_of_register (regnum
, frame
);
657 regtype
= value_type (val
);
659 catch (const gdb_exception_error
&ex
)
661 /* Handle failure to read a register without interrupting the entire
662 'info registers' flow. */
663 fprintf_filtered (file
, "%s\n", ex
.what ());
667 print_raw_format
= (value_entirely_available (val
)
668 && !value_optimized_out (val
));
670 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
671 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
672 && TYPE_NFIELDS (regtype
) == 2
673 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
674 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
)
675 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
676 && TYPE_NFIELDS (regtype
) == 3
677 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
678 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
679 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 2)) == TYPE_CODE_FLT
))
681 struct value_print_options opts
;
682 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
683 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
685 get_user_print_options (&opts
);
689 value_embedded_offset (val
), 0,
690 file
, 0, val
, &opts
, current_language
);
692 if (print_raw_format
)
694 fprintf_filtered (file
, "\t(raw ");
695 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
697 fprintf_filtered (file
, ")");
702 struct value_print_options opts
;
704 /* Print the register in hex. */
705 get_formatted_print_options (&opts
, 'x');
708 value_embedded_offset (val
), 0,
709 file
, 0, val
, &opts
, current_language
);
711 if (print_raw_format
)
713 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
716 int size
= register_size (gdbarch
, regnum
);
719 /* The SD field is always in the upper bit of MSTATUS, regardless
720 of the number of bits in MSTATUS. */
721 d
= value_as_long (val
);
723 fprintf_filtered (file
,
724 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
725 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
726 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
727 (int) ((d
>> (xlen
- 1)) & 0x1),
728 (int) ((d
>> 24) & 0x1f),
729 (int) ((d
>> 19) & 0x1),
730 (int) ((d
>> 18) & 0x1),
731 (int) ((d
>> 17) & 0x1),
732 (int) ((d
>> 15) & 0x3),
733 (int) ((d
>> 13) & 0x3),
734 (int) ((d
>> 11) & 0x3),
735 (int) ((d
>> 9) & 0x3),
736 (int) ((d
>> 8) & 0x1),
737 (int) ((d
>> 7) & 0x1),
738 (int) ((d
>> 6) & 0x1),
739 (int) ((d
>> 5) & 0x1),
740 (int) ((d
>> 4) & 0x1),
741 (int) ((d
>> 3) & 0x1),
742 (int) ((d
>> 2) & 0x1),
743 (int) ((d
>> 1) & 0x1),
744 (int) ((d
>> 0) & 0x1));
746 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
751 int size
= register_size (gdbarch
, regnum
);
753 /* The MXL field is always in the upper two bits of MISA,
754 regardless of the number of bits in MISA. Mask out other
755 bits to ensure we have a positive value. */
756 d
= value_as_long (val
);
757 base
= (d
>> ((size
* 8) - 2)) & 0x3;
760 for (; base
> 0; base
--)
762 fprintf_filtered (file
, "\tRV%d", xlen
);
764 for (i
= 0; i
< 26; i
++)
767 fprintf_filtered (file
, "%c", 'A' + i
);
770 else if (regnum
== RISCV_CSR_FCSR_REGNUM
771 || regnum
== RISCV_CSR_FFLAGS_REGNUM
772 || regnum
== RISCV_CSR_FRM_REGNUM
)
776 d
= value_as_long (val
);
778 fprintf_filtered (file
, "\t");
779 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
780 fprintf_filtered (file
,
781 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
782 (int) ((d
>> 5) & 0x7),
783 (int) ((d
>> 4) & 0x1),
784 (int) ((d
>> 3) & 0x1),
785 (int) ((d
>> 2) & 0x1),
786 (int) ((d
>> 1) & 0x1),
787 (int) ((d
>> 0) & 0x1));
789 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
791 static const char * const sfrm
[] =
793 "RNE (round to nearest; ties to even)",
794 "RTZ (Round towards zero)",
795 "RDN (Round down towards -INF)",
796 "RUP (Round up towards +INF)",
797 "RMM (Round to nearest; ties to max magnitude)",
800 "dynamic rounding mode",
802 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
803 ? (d
>> 5) : d
) & 0x3;
805 fprintf_filtered (file
, "%sFRM:%i [%s]",
806 (regnum
== RISCV_CSR_FCSR_REGNUM
811 else if (regnum
== RISCV_PRIV_REGNUM
)
816 d
= value_as_long (val
);
821 static const char * const sprv
[] =
828 fprintf_filtered (file
, "\tprv:%d [%s]",
832 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
836 /* If not a vector register, print it also according to its
838 if (TYPE_VECTOR (regtype
) == 0)
840 get_user_print_options (&opts
);
842 fprintf_filtered (file
, "\t");
844 value_embedded_offset (val
), 0,
845 file
, 0, val
, &opts
, current_language
);
850 fprintf_filtered (file
, "\n");
853 /* Return true if REGNUM is a valid CSR register. The CSR register space
854 is sparsely populated, so not every number is a named CSR. */
857 riscv_is_regnum_a_named_csr (int regnum
)
859 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
860 && regnum
<= RISCV_LAST_CSR_REGNUM
);
864 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
865 #include "opcode/riscv-opc.h"
874 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
878 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
879 struct reggroup
*reggroup
)
881 /* Used by 'info registers' and 'info registers <groupname>'. */
883 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
884 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
887 if (regnum
> RISCV_LAST_REGNUM
)
889 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
893 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
896 if (reggroup
== all_reggroup
)
898 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
900 if (riscv_is_regnum_a_named_csr (regnum
))
904 else if (reggroup
== float_reggroup
)
905 return (riscv_is_fp_regno_p (regnum
)
906 || regnum
== RISCV_CSR_FCSR_REGNUM
907 || regnum
== RISCV_CSR_FFLAGS_REGNUM
908 || regnum
== RISCV_CSR_FRM_REGNUM
);
909 else if (reggroup
== general_reggroup
)
910 return regnum
< RISCV_FIRST_FP_REGNUM
;
911 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
913 if (riscv_has_fp_regs (gdbarch
))
914 return (regnum
<= RISCV_LAST_FP_REGNUM
915 || regnum
== RISCV_CSR_FCSR_REGNUM
916 || regnum
== RISCV_CSR_FFLAGS_REGNUM
917 || regnum
== RISCV_CSR_FRM_REGNUM
);
919 return regnum
< RISCV_FIRST_FP_REGNUM
;
921 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
923 if (regnum
== RISCV_PRIV_REGNUM
)
925 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
927 if (riscv_is_regnum_a_named_csr (regnum
))
931 else if (reggroup
== vector_reggroup
)
937 /* Implement the print_registers_info gdbarch method. This is used by
938 'info registers' and 'info all-registers'. */
941 riscv_print_registers_info (struct gdbarch
*gdbarch
,
942 struct ui_file
*file
,
943 struct frame_info
*frame
,
944 int regnum
, int print_all
)
948 /* Print one specified register. */
949 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
950 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
951 error (_("Not a valid register for the current processor type"));
952 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
956 struct reggroup
*reggroup
;
959 reggroup
= all_reggroup
;
961 reggroup
= general_reggroup
;
963 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
965 /* Zero never changes, so might as well hide by default. */
966 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
969 /* Registers with no name are not valid on this ISA. */
970 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
971 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
974 /* Is the register in the group we're interested in? */
975 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
978 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
983 /* Class that handles one decoded RiscV instruction. */
989 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
992 /* Unknown value is used at initialisation time. */
995 /* These instructions are all the ones we are interested in during the
1005 /* These are needed for software breakopint support. */
1014 /* These are needed for stepping over atomic sequences. */
1018 /* Other instructions are not interesting during the prologue scan, and
1033 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1035 /* Get the length of the instruction in bytes. */
1037 { return m_length
; }
1039 /* Get the opcode for this instruction. */
1040 enum opcode
opcode () const
1041 { return m_opcode
; }
1043 /* Get destination register field for this instruction. This is only
1044 valid if the OPCODE implies there is such a field for this
1049 /* Get the RS1 register field for this instruction. This is only valid
1050 if the OPCODE implies there is such a field for this instruction. */
1054 /* Get the RS2 register field for this instruction. This is only valid
1055 if the OPCODE implies there is such a field for this instruction. */
1059 /* Get the immediate for this instruction in signed form. This is only
1060 valid if the OPCODE implies there is such a field for this
1062 int imm_signed () const
1067 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1068 int decode_register_index (unsigned long opcode
, int offset
)
1070 return (opcode
>> offset
) & 0x1F;
1073 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1074 int decode_register_index_short (unsigned long opcode
, int offset
)
1076 return ((opcode
>> offset
) & 0x7) + 8;
1079 /* Helper for DECODE, decode 32-bit R-type instruction. */
1080 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1083 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1084 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1085 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1088 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1089 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1092 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1093 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1096 /* Helper for DECODE, decode 32-bit I-type instruction. */
1097 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1100 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1101 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1102 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1105 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1106 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1109 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1110 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1113 /* Helper for DECODE, decode 32-bit S-type instruction. */
1114 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1117 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1118 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1119 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1122 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1123 encoding is different for each CS format instruction, so extracting
1124 the immediate is left up to the caller, who should pass the extracted
1125 immediate value through in IMM. */
1126 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1130 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1131 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1134 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1135 encoding is different for each CSS format instruction, so extracting
1136 the immediate is left up to the caller, who should pass the extracted
1137 immediate value through in IMM. */
1138 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1142 m_rs1
= RISCV_SP_REGNUM
;
1143 /* Not a compressed register number in this case. */
1144 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1147 /* Helper for DECODE, decode 32-bit U-type instruction. */
1148 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1151 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1152 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1155 /* Helper for DECODE, decode 32-bit J-type instruction. */
1156 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1159 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1160 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1163 /* Helper for DECODE, decode 32-bit J-type instruction. */
1164 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1167 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1170 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1173 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1174 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1175 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1178 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1181 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1182 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1185 /* Fetch instruction from target memory at ADDR, return the content of
1186 the instruction, and update LEN with the instruction length. */
1187 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1188 CORE_ADDR addr
, int *len
);
1190 /* The length of the instruction in bytes. Should be 2 or 4. */
1193 /* The instruction opcode. */
1194 enum opcode m_opcode
;
1196 /* The three possible registers an instruction might reference. Not
1197 every instruction fills in all of these registers. Which fields are
1198 valid depends on the opcode. The naming of these fields matches the
1199 naming in the riscv isa manual. */
1204 /* Possible instruction immediate. This is only valid if the instruction
1205 format contains an immediate, not all instruction, whether this is
1206 valid depends on the opcode. Despite only having one format for now
1207 the immediate is packed into a union, later instructions might require
1208 an unsigned formatted immediate, having the union in place now will
1209 reduce the need for code churn later. */
1210 union riscv_insn_immediate
1212 riscv_insn_immediate ()
1222 /* Fetch instruction from target memory at ADDR, return the content of the
1223 instruction, and update LEN with the instruction length. */
1226 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1227 CORE_ADDR addr
, int *len
)
1229 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1231 int instlen
, status
;
1233 /* All insns are at least 16 bits. */
1234 status
= target_read_memory (addr
, buf
, 2);
1236 memory_error (TARGET_XFER_E_IO
, addr
);
1238 /* If we need more, grab it now. */
1239 instlen
= riscv_insn_length (buf
[0]);
1240 gdb_assert (instlen
<= sizeof (buf
));
1245 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1247 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1250 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1253 /* Fetch from target memory an instruction at PC and decode it. This can
1254 throw an error if the memory access fails, callers are responsible for
1255 handling this error if that is appropriate. */
1258 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1262 /* Fetch the instruction, and the instructions length. */
1263 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1267 if (is_add_insn (ival
))
1268 decode_r_type_insn (ADD
, ival
);
1269 else if (is_addw_insn (ival
))
1270 decode_r_type_insn (ADDW
, ival
);
1271 else if (is_addi_insn (ival
))
1272 decode_i_type_insn (ADDI
, ival
);
1273 else if (is_addiw_insn (ival
))
1274 decode_i_type_insn (ADDIW
, ival
);
1275 else if (is_auipc_insn (ival
))
1276 decode_u_type_insn (AUIPC
, ival
);
1277 else if (is_lui_insn (ival
))
1278 decode_u_type_insn (LUI
, ival
);
1279 else if (is_sd_insn (ival
))
1280 decode_s_type_insn (SD
, ival
);
1281 else if (is_sw_insn (ival
))
1282 decode_s_type_insn (SW
, ival
);
1283 else if (is_jal_insn (ival
))
1284 decode_j_type_insn (JAL
, ival
);
1285 else if (is_jalr_insn (ival
))
1286 decode_i_type_insn (JALR
, ival
);
1287 else if (is_beq_insn (ival
))
1288 decode_b_type_insn (BEQ
, ival
);
1289 else if (is_bne_insn (ival
))
1290 decode_b_type_insn (BNE
, ival
);
1291 else if (is_blt_insn (ival
))
1292 decode_b_type_insn (BLT
, ival
);
1293 else if (is_bge_insn (ival
))
1294 decode_b_type_insn (BGE
, ival
);
1295 else if (is_bltu_insn (ival
))
1296 decode_b_type_insn (BLTU
, ival
);
1297 else if (is_bgeu_insn (ival
))
1298 decode_b_type_insn (BGEU
, ival
);
1299 else if (is_lr_w_insn (ival
))
1300 decode_r_type_insn (LR
, ival
);
1301 else if (is_lr_d_insn (ival
))
1302 decode_r_type_insn (LR
, ival
);
1303 else if (is_sc_w_insn (ival
))
1304 decode_r_type_insn (SC
, ival
);
1305 else if (is_sc_d_insn (ival
))
1306 decode_r_type_insn (SC
, ival
);
1308 /* None of the other fields are valid in this case. */
1311 else if (m_length
== 2)
1313 int xlen
= riscv_isa_xlen (gdbarch
);
1315 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1316 C_JALR. So must try to match C_JALR first as it has more bits in
1318 if (is_c_jalr_insn (ival
))
1319 decode_cr_type_insn (JALR
, ival
);
1320 else if (is_c_add_insn (ival
))
1321 decode_cr_type_insn (ADD
, ival
);
1322 /* C_ADDW is RV64 and RV128 only. */
1323 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1324 decode_cr_type_insn (ADDW
, ival
);
1325 else if (is_c_addi_insn (ival
))
1326 decode_ci_type_insn (ADDI
, ival
);
1327 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1328 only and C_JAL is RV32 only. */
1329 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1330 decode_ci_type_insn (ADDIW
, ival
);
1331 else if (xlen
== 4 && is_c_jal_insn (ival
))
1332 decode_cj_type_insn (JAL
, ival
);
1333 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1334 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1336 else if (is_c_addi16sp_insn (ival
))
1339 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1340 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1342 else if (is_c_addi4spn_insn (ival
))
1345 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1346 m_rs1
= RISCV_SP_REGNUM
;
1347 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1349 else if (is_c_lui_insn (ival
))
1352 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1353 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1355 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1356 and C_FSW is RV32 only. */
1357 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1358 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1359 else if (is_c_sw_insn (ival
))
1360 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1361 else if (is_c_swsp_insn (ival
))
1362 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1363 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1364 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1365 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1366 So must try to match C_JR first as it ahs more bits in mask. */
1367 else if (is_c_jr_insn (ival
))
1368 decode_cr_type_insn (JALR
, ival
);
1369 else if (is_c_j_insn (ival
))
1370 decode_cj_type_insn (JAL
, ival
);
1371 else if (is_c_beqz_insn (ival
))
1372 decode_cb_type_insn (BEQ
, ival
);
1373 else if (is_c_bnez_insn (ival
))
1374 decode_cb_type_insn (BNE
, ival
);
1376 /* None of the other fields of INSN are valid in this case. */
1380 internal_error (__FILE__
, __LINE__
,
1381 _("unable to decode %d byte instructions in "
1382 "prologue at %s"), m_length
,
1383 core_addr_to_string (pc
));
1386 /* The prologue scanner. This is currently only used for skipping the
1387 prologue of a function when the DWARF information is not sufficient.
1388 However, it is written with filling of the frame cache in mind, which
1389 is why different groups of stack setup instructions are split apart
1390 during the core of the inner loop. In the future, the intention is to
1391 extend this function to fully support building up a frame cache that
1392 can unwind register values when there is no DWARF information. */
1395 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1396 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1397 struct riscv_unwind_cache
*cache
)
1399 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1400 CORE_ADDR end_prologue_addr
= 0;
1402 /* Find an upper limit on the function prologue using the debug
1403 information. If the debug information could not be used to provide
1404 that bound, then use an arbitrary large number as the upper bound. */
1405 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1406 if (after_prologue_pc
== 0)
1407 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1408 if (after_prologue_pc
< end_pc
)
1409 end_pc
= after_prologue_pc
;
1411 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1412 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1413 regs
[regno
] = pv_register (regno
, 0);
1414 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1416 if (riscv_debug_unwinder
)
1419 "Prologue scan for function starting at %s (limit %s)\n",
1420 core_addr_to_string (start_pc
),
1421 core_addr_to_string (end_pc
));
1423 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1425 struct riscv_insn insn
;
1427 /* Decode the current instruction, and decide where the next
1428 instruction lives based on the size of this instruction. */
1429 insn
.decode (gdbarch
, cur_pc
);
1430 gdb_assert (insn
.length () > 0);
1431 next_pc
= cur_pc
+ insn
.length ();
1433 /* Look for common stack adjustment insns. */
1434 if ((insn
.opcode () == riscv_insn::ADDI
1435 || insn
.opcode () == riscv_insn::ADDIW
)
1436 && insn
.rd () == RISCV_SP_REGNUM
1437 && insn
.rs1 () == RISCV_SP_REGNUM
)
1439 /* Handle: addi sp, sp, -i
1440 or: addiw sp, sp, -i */
1441 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1442 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1444 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1446 else if ((insn
.opcode () == riscv_insn::SW
1447 || insn
.opcode () == riscv_insn::SD
)
1448 && (insn
.rs1 () == RISCV_SP_REGNUM
1449 || insn
.rs1 () == RISCV_FP_REGNUM
))
1451 /* Handle: sw reg, offset(sp)
1452 or: sd reg, offset(sp)
1453 or: sw reg, offset(s0)
1454 or: sd reg, offset(s0) */
1455 /* Instruction storing a register onto the stack. */
1456 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1457 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1458 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1459 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1462 else if (insn
.opcode () == riscv_insn::ADDI
1463 && insn
.rd () == RISCV_FP_REGNUM
1464 && insn
.rs1 () == RISCV_SP_REGNUM
)
1466 /* Handle: addi s0, sp, size */
1467 /* Instructions setting up the frame pointer. */
1468 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1469 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1471 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1473 else if ((insn
.opcode () == riscv_insn::ADD
1474 || insn
.opcode () == riscv_insn::ADDW
)
1475 && insn
.rd () == RISCV_FP_REGNUM
1476 && insn
.rs1 () == RISCV_SP_REGNUM
1477 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1479 /* Handle: add s0, sp, 0
1480 or: addw s0, sp, 0 */
1481 /* Instructions setting up the frame pointer. */
1482 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1483 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1484 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1486 else if ((insn
.opcode () == riscv_insn::ADDI
1487 && insn
.rd () == RISCV_ZERO_REGNUM
1488 && insn
.rs1 () == RISCV_ZERO_REGNUM
1489 && insn
.imm_signed () == 0))
1491 /* Handle: add x0, x0, 0 (NOP) */
1493 else if (insn
.opcode () == riscv_insn::AUIPC
)
1495 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1496 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1498 else if (insn
.opcode () == riscv_insn::LUI
)
1500 /* Handle: lui REG, n
1501 Where REG is not gp register. */
1502 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1503 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1505 else if (insn
.opcode () == riscv_insn::ADDI
)
1507 /* Handle: addi REG1, REG2, IMM */
1508 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1509 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1511 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1513 else if (insn
.opcode () == riscv_insn::ADD
)
1515 /* Handle: addi REG1, REG2, IMM */
1516 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1517 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1518 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1519 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1523 end_prologue_addr
= cur_pc
;
1528 if (end_prologue_addr
== 0)
1529 end_prologue_addr
= cur_pc
;
1531 if (riscv_debug_unwinder
)
1532 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1533 core_addr_to_string (end_prologue_addr
));
1537 /* Figure out if it is a frame pointer or just a stack pointer. Also
1538 the offset held in the pv_t is from the original register value to
1539 the current value, which for a grows down stack means a negative
1540 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1541 from the current value to the original value. */
1542 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1544 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1545 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1549 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1550 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1553 /* Assign offset from old SP to all saved registers. As we don't
1554 have the previous value for the frame base register at this
1555 point, we store the offset as the address in the trad_frame, and
1556 then convert this to an actual address later. */
1557 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1560 if (stack
.find_reg (gdbarch
, i
, &offset
))
1562 if (riscv_debug_unwinder
)
1564 /* Display OFFSET as a signed value, the offsets are from
1565 the frame base address to the registers location on
1566 the stack, with a descending stack this means the
1567 offsets are always negative. */
1568 fprintf_unfiltered (gdb_stdlog
,
1569 "Register $%s at stack offset %s\n",
1570 gdbarch_register_name (gdbarch
, i
),
1571 plongest ((LONGEST
) offset
));
1573 trad_frame_set_addr (cache
->regs
, i
, offset
);
1578 return end_prologue_addr
;
1581 /* Implement the riscv_skip_prologue gdbarch method. */
1584 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1586 CORE_ADDR func_addr
;
1588 /* See if we can determine the end of the prologue via the symbol
1589 table. If so, then return either PC, or the PC after the
1590 prologue, whichever is greater. */
1591 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1593 CORE_ADDR post_prologue_pc
1594 = skip_prologue_using_sal (gdbarch
, func_addr
);
1596 if (post_prologue_pc
!= 0)
1597 return std::max (pc
, post_prologue_pc
);
1600 /* Can't determine prologue from the symbol table, need to examine
1601 instructions. Pass -1 for the end address to indicate the prologue
1602 scanner can scan as far as it needs to find the end of the prologue. */
1603 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1606 /* Implement the gdbarch push dummy code callback. */
1609 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1610 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1611 struct type
*value_type
, CORE_ADDR
*real_pc
,
1612 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1614 /* Allocate space for a breakpoint, and keep the stack correctly
1622 /* Implement the gdbarch type alignment method, overrides the generic
1623 alignment algorithm for anything that is RISC-V specific. */
1626 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
1628 type
= check_typedef (type
);
1629 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
))
1630 return std::min (TYPE_LENGTH (type
), (ULONGEST
) BIGGEST_ALIGNMENT
);
1632 /* Anything else will be aligned by the generic code. */
1636 /* Holds information about a single argument either being passed to an
1637 inferior function, or returned from an inferior function. This includes
1638 information about the size, type, etc of the argument, and also
1639 information about how the argument will be passed (or returned). */
1641 struct riscv_arg_info
1643 /* Contents of the argument. */
1644 const gdb_byte
*contents
;
1646 /* Length of argument. */
1649 /* Alignment required for an argument of this type. */
1652 /* The type for this argument. */
1655 /* Each argument can have either 1 or 2 locations assigned to it. Each
1656 location describes where part of the argument will be placed. The
1657 second location is valid based on the LOC_TYPE and C_LENGTH fields
1658 of the first location (which is always valid). */
1661 /* What type of location this is. */
1664 /* Argument passed in a register. */
1667 /* Argument passed as an on stack argument. */
1670 /* Argument passed by reference. The second location is always
1671 valid for a BY_REF argument, and describes where the address
1672 of the BY_REF argument should be placed. */
1676 /* Information that depends on the location type. */
1679 /* Which register number to use. */
1682 /* The offset into the stack region. */
1686 /* The length of contents covered by this location. If this is less
1687 than the total length of the argument, then the second location
1688 will be valid, and will describe where the rest of the argument
1692 /* The offset within CONTENTS for this part of the argument. Will
1693 always be 0 for the first part. For the second part of the
1694 argument, this might be the C_LENGTH value of the first part,
1695 however, if we are passing a structure in two registers, and there's
1696 is padding between the first and second field, then this offset
1697 might be greater than the length of the first argument part. When
1698 the second argument location is not holding part of the argument
1699 value, but is instead holding the address of a reference argument,
1700 then this offset will be set to 0. */
1704 /* TRUE if this is an unnamed argument. */
1708 /* Information about a set of registers being used for passing arguments as
1709 part of a function call. The register set must be numerically
1710 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1711 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1713 struct riscv_arg_reg
1715 riscv_arg_reg (int first
, int last
)
1716 : next_regnum (first
),
1722 /* The GDB register number to use in this set. */
1725 /* The last GDB register number to use in this set. */
1729 /* Arguments can be passed as on stack arguments, or by reference. The
1730 on stack arguments must be in a continuous region starting from $sp,
1731 while the by reference arguments can be anywhere, but we'll put them
1732 on the stack after (at higher address) the on stack arguments.
1734 This might not be the right approach to take. The ABI is clear that
1735 an argument passed by reference can be modified by the callee, which
1736 us placing the argument (temporarily) onto the stack will not achieve
1737 (changes will be lost). There's also the possibility that very large
1738 arguments could overflow the stack.
1740 This struct is used to track offset into these two areas for where
1741 arguments are to be placed. */
1742 struct riscv_memory_offsets
1744 riscv_memory_offsets ()
1751 /* Offset into on stack argument area. */
1754 /* Offset into the pass by reference area. */
1758 /* Holds information about where arguments to a call will be placed. This
1759 is updated as arguments are added onto the call, and can be used to
1760 figure out where the next argument should be placed. */
1762 struct riscv_call_info
1764 riscv_call_info (struct gdbarch
*gdbarch
)
1765 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1766 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1768 xlen
= riscv_abi_xlen (gdbarch
);
1769 flen
= riscv_abi_flen (gdbarch
);
1771 /* Disable use of floating point registers if needed. */
1772 if (!riscv_has_fp_abi (gdbarch
))
1773 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1776 /* Track the memory areas used for holding in-memory arguments to a
1778 struct riscv_memory_offsets memory
;
1780 /* Holds information about the next integer register to use for passing
1782 struct riscv_arg_reg int_regs
;
1784 /* Holds information about the next floating point register to use for
1785 passing an argument. */
1786 struct riscv_arg_reg float_regs
;
1788 /* The XLEN and FLEN are copied in to this structure for convenience, and
1789 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
1794 /* Return the number of registers available for use as parameters in the
1795 register set REG. Returned value can be 0 or more. */
1798 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1800 if (reg
->next_regnum
> reg
->last_regnum
)
1803 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1806 /* If there is at least one register available in the register set REG then
1807 the next register from REG is assigned to LOC and the length field of
1808 LOC is updated to LENGTH. The register set REG is updated to indicate
1809 that the assigned register is no longer available and the function
1812 If there are no registers available in REG then the function returns
1813 false, and LOC and REG are unchanged. */
1816 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1817 struct riscv_arg_reg
*reg
,
1818 int length
, int offset
)
1820 if (reg
->next_regnum
<= reg
->last_regnum
)
1822 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1823 loc
->loc_data
.regno
= reg
->next_regnum
;
1825 loc
->c_length
= length
;
1826 loc
->c_offset
= offset
;
1833 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1834 record that an area of stack has been used to hold the parameter
1837 The length field of LOC is updated to LENGTH, the length of the
1838 parameter being stored, and ALIGN is the alignment required by the
1839 parameter, which will affect how memory is allocated out of MEMORY. */
1842 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1843 struct riscv_memory_offsets
*memory
,
1844 int length
, int align
)
1846 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1848 = align_up (memory
->arg_offset
, align
);
1849 loc
->loc_data
.offset
= memory
->arg_offset
;
1850 memory
->arg_offset
+= length
;
1851 loc
->c_length
= length
;
1853 /* Offset is always 0, either we're the first location part, in which
1854 case we're reading content from the start of the argument, or we're
1855 passing the address of a reference argument, so 0. */
1859 /* Update AINFO, which describes an argument that should be passed or
1860 returned using the integer ABI. The argloc fields within AINFO are
1861 updated to describe the location in which the argument will be passed to
1862 a function, or returned from a function.
1864 The CINFO structure contains the ongoing call information, the holds
1865 information such as which argument registers are remaining to be
1866 assigned to parameter, and how much memory has been used by parameters
1869 By examining the state of CINFO a suitable location can be selected,
1870 and assigned to AINFO. */
1873 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1874 struct riscv_call_info
*cinfo
)
1876 if (ainfo
->length
> (2 * cinfo
->xlen
))
1878 /* Argument is going to be passed by reference. */
1879 ainfo
->argloc
[0].loc_type
1880 = riscv_arg_info::location::by_ref
;
1881 cinfo
->memory
.ref_offset
1882 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1883 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1884 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1885 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1887 /* The second location for this argument is given over to holding the
1888 address of the by-reference data. Pass 0 for the offset as this
1889 is not part of the actual argument value. */
1890 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1893 riscv_assign_stack_location (&ainfo
->argloc
[1],
1894 &cinfo
->memory
, cinfo
->xlen
,
1899 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
1900 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
1902 /* Unnamed arguments in registers that require 2*XLEN alignment are
1903 passed in an aligned register pair. */
1904 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
1905 && cinfo
->int_regs
.next_regnum
& 1)
1906 cinfo
->int_regs
.next_regnum
++;
1908 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1909 &cinfo
->int_regs
, len
, 0))
1910 riscv_assign_stack_location (&ainfo
->argloc
[0],
1911 &cinfo
->memory
, len
, align
);
1913 if (len
< ainfo
->length
)
1915 len
= ainfo
->length
- len
;
1916 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1917 &cinfo
->int_regs
, len
,
1919 riscv_assign_stack_location (&ainfo
->argloc
[1],
1920 &cinfo
->memory
, len
, cinfo
->xlen
);
1925 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1926 is being passed with the floating point ABI. */
1929 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1930 struct riscv_call_info
*cinfo
)
1932 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
1933 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1936 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1939 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1943 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1944 is a complex floating point argument, and is therefore handled
1945 differently to other argument types. */
1948 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1949 struct riscv_call_info
*cinfo
)
1951 if (ainfo
->length
<= (2 * cinfo
->flen
)
1952 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
1953 && !ainfo
->is_unnamed
)
1956 int len
= ainfo
->length
/ 2;
1958 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1959 &cinfo
->float_regs
, len
, 0);
1960 gdb_assert (result
);
1962 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1963 &cinfo
->float_regs
, len
, len
);
1964 gdb_assert (result
);
1967 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1970 /* A structure used for holding information about a structure type within
1971 the inferior program. The RiscV ABI has special rules for handling some
1972 structures with a single field or with two fields. The counting of
1973 fields here is done after flattening out all nested structures. */
1975 class riscv_struct_info
1978 riscv_struct_info ()
1979 : m_number_of_fields (0),
1980 m_types
{ nullptr, nullptr },
1986 /* Analyse TYPE descending into nested structures, count the number of
1987 scalar fields and record the types of the first two fields found. */
1988 void analyse (struct type
*type
)
1990 analyse_inner (type
, 0);
1993 /* The number of scalar fields found in the analysed type. This is
1994 currently only accurate if the value returned is 0, 1, or 2 as the
1995 analysis stops counting when the number of fields is 3. This is
1996 because the RiscV ABI only has special cases for 1 or 2 fields,
1997 anything else we just don't care about. */
1998 int number_of_fields () const
1999 { return m_number_of_fields
; }
2001 /* Return the type for scalar field INDEX within the analysed type. Will
2002 return nullptr if there is no field at that index. Only INDEX values
2003 0 and 1 can be requested as the RiscV ABI only has special cases for
2004 structures with 1 or 2 fields. */
2005 struct type
*field_type (int index
) const
2007 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2008 return m_types
[index
];
2011 /* Return the offset of scalar field INDEX within the analysed type. Will
2012 return 0 if there is no field at that index. Only INDEX values 0 and
2013 1 can be requested as the RiscV ABI only has special cases for
2014 structures with 1 or 2 fields. */
2015 int field_offset (int index
) const
2017 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2018 return m_offsets
[index
];
2022 /* The number of scalar fields found within the structure after recursing
2023 into nested structures. */
2024 int m_number_of_fields
;
2026 /* The types of the first two scalar fields found within the structure
2027 after recursing into nested structures. */
2028 struct type
*m_types
[2];
2030 /* The offsets of the first two scalar fields found within the structure
2031 after recursing into nested structures. */
2034 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2035 offset from the start of the top level structure being analysed. */
2036 void analyse_inner (struct type
*type
, int offset
);
2039 /* See description in class declaration. */
2042 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2044 unsigned int count
= TYPE_NFIELDS (type
);
2047 for (i
= 0; i
< count
; ++i
)
2049 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
2052 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
2053 field_type
= check_typedef (field_type
);
2055 = offset
+ TYPE_FIELD_BITPOS (type
, i
) / TARGET_CHAR_BIT
;
2057 switch (TYPE_CODE (field_type
))
2059 case TYPE_CODE_STRUCT
:
2060 analyse_inner (field_type
, field_offset
);
2064 /* RiscV only flattens out structures. Anything else does not
2065 need to be flattened, we just record the type, and when we
2066 look at the analysis results we'll realise this is not a
2067 structure we can special case, and pass the structure in
2069 if (m_number_of_fields
< 2)
2071 m_types
[m_number_of_fields
] = field_type
;
2072 m_offsets
[m_number_of_fields
] = field_offset
;
2074 m_number_of_fields
++;
2078 /* RiscV only has special handling for structures with 1 or 2 scalar
2079 fields, any more than that and the structure is just passed in
2080 memory. We can safely drop out early when we find 3 or more
2083 if (m_number_of_fields
> 2)
2088 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2089 is a structure. Small structures on RiscV have some special case
2090 handling in order that the structure might be passed in register.
2091 Larger structures are passed in memory. After assigning location
2092 information to AINFO, CINFO will have been updated. */
2095 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2096 struct riscv_call_info
*cinfo
)
2098 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2100 struct riscv_struct_info sinfo
;
2102 sinfo
.analyse (ainfo
->type
);
2103 if (sinfo
.number_of_fields () == 1
2104 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
2106 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2107 except we use the type of the complex field instead of the
2108 type from AINFO, and the first location might be at a non-zero
2110 if (TYPE_LENGTH (sinfo
.field_type (0)) <= (2 * cinfo
->flen
)
2111 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2112 && !ainfo
->is_unnamed
)
2115 int len
= TYPE_LENGTH (sinfo
.field_type (0)) / 2;
2116 int offset
= sinfo
.field_offset (0);
2118 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2119 &cinfo
->float_regs
, len
,
2121 gdb_assert (result
);
2123 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2124 &cinfo
->float_regs
, len
,
2126 gdb_assert (result
);
2129 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2133 if (sinfo
.number_of_fields () == 1
2134 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
2136 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2137 except we use the type of the first scalar field instead of
2138 the type from AINFO. Also the location might be at a non-zero
2140 if (TYPE_LENGTH (sinfo
.field_type (0)) > cinfo
->flen
2141 || ainfo
->is_unnamed
)
2142 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2145 int offset
= sinfo
.field_offset (0);
2146 int len
= TYPE_LENGTH (sinfo
.field_type (0));
2148 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2151 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2156 if (sinfo
.number_of_fields () == 2
2157 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2158 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2159 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2160 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2161 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2163 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2164 int offset
= sinfo
.field_offset (0);
2165 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2166 &cinfo
->float_regs
, len0
, offset
))
2167 error (_("failed during argument setup"));
2169 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2170 offset
= sinfo
.field_offset (1);
2171 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2172 - TYPE_LENGTH (sinfo
.field_type (0))));
2174 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2177 error (_("failed during argument setup"));
2181 if (sinfo
.number_of_fields () == 2
2182 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2183 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2184 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2185 && is_integral_type (sinfo
.field_type (1))
2186 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2188 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2189 int offset
= sinfo
.field_offset (0);
2190 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2191 &cinfo
->float_regs
, len0
, offset
))
2192 error (_("failed during argument setup"));
2194 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2195 offset
= sinfo
.field_offset (1);
2196 gdb_assert (len1
<= cinfo
->xlen
);
2197 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2198 &cinfo
->int_regs
, len1
, offset
))
2199 error (_("failed during argument setup"));
2203 if (sinfo
.number_of_fields () == 2
2204 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2205 && (is_integral_type (sinfo
.field_type (0))
2206 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2207 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2208 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2210 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2211 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2213 gdb_assert (len0
<= cinfo
->xlen
);
2214 gdb_assert (len1
<= cinfo
->flen
);
2216 int offset
= sinfo
.field_offset (0);
2217 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2218 &cinfo
->int_regs
, len0
, offset
))
2219 error (_("failed during argument setup"));
2221 offset
= sinfo
.field_offset (1);
2222 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2225 error (_("failed during argument setup"));
2231 /* Non of the structure flattening cases apply, so we just pass using
2233 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2236 /* Assign a location to call (or return) argument AINFO, the location is
2237 selected from CINFO which holds information about what call argument
2238 locations are available for use next. The TYPE is the type of the
2239 argument being passed, this information is recorded into AINFO (along
2240 with some additional information derived from the type). IS_UNNAMED
2241 is true if this is an unnamed (stdarg) argument, this info is also
2242 recorded into AINFO.
2244 After assigning a location to AINFO, CINFO will have been updated. */
2247 riscv_arg_location (struct gdbarch
*gdbarch
,
2248 struct riscv_arg_info
*ainfo
,
2249 struct riscv_call_info
*cinfo
,
2250 struct type
*type
, bool is_unnamed
)
2253 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2254 ainfo
->align
= type_align (ainfo
->type
);
2255 ainfo
->is_unnamed
= is_unnamed
;
2256 ainfo
->contents
= nullptr;
2257 ainfo
->argloc
[0].c_length
= 0;
2258 ainfo
->argloc
[1].c_length
= 0;
2260 switch (TYPE_CODE (ainfo
->type
))
2263 case TYPE_CODE_BOOL
:
2264 case TYPE_CODE_CHAR
:
2265 case TYPE_CODE_RANGE
:
2266 case TYPE_CODE_ENUM
:
2268 if (ainfo
->length
<= cinfo
->xlen
)
2270 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2271 ainfo
->length
= cinfo
->xlen
;
2273 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2275 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2276 ainfo
->length
= 2 * cinfo
->xlen
;
2279 /* Recalculate the alignment requirement. */
2280 ainfo
->align
= type_align (ainfo
->type
);
2281 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2285 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2288 case TYPE_CODE_COMPLEX
:
2289 riscv_call_arg_complex_float (ainfo
, cinfo
);
2292 case TYPE_CODE_STRUCT
:
2293 riscv_call_arg_struct (ainfo
, cinfo
);
2297 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2302 /* Used for printing debug information about the call argument location in
2303 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2304 addresses for the location of pass-by-reference and
2305 arguments-on-the-stack memory areas. */
2308 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2309 struct riscv_arg_info
*info
,
2310 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2312 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2313 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2314 switch (info
->argloc
[0].loc_type
)
2316 case riscv_arg_info::location::in_reg
:
2318 (stream
, ", register %s",
2319 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2320 if (info
->argloc
[0].c_length
< info
->length
)
2322 switch (info
->argloc
[1].loc_type
)
2324 case riscv_arg_info::location::in_reg
:
2326 (stream
, ", register %s",
2327 gdbarch_register_name (gdbarch
,
2328 info
->argloc
[1].loc_data
.regno
));
2331 case riscv_arg_info::location::on_stack
:
2332 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2333 info
->argloc
[1].loc_data
.offset
);
2336 case riscv_arg_info::location::by_ref
:
2338 /* The second location should never be a reference, any
2339 argument being passed by reference just places its address
2340 in the first location and is done. */
2341 error (_("invalid argument location"));
2345 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2346 fprintf_unfiltered (stream
, " (offset 0x%x)",
2347 info
->argloc
[1].c_offset
);
2351 case riscv_arg_info::location::on_stack
:
2352 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2353 info
->argloc
[0].loc_data
.offset
);
2356 case riscv_arg_info::location::by_ref
:
2358 (stream
, ", by reference, data at offset 0x%x (%s)",
2359 info
->argloc
[0].loc_data
.offset
,
2360 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2361 if (info
->argloc
[1].loc_type
2362 == riscv_arg_info::location::in_reg
)
2364 (stream
, ", address in register %s",
2365 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2368 gdb_assert (info
->argloc
[1].loc_type
2369 == riscv_arg_info::location::on_stack
);
2371 (stream
, ", address on stack at offset 0x%x (%s)",
2372 info
->argloc
[1].loc_data
.offset
,
2373 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2378 gdb_assert_not_reached (_("unknown argument location type"));
2382 /* Implement the push dummy call gdbarch callback. */
2385 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2386 struct value
*function
,
2387 struct regcache
*regcache
,
2390 struct value
**args
,
2392 function_call_return_method return_method
,
2393 CORE_ADDR struct_addr
)
2396 CORE_ADDR sp_args
, sp_refs
;
2397 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2399 struct riscv_arg_info
*arg_info
=
2400 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2402 struct riscv_call_info
call_info (gdbarch
);
2406 struct type
*ftype
= check_typedef (value_type (function
));
2408 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2409 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2411 /* We'll use register $a0 if we're returning a struct. */
2412 if (return_method
== return_method_struct
)
2413 ++call_info
.int_regs
.next_regnum
;
2415 for (i
= 0; i
< nargs
; ++i
)
2417 struct value
*arg_value
;
2418 struct type
*arg_type
;
2419 struct riscv_arg_info
*info
= &arg_info
[i
];
2421 arg_value
= args
[i
];
2422 arg_type
= check_typedef (value_type (arg_value
));
2424 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
2425 TYPE_VARARGS (ftype
) && i
>= TYPE_NFIELDS (ftype
));
2427 if (info
->type
!= arg_type
)
2428 arg_value
= value_cast (info
->type
, arg_value
);
2429 info
->contents
= value_contents (arg_value
);
2432 /* Adjust the stack pointer and align it. */
2433 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2434 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2436 if (riscv_debug_infcall
> 0)
2438 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2439 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2440 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2441 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2442 call_info
.xlen
, call_info
.flen
);
2443 if (return_method
== return_method_struct
)
2444 fprintf_unfiltered (gdb_stdlog
,
2445 "[*] struct return pointer in register $A0\n");
2446 for (i
= 0; i
< nargs
; ++i
)
2448 struct riscv_arg_info
*info
= &arg_info
[i
];
2450 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2451 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2452 fprintf_unfiltered (gdb_stdlog
, "\n");
2454 if (call_info
.memory
.arg_offset
> 0
2455 || call_info
.memory
.ref_offset
> 0)
2457 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2458 core_addr_to_string (osp
));
2459 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2460 call_info
.memory
.arg_offset
);
2461 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2462 call_info
.memory
.ref_offset
);
2463 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2464 core_addr_to_string_nz (osp
- sp
));
2468 /* Now load the argument into registers, or onto the stack. */
2470 if (return_method
== return_method_struct
)
2472 gdb_byte buf
[sizeof (LONGEST
)];
2474 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2475 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2478 for (i
= 0; i
< nargs
; ++i
)
2481 int second_arg_length
= 0;
2482 const gdb_byte
*second_arg_data
;
2483 struct riscv_arg_info
*info
= &arg_info
[i
];
2485 gdb_assert (info
->length
> 0);
2487 switch (info
->argloc
[0].loc_type
)
2489 case riscv_arg_info::location::in_reg
:
2491 gdb_byte tmp
[sizeof (ULONGEST
)];
2493 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2494 /* FP values in FP registers must be NaN-boxed. */
2495 if (riscv_is_fp_regno_p (info
->argloc
[0].loc_data
.regno
)
2496 && info
->argloc
[0].c_length
< call_info
.flen
)
2497 memset (tmp
, -1, sizeof (tmp
));
2499 memset (tmp
, 0, sizeof (tmp
));
2500 memcpy (tmp
, (info
->contents
+ info
->argloc
[0].c_offset
),
2501 info
->argloc
[0].c_length
);
2502 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2504 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
2505 ? info
->argloc
[1].c_length
: 0);
2506 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2510 case riscv_arg_info::location::on_stack
:
2511 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2512 write_memory (dst
, info
->contents
, info
->length
);
2513 second_arg_length
= 0;
2516 case riscv_arg_info::location::by_ref
:
2517 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2518 write_memory (dst
, info
->contents
, info
->length
);
2520 second_arg_length
= call_info
.xlen
;
2521 second_arg_data
= (gdb_byte
*) &dst
;
2525 gdb_assert_not_reached (_("unknown argument location type"));
2528 if (second_arg_length
> 0)
2530 switch (info
->argloc
[1].loc_type
)
2532 case riscv_arg_info::location::in_reg
:
2534 gdb_byte tmp
[sizeof (ULONGEST
)];
2536 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2537 && second_arg_length
<= call_info
.flen
)
2538 || second_arg_length
<= call_info
.xlen
);
2539 /* FP values in FP registers must be NaN-boxed. */
2540 if (riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2541 && second_arg_length
< call_info
.flen
)
2542 memset (tmp
, -1, sizeof (tmp
));
2544 memset (tmp
, 0, sizeof (tmp
));
2545 memcpy (tmp
, second_arg_data
, second_arg_length
);
2546 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2550 case riscv_arg_info::location::on_stack
:
2554 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2555 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2559 case riscv_arg_info::location::by_ref
:
2561 /* The second location should never be a reference, any
2562 argument being passed by reference just places its address
2563 in the first location and is done. */
2564 error (_("invalid argument location"));
2570 /* Set the dummy return value to bp_addr.
2571 A dummy breakpoint will be setup to execute the call. */
2573 if (riscv_debug_infcall
> 0)
2574 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2575 core_addr_to_string (bp_addr
));
2576 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2578 /* Finally, update the stack pointer. */
2580 if (riscv_debug_infcall
> 0)
2581 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2582 core_addr_to_string (sp
));
2583 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2588 /* Implement the return_value gdbarch method. */
2590 static enum return_value_convention
2591 riscv_return_value (struct gdbarch
*gdbarch
,
2592 struct value
*function
,
2594 struct regcache
*regcache
,
2596 const gdb_byte
*writebuf
)
2598 struct riscv_call_info
call_info (gdbarch
);
2599 struct riscv_arg_info info
;
2600 struct type
*arg_type
;
2602 arg_type
= check_typedef (type
);
2603 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
2605 if (riscv_debug_infcall
> 0)
2607 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2608 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2609 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2610 fprintf_unfiltered (gdb_stdlog
, "\n");
2613 if (readbuf
!= nullptr || writebuf
!= nullptr)
2615 unsigned int arg_len
;
2616 struct value
*abi_val
;
2617 gdb_byte
*old_readbuf
= nullptr;
2620 /* We only do one thing at a time. */
2621 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
2623 /* In some cases the argument is not returned as the declared type,
2624 and we need to cast to or from the ABI type in order to
2625 correctly access the argument. When writing to the machine we
2626 do the cast here, when reading from the machine the cast occurs
2627 later, after extracting the value. As the ABI type can be
2628 larger than the declared type, then the read or write buffers
2629 passed in might be too small. Here we ensure that we are using
2630 buffers of sufficient size. */
2631 if (writebuf
!= nullptr)
2633 struct value
*arg_val
= value_from_contents (arg_type
, writebuf
);
2634 abi_val
= value_cast (info
.type
, arg_val
);
2635 writebuf
= value_contents_raw (abi_val
);
2639 abi_val
= allocate_value (info
.type
);
2640 old_readbuf
= readbuf
;
2641 readbuf
= value_contents_raw (abi_val
);
2643 arg_len
= TYPE_LENGTH (info
.type
);
2645 switch (info
.argloc
[0].loc_type
)
2647 /* Return value in register(s). */
2648 case riscv_arg_info::location::in_reg
:
2650 regnum
= info
.argloc
[0].loc_data
.regno
;
2651 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
2652 gdb_assert (info
.argloc
[0].c_length
2653 <= register_size (gdbarch
, regnum
));
2657 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
2658 regcache
->cooked_read_part (regnum
, 0,
2659 info
.argloc
[0].c_length
,
2665 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
2666 regcache
->cooked_write_part (regnum
, 0,
2667 info
.argloc
[0].c_length
,
2671 /* A return value in register can have a second part in a
2673 if (info
.argloc
[1].c_length
> 0)
2675 switch (info
.argloc
[1].loc_type
)
2677 case riscv_arg_info::location::in_reg
:
2678 regnum
= info
.argloc
[1].loc_data
.regno
;
2680 gdb_assert ((info
.argloc
[0].c_length
2681 + info
.argloc
[1].c_length
) <= arg_len
);
2682 gdb_assert (info
.argloc
[1].c_length
2683 <= register_size (gdbarch
, regnum
));
2687 readbuf
+= info
.argloc
[1].c_offset
;
2688 regcache
->cooked_read_part (regnum
, 0,
2689 info
.argloc
[1].c_length
,
2695 writebuf
+= info
.argloc
[1].c_offset
;
2696 regcache
->cooked_write_part (regnum
, 0,
2697 info
.argloc
[1].c_length
,
2702 case riscv_arg_info::location::by_ref
:
2703 case riscv_arg_info::location::on_stack
:
2705 error (_("invalid argument location"));
2712 /* Return value by reference will have its address in A0. */
2713 case riscv_arg_info::location::by_ref
:
2717 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2719 if (readbuf
!= nullptr)
2720 read_memory (addr
, readbuf
, info
.length
);
2721 if (writebuf
!= nullptr)
2722 write_memory (addr
, writebuf
, info
.length
);
2726 case riscv_arg_info::location::on_stack
:
2728 error (_("invalid argument location"));
2732 /* This completes the cast from abi type back to the declared type
2733 in the case that we are reading from the machine. See the
2734 comment at the head of this block for more details. */
2735 if (readbuf
!= nullptr)
2737 struct value
*arg_val
= value_cast (arg_type
, abi_val
);
2738 memcpy (old_readbuf
, value_contents_raw (arg_val
),
2739 TYPE_LENGTH (arg_type
));
2743 switch (info
.argloc
[0].loc_type
)
2745 case riscv_arg_info::location::in_reg
:
2746 return RETURN_VALUE_REGISTER_CONVENTION
;
2747 case riscv_arg_info::location::by_ref
:
2748 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2749 case riscv_arg_info::location::on_stack
:
2751 error (_("invalid argument location"));
2755 /* Implement the frame_align gdbarch method. */
2758 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2760 return align_down (addr
, 16);
2763 /* Generate, or return the cached frame cache for the RiscV frame
2766 static struct riscv_unwind_cache
*
2767 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2769 CORE_ADDR pc
, start_addr
;
2770 struct riscv_unwind_cache
*cache
;
2771 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2774 if ((*this_cache
) != NULL
)
2775 return (struct riscv_unwind_cache
*) *this_cache
;
2777 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2778 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2779 (*this_cache
) = cache
;
2781 /* Scan the prologue, filling in the cache. */
2782 start_addr
= get_frame_func (this_frame
);
2783 pc
= get_frame_pc (this_frame
);
2784 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2786 /* We can now calculate the frame base address. */
2788 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2789 + cache
->frame_base_offset
);
2790 if (riscv_debug_unwinder
)
2791 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2792 core_addr_to_string (cache
->frame_base
),
2793 gdbarch_register_name (gdbarch
,
2794 cache
->frame_base_reg
),
2795 cache
->frame_base_offset
);
2797 /* The prologue scanner sets the address of registers stored to the stack
2798 as the offset of that register from the frame base. The prologue
2799 scanner doesn't know the actual frame base value, and so is unable to
2800 compute the exact address. We do now know the frame base value, so
2801 update the address of registers stored to the stack. */
2802 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2803 for (regno
= 0; regno
< numregs
; ++regno
)
2805 if (trad_frame_addr_p (cache
->regs
, regno
))
2806 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2809 /* The previous $pc can be found wherever the $ra value can be found.
2810 The previous $ra value is gone, this would have been stored be the
2811 previous frame if required. */
2812 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2813 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2815 /* Build the frame id. */
2816 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2818 /* The previous $sp value is the frame base value. */
2819 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2825 /* Implement the this_id callback for RiscV frame unwinder. */
2828 riscv_frame_this_id (struct frame_info
*this_frame
,
2829 void **prologue_cache
,
2830 struct frame_id
*this_id
)
2832 struct riscv_unwind_cache
*cache
;
2836 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2837 *this_id
= cache
->this_id
;
2839 catch (const gdb_exception_error
&ex
)
2841 /* Ignore errors, this leaves the frame id as the predefined outer
2842 frame id which terminates the backtrace at this point. */
2846 /* Implement the prev_register callback for RiscV frame unwinder. */
2848 static struct value
*
2849 riscv_frame_prev_register (struct frame_info
*this_frame
,
2850 void **prologue_cache
,
2853 struct riscv_unwind_cache
*cache
;
2855 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2856 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2859 /* Structure defining the RiscV normal frame unwind functions. Since we
2860 are the fallback unwinder (DWARF unwinder is used first), we use the
2861 default frame sniffer, which always accepts the frame. */
2863 static const struct frame_unwind riscv_frame_unwind
=
2865 /*.type =*/ NORMAL_FRAME
,
2866 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2867 /*.this_id =*/ riscv_frame_this_id
,
2868 /*.prev_register =*/ riscv_frame_prev_register
,
2869 /*.unwind_data =*/ NULL
,
2870 /*.sniffer =*/ default_frame_sniffer
,
2871 /*.dealloc_cache =*/ NULL
,
2872 /*.prev_arch =*/ NULL
,
2875 /* Extract a set of required target features out of INFO, specifically the
2876 bfd being executed is examined to see what target features it requires.
2877 IF there is no current bfd, or the bfd doesn't indicate any useful
2878 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2880 static struct riscv_gdbarch_features
2881 riscv_features_from_gdbarch_info (const struct gdbarch_info info
)
2883 struct riscv_gdbarch_features features
;
2885 /* Now try to improve on the defaults by looking at the binary we are
2886 going to execute. We assume the user knows what they are doing and
2887 that the target will match the binary. Remember, this code path is
2888 only used at all if the target hasn't given us a description, so this
2889 is really a last ditched effort to do something sane before giving
2891 if (info
.abfd
!= NULL
2892 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2894 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2895 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2897 if (eclass
== ELFCLASS32
)
2899 else if (eclass
== ELFCLASS64
)
2902 internal_error (__FILE__
, __LINE__
,
2903 _("unknown ELF header class %d"), eclass
);
2905 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2907 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2912 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2914 if (binfo
->bits_per_word
== 32)
2916 else if (binfo
->bits_per_word
== 64)
2919 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2920 binfo
->bits_per_word
);
2926 /* Find a suitable default target description. Use the contents of INFO,
2927 specifically the bfd object being executed, to guide the selection of a
2928 suitable default target description. */
2930 static const struct target_desc
*
2931 riscv_find_default_target_description (const struct gdbarch_info info
)
2933 /* Extract desired feature set from INFO. */
2934 struct riscv_gdbarch_features features
2935 = riscv_features_from_gdbarch_info (info
);
2937 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2938 this case we fall back to a minimal useful target, 8-byte x-registers,
2939 with no floating point. */
2940 if (features
.xlen
== 0)
2943 /* Now build a target description based on the feature set. */
2944 return riscv_create_target_description (features
);
2947 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2948 is updated with the register numbers for each register as listed in
2949 REG_SET. If any register marked as required in REG_SET is not found in
2950 FEATURE then this function returns false, otherwise, it returns true. */
2953 riscv_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
2954 const struct tdesc_feature
*feature
,
2955 const struct riscv_register_feature
*reg_set
)
2957 for (const auto ®
: reg_set
->registers
)
2961 for (const char *name
: reg
.names
)
2964 tdesc_numbered_register (feature
, tdesc_data
, reg
.regnum
, name
);
2970 if (!found
&& reg
.required_p
)
2977 /* Add all the expected register sets into GDBARCH. */
2980 riscv_add_reggroups (struct gdbarch
*gdbarch
)
2982 /* Add predefined register groups. */
2983 reggroup_add (gdbarch
, all_reggroup
);
2984 reggroup_add (gdbarch
, save_reggroup
);
2985 reggroup_add (gdbarch
, restore_reggroup
);
2986 reggroup_add (gdbarch
, system_reggroup
);
2987 reggroup_add (gdbarch
, vector_reggroup
);
2988 reggroup_add (gdbarch
, general_reggroup
);
2989 reggroup_add (gdbarch
, float_reggroup
);
2991 /* Add RISC-V specific register groups. */
2992 reggroup_add (gdbarch
, csr_reggroup
);
2995 /* Create register aliases for all the alternative names that exist for
2996 registers in REG_SET. */
2999 riscv_setup_register_aliases (struct gdbarch
*gdbarch
,
3000 const struct riscv_register_feature
*reg_set
)
3002 for (auto ®
: reg_set
->registers
)
3004 /* The first item in the names list is the preferred name for the
3005 register, this is what RISCV_REGISTER_NAME returns, and so we
3006 don't need to create an alias with that name here. */
3007 for (int i
= 1; i
< reg
.names
.size (); ++i
)
3008 user_reg_add (gdbarch
, reg
.names
[i
], value_of_riscv_user_reg
,
3013 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3016 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3018 if (reg
< RISCV_DWARF_REGNUM_X31
)
3019 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3021 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3022 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3027 /* Initialize the current architecture based on INFO. If possible,
3028 re-use an architecture from ARCHES, which is a list of
3029 architectures already created during this debugging session.
3031 Called e.g. at program startup, when reading a core file, and when
3032 reading a binary file. */
3034 static struct gdbarch
*
3035 riscv_gdbarch_init (struct gdbarch_info info
,
3036 struct gdbarch_list
*arches
)
3038 struct gdbarch
*gdbarch
;
3039 struct gdbarch_tdep
*tdep
;
3040 struct riscv_gdbarch_features features
;
3041 const struct target_desc
*tdesc
= info
.target_desc
;
3043 /* Ensure we always have a target description. */
3044 if (!tdesc_has_registers (tdesc
))
3045 tdesc
= riscv_find_default_target_description (info
);
3048 if (riscv_debug_gdbarch
)
3049 fprintf_unfiltered (gdb_stdlog
, "Have got a target description\n");
3051 const struct tdesc_feature
*feature_cpu
3052 = tdesc_find_feature (tdesc
, riscv_xreg_feature
.name
);
3053 const struct tdesc_feature
*feature_fpu
3054 = tdesc_find_feature (tdesc
, riscv_freg_feature
.name
);
3055 const struct tdesc_feature
*feature_virtual
3056 = tdesc_find_feature (tdesc
, riscv_virtual_feature
.name
);
3057 const struct tdesc_feature
*feature_csr
3058 = tdesc_find_feature (tdesc
, riscv_csr_feature
.name
);
3060 if (feature_cpu
== NULL
)
3063 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3065 bool valid_p
= riscv_check_tdesc_feature (tdesc_data
,
3067 &riscv_xreg_feature
);
3070 /* Check that all of the core cpu registers have the same bitsize. */
3071 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
3073 for (auto &tdesc_reg
: feature_cpu
->registers
)
3074 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
3076 if (riscv_debug_gdbarch
)
3079 "From target-description, xlen = %d\n", xlen_bitsize
);
3081 features
.xlen
= (xlen_bitsize
/ 8);
3084 if (feature_fpu
!= NULL
)
3086 valid_p
&= riscv_check_tdesc_feature (tdesc_data
, feature_fpu
,
3087 &riscv_freg_feature
);
3089 int bitsize
= tdesc_register_bitsize (feature_fpu
, "ft0");
3090 features
.flen
= (bitsize
/ 8);
3092 if (riscv_debug_gdbarch
)
3095 "From target-description, flen = %d\n", bitsize
);
3101 if (riscv_debug_gdbarch
)
3104 "No FPU in target-description, assume soft-float ABI\n");
3107 if (feature_virtual
)
3108 riscv_check_tdesc_feature (tdesc_data
, feature_virtual
,
3109 &riscv_virtual_feature
);
3112 riscv_check_tdesc_feature (tdesc_data
, feature_csr
,
3113 &riscv_csr_feature
);
3117 if (riscv_debug_gdbarch
)
3118 fprintf_unfiltered (gdb_stdlog
, "Target description is not valid\n");
3119 tdesc_data_cleanup (tdesc_data
);
3123 /* Have a look at what the supplied (if any) bfd object requires of the
3124 target, then check that this matches with what the target is
3126 struct riscv_gdbarch_features abi_features
3127 = riscv_features_from_gdbarch_info (info
);
3128 /* In theory a binary compiled for RV32 could run on an RV64 target,
3129 however, this has not been tested in GDB yet, so for now we require
3130 that the requested xlen match the targets xlen. */
3131 if (abi_features
.xlen
!= 0 && abi_features
.xlen
!= features
.xlen
)
3132 error (_("bfd requires xlen %d, but target has xlen %d"),
3133 abi_features
.xlen
, features
.xlen
);
3134 /* We do support running binaries compiled for 32-bit float on targets
3135 with 64-bit float, so we only complain if the binary requires more
3136 than the target has available. */
3137 if (abi_features
.flen
> features
.flen
)
3138 error (_("bfd requires flen %d, but target has flen %d"),
3139 abi_features
.flen
, features
.flen
);
3141 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3142 features from the INFO object. In this case we assume that the xlen
3143 abi matches the hardware. */
3144 if (abi_features
.xlen
== 0)
3145 abi_features
.xlen
= features
.xlen
;
3147 /* Find a candidate among the list of pre-declared architectures. */
3148 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3150 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3152 /* Check that the feature set of the ARCHES matches the feature set
3153 we are looking for. If it doesn't then we can't reuse this
3155 struct gdbarch_tdep
*other_tdep
= gdbarch_tdep (arches
->gdbarch
);
3157 if (other_tdep
->isa_features
!= features
3158 || other_tdep
->abi_features
!= abi_features
)
3166 tdesc_data_cleanup (tdesc_data
);
3167 return arches
->gdbarch
;
3170 /* None found, so create a new architecture from the information provided. */
3171 tdep
= new (struct gdbarch_tdep
);
3172 gdbarch
= gdbarch_alloc (&info
, tdep
);
3173 tdep
->isa_features
= features
;
3174 tdep
->abi_features
= abi_features
;
3176 /* Target data types. */
3177 set_gdbarch_short_bit (gdbarch
, 16);
3178 set_gdbarch_int_bit (gdbarch
, 32);
3179 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3180 set_gdbarch_long_long_bit (gdbarch
, 64);
3181 set_gdbarch_float_bit (gdbarch
, 32);
3182 set_gdbarch_double_bit (gdbarch
, 64);
3183 set_gdbarch_long_double_bit (gdbarch
, 128);
3184 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3185 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3186 set_gdbarch_char_signed (gdbarch
, 0);
3187 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3189 /* Information about the target architecture. */
3190 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3191 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3192 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3193 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3195 /* Functions to analyze frames. */
3196 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3197 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3198 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3200 /* Functions handling dummy frames. */
3201 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3202 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3203 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3205 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3207 dwarf2_append_unwinders (gdbarch
);
3208 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3210 /* Register architecture. */
3211 riscv_add_reggroups (gdbarch
);
3213 /* Internal <-> external register number maps. */
3214 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3216 /* We reserve all possible register numbers for the known registers.
3217 This means the target description mechanism will add any target
3218 specific registers after this number. This helps make debugging GDB
3219 just a little easier. */
3220 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3222 /* We don't have to provide the count of 0 here (its the default) but
3223 include this line to make it explicit that, right now, we don't have
3224 any pseudo registers on RISC-V. */
3225 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
3227 /* Some specific register numbers GDB likes to know about. */
3228 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3229 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3231 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3233 /* Finalise the target description registers. */
3234 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3236 /* Override the register type callback setup by the target description
3237 mechanism. This allows us to provide special type for floating point
3239 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3241 /* Override the register name callback setup by the target description
3242 mechanism. This allows us to force our preferred names for the
3243 registers, no matter what the target description called them. */
3244 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3246 /* Override the register group callback setup by the target description
3247 mechanism. This allows us to force registers into the groups we
3248 want, ignoring what the target tells us. */
3249 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
3251 /* Create register aliases for alternative register names. */
3252 riscv_setup_register_aliases (gdbarch
, &riscv_xreg_feature
);
3253 if (riscv_has_fp_regs (gdbarch
))
3254 riscv_setup_register_aliases (gdbarch
, &riscv_freg_feature
);
3255 riscv_setup_register_aliases (gdbarch
, &riscv_csr_feature
);
3257 /* Hook in OS ABI-specific overrides, if they have been registered. */
3258 gdbarch_init_osabi (info
, gdbarch
);
3263 /* This decodes the current instruction and determines the address of the
3264 next instruction. */
3267 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
3269 struct gdbarch
*gdbarch
= regcache
->arch ();
3270 struct riscv_insn insn
;
3273 insn
.decode (gdbarch
, pc
);
3274 next_pc
= pc
+ insn
.length ();
3276 if (insn
.opcode () == riscv_insn::JAL
)
3277 next_pc
= pc
+ insn
.imm_signed ();
3278 else if (insn
.opcode () == riscv_insn::JALR
)
3281 regcache
->cooked_read (insn
.rs1 (), &source
);
3282 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
3284 else if (insn
.opcode () == riscv_insn::BEQ
)
3287 regcache
->cooked_read (insn
.rs1 (), &src1
);
3288 regcache
->cooked_read (insn
.rs2 (), &src2
);
3290 next_pc
= pc
+ insn
.imm_signed ();
3292 else if (insn
.opcode () == riscv_insn::BNE
)
3295 regcache
->cooked_read (insn
.rs1 (), &src1
);
3296 regcache
->cooked_read (insn
.rs2 (), &src2
);
3298 next_pc
= pc
+ insn
.imm_signed ();
3300 else if (insn
.opcode () == riscv_insn::BLT
)
3303 regcache
->cooked_read (insn
.rs1 (), &src1
);
3304 regcache
->cooked_read (insn
.rs2 (), &src2
);
3306 next_pc
= pc
+ insn
.imm_signed ();
3308 else if (insn
.opcode () == riscv_insn::BGE
)
3311 regcache
->cooked_read (insn
.rs1 (), &src1
);
3312 regcache
->cooked_read (insn
.rs2 (), &src2
);
3314 next_pc
= pc
+ insn
.imm_signed ();
3316 else if (insn
.opcode () == riscv_insn::BLTU
)
3318 ULONGEST src1
, src2
;
3319 regcache
->cooked_read (insn
.rs1 (), &src1
);
3320 regcache
->cooked_read (insn
.rs2 (), &src2
);
3322 next_pc
= pc
+ insn
.imm_signed ();
3324 else if (insn
.opcode () == riscv_insn::BGEU
)
3326 ULONGEST src1
, src2
;
3327 regcache
->cooked_read (insn
.rs1 (), &src1
);
3328 regcache
->cooked_read (insn
.rs2 (), &src2
);
3330 next_pc
= pc
+ insn
.imm_signed ();
3336 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3337 for the end of the sequence and put the breakpoint there. */
3340 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
3343 struct gdbarch
*gdbarch
= regcache
->arch ();
3344 struct riscv_insn insn
;
3345 CORE_ADDR cur_step_pc
= pc
;
3346 CORE_ADDR last_addr
= 0;
3348 /* First instruction has to be a load reserved. */
3349 insn
.decode (gdbarch
, cur_step_pc
);
3350 if (insn
.opcode () != riscv_insn::LR
)
3352 cur_step_pc
= cur_step_pc
+ insn
.length ();
3354 /* Next instruction should be branch to exit. */
3355 insn
.decode (gdbarch
, cur_step_pc
);
3356 if (insn
.opcode () != riscv_insn::BNE
)
3358 last_addr
= cur_step_pc
+ insn
.imm_signed ();
3359 cur_step_pc
= cur_step_pc
+ insn
.length ();
3361 /* Next instruction should be store conditional. */
3362 insn
.decode (gdbarch
, cur_step_pc
);
3363 if (insn
.opcode () != riscv_insn::SC
)
3365 cur_step_pc
= cur_step_pc
+ insn
.length ();
3367 /* Next instruction should be branch to start. */
3368 insn
.decode (gdbarch
, cur_step_pc
);
3369 if (insn
.opcode () != riscv_insn::BNE
)
3371 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
3373 cur_step_pc
= cur_step_pc
+ insn
.length ();
3375 /* We should now be at the end of the sequence. */
3376 if (cur_step_pc
!= last_addr
)
3379 *next_pc
= cur_step_pc
;
3383 /* This is called just before we want to resume the inferior, if we want to
3384 single-step it but there is no hardware or kernel single-step support. We
3385 find the target of the coming instruction and breakpoint it. */
3387 std::vector
<CORE_ADDR
>
3388 riscv_software_single_step (struct regcache
*regcache
)
3390 CORE_ADDR pc
, next_pc
;
3392 pc
= regcache_read_pc (regcache
);
3394 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
3397 next_pc
= riscv_next_pc (regcache
, pc
);
3402 /* Create RISC-V specific reggroups. */
3405 riscv_init_reggroups ()
3407 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
3411 _initialize_riscv_tdep (void)
3413 riscv_create_csr_aliases ();
3414 riscv_init_reggroups ();
3416 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
3418 /* Add root prefix command for all "set debug riscv" and "show debug
3420 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
3421 _("RISC-V specific debug commands."),
3422 &setdebugriscvcmdlist
, "set debug riscv ", 0,
3425 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
3426 _("RISC-V specific debug commands."),
3427 &showdebugriscvcmdlist
, "show debug riscv ", 0,
3430 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
3431 &riscv_debug_breakpoints
, _("\
3432 Set riscv breakpoint debugging."), _("\
3433 Show riscv breakpoint debugging."), _("\
3434 When non-zero, print debugging information for the riscv specific parts\n\
3435 of the breakpoint mechanism."),
3437 show_riscv_debug_variable
,
3438 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3440 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
3441 &riscv_debug_infcall
, _("\
3442 Set riscv inferior call debugging."), _("\
3443 Show riscv inferior call debugging."), _("\
3444 When non-zero, print debugging information for the riscv specific parts\n\
3445 of the inferior call mechanism."),
3447 show_riscv_debug_variable
,
3448 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3450 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
3451 &riscv_debug_unwinder
, _("\
3452 Set riscv stack unwinding debugging."), _("\
3453 Show riscv stack unwinding debugging."), _("\
3454 When non-zero, print debugging information for the riscv specific parts\n\
3455 of the stack unwinding mechanism."),
3457 show_riscv_debug_variable
,
3458 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3460 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
3461 &riscv_debug_gdbarch
, _("\
3462 Set riscv gdbarch initialisation debugging."), _("\
3463 Show riscv gdbarch initialisation debugging."), _("\
3464 When non-zero, print debugging information for the riscv gdbarch\n\
3465 initialisation process."),
3467 show_riscv_debug_variable
,
3468 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3470 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3471 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
3472 _("RISC-V specific commands."),
3473 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
3475 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
3476 _("RISC-V specific commands."),
3477 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3480 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3481 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3482 &use_compressed_breakpoints
,
3484 Set debugger's use of compressed breakpoints."), _(" \
3485 Show debugger's use of compressed breakpoints."), _("\
3486 Debugging compressed code requires compressed breakpoints to be used. If\n\
3487 left to 'auto' then gdb will use them if the existing instruction is a\n\
3488 compressed instruction. If that doesn't give the correct behavior, then\n\
3489 this option can be used."),
3491 show_use_compressed_breakpoints
,