opcodes/ChangeLog

   1 2021-01-30  Nick Clifton  <nickc@redhat.com>
   2
   3         This is the 2.35.2 release.
   4
   5         * configure: Regenerate.
   6         * po/opcodes.pot: Regenerate.
   7
   8 2021-01-28  Alan Modra  <amodra@gmail.com>
   9
  10         Apply from master
  11         2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
  12         * ppc-opc.c (insert_dw, (extract_dw): New functions.
  13         (DW, (XRC_MASK): Define.
  14         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
  15
  16 2021-01-26  Alan Modra  <amodra@gmail.com>
  17
  18         * i386-gen.c (parse_template): Ensure entire template_instance
  19         is initialised.
  20
  21 2020-10-07  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         PR gas/26685
  24         * i386-dis.c (mod_table): Replace Gv with Gdq on movdiri.
  25
  26 2020-10-07  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c (OP_E_memory): Revert previous change.
  29
  30 2020-09-24  Alan Modra  <amodra@gmail.com>
  31
  32         Apply from master
  33         2020-08-19  Alan Modra  <amodra@gmail.com>
  34         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
  35         vcmpuq and xvtlsbb.
  36
  37         2020-08-10  Alan Modra  <amodra@gmail.com>
  38         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
  39         instructions.
  40
  41         2020-08-10  Alan Modra  <amodra@gmail.com>
  42         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
  43         Enable icbt for power5, miso for power8.
  44
  45         2020-08-10  Alan Modra  <amodra@gmail.com>
  46         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
  47         mtvsrd, and similarly for mfvsrd.
  48
  49 2020-09-19  Nick Clifton  <nickc@redhat.com>
  50
  51         This is the 2.35.1 point release.
  52
  53         * configure: Regenerate.
  54         * po/opcodes.pot: Regenerate.
  55
  56 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
  57
  58         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
  59
  60 2020-08-26  David Faust  <david.faust@oracle.com>
  61
  62         * bpf-desc.c: Regenerate.
  63         * bpf-desc.h: Likewise.
  64         * bpf-opc.c: Likewise.
  65         * bpf-opc.h: Likewise.
  66         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
  67         ISA when appropriate.
  68
  69 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
  70
  71         Backported from master:
  72         2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
  73
  74         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
  75         <xvcvbf16spn>: ...to this.
  76
  77 2020-08-12  Nick Clifton  <nickc@redhat.com>
  78
  79         * po/sr.po: Updated Serbian translation.
  80
  81 2020-08-04  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         PR gas/26305
  84         * i386-opc.h (Prefix_Disp8): New.
  85         (Prefix_Disp16): Likewise.
  86         (Prefix_Disp32): Likewise.
  87         (Prefix_Load): Likewise.
  88         (Prefix_Store): Likewise.
  89         (Prefix_VEX): Likewise.
  90         (Prefix_VEX3): Likewise.
  91         (Prefix_EVEX): Likewise.
  92         (Prefix_REX): Likewise.
  93         (Prefix_NoOptimize): Likewise.
  94         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
  95         * i386-tbl.h: Regenerated.
  96
  97 2020-07-24  Nick Clifton  <nickc@redhat.com>
  98
  99         * configure: Regenerate.
 100
 101 2020-07-24  Nick Clifton  <nickc@redhat.com>
 102
 103         2.35 Release:
 104         * configure: Regenerate.
 105         * po/opcodes.pot: Regenerate.
 106
 107 2020-07-24  Nick Clifton  <nickc@redhat.com>
 108
 109         * po/de.po: Updated German translation.
 110
 111 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 112
 113         PR gas/26237
 114         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 115         without base nor index registers.
 116
 117 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 118
 119         PR gas/26237
 120         * i386-dis.c (OP_E_memory): Without base nor index registers,
 121         zero-extend lower 32-bit displacement to 64 bits.
 122
 123 2020-07-06  Nick Clifton  <nickc@redhat.com>
 124
 125         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 126         * po/uk.po: Updated Ukranian translation.
 127
 128 2020-07-04  Nick Clifton  <nickc@redhat.com>
 129
 130         * configure: Regenerate.
 131         * po/opcodes.pot: Regenerate.
 132
 133 2020-07-04  Nick Clifton  <nickc@redhat.com>
 134
 135         Binutils 2.35 branch created.
 136
 137 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 140         * i386-opc.h (VexSwapSources): New.
 141         (i386_opcode_modifier): Add vexswapsources.
 142         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 143         with two source operands swapped.
 144         * i386-tbl.h: Regenerated.
 145
 146 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 147
 148         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 149         unprivileged CSR can also be initialized.
 150
 151 2020-06-29  Alan Modra  <amodra@gmail.com>
 152
 153         * arm-dis.c: Use C style comments.
 154         * cr16-opc.c: Likewise.
 155         * ft32-dis.c: Likewise.
 156         * moxie-opc.c: Likewise.
 157         * tic54x-dis.c: Likewise.
 158         * s12z-opc.c: Remove useless comment.
 159         * xgate-dis.c: Likewise.
 160
 161 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         * i386-opc.tbl: Add a blank line.
 164
 165 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 166
 167         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 168         (VecSIB128): Renamed to ...
 169         (VECSIB128): This.
 170         (VecSIB256): Renamed to ...
 171         (VECSIB256): This.
 172         (VecSIB512): Renamed to ...
 173         (VECSIB512): This.
 174         (VecSIB): Renamed to ...
 175         (SIB): This.
 176         (i386_opcode_modifier): Replace vecsib with sib.
 177         * i386-opc.tbl (VecSIB128): New.
 178         (VecSIB256): Likewise.
 179         (VecSIB512): Likewise.
 180         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 181         and VecSIB512, respectively.
 182
 183 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-dis.c: Adjust description of I macro.
 186         (x86_64_table): Drop use of I.
 187         (float_mem): Replace use of I.
 188         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 189
 190 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-dis.c: (print_insn): Avoid straight assignment to
 193         priv.orig_sizeflag when processing -M sub-options.
 194
 195 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-dis.c: Adjust description of J macro.
 198         (dis386, x86_64_table, mod_table): Replace J.
 199         (putop): Remove handling of J.
 200
 201 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 204
 205 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-dis.c: Adjust description of "LQ" macro.
 208         (dis386_twobyte): Use LQ for sysret.
 209         (putop): Adjust handling of LQ.
 210
 211 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 212
 213         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 214         * riscv-dis.c: Include elfxx-riscv.h.
 215
 216 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 219
 220 2020-06-17  Lili Cui  <lili.cui@intel.com>
 221
 222         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 223
 224 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         PR gas/26115
 227         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 228         * i386-opc.tbl: Likewise.
 229         * i386-tbl.h: Regenerated.
 230
 231 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 232
 233         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 234
 235 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 236
 237         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 238         (SR_CORE): Likewise.
 239         (SR_FEAT): Likewise.
 240         (SR_RNG): Likewise.
 241         (SR_V8_1): Likewise.
 242         (SR_V8_2): Likewise.
 243         (SR_V8_3): Likewise.
 244         (SR_V8_4): Likewise.
 245         (SR_PAN): Likewise.
 246         (SR_RAS): Likewise.
 247         (SR_SSBS): Likewise.
 248         (SR_SVE): Likewise.
 249         (SR_ID_PFR2): Likewise.
 250         (SR_PROFILE): Likewise.
 251         (SR_MEMTAG): Likewise.
 252         (SR_SCXTNUM): Likewise.
 253         (aarch64_sys_regs): Refactor to store feature information in the table.
 254         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 255         that now describe their own features.
 256         (aarch64_pstatefield_supported_p): Likewise.
 257
 258 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 259
 260         * i386-dis.c (prefix_table): Fix a typo in comments.
 261
 262 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-dis.c (rex_ignored): Delete.
 265         (ckprefix): Drop rex_ignored initialization.
 266         (get_valid_dis386): Drop setting of rex_ignored.
 267         (print_insn): Drop checking of rex_ignored. Don't record data
 268         size prefix as used with VEX-and-alike encodings.
 269
 270 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 273         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 274         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 275         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 276         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 277         VEX_0F12, and VEX_0F16.
 278         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 279         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 280         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 281         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 282         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 283         MOD_VEX_0F16_PREFIX_2 entries.
 284
 285 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 288         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 289         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 290         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 291         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 292         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 293         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 294         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 295         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 296         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 297         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 298         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 299         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 300         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 301         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 302         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 303         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 304         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 305         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 306         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 307         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 308         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 309         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 310         EVEX_W_0FC6_P_2): Delete.
 311         (print_insn): Add EVEX.W vs embedded prefix consistency check
 312         to prefix validation.
 313         * i386-dis-evex.h (evex_table): Don't further descend for
 314         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 315         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 316         and 0F2B.
 317         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 318         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 319         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 320         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 321         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 322         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 323         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 324         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 325         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 326         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 327         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 328         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 329         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 330         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 331         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 332         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 333         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 334         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 335         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 336         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 337         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 338         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 339         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 340         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 341         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 342         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 343         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 344
 345 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 348         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 349         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 350         vmovmskpX.
 351         (print_insn): Drop pointless check against bad_opcode. Split
 352         prefix validation into legacy and VEX-and-alike parts.
 353         (putop): Re-work 'X' macro handling.
 354
 355 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-dis.c (MOD_0F51): Rename to ...
 358         (MOD_0F50): ... this.
 359
 360 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 361
 362         * arm-dis.c (arm_opcodes): Add dfb.
 363         (thumb32_opcodes): Add dfb.
 364
 365 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 368
 369 2020-06-06  Alan Modra  <amodra@gmail.com>
 370
 371         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 372
 373 2020-06-05  Alan Modra  <amodra@gmail.com>
 374
 375         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 376         size is large enough.
 377
 378 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 379
 380         * disassemble.c (disassemble_init_for_target): Set endian_code for
 381         bpf targets.
 382         * bpf-desc.c: Regenerate.
 383         * bpf-opc.c: Likewise.
 384         * bpf-dis.c: Likewise.
 385
 386 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 387
 388         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 389         (cgen_put_insn_value): Likewise.
 390         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 391         * cgen-dis.in (print_insn): Likewise.
 392         * cgen-ibld.in (insert_1): Likewise.
 393         (insert_1): Likewise.
 394         (insert_insn_normal): Likewise.
 395         (extract_1): Likewise.
 396         * bpf-dis.c: Regenerate.
 397         * bpf-ibld.c: Likewise.
 398         * bpf-ibld.c: Likewise.
 399         * cgen-dis.in: Likewise.
 400         * cgen-ibld.in: Likewise.
 401         * cgen-opc.c: Likewise.
 402         * epiphany-dis.c: Likewise.
 403         * epiphany-ibld.c: Likewise.
 404         * fr30-dis.c: Likewise.
 405         * fr30-ibld.c: Likewise.
 406         * frv-dis.c: Likewise.
 407         * frv-ibld.c: Likewise.
 408         * ip2k-dis.c: Likewise.
 409         * ip2k-ibld.c: Likewise.
 410         * iq2000-dis.c: Likewise.
 411         * iq2000-ibld.c: Likewise.
 412         * lm32-dis.c: Likewise.
 413         * lm32-ibld.c: Likewise.
 414         * m32c-dis.c: Likewise.
 415         * m32c-ibld.c: Likewise.
 416         * m32r-dis.c: Likewise.
 417         * m32r-ibld.c: Likewise.
 418         * mep-dis.c: Likewise.
 419         * mep-ibld.c: Likewise.
 420         * mt-dis.c: Likewise.
 421         * mt-ibld.c: Likewise.
 422         * or1k-dis.c: Likewise.
 423         * or1k-ibld.c: Likewise.
 424         * xc16x-dis.c: Likewise.
 425         * xc16x-ibld.c: Likewise.
 426         * xstormy16-dis.c: Likewise.
 427         * xstormy16-ibld.c: Likewise.
 428
 429 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 430
 431         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 432         (print_insn_): Handle instruction endian.
 433         * bpf-dis.c: Regenerate.
 434         * bpf-desc.c: Regenerate.
 435         * epiphany-dis.c: Likewise.
 436         * epiphany-desc.c: Likewise.
 437         * fr30-dis.c: Likewise.
 438         * fr30-desc.c: Likewise.
 439         * frv-dis.c: Likewise.
 440         * frv-desc.c: Likewise.
 441         * ip2k-dis.c: Likewise.
 442         * ip2k-desc.c: Likewise.
 443         * iq2000-dis.c: Likewise.
 444         * iq2000-desc.c: Likewise.
 445         * lm32-dis.c: Likewise.
 446         * lm32-desc.c: Likewise.
 447         * m32c-dis.c: Likewise.
 448         * m32c-desc.c: Likewise.
 449         * m32r-dis.c: Likewise.
 450         * m32r-desc.c: Likewise.
 451         * mep-dis.c: Likewise.
 452         * mep-desc.c: Likewise.
 453         * mt-dis.c: Likewise.
 454         * mt-desc.c: Likewise.
 455         * or1k-dis.c: Likewise.
 456         * or1k-desc.c: Likewise.
 457         * xc16x-dis.c: Likewise.
 458         * xc16x-desc.c: Likewise.
 459         * xstormy16-dis.c: Likewise.
 460         * xstormy16-desc.c: Likewise.
 461
 462 2020-06-03  Nick Clifton  <nickc@redhat.com>
 463
 464         * po/sr.po: Updated Serbian translation.
 465
 466 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 467
 468         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 469         (riscv_get_priv_spec_class): Likewise.
 470
 471 2020-06-01  Alan Modra  <amodra@gmail.com>
 472
 473         * bpf-desc.c: Regenerate.
 474
 475 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 476             David Faust <david.faust@oracle.com>
 477
 478         * bpf-desc.c: Regenerate.
 479         * bpf-opc.h: Likewise.
 480         * bpf-opc.c: Likewise.
 481         * bpf-dis.c: Likewise.
 482
 483 2020-05-28  Alan Modra  <amodra@gmail.com>
 484
 485         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 486         values.
 487
 488 2020-05-28  Alan Modra  <amodra@gmail.com>
 489
 490         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 491         immediates.
 492         (print_insn_ns32k): Revert last change.
 493
 494 2020-05-28  Nick Clifton  <nickc@redhat.com>
 495
 496         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 497         static.
 498
 499 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 500
 501         Fix extraction of signed constants in nios2 disassembler (again).
 502
 503         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 504         extractions of signed fields.
 505
 506 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 507
 508         * s390-opc.txt: Relocate vector load/store instructions with
 509         additional alignment parameter and change architecture level
 510         constraint from z14 to z13.
 511
 512 2020-05-21  Alan Modra  <amodra@gmail.com>
 513
 514         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 515         * sparc-dis.c: Likewise.
 516         * tic4x-dis.c: Likewise.
 517         * xtensa-dis.c: Likewise.
 518         * bpf-desc.c: Regenerate.
 519         * epiphany-desc.c: Regenerate.
 520         * fr30-desc.c: Regenerate.
 521         * frv-desc.c: Regenerate.
 522         * ip2k-desc.c: Regenerate.
 523         * iq2000-desc.c: Regenerate.
 524         * lm32-desc.c: Regenerate.
 525         * m32c-desc.c: Regenerate.
 526         * m32r-desc.c: Regenerate.
 527         * mep-asm.c: Regenerate.
 528         * mep-desc.c: Regenerate.
 529         * mt-desc.c: Regenerate.
 530         * or1k-desc.c: Regenerate.
 531         * xc16x-desc.c: Regenerate.
 532         * xstormy16-desc.c: Regenerate.
 533
 534 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 535
 536         * riscv-opc.c (riscv_ext_version_table): The table used to store
 537         all information about the supported spec and the corresponding ISA
 538         versions.  Currently, only Zicsr is supported to verify the
 539         correctness of Z sub extension settings.  Others will be supported
 540         in the future patches.
 541         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 542         classes and the corresponding strings.
 543         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 544         spec class by giving a ISA spec string.
 545         * riscv-opc.c (struct priv_spec_t): New structure.
 546         (struct priv_spec_t priv_specs): List for all supported privilege spec
 547         classes and the corresponding strings.
 548         (riscv_get_priv_spec_class): New function.  Get the corresponding
 549         privilege spec class by giving a spec string.
 550         (riscv_get_priv_spec_name): New function.  Get the corresponding
 551         privilege spec string by giving a CSR version class.
 552         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 553         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 554         according to the chosen version.  Build a hash table riscv_csr_hash to
 555         store the valid CSR for the chosen pirv verison.  Dump the direct
 556         CSR address rather than it's name if it is invalid.
 557         (parse_riscv_dis_option_without_args): New function.  Parse the options
 558         without arguments.
 559         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 560         parse the options without arguments first, and then handle the options
 561         with arguments.  Add the new option -Mpriv-spec, which has argument.
 562         * riscv-dis.c (print_riscv_disassembler_options): Add description
 563         about the new OBJDUMP option.
 564
 565 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 566
 567         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 568         WC values on POWER10 sync, dcbf  and wait instructions.
 569         (insert_pl, extract_pl): New functions.
 570         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 571         (LS3): New , 3-bit L for sync.
 572         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 573         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 574         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 575         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 576         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 577         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 578         <wait>: Enable PL operand on POWER10.
 579         <dcbf>: Enable L3OPT operand on POWER10.
 580         <sync>: Enable SC2 operand on POWER10.
 581
 582 2020-05-19  Stafford Horne  <shorne@gmail.com>
 583
 584         PR 25184
 585         * or1k-asm.c: Regenerate.
 586         * or1k-desc.c: Regenerate.
 587         * or1k-desc.h: Regenerate.
 588         * or1k-dis.c: Regenerate.
 589         * or1k-ibld.c: Regenerate.
 590         * or1k-opc.c: Regenerate.
 591         * or1k-opc.h: Regenerate.
 592         * or1k-opinst.c: Regenerate.
 593
 594 2020-05-11  Alan Modra  <amodra@gmail.com>
 595
 596         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 597         xsmaxcqp, xsmincqp.
 598
 599 2020-05-11  Alan Modra  <amodra@gmail.com>
 600
 601         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 602         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 603
 604 2020-05-11  Alan Modra  <amodra@gmail.com>
 605
 606         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 607
 608 2020-05-11  Alan Modra  <amodra@gmail.com>
 609
 610         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 611         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 612
 613 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 614
 615         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 616         mnemonics.
 617
 618 2020-05-11  Alan Modra  <amodra@gmail.com>
 619
 620         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 621         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 622         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 623         (prefix_opcodes): Add xxeval.
 624
 625 2020-05-11  Alan Modra  <amodra@gmail.com>
 626
 627         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 628         xxgenpcvwm, xxgenpcvdm.
 629
 630 2020-05-11  Alan Modra  <amodra@gmail.com>
 631
 632         * ppc-opc.c (MP, VXVAM_MASK): Define.
 633         (VXVAPS_MASK): Use VXVA_MASK.
 634         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 635         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 636         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 637         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 638
 639 2020-05-11  Alan Modra  <amodra@gmail.com>
 640             Peter Bergner  <bergner@linux.ibm.com>
 641
 642         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 643         New functions.
 644         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 645         YMSK2, XA6a, XA6ap, XB6a entries.
 646         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 647         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 648         (PPCVSX4): Define.
 649         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 650         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 651         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 652         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 653         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 654         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 655         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 656         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 657         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 658         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 659         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 660         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 661         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 662         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 663
 664 2020-05-11  Alan Modra  <amodra@gmail.com>
 665
 666         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 667         (insert_xts, extract_xts): New functions.
 668         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 669         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 670         (VXRC_MASK, VXSH_MASK): Define.
 671         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 672         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 673         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 674         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 675         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 676         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 677         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 678
 679 2020-05-11  Alan Modra  <amodra@gmail.com>
 680
 681         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 682         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 683         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 684         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 685         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 686
 687 2020-05-11  Alan Modra  <amodra@gmail.com>
 688
 689         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 690         (XTP, DQXP, DQXP_MASK): Define.
 691         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 692         (prefix_opcodes): Add plxvp and pstxvp.
 693
 694 2020-05-11  Alan Modra  <amodra@gmail.com>
 695
 696         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 697         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 698         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 699
 700 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 701
 702         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 703
 704 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 705
 706         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 707         (L1OPT): Define.
 708         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 709
 710 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 711
 712         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 713
 714 2020-05-11  Alan Modra  <amodra@gmail.com>
 715
 716         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 717
 718 2020-05-11  Alan Modra  <amodra@gmail.com>
 719
 720         * ppc-dis.c (ppc_opts): Add "power10" entry.
 721         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 722         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 723
 724 2020-05-11  Nick Clifton  <nickc@redhat.com>
 725
 726         * po/fr.po: Updated French translation.
 727
 728 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 729
 730         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 731         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 732         (operand_general_constraint_met_p): validate
 733         AARCH64_OPND_UNDEFINED.
 734         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 735         for FLD_imm16_2.
 736         * aarch64-asm-2.c: Regenerated.
 737         * aarch64-dis-2.c: Regenerated.
 738         * aarch64-opc-2.c: Regenerated.
 739
 740 2020-04-29  Nick Clifton  <nickc@redhat.com>
 741
 742         PR 22699
 743         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 744         and SETRC insns.
 745
 746 2020-04-29  Nick Clifton  <nickc@redhat.com>
 747
 748         * po/sv.po: Updated Swedish translation.
 749
 750 2020-04-29  Nick Clifton  <nickc@redhat.com>
 751
 752         PR 22699
 753         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 754         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 755         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 756         IMM0_8U case.
 757
 758 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 759
 760         PR 25848
 761         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 762         cmpi only on m68020up and cpu32.
 763
 764 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 765
 766         * aarch64-asm.c (aarch64_ins_none): New.
 767         * aarch64-asm.h (ins_none): New declaration.
 768         * aarch64-dis.c (aarch64_ext_none): New.
 769         * aarch64-dis.h (ext_none): New declaration.
 770         * aarch64-opc.c (aarch64_print_operand): Update case for
 771         AARCH64_OPND_BARRIER_PSB.
 772         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 773         (AARCH64_OPERANDS): Update inserter/extracter for
 774         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 775         * aarch64-asm-2.c: Regenerated.
 776         * aarch64-dis-2.c: Regenerated.
 777         * aarch64-opc-2.c: Regenerated.
 778
 779 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 780
 781         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 782         (aarch64_feature_ras, RAS): Likewise.
 783         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 784         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 785         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 786         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 787         * aarch64-asm-2.c: Regenerated.
 788         * aarch64-dis-2.c: Regenerated.
 789         * aarch64-opc-2.c: Regenerated.
 790
 791 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 792
 793         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 794         (print_insn_neon): Support disassembly of conditional
 795         instructions.
 796
 797 2020-02-16  David Faust  <david.faust@oracle.com>
 798
 799         * bpf-desc.c: Regenerate.
 800         * bpf-desc.h: Likewise.
 801         * bpf-opc.c: Regenerate.
 802         * bpf-opc.h: Likewise.
 803
 804 2020-04-07  Lili Cui  <lili.cui@intel.com>
 805
 806         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 807         (prefix_table): New instructions (see prefixes above).
 808         (rm_table): Likewise
 809         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 810         CPU_ANY_TSXLDTRK_FLAGS.
 811         (cpu_flags): Add CpuTSXLDTRK.
 812         * i386-opc.h (enum): Add CpuTSXLDTRK.
 813         (i386_cpu_flags): Add cputsxldtrk.
 814         * i386-opc.tbl: Add XSUSPLDTRK insns.
 815         * i386-init.h: Regenerate.
 816         * i386-tbl.h: Likewise.
 817
 818 2020-04-02  Lili Cui  <lili.cui@intel.com>
 819
 820         * i386-dis.c (prefix_table): New instructions serialize.
 821         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 822         CPU_ANY_SERIALIZE_FLAGS.
 823         (cpu_flags): Add CpuSERIALIZE.
 824         * i386-opc.h (enum): Add CpuSERIALIZE.
 825         (i386_cpu_flags): Add cpuserialize.
 826         * i386-opc.tbl: Add SERIALIZE insns.
 827         * i386-init.h: Regenerate.
 828         * i386-tbl.h: Likewise.
 829
 830 2020-03-26  Alan Modra  <amodra@gmail.com>
 831
 832         * disassemble.h (opcodes_assert): Declare.
 833         (OPCODES_ASSERT): Define.
 834         * disassemble.c: Don't include assert.h.  Include opintl.h.
 835         (opcodes_assert): New function.
 836         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 837         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 838         calculate maxlen.  Omit insn decoding when insn length exceeds
 839         maxlen.  Exit from nibble loop when looking for E, before
 840         accessing next data byte.  Move processing of E outside loop.
 841         Replace tests of maxlen in loop with assertions.
 842
 843 2020-03-26  Alan Modra  <amodra@gmail.com>
 844
 845         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 846
 847 2020-03-25  Alan Modra  <amodra@gmail.com>
 848
 849         * z80-dis.c (suffix): Init mybuf.
 850
 851 2020-03-22  Alan Modra  <amodra@gmail.com>
 852
 853         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 854         successflly read from section.
 855
 856 2020-03-22  Alan Modra  <amodra@gmail.com>
 857
 858         * arc-dis.c (find_format): Use ISO C string concatenation rather
 859         than line continuation within a string.  Don't access needs_limm
 860         before testing opcode != NULL.
 861
 862 2020-03-22  Alan Modra  <amodra@gmail.com>
 863
 864         * ns32k-dis.c (print_insn_arg): Update comment.
 865         (print_insn_ns32k): Reduce size of index_offset array, and
 866         initialize, passing -1 to print_insn_arg for args that are not
 867         an index.  Don't exit arg loop early.  Abort on bad arg number.
 868
 869 2020-03-22  Alan Modra  <amodra@gmail.com>
 870
 871         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 872         * s12z-opc.c: Formatting.
 873         (operands_f): Return an int.
 874         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 875         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 876         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 877         (exg_sex_discrim): Likewise.
 878         (create_immediate_operand, create_bitfield_operand),
 879         (create_register_operand_with_size, create_register_all_operand),
 880         (create_register_all16_operand, create_simple_memory_operand),
 881         (create_memory_operand, create_memory_auto_operand): Don't
 882         segfault on malloc failure.
 883         (z_ext24_decode): Return an int status, negative on fail, zero
 884         on success.
 885         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 886         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 887         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 888         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 889         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 890         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 891         (loop_primitive_decode, shift_decode, psh_pul_decode),
 892         (bit_field_decode): Similarly.
 893         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 894         to return value, update callers.
 895         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 896         Don't segfault on NULL operand.
 897         (decode_operation): Return OP_INVALID on first fail.
 898         (decode_s12z): Check all reads, returning -1 on fail.
 899
 900 2020-03-20  Alan Modra  <amodra@gmail.com>
 901
 902         * metag-dis.c (print_insn_metag): Don't ignore status from
 903         read_memory_func.
 904
 905 2020-03-20  Alan Modra  <amodra@gmail.com>
 906
 907         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 908         Initialize parts of buffer not written when handling a possible
 909         2-byte insn at end of section.  Don't attempt decoding of such
 910         an insn by the 4-byte machinery.
 911
 912 2020-03-20  Alan Modra  <amodra@gmail.com>
 913
 914         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 915         partially filled buffer.  Prevent lookup of 4-byte insns when
 916         only VLE 2-byte insns are possible due to section size.  Print
 917         ".word" rather than ".long" for 2-byte leftovers.
 918
 919 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 920
 921         PR 25641
 922         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 923
 924 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-dis.c (X86_64_0D): Rename to ...
 927         (X86_64_0E): ... this.
 928
 929 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 930
 931         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 932         * Makefile.in: Regenerated.
 933
 934 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 937         3-operand pseudos.
 938         * i386-tbl.h: Re-generate.
 939
 940 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 943         vprot*, vpsha*, and vpshl*.
 944         * i386-tbl.h: Re-generate.
 945
 946 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 949         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 950         * i386-tbl.h: Re-generate.
 951
 952 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 955         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 956         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 957         * i386-tbl.h: Re-generate.
 958
 959 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-gen.c (struct template_arg, struct template_instance,
 962         struct template_param, struct template, templates,
 963         parse_template, expand_templates): New.
 964         (process_i386_opcodes): Various local variables moved to
 965         expand_templates. Call parse_template and expand_templates.
 966         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 967         * i386-tbl.h: Re-generate.
 968
 969 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 972         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 973         register and memory source templates. Replace VexW= by VexW*
 974         where applicable.
 975         * i386-tbl.h: Re-generate.
 976
 977 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 978
 979         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 980         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 981         * i386-tbl.h: Re-generate.
 982
 983 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 986         * i386-tbl.h: Re-generate.
 987
 988 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 991         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 992         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 993         VexW0 on SSE2AVX variants.
 994         (vmovq): Drop NoRex64 from XMM/XMM variants.
 995         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 996         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 997         applicable use VexW0.
 998         * i386-tbl.h: Re-generate.
 999
1000 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1003         * i386-opc.h (Rex64): Delete.
1004         (struct i386_opcode_modifier): Remove rex64 field.
1005         * i386-opc.tbl (crc32): Drop Rex64.
1006         Replace Rex64 with Size64 everywhere else.
1007         * i386-tbl.h: Re-generate.
1008
1009 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-dis.c (OP_E_memory): Exclude recording of used address
1012         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1013         addressed memory operands for MPX insns.
1014
1015 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1018         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1019         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1020         (ptwrite): Split into non-64-bit and 64-bit forms.
1021         * i386-tbl.h: Re-generate.
1022
1023 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1024
1025         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1026         template.
1027         * i386-tbl.h: Re-generate.
1028
1029 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1030
1031         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1032         (prefix_table): Move vmmcall here. Add vmgexit.
1033         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1034         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1035         (cpu_flags): Add CpuSEV_ES entry.
1036         * i386-opc.h (CpuSEV_ES): New.
1037         (union i386_cpu_flags): Add cpusev_es field.
1038         * i386-opc.tbl (vmgexit): New.
1039         * i386-init.h, i386-tbl.h: Re-generate.
1040
1041 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1042
1043         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1044         with MnemonicSize.
1045         * i386-opc.h (IGNORESIZE): New.
1046         (DEFAULTSIZE): Likewise.
1047         (IgnoreSize): Removed.
1048         (DefaultSize): Likewise.
1049         (MnemonicSize): New.
1050         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1051         mnemonicsize.
1052         * i386-opc.tbl (IgnoreSize): New.
1053         (DefaultSize): Likewise.
1054         * i386-tbl.h: Regenerated.
1055
1056 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1057
1058         PR 25627
1059         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1060         instructions.
1061
1062 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1063
1064         PR gas/25622
1065         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1066         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1067         * i386-tbl.h: Regenerated.
1068
1069 2020-02-26  Alan Modra  <amodra@gmail.com>
1070
1071         * aarch64-asm.c: Indent labels correctly.
1072         * aarch64-dis.c: Likewise.
1073         * aarch64-gen.c: Likewise.
1074         * aarch64-opc.c: Likewise.
1075         * alpha-dis.c: Likewise.
1076         * i386-dis.c: Likewise.
1077         * nds32-asm.c: Likewise.
1078         * nfp-dis.c: Likewise.
1079         * visium-dis.c: Likewise.
1080
1081 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1082
1083         * arc-regs.h (int_vector_base): Make it available for all ARC
1084         CPUs.
1085
1086 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1087
1088         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1089         changed.
1090
1091 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1092
1093         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1094         c.mv/c.li if rs1 is zero.
1095
1096 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1097
1098         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1099         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1100         CPU_POPCNT_FLAGS.
1101         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1102         * i386-opc.h (CpuABM): Removed.
1103         (CpuPOPCNT): New.
1104         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1105         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1106         popcnt.  Remove CpuABM from lzcnt.
1107         * i386-init.h: Regenerated.
1108         * i386-tbl.h: Likewise.
1109
1110 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1113         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1114         VexW1 instead of open-coding them.
1115         * i386-tbl.h: Re-generate.
1116
1117 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-opc.tbl (AddrPrefixOpReg): Define.
1120         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1121         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1122         templates. Drop NoRex64.
1123         * i386-tbl.h: Re-generate.
1124
1125 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1126
1127         PR gas/6518
1128         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1129         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1130         into Intel syntax instance (with Unpsecified) and AT&T one
1131         (without).
1132         (vcvtneps2bf16): Likewise, along with folding the two so far
1133         separate ones.
1134         * i386-tbl.h: Re-generate.
1135
1136 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1137
1138         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1139         CPU_ANY_SSE4A_FLAGS.
1140
1141 2020-02-17  Alan Modra  <amodra@gmail.com>
1142
1143         * i386-gen.c (cpu_flag_init): Correct last change.
1144
1145 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1146
1147         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1148         CPU_ANY_SSE4_FLAGS.
1149
1150 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1153         (movzx): Likewise.
1154
1155 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1156
1157         PR gas/25438
1158         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1159         destination for Cpu64-only variant.
1160         (movzx): Fold patterns.
1161         * i386-tbl.h: Re-generate.
1162
1163 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1164
1165         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1166         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1167         CPU_ANY_SSE4_FLAGS entry.
1168         * i386-init.h: Re-generate.
1169
1170 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1173         with Unspecified, making the present one AT&T syntax only.
1174         * i386-tbl.h: Re-generate.
1175
1176 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1177
1178         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1179         * i386-tbl.h: Re-generate.
1180
1181 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1182
1183         PR gas/24546
1184         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1185         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1186         Amd64 and Intel64 templates.
1187         (call, jmp): Likewise for far indirect variants. Dro
1188         Unspecified.
1189         * i386-tbl.h: Re-generate.
1190
1191 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1194         * i386-opc.h (ShortForm): Delete.
1195         (struct i386_opcode_modifier): Remove shortform field.
1196         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1197         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1198         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1199         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1200         Drop ShortForm.
1201         * i386-tbl.h: Re-generate.
1202
1203 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1204
1205         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1206         fucompi): Drop ShortForm from operand-less templates.
1207         * i386-tbl.h: Re-generate.
1208
1209 2020-02-11  Alan Modra  <amodra@gmail.com>
1210
1211         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1212         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1213         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1214         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1215         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1216
1217 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1218
1219         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1220         (cde_opcodes): Add VCX* instructions.
1221
1222 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1223             Matthew Malcomson  <matthew.malcomson@arm.com>
1224
1225         * arm-dis.c (struct cdeopcode32): New.
1226         (CDE_OPCODE): New macro.
1227         (cde_opcodes): New disassembly table.
1228         (regnames): New option to table.
1229         (cde_coprocs): New global variable.
1230         (print_insn_cde): New
1231         (print_insn_thumb32): Use print_insn_cde.
1232         (parse_arm_disassembler_options): Parse coprocN args.
1233
1234 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         PR gas/25516
1237         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1238         with ISA64.
1239         * i386-opc.h (AMD64): Removed.
1240         (Intel64): Likewose.
1241         (AMD64): New.
1242         (INTEL64): Likewise.
1243         (INTEL64ONLY): Likewise.
1244         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1245         * i386-opc.tbl (Amd64): New.
1246         (Intel64): Likewise.
1247         (Intel64Only): Likewise.
1248         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1249         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1250         * i386-tbl.h: Regenerated.
1251
1252 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1253
1254         PR 25469
1255         * z80-dis.c: Add support for GBZ80 opcodes.
1256
1257 2020-02-04  Alan Modra  <amodra@gmail.com>
1258
1259         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1260
1261 2020-02-03  Alan Modra  <amodra@gmail.com>
1262
1263         * m32c-ibld.c: Regenerate.
1264
1265 2020-02-01  Alan Modra  <amodra@gmail.com>
1266
1267         * frv-ibld.c: Regenerate.
1268
1269 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1270
1271         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1272         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1273         (OP_E_memory): Replace xmm_mdq_mode case label by
1274         vex_scalar_w_dq_mode one.
1275         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1276
1277 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1278
1279         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1280         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1281         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1282         (intel_operand_size): Drop vex_w_dq_mode case label.
1283
1284 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1285
1286         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1287         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1288
1289 2020-01-30  Alan Modra  <amodra@gmail.com>
1290
1291         * m32c-ibld.c: Regenerate.
1292
1293 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1294
1295         * bpf-opc.c: Regenerate.
1296
1297 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1298
1299         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1300         (dis386): Use them to replace C2/C3 table entries.
1301         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1302         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1303         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1304         * i386-tbl.h: Re-generate.
1305
1306 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1307
1308         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1309         forms.
1310         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1311         DefaultSize.
1312         * i386-tbl.h: Re-generate.
1313
1314 2020-01-30  Alan Modra  <amodra@gmail.com>
1315
1316         * tic4x-dis.c (tic4x_dp): Make unsigned.
1317
1318 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1319             Jan Beulich  <jbeulich@suse.com>
1320
1321         PR binutils/25445
1322         * i386-dis.c (MOVSXD_Fixup): New function.
1323         (movsxd_mode): New enum.
1324         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1325         (intel_operand_size): Handle movsxd_mode.
1326         (OP_E_register): Likewise.
1327         (OP_G): Likewise.
1328         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1329         register on movsxd.  Add movsxd with 16-bit destination register
1330         for AMD64 and Intel64 ISAs.
1331         * i386-tbl.h: Regenerated.
1332
1333 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1334
1335         PR 25403
1336         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1337         * aarch64-asm-2.c: Regenerate
1338         * aarch64-dis-2.c: Likewise.
1339         * aarch64-opc-2.c: Likewise.
1340
1341 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1342
1343         * i386-opc.tbl (sysret): Drop DefaultSize.
1344         * i386-tbl.h: Re-generate.
1345
1346 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1349         Dword.
1350         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1351         * i386-tbl.h: Re-generate.
1352
1353 2020-01-20  Nick Clifton  <nickc@redhat.com>
1354
1355         * po/de.po: Updated German translation.
1356         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1357         * po/uk.po: Updated Ukranian translation.
1358
1359 2020-01-20  Alan Modra  <amodra@gmail.com>
1360
1361         * hppa-dis.c (fput_const): Remove useless cast.
1362
1363 2020-01-20  Alan Modra  <amodra@gmail.com>
1364
1365         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1366
1367 2020-01-18  Nick Clifton  <nickc@redhat.com>
1368
1369         * configure: Regenerate.
1370         * po/opcodes.pot: Regenerate.
1371
1372 2020-01-18  Nick Clifton  <nickc@redhat.com>
1373
1374         Binutils 2.34 branch created.
1375
1376 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1377
1378         * opintl.h: Fix spelling error (seperate).
1379
1380 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1381
1382         * i386-opc.tbl: Add {vex} pseudo prefix.
1383         * i386-tbl.h: Regenerated.
1384
1385 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1386
1387         PR 25376
1388         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1389         (neon_opcodes): Likewise.
1390         (select_arm_features): Make sure we enable MVE bits when selecting
1391         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1392         any architecture.
1393
1394 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1395
1396         * i386-opc.tbl: Drop stale comment from XOP section.
1397
1398 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1399
1400         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1401         (extractps): Add VexWIG to SSE2AVX forms.
1402         * i386-tbl.h: Re-generate.
1403
1404 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1405
1406         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1407         Size64 from and use VexW1 on SSE2AVX forms.
1408         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1409         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1410         * i386-tbl.h: Re-generate.
1411
1412 2020-01-15  Alan Modra  <amodra@gmail.com>
1413
1414         * tic4x-dis.c (tic4x_version): Make unsigned long.
1415         (optab, optab_special, registernames): New file scope vars.
1416         (tic4x_print_register): Set up registernames rather than
1417         malloc'd registertable.
1418         (tic4x_disassemble): Delete optable and optable_special.  Use
1419         optab and optab_special instead.  Throw away old optab,
1420         optab_special and registernames when info->mach changes.
1421
1422 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1423
1424         PR 25377
1425         * z80-dis.c (suffix): Use .db instruction to generate double
1426         prefix.
1427
1428 2020-01-14  Alan Modra  <amodra@gmail.com>
1429
1430         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1431         values to unsigned before shifting.
1432
1433 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1434
1435         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1436         flow instructions.
1437         (print_insn_thumb16, print_insn_thumb32): Likewise.
1438         (print_insn): Initialize the insn info.
1439         * i386-dis.c (print_insn): Initialize the insn info fields, and
1440         detect jumps.
1441
1442 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1443
1444         * arc-opc.c (C_NE): Make it required.
1445
1446 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1447
1448         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1449         reserved register name.
1450
1451 2020-01-13  Alan Modra  <amodra@gmail.com>
1452
1453         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1454         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1455
1456 2020-01-13  Alan Modra  <amodra@gmail.com>
1457
1458         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1459         result of wasm_read_leb128 in a uint64_t and check that bits
1460         are not lost when copying to other locals.  Use uint32_t for
1461         most locals.  Use PRId64 when printing int64_t.
1462
1463 2020-01-13  Alan Modra  <amodra@gmail.com>
1464
1465         * score-dis.c: Formatting.
1466         * score7-dis.c: Formatting.
1467
1468 2020-01-13  Alan Modra  <amodra@gmail.com>
1469
1470         * score-dis.c (print_insn_score48): Use unsigned variables for
1471         unsigned values.  Don't left shift negative values.
1472         (print_insn_score32): Likewise.
1473         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1474
1475 2020-01-13  Alan Modra  <amodra@gmail.com>
1476
1477         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1478
1479 2020-01-13  Alan Modra  <amodra@gmail.com>
1480
1481         * fr30-ibld.c: Regenerate.
1482
1483 2020-01-13  Alan Modra  <amodra@gmail.com>
1484
1485         * xgate-dis.c (print_insn): Don't left shift signed value.
1486         (ripBits): Formatting, use 1u.
1487
1488 2020-01-10  Alan Modra  <amodra@gmail.com>
1489
1490         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1491         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1492
1493 2020-01-10  Alan Modra  <amodra@gmail.com>
1494
1495         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1496         and XRREG value earlier to avoid a shift with negative exponent.
1497         * m10200-dis.c (disassemble): Similarly.
1498
1499 2020-01-09  Nick Clifton  <nickc@redhat.com>
1500
1501         PR 25224
1502         * z80-dis.c (ld_ii_ii): Use correct cast.
1503
1504 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1505
1506         PR 25224
1507         * z80-dis.c (ld_ii_ii): Use character constant when checking
1508         opcode byte value.
1509
1510 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1511
1512         * i386-dis.c (SEP_Fixup): New.
1513         (SEP): Define.
1514         (dis386_twobyte): Use it for sysenter/sysexit.
1515         (enum x86_64_isa): Change amd64 enumerator to value 1.
1516         (OP_J): Compare isa64 against intel64 instead of amd64.
1517         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1518         forms.
1519         * i386-tbl.h: Re-generate.
1520
1521 2020-01-08  Alan Modra  <amodra@gmail.com>
1522
1523         * z8k-dis.c: Include libiberty.h
1524         (instr_data_s): Make max_fetched unsigned.
1525         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1526         Don't exceed byte_info bounds.
1527         (output_instr): Make num_bytes unsigned.
1528         (unpack_instr): Likewise for nibl_count and loop.
1529         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1530         idx unsigned.
1531         * z8k-opc.h: Regenerate.
1532
1533 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1534
1535         * arc-tbl.h (llock): Use 'LLOCK' as class.
1536         (llockd): Likewise.
1537         (scond): Use 'SCOND' as class.
1538         (scondd): Likewise.
1539         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1540         (scondd): Likewise.
1541
1542 2020-01-06  Alan Modra  <amodra@gmail.com>
1543
1544         * m32c-ibld.c: Regenerate.
1545
1546 2020-01-06  Alan Modra  <amodra@gmail.com>
1547
1548         PR 25344
1549         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1550         Peek at next byte to prevent recursion on repeated prefix bytes.
1551         Ensure uninitialised "mybuf" is not accessed.
1552         (print_insn_z80): Don't zero n_fetch and n_used here,..
1553         (print_insn_z80_buf): ..do it here instead.
1554
1555 2020-01-04  Alan Modra  <amodra@gmail.com>
1556
1557         * m32r-ibld.c: Regenerate.
1558
1559 2020-01-04  Alan Modra  <amodra@gmail.com>
1560
1561         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1562
1563 2020-01-04  Alan Modra  <amodra@gmail.com>
1564
1565         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1566
1567 2020-01-04  Alan Modra  <amodra@gmail.com>
1568
1569         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1570
1571 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1572
1573         * aarch64-tbl.h (aarch64_opcode_table): Use
1574         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1575
1576 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1577
1578         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1579         forms of SUDOT and USDOT.
1580
1581 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1582
1583         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1584         uzip{1,2}.
1585         * opcodes/aarch64-dis-2.c: Re-generate.
1586
1587 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1588
1589         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1590         FMMLA encoding.
1591         * opcodes/aarch64-dis-2.c: Re-generate.
1592
1593 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1594
1595         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1596
1597 2020-01-01  Alan Modra  <amodra@gmail.com>
1598
1599         Update year range in copyright notice of all files.
1600
1601 For older changes see ChangeLog-2019
1602 \f
1603 Copyright (C) 2020 Free Software Foundation, Inc.
1604
1605 Copying and distribution of this file, with or without modification,
1606 are permitted in any medium without royalty provided the copyright
1607 notice and this notice are preserved.
1608
1609 Local Variables:
1610 mode: change-log
1611 left-margin: 8
1612 fill-column: 74
1613 version-control: never
1614 End: