opcodes/ChangeLog

   1 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/26237
   4         * i386-dis.c (OP_E_memory): Without base nor index registers,
   5         zero-extend lower 32-bit displacement to 64 bits.
   6
   7 2020-07-06  Nick Clifton  <nickc@redhat.com>
   8
   9         * po/pt_BR.po: Updated Brazilian Portugugese translation.
  10         * po/uk.po: Updated Ukranian translation.
  11
  12 2020-07-04  Nick Clifton  <nickc@redhat.com>
  13
  14         * configure: Regenerate.
  15         * po/opcodes.pot: Regenerate.
  16
  17 2020-07-04  Nick Clifton  <nickc@redhat.com>
  18
  19         Binutils 2.35 branch created.
  20
  21 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
  24         * i386-opc.h (VexSwapSources): New.
  25         (i386_opcode_modifier): Add vexswapsources.
  26         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
  27         with two source operands swapped.
  28         * i386-tbl.h: Regenerated.
  29
  30 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
  31
  32         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
  33         unprivileged CSR can also be initialized.
  34
  35 2020-06-29  Alan Modra  <amodra@gmail.com>
  36
  37         * arm-dis.c: Use C style comments.
  38         * cr16-opc.c: Likewise.
  39         * ft32-dis.c: Likewise.
  40         * moxie-opc.c: Likewise.
  41         * tic54x-dis.c: Likewise.
  42         * s12z-opc.c: Remove useless comment.
  43         * xgate-dis.c: Likewise.
  44
  45 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  46
  47         * i386-opc.tbl: Add a blank line.
  48
  49 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
  52         (VecSIB128): Renamed to ...
  53         (VECSIB128): This.
  54         (VecSIB256): Renamed to ...
  55         (VECSIB256): This.
  56         (VecSIB512): Renamed to ...
  57         (VECSIB512): This.
  58         (VecSIB): Renamed to ...
  59         (SIB): This.
  60         (i386_opcode_modifier): Replace vecsib with sib.
  61         * i386-opc.tbl (VecSIB128): New.
  62         (VecSIB256): Likewise.
  63         (VecSIB512): Likewise.
  64         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  65         and VecSIB512, respectively.
  66
  67 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-dis.c: Adjust description of I macro.
  70         (x86_64_table): Drop use of I.
  71         (float_mem): Replace use of I.
  72         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  73
  74 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-dis.c: (print_insn): Avoid straight assignment to
  77         priv.orig_sizeflag when processing -M sub-options.
  78
  79 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-dis.c: Adjust description of J macro.
  82         (dis386, x86_64_table, mod_table): Replace J.
  83         (putop): Remove handling of J.
  84
  85 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  88
  89 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-dis.c: Adjust description of "LQ" macro.
  92         (dis386_twobyte): Use LQ for sysret.
  93         (putop): Adjust handling of LQ.
  94
  95 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  96
  97         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  98         * riscv-dis.c: Include elfxx-riscv.h.
  99
 100 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 103
 104 2020-06-17  Lili Cui  <lili.cui@intel.com>
 105
 106         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 107
 108 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         PR gas/26115
 111         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 112         * i386-opc.tbl: Likewise.
 113         * i386-tbl.h: Regenerated.
 114
 115 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 116
 117         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 118
 119 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 120
 121         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 122         (SR_CORE): Likewise.
 123         (SR_FEAT): Likewise.
 124         (SR_RNG): Likewise.
 125         (SR_V8_1): Likewise.
 126         (SR_V8_2): Likewise.
 127         (SR_V8_3): Likewise.
 128         (SR_V8_4): Likewise.
 129         (SR_PAN): Likewise.
 130         (SR_RAS): Likewise.
 131         (SR_SSBS): Likewise.
 132         (SR_SVE): Likewise.
 133         (SR_ID_PFR2): Likewise.
 134         (SR_PROFILE): Likewise.
 135         (SR_MEMTAG): Likewise.
 136         (SR_SCXTNUM): Likewise.
 137         (aarch64_sys_regs): Refactor to store feature information in the table.
 138         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 139         that now describe their own features.
 140         (aarch64_pstatefield_supported_p): Likewise.
 141
 142 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         * i386-dis.c (prefix_table): Fix a typo in comments.
 145
 146 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-dis.c (rex_ignored): Delete.
 149         (ckprefix): Drop rex_ignored initialization.
 150         (get_valid_dis386): Drop setting of rex_ignored.
 151         (print_insn): Drop checking of rex_ignored. Don't record data
 152         size prefix as used with VEX-and-alike encodings.
 153
 154 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 157         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 158         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 159         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 160         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 161         VEX_0F12, and VEX_0F16.
 162         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 163         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 164         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 165         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 166         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 167         MOD_VEX_0F16_PREFIX_2 entries.
 168
 169 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 172         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 173         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 174         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 175         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 176         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 177         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 178         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 179         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 180         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 181         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 182         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 183         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 184         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 185         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 186         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 187         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 188         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 189         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 190         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 191         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 192         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 193         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 194         EVEX_W_0FC6_P_2): Delete.
 195         (print_insn): Add EVEX.W vs embedded prefix consistency check
 196         to prefix validation.
 197         * i386-dis-evex.h (evex_table): Don't further descend for
 198         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 199         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 200         and 0F2B.
 201         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 202         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 203         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 204         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 205         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 206         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 207         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 208         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 209         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 210         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 211         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 212         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 213         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 214         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 215         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 216         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 217         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 218         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 219         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 220         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 221         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 222         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 223         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 224         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 225         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 226         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 227         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 228
 229 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 232         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 233         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 234         vmovmskpX.
 235         (print_insn): Drop pointless check against bad_opcode. Split
 236         prefix validation into legacy and VEX-and-alike parts.
 237         (putop): Re-work 'X' macro handling.
 238
 239 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 240
 241         * i386-dis.c (MOD_0F51): Rename to ...
 242         (MOD_0F50): ... this.
 243
 244 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 245
 246         * arm-dis.c (arm_opcodes): Add dfb.
 247         (thumb32_opcodes): Add dfb.
 248
 249 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 252
 253 2020-06-06  Alan Modra  <amodra@gmail.com>
 254
 255         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 256
 257 2020-06-05  Alan Modra  <amodra@gmail.com>
 258
 259         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 260         size is large enough.
 261
 262 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 263
 264         * disassemble.c (disassemble_init_for_target): Set endian_code for
 265         bpf targets.
 266         * bpf-desc.c: Regenerate.
 267         * bpf-opc.c: Likewise.
 268         * bpf-dis.c: Likewise.
 269
 270 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 271
 272         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 273         (cgen_put_insn_value): Likewise.
 274         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 275         * cgen-dis.in (print_insn): Likewise.
 276         * cgen-ibld.in (insert_1): Likewise.
 277         (insert_1): Likewise.
 278         (insert_insn_normal): Likewise.
 279         (extract_1): Likewise.
 280         * bpf-dis.c: Regenerate.
 281         * bpf-ibld.c: Likewise.
 282         * bpf-ibld.c: Likewise.
 283         * cgen-dis.in: Likewise.
 284         * cgen-ibld.in: Likewise.
 285         * cgen-opc.c: Likewise.
 286         * epiphany-dis.c: Likewise.
 287         * epiphany-ibld.c: Likewise.
 288         * fr30-dis.c: Likewise.
 289         * fr30-ibld.c: Likewise.
 290         * frv-dis.c: Likewise.
 291         * frv-ibld.c: Likewise.
 292         * ip2k-dis.c: Likewise.
 293         * ip2k-ibld.c: Likewise.
 294         * iq2000-dis.c: Likewise.
 295         * iq2000-ibld.c: Likewise.
 296         * lm32-dis.c: Likewise.
 297         * lm32-ibld.c: Likewise.
 298         * m32c-dis.c: Likewise.
 299         * m32c-ibld.c: Likewise.
 300         * m32r-dis.c: Likewise.
 301         * m32r-ibld.c: Likewise.
 302         * mep-dis.c: Likewise.
 303         * mep-ibld.c: Likewise.
 304         * mt-dis.c: Likewise.
 305         * mt-ibld.c: Likewise.
 306         * or1k-dis.c: Likewise.
 307         * or1k-ibld.c: Likewise.
 308         * xc16x-dis.c: Likewise.
 309         * xc16x-ibld.c: Likewise.
 310         * xstormy16-dis.c: Likewise.
 311         * xstormy16-ibld.c: Likewise.
 312
 313 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 314
 315         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 316         (print_insn_): Handle instruction endian.
 317         * bpf-dis.c: Regenerate.
 318         * bpf-desc.c: Regenerate.
 319         * epiphany-dis.c: Likewise.
 320         * epiphany-desc.c: Likewise.
 321         * fr30-dis.c: Likewise.
 322         * fr30-desc.c: Likewise.
 323         * frv-dis.c: Likewise.
 324         * frv-desc.c: Likewise.
 325         * ip2k-dis.c: Likewise.
 326         * ip2k-desc.c: Likewise.
 327         * iq2000-dis.c: Likewise.
 328         * iq2000-desc.c: Likewise.
 329         * lm32-dis.c: Likewise.
 330         * lm32-desc.c: Likewise.
 331         * m32c-dis.c: Likewise.
 332         * m32c-desc.c: Likewise.
 333         * m32r-dis.c: Likewise.
 334         * m32r-desc.c: Likewise.
 335         * mep-dis.c: Likewise.
 336         * mep-desc.c: Likewise.
 337         * mt-dis.c: Likewise.
 338         * mt-desc.c: Likewise.
 339         * or1k-dis.c: Likewise.
 340         * or1k-desc.c: Likewise.
 341         * xc16x-dis.c: Likewise.
 342         * xc16x-desc.c: Likewise.
 343         * xstormy16-dis.c: Likewise.
 344         * xstormy16-desc.c: Likewise.
 345
 346 2020-06-03  Nick Clifton  <nickc@redhat.com>
 347
 348         * po/sr.po: Updated Serbian translation.
 349
 350 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 351
 352         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 353         (riscv_get_priv_spec_class): Likewise.
 354
 355 2020-06-01  Alan Modra  <amodra@gmail.com>
 356
 357         * bpf-desc.c: Regenerate.
 358
 359 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 360             David Faust <david.faust@oracle.com>
 361
 362         * bpf-desc.c: Regenerate.
 363         * bpf-opc.h: Likewise.
 364         * bpf-opc.c: Likewise.
 365         * bpf-dis.c: Likewise.
 366
 367 2020-05-28  Alan Modra  <amodra@gmail.com>
 368
 369         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 370         values.
 371
 372 2020-05-28  Alan Modra  <amodra@gmail.com>
 373
 374         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 375         immediates.
 376         (print_insn_ns32k): Revert last change.
 377
 378 2020-05-28  Nick Clifton  <nickc@redhat.com>
 379
 380         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 381         static.
 382
 383 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 384
 385         Fix extraction of signed constants in nios2 disassembler (again).
 386
 387         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 388         extractions of signed fields.
 389
 390 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 391
 392         * s390-opc.txt: Relocate vector load/store instructions with
 393         additional alignment parameter and change architecture level
 394         constraint from z14 to z13.
 395
 396 2020-05-21  Alan Modra  <amodra@gmail.com>
 397
 398         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 399         * sparc-dis.c: Likewise.
 400         * tic4x-dis.c: Likewise.
 401         * xtensa-dis.c: Likewise.
 402         * bpf-desc.c: Regenerate.
 403         * epiphany-desc.c: Regenerate.
 404         * fr30-desc.c: Regenerate.
 405         * frv-desc.c: Regenerate.
 406         * ip2k-desc.c: Regenerate.
 407         * iq2000-desc.c: Regenerate.
 408         * lm32-desc.c: Regenerate.
 409         * m32c-desc.c: Regenerate.
 410         * m32r-desc.c: Regenerate.
 411         * mep-asm.c: Regenerate.
 412         * mep-desc.c: Regenerate.
 413         * mt-desc.c: Regenerate.
 414         * or1k-desc.c: Regenerate.
 415         * xc16x-desc.c: Regenerate.
 416         * xstormy16-desc.c: Regenerate.
 417
 418 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 419
 420         * riscv-opc.c (riscv_ext_version_table): The table used to store
 421         all information about the supported spec and the corresponding ISA
 422         versions.  Currently, only Zicsr is supported to verify the
 423         correctness of Z sub extension settings.  Others will be supported
 424         in the future patches.
 425         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 426         classes and the corresponding strings.
 427         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 428         spec class by giving a ISA spec string.
 429         * riscv-opc.c (struct priv_spec_t): New structure.
 430         (struct priv_spec_t priv_specs): List for all supported privilege spec
 431         classes and the corresponding strings.
 432         (riscv_get_priv_spec_class): New function.  Get the corresponding
 433         privilege spec class by giving a spec string.
 434         (riscv_get_priv_spec_name): New function.  Get the corresponding
 435         privilege spec string by giving a CSR version class.
 436         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 437         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 438         according to the chosen version.  Build a hash table riscv_csr_hash to
 439         store the valid CSR for the chosen pirv verison.  Dump the direct
 440         CSR address rather than it's name if it is invalid.
 441         (parse_riscv_dis_option_without_args): New function.  Parse the options
 442         without arguments.
 443         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 444         parse the options without arguments first, and then handle the options
 445         with arguments.  Add the new option -Mpriv-spec, which has argument.
 446         * riscv-dis.c (print_riscv_disassembler_options): Add description
 447         about the new OBJDUMP option.
 448
 449 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 450
 451         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 452         WC values on POWER10 sync, dcbf  and wait instructions.
 453         (insert_pl, extract_pl): New functions.
 454         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 455         (LS3): New , 3-bit L for sync.
 456         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 457         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 458         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 459         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 460         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 461         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 462         <wait>: Enable PL operand on POWER10.
 463         <dcbf>: Enable L3OPT operand on POWER10.
 464         <sync>: Enable SC2 operand on POWER10.
 465
 466 2020-05-19  Stafford Horne  <shorne@gmail.com>
 467
 468         PR 25184
 469         * or1k-asm.c: Regenerate.
 470         * or1k-desc.c: Regenerate.
 471         * or1k-desc.h: Regenerate.
 472         * or1k-dis.c: Regenerate.
 473         * or1k-ibld.c: Regenerate.
 474         * or1k-opc.c: Regenerate.
 475         * or1k-opc.h: Regenerate.
 476         * or1k-opinst.c: Regenerate.
 477
 478 2020-05-11  Alan Modra  <amodra@gmail.com>
 479
 480         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 481         xsmaxcqp, xsmincqp.
 482
 483 2020-05-11  Alan Modra  <amodra@gmail.com>
 484
 485         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 486         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 487
 488 2020-05-11  Alan Modra  <amodra@gmail.com>
 489
 490         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 491
 492 2020-05-11  Alan Modra  <amodra@gmail.com>
 493
 494         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 495         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 496
 497 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 498
 499         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 500         mnemonics.
 501
 502 2020-05-11  Alan Modra  <amodra@gmail.com>
 503
 504         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 505         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 506         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 507         (prefix_opcodes): Add xxeval.
 508
 509 2020-05-11  Alan Modra  <amodra@gmail.com>
 510
 511         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 512         xxgenpcvwm, xxgenpcvdm.
 513
 514 2020-05-11  Alan Modra  <amodra@gmail.com>
 515
 516         * ppc-opc.c (MP, VXVAM_MASK): Define.
 517         (VXVAPS_MASK): Use VXVA_MASK.
 518         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 519         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 520         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 521         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 522
 523 2020-05-11  Alan Modra  <amodra@gmail.com>
 524             Peter Bergner  <bergner@linux.ibm.com>
 525
 526         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 527         New functions.
 528         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 529         YMSK2, XA6a, XA6ap, XB6a entries.
 530         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 531         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 532         (PPCVSX4): Define.
 533         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 534         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 535         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 536         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 537         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 538         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 539         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 540         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 541         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 542         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 543         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 544         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 545         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 546         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 547
 548 2020-05-11  Alan Modra  <amodra@gmail.com>
 549
 550         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 551         (insert_xts, extract_xts): New functions.
 552         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 553         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 554         (VXRC_MASK, VXSH_MASK): Define.
 555         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 556         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 557         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 558         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 559         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 560         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 561         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 562
 563 2020-05-11  Alan Modra  <amodra@gmail.com>
 564
 565         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 566         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 567         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 568         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 569         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 570
 571 2020-05-11  Alan Modra  <amodra@gmail.com>
 572
 573         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 574         (XTP, DQXP, DQXP_MASK): Define.
 575         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 576         (prefix_opcodes): Add plxvp and pstxvp.
 577
 578 2020-05-11  Alan Modra  <amodra@gmail.com>
 579
 580         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 581         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 582         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 583
 584 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 585
 586         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 587
 588 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 589
 590         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 591         (L1OPT): Define.
 592         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 593
 594 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 595
 596         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 597
 598 2020-05-11  Alan Modra  <amodra@gmail.com>
 599
 600         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 601
 602 2020-05-11  Alan Modra  <amodra@gmail.com>
 603
 604         * ppc-dis.c (ppc_opts): Add "power10" entry.
 605         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 606         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 607
 608 2020-05-11  Nick Clifton  <nickc@redhat.com>
 609
 610         * po/fr.po: Updated French translation.
 611
 612 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 613
 614         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 615         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 616         (operand_general_constraint_met_p): validate
 617         AARCH64_OPND_UNDEFINED.
 618         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 619         for FLD_imm16_2.
 620         * aarch64-asm-2.c: Regenerated.
 621         * aarch64-dis-2.c: Regenerated.
 622         * aarch64-opc-2.c: Regenerated.
 623
 624 2020-04-29  Nick Clifton  <nickc@redhat.com>
 625
 626         PR 22699
 627         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 628         and SETRC insns.
 629
 630 2020-04-29  Nick Clifton  <nickc@redhat.com>
 631
 632         * po/sv.po: Updated Swedish translation.
 633
 634 2020-04-29  Nick Clifton  <nickc@redhat.com>
 635
 636         PR 22699
 637         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 638         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 639         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 640         IMM0_8U case.
 641
 642 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 643
 644         PR 25848
 645         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 646         cmpi only on m68020up and cpu32.
 647
 648 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 649
 650         * aarch64-asm.c (aarch64_ins_none): New.
 651         * aarch64-asm.h (ins_none): New declaration.
 652         * aarch64-dis.c (aarch64_ext_none): New.
 653         * aarch64-dis.h (ext_none): New declaration.
 654         * aarch64-opc.c (aarch64_print_operand): Update case for
 655         AARCH64_OPND_BARRIER_PSB.
 656         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 657         (AARCH64_OPERANDS): Update inserter/extracter for
 658         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 659         * aarch64-asm-2.c: Regenerated.
 660         * aarch64-dis-2.c: Regenerated.
 661         * aarch64-opc-2.c: Regenerated.
 662
 663 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 664
 665         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 666         (aarch64_feature_ras, RAS): Likewise.
 667         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 668         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 669         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 670         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 671         * aarch64-asm-2.c: Regenerated.
 672         * aarch64-dis-2.c: Regenerated.
 673         * aarch64-opc-2.c: Regenerated.
 674
 675 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 676
 677         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 678         (print_insn_neon): Support disassembly of conditional
 679         instructions.
 680
 681 2020-02-16  David Faust  <david.faust@oracle.com>
 682
 683         * bpf-desc.c: Regenerate.
 684         * bpf-desc.h: Likewise.
 685         * bpf-opc.c: Regenerate.
 686         * bpf-opc.h: Likewise.
 687
 688 2020-04-07  Lili Cui  <lili.cui@intel.com>
 689
 690         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 691         (prefix_table): New instructions (see prefixes above).
 692         (rm_table): Likewise
 693         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 694         CPU_ANY_TSXLDTRK_FLAGS.
 695         (cpu_flags): Add CpuTSXLDTRK.
 696         * i386-opc.h (enum): Add CpuTSXLDTRK.
 697         (i386_cpu_flags): Add cputsxldtrk.
 698         * i386-opc.tbl: Add XSUSPLDTRK insns.
 699         * i386-init.h: Regenerate.
 700         * i386-tbl.h: Likewise.
 701
 702 2020-04-02  Lili Cui  <lili.cui@intel.com>
 703
 704         * i386-dis.c (prefix_table): New instructions serialize.
 705         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 706         CPU_ANY_SERIALIZE_FLAGS.
 707         (cpu_flags): Add CpuSERIALIZE.
 708         * i386-opc.h (enum): Add CpuSERIALIZE.
 709         (i386_cpu_flags): Add cpuserialize.
 710         * i386-opc.tbl: Add SERIALIZE insns.
 711         * i386-init.h: Regenerate.
 712         * i386-tbl.h: Likewise.
 713
 714 2020-03-26  Alan Modra  <amodra@gmail.com>
 715
 716         * disassemble.h (opcodes_assert): Declare.
 717         (OPCODES_ASSERT): Define.
 718         * disassemble.c: Don't include assert.h.  Include opintl.h.
 719         (opcodes_assert): New function.
 720         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 721         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 722         calculate maxlen.  Omit insn decoding when insn length exceeds
 723         maxlen.  Exit from nibble loop when looking for E, before
 724         accessing next data byte.  Move processing of E outside loop.
 725         Replace tests of maxlen in loop with assertions.
 726
 727 2020-03-26  Alan Modra  <amodra@gmail.com>
 728
 729         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 730
 731 2020-03-25  Alan Modra  <amodra@gmail.com>
 732
 733         * z80-dis.c (suffix): Init mybuf.
 734
 735 2020-03-22  Alan Modra  <amodra@gmail.com>
 736
 737         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 738         successflly read from section.
 739
 740 2020-03-22  Alan Modra  <amodra@gmail.com>
 741
 742         * arc-dis.c (find_format): Use ISO C string concatenation rather
 743         than line continuation within a string.  Don't access needs_limm
 744         before testing opcode != NULL.
 745
 746 2020-03-22  Alan Modra  <amodra@gmail.com>
 747
 748         * ns32k-dis.c (print_insn_arg): Update comment.
 749         (print_insn_ns32k): Reduce size of index_offset array, and
 750         initialize, passing -1 to print_insn_arg for args that are not
 751         an index.  Don't exit arg loop early.  Abort on bad arg number.
 752
 753 2020-03-22  Alan Modra  <amodra@gmail.com>
 754
 755         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 756         * s12z-opc.c: Formatting.
 757         (operands_f): Return an int.
 758         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 759         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 760         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 761         (exg_sex_discrim): Likewise.
 762         (create_immediate_operand, create_bitfield_operand),
 763         (create_register_operand_with_size, create_register_all_operand),
 764         (create_register_all16_operand, create_simple_memory_operand),
 765         (create_memory_operand, create_memory_auto_operand): Don't
 766         segfault on malloc failure.
 767         (z_ext24_decode): Return an int status, negative on fail, zero
 768         on success.
 769         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 770         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 771         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 772         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 773         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 774         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 775         (loop_primitive_decode, shift_decode, psh_pul_decode),
 776         (bit_field_decode): Similarly.
 777         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 778         to return value, update callers.
 779         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 780         Don't segfault on NULL operand.
 781         (decode_operation): Return OP_INVALID on first fail.
 782         (decode_s12z): Check all reads, returning -1 on fail.
 783
 784 2020-03-20  Alan Modra  <amodra@gmail.com>
 785
 786         * metag-dis.c (print_insn_metag): Don't ignore status from
 787         read_memory_func.
 788
 789 2020-03-20  Alan Modra  <amodra@gmail.com>
 790
 791         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 792         Initialize parts of buffer not written when handling a possible
 793         2-byte insn at end of section.  Don't attempt decoding of such
 794         an insn by the 4-byte machinery.
 795
 796 2020-03-20  Alan Modra  <amodra@gmail.com>
 797
 798         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 799         partially filled buffer.  Prevent lookup of 4-byte insns when
 800         only VLE 2-byte insns are possible due to section size.  Print
 801         ".word" rather than ".long" for 2-byte leftovers.
 802
 803 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 804
 805         PR 25641
 806         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 807
 808 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-dis.c (X86_64_0D): Rename to ...
 811         (X86_64_0E): ... this.
 812
 813 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 816         * Makefile.in: Regenerated.
 817
 818 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 821         3-operand pseudos.
 822         * i386-tbl.h: Re-generate.
 823
 824 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 827         vprot*, vpsha*, and vpshl*.
 828         * i386-tbl.h: Re-generate.
 829
 830 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 833         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 834         * i386-tbl.h: Re-generate.
 835
 836 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 839         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 840         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 841         * i386-tbl.h: Re-generate.
 842
 843 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-gen.c (struct template_arg, struct template_instance,
 846         struct template_param, struct template, templates,
 847         parse_template, expand_templates): New.
 848         (process_i386_opcodes): Various local variables moved to
 849         expand_templates. Call parse_template and expand_templates.
 850         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 851         * i386-tbl.h: Re-generate.
 852
 853 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 856         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 857         register and memory source templates. Replace VexW= by VexW*
 858         where applicable.
 859         * i386-tbl.h: Re-generate.
 860
 861 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 864         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 865         * i386-tbl.h: Re-generate.
 866
 867 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 870         * i386-tbl.h: Re-generate.
 871
 872 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 875         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 876         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 877         VexW0 on SSE2AVX variants.
 878         (vmovq): Drop NoRex64 from XMM/XMM variants.
 879         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 880         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 881         applicable use VexW0.
 882         * i386-tbl.h: Re-generate.
 883
 884 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 885
 886         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 887         * i386-opc.h (Rex64): Delete.
 888         (struct i386_opcode_modifier): Remove rex64 field.
 889         * i386-opc.tbl (crc32): Drop Rex64.
 890         Replace Rex64 with Size64 everywhere else.
 891         * i386-tbl.h: Re-generate.
 892
 893 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-dis.c (OP_E_memory): Exclude recording of used address
 896         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 897         addressed memory operands for MPX insns.
 898
 899 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 902         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 903         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 904         (ptwrite): Split into non-64-bit and 64-bit forms.
 905         * i386-tbl.h: Re-generate.
 906
 907 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 910         template.
 911         * i386-tbl.h: Re-generate.
 912
 913 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 916         (prefix_table): Move vmmcall here. Add vmgexit.
 917         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 918         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 919         (cpu_flags): Add CpuSEV_ES entry.
 920         * i386-opc.h (CpuSEV_ES): New.
 921         (union i386_cpu_flags): Add cpusev_es field.
 922         * i386-opc.tbl (vmgexit): New.
 923         * i386-init.h, i386-tbl.h: Re-generate.
 924
 925 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 926
 927         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 928         with MnemonicSize.
 929         * i386-opc.h (IGNORESIZE): New.
 930         (DEFAULTSIZE): Likewise.
 931         (IgnoreSize): Removed.
 932         (DefaultSize): Likewise.
 933         (MnemonicSize): New.
 934         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 935         mnemonicsize.
 936         * i386-opc.tbl (IgnoreSize): New.
 937         (DefaultSize): Likewise.
 938         * i386-tbl.h: Regenerated.
 939
 940 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 941
 942         PR 25627
 943         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 944         instructions.
 945
 946 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 947
 948         PR gas/25622
 949         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 950         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 951         * i386-tbl.h: Regenerated.
 952
 953 2020-02-26  Alan Modra  <amodra@gmail.com>
 954
 955         * aarch64-asm.c: Indent labels correctly.
 956         * aarch64-dis.c: Likewise.
 957         * aarch64-gen.c: Likewise.
 958         * aarch64-opc.c: Likewise.
 959         * alpha-dis.c: Likewise.
 960         * i386-dis.c: Likewise.
 961         * nds32-asm.c: Likewise.
 962         * nfp-dis.c: Likewise.
 963         * visium-dis.c: Likewise.
 964
 965 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 966
 967         * arc-regs.h (int_vector_base): Make it available for all ARC
 968         CPUs.
 969
 970 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 971
 972         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 973         changed.
 974
 975 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 976
 977         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 978         c.mv/c.li if rs1 is zero.
 979
 980 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 981
 982         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 983         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 984         CPU_POPCNT_FLAGS.
 985         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 986         * i386-opc.h (CpuABM): Removed.
 987         (CpuPOPCNT): New.
 988         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 989         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 990         popcnt.  Remove CpuABM from lzcnt.
 991         * i386-init.h: Regenerated.
 992         * i386-tbl.h: Likewise.
 993
 994 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 997         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 998         VexW1 instead of open-coding them.
 999         * i386-tbl.h: Re-generate.
1000
1001 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-opc.tbl (AddrPrefixOpReg): Define.
1004         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1005         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1006         templates. Drop NoRex64.
1007         * i386-tbl.h: Re-generate.
1008
1009 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1010
1011         PR gas/6518
1012         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1013         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1014         into Intel syntax instance (with Unpsecified) and AT&T one
1015         (without).
1016         (vcvtneps2bf16): Likewise, along with folding the two so far
1017         separate ones.
1018         * i386-tbl.h: Re-generate.
1019
1020 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1021
1022         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1023         CPU_ANY_SSE4A_FLAGS.
1024
1025 2020-02-17  Alan Modra  <amodra@gmail.com>
1026
1027         * i386-gen.c (cpu_flag_init): Correct last change.
1028
1029 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1030
1031         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1032         CPU_ANY_SSE4_FLAGS.
1033
1034 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1035
1036         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1037         (movzx): Likewise.
1038
1039 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1040
1041         PR gas/25438
1042         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1043         destination for Cpu64-only variant.
1044         (movzx): Fold patterns.
1045         * i386-tbl.h: Re-generate.
1046
1047 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1050         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1051         CPU_ANY_SSE4_FLAGS entry.
1052         * i386-init.h: Re-generate.
1053
1054 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1057         with Unspecified, making the present one AT&T syntax only.
1058         * i386-tbl.h: Re-generate.
1059
1060 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1061
1062         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1063         * i386-tbl.h: Re-generate.
1064
1065 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1066
1067         PR gas/24546
1068         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1069         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1070         Amd64 and Intel64 templates.
1071         (call, jmp): Likewise for far indirect variants. Dro
1072         Unspecified.
1073         * i386-tbl.h: Re-generate.
1074
1075 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1076
1077         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1078         * i386-opc.h (ShortForm): Delete.
1079         (struct i386_opcode_modifier): Remove shortform field.
1080         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1081         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1082         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1083         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1084         Drop ShortForm.
1085         * i386-tbl.h: Re-generate.
1086
1087 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1090         fucompi): Drop ShortForm from operand-less templates.
1091         * i386-tbl.h: Re-generate.
1092
1093 2020-02-11  Alan Modra  <amodra@gmail.com>
1094
1095         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1096         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1097         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1098         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1099         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1100
1101 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1102
1103         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1104         (cde_opcodes): Add VCX* instructions.
1105
1106 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1107             Matthew Malcomson  <matthew.malcomson@arm.com>
1108
1109         * arm-dis.c (struct cdeopcode32): New.
1110         (CDE_OPCODE): New macro.
1111         (cde_opcodes): New disassembly table.
1112         (regnames): New option to table.
1113         (cde_coprocs): New global variable.
1114         (print_insn_cde): New
1115         (print_insn_thumb32): Use print_insn_cde.
1116         (parse_arm_disassembler_options): Parse coprocN args.
1117
1118 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1119
1120         PR gas/25516
1121         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1122         with ISA64.
1123         * i386-opc.h (AMD64): Removed.
1124         (Intel64): Likewose.
1125         (AMD64): New.
1126         (INTEL64): Likewise.
1127         (INTEL64ONLY): Likewise.
1128         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1129         * i386-opc.tbl (Amd64): New.
1130         (Intel64): Likewise.
1131         (Intel64Only): Likewise.
1132         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1133         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1134         * i386-tbl.h: Regenerated.
1135
1136 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1137
1138         PR 25469
1139         * z80-dis.c: Add support for GBZ80 opcodes.
1140
1141 2020-02-04  Alan Modra  <amodra@gmail.com>
1142
1143         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1144
1145 2020-02-03  Alan Modra  <amodra@gmail.com>
1146
1147         * m32c-ibld.c: Regenerate.
1148
1149 2020-02-01  Alan Modra  <amodra@gmail.com>
1150
1151         * frv-ibld.c: Regenerate.
1152
1153 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1154
1155         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1156         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1157         (OP_E_memory): Replace xmm_mdq_mode case label by
1158         vex_scalar_w_dq_mode one.
1159         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1160
1161 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1164         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1165         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1166         (intel_operand_size): Drop vex_w_dq_mode case label.
1167
1168 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1169
1170         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1171         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1172
1173 2020-01-30  Alan Modra  <amodra@gmail.com>
1174
1175         * m32c-ibld.c: Regenerate.
1176
1177 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1178
1179         * bpf-opc.c: Regenerate.
1180
1181 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1184         (dis386): Use them to replace C2/C3 table entries.
1185         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1186         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1187         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1188         * i386-tbl.h: Re-generate.
1189
1190 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1191
1192         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1193         forms.
1194         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1195         DefaultSize.
1196         * i386-tbl.h: Re-generate.
1197
1198 2020-01-30  Alan Modra  <amodra@gmail.com>
1199
1200         * tic4x-dis.c (tic4x_dp): Make unsigned.
1201
1202 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1203             Jan Beulich  <jbeulich@suse.com>
1204
1205         PR binutils/25445
1206         * i386-dis.c (MOVSXD_Fixup): New function.
1207         (movsxd_mode): New enum.
1208         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1209         (intel_operand_size): Handle movsxd_mode.
1210         (OP_E_register): Likewise.
1211         (OP_G): Likewise.
1212         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1213         register on movsxd.  Add movsxd with 16-bit destination register
1214         for AMD64 and Intel64 ISAs.
1215         * i386-tbl.h: Regenerated.
1216
1217 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1218
1219         PR 25403
1220         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1221         * aarch64-asm-2.c: Regenerate
1222         * aarch64-dis-2.c: Likewise.
1223         * aarch64-opc-2.c: Likewise.
1224
1225 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1226
1227         * i386-opc.tbl (sysret): Drop DefaultSize.
1228         * i386-tbl.h: Re-generate.
1229
1230 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1231
1232         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1233         Dword.
1234         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1235         * i386-tbl.h: Re-generate.
1236
1237 2020-01-20  Nick Clifton  <nickc@redhat.com>
1238
1239         * po/de.po: Updated German translation.
1240         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1241         * po/uk.po: Updated Ukranian translation.
1242
1243 2020-01-20  Alan Modra  <amodra@gmail.com>
1244
1245         * hppa-dis.c (fput_const): Remove useless cast.
1246
1247 2020-01-20  Alan Modra  <amodra@gmail.com>
1248
1249         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1250
1251 2020-01-18  Nick Clifton  <nickc@redhat.com>
1252
1253         * configure: Regenerate.
1254         * po/opcodes.pot: Regenerate.
1255
1256 2020-01-18  Nick Clifton  <nickc@redhat.com>
1257
1258         Binutils 2.34 branch created.
1259
1260 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1261
1262         * opintl.h: Fix spelling error (seperate).
1263
1264 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1265
1266         * i386-opc.tbl: Add {vex} pseudo prefix.
1267         * i386-tbl.h: Regenerated.
1268
1269 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1270
1271         PR 25376
1272         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1273         (neon_opcodes): Likewise.
1274         (select_arm_features): Make sure we enable MVE bits when selecting
1275         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1276         any architecture.
1277
1278 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-opc.tbl: Drop stale comment from XOP section.
1281
1282 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1283
1284         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1285         (extractps): Add VexWIG to SSE2AVX forms.
1286         * i386-tbl.h: Re-generate.
1287
1288 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1289
1290         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1291         Size64 from and use VexW1 on SSE2AVX forms.
1292         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1293         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1294         * i386-tbl.h: Re-generate.
1295
1296 2020-01-15  Alan Modra  <amodra@gmail.com>
1297
1298         * tic4x-dis.c (tic4x_version): Make unsigned long.
1299         (optab, optab_special, registernames): New file scope vars.
1300         (tic4x_print_register): Set up registernames rather than
1301         malloc'd registertable.
1302         (tic4x_disassemble): Delete optable and optable_special.  Use
1303         optab and optab_special instead.  Throw away old optab,
1304         optab_special and registernames when info->mach changes.
1305
1306 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1307
1308         PR 25377
1309         * z80-dis.c (suffix): Use .db instruction to generate double
1310         prefix.
1311
1312 2020-01-14  Alan Modra  <amodra@gmail.com>
1313
1314         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1315         values to unsigned before shifting.
1316
1317 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1318
1319         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1320         flow instructions.
1321         (print_insn_thumb16, print_insn_thumb32): Likewise.
1322         (print_insn): Initialize the insn info.
1323         * i386-dis.c (print_insn): Initialize the insn info fields, and
1324         detect jumps.
1325
1326 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1327
1328         * arc-opc.c (C_NE): Make it required.
1329
1330 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1331
1332         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1333         reserved register name.
1334
1335 2020-01-13  Alan Modra  <amodra@gmail.com>
1336
1337         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1338         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1339
1340 2020-01-13  Alan Modra  <amodra@gmail.com>
1341
1342         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1343         result of wasm_read_leb128 in a uint64_t and check that bits
1344         are not lost when copying to other locals.  Use uint32_t for
1345         most locals.  Use PRId64 when printing int64_t.
1346
1347 2020-01-13  Alan Modra  <amodra@gmail.com>
1348
1349         * score-dis.c: Formatting.
1350         * score7-dis.c: Formatting.
1351
1352 2020-01-13  Alan Modra  <amodra@gmail.com>
1353
1354         * score-dis.c (print_insn_score48): Use unsigned variables for
1355         unsigned values.  Don't left shift negative values.
1356         (print_insn_score32): Likewise.
1357         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1358
1359 2020-01-13  Alan Modra  <amodra@gmail.com>
1360
1361         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1362
1363 2020-01-13  Alan Modra  <amodra@gmail.com>
1364
1365         * fr30-ibld.c: Regenerate.
1366
1367 2020-01-13  Alan Modra  <amodra@gmail.com>
1368
1369         * xgate-dis.c (print_insn): Don't left shift signed value.
1370         (ripBits): Formatting, use 1u.
1371
1372 2020-01-10  Alan Modra  <amodra@gmail.com>
1373
1374         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1375         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1376
1377 2020-01-10  Alan Modra  <amodra@gmail.com>
1378
1379         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1380         and XRREG value earlier to avoid a shift with negative exponent.
1381         * m10200-dis.c (disassemble): Similarly.
1382
1383 2020-01-09  Nick Clifton  <nickc@redhat.com>
1384
1385         PR 25224
1386         * z80-dis.c (ld_ii_ii): Use correct cast.
1387
1388 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1389
1390         PR 25224
1391         * z80-dis.c (ld_ii_ii): Use character constant when checking
1392         opcode byte value.
1393
1394 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1395
1396         * i386-dis.c (SEP_Fixup): New.
1397         (SEP): Define.
1398         (dis386_twobyte): Use it for sysenter/sysexit.
1399         (enum x86_64_isa): Change amd64 enumerator to value 1.
1400         (OP_J): Compare isa64 against intel64 instead of amd64.
1401         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1402         forms.
1403         * i386-tbl.h: Re-generate.
1404
1405 2020-01-08  Alan Modra  <amodra@gmail.com>
1406
1407         * z8k-dis.c: Include libiberty.h
1408         (instr_data_s): Make max_fetched unsigned.
1409         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1410         Don't exceed byte_info bounds.
1411         (output_instr): Make num_bytes unsigned.
1412         (unpack_instr): Likewise for nibl_count and loop.
1413         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1414         idx unsigned.
1415         * z8k-opc.h: Regenerate.
1416
1417 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1418
1419         * arc-tbl.h (llock): Use 'LLOCK' as class.
1420         (llockd): Likewise.
1421         (scond): Use 'SCOND' as class.
1422         (scondd): Likewise.
1423         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1424         (scondd): Likewise.
1425
1426 2020-01-06  Alan Modra  <amodra@gmail.com>
1427
1428         * m32c-ibld.c: Regenerate.
1429
1430 2020-01-06  Alan Modra  <amodra@gmail.com>
1431
1432         PR 25344
1433         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1434         Peek at next byte to prevent recursion on repeated prefix bytes.
1435         Ensure uninitialised "mybuf" is not accessed.
1436         (print_insn_z80): Don't zero n_fetch and n_used here,..
1437         (print_insn_z80_buf): ..do it here instead.
1438
1439 2020-01-04  Alan Modra  <amodra@gmail.com>
1440
1441         * m32r-ibld.c: Regenerate.
1442
1443 2020-01-04  Alan Modra  <amodra@gmail.com>
1444
1445         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1446
1447 2020-01-04  Alan Modra  <amodra@gmail.com>
1448
1449         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1450
1451 2020-01-04  Alan Modra  <amodra@gmail.com>
1452
1453         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1454
1455 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1456
1457         * aarch64-tbl.h (aarch64_opcode_table): Use
1458         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1459
1460 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1461
1462         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1463         forms of SUDOT and USDOT.
1464
1465 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1466
1467         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1468         uzip{1,2}.
1469         * opcodes/aarch64-dis-2.c: Re-generate.
1470
1471 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1472
1473         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1474         FMMLA encoding.
1475         * opcodes/aarch64-dis-2.c: Re-generate.
1476
1477 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1478
1479         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1480
1481 2020-01-01  Alan Modra  <amodra@gmail.com>
1482
1483         Update year range in copyright notice of all files.
1484
1485 For older changes see ChangeLog-2019
1486 \f
1487 Copyright (C) 2020 Free Software Foundation, Inc.
1488
1489 Copying and distribution of this file, with or without modification,
1490 are permitted in any medium without royalty provided the copyright
1491 notice and this notice are preserved.
1492
1493 Local Variables:
1494 mode: change-log
1495 left-margin: 8
1496 fill-column: 74
1497 version-control: never
1498 End: