opcodes/ChangeLog

   1 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
   2
   3         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
   4         c.mv/c.li if rs1 is zero.
   5
   6 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-gen.c (cpu_flag_init): Replace CpuABM with
   9         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  10         CPU_POPCNT_FLAGS.
  11         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  12         * i386-opc.h (CpuABM): Removed.
  13         (CpuPOPCNT): New.
  14         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  15         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  16         popcnt.  Remove CpuABM from lzcnt.
  17         * i386-init.h: Regenerated.
  18         * i386-tbl.h: Likewise.
  19
  20 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  23         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  24         VexW1 instead of open-coding them.
  25         * i386-tbl.h: Re-generate.
  26
  27 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-opc.tbl (AddrPrefixOpReg): Define.
  30         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  31         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  32         templates. Drop NoRex64.
  33         * i386-tbl.h: Re-generate.
  34
  35 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  36
  37         PR gas/6518
  38         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  39         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  40         into Intel syntax instance (with Unpsecified) and AT&T one
  41         (without).
  42         (vcvtneps2bf16): Likewise, along with folding the two so far
  43         separate ones.
  44         * i386-tbl.h: Re-generate.
  45
  46 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  49         CPU_ANY_SSE4A_FLAGS.
  50
  51 2020-02-17  Alan Modra  <amodra@gmail.com>
  52
  53         * i386-gen.c (cpu_flag_init): Correct last change.
  54
  55 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  58         CPU_ANY_SSE4_FLAGS.
  59
  60 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  63         (movzx): Likewise.
  64
  65 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  66
  67         PR gas/25438
  68         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  69         destination for Cpu64-only variant.
  70         (movzx): Fold patterns.
  71         * i386-tbl.h: Re-generate.
  72
  73 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  76         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  77         CPU_ANY_SSE4_FLAGS entry.
  78         * i386-init.h: Re-generate.
  79
  80 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  81
  82         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  83         with Unspecified, making the present one AT&T syntax only.
  84         * i386-tbl.h: Re-generate.
  85
  86 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  89         * i386-tbl.h: Re-generate.
  90
  91 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  92
  93         PR gas/24546
  94         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  95         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  96         Amd64 and Intel64 templates.
  97         (call, jmp): Likewise for far indirect variants. Dro
  98         Unspecified.
  99         * i386-tbl.h: Re-generate.
 100
 101 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 104         * i386-opc.h (ShortForm): Delete.
 105         (struct i386_opcode_modifier): Remove shortform field.
 106         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 107         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 108         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 109         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 110         Drop ShortForm.
 111         * i386-tbl.h: Re-generate.
 112
 113 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 116         fucompi): Drop ShortForm from operand-less templates.
 117         * i386-tbl.h: Re-generate.
 118
 119 2020-02-11  Alan Modra  <amodra@gmail.com>
 120
 121         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 122         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 123         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 124         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 125         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 126
 127 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 128
 129         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 130         (cde_opcodes): Add VCX* instructions.
 131
 132 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 133             Matthew Malcomson  <matthew.malcomson@arm.com>
 134
 135         * arm-dis.c (struct cdeopcode32): New.
 136         (CDE_OPCODE): New macro.
 137         (cde_opcodes): New disassembly table.
 138         (regnames): New option to table.
 139         (cde_coprocs): New global variable.
 140         (print_insn_cde): New
 141         (print_insn_thumb32): Use print_insn_cde.
 142         (parse_arm_disassembler_options): Parse coprocN args.
 143
 144 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         PR gas/25516
 147         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 148         with ISA64.
 149         * i386-opc.h (AMD64): Removed.
 150         (Intel64): Likewose.
 151         (AMD64): New.
 152         (INTEL64): Likewise.
 153         (INTEL64ONLY): Likewise.
 154         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 155         * i386-opc.tbl (Amd64): New.
 156         (Intel64): Likewise.
 157         (Intel64Only): Likewise.
 158         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 159         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 160         * i386-tbl.h: Regenerated.
 161
 162 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 163
 164         PR 25469
 165         * z80-dis.c: Add support for GBZ80 opcodes.
 166
 167 2020-02-04  Alan Modra  <amodra@gmail.com>
 168
 169         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 170
 171 2020-02-03  Alan Modra  <amodra@gmail.com>
 172
 173         * m32c-ibld.c: Regenerate.
 174
 175 2020-02-01  Alan Modra  <amodra@gmail.com>
 176
 177         * frv-ibld.c: Regenerate.
 178
 179 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 182         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 183         (OP_E_memory): Replace xmm_mdq_mode case label by
 184         vex_scalar_w_dq_mode one.
 185         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 186
 187 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 190         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 191         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 192         (intel_operand_size): Drop vex_w_dq_mode case label.
 193
 194 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 195
 196         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 197         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 198
 199 2020-01-30  Alan Modra  <amodra@gmail.com>
 200
 201         * m32c-ibld.c: Regenerate.
 202
 203 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 204
 205         * bpf-opc.c: Regenerate.
 206
 207 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 210         (dis386): Use them to replace C2/C3 table entries.
 211         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 212         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 213         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 214         * i386-tbl.h: Re-generate.
 215
 216 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 219         forms.
 220         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 221         DefaultSize.
 222         * i386-tbl.h: Re-generate.
 223
 224 2020-01-30  Alan Modra  <amodra@gmail.com>
 225
 226         * tic4x-dis.c (tic4x_dp): Make unsigned.
 227
 228 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 229             Jan Beulich  <jbeulich@suse.com>
 230
 231         PR binutils/25445
 232         * i386-dis.c (MOVSXD_Fixup): New function.
 233         (movsxd_mode): New enum.
 234         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 235         (intel_operand_size): Handle movsxd_mode.
 236         (OP_E_register): Likewise.
 237         (OP_G): Likewise.
 238         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 239         register on movsxd.  Add movsxd with 16-bit destination register
 240         for AMD64 and Intel64 ISAs.
 241         * i386-tbl.h: Regenerated.
 242
 243 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 244
 245         PR 25403
 246         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 247         * aarch64-asm-2.c: Regenerate
 248         * aarch64-dis-2.c: Likewise.
 249         * aarch64-opc-2.c: Likewise.
 250
 251 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (sysret): Drop DefaultSize.
 254         * i386-tbl.h: Re-generate.
 255
 256 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 259         Dword.
 260         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 261         * i386-tbl.h: Re-generate.
 262
 263 2020-01-20  Nick Clifton  <nickc@redhat.com>
 264
 265         * po/de.po: Updated German translation.
 266         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 267         * po/uk.po: Updated Ukranian translation.
 268
 269 2020-01-20  Alan Modra  <amodra@gmail.com>
 270
 271         * hppa-dis.c (fput_const): Remove useless cast.
 272
 273 2020-01-20  Alan Modra  <amodra@gmail.com>
 274
 275         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 276
 277 2020-01-18  Nick Clifton  <nickc@redhat.com>
 278
 279         * configure: Regenerate.
 280         * po/opcodes.pot: Regenerate.
 281
 282 2020-01-18  Nick Clifton  <nickc@redhat.com>
 283
 284         Binutils 2.34 branch created.
 285
 286 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 287
 288         * opintl.h: Fix spelling error (seperate).
 289
 290 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386-opc.tbl: Add {vex} pseudo prefix.
 293         * i386-tbl.h: Regenerated.
 294
 295 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 296
 297         PR 25376
 298         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 299         (neon_opcodes): Likewise.
 300         (select_arm_features): Make sure we enable MVE bits when selecting
 301         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 302         any architecture.
 303
 304 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-opc.tbl: Drop stale comment from XOP section.
 307
 308 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 311         (extractps): Add VexWIG to SSE2AVX forms.
 312         * i386-tbl.h: Re-generate.
 313
 314 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 317         Size64 from and use VexW1 on SSE2AVX forms.
 318         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 319         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 320         * i386-tbl.h: Re-generate.
 321
 322 2020-01-15  Alan Modra  <amodra@gmail.com>
 323
 324         * tic4x-dis.c (tic4x_version): Make unsigned long.
 325         (optab, optab_special, registernames): New file scope vars.
 326         (tic4x_print_register): Set up registernames rather than
 327         malloc'd registertable.
 328         (tic4x_disassemble): Delete optable and optable_special.  Use
 329         optab and optab_special instead.  Throw away old optab,
 330         optab_special and registernames when info->mach changes.
 331
 332 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 333
 334         PR 25377
 335         * z80-dis.c (suffix): Use .db instruction to generate double
 336         prefix.
 337
 338 2020-01-14  Alan Modra  <amodra@gmail.com>
 339
 340         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 341         values to unsigned before shifting.
 342
 343 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 344
 345         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 346         flow instructions.
 347         (print_insn_thumb16, print_insn_thumb32): Likewise.
 348         (print_insn): Initialize the insn info.
 349         * i386-dis.c (print_insn): Initialize the insn info fields, and
 350         detect jumps.
 351
 352 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 353
 354         * arc-opc.c (C_NE): Make it required.
 355
 356 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 357
 358         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 359         reserved register name.
 360
 361 2020-01-13  Alan Modra  <amodra@gmail.com>
 362
 363         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 364         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 365
 366 2020-01-13  Alan Modra  <amodra@gmail.com>
 367
 368         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 369         result of wasm_read_leb128 in a uint64_t and check that bits
 370         are not lost when copying to other locals.  Use uint32_t for
 371         most locals.  Use PRId64 when printing int64_t.
 372
 373 2020-01-13  Alan Modra  <amodra@gmail.com>
 374
 375         * score-dis.c: Formatting.
 376         * score7-dis.c: Formatting.
 377
 378 2020-01-13  Alan Modra  <amodra@gmail.com>
 379
 380         * score-dis.c (print_insn_score48): Use unsigned variables for
 381         unsigned values.  Don't left shift negative values.
 382         (print_insn_score32): Likewise.
 383         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 384
 385 2020-01-13  Alan Modra  <amodra@gmail.com>
 386
 387         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 388
 389 2020-01-13  Alan Modra  <amodra@gmail.com>
 390
 391         * fr30-ibld.c: Regenerate.
 392
 393 2020-01-13  Alan Modra  <amodra@gmail.com>
 394
 395         * xgate-dis.c (print_insn): Don't left shift signed value.
 396         (ripBits): Formatting, use 1u.
 397
 398 2020-01-10  Alan Modra  <amodra@gmail.com>
 399
 400         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 401         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 402
 403 2020-01-10  Alan Modra  <amodra@gmail.com>
 404
 405         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 406         and XRREG value earlier to avoid a shift with negative exponent.
 407         * m10200-dis.c (disassemble): Similarly.
 408
 409 2020-01-09  Nick Clifton  <nickc@redhat.com>
 410
 411         PR 25224
 412         * z80-dis.c (ld_ii_ii): Use correct cast.
 413
 414 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 415
 416         PR 25224
 417         * z80-dis.c (ld_ii_ii): Use character constant when checking
 418         opcode byte value.
 419
 420 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-dis.c (SEP_Fixup): New.
 423         (SEP): Define.
 424         (dis386_twobyte): Use it for sysenter/sysexit.
 425         (enum x86_64_isa): Change amd64 enumerator to value 1.
 426         (OP_J): Compare isa64 against intel64 instead of amd64.
 427         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 428         forms.
 429         * i386-tbl.h: Re-generate.
 430
 431 2020-01-08  Alan Modra  <amodra@gmail.com>
 432
 433         * z8k-dis.c: Include libiberty.h
 434         (instr_data_s): Make max_fetched unsigned.
 435         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 436         Don't exceed byte_info bounds.
 437         (output_instr): Make num_bytes unsigned.
 438         (unpack_instr): Likewise for nibl_count and loop.
 439         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 440         idx unsigned.
 441         * z8k-opc.h: Regenerate.
 442
 443 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 444
 445         * arc-tbl.h (llock): Use 'LLOCK' as class.
 446         (llockd): Likewise.
 447         (scond): Use 'SCOND' as class.
 448         (scondd): Likewise.
 449         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 450         (scondd): Likewise.
 451
 452 2020-01-06  Alan Modra  <amodra@gmail.com>
 453
 454         * m32c-ibld.c: Regenerate.
 455
 456 2020-01-06  Alan Modra  <amodra@gmail.com>
 457
 458         PR 25344
 459         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 460         Peek at next byte to prevent recursion on repeated prefix bytes.
 461         Ensure uninitialised "mybuf" is not accessed.
 462         (print_insn_z80): Don't zero n_fetch and n_used here,..
 463         (print_insn_z80_buf): ..do it here instead.
 464
 465 2020-01-04  Alan Modra  <amodra@gmail.com>
 466
 467         * m32r-ibld.c: Regenerate.
 468
 469 2020-01-04  Alan Modra  <amodra@gmail.com>
 470
 471         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 472
 473 2020-01-04  Alan Modra  <amodra@gmail.com>
 474
 475         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 476
 477 2020-01-04  Alan Modra  <amodra@gmail.com>
 478
 479         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 480
 481 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 482
 483         * aarch64-tbl.h (aarch64_opcode_table): Use
 484         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 485
 486 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 487
 488         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 489         forms of SUDOT and USDOT.
 490
 491 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 492
 493         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 494         uzip{1,2}.
 495         * opcodes/aarch64-dis-2.c: Re-generate.
 496
 497 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 498
 499         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 500         FMMLA encoding.
 501         * opcodes/aarch64-dis-2.c: Re-generate.
 502
 503 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 504
 505         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 506
 507 2020-01-01  Alan Modra  <amodra@gmail.com>
 508
 509         Update year range in copyright notice of all files.
 510
 511 For older changes see ChangeLog-2019
 512 \f
 513 Copyright (C) 2020 Free Software Foundation, Inc.
 514
 515 Copying and distribution of this file, with or without modification,
 516 are permitted in any medium without royalty provided the copyright
 517 notice and this notice are preserved.
 518
 519 Local Variables:
 520 mode: change-log
 521 left-margin: 8
 522 fill-column: 74
 523 version-control: never
 524 End: