opcodes/ChangeLog

   1 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
   4         AARCH64_OPND_SYSREG_SR.
   5         * aarch64-opc.c (aarch64_print_operand): Likewise.
   6         (aarch64_sys_regs_sr): Define table.
   7         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
   8         AARCH64_FEATURE_PREDRES.
   9         * aarch64-tbl.h (aarch64_feature_predres): New.
  10         (PREDRES, PREDRES_INSN): New.
  11         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
  12         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
  13         * aarch64-asm-2.c: Regenerate.
  14         * aarch64-dis-2.c: Regenerate.
  15         * aarch64-opc-2.c: Regenerate.
  16
  17 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  18
  19         * aarch64-tbl.h (aarch64_feature_sb): New.
  20         (SB, SB_INSN): New.
  21         (aarch64_opcode_table): Add entry for sb.
  22         * aarch64-asm-2.c: Regenerate.
  23         * aarch64-dis-2.c: Regenerate.
  24         * aarch64-opc-2.c: Regenerate.
  25
  26 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  27
  28         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
  29         (aarch64_feature_frintts): New.
  30         (FLAGMANIP, FRINTTS): New.
  31         (aarch64_opcode_table): Add entries for xaflag, axflag
  32         and frint[32,64][x,z] instructions.
  33         * aarch64-asm-2.c: Regenerate.
  34         * aarch64-dis-2.c: Regenerate.
  35         * aarch64-opc-2.c: Regenerate.
  36
  37 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  38
  39         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
  40         (ARMV8_5, V8_5_INSN): New.
  41
  42 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
  43
  44         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
  45
  46 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         * i386-dis.c (rm_table): Add enclv.
  49         * i386-opc.tbl: Add enclv.
  50         * i386-tbl.h: Regenerated.
  51
  52 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
  53
  54         * arm-dis.c (arm_opcodes): Add sb.
  55         (thumb32_opcodes): Likewise.
  56
  57 2018-10-05  Richard Henderson  <rth@twiddle.net>
  58             Stafford Horne  <shorne@gmail.com>
  59
  60         * or1k-desc.c: Regenerate.
  61         * or1k-desc.h: Regenerate.
  62         * or1k-opc.c: Regenerate.
  63         * or1k-opc.h: Regenerate.
  64         * or1k-opinst.c: Regenerate.
  65
  66 2018-10-05  Richard Henderson  <rth@twiddle.net>
  67
  68         * or1k-asm.c: Regenerated.
  69         * or1k-desc.c: Regenerated.
  70         * or1k-desc.h: Regenerated.
  71         * or1k-dis.c: Regenerated.
  72         * or1k-ibld.c: Regenerated.
  73         * or1k-opc.c: Regenerated.
  74         * or1k-opc.h: Regenerated.
  75         * or1k-opinst.c: Regenerated.
  76
  77 2018-10-05  Richard Henderson  <rth@twiddle.net>
  78
  79         * or1k-asm.c: Regenerate.
  80
  81 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  82
  83         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  84         * aarch64-dis.c (print_operands): Refactor to take notes.
  85         (print_verifier_notes): New.
  86         (print_aarch64_insn): Apply constraint verifier.
  87         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  88         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
  89
  90 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  91
  92         * aarch64-opc.c (init_insn_block): New.
  93         (verify_constraints, aarch64_is_destructive_by_operands): New.
  94         * aarch64-opc.h (verify_constraints): New.
  95
  96 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  97
  98         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  99         * aarch64-opc.c (verify_ldpsw): Update arguments.
 100
 101 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 102
 103         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 104         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 105
 106 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 107
 108         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 109         * aarch64-dis.c (insn_sequence): New.
 110
 111 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 112
 113         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 114         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 115         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 116         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 117         constraints.
 118         (_SVE_INSNC): New.
 119         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 120         constraints.
 121         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 122         F_SCAN flags.
 123         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 124         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 125         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 126         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 127         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 128         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 129         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 130
 131 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 132
 133         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 134
 135 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 136
 137         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 138         are used when extracting signed fields and converting them to
 139         potentially 64-bit types.
 140
 141 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 142
 143         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 144         * Makefile.in: Re-generate.
 145         * aclocal.m4: Re-generate.
 146         * configure: Re-generate.
 147         * configure.ac: Remove check for -Wno-missing-field-initializers.
 148         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 149         (csky_v2_opcodes): Likewise.
 150
 151 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 152
 153         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 154
 155 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 156
 157         * nds32-asm.c (operand_fields): Remove the unused fields.
 158         (nds32_opcodes): Remove the unused instructions.
 159         * nds32-dis.c (nds32_ex9_info): Removed.
 160         (nds32_parse_opcode): Updated.
 161         (print_insn_nds32): Likewise.
 162         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 163         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 164         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 165         build_opcode_hash_table): New functions.
 166         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 167         nds32_opcode_table): New.
 168         (hw_ktabs): Declare it to a pointer rather than an array.
 169         (build_hash_table): Removed.
 170         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 171         SYN_ROPT and upadte HW_GPR and HW_INT.
 172         * nds32-dis.c (keywords): Remove const.
 173         (match_field): New function.
 174         (nds32_parse_opcode): Updated.
 175         * disassemble.c (disassemble_init_for_target):
 176         Add disassemble_init_nds32.
 177         * nds32-dis.c (eum map_type): New.
 178         (nds32_private_data): Likewise.
 179         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 180         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 181         (print_insn_nds32): Updated.
 182         * nds32-asm.c (parse_aext_reg): Add new parameter.
 183         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 184         are allowed to use.
 185         All callers changed.
 186         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 187         (operand_fields): Add new fields.
 188         (nds32_opcodes): Add new instructions.
 189         (keyword_aridxi_mx): New keyword.
 190         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 191         and NASM_ATTR_ZOL.
 192         (ALU2_1, ALU2_2, ALU2_3): New macros.
 193         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 194
 195 2018-09-17  Kito Cheng  <kito@andestech.com>
 196
 197         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 198
 199 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 200
 201         PR gas/23670
 202         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 203         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 204         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 205         (EVEX_LEN_0F7E_P_1): Likewise.
 206         (EVEX_LEN_0F7E_P_2): Likewise.
 207         (EVEX_LEN_0FD6_P_2): Likewise.
 208         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 209         (EVEX_LEN_TABLE): Likewise.
 210         (EVEX_LEN_0F6E_P_2): New enum.
 211         (EVEX_LEN_0F7E_P_1): Likewise.
 212         (EVEX_LEN_0F7E_P_2): Likewise.
 213         (EVEX_LEN_0FD6_P_2): Likewise.
 214         (evex_len_table): New.
 215         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 216         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 217         * i386-tbl.h: Regenerated.
 218
 219 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 220
 221         PR gas/23665
 222         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 223         VEX_LEN_0F7E_P_2 entries.
 224         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 225         * i386-tbl.h: Regenerated.
 226
 227 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 228
 229         * i386-dis.c (VZERO_Fixup): Removed.
 230         (VZERO): Likewise.
 231         (VEX_LEN_0F10_P_1): Likewise.
 232         (VEX_LEN_0F10_P_3): Likewise.
 233         (VEX_LEN_0F11_P_1): Likewise.
 234         (VEX_LEN_0F11_P_3): Likewise.
 235         (VEX_LEN_0F2E_P_0): Likewise.
 236         (VEX_LEN_0F2E_P_2): Likewise.
 237         (VEX_LEN_0F2F_P_0): Likewise.
 238         (VEX_LEN_0F2F_P_2): Likewise.
 239         (VEX_LEN_0F51_P_1): Likewise.
 240         (VEX_LEN_0F51_P_3): Likewise.
 241         (VEX_LEN_0F52_P_1): Likewise.
 242         (VEX_LEN_0F53_P_1): Likewise.
 243         (VEX_LEN_0F58_P_1): Likewise.
 244         (VEX_LEN_0F58_P_3): Likewise.
 245         (VEX_LEN_0F59_P_1): Likewise.
 246         (VEX_LEN_0F59_P_3): Likewise.
 247         (VEX_LEN_0F5A_P_1): Likewise.
 248         (VEX_LEN_0F5A_P_3): Likewise.
 249         (VEX_LEN_0F5C_P_1): Likewise.
 250         (VEX_LEN_0F5C_P_3): Likewise.
 251         (VEX_LEN_0F5D_P_1): Likewise.
 252         (VEX_LEN_0F5D_P_3): Likewise.
 253         (VEX_LEN_0F5E_P_1): Likewise.
 254         (VEX_LEN_0F5E_P_3): Likewise.
 255         (VEX_LEN_0F5F_P_1): Likewise.
 256         (VEX_LEN_0F5F_P_3): Likewise.
 257         (VEX_LEN_0FC2_P_1): Likewise.
 258         (VEX_LEN_0FC2_P_3): Likewise.
 259         (VEX_LEN_0F3A0A_P_2): Likewise.
 260         (VEX_LEN_0F3A0B_P_2): Likewise.
 261         (VEX_W_0F10_P_0): Likewise.
 262         (VEX_W_0F10_P_1): Likewise.
 263         (VEX_W_0F10_P_2): Likewise.
 264         (VEX_W_0F10_P_3): Likewise.
 265         (VEX_W_0F11_P_0): Likewise.
 266         (VEX_W_0F11_P_1): Likewise.
 267         (VEX_W_0F11_P_2): Likewise.
 268         (VEX_W_0F11_P_3): Likewise.
 269         (VEX_W_0F12_P_0_M_0): Likewise.
 270         (VEX_W_0F12_P_0_M_1): Likewise.
 271         (VEX_W_0F12_P_1): Likewise.
 272         (VEX_W_0F12_P_2): Likewise.
 273         (VEX_W_0F12_P_3): Likewise.
 274         (VEX_W_0F13_M_0): Likewise.
 275         (VEX_W_0F14): Likewise.
 276         (VEX_W_0F15): Likewise.
 277         (VEX_W_0F16_P_0_M_0): Likewise.
 278         (VEX_W_0F16_P_0_M_1): Likewise.
 279         (VEX_W_0F16_P_1): Likewise.
 280         (VEX_W_0F16_P_2): Likewise.
 281         (VEX_W_0F17_M_0): Likewise.
 282         (VEX_W_0F28): Likewise.
 283         (VEX_W_0F29): Likewise.
 284         (VEX_W_0F2B_M_0): Likewise.
 285         (VEX_W_0F2E_P_0): Likewise.
 286         (VEX_W_0F2E_P_2): Likewise.
 287         (VEX_W_0F2F_P_0): Likewise.
 288         (VEX_W_0F2F_P_2): Likewise.
 289         (VEX_W_0F50_M_0): Likewise.
 290         (VEX_W_0F51_P_0): Likewise.
 291         (VEX_W_0F51_P_1): Likewise.
 292         (VEX_W_0F51_P_2): Likewise.
 293         (VEX_W_0F51_P_3): Likewise.
 294         (VEX_W_0F52_P_0): Likewise.
 295         (VEX_W_0F52_P_1): Likewise.
 296         (VEX_W_0F53_P_0): Likewise.
 297         (VEX_W_0F53_P_1): Likewise.
 298         (VEX_W_0F58_P_0): Likewise.
 299         (VEX_W_0F58_P_1): Likewise.
 300         (VEX_W_0F58_P_2): Likewise.
 301         (VEX_W_0F58_P_3): Likewise.
 302         (VEX_W_0F59_P_0): Likewise.
 303         (VEX_W_0F59_P_1): Likewise.
 304         (VEX_W_0F59_P_2): Likewise.
 305         (VEX_W_0F59_P_3): Likewise.
 306         (VEX_W_0F5A_P_0): Likewise.
 307         (VEX_W_0F5A_P_1): Likewise.
 308         (VEX_W_0F5A_P_3): Likewise.
 309         (VEX_W_0F5B_P_0): Likewise.
 310         (VEX_W_0F5B_P_1): Likewise.
 311         (VEX_W_0F5B_P_2): Likewise.
 312         (VEX_W_0F5C_P_0): Likewise.
 313         (VEX_W_0F5C_P_1): Likewise.
 314         (VEX_W_0F5C_P_2): Likewise.
 315         (VEX_W_0F5C_P_3): Likewise.
 316         (VEX_W_0F5D_P_0): Likewise.
 317         (VEX_W_0F5D_P_1): Likewise.
 318         (VEX_W_0F5D_P_2): Likewise.
 319         (VEX_W_0F5D_P_3): Likewise.
 320         (VEX_W_0F5E_P_0): Likewise.
 321         (VEX_W_0F5E_P_1): Likewise.
 322         (VEX_W_0F5E_P_2): Likewise.
 323         (VEX_W_0F5E_P_3): Likewise.
 324         (VEX_W_0F5F_P_0): Likewise.
 325         (VEX_W_0F5F_P_1): Likewise.
 326         (VEX_W_0F5F_P_2): Likewise.
 327         (VEX_W_0F5F_P_3): Likewise.
 328         (VEX_W_0F60_P_2): Likewise.
 329         (VEX_W_0F61_P_2): Likewise.
 330         (VEX_W_0F62_P_2): Likewise.
 331         (VEX_W_0F63_P_2): Likewise.
 332         (VEX_W_0F64_P_2): Likewise.
 333         (VEX_W_0F65_P_2): Likewise.
 334         (VEX_W_0F66_P_2): Likewise.
 335         (VEX_W_0F67_P_2): Likewise.
 336         (VEX_W_0F68_P_2): Likewise.
 337         (VEX_W_0F69_P_2): Likewise.
 338         (VEX_W_0F6A_P_2): Likewise.
 339         (VEX_W_0F6B_P_2): Likewise.
 340         (VEX_W_0F6C_P_2): Likewise.
 341         (VEX_W_0F6D_P_2): Likewise.
 342         (VEX_W_0F6F_P_1): Likewise.
 343         (VEX_W_0F6F_P_2): Likewise.
 344         (VEX_W_0F70_P_1): Likewise.
 345         (VEX_W_0F70_P_2): Likewise.
 346         (VEX_W_0F70_P_3): Likewise.
 347         (VEX_W_0F71_R_2_P_2): Likewise.
 348         (VEX_W_0F71_R_4_P_2): Likewise.
 349         (VEX_W_0F71_R_6_P_2): Likewise.
 350         (VEX_W_0F72_R_2_P_2): Likewise.
 351         (VEX_W_0F72_R_4_P_2): Likewise.
 352         (VEX_W_0F72_R_6_P_2): Likewise.
 353         (VEX_W_0F73_R_2_P_2): Likewise.
 354         (VEX_W_0F73_R_3_P_2): Likewise.
 355         (VEX_W_0F73_R_6_P_2): Likewise.
 356         (VEX_W_0F73_R_7_P_2): Likewise.
 357         (VEX_W_0F74_P_2): Likewise.
 358         (VEX_W_0F75_P_2): Likewise.
 359         (VEX_W_0F76_P_2): Likewise.
 360         (VEX_W_0F77_P_0): Likewise.
 361         (VEX_W_0F7C_P_2): Likewise.
 362         (VEX_W_0F7C_P_3): Likewise.
 363         (VEX_W_0F7D_P_2): Likewise.
 364         (VEX_W_0F7D_P_3): Likewise.
 365         (VEX_W_0F7E_P_1): Likewise.
 366         (VEX_W_0F7F_P_1): Likewise.
 367         (VEX_W_0F7F_P_2): Likewise.
 368         (VEX_W_0FAE_R_2_M_0): Likewise.
 369         (VEX_W_0FAE_R_3_M_0): Likewise.
 370         (VEX_W_0FC2_P_0): Likewise.
 371         (VEX_W_0FC2_P_1): Likewise.
 372         (VEX_W_0FC2_P_2): Likewise.
 373         (VEX_W_0FC2_P_3): Likewise.
 374         (VEX_W_0FD0_P_2): Likewise.
 375         (VEX_W_0FD0_P_3): Likewise.
 376         (VEX_W_0FD1_P_2): Likewise.
 377         (VEX_W_0FD2_P_2): Likewise.
 378         (VEX_W_0FD3_P_2): Likewise.
 379         (VEX_W_0FD4_P_2): Likewise.
 380         (VEX_W_0FD5_P_2): Likewise.
 381         (VEX_W_0FD6_P_2): Likewise.
 382         (VEX_W_0FD7_P_2_M_1): Likewise.
 383         (VEX_W_0FD8_P_2): Likewise.
 384         (VEX_W_0FD9_P_2): Likewise.
 385         (VEX_W_0FDA_P_2): Likewise.
 386         (VEX_W_0FDB_P_2): Likewise.
 387         (VEX_W_0FDC_P_2): Likewise.
 388         (VEX_W_0FDD_P_2): Likewise.
 389         (VEX_W_0FDE_P_2): Likewise.
 390         (VEX_W_0FDF_P_2): Likewise.
 391         (VEX_W_0FE0_P_2): Likewise.
 392         (VEX_W_0FE1_P_2): Likewise.
 393         (VEX_W_0FE2_P_2): Likewise.
 394         (VEX_W_0FE3_P_2): Likewise.
 395         (VEX_W_0FE4_P_2): Likewise.
 396         (VEX_W_0FE5_P_2): Likewise.
 397         (VEX_W_0FE6_P_1): Likewise.
 398         (VEX_W_0FE6_P_2): Likewise.
 399         (VEX_W_0FE6_P_3): Likewise.
 400         (VEX_W_0FE7_P_2_M_0): Likewise.
 401         (VEX_W_0FE8_P_2): Likewise.
 402         (VEX_W_0FE9_P_2): Likewise.
 403         (VEX_W_0FEA_P_2): Likewise.
 404         (VEX_W_0FEB_P_2): Likewise.
 405         (VEX_W_0FEC_P_2): Likewise.
 406         (VEX_W_0FED_P_2): Likewise.
 407         (VEX_W_0FEE_P_2): Likewise.
 408         (VEX_W_0FEF_P_2): Likewise.
 409         (VEX_W_0FF0_P_3_M_0): Likewise.
 410         (VEX_W_0FF1_P_2): Likewise.
 411         (VEX_W_0FF2_P_2): Likewise.
 412         (VEX_W_0FF3_P_2): Likewise.
 413         (VEX_W_0FF4_P_2): Likewise.
 414         (VEX_W_0FF5_P_2): Likewise.
 415         (VEX_W_0FF6_P_2): Likewise.
 416         (VEX_W_0FF7_P_2): Likewise.
 417         (VEX_W_0FF8_P_2): Likewise.
 418         (VEX_W_0FF9_P_2): Likewise.
 419         (VEX_W_0FFA_P_2): Likewise.
 420         (VEX_W_0FFB_P_2): Likewise.
 421         (VEX_W_0FFC_P_2): Likewise.
 422         (VEX_W_0FFD_P_2): Likewise.
 423         (VEX_W_0FFE_P_2): Likewise.
 424         (VEX_W_0F3800_P_2): Likewise.
 425         (VEX_W_0F3801_P_2): Likewise.
 426         (VEX_W_0F3802_P_2): Likewise.
 427         (VEX_W_0F3803_P_2): Likewise.
 428         (VEX_W_0F3804_P_2): Likewise.
 429         (VEX_W_0F3805_P_2): Likewise.
 430         (VEX_W_0F3806_P_2): Likewise.
 431         (VEX_W_0F3807_P_2): Likewise.
 432         (VEX_W_0F3808_P_2): Likewise.
 433         (VEX_W_0F3809_P_2): Likewise.
 434         (VEX_W_0F380A_P_2): Likewise.
 435         (VEX_W_0F380B_P_2): Likewise.
 436         (VEX_W_0F3817_P_2): Likewise.
 437         (VEX_W_0F381C_P_2): Likewise.
 438         (VEX_W_0F381D_P_2): Likewise.
 439         (VEX_W_0F381E_P_2): Likewise.
 440         (VEX_W_0F3820_P_2): Likewise.
 441         (VEX_W_0F3821_P_2): Likewise.
 442         (VEX_W_0F3822_P_2): Likewise.
 443         (VEX_W_0F3823_P_2): Likewise.
 444         (VEX_W_0F3824_P_2): Likewise.
 445         (VEX_W_0F3825_P_2): Likewise.
 446         (VEX_W_0F3828_P_2): Likewise.
 447         (VEX_W_0F3829_P_2): Likewise.
 448         (VEX_W_0F382A_P_2_M_0): Likewise.
 449         (VEX_W_0F382B_P_2): Likewise.
 450         (VEX_W_0F3830_P_2): Likewise.
 451         (VEX_W_0F3831_P_2): Likewise.
 452         (VEX_W_0F3832_P_2): Likewise.
 453         (VEX_W_0F3833_P_2): Likewise.
 454         (VEX_W_0F3834_P_2): Likewise.
 455         (VEX_W_0F3835_P_2): Likewise.
 456         (VEX_W_0F3837_P_2): Likewise.
 457         (VEX_W_0F3838_P_2): Likewise.
 458         (VEX_W_0F3839_P_2): Likewise.
 459         (VEX_W_0F383A_P_2): Likewise.
 460         (VEX_W_0F383B_P_2): Likewise.
 461         (VEX_W_0F383C_P_2): Likewise.
 462         (VEX_W_0F383D_P_2): Likewise.
 463         (VEX_W_0F383E_P_2): Likewise.
 464         (VEX_W_0F383F_P_2): Likewise.
 465         (VEX_W_0F3840_P_2): Likewise.
 466         (VEX_W_0F3841_P_2): Likewise.
 467         (VEX_W_0F38DB_P_2): Likewise.
 468         (VEX_W_0F3A08_P_2): Likewise.
 469         (VEX_W_0F3A09_P_2): Likewise.
 470         (VEX_W_0F3A0A_P_2): Likewise.
 471         (VEX_W_0F3A0B_P_2): Likewise.
 472         (VEX_W_0F3A0C_P_2): Likewise.
 473         (VEX_W_0F3A0D_P_2): Likewise.
 474         (VEX_W_0F3A0E_P_2): Likewise.
 475         (VEX_W_0F3A0F_P_2): Likewise.
 476         (VEX_W_0F3A21_P_2): Likewise.
 477         (VEX_W_0F3A40_P_2): Likewise.
 478         (VEX_W_0F3A41_P_2): Likewise.
 479         (VEX_W_0F3A42_P_2): Likewise.
 480         (VEX_W_0F3A62_P_2): Likewise.
 481         (VEX_W_0F3A63_P_2): Likewise.
 482         (VEX_W_0F3ADF_P_2): Likewise.
 483         (VEX_LEN_0F77_P_0): New.
 484         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 485         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 486         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 487         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 488         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 489         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 490         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 491         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 492         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 493         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 494         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 495         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 496         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 497         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 498         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 499         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 500         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 501         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 502         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 503         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 504         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 505         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 506         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 507         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 508         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 509         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 510         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 511         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 512         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 513         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 514         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 515         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 516         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 517         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 518         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 519         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 520         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 521         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 522         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 523         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 524         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 525         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 526         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 527         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 528         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 529         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 530         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 531         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 532         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 533         (vex_table): Update VEX 0F28 and 0F29 entries.
 534         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 535         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 536         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 537         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 538         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 539         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 540         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 541         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 542         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 543         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 544         VEX_LEN_0F3A0B_P_2 entries.
 545         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 546         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 547         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 548         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 549         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 550         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 551         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 552         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 553         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 554         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 555         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 556         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 557         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 558         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 559         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 560         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 561         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 562         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 563         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 564         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 565         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 566         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 567         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 568         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 569         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 570         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 571         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 572         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 573         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 574         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 575         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 576         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 577         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 578         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 579         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 580         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 581         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 582         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 583         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 584         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 585         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 586         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 587         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 588         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 589         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 590         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 591         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 592         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 593         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 594         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 595         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 596         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 597         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 598         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 599         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 600         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 601         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 602         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 603         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 604         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 605         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 606         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 607         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 608         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 609         VEX_W_0F3ADF_P_2 entries.
 610         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 611         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 612         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 613
 614 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         * i386-opc.tbl (VexWIG): New.
 617         Replace VexW=3 with VexWIG.
 618
 619 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 620
 621         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 622         * i386-tbl.h: Regenerated.
 623
 624 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 625
 626         PR gas/23665
 627         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 628         VEX_LEN_0FD6_P_2 entries.
 629         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 630         * i386-tbl.h: Regenerated.
 631
 632 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         PR gas/23642
 635         * i386-opc.h (VEXWIG): New.
 636         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 637         * i386-tbl.h: Regenerated.
 638
 639 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         PR binutils/23655
 642         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 643         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 644         * i386-dis.c (EXxEVexR64): New.
 645         (evex_rounding_64_mode): Likewise.
 646         (OP_Rounding): Handle evex_rounding_64_mode.
 647
 648 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 649
 650         PR binutils/23655
 651         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 652         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 653         * i386-dis.c (Edqa): New.
 654         (dqa_mode): Likewise.
 655         (intel_operand_size): Handle dqa_mode as m_mode.
 656         (OP_E_register): Handle dqa_mode as dq_mode.
 657         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 658
 659 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 660
 661         * i386-dis.c (OP_E_memory): Reformat.
 662
 663 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-opc.tbl (crc32): Fold byte and word forms.
 666         * i386-tbl.h: Re-generate.
 667
 668 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 671         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 672         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 673         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 674         * i386-tbl.h: Regenerated.
 675
 676 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 679         meaningless.
 680         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 681         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 682         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 683         * i386-tbl.h: Re-generate.
 684
 685 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 688         AVX512_4VNNIW insns.
 689         * i386-tbl.h: Re-generate.
 690
 691 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 694         meaningless.
 695         * i386-tbl.h: Re-generate.
 696
 697 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 700         meaningless.
 701         * i386-tbl.h: Re-generate.
 702
 703 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 704
 705         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 706         meaningless.
 707         * i386-tbl.h: Re-generate.
 708
 709 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 712         meaningless.
 713         * i386-tbl.h: Re-generate.
 714
 715 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 718         meaningless.
 719         * i386-tbl.h: Re-generate.
 720
 721 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 724         * i386-tbl.h: Re-generate.
 725
 726 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 729         * i386-tbl.h: Re-generate.
 730
 731 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 734         meaningless.
 735         * i386-tbl.h: Re-generate.
 736
 737 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 740         meaningless.
 741         * i386-tbl.h: Re-generate.
 742
 743 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 744
 745         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 746         * i386-tbl.h: Re-generate.
 747
 748 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 751         * i386-tbl.h: Re-generate.
 752
 753 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 754
 755         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 756         * i386-tbl.h: Re-generate.
 757
 758 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 761         meaningless.
 762         * i386-tbl.h: Re-generate.
 763
 764 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 767         meaningless.
 768         * i386-tbl.h: Re-generate.
 769
 770 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 773         meaningless.
 774         * i386-tbl.h: Re-generate.
 775
 776 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 779         * i386-tbl.h: Re-generate.
 780
 781 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 784         * i386-tbl.h: Re-generate.
 785
 786 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 789         * i386-tbl.h: Re-generate.
 790
 791 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 794         (vpbroadcastw, rdpid): Drop NoRex64.
 795         * i386-tbl.h: Re-generate.
 796
 797 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 798
 799         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 800         store templates, adding D.
 801         * i386-tbl.h: Re-generate.
 802
 803 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 804
 805         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 806         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 807         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 808         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 809         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 810         Fold load and store templates where possible, adding D. Drop
 811         IgnoreSize where it was pointlessly present. Drop redundant
 812         *word.
 813         * i386-tbl.h: Re-generate.
 814
 815 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 818         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 819         (intel_operand_size): Handle v_bndmk_mode.
 820         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 821
 822 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 823
 824         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 825
 826 2018-08-31  Kito Cheng  <kito@andestech.com>
 827
 828         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 829         compressed floating point instructions.
 830
 831 2018-08-30  Kito Cheng  <kito@andestech.com>
 832
 833         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 834         riscv_opcode.xlen_requirement.
 835         * riscv-opc.c (riscv_opcodes): Update for struct change.
 836
 837 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 838
 839         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 840         psr (PWRPSR) instruction.
 841
 842 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 843
 844         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 845
 846 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 847
 848         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 849
 850 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 851
 852         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 853         loongson3a as an alias of gs464 for compatibility.
 854         * mips-opc.c (mips_opcodes): Change Comments.
 855
 856 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 857
 858         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 859         option.
 860         (print_mips_disassembler_options): Document -M loongson-ext.
 861         * mips-opc.c (LEXT2): New macro.
 862         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 863
 864 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 865
 866          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 867          descriptors.
 868          (parse_mips_ase_option): Handle -M loongson-ext option.
 869          (print_mips_disassembler_options): Document -M loongson-ext.
 870          * mips-opc.c (IL3A): Delete.
 871          * mips-opc.c (LEXT): New macro.
 872          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 873          instructions.
 874
 875 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 876
 877         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 878         descriptors.
 879         (parse_mips_ase_option): Handle -M loongson-cam option.
 880         (print_mips_disassembler_options): Document -M loongson-cam.
 881         * mips-opc.c (LCAM): New macro.
 882         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 883         instructions.
 884
 885 2018-08-21  Alan Modra  <amodra@gmail.com>
 886
 887         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 888         (skip_optional_operands): Count optional operands, and update
 889         ppc_optional_operand_value call.
 890         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 891         (extract_vlensi): Likewise.
 892         (extract_fxm): Return default value for missing optional operand.
 893         (extract_ls, extract_raq, extract_tbr): Likewise.
 894         (insert_sxl, extract_sxl): New functions.
 895         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 896         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 897         flag and extra entry.
 898         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 899         extract_sxl.
 900
 901 2018-08-20  Alan Modra  <amodra@gmail.com>
 902
 903         * sh-opc.h (MASK): Simplify.
 904
 905 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 906
 907         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 908         BM_RESERVED0 or BM_RESERVED1
 909         (bm_rel_decode, bm_n_bytes): Ditto.
 910
 911 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 912
 913         * s12z.h: Delete.
 914
 915 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 918         address with the addr32 prefix and without base nor index
 919         registers.
 920
 921 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 924         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 925         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 926         (cpu_flags): Add CpuCMOV and CpuFXSR.
 927         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 928         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 929         * i386-init.h: Regenerated.
 930         * i386-tbl.h: Likewise.
 931
 932 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 933
 934         * arc-regs.h: Update auxiliary registers.
 935
 936 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 939         (RegIP, RegIZ): Define.
 940         * i386-reg.tbl: Adjust comments.
 941         (rip): Use Qword instead of BaseIndex. Use RegIP.
 942         (eip): Use Dword instead of BaseIndex. Use RegIP.
 943         (riz): Add Qword. Use RegIZ.
 944         (eiz): Add Dword. Use RegIZ.
 945         * i386-tbl.h: Re-generate.
 946
 947 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 950         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 951         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 952         * i386-tbl.h: Re-generate.
 953
 954 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-gen.c (operand_types): Remove Mem field.
 957         * i386-opc.h (union i386_operand_type): Remove mem field.
 958         * i386-init.h, i386-tbl.h: Re-generate.
 959
 960 2018-08-01  Alan Modra  <amodra@gmail.com>
 961
 962         * po/POTFILES.in: Regenerate.
 963
 964 2018-07-31  Nick Clifton  <nickc@redhat.com>
 965
 966         * po/sv.po: Updated Swedish translation.
 967
 968 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 971         * i386-init.h, i386-tbl.h: Re-generate.
 972
 973 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.h (ZEROING_MASKING) Rename to ...
 976         (DYNAMIC_MASKING): ... this. Adjust comment.
 977         * i386-opc.tbl (MaskingMorZ): Define.
 978         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 979         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 980         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 981         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 982         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 983         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 984         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 985         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 986         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 987
 988 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-opc.tbl: Use element rather than vector size for AVX512*
 991         scatter/gather insns.
 992         * i386-tbl.h: Re-generate.
 993
 994 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 997         (cpu_flags): Drop CpuVREX.
 998         * i386-opc.h (CpuVREX): Delete.
 999         (union i386_cpu_flags): Remove cpuvrex.
1000         * i386-init.h, i386-tbl.h: Re-generate.
1001
1002 2018-07-30  Jim Wilson  <jimw@sifive.com>
1003
1004         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1005         fields.
1006         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1007
1008 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1009
1010         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1011         * Makefile.in: Regenerated.
1012         * configure.ac: Add C-SKY.
1013         * configure: Regenerated.
1014         * csky-dis.c: New file.
1015         * csky-opc.h: New file.
1016         * disassemble.c (ARCH_csky): Define.
1017         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1018         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1019
1020 2018-07-27  Alan Modra  <amodra@gmail.com>
1021
1022         * ppc-opc.c (insert_sprbat): Correct function parameter and
1023         return type.
1024         (extract_sprbat): Likewise, variable too.
1025
1026 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1027             Alan Modra  <amodra@gmail.com>
1028
1029         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1030         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1031         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1032         support disjointed BAT.
1033         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1034         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1035         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1036
1037 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1038             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1039
1040         * i386-gen.c (adjust_broadcast_modifier): New function.
1041         (process_i386_opcode_modifier): Add an argument for operands.
1042         Adjust the Broadcast value based on operands.
1043         (output_i386_opcode): Pass operand_types to
1044         process_i386_opcode_modifier.
1045         (process_i386_opcodes): Pass NULL as operands to
1046         process_i386_opcode_modifier.
1047         * i386-opc.h (BYTE_BROADCAST): New.
1048         (WORD_BROADCAST): Likewise.
1049         (DWORD_BROADCAST): Likewise.
1050         (QWORD_BROADCAST): Likewise.
1051         (i386_opcode_modifier): Expand broadcast to 3 bits.
1052         * i386-tbl.h: Regenerated.
1053
1054 2018-07-24  Alan Modra  <amodra@gmail.com>
1055
1056         PR 23430
1057         * or1k-desc.h: Regenerate.
1058
1059 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1062         vcvtusi2ss, and vcvtusi2sd.
1063         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1064         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1065         * i386-tbl.h: Re-generate.
1066
1067 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1068
1069         * arc-opc.c (extract_w6): Fix extending the sign.
1070
1071 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1072
1073         * arc-tbl.h (vewt): Allow it for ARC EM family.
1074
1075 2018-07-23  Alan Modra  <amodra@gmail.com>
1076
1077         PR 23419
1078         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1079         opcode variants for mtspr/mfspr encodings.
1080
1081 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1082             Maciej W. Rozycki  <macro@mips.com>
1083
1084         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1085         loongson3a descriptors.
1086         (parse_mips_ase_option): Handle -M loongson-mmi option.
1087         (print_mips_disassembler_options): Document -M loongson-mmi.
1088         * mips-opc.c (LMMI): New macro.
1089         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1090         instructions.
1091
1092 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1093
1094         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1095         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1096         IgnoreSize and [XYZ]MMword where applicable.
1097         * i386-tbl.h: Re-generate.
1098
1099 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1102         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1103         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1104         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1105         * i386-tbl.h: Re-generate.
1106
1107 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1110         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1111         VPCLMULQDQ templates into their respective AVX512VL counterparts
1112         where possible, using Disp8ShiftVL and CheckRegSize instead of
1113         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1114         * i386-tbl.h: Re-generate.
1115
1116 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1119         AVX512VL counterparts where possible, using Disp8ShiftVL and
1120         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1121         IgnoreSize) as appropriate.
1122         * i386-tbl.h: Re-generate.
1123
1124 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1125
1126         * i386-opc.tbl: Fold AVX512BW templates into their respective
1127         AVX512VL counterparts where possible, using Disp8ShiftVL and
1128         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1129         IgnoreSize) as appropriate.
1130         * i386-tbl.h: Re-generate.
1131
1132 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-opc.tbl: Fold AVX512CD templates into their respective
1135         AVX512VL counterparts where possible, using Disp8ShiftVL and
1136         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1137         IgnoreSize) as appropriate.
1138         * i386-tbl.h: Re-generate.
1139
1140 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-opc.h (DISP8_SHIFT_VL): New.
1143         * i386-opc.tbl (Disp8ShiftVL):  Define.
1144         (various): Fold AVX512VL templates into their respective
1145         AVX512F counterparts where possible, using Disp8ShiftVL and
1146         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1147         IgnoreSize) as appropriate.
1148         * i386-tbl.h: Re-generate.
1149
1150 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1151
1152         * Makefile.am: Change dependencies and rule for
1153         $(srcdir)/i386-init.h.
1154         * Makefile.in: Re-generate.
1155         * i386-gen.c (process_i386_opcodes): New local variable
1156         "marker". Drop opening of input file. Recognize marker and line
1157         number directives.
1158         * i386-opc.tbl (OPCODE_I386_H): Define.
1159         (i386-opc.h): Include it.
1160         (None): Undefine.
1161
1162 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1163
1164         PR gas/23418
1165         * i386-opc.h (Byte): Update comments.
1166         (Word): Likewise.
1167         (Dword): Likewise.
1168         (Fword): Likewise.
1169         (Qword): Likewise.
1170         (Tbyte): Likewise.
1171         (Xmmword): Likewise.
1172         (Ymmword): Likewise.
1173         (Zmmword): Likewise.
1174         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1175         vcvttps2uqq.
1176         * i386-tbl.h: Regenerated.
1177
1178 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1179
1180         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1181         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1182         * aarch64-asm-2.c: Regenerate.
1183         * aarch64-dis-2.c: Regenerate.
1184         * aarch64-opc-2.c: Regenerate.
1185
1186 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1187
1188         PR binutils/23192
1189         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1190         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1191         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1192         sqdmulh, sqrdmulh): Use Em16.
1193
1194 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1195
1196         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1197         csdb together with them.
1198         (thumb32_opcodes): Likewise.
1199
1200 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1201
1202         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1203         requiring 32-bit registers as operands 2 and 3. Improve
1204         comments.
1205         (mwait, mwaitx): Fold templates. Improve comments.
1206         OPERAND_TYPE_INOUTPORTREG.
1207         * i386-tbl.h: Re-generate.
1208
1209 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-gen.c (operand_type_init): Remove
1212         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1213         OPERAND_TYPE_INOUTPORTREG.
1214         * i386-init.h: Re-generate.
1215
1216 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1217
1218         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1219         (wrssq, wrussq): Add Qword.
1220         * i386-tbl.h: Re-generate.
1221
1222 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1223
1224         * i386-opc.h: Rename OTMax to OTNum.
1225         (OTNumOfUints): Adjust calculation.
1226         (OTUnused): Directly alias to OTNum.
1227
1228 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1229
1230         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1231         `reg_xys'.
1232         (lea_reg_xys): Likewise.
1233         (print_insn_loop_primitive): Rename `reg' local variable to
1234         `reg_dxy'.
1235
1236 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1237
1238         PR binutils/23242
1239         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1240
1241 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1242
1243         PR binutils/23369
1244         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1245         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1246
1247 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1248
1249         PR tdep/8282
1250         * mips-dis.c (mips_option_arg_t): New enumeration.
1251         (mips_options): New variable.
1252         (disassembler_options_mips): New function.
1253         (print_mips_disassembler_options): Reimplement in terms of
1254         `disassembler_options_mips'.
1255         * arm-dis.c (disassembler_options_arm): Adapt to using the
1256         `disasm_options_and_args_t' structure.
1257         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1258         * s390-dis.c (disassembler_options_s390): Likewise.
1259
1260 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1261
1262         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1263         expected result.
1264         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1265         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1266         * testsuite/ld-arm/tls-longplt.d: Likewise.
1267
1268 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1269
1270         PR binutils/23192
1271         * aarch64-asm-2.c: Regenerate.
1272         * aarch64-dis-2.c: Likewise.
1273         * aarch64-opc-2.c: Likewise.
1274         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1275         * aarch64-opc.c (operand_general_constraint_met_p,
1276         aarch64_print_operand): Likewise.
1277         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1278         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1279         fmlal2, fmlsl2.
1280         (AARCH64_OPERANDS): Add Em2.
1281
1282 2018-06-26  Nick Clifton  <nickc@redhat.com>
1283
1284         * po/uk.po: Updated Ukranian translation.
1285         * po/de.po: Updated German translation.
1286         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1287
1288 2018-06-26  Nick Clifton  <nickc@redhat.com>
1289
1290         * nfp-dis.c: Fix spelling mistake.
1291
1292 2018-06-24  Nick Clifton  <nickc@redhat.com>
1293
1294         * configure: Regenerate.
1295         * po/opcodes.pot: Regenerate.
1296
1297 2018-06-24  Nick Clifton  <nickc@redhat.com>
1298
1299         2.31 branch created.
1300
1301 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1302
1303         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1304         * aarch64-asm-2.c: Regenerate.
1305         * aarch64-dis-2.c: Likewise.
1306
1307 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1308
1309         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1310         `-M ginv' option description.
1311
1312 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1313
1314         PR gas/23305
1315         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1316         la and lla.
1317
1318 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1319
1320         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1321         * configure.ac: Remove AC_PREREQ.
1322         * Makefile.in: Re-generate.
1323         * aclocal.m4: Re-generate.
1324         * configure: Re-generate.
1325
1326 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1327
1328         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1329         mips64r6 descriptors.
1330         (parse_mips_ase_option): Handle -Mginv option.
1331         (print_mips_disassembler_options): Document -Mginv.
1332         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1333         (GINV): New macro.
1334         (mips_opcodes): Define ginvi and ginvt.
1335
1336 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1337             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1338
1339         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1340         * mips-opc.c (CRC, CRC64): New macros.
1341         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1342         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1343         crc32cd for CRC64.
1344
1345 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1346
1347         PR 20319
1348         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1349         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1350
1351 2018-06-06  Alan Modra  <amodra@gmail.com>
1352
1353         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1354         setjmp.  Move init for some other vars later too.
1355
1356 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1357
1358         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1359         (dis_private): Add new fields for property section tracking.
1360         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1361         (xtensa_instruction_fits): New functions.
1362         (fetch_data): Bump minimal fetch size to 4.
1363         (print_insn_xtensa): Make struct dis_private static.
1364         Load and prepare property table on section change.
1365         Don't disassemble literals. Don't disassemble instructions that
1366         cross property table boundaries.
1367
1368 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1369
1370         * configure: Regenerated.
1371
1372 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1373
1374         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1375         * i386-tbl.h: Re-generate.
1376
1377 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1378
1379         * i386-opc.tbl (sldt, str): Add NoRex64.
1380         * i386-tbl.h: Re-generate.
1381
1382 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1383
1384         * i386-opc.tbl (invpcid): Add Oword.
1385         * i386-tbl.h: Re-generate.
1386
1387 2018-06-01  Alan Modra  <amodra@gmail.com>
1388
1389         * sysdep.h (_bfd_error_handler): Don't declare.
1390         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1391         * rl78-decode.opc: Likewise.
1392         * msp430-decode.c: Regenerate.
1393         * rl78-decode.c: Regenerate.
1394
1395 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1396
1397         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1398         * i386-init.h : Regenerated.
1399
1400 2018-05-25  Alan Modra  <amodra@gmail.com>
1401
1402         * Makefile.in: Regenerate.
1403         * po/POTFILES.in: Regenerate.
1404
1405 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1406
1407         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1408         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1409         (insert_bab, extract_bab, insert_btab, extract_btab,
1410         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1411         (BAT, BBA VBA RBS XB6S): Delete macros.
1412         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1413         (BB, BD, RBX, XC6): Update for new macros.
1414         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1415         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1416         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1417         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1418
1419 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1420
1421         * Makefile.am: Add support for s12z architecture.
1422         * configure.ac: Likewise.
1423         * disassemble.c: Likewise.
1424         * disassemble.h: Likewise.
1425         * Makefile.in: Regenerate.
1426         * configure: Regenerate.
1427         * s12z-dis.c: New file.
1428         * s12z.h: New file.
1429
1430 2018-05-18  Alan Modra  <amodra@gmail.com>
1431
1432         * nfp-dis.c: Don't #include libbfd.h.
1433         (init_nfp3200_priv): Use bfd_get_section_contents.
1434         (nit_nfp6000_mecsr_sec): Likewise.
1435
1436 2018-05-17  Nick Clifton  <nickc@redhat.com>
1437
1438         * po/zh_CN.po: Updated simplified Chinese translation.
1439
1440 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1441
1442         PR binutils/23109
1443         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1444         * aarch64-dis-2.c: Regenerate.
1445
1446 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1447
1448         PR binutils/21446
1449         * aarch64-asm.c (opintl.h): Include.
1450         (aarch64_ins_sysreg): Enforce read/write constraints.
1451         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1452         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1453         (F_REG_READ, F_REG_WRITE): New.
1454         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1455         AARCH64_OPND_SYSREG.
1456         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1457         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1458         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1459         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1460         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1461         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1462         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1463         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1464         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1465         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1466         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1467         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1468         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1469         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1470         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1471         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1472         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1473
1474 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1475
1476         PR binutils/21446
1477         * aarch64-dis.c (no_notes: New.
1478         (parse_aarch64_dis_option): Support notes.
1479         (aarch64_decode_insn, print_operands): Likewise.
1480         (print_aarch64_disassembler_options): Document notes.
1481         * aarch64-opc.c (aarch64_print_operand): Support notes.
1482
1483 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1484
1485         PR binutils/21446
1486         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1487         and take error struct.
1488         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1489         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1490         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1491         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1492         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1493         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1494         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1495         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1496         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1497         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1498         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1499         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1500         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1501         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1502         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1503         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1504         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1505         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1506         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1507         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1508         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1509         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1510         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1511         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1512         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1513         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1514         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1515         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1516         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1517         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1518         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1519         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1520         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1521         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1522         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1523         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1524         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1525         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1526         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1527         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1528         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1529         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1530         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1531         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1532         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1533         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1534         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1535         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1536         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1537         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1538         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1539         (determine_disassembling_preference, aarch64_decode_insn,
1540         print_insn_aarch64_word, print_insn_data): Take errors struct.
1541         (print_insn_aarch64): Use errors.
1542         * aarch64-asm-2.c: Regenerate.
1543         * aarch64-dis-2.c: Regenerate.
1544         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1545         boolean in aarch64_insert_operan.
1546         (print_operand_extractor): Likewise.
1547         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1548
1549 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1550
1551         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1552
1553 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1554
1555         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1556
1557 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1558
1559         * cr16-opc.c (cr16_instruction): Comment typo fix.
1560         * hppa-dis.c (print_insn_hppa): Likewise.
1561
1562 2018-05-08  Jim Wilson  <jimw@sifive.com>
1563
1564         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1565         (match_c_slli64, match_srxi_as_c_srxi): New.
1566         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1567         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1568         <c.slli, c.srli, c.srai>: Use match_s_slli.
1569         <c.slli64, c.srli64, c.srai64>: New.
1570
1571 2018-05-08  Alan Modra  <amodra@gmail.com>
1572
1573         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1574         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1575         partition opcode space for index lookup.
1576
1577 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1578
1579         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1580         <insn_length>: ...with this.  Update usage.
1581         Remove duplicate call to *info->memory_error_func.
1582
1583 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1584             H.J. Lu  <hongjiu.lu@intel.com>
1585
1586         * i386-dis.c (Gva): New.
1587         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1588         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1589         (prefix_table): New instructions (see prefix above).
1590         (mod_table): New instructions (see prefix above).
1591         (OP_G): Handle va_mode.
1592         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1593         CPU_MOVDIR64B_FLAGS.
1594         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1595         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1596         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1597         * i386-opc.tbl: Add movidir{i,64b}.
1598         * i386-init.h: Regenerated.
1599         * i386-tbl.h: Likewise.
1600
1601 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1602
1603         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1604         AddrPrefixOpReg.
1605         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1606         (AddrPrefixOpReg): This.
1607         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1608         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1609
1610 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1611
1612         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1613         (vle_num_opcodes): Likewise.
1614         (spe2_num_opcodes): Likewise.
1615         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1616         initialization loop.
1617         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1618         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1619         only once.
1620
1621 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1622
1623         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1624
1625 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1626
1627         Makefile.am: Added nfp-dis.c.
1628         configure.ac: Added bfd_nfp_arch.
1629         disassemble.h: Added print_insn_nfp prototype.
1630         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1631         nfp-dis.c: New, for NFP support.
1632         po/POTFILES.in: Added nfp-dis.c to the list.
1633         Makefile.in: Regenerate.
1634         configure: Regenerate.
1635
1636 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1637
1638         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1639         templates into their base ones.
1640         * i386-tlb.h: Re-generate.
1641
1642 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1643
1644         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1645         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1646         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1647         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1648         * i386-init.h: Re-generate.
1649
1650 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1651
1652         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1653         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1654         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1655         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1656         comment.
1657         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1658         and CpuRegMask.
1659         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1660         CpuRegMask: Delete.
1661         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1662         cpuregzmm, and cpuregmask.
1663         * i386-init.h: Re-generate.
1664         * i386-tbl.h: Re-generate.
1665
1666 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1667
1668         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1669         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1670         * i386-init.h: Re-generate.
1671
1672 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1673
1674         * i386-gen.c (VexImmExt): Delete.
1675         * i386-opc.h (VexImmExt, veximmext): Delete.
1676         * i386-opc.tbl: Drop all VexImmExt uses.
1677         * i386-tlb.h: Re-generate.
1678
1679 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1680
1681         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1682         register-only forms.
1683         * i386-tlb.h: Re-generate.
1684
1685 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1686
1687         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1688
1689 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1690
1691         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1692         PREFIX_0F1C.
1693         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1694         (cpu_flags): Add CpuCLDEMOTE.
1695         * i386-init.h: Regenerate.
1696         * i386-opc.h (enum): Add CpuCLDEMOTE,
1697         (i386_cpu_flags): Add cpucldemote.
1698         * i386-opc.tbl: Add cldemote.
1699         * i386-tbl.h: Regenerate.
1700
1701 2018-04-16  Alan Modra  <amodra@gmail.com>
1702
1703         * Makefile.am: Remove sh5 and sh64 support.
1704         * configure.ac: Likewise.
1705         * disassemble.c: Likewise.
1706         * disassemble.h: Likewise.
1707         * sh-dis.c: Likewise.
1708         * sh64-dis.c: Delete.
1709         * sh64-opc.c: Delete.
1710         * sh64-opc.h: Delete.
1711         * Makefile.in: Regenerate.
1712         * configure: Regenerate.
1713         * po/POTFILES.in: Regenerate.
1714
1715 2018-04-16  Alan Modra  <amodra@gmail.com>
1716
1717         * Makefile.am: Remove w65 support.
1718         * configure.ac: Likewise.
1719         * disassemble.c: Likewise.
1720         * disassemble.h: Likewise.
1721         * w65-dis.c: Delete.
1722         * w65-opc.h: Delete.
1723         * Makefile.in: Regenerate.
1724         * configure: Regenerate.
1725         * po/POTFILES.in: Regenerate.
1726
1727 2018-04-16  Alan Modra  <amodra@gmail.com>
1728
1729         * configure.ac: Remove we32k support.
1730         * configure: Regenerate.
1731
1732 2018-04-16  Alan Modra  <amodra@gmail.com>
1733
1734         * Makefile.am: Remove m88k support.
1735         * configure.ac: Likewise.
1736         * disassemble.c: Likewise.
1737         * disassemble.h: Likewise.
1738         * m88k-dis.c: Delete.
1739         * Makefile.in: Regenerate.
1740         * configure: Regenerate.
1741         * po/POTFILES.in: Regenerate.
1742
1743 2018-04-16  Alan Modra  <amodra@gmail.com>
1744
1745         * Makefile.am: Remove i370 support.
1746         * configure.ac: Likewise.
1747         * disassemble.c: Likewise.
1748         * disassemble.h: Likewise.
1749         * i370-dis.c: Delete.
1750         * i370-opc.c: Delete.
1751         * Makefile.in: Regenerate.
1752         * configure: Regenerate.
1753         * po/POTFILES.in: Regenerate.
1754
1755 2018-04-16  Alan Modra  <amodra@gmail.com>
1756
1757         * Makefile.am: Remove h8500 support.
1758         * configure.ac: Likewise.
1759         * disassemble.c: Likewise.
1760         * disassemble.h: Likewise.
1761         * h8500-dis.c: Delete.
1762         * h8500-opc.h: Delete.
1763         * Makefile.in: Regenerate.
1764         * configure: Regenerate.
1765         * po/POTFILES.in: Regenerate.
1766
1767 2018-04-16  Alan Modra  <amodra@gmail.com>
1768
1769         * configure.ac: Remove tahoe support.
1770         * configure: Regenerate.
1771
1772 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1773
1774         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1775         umwait.
1776         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1777         64-bit mode.
1778         * i386-tbl.h: Regenerated.
1779
1780 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1781
1782         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1783         PREFIX_MOD_1_0FAE_REG_6.
1784         (va_mode): New.
1785         (OP_E_register): Use va_mode.
1786         * i386-dis-evex.h (prefix_table):
1787         New instructions (see prefixes above).
1788         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1789         (cpu_flags): Likewise.
1790         * i386-opc.h (enum): Likewise.
1791         (i386_cpu_flags): Likewise.
1792         * i386-opc.tbl: Add umonitor, umwait, tpause.
1793         * i386-init.h: Regenerate.
1794         * i386-tbl.h: Likewise.
1795
1796 2018-04-11  Alan Modra  <amodra@gmail.com>
1797
1798         * opcodes/i860-dis.c: Delete.
1799         * opcodes/i960-dis.c: Delete.
1800         * Makefile.am: Remove i860 and i960 support.
1801         * configure.ac: Likewise.
1802         * disassemble.c: Likewise.
1803         * disassemble.h: Likewise.
1804         * Makefile.in: Regenerate.
1805         * configure: Regenerate.
1806         * po/POTFILES.in: Regenerate.
1807
1808 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1809
1810         PR binutils/23025
1811         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1812         to 0.
1813         (print_insn): Clear vex instead of vex.evex.
1814
1815 2018-04-04  Nick Clifton  <nickc@redhat.com>
1816
1817         * po/es.po: Updated Spanish translation.
1818
1819 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1820
1821         * i386-gen.c (opcode_modifiers): Delete VecESize.
1822         * i386-opc.h (VecESize): Delete.
1823         (struct i386_opcode_modifier): Delete vecesize.
1824         * i386-opc.tbl: Drop VecESize.
1825         * i386-tlb.h: Re-generate.
1826
1827 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1828
1829         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1830         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1831         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1832         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1833         * i386-tlb.h: Re-generate.
1834
1835 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1836
1837         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1838         Fold AVX512 forms
1839         * i386-tlb.h: Re-generate.
1840
1841 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1842
1843         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1844         (vex_len_table): Drop Y for vcvt*2si.
1845         (putop): Replace plain 'Y' handling by abort().
1846
1847 2018-03-28  Nick Clifton  <nickc@redhat.com>
1848
1849         PR 22988
1850         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1851         instructions with only a base address register.
1852         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1853         handle AARHC64_OPND_SVE_ADDR_R.
1854         (aarch64_print_operand): Likewise.
1855         * aarch64-asm-2.c: Regenerate.
1856         * aarch64_dis-2.c: Regenerate.
1857         * aarch64-opc-2.c: Regenerate.
1858
1859 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1860
1861         * i386-opc.tbl: Drop VecESize from register only insn forms and
1862         memory forms not allowing broadcast.
1863         * i386-tlb.h: Re-generate.
1864
1865 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1866
1867         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1868         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1869         sha256*): Drop Disp<N>.
1870
1871 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1872
1873         * i386-dis.c (EbndS, bnd_swap_mode): New.
1874         (prefix_table): Use EbndS.
1875         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1876         * i386-opc.tbl (bndmov): Move misplaced Load.
1877         * i386-tlb.h: Re-generate.
1878
1879 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1880
1881         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1882         templates allowing memory operands and folded ones for register
1883         only flavors.
1884         * i386-tlb.h: Re-generate.
1885
1886 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1887
1888         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1889         256-bit templates. Drop redundant leftover Disp<N>.
1890         * i386-tlb.h: Re-generate.
1891
1892 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1893
1894         * riscv-opc.c (riscv_insn_types): New.
1895
1896 2018-03-13  Nick Clifton  <nickc@redhat.com>
1897
1898         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1899
1900 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1901
1902         * i386-opc.tbl: Add Optimize to clr.
1903         * i386-tbl.h: Regenerated.
1904
1905 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1906
1907         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1908         * i386-opc.h (OldGcc): Removed.
1909         (i386_opcode_modifier): Remove oldgcc.
1910         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1911         instructions for old (<= 2.8.1) versions of gcc.
1912         * i386-tbl.h: Regenerated.
1913
1914 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1915
1916         * i386-opc.h (EVEXDYN): New.
1917         * i386-opc.tbl: Fold various AVX512VL templates.
1918         * i386-tlb.h: Re-generate.
1919
1920 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1921
1922         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1923         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1924         vpexpandd, vpexpandq): Fold AFX512VF templates.
1925         * i386-tlb.h: Re-generate.
1926
1927 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1928
1929         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1930         Fold 128- and 256-bit VEX-encoded templates.
1931         * i386-tlb.h: Re-generate.
1932
1933 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1934
1935         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1936         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1937         vpexpandd, vpexpandq): Fold AVX512F templates.
1938         * i386-tlb.h: Re-generate.
1939
1940 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1941
1942         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1943         64-bit templates. Drop Disp<N>.
1944         * i386-tlb.h: Re-generate.
1945
1946 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1947
1948         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1949         and 256-bit templates.
1950         * i386-tlb.h: Re-generate.
1951
1952 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1955         * i386-tlb.h: Re-generate.
1956
1957 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1958
1959         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1960         Drop NoAVX.
1961         * i386-tlb.h: Re-generate.
1962
1963 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1964
1965         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1966         * i386-tlb.h: Re-generate.
1967
1968 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1969
1970         * i386-gen.c (opcode_modifiers): Delete FloatD.
1971         * i386-opc.h (FloatD): Delete.
1972         (struct i386_opcode_modifier): Delete floatd.
1973         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1974         FloatD by D.
1975         * i386-tlb.h: Re-generate.
1976
1977 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1978
1979         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1980
1981 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1982
1983         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1984         * i386-tlb.h: Re-generate.
1985
1986 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1987
1988         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1989         forms.
1990         * i386-tlb.h: Re-generate.
1991
1992 2018-03-07  Alan Modra  <amodra@gmail.com>
1993
1994         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1995         bfd_arch_rs6000.
1996         * disassemble.h (print_insn_rs6000): Delete.
1997         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1998         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1999         (print_insn_rs6000): Delete.
2000
2001 2018-03-03  Alan Modra  <amodra@gmail.com>
2002
2003         * sysdep.h (opcodes_error_handler): Define.
2004         (_bfd_error_handler): Declare.
2005         * Makefile.am: Remove stray #.
2006         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2007         EDIT" comment.
2008         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2009         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2010         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2011         opcodes_error_handler to print errors.  Standardize error messages.
2012         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2013         and include opintl.h.
2014         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2015         * i386-gen.c: Standardize error messages.
2016         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2017         * Makefile.in: Regenerate.
2018         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2019         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2020         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2021         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2022         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2023         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2024         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2025         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2026         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2027         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2028         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2029         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2030         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2031
2032 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2033
2034         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2035         vpsub[bwdq] instructions.
2036         * i386-tbl.h: Regenerated.
2037
2038 2018-03-01  Alan Modra  <amodra@gmail.com>
2039
2040         * configure.ac (ALL_LINGUAS): Sort.
2041         * configure: Regenerate.
2042
2043 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2044
2045         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2046         macro by assignements.
2047
2048 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2049
2050         PR gas/22871
2051         * i386-gen.c (opcode_modifiers): Add Optimize.
2052         * i386-opc.h (Optimize): New enum.
2053         (i386_opcode_modifier): Add optimize.
2054         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2055         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2056         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2057         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2058         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2059         vpxord and vpxorq.
2060         * i386-tbl.h: Regenerated.
2061
2062 2018-02-26  Alan Modra  <amodra@gmail.com>
2063
2064         * crx-dis.c (getregliststring): Allocate a large enough buffer
2065         to silence false positive gcc8 warning.
2066
2067 2018-02-22  Shea Levy <shea@shealevy.com>
2068
2069         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2070
2071 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2072
2073         * i386-opc.tbl: Add {rex},
2074         * i386-tbl.h: Regenerated.
2075
2076 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2077
2078         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2079         (mips16_opcodes): Replace `M' with `m' for "restore".
2080
2081 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2082
2083         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2084
2085 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2086
2087         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2088         variable to `function_index'.
2089
2090 2018-02-13  Nick Clifton  <nickc@redhat.com>
2091
2092         PR 22823
2093         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2094         about truncation of printing.
2095
2096 2018-02-12  Henry Wong <henry@stuffedcow.net>
2097
2098         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2099
2100 2018-02-05  Nick Clifton  <nickc@redhat.com>
2101
2102         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2103
2104 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2105
2106         * i386-dis.c (enum): Add pconfig.
2107         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2108         (cpu_flags): Add CpuPCONFIG.
2109         * i386-opc.h (enum): Add CpuPCONFIG.
2110         (i386_cpu_flags): Add cpupconfig.
2111         * i386-opc.tbl: Add PCONFIG instruction.
2112         * i386-init.h: Regenerate.
2113         * i386-tbl.h: Likewise.
2114
2115 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2116
2117         * i386-dis.c (enum): Add PREFIX_0F09.
2118         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2119         (cpu_flags): Add CpuWBNOINVD.
2120         * i386-opc.h (enum): Add CpuWBNOINVD.
2121         (i386_cpu_flags): Add cpuwbnoinvd.
2122         * i386-opc.tbl: Add WBNOINVD instruction.
2123         * i386-init.h: Regenerate.
2124         * i386-tbl.h: Likewise.
2125
2126 2018-01-17  Jim Wilson  <jimw@sifive.com>
2127
2128         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2129
2130 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2131
2132         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2133         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2134         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2135         (cpu_flags): Add CpuIBT, CpuSHSTK.
2136         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2137         (i386_cpu_flags): Add cpuibt, cpushstk.
2138         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2139         * i386-init.h: Regenerate.
2140         * i386-tbl.h: Likewise.
2141
2142 2018-01-16  Nick Clifton  <nickc@redhat.com>
2143
2144         * po/pt_BR.po: Updated Brazilian Portugese translation.
2145         * po/de.po: Updated German translation.
2146
2147 2018-01-15  Jim Wilson  <jimw@sifive.com>
2148
2149         * riscv-opc.c (match_c_nop): New.
2150         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2151
2152 2018-01-15  Nick Clifton  <nickc@redhat.com>
2153
2154         * po/uk.po: Updated Ukranian translation.
2155
2156 2018-01-13  Nick Clifton  <nickc@redhat.com>
2157
2158         * po/opcodes.pot: Regenerated.
2159
2160 2018-01-13  Nick Clifton  <nickc@redhat.com>
2161
2162         * configure: Regenerate.
2163
2164 2018-01-13  Nick Clifton  <nickc@redhat.com>
2165
2166         2.30 branch created.
2167
2168 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2169
2170         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2171         * i386-tbl.h: Regenerate.
2172
2173 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2174
2175         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2176         * i386-tbl.h: Re-generate.
2177
2178 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2179
2180         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2181         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2182         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2183         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2184         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2185         Disp8MemShift of AVX512VL forms.
2186         * i386-tbl.h: Re-generate.
2187
2188 2018-01-09  Jim Wilson  <jimw@sifive.com>
2189
2190         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2191         then the hi_addr value is zero.
2192
2193 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2194
2195         * arm-dis.c (arm_opcodes): Add csdb.
2196         (thumb32_opcodes): Add csdb.
2197
2198 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2199
2200         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2201         * aarch64-asm-2.c: Regenerate.
2202         * aarch64-dis-2.c: Regenerate.
2203         * aarch64-opc-2.c: Regenerate.
2204
2205 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2206
2207         PR gas/22681
2208         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2209         Remove AVX512 vmovd with 64-bit operands.
2210         * i386-tbl.h: Regenerated.
2211
2212 2018-01-05  Jim Wilson  <jimw@sifive.com>
2213
2214         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2215         jalr.
2216
2217 2018-01-03  Alan Modra  <amodra@gmail.com>
2218
2219         Update year range in copyright notice of all files.
2220
2221 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2222
2223         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2224         and OPERAND_TYPE_REGZMM entries.
2225
2226 For older changes see ChangeLog-2017
2227 \f
2228 Copyright (C) 2018 Free Software Foundation, Inc.
2229
2230 Copying and distribution of this file, with or without modification,
2231 are permitted in any medium without royalty provided the copyright
2232 notice and this notice are preserved.
2233
2234 Local Variables:
2235 mode: change-log
2236 left-margin: 8
2237 fill-column: 74
2238 version-control: never
2239 End: