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[ARC] Fix assembler relaxation.
[thirdparty/binutils-gdb.git] / opcodes / arc-opc.c
1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "bfd.h"
25 #include "opcode/arc.h"
26 #include "opintl.h"
27 #include "libiberty.h"
28
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. All NPS400 features are built into all ARC target builds as
31 this reduces the chances that regressions might creep in. */
32
33 /* Insert RA register into a 32-bit opcode, with checks. */
34 static unsigned long long
35 insert_ra_chk (unsigned long long insn,
36 long long int value,
37 const char **errmsg ATTRIBUTE_UNUSED)
38 {
39 if (value == 60)
40 *errmsg = _("LP_COUNT register cannot be used as destination register");
41
42 return insn | (value & 0x3F);
43 }
44 /* Insert RB register into a 32-bit opcode. */
45 static unsigned long long
46 insert_rb (unsigned long long insn,
47 long long int value,
48 const char **errmsg ATTRIBUTE_UNUSED)
49 {
50 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
51 }
52
53 /* Insert RB register with checks. */
54 static unsigned long long
55 insert_rb_chk (unsigned long long insn,
56 long long int value,
57 const char **errmsg ATTRIBUTE_UNUSED)
58 {
59 if (value == 60)
60 *errmsg = _("LP_COUNT register cannot be used as destination register");
61
62 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
63 }
64
65 static long long int
66 extract_rb (unsigned long long insn ATTRIBUTE_UNUSED,
67 bfd_boolean * invalid ATTRIBUTE_UNUSED)
68 {
69 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
70
71 if (value == 0x3e && invalid)
72 *invalid = TRUE; /* A limm operand, it should be extracted in a
73 different way. */
74
75 return value;
76 }
77
78 static unsigned long long
79 insert_rad (unsigned long long insn,
80 long long int value,
81 const char **errmsg ATTRIBUTE_UNUSED)
82 {
83 if (value & 0x01)
84 *errmsg = _("cannot use odd number destination register");
85 if (value == 60)
86 *errmsg = _("LP_COUNT register cannot be used as destination register");
87
88 return insn | (value & 0x3F);
89 }
90
91 static unsigned long long
92 insert_rcd (unsigned long long insn,
93 long long int value,
94 const char **errmsg ATTRIBUTE_UNUSED)
95 {
96 if (value & 0x01)
97 *errmsg = _("cannot use odd number source register");
98
99 return insn | ((value & 0x3F) << 6);
100 }
101
102 /* Dummy insert ZERO operand function. */
103
104 static unsigned long long
105 insert_za (unsigned long long insn,
106 long long int value,
107 const char **errmsg)
108 {
109 if (value)
110 *errmsg = _("operand is not zero");
111 return insn;
112 }
113
114 /* Insert Y-bit in bbit/br instructions. This function is called only
115 when solving fixups. */
116
117 static unsigned long long
118 insert_Ybit (unsigned long long insn,
119 long long int value,
120 const char **errmsg ATTRIBUTE_UNUSED)
121 {
122 if (value > 0)
123 insn |= 0x08;
124
125 return insn;
126 }
127
128 /* Insert Y-bit in bbit/br instructions. This function is called only
129 when solving fixups. */
130
131 static unsigned long long
132 insert_NYbit (unsigned long long insn,
133 long long int value,
134 const char **errmsg ATTRIBUTE_UNUSED)
135 {
136 if (value < 0)
137 insn |= 0x08;
138
139 return insn;
140 }
141
142 /* Insert H register into a 16-bit opcode. */
143
144 static unsigned long long
145 insert_rhv1 (unsigned long long insn,
146 long long int value,
147 const char **errmsg ATTRIBUTE_UNUSED)
148 {
149 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
150 }
151
152 static long long int
153 extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED,
154 bfd_boolean * invalid ATTRIBUTE_UNUSED)
155 {
156 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
157
158 return value;
159 }
160
161 /* Insert H register into a 16-bit opcode. */
162
163 static unsigned long long
164 insert_rhv2 (unsigned long long insn,
165 long long int value,
166 const char **errmsg)
167 {
168 if (value == 0x1E)
169 *errmsg =
170 _("Register R30 is a limm indicator");
171 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
172 }
173
174 static long long int
175 extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED,
176 bfd_boolean * invalid ATTRIBUTE_UNUSED)
177 {
178 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
179
180 return value;
181 }
182
183 static unsigned long long
184 insert_r0 (unsigned long long insn,
185 long long int value,
186 const char **errmsg ATTRIBUTE_UNUSED)
187 {
188 if (value != 0)
189 *errmsg = _("Register must be R0");
190 return insn;
191 }
192
193 static long long int
194 extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
195 bfd_boolean * invalid ATTRIBUTE_UNUSED)
196 {
197 return 0;
198 }
199
200
201 static unsigned long long
202 insert_r1 (unsigned long long insn,
203 long long int value,
204 const char **errmsg ATTRIBUTE_UNUSED)
205 {
206 if (value != 1)
207 *errmsg = _("Register must be R1");
208 return insn;
209 }
210
211 static long long int
212 extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
213 bfd_boolean * invalid ATTRIBUTE_UNUSED)
214 {
215 return 1;
216 }
217
218 static unsigned long long
219 insert_r2 (unsigned long long insn,
220 long long int value,
221 const char **errmsg ATTRIBUTE_UNUSED)
222 {
223 if (value != 2)
224 *errmsg = _("Register must be R2");
225 return insn;
226 }
227
228 static long long int
229 extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
230 bfd_boolean * invalid ATTRIBUTE_UNUSED)
231 {
232 return 2;
233 }
234
235 static unsigned long long
236 insert_r3 (unsigned long long insn,
237 long long int value,
238 const char **errmsg ATTRIBUTE_UNUSED)
239 {
240 if (value != 3)
241 *errmsg = _("Register must be R3");
242 return insn;
243 }
244
245 static long long int
246 extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
247 bfd_boolean * invalid ATTRIBUTE_UNUSED)
248 {
249 return 3;
250 }
251
252 static unsigned long long
253 insert_sp (unsigned long long insn,
254 long long int value,
255 const char **errmsg ATTRIBUTE_UNUSED)
256 {
257 if (value != 28)
258 *errmsg = _("Register must be SP");
259 return insn;
260 }
261
262 static long long int
263 extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
264 bfd_boolean * invalid ATTRIBUTE_UNUSED)
265 {
266 return 28;
267 }
268
269 static unsigned long long
270 insert_gp (unsigned long long insn,
271 long long int value,
272 const char **errmsg ATTRIBUTE_UNUSED)
273 {
274 if (value != 26)
275 *errmsg = _("Register must be GP");
276 return insn;
277 }
278
279 static long long int
280 extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
281 bfd_boolean * invalid ATTRIBUTE_UNUSED)
282 {
283 return 26;
284 }
285
286 static unsigned long long
287 insert_pcl (unsigned long long insn,
288 long long int value,
289 const char **errmsg ATTRIBUTE_UNUSED)
290 {
291 if (value != 63)
292 *errmsg = _("Register must be PCL");
293 return insn;
294 }
295
296 static long long int
297 extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
298 bfd_boolean * invalid ATTRIBUTE_UNUSED)
299 {
300 return 63;
301 }
302
303 static unsigned long long
304 insert_blink (unsigned long long insn,
305 long long int value,
306 const char **errmsg ATTRIBUTE_UNUSED)
307 {
308 if (value != 31)
309 *errmsg = _("Register must be BLINK");
310 return insn;
311 }
312
313 static long long int
314 extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
315 bfd_boolean * invalid ATTRIBUTE_UNUSED)
316 {
317 return 31;
318 }
319
320 static unsigned long long
321 insert_ilink1 (unsigned long long insn,
322 long long int value,
323 const char **errmsg ATTRIBUTE_UNUSED)
324 {
325 if (value != 29)
326 *errmsg = _("Register must be ILINK1");
327 return insn;
328 }
329
330 static long long int
331 extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
332 bfd_boolean * invalid ATTRIBUTE_UNUSED)
333 {
334 return 29;
335 }
336
337 static unsigned long long
338 insert_ilink2 (unsigned long long insn,
339 long long int value,
340 const char **errmsg ATTRIBUTE_UNUSED)
341 {
342 if (value != 30)
343 *errmsg = _("Register must be ILINK2");
344 return insn;
345 }
346
347 static long long int
348 extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
349 bfd_boolean * invalid ATTRIBUTE_UNUSED)
350 {
351 return 30;
352 }
353
354 static unsigned long long
355 insert_ras (unsigned long long insn,
356 long long int value,
357 const char **errmsg ATTRIBUTE_UNUSED)
358 {
359 switch (value)
360 {
361 case 0:
362 case 1:
363 case 2:
364 case 3:
365 insn |= value;
366 break;
367 case 12:
368 case 13:
369 case 14:
370 case 15:
371 insn |= (value - 8);
372 break;
373 default:
374 *errmsg = _("Register must be either r0-r3 or r12-r15");
375 break;
376 }
377 return insn;
378 }
379
380 static long long int
381 extract_ras (unsigned long long insn ATTRIBUTE_UNUSED,
382 bfd_boolean * invalid ATTRIBUTE_UNUSED)
383 {
384 int value = insn & 0x07;
385 if (value > 3)
386 return (value + 8);
387 else
388 return value;
389 }
390
391 static unsigned long long
392 insert_rbs (unsigned long long insn,
393 long long int value,
394 const char **errmsg ATTRIBUTE_UNUSED)
395 {
396 switch (value)
397 {
398 case 0:
399 case 1:
400 case 2:
401 case 3:
402 insn |= value << 8;
403 break;
404 case 12:
405 case 13:
406 case 14:
407 case 15:
408 insn |= ((value - 8)) << 8;
409 break;
410 default:
411 *errmsg = _("Register must be either r0-r3 or r12-r15");
412 break;
413 }
414 return insn;
415 }
416
417 static long long int
418 extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED,
419 bfd_boolean * invalid ATTRIBUTE_UNUSED)
420 {
421 int value = (insn >> 8) & 0x07;
422 if (value > 3)
423 return (value + 8);
424 else
425 return value;
426 }
427
428 static unsigned long long
429 insert_rcs (unsigned long long insn,
430 long long int value,
431 const char **errmsg ATTRIBUTE_UNUSED)
432 {
433 switch (value)
434 {
435 case 0:
436 case 1:
437 case 2:
438 case 3:
439 insn |= value << 5;
440 break;
441 case 12:
442 case 13:
443 case 14:
444 case 15:
445 insn |= ((value - 8)) << 5;
446 break;
447 default:
448 *errmsg = _("Register must be either r0-r3 or r12-r15");
449 break;
450 }
451 return insn;
452 }
453
454 static long long int
455 extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED,
456 bfd_boolean * invalid ATTRIBUTE_UNUSED)
457 {
458 int value = (insn >> 5) & 0x07;
459 if (value > 3)
460 return (value + 8);
461 else
462 return value;
463 }
464
465 static unsigned long long
466 insert_simm3s (unsigned long long insn,
467 long long int value,
468 const char **errmsg ATTRIBUTE_UNUSED)
469 {
470 int tmp = 0;
471 switch (value)
472 {
473 case -1:
474 tmp = 0x07;
475 break;
476 case 0:
477 tmp = 0x00;
478 break;
479 case 1:
480 tmp = 0x01;
481 break;
482 case 2:
483 tmp = 0x02;
484 break;
485 case 3:
486 tmp = 0x03;
487 break;
488 case 4:
489 tmp = 0x04;
490 break;
491 case 5:
492 tmp = 0x05;
493 break;
494 case 6:
495 tmp = 0x06;
496 break;
497 default:
498 *errmsg = _("Accepted values are from -1 to 6");
499 break;
500 }
501
502 insn |= tmp << 8;
503 return insn;
504 }
505
506 static long long int
507 extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED,
508 bfd_boolean * invalid ATTRIBUTE_UNUSED)
509 {
510 int value = (insn >> 8) & 0x07;
511 if (value == 7)
512 return -1;
513 else
514 return value;
515 }
516
517 static unsigned long long
518 insert_rrange (unsigned long long insn,
519 long long int value,
520 const char **errmsg ATTRIBUTE_UNUSED)
521 {
522 int reg1 = (value >> 16) & 0xFFFF;
523 int reg2 = value & 0xFFFF;
524 if (reg1 != 13)
525 {
526 *errmsg = _("First register of the range should be r13");
527 return insn;
528 }
529 if (reg2 < 13 || reg2 > 26)
530 {
531 *errmsg = _("Last register of the range doesn't fit");
532 return insn;
533 }
534 insn |= ((reg2 - 12) & 0x0F) << 1;
535 return insn;
536 }
537
538 static long long int
539 extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED,
540 bfd_boolean * invalid ATTRIBUTE_UNUSED)
541 {
542 return (insn >> 1) & 0x0F;
543 }
544
545 static unsigned long long
546 insert_fpel (unsigned long long insn,
547 long long int value,
548 const char **errmsg ATTRIBUTE_UNUSED)
549 {
550 if (value != 27)
551 {
552 *errmsg = _("Invalid register number, should be fp");
553 return insn;
554 }
555
556 insn |= 0x0100;
557 return insn;
558 }
559
560 static long long int
561 extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED,
562 bfd_boolean * invalid ATTRIBUTE_UNUSED)
563 {
564 return (insn & 0x0100) ? 27 : -1;
565 }
566
567 static unsigned long long
568 insert_blinkel (unsigned long long insn,
569 long long int value,
570 const char **errmsg ATTRIBUTE_UNUSED)
571 {
572 if (value != 31)
573 {
574 *errmsg = _("Invalid register number, should be blink");
575 return insn;
576 }
577
578 insn |= 0x0200;
579 return insn;
580 }
581
582 static long long int
583 extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED,
584 bfd_boolean * invalid ATTRIBUTE_UNUSED)
585 {
586 return (insn & 0x0200) ? 31 : -1;
587 }
588
589 static unsigned long long
590 insert_pclel (unsigned long long insn,
591 long long int value,
592 const char **errmsg ATTRIBUTE_UNUSED)
593 {
594 if (value != 63)
595 {
596 *errmsg = _("Invalid register number, should be pcl");
597 return insn;
598 }
599
600 insn |= 0x0400;
601 return insn;
602 }
603
604 static long long int
605 extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED,
606 bfd_boolean * invalid ATTRIBUTE_UNUSED)
607 {
608 return (insn & 0x0400) ? 63 : -1;
609 }
610
611 #define INSERT_W6
612 /* mask = 00000000000000000000111111000000
613 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
614 static unsigned long long
615 insert_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
616 long long int value ATTRIBUTE_UNUSED,
617 const char **errmsg ATTRIBUTE_UNUSED)
618 {
619 insn |= ((value >> 0) & 0x003f) << 6;
620
621 return insn;
622 }
623
624 #define EXTRACT_W6
625 /* mask = 00000000000000000000111111000000. */
626 static long long int
627 extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
628 bfd_boolean * invalid ATTRIBUTE_UNUSED)
629 {
630 unsigned value = 0;
631
632 value |= ((insn >> 6) & 0x003f) << 0;
633
634 return value;
635 }
636
637 #define INSERT_G_S
638 /* mask = 0000011100022000
639 insn = 01000ggghhhGG0HH. */
640 static unsigned long long
641 insert_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
642 long long int value ATTRIBUTE_UNUSED,
643 const char **errmsg ATTRIBUTE_UNUSED)
644 {
645 insn |= ((value >> 0) & 0x0007) << 8;
646 insn |= ((value >> 3) & 0x0003) << 3;
647
648 return insn;
649 }
650
651 #define EXTRACT_G_S
652 /* mask = 0000011100022000. */
653 static long long int
654 extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
655 bfd_boolean * invalid ATTRIBUTE_UNUSED)
656 {
657 int value = 0;
658
659 value |= ((insn >> 8) & 0x0007) << 0;
660 value |= ((insn >> 3) & 0x0003) << 3;
661
662 /* Extend the sign. */
663 int signbit = 1 << (6 - 1);
664 value = (value ^ signbit) - signbit;
665
666 return value;
667 }
668
669 /* ARC NPS400 Support: See comment near head of file. */
670 #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
671 static unsigned long long \
672 insert_nps_3bit_reg_at_##OFFSET##_##NAME \
673 (unsigned long long insn ATTRIBUTE_UNUSED, \
674 long long int value ATTRIBUTE_UNUSED, \
675 const char **errmsg ATTRIBUTE_UNUSED) \
676 { \
677 switch (value) \
678 { \
679 case 0: \
680 case 1: \
681 case 2: \
682 case 3: \
683 insn |= value << (OFFSET); \
684 break; \
685 case 12: \
686 case 13: \
687 case 14: \
688 case 15: \
689 insn |= (value - 8) << (OFFSET); \
690 break; \
691 default: \
692 *errmsg = _("Register must be either r0-r3 or r12-r15"); \
693 break; \
694 } \
695 return insn; \
696 } \
697 \
698 static long long int \
699 extract_nps_3bit_reg_at_##OFFSET##_##NAME \
700 (unsigned long long insn ATTRIBUTE_UNUSED, \
701 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
702 { \
703 int value = (insn >> (OFFSET)) & 0x07; \
704 if (value > 3) \
705 value += 8; \
706 return value; \
707 } \
708
709 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
710 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
711 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
712 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
713
714 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
715 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
716 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
717 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
718
719 static unsigned long long
720 insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
721 long long int value ATTRIBUTE_UNUSED,
722 const char **errmsg ATTRIBUTE_UNUSED)
723 {
724 switch (value)
725 {
726 case 1:
727 value = 0;
728 break;
729 case 2:
730 value = 1;
731 break;
732 case 4:
733 value = 2;
734 break;
735 case 8:
736 value = 3;
737 break;
738 default:
739 value = 0;
740 *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
741 break;
742 }
743
744 insn |= value << 10;
745 return insn;
746 }
747
748 static long long int
749 extract_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
750 bfd_boolean * invalid ATTRIBUTE_UNUSED)
751 {
752 return 1 << ((insn >> 10) & 0x3);
753 }
754
755 static unsigned long long
756 insert_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
757 long long int value ATTRIBUTE_UNUSED,
758 const char **errmsg ATTRIBUTE_UNUSED)
759 {
760 insn |= ((value >> 5) & 7) << 12;
761 insn |= (value & 0x1f);
762 return insn;
763 }
764
765 static long long int
766 extract_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
767 bfd_boolean * invalid ATTRIBUTE_UNUSED)
768 {
769 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
770 }
771
772 static unsigned long long
773 insert_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
774 long long int value ATTRIBUTE_UNUSED,
775 const char **errmsg ATTRIBUTE_UNUSED)
776 {
777 switch (value)
778 {
779 case 1:
780 case 2:
781 case 4:
782 break;
783
784 default:
785 *errmsg = _("invalid immediate, must be 1, 2, or 4");
786 value = 0;
787 }
788
789 insn |= (value << 6);
790 return insn;
791 }
792
793 static long long int
794 extract_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
795 bfd_boolean * invalid ATTRIBUTE_UNUSED)
796 {
797 return (insn >> 6) & 0x3f;
798 }
799
800 static unsigned long long
801 insert_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
802 long long int value ATTRIBUTE_UNUSED,
803 const char **errmsg ATTRIBUTE_UNUSED)
804 {
805 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
806 return insn;
807 }
808
809 static long long int
810 extract_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
811 bfd_boolean * invalid ATTRIBUTE_UNUSED)
812 {
813 return (insn & 0x1f);
814 }
815
816 static unsigned long long
817 insert_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
818 long long int value ATTRIBUTE_UNUSED,
819 const char **errmsg ATTRIBUTE_UNUSED)
820 {
821 int top = (value >> 16) & 0xffff;
822 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
823 *errmsg = _("invalid value for CMEM ld/st immediate");
824 insn |= (value & 0xffff);
825 return insn;
826 }
827
828 static long long int
829 extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
830 bfd_boolean * invalid ATTRIBUTE_UNUSED)
831 {
832 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
833 }
834
835 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
836 static unsigned long long \
837 insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
838 long long int value ATTRIBUTE_UNUSED, \
839 const char **errmsg ATTRIBUTE_UNUSED) \
840 { \
841 switch (value) \
842 { \
843 case 0: \
844 case 8: \
845 case 16: \
846 case 24: \
847 value = value / 8; \
848 break; \
849 default: \
850 *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
851 value = 0; \
852 } \
853 insn |= (value << SHIFT); \
854 return insn; \
855 } \
856 \
857 static long long int \
858 extract_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
859 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
860 { \
861 return ((insn >> SHIFT) & 0x3) * 8; \
862 }
863
864 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
865 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
866
867 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
868 static unsigned long long \
869 insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
870 long long int value ATTRIBUTE_UNUSED, \
871 const char **errmsg ATTRIBUTE_UNUSED) \
872 { \
873 if (value < LOWER || value > UPPER) \
874 { \
875 *errmsg = _("Invalid size, value must be " \
876 #LOWER " to " #UPPER "."); \
877 return insn; \
878 } \
879 value -= BIAS; \
880 insn |= (value << SHIFT); \
881 return insn; \
882 } \
883 \
884 static long long int \
885 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
886 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
887 { \
888 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
889 }
890
891 MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
892 MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
893 MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
894 MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
895 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
896 MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
897 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
898 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
899 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
900 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
901 MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
902
903 static long long int
904 extract_nps_qcmp_m3 (unsigned long long insn ATTRIBUTE_UNUSED,
905 bfd_boolean * invalid ATTRIBUTE_UNUSED)
906 {
907 int m3 = (insn >> 5) & 0xf;
908 if (m3 == 0xf)
909 *invalid = TRUE;
910 return m3;
911 }
912
913 static long long int
914 extract_nps_qcmp_m2 (unsigned long long insn ATTRIBUTE_UNUSED,
915 bfd_boolean * invalid ATTRIBUTE_UNUSED)
916 {
917 bfd_boolean tmp_invalid = FALSE;
918 int m2 = (insn >> 15) & 0x1;
919 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
920
921 if (m2 == 0 && m3 == 0xf)
922 *invalid = TRUE;
923 return m2;
924 }
925
926 static long long int
927 extract_nps_qcmp_m1 (unsigned long long insn ATTRIBUTE_UNUSED,
928 bfd_boolean * invalid ATTRIBUTE_UNUSED)
929 {
930 bfd_boolean tmp_invalid = FALSE;
931 int m1 = (insn >> 14) & 0x1;
932 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
933 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
934
935 if (m1 == 0 && m2 == 0 && m3 == 0xf)
936 *invalid = TRUE;
937 return m1;
938 }
939
940 static unsigned long long
941 insert_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
942 long long int value ATTRIBUTE_UNUSED,
943 const char **errmsg ATTRIBUTE_UNUSED)
944 {
945 unsigned pwr;
946
947 if (value < 1 || value > 256)
948 {
949 *errmsg = _("value out of range 1 - 256");
950 return 0;
951 }
952
953 for (pwr = 0; (value & 1) == 0; value >>= 1)
954 ++pwr;
955
956 if (value != 1)
957 {
958 *errmsg = _("value must be power of 2");
959 return 0;
960 }
961
962 return insn | (pwr << 8);
963 }
964
965 static long long int
966 extract_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
967 bfd_boolean * invalid ATTRIBUTE_UNUSED)
968 {
969 unsigned entry_size = (insn >> 8) & 0xf;
970 return 1 << entry_size;
971 }
972
973 static unsigned long long
974 insert_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
975 long long int value ATTRIBUTE_UNUSED,
976 const char **errmsg ATTRIBUTE_UNUSED)
977 {
978 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
979 }
980
981 static long long int
982 extract_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
983 bfd_boolean * invalid ATTRIBUTE_UNUSED)
984 {
985 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
986 }
987
988 static unsigned long long
989 insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
990 long long int value ATTRIBUTE_UNUSED,
991 const char **errmsg ATTRIBUTE_UNUSED)
992 {
993 return insn | (value << 42) | (value << 37);
994 }
995
996 static long long int
997 extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
998 bfd_boolean * invalid ATTRIBUTE_UNUSED)
999 {
1000 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
1001 *invalid = TRUE;
1002 return ((insn >> 37) & 0x1f);
1003 }
1004
1005 static unsigned long long
1006 insert_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
1007 long long int value ATTRIBUTE_UNUSED,
1008 const char **errmsg ATTRIBUTE_UNUSED)
1009 {
1010 if (value < 0 || value > 28)
1011 *errmsg = _("Value must be in the range 0 to 28");
1012 return insn | (value << 20);
1013 }
1014
1015 static long long int
1016 extract_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
1017 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1018 {
1019 int value = (insn >> 20) & 0x1f;
1020 if (value > 28)
1021 *invalid = TRUE;
1022 return value;
1023 }
1024
1025 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1026 static unsigned long long \
1027 insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1028 long long int value ATTRIBUTE_UNUSED, \
1029 const char **errmsg ATTRIBUTE_UNUSED) \
1030 { \
1031 if (value < 1 || value > UPPER) \
1032 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1033 if (value == UPPER) \
1034 value = 0; \
1035 return insn | (value << SHIFT); \
1036 } \
1037 \
1038 static long long int \
1039 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1040 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1041 { \
1042 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1043 if (value == 0) \
1044 value = UPPER; \
1045 return value; \
1046 }
1047
1048 MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1049 MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1050 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1051 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1052 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1053 MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
1054 MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
1055
1056 static unsigned long long
1057 insert_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
1058 long long int value ATTRIBUTE_UNUSED,
1059 const char **errmsg ATTRIBUTE_UNUSED)
1060 {
1061 if (value < 0 || value > 240)
1062 *errmsg = _("Value must be in the range 0 to 240");
1063 if ((value % 16) != 0)
1064 *errmsg = _("Value must be a multiple of 16");
1065 value = value / 16;
1066 return insn | (value << 6);
1067 }
1068
1069 static long long int
1070 extract_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
1071 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1072 {
1073 int value = (insn >> 6) & 0xF;
1074 return value * 16;
1075 }
1076
1077 #define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
1078 static unsigned long long \
1079 insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1080 long long int value ATTRIBUTE_UNUSED, \
1081 const char **errmsg ATTRIBUTE_UNUSED) \
1082 { \
1083 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1084 *errmsg = _("Invalid address type for operand"); \
1085 return insn; \
1086 } \
1087 \
1088 static long long int \
1089 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1090 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1091 { \
1092 return ARC_NPS400_ADDRTYPE_##VALUE; \
1093 }
1094
1095 MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1096 MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1097 MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1098 MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1099 MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1100 MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1101 MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1102 MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1103 MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1104 MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1105 MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1106 MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1107 MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1108 MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1109 MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1110 MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1111
1112 static unsigned long long
1113 insert_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
1114 long long int value ATTRIBUTE_UNUSED,
1115 const char **errmsg ATTRIBUTE_UNUSED)
1116 {
1117 if (value < 0 || value > 31)
1118 *errmsg = _("Value must be in the range 0 to 31");
1119 return insn | (value << 43) | (value << 48);
1120 }
1121
1122
1123 static long long int
1124 extract_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
1125 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1126 {
1127 int value1 = (insn >> 43) & 0x1F;
1128 int value2 = (insn >> 48) & 0x1F;
1129
1130 if (value1 != value2)
1131 *invalid = TRUE;
1132
1133 return value1;
1134 }
1135
1136 /* Include the generic extract/insert functions. Order is important
1137 as some of the functions present in the .h may be disabled via
1138 defines. */
1139 #include "arc-fxi.h"
1140
1141 /* The flag operands table.
1142
1143 The format of the table is
1144 NAME CODE BITS SHIFT FAVAIL. */
1145 const struct arc_flag_operand arc_flag_operands[] =
1146 {
1147 #define F_NULL 0
1148 { 0, 0, 0, 0, 0},
1149 #define F_ALWAYS (F_NULL + 1)
1150 { "al", 0, 0, 0, 0 },
1151 #define F_RA (F_ALWAYS + 1)
1152 { "ra", 0, 0, 0, 0 },
1153 #define F_EQUAL (F_RA + 1)
1154 { "eq", 1, 5, 0, 1 },
1155 #define F_ZERO (F_EQUAL + 1)
1156 { "z", 1, 5, 0, 0 },
1157 #define F_NOTEQUAL (F_ZERO + 1)
1158 { "ne", 2, 5, 0, 1 },
1159 #define F_NOTZERO (F_NOTEQUAL + 1)
1160 { "nz", 2, 5, 0, 0 },
1161 #define F_POZITIVE (F_NOTZERO + 1)
1162 { "p", 3, 5, 0, 1 },
1163 #define F_PL (F_POZITIVE + 1)
1164 { "pl", 3, 5, 0, 0 },
1165 #define F_NEGATIVE (F_PL + 1)
1166 { "n", 4, 5, 0, 1 },
1167 #define F_MINUS (F_NEGATIVE + 1)
1168 { "mi", 4, 5, 0, 0 },
1169 #define F_CARRY (F_MINUS + 1)
1170 { "c", 5, 5, 0, 1 },
1171 #define F_CARRYSET (F_CARRY + 1)
1172 { "cs", 5, 5, 0, 0 },
1173 #define F_LOWER (F_CARRYSET + 1)
1174 { "lo", 5, 5, 0, 0 },
1175 #define F_CARRYCLR (F_LOWER + 1)
1176 { "cc", 6, 5, 0, 0 },
1177 #define F_NOTCARRY (F_CARRYCLR + 1)
1178 { "nc", 6, 5, 0, 1 },
1179 #define F_HIGHER (F_NOTCARRY + 1)
1180 { "hs", 6, 5, 0, 0 },
1181 #define F_OVERFLOWSET (F_HIGHER + 1)
1182 { "vs", 7, 5, 0, 0 },
1183 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1184 { "v", 7, 5, 0, 1 },
1185 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1186 { "nv", 8, 5, 0, 1 },
1187 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1188 { "vc", 8, 5, 0, 0 },
1189 #define F_GT (F_OVERFLOWCLR + 1)
1190 { "gt", 9, 5, 0, 1 },
1191 #define F_GE (F_GT + 1)
1192 { "ge", 10, 5, 0, 1 },
1193 #define F_LT (F_GE + 1)
1194 { "lt", 11, 5, 0, 1 },
1195 #define F_LE (F_LT + 1)
1196 { "le", 12, 5, 0, 1 },
1197 #define F_HI (F_LE + 1)
1198 { "hi", 13, 5, 0, 1 },
1199 #define F_LS (F_HI + 1)
1200 { "ls", 14, 5, 0, 1 },
1201 #define F_PNZ (F_LS + 1)
1202 { "pnz", 15, 5, 0, 1 },
1203
1204 /* FLAG. */
1205 #define F_FLAG (F_PNZ + 1)
1206 { "f", 1, 1, 15, 1 },
1207 #define F_FFAKE (F_FLAG + 1)
1208 { "f", 0, 0, 0, 1 },
1209
1210 /* Delay slot. */
1211 #define F_ND (F_FFAKE + 1)
1212 { "nd", 0, 1, 5, 0 },
1213 #define F_D (F_ND + 1)
1214 { "d", 1, 1, 5, 1 },
1215 #define F_DFAKE (F_D + 1)
1216 { "d", 0, 0, 0, 1 },
1217 #define F_DNZ_ND (F_DFAKE + 1)
1218 { "nd", 0, 1, 16, 0 },
1219 #define F_DNZ_D (F_DNZ_ND + 1)
1220 { "d", 1, 1, 16, 1 },
1221
1222 /* Data size. */
1223 #define F_SIZEB1 (F_DNZ_D + 1)
1224 { "b", 1, 2, 1, 1 },
1225 #define F_SIZEB7 (F_SIZEB1 + 1)
1226 { "b", 1, 2, 7, 1 },
1227 #define F_SIZEB17 (F_SIZEB7 + 1)
1228 { "b", 1, 2, 17, 1 },
1229 #define F_SIZEW1 (F_SIZEB17 + 1)
1230 { "w", 2, 2, 1, 0 },
1231 #define F_SIZEW7 (F_SIZEW1 + 1)
1232 { "w", 2, 2, 7, 0 },
1233 #define F_SIZEW17 (F_SIZEW7 + 1)
1234 { "w", 2, 2, 17, 0 },
1235
1236 /* Sign extension. */
1237 #define F_SIGN6 (F_SIZEW17 + 1)
1238 { "x", 1, 1, 6, 1 },
1239 #define F_SIGN16 (F_SIGN6 + 1)
1240 { "x", 1, 1, 16, 1 },
1241 #define F_SIGNX (F_SIGN16 + 1)
1242 { "x", 0, 0, 0, 1 },
1243
1244 /* Address write-back modes. */
1245 #define F_A3 (F_SIGNX + 1)
1246 { "a", 1, 2, 3, 0 },
1247 #define F_A9 (F_A3 + 1)
1248 { "a", 1, 2, 9, 0 },
1249 #define F_A22 (F_A9 + 1)
1250 { "a", 1, 2, 22, 0 },
1251 #define F_AW3 (F_A22 + 1)
1252 { "aw", 1, 2, 3, 1 },
1253 #define F_AW9 (F_AW3 + 1)
1254 { "aw", 1, 2, 9, 1 },
1255 #define F_AW22 (F_AW9 + 1)
1256 { "aw", 1, 2, 22, 1 },
1257 #define F_AB3 (F_AW22 + 1)
1258 { "ab", 2, 2, 3, 1 },
1259 #define F_AB9 (F_AB3 + 1)
1260 { "ab", 2, 2, 9, 1 },
1261 #define F_AB22 (F_AB9 + 1)
1262 { "ab", 2, 2, 22, 1 },
1263 #define F_AS3 (F_AB22 + 1)
1264 { "as", 3, 2, 3, 1 },
1265 #define F_AS9 (F_AS3 + 1)
1266 { "as", 3, 2, 9, 1 },
1267 #define F_AS22 (F_AS9 + 1)
1268 { "as", 3, 2, 22, 1 },
1269 #define F_ASFAKE (F_AS22 + 1)
1270 { "as", 0, 0, 0, 1 },
1271
1272 /* Cache bypass. */
1273 #define F_DI5 (F_ASFAKE + 1)
1274 { "di", 1, 1, 5, 1 },
1275 #define F_DI11 (F_DI5 + 1)
1276 { "di", 1, 1, 11, 1 },
1277 #define F_DI14 (F_DI11 + 1)
1278 { "di", 1, 1, 14, 1 },
1279 #define F_DI15 (F_DI14 + 1)
1280 { "di", 1, 1, 15, 1 },
1281
1282 /* ARCv2 specific. */
1283 #define F_NT (F_DI15 + 1)
1284 { "nt", 0, 1, 3, 1},
1285 #define F_T (F_NT + 1)
1286 { "t", 1, 1, 3, 1},
1287 #define F_H1 (F_T + 1)
1288 { "h", 2, 2, 1, 1 },
1289 #define F_H7 (F_H1 + 1)
1290 { "h", 2, 2, 7, 1 },
1291 #define F_H17 (F_H7 + 1)
1292 { "h", 2, 2, 17, 1 },
1293 #define F_SIZED (F_H17 + 1)
1294 { "dd", 8, 0, 0, 0 }, /* Fake. */
1295
1296 /* Fake Flags. */
1297 #define F_NE (F_SIZED + 1)
1298 { "ne", 0, 0, 0, 1 },
1299
1300 /* ARC NPS400 Support: See comment near head of file. */
1301 #define F_NPS_CL (F_NE + 1)
1302 { "cl", 0, 0, 0, 1 },
1303
1304 #define F_NPS_FLAG (F_NPS_CL + 1)
1305 { "f", 1, 1, 20, 1 },
1306
1307 #define F_NPS_R (F_NPS_FLAG + 1)
1308 { "r", 1, 1, 15, 1 },
1309
1310 #define F_NPS_RW (F_NPS_R + 1)
1311 { "rw", 0, 1, 7, 1 },
1312
1313 #define F_NPS_RD (F_NPS_RW + 1)
1314 { "rd", 1, 1, 7, 1 },
1315
1316 #define F_NPS_WFT (F_NPS_RD + 1)
1317 { "wft", 0, 0, 0, 1 },
1318
1319 #define F_NPS_IE1 (F_NPS_WFT + 1)
1320 { "ie1", 1, 2, 8, 1 },
1321
1322 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1323 { "ie2", 2, 2, 8, 1 },
1324
1325 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1326 { "ie12", 3, 2, 8, 1 },
1327
1328 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1329 { "rd", 0, 1, 6, 1 },
1330
1331 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1332 { "wr", 1, 1, 6, 1 },
1333
1334 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1335 { "off", 0, 0, 0, 1 },
1336
1337 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1338 { "restore", 0, 0, 0, 1 },
1339
1340 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1341 { "sx", 1, 1, 14, 1 },
1342
1343 #define F_NPS_AR (F_NPS_SX + 1)
1344 { "ar", 0, 1, 0, 1 },
1345
1346 #define F_NPS_AL (F_NPS_AR + 1)
1347 { "al", 1, 1, 0, 1 },
1348
1349 #define F_NPS_S (F_NPS_AL + 1)
1350 { "s", 0, 0, 0, 1 },
1351
1352 #define F_NPS_ZNCV_RD (F_NPS_S + 1)
1353 { "rd", 0, 1, 15, 1 },
1354
1355 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1356 { "wr", 1, 1, 15, 1 },
1357
1358 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1359 { "p0", 0, 0, 0, 1 },
1360
1361 #define F_NPS_P1 (F_NPS_P0 + 1)
1362 { "p1", 0, 0, 0, 1 },
1363
1364 #define F_NPS_P2 (F_NPS_P1 + 1)
1365 { "p2", 0, 0, 0, 1 },
1366
1367 #define F_NPS_P3 (F_NPS_P2 + 1)
1368 { "p3", 0, 0, 0, 1 },
1369
1370 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1371 { "di", 0, 0, 0, 1 },
1372
1373 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1374 { "cl", 1, 1, 6, 1 },
1375
1376 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1377 { "cl", 1, 1, 16, 1 },
1378
1379 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1380 { "x2", 1, 2, 9, 1 },
1381
1382 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1383 { "x2", 1, 2, 22, 1 },
1384
1385 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1386 { "x4", 2, 2, 9, 1 },
1387
1388 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1389 { "x4", 2, 2, 22, 1 },
1390 };
1391
1392 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1393
1394 /* Table of the flag classes.
1395
1396 The format of the table is
1397 CLASS {FLAG_CODE}. */
1398 const struct arc_flag_class arc_flag_classes[] =
1399 {
1400 #define C_EMPTY 0
1401 { F_CLASS_NONE, { F_NULL } },
1402
1403 #define C_CC_EQ (C_EMPTY + 1)
1404 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1405
1406 #define C_CC_GE (C_CC_EQ + 1)
1407 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1408
1409 #define C_CC_GT (C_CC_GE + 1)
1410 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1411
1412 #define C_CC_HI (C_CC_GT + 1)
1413 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1414
1415 #define C_CC_HS (C_CC_HI + 1)
1416 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1417
1418 #define C_CC_LE (C_CC_HS + 1)
1419 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1420
1421 #define C_CC_LO (C_CC_LE + 1)
1422 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1423
1424 #define C_CC_LS (C_CC_LO + 1)
1425 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1426
1427 #define C_CC_LT (C_CC_LS + 1)
1428 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1429
1430 #define C_CC_NE (C_CC_LT + 1)
1431 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1432
1433 #define C_AA_AB (C_CC_NE + 1)
1434 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1435
1436 #define C_AA_AW (C_AA_AB + 1)
1437 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1438
1439 #define C_ZZ_D (C_AA_AW + 1)
1440 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1441
1442 #define C_ZZ_H (C_ZZ_D + 1)
1443 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1444
1445 #define C_ZZ_B (C_ZZ_H + 1)
1446 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1447
1448 #define C_CC (C_ZZ_B + 1)
1449 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
1450 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1451 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1452 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1453 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1454 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1455 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1456
1457 #define C_AA_ADDR3 (C_CC + 1)
1458 #define C_AA27 (C_CC + 1)
1459 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1460 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1461 #define C_AA21 (C_AA_ADDR3 + 1)
1462 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1463 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1464 #define C_AA8 (C_AA_ADDR9 + 1)
1465 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1466
1467 #define C_F (C_AA_ADDR22 + 1)
1468 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1469 #define C_FHARD (C_F + 1)
1470 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1471
1472 #define C_T (C_FHARD + 1)
1473 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1474 #define C_D (C_T + 1)
1475 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1476 #define C_DNZ_D (C_D + 1)
1477 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
1478
1479 #define C_DHARD (C_DNZ_D + 1)
1480 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1481
1482 #define C_DI20 (C_DHARD + 1)
1483 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1484 #define C_DI14 (C_DI20 + 1)
1485 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1486 #define C_DI16 (C_DI14 + 1)
1487 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1488 #define C_DI26 (C_DI16 + 1)
1489 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1490
1491 #define C_X25 (C_DI26 + 1)
1492 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1493 #define C_X15 (C_X25 + 1)
1494 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1495 #define C_XHARD (C_X15 + 1)
1496 #define C_X (C_X15 + 1)
1497 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1498
1499 #define C_ZZ13 (C_X + 1)
1500 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1501 #define C_ZZ23 (C_ZZ13 + 1)
1502 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1503 #define C_ZZ29 (C_ZZ23 + 1)
1504 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1505
1506 #define C_AS (C_ZZ29 + 1)
1507 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1508
1509 #define C_NE (C_AS + 1)
1510 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1511
1512 /* ARC NPS400 Support: See comment near head of file. */
1513 #define C_NPS_CL (C_NE + 1)
1514 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1515
1516 #define C_NPS_F (C_NPS_CL + 1)
1517 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1518
1519 #define C_NPS_R (C_NPS_F + 1)
1520 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1521
1522 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1523 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1524
1525 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1526 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1527
1528 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1529 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1530
1531 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1532 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1533
1534 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1535 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1536
1537 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1538 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1539
1540 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1541 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1542
1543 #define C_NPS_AR_AL (C_NPS_SX + 1)
1544 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1545
1546 #define C_NPS_S (C_NPS_AR_AL + 1)
1547 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1548
1549 #define C_NPS_ZNCV (C_NPS_S + 1)
1550 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
1551
1552 #define C_NPS_P0 (C_NPS_ZNCV + 1)
1553 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1554
1555 #define C_NPS_P1 (C_NPS_P0 + 1)
1556 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1557
1558 #define C_NPS_P2 (C_NPS_P1 + 1)
1559 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1560
1561 #define C_NPS_P3 (C_NPS_P2 + 1)
1562 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
1563
1564 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1565 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1566
1567 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1568 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1569
1570 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1571 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1572
1573 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1574 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1575
1576 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1577 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
1578 };
1579
1580 const unsigned char flags_none[] = { 0 };
1581 const unsigned char flags_f[] = { C_F };
1582 const unsigned char flags_cc[] = { C_CC };
1583 const unsigned char flags_ccf[] = { C_CC, C_F };
1584
1585 /* The operands table.
1586
1587 The format of the operands table is:
1588
1589 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1590 const struct arc_operand arc_operands[] =
1591 {
1592 /* The fields are bits, shift, insert, extract, flags. The zero
1593 index is used to indicate end-of-list. */
1594 #define UNUSED 0
1595 { 0, 0, 0, 0, 0, 0 },
1596
1597 #define IGNORED (UNUSED + 1)
1598 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1599
1600 /* The plain integer register fields. Used by 32 bit
1601 instructions. */
1602 #define RA (IGNORED + 1)
1603 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1604 #define RA_CHK (RA + 1)
1605 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1606 #define RB (RA_CHK + 1)
1607 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1608 #define RB_CHK (RB + 1)
1609 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1610 #define RC (RB_CHK + 1)
1611 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1612 #define RBdup (RC + 1)
1613 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1614
1615 #define RAD (RBdup + 1)
1616 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1617 #define RCD (RAD + 1)
1618 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1619
1620 /* The plain integer register fields. Used by short
1621 instructions. */
1622 #define RA16 (RCD + 1)
1623 #define RA_S (RCD + 1)
1624 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1625 #define RB16 (RA16 + 1)
1626 #define RB_S (RA16 + 1)
1627 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1628 #define RB16dup (RB16 + 1)
1629 #define RB_Sdup (RB16 + 1)
1630 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1631 #define RC16 (RB16dup + 1)
1632 #define RC_S (RB16dup + 1)
1633 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1634 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1635 by V1 cpus. */
1636 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1637 #define R5H (R6H + 1) /* 5bit register field 'h' used
1638 by V2 cpus. */
1639 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1640 by V2 cpus. */
1641 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1642 #define R5Hdup (R5H + 1)
1643 #define RH_Sdup (R5H + 1)
1644 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1645 insert_rhv2, extract_rhv2 },
1646
1647 #define RG (R5Hdup + 1)
1648 #define G_S (R5Hdup + 1)
1649 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1650
1651 /* Fix registers. */
1652 #define R0 (RG + 1)
1653 #define R0_S (RG + 1)
1654 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1655 #define R1 (R0 + 1)
1656 #define R1_S (R0 + 1)
1657 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1658 #define R2 (R1 + 1)
1659 #define R2_S (R1 + 1)
1660 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1661 #define R3 (R2 + 1)
1662 #define R3_S (R2 + 1)
1663 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1664 #define RSP (R3 + 1)
1665 #define SP_S (R3 + 1)
1666 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1667 #define SPdup (RSP + 1)
1668 #define SP_Sdup (RSP + 1)
1669 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1670 #define GP (SPdup + 1)
1671 #define GP_S (SPdup + 1)
1672 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1673
1674 #define PCL_S (GP + 1)
1675 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1676
1677 #define BLINK (PCL_S + 1)
1678 #define BLINK_S (PCL_S + 1)
1679 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1680
1681 #define ILINK1 (BLINK + 1)
1682 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1683 #define ILINK2 (ILINK1 + 1)
1684 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1685
1686 /* Long immediate. */
1687 #define LIMM (ILINK2 + 1)
1688 #define LIMM_S (ILINK2 + 1)
1689 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1690 #define LIMMdup (LIMM + 1)
1691 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1692
1693 /* Special operands. */
1694 #define ZA (LIMMdup + 1)
1695 #define ZB (LIMMdup + 1)
1696 #define ZA_S (LIMMdup + 1)
1697 #define ZB_S (LIMMdup + 1)
1698 #define ZC_S (LIMMdup + 1)
1699 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1700
1701 #define RRANGE_EL (ZA + 1)
1702 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1703 insert_rrange, extract_rrange},
1704 #define FP_EL (RRANGE_EL + 1)
1705 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1706 insert_fpel, extract_fpel },
1707 #define BLINK_EL (FP_EL + 1)
1708 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1709 insert_blinkel, extract_blinkel },
1710 #define PCL_EL (BLINK_EL + 1)
1711 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1712 insert_pclel, extract_pclel },
1713
1714 /* Fake operand to handle the T flag. */
1715 #define BRAKET (PCL_EL + 1)
1716 #define BRAKETdup (PCL_EL + 1)
1717 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1718
1719 /* Fake operand to handle the T flag. */
1720 #define FKT_T (BRAKET + 1)
1721 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1722 /* Fake operand to handle the T flag. */
1723 #define FKT_NT (FKT_T + 1)
1724 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1725
1726 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1727 #define UIMM6_20 (FKT_NT + 1)
1728 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1729
1730 /* Exactly like the above but used by relaxation. */
1731 #define UIMM6_20R (UIMM6_20 + 1)
1732 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1733 insert_uimm6_20, extract_uimm6_20},
1734
1735 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1736 #define SIMM12_20 (UIMM6_20R + 1)
1737 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1738
1739 /* Exactly like the above but used by relaxation. */
1740 #define SIMM12_20R (SIMM12_20 + 1)
1741 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1742 insert_simm12_20, extract_simm12_20},
1743
1744 /* SIMM3_5_S mask = 0000011100000000. */
1745 #define SIMM3_5_S (SIMM12_20R + 1)
1746 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1747 insert_simm3s, extract_simm3s},
1748
1749 /* UIMM7_A32_11_S mask = 0000000000011111. */
1750 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1751 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1752 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1753 extract_uimm7_a32_11_s},
1754
1755 /* The same as above but used by relaxation. */
1756 #define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1757 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1758 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1759 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1760
1761 /* UIMM7_9_S mask = 0000000001111111. */
1762 #define UIMM7_9_S (UIMM7_A32_11R_S + 1)
1763 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1764
1765 /* UIMM3_13_S mask = 0000000000000111. */
1766 #define UIMM3_13_S (UIMM7_9_S + 1)
1767 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1768
1769 /* Exactly like the above but used for relaxation. */
1770 #define UIMM3_13R_S (UIMM3_13_S + 1)
1771 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1772 insert_uimm3_13_s, extract_uimm3_13_s},
1773
1774 /* SIMM11_A32_7_S mask = 0000000111111111. */
1775 #define SIMM11_A32_7_S (UIMM3_13R_S + 1)
1776 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1777 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1778
1779 /* UIMM6_13_S mask = 0000000002220111. */
1780 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1781 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1782 /* UIMM5_11_S mask = 0000000000011111. */
1783 #define UIMM5_11_S (UIMM6_13_S + 1)
1784 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1785 extract_uimm5_11_s},
1786
1787 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1788 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1789 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1790 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1791 extract_simm9_a16_8},
1792
1793 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1794 #define UIMM6_8 (SIMM9_A16_8 + 1)
1795 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1796
1797 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1798 #define SIMM21_A16_5 (UIMM6_8 + 1)
1799 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1800 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1801 insert_simm21_a16_5, extract_simm21_a16_5},
1802
1803 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1804 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1805 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1806 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1807 insert_simm25_a16_5, extract_simm25_a16_5},
1808
1809 /* SIMM10_A16_7_S mask = 0000000111111111. */
1810 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1811 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1812 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1813 extract_simm10_a16_7_s},
1814
1815 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1816 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1817 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1818
1819 /* SIMM7_A16_10_S mask = 0000000000111111. */
1820 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1821 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1822 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1823 extract_simm7_a16_10_s},
1824
1825 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1826 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1827 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1828 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1829 extract_simm21_a32_5},
1830
1831 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1832 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1833 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1834 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1835 extract_simm25_a32_5},
1836
1837 /* SIMM13_A32_5_S mask = 0000011111111111. */
1838 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1839 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1840 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1841 extract_simm13_a32_5_s},
1842
1843 /* SIMM8_A16_9_S mask = 0000000001111111. */
1844 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1845 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1846 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1847 extract_simm8_a16_9_s},
1848
1849 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1850 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1851 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1852
1853 /* UIMM10_6_S mask = 0000001111111111. */
1854 #define UIMM10_6_S (UIMM3_23 + 1)
1855 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1856
1857 /* UIMM6_11_S mask = 0000002200011110. */
1858 #define UIMM6_11_S (UIMM10_6_S + 1)
1859 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1860
1861 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1862 #define SIMM9_8 (UIMM6_11_S + 1)
1863 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1864 insert_simm9_8, extract_simm9_8},
1865
1866 /* The same as above but used by relaxation. */
1867 #define SIMM9_8R (SIMM9_8 + 1)
1868 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
1869 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
1870
1871 /* UIMM10_A32_8_S mask = 0000000011111111. */
1872 #define UIMM10_A32_8_S (SIMM9_8R + 1)
1873 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1874 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1875 extract_uimm10_a32_8_s},
1876
1877 /* SIMM9_7_S mask = 0000000111111111. */
1878 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1879 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1880 extract_simm9_7_s},
1881
1882 /* UIMM6_A16_11_S mask = 0000000000011111. */
1883 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1884 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1885 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1886 extract_uimm6_a16_11_s},
1887
1888 /* UIMM5_A32_11_S mask = 0000020000011000. */
1889 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1890 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1891 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1892 extract_uimm5_a32_11_s},
1893
1894 /* SIMM11_A32_13_S mask = 0000022222200111. */
1895 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1896 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1897 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1898
1899 /* UIMM7_13_S mask = 0000000022220111. */
1900 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1901 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1902
1903 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1904 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1905 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1906 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1907
1908 /* UIMM7_11_S mask = 0000022200011110. */
1909 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1910 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1911
1912 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1913 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1914 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1915 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1916 extract_uimm7_a16_20},
1917
1918 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1919 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1920 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1921 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1922 extract_simm13_a16_20},
1923
1924 /* UIMM8_8_S mask = 0000000011111111. */
1925 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1926 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1927
1928 /* The same as above but used for relaxation. */
1929 #define UIMM8_8R_S (UIMM8_8_S + 1)
1930 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1931 insert_uimm8_8_s, extract_uimm8_8_s},
1932
1933 /* W6 mask = 00000000000000000000111111000000. */
1934 #define W6 (UIMM8_8R_S + 1)
1935 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1936
1937 /* UIMM6_5_S mask = 0000011111100000. */
1938 #define UIMM6_5_S (W6 + 1)
1939 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1940
1941 /* ARC NPS400 Support: See comment near head of file. */
1942 #define NPS_R_DST_3B (UIMM6_5_S + 1)
1943 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
1944
1945 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1946 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
1947
1948 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1949 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
1950
1951 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
1952 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
1953
1954 #define NPS_R_SRC1 (NPS_R_DST + 1)
1955 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
1956
1957 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1958 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1959
1960 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1961 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1962
1963 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1964 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
1965
1966 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1967 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1968
1969 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1970 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1971
1972 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1973 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1974
1975 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
1976 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1977
1978 #define NPS_SIMM16 (NPS_UIMM16 + 1)
1979 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
1980
1981 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
1982 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
1983
1984 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1985 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
1986
1987 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1988 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1989
1990 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1991 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1992
1993 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1994 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1995
1996 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1997 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1998
1999 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
2000 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
2001
2002 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
2003 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
2004
2005 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2006 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2007
2008 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2009 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2010
2011 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
2012 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
2013
2014 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2015 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2016
2017 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2018 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2019
2020 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2021 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2022
2023 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
2024 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
2025
2026 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
2027 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2028
2029 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
2030 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2031
2032 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
2033 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
2034
2035 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
2036 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
2037
2038 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
2039 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
2040
2041 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
2042 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
2043
2044 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
2045 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2046
2047 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
2048 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2049
2050 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2051 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2052
2053 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2054 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2055
2056 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
2057 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2058
2059 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2060 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2061
2062 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2063 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2064
2065 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2066 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2067
2068 #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
2069 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
2070
2071 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
2072 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2073
2074 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2075 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2076
2077 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2078 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2079
2080 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2081 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
2082
2083 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2084 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2085
2086 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2087 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
2088
2089 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2090 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
2091
2092 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2093 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2094
2095 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2096 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2097
2098 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2099 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2100
2101 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2102 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
2103
2104 #define NPS_PSBC (NPS_MIN_HOFS + 1)
2105 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2106
2107 #define NPS_DPI_DST (NPS_PSBC + 1)
2108 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2109
2110 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
2111 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2112 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2113
2114 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2115 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width },
2116
2117 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2118 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2119
2120 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2121 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2122
2123 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2124 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2125
2126 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2127 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len },
2128
2129 #define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2130 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2131
2132 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2133 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2134
2135 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2136 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2137
2138 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2139 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2140
2141 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2142 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2143
2144 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2145 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
2146
2147 #define COLON (NPS_E4BY_INDEX3 + 1)
2148 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2149
2150 #define NPS_BD (COLON + 1)
2151 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
2152
2153 #define NPS_JID (NPS_BD + 1)
2154 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
2155
2156 #define NPS_LBD (NPS_JID + 1)
2157 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
2158
2159 #define NPS_MBD (NPS_LBD + 1)
2160 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
2161
2162 #define NPS_SD (NPS_MBD + 1)
2163 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
2164
2165 #define NPS_SM (NPS_SD + 1)
2166 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
2167
2168 #define NPS_XA (NPS_SM + 1)
2169 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
2170
2171 #define NPS_XD (NPS_XA + 1)
2172 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
2173
2174 #define NPS_CD (NPS_XD + 1)
2175 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
2176
2177 #define NPS_CBD (NPS_CD + 1)
2178 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
2179
2180 #define NPS_CJID (NPS_CBD + 1)
2181 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
2182
2183 #define NPS_CLBD (NPS_CJID + 1)
2184 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
2185
2186 #define NPS_CM (NPS_CLBD + 1)
2187 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
2188
2189 #define NPS_CSD (NPS_CM + 1)
2190 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
2191
2192 #define NPS_CXA (NPS_CSD + 1)
2193 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
2194
2195 #define NPS_CXD (NPS_CXA + 1)
2196 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
2197
2198 #define NPS_BD_TYPE (NPS_CXD + 1)
2199 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2200
2201 #define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2202 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2203
2204 #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2205 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2206
2207 #define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
2208 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
2209
2210 #define NPS_R_DST_3B_48 (NPS_PMU_NUM_JOB + 1)
2211 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2212
2213 #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2214 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2215
2216 #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2217 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2218
2219 #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2220 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2221
2222 #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2223 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2224
2225 #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2226 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
2227
2228 #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2229 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2230
2231 #define NPS_RB_64 (NPS_RA_64 + 1)
2232 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2233
2234 #define NPS_RBdup_64 (NPS_RB_64 + 1)
2235 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2236
2237 #define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2238 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
2239
2240 #define NPS_RC_64 (NPS_RBdouble_64 + 1)
2241 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2242
2243 #define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2244 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2245
2246 #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2247 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size }
2248 };
2249 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
2250
2251 const unsigned arc_Toperand = FKT_T;
2252 const unsigned arc_NToperand = FKT_NT;
2253
2254 const unsigned char arg_none[] = { 0 };
2255 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2256 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2257 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2258 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2259 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2260 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2261 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2262 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2263 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2264 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2265 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2266
2267 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2268 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2269 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2270
2271 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2272 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2273 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2274
2275 const unsigned char arg_32bit_rbrc[] = { RB, RC };
2276 const unsigned char arg_32bit_zarc[] = { ZA, RC };
2277 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2278 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2279 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2280 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2281
2282 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2283 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2284 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2285 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2286
2287 const unsigned char arg_32bit_rc[] = { RC };
2288 const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2289 const unsigned char arg_32bit_limm[] = { LIMM };
2290
2291 /* The opcode table.
2292
2293 The format of the opcode table is:
2294
2295 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2296
2297 The table is organised such that, where possible, all instructions with
2298 the same mnemonic are together in a block. When the assembler searches
2299 for a suitable instruction the entries are checked in table order, so
2300 more specific, or specialised cases should appear earlier in the table.
2301
2302 As an example, consider two instructions 'add a,b,u6' and 'add
2303 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2304 32-bit instruction, while the second takes a 32-bit immediate that is
2305 encoded in a follow-on 32-bit, making the total instruction length
2306 64-bits. In this case the u6 variant must appear first in the table, as
2307 all u6 immediates could also be encoded using the 'limm' extension,
2308 however, we want to use the shorter instruction wherever possible.
2309
2310 It is possible though to split instructions with the same mnemonic into
2311 multiple groups. However, the instructions are still checked in table
2312 order, even across groups. The only time that instructions with the
2313 same mnemonic should be split into different groups is when different
2314 variants of the instruction appear in different architectures, in which
2315 case, grouping all instructions from a particular architecture together
2316 might be preferable to merging the instruction into the main instruction
2317 table.
2318
2319 An example of this split instruction groups can be found with the 'sync'
2320 instruction. The core arc architecture provides a 'sync' instruction,
2321 while the nps instruction set extension provides 'sync.rd' and
2322 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2323 mnemonic, so we end up with two groups for the sync instruction, the
2324 first within the core arc instruction table, and the second within the
2325 nps extension instructions. */
2326 const struct arc_opcode arc_opcodes[] =
2327 {
2328 #include "arc-tbl.h"
2329 #include "arc-nps400-tbl.h"
2330 #include "arc-ext-tbl.h"
2331
2332 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2333 };
2334
2335 /* List with special cases instructions and the applicable flags. */
2336 const struct arc_flag_special arc_flag_special_cases[] =
2337 {
2338 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2339 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2340 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2341 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2342 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2343 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2344 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2345 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2346 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2347 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2348 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2349 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2350 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2351 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2352 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2353 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2354 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2355 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2356 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2357 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2358 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2359 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2360 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2361 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2362 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2363 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2364 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2365 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2366 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2367 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2368 };
2369
2370 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
2371
2372 /* Relocations. */
2373 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2374 {
2375 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2376 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2377 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2378 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2379 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2380 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2381 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2382 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2383
2384 /* Next two entries will cover the undefined behavior ldb/stb with
2385 address scaling. */
2386 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2387 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2388 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2389 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2390
2391 { "sda", "ld", { F_ASFAKE, F_NULL },
2392 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2393 { "sda", "st", { F_ASFAKE, F_NULL },
2394 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2395 { "sda", "ldd", { F_ASFAKE, F_NULL },
2396 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2397 { "sda", "std", { F_ASFAKE, F_NULL },
2398 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2399
2400 /* Short instructions. */
2401 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2402 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2403 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2404 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2405
2406 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2407 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2408
2409 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2410 BFD_RELOC_ARC_S25H_PCREL_PLT },
2411 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2412 BFD_RELOC_ARC_S21H_PCREL_PLT },
2413 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2414 BFD_RELOC_ARC_S25W_PCREL_PLT },
2415 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2416 BFD_RELOC_ARC_S21W_PCREL_PLT },
2417
2418 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
2419 };
2420
2421 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
2422
2423 const struct arc_pseudo_insn arc_pseudo_insns[] =
2424 {
2425 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2426 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2427 { BRAKETdup, 1, 0, 4} } },
2428 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2429 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2430 { BRAKETdup, 1, 0, 4} } },
2431
2432 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2433 { SIMM9_A16_8, 0, 0, 2 } } },
2434 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2435 { SIMM9_A16_8, 0, 0, 2 } } },
2436 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2437 { SIMM9_A16_8, 0, 0, 2 } } },
2438 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2439 { SIMM9_A16_8, 0, 0, 2 } } },
2440 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2441 { SIMM9_A16_8, 0, 0, 2 } } },
2442
2443 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2444 { SIMM9_A16_8, 0, 0, 2 } } },
2445 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2446 { SIMM9_A16_8, 0, 0, 2 } } },
2447 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2448 { SIMM9_A16_8, 0, 0, 2 } } },
2449 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2450 { SIMM9_A16_8, 0, 0, 2 } } },
2451 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2452 { SIMM9_A16_8, 0, 0, 2 } } },
2453
2454 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2455 { SIMM9_A16_8, 0, 0, 2 } } },
2456 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2457 { SIMM9_A16_8, 0, 0, 2 } } },
2458 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2459 { SIMM9_A16_8, 0, 0, 2 } } },
2460 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2461 { SIMM9_A16_8, 0, 0, 2 } } },
2462 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2463 { SIMM9_A16_8, 0, 0, 2 } } },
2464
2465 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2466 { SIMM9_A16_8, 0, 0, 2 } } },
2467 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2468 { SIMM9_A16_8, 0, 0, 2 } } },
2469 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2470 { SIMM9_A16_8, 0, 0, 2 } } },
2471 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2472 { SIMM9_A16_8, 0, 0, 2 } } },
2473 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2474 { SIMM9_A16_8, 0, 0, 2 } } },
2475 };
2476
2477 const unsigned arc_num_pseudo_insn =
2478 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
2479
2480 const struct arc_aux_reg arc_aux_regs[] =
2481 {
2482 #undef DEF
2483 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
2484 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
2485
2486 #include "arc-regs.h"
2487
2488 #undef DEF
2489 };
2490
2491 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
2492
2493 /* NOTE: The order of this array MUST be consistent with 'enum
2494 arc_rlx_types' located in tc-arc.h! */
2495 const struct arc_opcode arc_relax_opcodes[] =
2496 {
2497 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2498
2499 /* bl_s s13 11111sssssssssss. */
2500 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2501 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2502 { SIMM13_A32_5_S }, { 0 }},
2503
2504 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2505 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2506 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2507 { SIMM25_A32_5 }, { C_D }},
2508
2509 /* b_s s10 1111000sssssssss. */
2510 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2511 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2512 { SIMM10_A16_7_S }, { 0 }},
2513
2514 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2515 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2516 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2517 { SIMM25_A16_5 }, { C_D }},
2518
2519 /* add_s c,b,u3 01101bbbccc00uuu. */
2520 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2521 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2522 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2523
2524 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
2525 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2526 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2527 { RA, RB, UIMM6_20R }, { C_F }},
2528
2529 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2530 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2531 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2532 { RA, RB, LIMM }, { C_F }},
2533
2534 /* ld_s c,b,u7 10000bbbcccuuuuu. */
2535 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2536 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2537 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
2538
2539 /* ld<.di><.aa><.x><zz> a,b,s9
2540 00010bbbssssssssSBBBDaaZZXAAAAAA. */
2541 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2542 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2543 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
2544 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2545
2546 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2547 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2548 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2549 { RA, BRAKET, RB, LIMM, BRAKETdup },
2550 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2551
2552 /* mov_s b,u8 11011bbbuuuuuuuu. */
2553 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2554 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2555 { RB_S, UIMM8_8R_S }, { 0 }},
2556
2557 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
2558 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2559 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2560 { RB, SIMM12_20R }, { C_F }},
2561
2562 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2563 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2564 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2565 { RB, LIMM }, { C_F }},
2566
2567 /* sub_s c,b,u3 01101bbbccc01uuu. */
2568 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2569 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2570 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2571
2572 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
2573 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2574 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2575 { RA, RB, UIMM6_20R }, { C_F }},
2576
2577 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2578 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2579 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2580 { RA, RB, LIMM }, { C_F }},
2581
2582 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
2583 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2584 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
2585
2586 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2587 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2588 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2589
2590 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
2591 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2592 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2593 { RB, UIMM6_20R }, { C_F, C_CC }},
2594
2595 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2596 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2597 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2598 { RB, LIMM }, { C_F, C_CC }},
2599
2600 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
2601 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2602 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2603 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
2604
2605 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2606 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2607 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2608 { RB, RBdup, LIMM }, { C_F, C_CC }}
2609 };
2610
2611 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
2612
2613 /* Return length of an opcode in bytes. */
2614
2615 int
2616 arc_opcode_len (const struct arc_opcode *opcode)
2617 {
2618 if (opcode->mask < 0x10000ull)
2619 return 2;
2620
2621 if (opcode->mask < 0x100000000ull)
2622 return 4;
2623
2624 if (opcode->mask < 0x1000000000000ull)
2625 return 6;
2626
2627 return 8;
2628 }
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