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[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include "sysdep.h"
23 #include "dis-asm.h"
24 #define DEFINE_TABLE
25 #include "arm-opc.h"
26 #include "coff/internal.h"
27 #include "libcoff.h"
28 #include "opintl.h"
29
30 /* FIXME: This shouldn't be done here */
31 #include "elf-bfd.h"
32 #include "elf/internal.h"
33 #include "elf/arm.h"
34
35 #ifndef streq
36 #define streq(a,b) (strcmp ((a), (b)) == 0)
37 #endif
38 #ifndef strneq
39 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
40 #endif
41
42 static char * arm_conditional[] =
43 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
44 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
45
46 static char * arm_regnames_raw[] =
47 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
48 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
49
50 static char * arm_regnames_standard[] =
51 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
52 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
53
54 static char * arm_regnames_apcs[] =
55 {"a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4",
56 "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc"};
57
58 /* Choose which register name set to use. */
59 static char ** arm_regnames = arm_regnames_standard;
60
61 static boolean force_thumb = false;
62
63 static char * arm_fp_const[] =
64 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
65
66 static char * arm_shift[] =
67 {"lsl", "lsr", "asr", "ror"};
68 \f
69 /* Forward declarations. */
70 static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
71 static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
72 static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
73 static void parse_disassembler_option PARAMS ((char *));
74 static void parse_disassembler_options PARAMS ((char *));
75 \f
76 /* Functions. */
77 static void
78 arm_decode_shift (given, func, stream)
79 long given;
80 fprintf_ftype func;
81 void * stream;
82 {
83 func (stream, "%s", arm_regnames[given & 0xf]);
84
85 if ((given & 0xff0) != 0)
86 {
87 if ((given & 0x10) == 0)
88 {
89 int amount = (given & 0xf80) >> 7;
90 int shift = (given & 0x60) >> 5;
91
92 if (amount == 0)
93 {
94 if (shift == 3)
95 {
96 func (stream, ", rrx");
97 return;
98 }
99
100 amount = 32;
101 }
102
103 func (stream, ", %s #%d", arm_shift[shift], amount);
104 }
105 else
106 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
107 arm_regnames[(given & 0xf00) >> 8]);
108 }
109 }
110
111 /* Print one instruction from PC on INFO->STREAM.
112 Return the size of the instruction (always 4 on ARM). */
113
114 static int
115 print_insn_arm (pc, info, given)
116 bfd_vma pc;
117 struct disassemble_info * info;
118 long given;
119 {
120 struct arm_opcode * insn;
121 void * stream = info->stream;
122 fprintf_ftype func = info->fprintf_func;
123
124 for (insn = arm_opcodes; insn->assembler; insn++)
125 {
126 if ((given & insn->mask) == insn->value)
127 {
128 char * c;
129
130 for (c = insn->assembler; *c; c++)
131 {
132 if (*c == '%')
133 {
134 switch (*++c)
135 {
136 case '%':
137 func (stream, "%%");
138 break;
139
140 case 'a':
141 if (((given & 0x000f0000) == 0x000f0000)
142 && ((given & 0x02000000) == 0))
143 {
144 int offset = given & 0xfff;
145
146 func (stream, "[pc");
147
148 if (given & 0x01000000)
149 {
150 if ((given & 0x00800000) == 0)
151 offset = - offset;
152
153 /* pre-indexed */
154 func (stream, ", #%x]", offset);
155
156 offset += pc + 8;
157
158 /* Cope with the possibility of write-back being used.
159 Probably a very dangerous thing for the programmer
160 to do, but who are we to argue ? */
161 if (given & 0x00200000)
162 func (stream, "!");
163 }
164 else
165 {
166 /* post indexed */
167 func (stream, "], #%x", offset);
168
169 offset = pc + 8; /* ie ignore the offset */
170 }
171
172 func (stream, "\t; ");
173 info->print_address_func (offset, info);
174 }
175 else
176 {
177 func (stream, "[%s",
178 arm_regnames[(given >> 16) & 0xf]);
179 if ((given & 0x01000000) != 0)
180 {
181 if ((given & 0x02000000) == 0)
182 {
183 int offset = given & 0xfff;
184 if (offset)
185 func (stream, ", %s#%d",
186 (((given & 0x00800000) == 0)
187 ? "-" : ""), offset);
188 }
189 else
190 {
191 func (stream, ", %s",
192 (((given & 0x00800000) == 0)
193 ? "-" : ""));
194 arm_decode_shift (given, func, stream);
195 }
196
197 func (stream, "]%s",
198 ((given & 0x00200000) != 0) ? "!" : "");
199 }
200 else
201 {
202 if ((given & 0x02000000) == 0)
203 {
204 int offset = given & 0xfff;
205 if (offset)
206 func (stream, "], %s#%d",
207 (((given & 0x00800000) == 0)
208 ? "-" : ""), offset);
209 else
210 func (stream, "]");
211 }
212 else
213 {
214 func (stream, "], %s",
215 (((given & 0x00800000) == 0)
216 ? "-" : ""));
217 arm_decode_shift (given, func, stream);
218 }
219 }
220 }
221 break;
222
223 case 's':
224 if ((given & 0x004f0000) == 0x004f0000)
225 {
226 /* PC relative with immediate offset */
227 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
228
229 if ((given & 0x00800000) == 0)
230 offset = -offset;
231
232 func (stream, "[pc, #%x]\t; ", offset);
233
234 (*info->print_address_func)
235 (offset + pc + 8, info);
236 }
237 else
238 {
239 func (stream, "[%s",
240 arm_regnames[(given >> 16) & 0xf]);
241 if ((given & 0x01000000) != 0)
242 {
243 /* pre-indexed */
244 if ((given & 0x00400000) == 0x00400000)
245 {
246 /* immediate */
247 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
248 if (offset)
249 func (stream, ", %s#%d",
250 (((given & 0x00800000) == 0)
251 ? "-" : ""), offset);
252 }
253 else
254 {
255 /* register */
256 func (stream, ", %s%s",
257 (((given & 0x00800000) == 0)
258 ? "-" : ""),
259 arm_regnames[given & 0xf]);
260 }
261
262 func (stream, "]%s",
263 ((given & 0x00200000) != 0) ? "!" : "");
264 }
265 else
266 {
267 /* post-indexed */
268 if ((given & 0x00400000) == 0x00400000)
269 {
270 /* immediate */
271 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
272 if (offset)
273 func (stream, "], %s#%d",
274 (((given & 0x00800000) == 0)
275 ? "-" : ""), offset);
276 else
277 func (stream, "]");
278 }
279 else
280 {
281 /* register */
282 func (stream, "], %s%s",
283 (((given & 0x00800000) == 0)
284 ? "-" : ""),
285 arm_regnames[given & 0xf]);
286 }
287 }
288 }
289 break;
290
291 case 'b':
292 (*info->print_address_func)
293 (BDISP (given) * 4 + pc + 8, info);
294 break;
295
296 case 'c':
297 func (stream, "%s",
298 arm_conditional [(given >> 28) & 0xf]);
299 break;
300
301 case 'm':
302 {
303 int started = 0;
304 int reg;
305
306 func (stream, "{");
307 for (reg = 0; reg < 16; reg++)
308 if ((given & (1 << reg)) != 0)
309 {
310 if (started)
311 func (stream, ", ");
312 started = 1;
313 func (stream, "%s", arm_regnames[reg]);
314 }
315 func (stream, "}");
316 }
317 break;
318
319 case 'o':
320 if ((given & 0x02000000) != 0)
321 {
322 int rotate = (given & 0xf00) >> 7;
323 int immed = (given & 0xff);
324 immed = (((immed << (32 - rotate))
325 | (immed >> rotate)) & 0xffffffff);
326 func (stream, "#%d\t; 0x%x", immed, immed);
327 }
328 else
329 arm_decode_shift (given, func, stream);
330 break;
331
332 case 'p':
333 if ((given & 0x0000f000) == 0x0000f000)
334 func (stream, "p");
335 break;
336
337 case 't':
338 if ((given & 0x01200000) == 0x00200000)
339 func (stream, "t");
340 break;
341
342 case 'h':
343 if ((given & 0x00000020) == 0x00000020)
344 func (stream, "h");
345 else
346 func (stream, "b");
347 break;
348
349 case 'A':
350 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
351 if ((given & 0x01000000) != 0)
352 {
353 int offset = given & 0xff;
354 if (offset)
355 func (stream, ", %s#%d]%s",
356 ((given & 0x00800000) == 0 ? "-" : ""),
357 offset * 4,
358 ((given & 0x00200000) != 0 ? "!" : ""));
359 else
360 func (stream, "]");
361 }
362 else
363 {
364 int offset = given & 0xff;
365 if (offset)
366 func (stream, "], %s#%d",
367 ((given & 0x00800000) == 0 ? "-" : ""),
368 offset * 4);
369 else
370 func (stream, "]");
371 }
372 break;
373
374 case 'C':
375 switch (given & 0x00090000)
376 {
377 default:
378 func (stream, "_???");
379 break;
380 case 0x90000:
381 func (stream, "_all");
382 break;
383 case 0x10000:
384 func (stream, "_ctl");
385 break;
386 case 0x80000:
387 func (stream, "_flg");
388 break;
389 }
390 break;
391
392 case 'F':
393 switch (given & 0x00408000)
394 {
395 case 0:
396 func (stream, "4");
397 break;
398 case 0x8000:
399 func (stream, "1");
400 break;
401 case 0x00400000:
402 func (stream, "2");
403 break;
404 default:
405 func (stream, "3");
406 }
407 break;
408
409 case 'P':
410 switch (given & 0x00080080)
411 {
412 case 0:
413 func (stream, "s");
414 break;
415 case 0x80:
416 func (stream, "d");
417 break;
418 case 0x00080000:
419 func (stream, "e");
420 break;
421 default:
422 func (stream, _("<illegal precision>"));
423 break;
424 }
425 break;
426 case 'Q':
427 switch (given & 0x00408000)
428 {
429 case 0:
430 func (stream, "s");
431 break;
432 case 0x8000:
433 func (stream, "d");
434 break;
435 case 0x00400000:
436 func (stream, "e");
437 break;
438 default:
439 func (stream, "p");
440 break;
441 }
442 break;
443 case 'R':
444 switch (given & 0x60)
445 {
446 case 0:
447 break;
448 case 0x20:
449 func (stream, "p");
450 break;
451 case 0x40:
452 func (stream, "m");
453 break;
454 default:
455 func (stream, "z");
456 break;
457 }
458 break;
459
460 case '0': case '1': case '2': case '3': case '4':
461 case '5': case '6': case '7': case '8': case '9':
462 {
463 int bitstart = *c++ - '0';
464 int bitend = 0;
465 while (*c >= '0' && *c <= '9')
466 bitstart = (bitstart * 10) + *c++ - '0';
467
468 switch (*c)
469 {
470 case '-':
471 c++;
472 while (*c >= '0' && *c <= '9')
473 bitend = (bitend * 10) + *c++ - '0';
474 if (!bitend)
475 abort ();
476 switch (*c)
477 {
478 case 'r':
479 {
480 long reg;
481 reg = given >> bitstart;
482 reg &= (2 << (bitend - bitstart)) - 1;
483 func (stream, "%s", arm_regnames[reg]);
484 }
485 break;
486 case 'd':
487 {
488 long reg;
489 reg = given >> bitstart;
490 reg &= (2 << (bitend - bitstart)) - 1;
491 func (stream, "%d", reg);
492 }
493 break;
494 case 'x':
495 {
496 long reg;
497 reg = given >> bitstart;
498 reg &= (2 << (bitend - bitstart)) - 1;
499 func (stream, "0x%08x", reg);
500
501 /* Some SWI instructions have special meanings. */
502 if ((given & 0x0fffffff) == 0x0FF00000)
503 func (stream, "\t; IMB");
504 else if ((given & 0x0fffffff) == 0x0FF00001)
505 func (stream, "\t; IMBRange");
506 }
507 break;
508 case 'X':
509 {
510 long reg;
511 reg = given >> bitstart;
512 reg &= (2 << (bitend - bitstart)) - 1;
513 func (stream, "%01x", reg & 0xf);
514 }
515 break;
516 case 'f':
517 {
518 long reg;
519 reg = given >> bitstart;
520 reg &= (2 << (bitend - bitstart)) - 1;
521 if (reg > 7)
522 func (stream, "#%s",
523 arm_fp_const[reg & 7]);
524 else
525 func (stream, "f%d", reg);
526 }
527 break;
528 default:
529 abort ();
530 }
531 break;
532 case '`':
533 c++;
534 if ((given & (1 << bitstart)) == 0)
535 func (stream, "%c", *c);
536 break;
537 case '\'':
538 c++;
539 if ((given & (1 << bitstart)) != 0)
540 func (stream, "%c", *c);
541 break;
542 case '?':
543 ++c;
544 if ((given & (1 << bitstart)) != 0)
545 func (stream, "%c", *c++);
546 else
547 func (stream, "%c", *++c);
548 break;
549 default:
550 abort ();
551 }
552 break;
553
554 default:
555 abort ();
556 }
557 }
558 }
559 else
560 func (stream, "%c", *c);
561 }
562 return 4;
563 }
564 }
565 abort ();
566 }
567
568 /* Print one instruction from PC on INFO->STREAM.
569 Return the size of the instruction. */
570
571 static int
572 print_insn_thumb (pc, info, given)
573 bfd_vma pc;
574 struct disassemble_info * info;
575 long given;
576 {
577 struct thumb_opcode * insn;
578 void * stream = info->stream;
579 fprintf_ftype func = info->fprintf_func;
580
581 for (insn = thumb_opcodes; insn->assembler; insn++)
582 {
583 if ((given & insn->mask) == insn->value)
584 {
585 char * c = insn->assembler;
586
587 /* Special processing for Thumb 2 instruction BL sequence: */
588 if (!*c) /* check for empty (not NULL) assembler string */
589 {
590 info->bytes_per_chunk = 4;
591 info->bytes_per_line = 4;
592
593 func (stream, "%04x\tbl\t", given & 0xffff);
594 (*info->print_address_func)
595 (BDISP23 (given) * 2 + pc + 4, info);
596 return 4;
597 }
598 else
599 {
600 info->bytes_per_chunk = 2;
601 info->bytes_per_line = 4;
602
603 given &= 0xffff;
604 func (stream, "%04x\t", given);
605
606 for (; *c; c++)
607 {
608 if (*c == '%')
609 {
610 int domaskpc = 0;
611 int domasklr = 0;
612
613 switch (*++c)
614 {
615 case '%':
616 func (stream, "%%");
617 break;
618
619 case 'S':
620 {
621 long reg;
622 reg = (given >> 3) & 0x7;
623 if (given & (1 << 6))
624 reg += 8;
625 func (stream, "%s", arm_regnames[reg]);
626 }
627 break;
628
629 case 'D':
630 {
631 long reg;
632
633 reg = given & 0x7;
634 if (given & (1 << 7))
635 reg += 8;
636 func (stream, "%s", arm_regnames[reg]);
637 }
638 break;
639
640 case 'T':
641 func (stream, "%s",
642 arm_conditional [(given >> 8) & 0xf]);
643 break;
644
645 case 'N':
646 if (given & (1 << 8))
647 domasklr = 1;
648 /* fall through */
649 case 'O':
650 if (*c == 'O' && (given & (1 << 8)))
651 domaskpc = 1;
652 /* fall through */
653 case 'M':
654 {
655 int started = 0;
656 int reg;
657
658 func (stream, "{");
659 /* It would be nice if we could spot
660 ranges, and generate the rS-rE format: */
661 for (reg = 0; (reg < 8); reg++)
662 if ((given & (1 << reg)) != 0)
663 {
664 if (started)
665 func (stream, ", ");
666 started = 1;
667 func (stream, "%s", arm_regnames[reg]);
668 }
669
670 if (domasklr)
671 {
672 if (started)
673 func (stream, ", ");
674 started = 1;
675 func (stream, "lr");
676 }
677
678 if (domaskpc)
679 {
680 if (started)
681 func (stream, ", ");
682 func (stream, "pc");
683 }
684
685 func (stream, "}");
686 }
687 break;
688
689
690 case '0': case '1': case '2': case '3': case '4':
691 case '5': case '6': case '7': case '8': case '9':
692 {
693 int bitstart = *c++ - '0';
694 int bitend = 0;
695
696 while (*c >= '0' && *c <= '9')
697 bitstart = (bitstart * 10) + *c++ - '0';
698
699 switch (*c)
700 {
701 case '-':
702 {
703 long reg;
704
705 c++;
706 while (*c >= '0' && *c <= '9')
707 bitend = (bitend * 10) + *c++ - '0';
708 if (!bitend)
709 abort ();
710 reg = given >> bitstart;
711 reg &= (2 << (bitend - bitstart)) - 1;
712 switch (*c)
713 {
714 case 'r':
715 func (stream, "%s", arm_regnames[reg]);
716 break;
717
718 case 'd':
719 func (stream, "%d", reg);
720 break;
721
722 case 'H':
723 func (stream, "%d", reg << 1);
724 break;
725
726 case 'W':
727 func (stream, "%d", reg << 2);
728 break;
729
730 case 'a':
731 /* PC-relative address -- the bottom two
732 bits of the address are dropped before
733 the calculation. */
734 info->print_address_func
735 (((pc + 4) & ~3) + (reg << 2), info);
736 break;
737
738 case 'x':
739 func (stream, "0x%04x", reg);
740 break;
741
742 case 'I':
743 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
744 func (stream, "%d", reg);
745 break;
746
747 case 'B':
748 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
749 (*info->print_address_func)
750 (reg * 2 + pc + 4, info);
751 break;
752
753 default:
754 abort ();
755 }
756 }
757 break;
758
759 case '\'':
760 c++;
761 if ((given & (1 << bitstart)) != 0)
762 func (stream, "%c", *c);
763 break;
764
765 case '?':
766 ++c;
767 if ((given & (1 << bitstart)) != 0)
768 func (stream, "%c", *c++);
769 else
770 func (stream, "%c", *++c);
771 break;
772
773 default:
774 abort ();
775 }
776 }
777 break;
778
779 default:
780 abort ();
781 }
782 }
783 else
784 func (stream, "%c", *c);
785 }
786 }
787 return 2;
788 }
789 }
790
791 /* no match */
792 abort ();
793 }
794
795 /* Select a different register name set.
796 Returns true if the name set selected is the APCS name set. */
797 int
798 arm_toggle_regnames ()
799 {
800 if (arm_regnames == arm_regnames_standard)
801 arm_regnames = arm_regnames_apcs;
802 else
803 arm_regnames = arm_regnames_standard;
804
805 return arm_regnames == arm_regnames_apcs;
806 }
807
808 static void
809 parse_disassembler_option (option)
810 char * option;
811 {
812 if (option == NULL)
813 return;
814
815 if (strneq (option, "reg-names-", 10))
816 {
817 option += 10;
818
819 if (streq (option, "std"))
820 arm_regnames = arm_regnames_standard;
821 else if (streq (option, "apcs"))
822 arm_regnames = arm_regnames_apcs;
823 else if (streq (option, "raw"))
824 arm_regnames = arm_regnames_raw;
825 else
826 fprintf (stderr, "Unrecognised register name set: %s\n", option);
827 }
828 else if (streq (option, "force-thumb"))
829 force_thumb = 1;
830 else if (streq (option, "no-force-thumb"))
831 force_thumb = 0;
832 else
833 fprintf (stderr, "Unrecognised disassembler option: %s\n", option);
834
835 return;
836 }
837
838 static void
839 parse_disassembler_options (options)
840 char * options;
841 {
842 char * space;
843
844 if (options == NULL)
845 return;
846
847 do
848 {
849 space = strchr (options, ' ');
850
851 if (space)
852 {
853 * space = '\0';
854 parse_disassembler_option (options);
855 * space = ' ';
856 options = space + 1;
857 }
858 else
859 parse_disassembler_option (options);
860 }
861 while (space);
862 }
863
864 /* NOTE: There are no checks in these routines that the relevant number of
865 data bytes exist. */
866
867 int
868 print_insn_big_arm (pc, info)
869 bfd_vma pc;
870 struct disassemble_info * info;
871 {
872 unsigned char b[4];
873 long given;
874 int status;
875 coff_symbol_type * cs;
876 elf_symbol_type * es;
877 int is_thumb;
878
879 if (info->disassembler_options)
880 {
881 parse_disassembler_options (info->disassembler_options);
882
883 /* To avoid repeated parsing of this option, we remove it here. */
884 info->disassembler_options = NULL;
885 }
886
887 is_thumb = force_thumb;
888
889 if (!is_thumb && info->symbols != NULL)
890 {
891 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
892 {
893 cs = coffsymbol (*info->symbols);
894 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
895 || cs->native->u.syment.n_sclass == C_THUMBSTAT
896 || cs->native->u.syment.n_sclass == C_THUMBLABEL
897 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
898 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
899 }
900 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
901 {
902 es = *(elf_symbol_type **)(info->symbols);
903 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
904 STT_ARM_TFUNC;
905 }
906 }
907
908 info->bytes_per_chunk = 4;
909 info->display_endian = BFD_ENDIAN_BIG;
910
911 /* Always fetch word aligned values. */
912
913 status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
914 if (status != 0)
915 {
916 (*info->memory_error_func) (status, pc, info);
917 return -1;
918 }
919
920 if (is_thumb)
921 {
922 if (pc & 0x2)
923 {
924 given = (b[2] << 8) | b[3];
925
926 status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
927 if (status != 0)
928 {
929 info->memory_error_func (status, pc + 4, info);
930 return -1;
931 }
932
933 given |= (b[0] << 24) | (b[1] << 16);
934 }
935 else
936 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
937 }
938 else
939 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
940
941 if (is_thumb)
942 status = print_insn_thumb (pc, info, given);
943 else
944 status = print_insn_arm (pc, info, given);
945
946 return status;
947 }
948
949 int
950 print_insn_little_arm (pc, info)
951 bfd_vma pc;
952 struct disassemble_info * info;
953 {
954 unsigned char b[4];
955 long given;
956 int status;
957 coff_symbol_type * cs;
958 elf_symbol_type * es;
959 int is_thumb;
960
961 if (info->disassembler_options)
962 {
963 parse_disassembler_options (info->disassembler_options);
964
965 /* To avoid repeated parsing of this option, we remove it here. */
966 info->disassembler_options = NULL;
967 }
968
969 is_thumb = force_thumb;
970
971 if (!is_thumb && info->symbols != NULL)
972 {
973 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
974 {
975 cs = coffsymbol (*info->symbols);
976 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
977 || cs->native->u.syment.n_sclass == C_THUMBSTAT
978 || cs->native->u.syment.n_sclass == C_THUMBLABEL
979 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
980 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
981 }
982 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
983 {
984 es = *(elf_symbol_type **)(info->symbols);
985 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
986 STT_ARM_TFUNC;
987 }
988 }
989
990 info->bytes_per_chunk = 4;
991 info->display_endian = BFD_ENDIAN_LITTLE;
992
993 status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info);
994 if (status != 0 && is_thumb)
995 {
996 info->bytes_per_chunk = 2;
997
998 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
999 b[3] = b[2] = 0;
1000 }
1001
1002 if (status != 0)
1003 {
1004 info->memory_error_func (status, pc, info);
1005 return -1;
1006 }
1007
1008 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
1009
1010 if (is_thumb)
1011 status = print_insn_thumb (pc, info, given);
1012 else
1013 status = print_insn_arm (pc, info, given);
1014
1015 return status;
1016 }
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