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[PATCH[ARM]Check mapping symbol while backward searching for IT block.
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24
25 #include "dis-asm.h"
26 #include "opcode/arm.h"
27 #include "opintl.h"
28 #include "safe-ctype.h"
29 #include "floatformat.h"
30
31 /* FIXME: This shouldn't be done here. */
32 #include "coff/internal.h"
33 #include "libcoff.h"
34 #include "elf-bfd.h"
35 #include "elf/internal.h"
36 #include "elf/arm.h"
37 #include "mach-o.h"
38
39 /* FIXME: Belongs in global header. */
40 #ifndef strneq
41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42 #endif
43
44 #ifndef NUM_ELEM
45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
46 #endif
47
48 /* Cached mapping symbol state. */
49 enum map_type
50 {
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54 };
55
56 struct arm_private_data
57 {
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
71 };
72
73 struct opcode32
74 {
75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
78 const char * assembler; /* How to disassemble this insn. */
79 };
80
81 struct opcode16
82 {
83 arm_feature_set arch; /* Architecture defining this insn. */
84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
85 const char *assembler; /* How to disassemble this insn. */
86 };
87
88 /* print_insn_coprocessor recognizes the following format control codes:
89
90 %% %
91
92 %c print condition code (always bits 28-31 in ARM mode)
93 %q print shifter argument
94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
96 %A print address for ldc/stc/ldf/stf instruction
97 %B print vstm/vldm register list
98 %I print cirrus signed shift immediate: bits 0..3|4..6
99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
104 %<bitfield>c print as a condition code (for vsel)
105 %<bitfield>r print as an ARM register
106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
108 %<bitfield>d print the bitfield in decimal
109 %<bitfield>k print immediate for VFPv3 conversion instruction
110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
119 %<bitfield>E print a quarter-float immediate value
120
121 %y<code> print a single precision VFP reg.
122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
123 %z<code> print a double precision VFP reg
124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
125
126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
129
130 %L print as an iWMMXt N/M width field.
131 %Z print the Immediate of a WSHUFH instruction.
132 %l like 'A' except use byte offsets for 'B' & 'H'
133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
136 %r print register offset address for wldt/wstr instruction. */
137
138 enum opcode_sentinel_enum
139 {
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143 } opcode_sentinels;
144
145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
147
148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
149
150 static const struct opcode32 coprocessor_opcodes[] =
151 {
152 /* XScale instructions. */
153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
165
166 /* Intel Wireless MMX technology instructions. */
167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
322
323 /* Floating point coprocessor (FPA) instructions. */
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
410
411 /* Register load/store. */
412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
453
454 /* Data transfer between ARM and NEON registers. */
455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
483 /* Half-precision conversion instructions. */
484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
492
493 /* Floating point coprocessor (VFP) instructions. */
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
628
629 /* Cirrus coprocessor instructions. */
630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
802
803 /* VFP Fused multiply add instructions. */
804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
820
821 /* FP v5. */
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
846
847 /* Generic coprocessor instructions. */
848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
870
871 /* V6 coprocessor instructions. */
872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
878
879 /* V5 coprocessor instructions. */
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
894 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
895 };
896
897 /* Neon opcode table: This does not encode the top byte -- that is
898 checked by the print_insn_neon routine, as it depends on whether we are
899 doing thumb32 or arm32 disassembly. */
900
901 /* print_insn_neon recognizes the following format control codes:
902
903 %% %
904
905 %c print condition code
906 %u print condition code (unconditional in ARM mode,
907 UNPREDICTABLE if not AL in Thumb)
908 %A print v{st,ld}[1234] operands
909 %B print v{st,ld}[1234] any one operands
910 %C print v{st,ld}[1234] single->all operands
911 %D print scalar
912 %E print vmov, vmvn, vorr, vbic encoded constant
913 %F print vtbl,vtbx register list
914
915 %<bitfield>r print as an ARM register
916 %<bitfield>d print the bitfield in decimal
917 %<bitfield>e print the 2^N - bitfield in decimal
918 %<bitfield>D print as a NEON D register
919 %<bitfield>Q print as a NEON Q register
920 %<bitfield>R print as a NEON D or Q register
921 %<bitfield>Sn print byte scaled width limited by n
922 %<bitfield>Tn print short scaled width limited by n
923 %<bitfield>Un print long scaled width limited by n
924
925 %<bitfield>'c print specified char iff bitfield is all ones
926 %<bitfield>`c print specified char iff bitfield is all zeroes
927 %<bitfield>?ab... select from array of values in big endian order. */
928
929 static const struct opcode32 neon_opcodes[] =
930 {
931 /* Extract. */
932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
933 0xf2b00840, 0xffb00850,
934 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
936 0xf2b00000, 0xffb00810,
937 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
938
939 /* Move data element to all lanes. */
940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
945 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
946
947 /* Table lookup. */
948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
951 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
952
953 /* Half-precision conversions. */
954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
956 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
957 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
958
959 /* NEON fused multiply add instructions. */
960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
963 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
964
965 /* Two registers, miscellaneous. */
966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
969 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
983 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1005 0xf3b20300, 0xffb30fd0,
1006 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf3b30600, 0xffb30e10,
1051 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1052
1053 /* Three registers of the same length. */
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1067 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1071 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2000b00, 0xff800f10,
1132 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf2000b10, 0xff800f10,
1135 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3000b00, 0xff800f10,
1144 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf2000000, 0xfe800f10,
1147 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf2000010, 0xfe800f10,
1150 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf2000100, 0xfe800f10,
1153 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf2000200, 0xfe800f10,
1156 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf2000210, 0xfe800f10,
1159 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf2000300, 0xfe800f10,
1162 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf2000310, 0xfe800f10,
1165 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf2000400, 0xfe800f10,
1168 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2000410, 0xfe800f10,
1171 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173 0xf2000500, 0xfe800f10,
1174 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf2000510, 0xfe800f10,
1177 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf2000600, 0xfe800f10,
1180 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf2000610, 0xfe800f10,
1183 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf2000700, 0xfe800f10,
1186 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf2000710, 0xfe800f10,
1189 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf2000910, 0xfe800f10,
1192 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf2000a00, 0xfe800f10,
1195 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf2000a10, 0xfe800f10,
1198 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1200 0xf3000b10, 0xff800f10,
1201 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1203 0xf3000c10, 0xff800f10,
1204 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205
1206 /* One register and an immediate value. */
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1233
1234 /* Two registers and a shift amount. */
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf2880950, 0xfeb80fd0,
1247 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2900950, 0xfeb00fd0,
1270 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2a00950, 0xfea00fd0,
1315 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2a00e10, 0xfea00e90,
1354 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1355
1356 /* Three registers of different lengths. */
1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2800400, 0xff800f50,
1363 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2800600, 0xff800f50,
1366 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2800900, 0xff800f50,
1369 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2800b00, 0xff800f50,
1372 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2800d00, 0xff800f50,
1375 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3800400, 0xff800f50,
1378 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3800600, 0xff800f50,
1381 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800000, 0xfe800f50,
1384 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2800100, 0xfe800f50,
1387 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800200, 0xfe800f50,
1390 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2800300, 0xfe800f50,
1393 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800500, 0xfe800f50,
1396 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2800700, 0xfe800f50,
1399 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800800, 0xfe800f50,
1402 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800a00, 0xfe800f50,
1405 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800c00, 0xfe800f50,
1408 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1409
1410 /* Two registers and a scalar. */
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2800240, 0xfe800f50,
1451 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2800640, 0xfe800f50,
1454 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2800a40, 0xfe800f50,
1457 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1459 0xf2800e40, 0xff800f50,
1460 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1462 0xf2800f40, 0xff800f50,
1463 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1465 0xf3800e40, 0xff800f50,
1466 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1468 0xf3800f40, 0xff800f50,
1469 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1470 },
1471
1472 /* Element and structure load/store. */
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1511
1512 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1513 };
1514
1515 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1516 ordered: they must be searched linearly from the top to obtain a correct
1517 match. */
1518
1519 /* print_insn_arm recognizes the following format control codes:
1520
1521 %% %
1522
1523 %a print address for ldr/str instruction
1524 %s print address for ldr/str halfword/signextend instruction
1525 %S like %s but allow UNPREDICTABLE addressing
1526 %b print branch destination
1527 %c print condition code (always bits 28-31)
1528 %m print register mask for ldm/stm instruction
1529 %o print operand2 (immediate or register + shift)
1530 %p print 'p' iff bits 12-15 are 15
1531 %t print 't' iff bit 21 set and bit 24 clear
1532 %B print arm BLX(1) destination
1533 %C print the PSR sub type.
1534 %U print barrier type.
1535 %P print address for pli instruction.
1536
1537 %<bitfield>r print as an ARM register
1538 %<bitfield>T print as an ARM register + 1
1539 %<bitfield>R as %r but r15 is UNPREDICTABLE
1540 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1541 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1542 %<bitfield>d print the bitfield in decimal
1543 %<bitfield>W print the bitfield plus one in decimal
1544 %<bitfield>x print the bitfield in hex
1545 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1546
1547 %<bitfield>'c print specified char iff bitfield is all ones
1548 %<bitfield>`c print specified char iff bitfield is all zeroes
1549 %<bitfield>?ab... select from array of values in big endian order
1550
1551 %e print arm SMI operand (bits 0..7,8..19).
1552 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1553 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1554 %R print the SPSR/CPSR or banked register of an MRS. */
1555
1556 static const struct opcode32 arm_opcodes[] =
1557 {
1558 /* ARM instructions. */
1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1560 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1562 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1563
1564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1565 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1567 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1569 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1571 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1573 0x00800090, 0x0fa000f0,
1574 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1576 0x00a00090, 0x0fa000f0,
1577 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1578
1579 /* V8.2 RAS extension instructions. */
1580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
1581 0xe320f010, 0xffffffff, "esb"},
1582
1583 /* V8 instructions. */
1584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1585 0x0320f005, 0x0fffffff, "sevl"},
1586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1587 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1589 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1590 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1591 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1593 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1595 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1596 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1597 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1598 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1599 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1600 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1601 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1602 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1603 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1604 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1605 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1606 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1607 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1608 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1609 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1610 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1611 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1612 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1613 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1614 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1615 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1616 /* CRC32 instructions. */
1617 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1618 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1619 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1620 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1621 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1622 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1623 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1624 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1625 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1626 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1627 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1628 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1629
1630 /* Privileged Access Never extension instructions. */
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1632 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1633
1634 /* Virtualization Extension instructions. */
1635 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1636 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1637
1638 /* Integer Divide Extension instructions. */
1639 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1640 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1641 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1642 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1643
1644 /* MP Extension instructions. */
1645 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1646
1647 /* V7 instructions. */
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1656 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1657
1658 /* ARM V6T2 instructions. */
1659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1660 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1662 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1664 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1666 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1667
1668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1669 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1671 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1672
1673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1674 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1675 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1676 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1678 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1680 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1681
1682 /* ARM Security extension instructions. */
1683 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1684 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1685
1686 /* ARM V6K instructions. */
1687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1688 0xf57ff01f, 0xffffffff, "clrex"},
1689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1690 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1692 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1694 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1696 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1698 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1700 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1701
1702 /* ARM V6K NOP hints. */
1703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1704 0x0320f001, 0x0fffffff, "yield%c"},
1705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1706 0x0320f002, 0x0fffffff, "wfe%c"},
1707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1708 0x0320f003, 0x0fffffff, "wfi%c"},
1709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1710 0x0320f004, 0x0fffffff, "sev%c"},
1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1712 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1713
1714 /* ARM V6 instructions. */
1715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1716 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1718 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1720 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1722 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1724 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1726 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1728 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1730 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1732 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1734 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1736 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1738 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1740 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1742 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1744 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1746 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1748 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1750 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1752 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1754 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1756 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1758 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1760 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1762 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1764 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1766 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1768 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1770 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1772 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1774 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1776 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1778 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1780 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1782 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1784 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1786 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1788 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1959
1960 /* V5J instruction. */
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1962 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1963
1964 /* V5 Instructions. */
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1966 0xe1200070, 0xfff000f0,
1967 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1969 0xfa000000, 0xfe000000, "blx\t%B"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1971 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1973 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1974
1975 /* V5E "El Segundo" Instructions. */
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1977 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1979 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1981 0xf450f000, 0xfc70f000, "pld\t%a"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1983 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1985 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1987 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1989 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1990
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1992 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1994 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1995
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1997 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1999 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2001 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2003 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2004
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2006 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2008 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2010 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2012 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2013
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2015 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2017 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2018
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2020 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2022 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2024 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2026 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2027
2028 /* ARM Instructions. */
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2030 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2031
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2039 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2041 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2043 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2044
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2046 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2048 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2050 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2052 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2053
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2055 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2057 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2059 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2061 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2062
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2064 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2066 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2068 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2069
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2071 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2073 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2075 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2076
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2080 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2082 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2083
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2085 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2087 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2089 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2090
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2092 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2094 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2096 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2097
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2099 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2101 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2103 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2104
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2106 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2108 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2110 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2111
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2113 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2115 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2117 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2118
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2120 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2122 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2124 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2125
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2127 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2129 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2132
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2134 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2136 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2138 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2140 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
2141
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2145 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2147 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2148
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2152 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2154 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2155
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2159 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2161 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2162
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2164 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2172 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2174 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2176 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2177
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2184
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2186 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2188 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2190 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2191
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2195 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2196
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2198 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2199
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2204
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2206 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x092d0000, 0x0fff0000, "push%c\t%m"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2243
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2282
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2287
2288 /* The rest. */
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2290 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2293 {ARM_FEATURE_CORE_LOW (0),
2294 0x00000000, 0x00000000, 0}
2295 };
2296
2297 /* print_insn_thumb16 recognizes the following format control codes:
2298
2299 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2300 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2301 %<bitfield>I print bitfield as a signed decimal
2302 (top bit of range being the sign bit)
2303 %N print Thumb register mask (with LR)
2304 %O print Thumb register mask (with PC)
2305 %M print Thumb register mask
2306 %b print CZB's 6-bit unsigned branch destination
2307 %s print Thumb right-shift immediate (6..10; 0 == 32).
2308 %c print the condition code
2309 %C print the condition code, or "s" if not conditional
2310 %x print warning if conditional an not at end of IT block"
2311 %X print "\t; unpredictable <IT:code>" if conditional
2312 %I print IT instruction suffix and operands
2313 %W print Thumb Writeback indicator for LDMIA
2314 %<bitfield>r print bitfield as an ARM register
2315 %<bitfield>d print bitfield as a decimal
2316 %<bitfield>H print (bitfield * 2) as a decimal
2317 %<bitfield>W print (bitfield * 4) as a decimal
2318 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2319 %<bitfield>B print Thumb branch destination (signed displacement)
2320 %<bitfield>c print bitfield as a condition code
2321 %<bitnum>'c print specified char iff bit is one
2322 %<bitnum>?ab print a if bit is one else print b. */
2323
2324 static const struct opcode16 thumb_opcodes[] =
2325 {
2326 /* Thumb instructions. */
2327
2328 /* ARM V8 instructions. */
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2332
2333 /* ARM V6K no-argument instructions. */
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2340
2341 /* ARM V6T2 instructions. */
2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2343 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2345 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2347
2348 /* ARM V6. */
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2360
2361 /* ARM V5 ISA extends Thumb. */
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2363 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2364 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2366 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2367 /* ARM V4T ISA (Thumb v1). */
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2369 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2370 /* Format 4. */
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2387 /* format 13 */
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2390 /* format 5 */
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2395 /* format 14 */
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2398 /* format 2 */
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2400 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2402 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2404 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2406 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2407 /* format 8 */
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2409 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2411 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2413 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2414 /* format 7 */
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2416 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2418 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2419 /* format 1 */
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2422 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2425 /* format 3 */
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2430 /* format 6 */
2431 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2433 0x4800, 0xF800,
2434 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2435 /* format 9 */
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2437 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2439 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2441 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2443 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2444 /* format 10 */
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2446 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2448 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2449 /* format 11 */
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2451 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2453 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2454 /* format 12 */
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2456 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2458 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2459 /* format 15 */
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2462 /* format 17 */
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2464 /* format 16 */
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2468 /* format 18 */
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2470
2471 /* The E800 .. FFFF range is unconditionally redirected to the
2472 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2473 are processed via that table. Thus, we can never encounter a
2474 bare "second half of BL/BLX(1)" instruction here. */
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2476 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2477 };
2478
2479 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2480 We adopt the convention that hw1 is the high 16 bits of .value and
2481 .mask, hw2 the low 16 bits.
2482
2483 print_insn_thumb32 recognizes the following format control codes:
2484
2485 %% %
2486
2487 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2488 %M print a modified 12-bit immediate (same location)
2489 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2490 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2491 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2492 %S print a possibly-shifted Rm
2493
2494 %L print address for a ldrd/strd instruction
2495 %a print the address of a plain load/store
2496 %w print the width and signedness of a core load/store
2497 %m print register mask for ldm/stm
2498
2499 %E print the lsb and width fields of a bfc/bfi instruction
2500 %F print the lsb and width fields of a sbfx/ubfx instruction
2501 %b print a conditional branch offset
2502 %B print an unconditional branch offset
2503 %s print the shift field of an SSAT instruction
2504 %R print the rotation field of an SXT instruction
2505 %U print barrier type.
2506 %P print address for pli instruction.
2507 %c print the condition code
2508 %x print warning if conditional an not at end of IT block"
2509 %X print "\t; unpredictable <IT:code>" if conditional
2510
2511 %<bitfield>d print bitfield in decimal
2512 %<bitfield>D print bitfield plus one in decimal
2513 %<bitfield>W print bitfield*4 in decimal
2514 %<bitfield>r print bitfield as an ARM register
2515 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2516 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
2517 %<bitfield>c print bitfield as a condition code
2518
2519 %<bitfield>'c print specified char iff bitfield is all ones
2520 %<bitfield>`c print specified char iff bitfield is all zeroes
2521 %<bitfield>?ab... select from array of values in big endian order
2522
2523 With one exception at the bottom (done because BL and BLX(1) need
2524 to come dead last), this table was machine-sorted first in
2525 decreasing order of number of bits set in the mask, then in
2526 increasing numeric order of mask, then in increasing numeric order
2527 of opcode. This order is not the clearest for a human reader, but
2528 is guaranteed never to catch a special-case bit pattern with a more
2529 general mask, which is important, because this instruction encoding
2530 makes heavy use of special-case bit patterns. */
2531 static const struct opcode32 thumb32_opcodes[] =
2532 {
2533 /* V8-M instructions. */
2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2535 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2537 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2538
2539 /* ARM V8.2 RAS extension instructions. */
2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
2541 0xf3af8010, 0xffffffff, "esb"},
2542
2543 /* V8 instructions. */
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2545 0xf3af8005, 0xffffffff, "sevl%c.w"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2547 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2549 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2551 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2553 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2555 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2557 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2559 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2561 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2563 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2565 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2567 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2569 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2571 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2573 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2575 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2576
2577 /* CRC32 instructions. */
2578 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2579 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2580 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2581 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2582 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2583 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2584 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2585 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2586 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2587 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2588 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2589 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2590
2591 /* V7 instructions. */
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2600 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2602 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2603
2604 /* Virtualization Extension instructions. */
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2606 /* We skip ERET as that is SUBS pc, lr, #0. */
2607
2608 /* MP Extension instructions. */
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2610
2611 /* Security extension instructions. */
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2613
2614 /* Instructions defined in the basic V6T2 set. */
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2623
2624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2625 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2645 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2647 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2652 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2653 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2655 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2665 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2673 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2781 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2849 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xf810f000, 0xff70f000, "pld%c\t%a"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xfb100000, 0xfff000c0,
2882 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xfbc00080, 0xfff000c0,
2885 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2897 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2901 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2923 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xe9400000, 0xff500000,
2958 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xe9500000, 0xff500000,
2961 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xe8600000, 0xff700000,
2964 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xe8700000, 0xff700000,
2967 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
2972
2973 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
2982
2983 /* These have been 32-bit since the invention of Thumb. */
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2985 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2987 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
2988
2989 /* Fallback. */
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2991 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2992 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2993 };
2994
2995 static const char *const arm_conditional[] =
2996 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
2997 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
2998
2999 static const char *const arm_fp_const[] =
3000 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3001
3002 static const char *const arm_shift[] =
3003 {"lsl", "lsr", "asr", "ror"};
3004
3005 typedef struct
3006 {
3007 const char *name;
3008 const char *description;
3009 const char *reg_names[16];
3010 }
3011 arm_regname;
3012
3013 static const arm_regname regnames[] =
3014 {
3015 { "raw" , "Select raw register names",
3016 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3017 { "gcc", "Select register names used by GCC",
3018 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3019 { "std", "Select register names used in ARM's ISA documentation",
3020 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3021 { "apcs", "Select register names used in the APCS",
3022 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3023 { "atpcs", "Select register names used in the ATPCS",
3024 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3025 { "special-atpcs", "Select special register names used in the ATPCS",
3026 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3027 };
3028
3029 static const char *const iwmmxt_wwnames[] =
3030 {"b", "h", "w", "d"};
3031
3032 static const char *const iwmmxt_wwssnames[] =
3033 {"b", "bus", "bc", "bss",
3034 "h", "hus", "hc", "hss",
3035 "w", "wus", "wc", "wss",
3036 "d", "dus", "dc", "dss"
3037 };
3038
3039 static const char *const iwmmxt_regnames[] =
3040 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3041 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3042 };
3043
3044 static const char *const iwmmxt_cregnames[] =
3045 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3046 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3047 };
3048
3049 /* Default to GCC register name set. */
3050 static unsigned int regname_selected = 1;
3051
3052 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3053 #define arm_regnames regnames[regname_selected].reg_names
3054
3055 static bfd_boolean force_thumb = FALSE;
3056
3057 /* Current IT instruction state. This contains the same state as the IT
3058 bits in the CPSR. */
3059 static unsigned int ifthen_state;
3060 /* IT state for the next instruction. */
3061 static unsigned int ifthen_next_state;
3062 /* The address of the insn for which the IT state is valid. */
3063 static bfd_vma ifthen_address;
3064 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3065 /* Indicates that the current Conditional state is unconditional or outside
3066 an IT block. */
3067 #define COND_UNCOND 16
3068
3069 \f
3070 /* Functions. */
3071 int
3072 get_arm_regname_num_options (void)
3073 {
3074 return NUM_ARM_REGNAMES;
3075 }
3076
3077 int
3078 set_arm_regname_option (int option)
3079 {
3080 int old = regname_selected;
3081 regname_selected = option;
3082 return old;
3083 }
3084
3085 int
3086 get_arm_regnames (int option,
3087 const char **setname,
3088 const char **setdescription,
3089 const char *const **register_names)
3090 {
3091 *setname = regnames[option].name;
3092 *setdescription = regnames[option].description;
3093 *register_names = regnames[option].reg_names;
3094 return 16;
3095 }
3096
3097 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3098 Returns pointer to following character of the format string and
3099 fills in *VALUEP and *WIDTHP with the extracted value and number of
3100 bits extracted. WIDTHP can be NULL. */
3101
3102 static const char *
3103 arm_decode_bitfield (const char *ptr,
3104 unsigned long insn,
3105 unsigned long *valuep,
3106 int *widthp)
3107 {
3108 unsigned long value = 0;
3109 int width = 0;
3110
3111 do
3112 {
3113 int start, end;
3114 int bits;
3115
3116 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3117 start = start * 10 + *ptr - '0';
3118 if (*ptr == '-')
3119 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3120 end = end * 10 + *ptr - '0';
3121 else
3122 end = start;
3123 bits = end - start;
3124 if (bits < 0)
3125 abort ();
3126 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3127 width += bits + 1;
3128 }
3129 while (*ptr++ == ',');
3130 *valuep = value;
3131 if (widthp)
3132 *widthp = width;
3133 return ptr - 1;
3134 }
3135
3136 static void
3137 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3138 bfd_boolean print_shift)
3139 {
3140 func (stream, "%s", arm_regnames[given & 0xf]);
3141
3142 if ((given & 0xff0) != 0)
3143 {
3144 if ((given & 0x10) == 0)
3145 {
3146 int amount = (given & 0xf80) >> 7;
3147 int shift = (given & 0x60) >> 5;
3148
3149 if (amount == 0)
3150 {
3151 if (shift == 3)
3152 {
3153 func (stream, ", rrx");
3154 return;
3155 }
3156
3157 amount = 32;
3158 }
3159
3160 if (print_shift)
3161 func (stream, ", %s #%d", arm_shift[shift], amount);
3162 else
3163 func (stream, ", #%d", amount);
3164 }
3165 else if ((given & 0x80) == 0x80)
3166 func (stream, "\t; <illegal shifter operand>");
3167 else if (print_shift)
3168 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3169 arm_regnames[(given & 0xf00) >> 8]);
3170 else
3171 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3172 }
3173 }
3174
3175 #define W_BIT 21
3176 #define I_BIT 22
3177 #define U_BIT 23
3178 #define P_BIT 24
3179
3180 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3181 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3182 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3183 #define PRE_BIT_SET (given & (1 << P_BIT))
3184
3185 /* Print one coprocessor instruction on INFO->STREAM.
3186 Return TRUE if the instuction matched, FALSE if this is not a
3187 recognised coprocessor instruction. */
3188
3189 static bfd_boolean
3190 print_insn_coprocessor (bfd_vma pc,
3191 struct disassemble_info *info,
3192 long given,
3193 bfd_boolean thumb)
3194 {
3195 const struct opcode32 *insn;
3196 void *stream = info->stream;
3197 fprintf_ftype func = info->fprintf_func;
3198 unsigned long mask;
3199 unsigned long value = 0;
3200 int cond;
3201 struct arm_private_data *private_data = info->private_data;
3202 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3203
3204 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3205
3206 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3207 {
3208 unsigned long u_reg = 16;
3209 bfd_boolean is_unpredictable = FALSE;
3210 signed long value_in_comment = 0;
3211 const char *c;
3212
3213 if (ARM_FEATURE_ZERO (insn->arch))
3214 switch (insn->value)
3215 {
3216 case SENTINEL_IWMMXT_START:
3217 if (info->mach != bfd_mach_arm_XScale
3218 && info->mach != bfd_mach_arm_iWMMXt
3219 && info->mach != bfd_mach_arm_iWMMXt2)
3220 do
3221 insn++;
3222 while ((! ARM_FEATURE_ZERO (insn->arch))
3223 && insn->value != SENTINEL_IWMMXT_END);
3224 continue;
3225
3226 case SENTINEL_IWMMXT_END:
3227 continue;
3228
3229 case SENTINEL_GENERIC_START:
3230 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3231 continue;
3232
3233 default:
3234 abort ();
3235 }
3236
3237 mask = insn->mask;
3238 value = insn->value;
3239 if (thumb)
3240 {
3241 /* The high 4 bits are 0xe for Arm conditional instructions, and
3242 0xe for arm unconditional instructions. The rest of the
3243 encoding is the same. */
3244 mask |= 0xf0000000;
3245 value |= 0xe0000000;
3246 if (ifthen_state)
3247 cond = IFTHEN_COND;
3248 else
3249 cond = COND_UNCOND;
3250 }
3251 else
3252 {
3253 /* Only match unconditional instuctions against unconditional
3254 patterns. */
3255 if ((given & 0xf0000000) == 0xf0000000)
3256 {
3257 mask |= 0xf0000000;
3258 cond = COND_UNCOND;
3259 }
3260 else
3261 {
3262 cond = (given >> 28) & 0xf;
3263 if (cond == 0xe)
3264 cond = COND_UNCOND;
3265 }
3266 }
3267
3268 if ((given & mask) != value)
3269 continue;
3270
3271 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3272 continue;
3273
3274 for (c = insn->assembler; *c; c++)
3275 {
3276 if (*c == '%')
3277 {
3278 switch (*++c)
3279 {
3280 case '%':
3281 func (stream, "%%");
3282 break;
3283
3284 case 'A':
3285 {
3286 int rn = (given >> 16) & 0xf;
3287 bfd_vma offset = given & 0xff;
3288
3289 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3290
3291 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3292 {
3293 /* Not unindexed. The offset is scaled. */
3294 offset = offset * 4;
3295 if (NEGATIVE_BIT_SET)
3296 offset = - offset;
3297 if (rn != 15)
3298 value_in_comment = offset;
3299 }
3300
3301 if (PRE_BIT_SET)
3302 {
3303 if (offset)
3304 func (stream, ", #%d]%s",
3305 (int) offset,
3306 WRITEBACK_BIT_SET ? "!" : "");
3307 else if (NEGATIVE_BIT_SET)
3308 func (stream, ", #-0]");
3309 else
3310 func (stream, "]");
3311 }
3312 else
3313 {
3314 func (stream, "]");
3315
3316 if (WRITEBACK_BIT_SET)
3317 {
3318 if (offset)
3319 func (stream, ", #%d", (int) offset);
3320 else if (NEGATIVE_BIT_SET)
3321 func (stream, ", #-0");
3322 }
3323 else
3324 {
3325 func (stream, ", {%s%d}",
3326 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3327 (int) offset);
3328 value_in_comment = offset;
3329 }
3330 }
3331 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3332 {
3333 func (stream, "\t; ");
3334 /* For unaligned PCs, apply off-by-alignment
3335 correction. */
3336 info->print_address_func (offset + pc
3337 + info->bytes_per_chunk * 2
3338 - (pc & 3),
3339 info);
3340 }
3341 }
3342 break;
3343
3344 case 'B':
3345 {
3346 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3347 int offset = (given >> 1) & 0x3f;
3348
3349 if (offset == 1)
3350 func (stream, "{d%d}", regno);
3351 else if (regno + offset > 32)
3352 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3353 else
3354 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3355 }
3356 break;
3357
3358 case 'u':
3359 if (cond != COND_UNCOND)
3360 is_unpredictable = TRUE;
3361
3362 /* Fall through. */
3363 case 'c':
3364 func (stream, "%s", arm_conditional[cond]);
3365 break;
3366
3367 case 'I':
3368 /* Print a Cirrus/DSP shift immediate. */
3369 /* Immediates are 7bit signed ints with bits 0..3 in
3370 bits 0..3 of opcode and bits 4..6 in bits 5..7
3371 of opcode. */
3372 {
3373 int imm;
3374
3375 imm = (given & 0xf) | ((given & 0xe0) >> 1);
3376
3377 /* Is ``imm'' a negative number? */
3378 if (imm & 0x40)
3379 imm -= 0x80;
3380
3381 func (stream, "%d", imm);
3382 }
3383
3384 break;
3385
3386 case 'F':
3387 switch (given & 0x00408000)
3388 {
3389 case 0:
3390 func (stream, "4");
3391 break;
3392 case 0x8000:
3393 func (stream, "1");
3394 break;
3395 case 0x00400000:
3396 func (stream, "2");
3397 break;
3398 default:
3399 func (stream, "3");
3400 }
3401 break;
3402
3403 case 'P':
3404 switch (given & 0x00080080)
3405 {
3406 case 0:
3407 func (stream, "s");
3408 break;
3409 case 0x80:
3410 func (stream, "d");
3411 break;
3412 case 0x00080000:
3413 func (stream, "e");
3414 break;
3415 default:
3416 func (stream, _("<illegal precision>"));
3417 break;
3418 }
3419 break;
3420
3421 case 'Q':
3422 switch (given & 0x00408000)
3423 {
3424 case 0:
3425 func (stream, "s");
3426 break;
3427 case 0x8000:
3428 func (stream, "d");
3429 break;
3430 case 0x00400000:
3431 func (stream, "e");
3432 break;
3433 default:
3434 func (stream, "p");
3435 break;
3436 }
3437 break;
3438
3439 case 'R':
3440 switch (given & 0x60)
3441 {
3442 case 0:
3443 break;
3444 case 0x20:
3445 func (stream, "p");
3446 break;
3447 case 0x40:
3448 func (stream, "m");
3449 break;
3450 default:
3451 func (stream, "z");
3452 break;
3453 }
3454 break;
3455
3456 case '0': case '1': case '2': case '3': case '4':
3457 case '5': case '6': case '7': case '8': case '9':
3458 {
3459 int width;
3460
3461 c = arm_decode_bitfield (c, given, &value, &width);
3462
3463 switch (*c)
3464 {
3465 case 'R':
3466 if (value == 15)
3467 is_unpredictable = TRUE;
3468 /* Fall through. */
3469 case 'r':
3470 if (c[1] == 'u')
3471 {
3472 /* Eat the 'u' character. */
3473 ++ c;
3474
3475 if (u_reg == value)
3476 is_unpredictable = TRUE;
3477 u_reg = value;
3478 }
3479 func (stream, "%s", arm_regnames[value]);
3480 break;
3481 case 'D':
3482 func (stream, "d%ld", value);
3483 break;
3484 case 'Q':
3485 if (value & 1)
3486 func (stream, "<illegal reg q%ld.5>", value >> 1);
3487 else
3488 func (stream, "q%ld", value >> 1);
3489 break;
3490 case 'd':
3491 func (stream, "%ld", value);
3492 value_in_comment = value;
3493 break;
3494 case 'E':
3495 {
3496 /* Converts immediate 8 bit back to float value. */
3497 unsigned floatVal = (value & 0x80) << 24
3498 | (value & 0x3F) << 19
3499 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3500
3501 /* Quarter float have a maximum value of 31.0.
3502 Get floating point value multiplied by 1e7.
3503 The maximum value stays in limit of a 32-bit int. */
3504 unsigned decVal =
3505 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3506 (16 + (value & 0xF));
3507
3508 if (!(decVal % 1000000))
3509 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3510 floatVal, value & 0x80 ? '-' : ' ',
3511 decVal / 10000000,
3512 decVal % 10000000 / 1000000);
3513 else if (!(decVal % 10000))
3514 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3515 floatVal, value & 0x80 ? '-' : ' ',
3516 decVal / 10000000,
3517 decVal % 10000000 / 10000);
3518 else
3519 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3520 floatVal, value & 0x80 ? '-' : ' ',
3521 decVal / 10000000, decVal % 10000000);
3522 break;
3523 }
3524 case 'k':
3525 {
3526 int from = (given & (1 << 7)) ? 32 : 16;
3527 func (stream, "%ld", from - value);
3528 }
3529 break;
3530
3531 case 'f':
3532 if (value > 7)
3533 func (stream, "#%s", arm_fp_const[value & 7]);
3534 else
3535 func (stream, "f%ld", value);
3536 break;
3537
3538 case 'w':
3539 if (width == 2)
3540 func (stream, "%s", iwmmxt_wwnames[value]);
3541 else
3542 func (stream, "%s", iwmmxt_wwssnames[value]);
3543 break;
3544
3545 case 'g':
3546 func (stream, "%s", iwmmxt_regnames[value]);
3547 break;
3548 case 'G':
3549 func (stream, "%s", iwmmxt_cregnames[value]);
3550 break;
3551
3552 case 'x':
3553 func (stream, "0x%lx", (value & 0xffffffffUL));
3554 break;
3555
3556 case 'c':
3557 switch (value)
3558 {
3559 case 0:
3560 func (stream, "eq");
3561 break;
3562
3563 case 1:
3564 func (stream, "vs");
3565 break;
3566
3567 case 2:
3568 func (stream, "ge");
3569 break;
3570
3571 case 3:
3572 func (stream, "gt");
3573 break;
3574
3575 default:
3576 func (stream, "??");
3577 break;
3578 }
3579 break;
3580
3581 case '`':
3582 c++;
3583 if (value == 0)
3584 func (stream, "%c", *c);
3585 break;
3586 case '\'':
3587 c++;
3588 if (value == ((1ul << width) - 1))
3589 func (stream, "%c", *c);
3590 break;
3591 case '?':
3592 func (stream, "%c", c[(1 << width) - (int) value]);
3593 c += 1 << width;
3594 break;
3595 default:
3596 abort ();
3597 }
3598 break;
3599
3600 case 'y':
3601 case 'z':
3602 {
3603 int single = *c++ == 'y';
3604 int regno;
3605
3606 switch (*c)
3607 {
3608 case '4': /* Sm pair */
3609 case '0': /* Sm, Dm */
3610 regno = given & 0x0000000f;
3611 if (single)
3612 {
3613 regno <<= 1;
3614 regno += (given >> 5) & 1;
3615 }
3616 else
3617 regno += ((given >> 5) & 1) << 4;
3618 break;
3619
3620 case '1': /* Sd, Dd */
3621 regno = (given >> 12) & 0x0000000f;
3622 if (single)
3623 {
3624 regno <<= 1;
3625 regno += (given >> 22) & 1;
3626 }
3627 else
3628 regno += ((given >> 22) & 1) << 4;
3629 break;
3630
3631 case '2': /* Sn, Dn */
3632 regno = (given >> 16) & 0x0000000f;
3633 if (single)
3634 {
3635 regno <<= 1;
3636 regno += (given >> 7) & 1;
3637 }
3638 else
3639 regno += ((given >> 7) & 1) << 4;
3640 break;
3641
3642 case '3': /* List */
3643 func (stream, "{");
3644 regno = (given >> 12) & 0x0000000f;
3645 if (single)
3646 {
3647 regno <<= 1;
3648 regno += (given >> 22) & 1;
3649 }
3650 else
3651 regno += ((given >> 22) & 1) << 4;
3652 break;
3653
3654 default:
3655 abort ();
3656 }
3657
3658 func (stream, "%c%d", single ? 's' : 'd', regno);
3659
3660 if (*c == '3')
3661 {
3662 int count = given & 0xff;
3663
3664 if (single == 0)
3665 count >>= 1;
3666
3667 if (--count)
3668 {
3669 func (stream, "-%c%d",
3670 single ? 's' : 'd',
3671 regno + count);
3672 }
3673
3674 func (stream, "}");
3675 }
3676 else if (*c == '4')
3677 func (stream, ", %c%d", single ? 's' : 'd',
3678 regno + 1);
3679 }
3680 break;
3681
3682 case 'L':
3683 switch (given & 0x00400100)
3684 {
3685 case 0x00000000: func (stream, "b"); break;
3686 case 0x00400000: func (stream, "h"); break;
3687 case 0x00000100: func (stream, "w"); break;
3688 case 0x00400100: func (stream, "d"); break;
3689 default:
3690 break;
3691 }
3692 break;
3693
3694 case 'Z':
3695 {
3696 /* given (20, 23) | given (0, 3) */
3697 value = ((given >> 16) & 0xf0) | (given & 0xf);
3698 func (stream, "%d", (int) value);
3699 }
3700 break;
3701
3702 case 'l':
3703 /* This is like the 'A' operator, except that if
3704 the width field "M" is zero, then the offset is
3705 *not* multiplied by four. */
3706 {
3707 int offset = given & 0xff;
3708 int multiplier = (given & 0x00000100) ? 4 : 1;
3709
3710 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3711
3712 if (multiplier > 1)
3713 {
3714 value_in_comment = offset * multiplier;
3715 if (NEGATIVE_BIT_SET)
3716 value_in_comment = - value_in_comment;
3717 }
3718
3719 if (offset)
3720 {
3721 if (PRE_BIT_SET)
3722 func (stream, ", #%s%d]%s",
3723 NEGATIVE_BIT_SET ? "-" : "",
3724 offset * multiplier,
3725 WRITEBACK_BIT_SET ? "!" : "");
3726 else
3727 func (stream, "], #%s%d",
3728 NEGATIVE_BIT_SET ? "-" : "",
3729 offset * multiplier);
3730 }
3731 else
3732 func (stream, "]");
3733 }
3734 break;
3735
3736 case 'r':
3737 {
3738 int imm4 = (given >> 4) & 0xf;
3739 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3740 int ubit = ! NEGATIVE_BIT_SET;
3741 const char *rm = arm_regnames [given & 0xf];
3742 const char *rn = arm_regnames [(given >> 16) & 0xf];
3743
3744 switch (puw_bits)
3745 {
3746 case 1:
3747 case 3:
3748 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3749 if (imm4)
3750 func (stream, ", lsl #%d", imm4);
3751 break;
3752
3753 case 4:
3754 case 5:
3755 case 6:
3756 case 7:
3757 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3758 if (imm4 > 0)
3759 func (stream, ", lsl #%d", imm4);
3760 func (stream, "]");
3761 if (puw_bits == 5 || puw_bits == 7)
3762 func (stream, "!");
3763 break;
3764
3765 default:
3766 func (stream, "INVALID");
3767 }
3768 }
3769 break;
3770
3771 case 'i':
3772 {
3773 long imm5;
3774 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3775 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3776 }
3777 break;
3778
3779 default:
3780 abort ();
3781 }
3782 }
3783 }
3784 else
3785 func (stream, "%c", *c);
3786 }
3787
3788 if (value_in_comment > 32 || value_in_comment < -16)
3789 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3790
3791 if (is_unpredictable)
3792 func (stream, UNPREDICTABLE_INSTRUCTION);
3793
3794 return TRUE;
3795 }
3796 return FALSE;
3797 }
3798
3799 /* Decodes and prints ARM addressing modes. Returns the offset
3800 used in the address, if any, if it is worthwhile printing the
3801 offset as a hexadecimal value in a comment at the end of the
3802 line of disassembly. */
3803
3804 static signed long
3805 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3806 {
3807 void *stream = info->stream;
3808 fprintf_ftype func = info->fprintf_func;
3809 bfd_vma offset = 0;
3810
3811 if (((given & 0x000f0000) == 0x000f0000)
3812 && ((given & 0x02000000) == 0))
3813 {
3814 offset = given & 0xfff;
3815
3816 func (stream, "[pc");
3817
3818 if (PRE_BIT_SET)
3819 {
3820 /* Pre-indexed. Elide offset of positive zero when
3821 non-writeback. */
3822 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3823 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3824
3825 if (NEGATIVE_BIT_SET)
3826 offset = -offset;
3827
3828 offset += pc + 8;
3829
3830 /* Cope with the possibility of write-back
3831 being used. Probably a very dangerous thing
3832 for the programmer to do, but who are we to
3833 argue ? */
3834 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
3835 }
3836 else /* Post indexed. */
3837 {
3838 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3839
3840 /* Ie ignore the offset. */
3841 offset = pc + 8;
3842 }
3843
3844 func (stream, "\t; ");
3845 info->print_address_func (offset, info);
3846 offset = 0;
3847 }
3848 else
3849 {
3850 func (stream, "[%s",
3851 arm_regnames[(given >> 16) & 0xf]);
3852
3853 if (PRE_BIT_SET)
3854 {
3855 if ((given & 0x02000000) == 0)
3856 {
3857 /* Elide offset of positive zero when non-writeback. */
3858 offset = given & 0xfff;
3859 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3860 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3861 }
3862 else
3863 {
3864 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
3865 arm_decode_shift (given, func, stream, TRUE);
3866 }
3867
3868 func (stream, "]%s",
3869 WRITEBACK_BIT_SET ? "!" : "");
3870 }
3871 else
3872 {
3873 if ((given & 0x02000000) == 0)
3874 {
3875 /* Always show offset. */
3876 offset = given & 0xfff;
3877 func (stream, "], #%s%d",
3878 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3879 }
3880 else
3881 {
3882 func (stream, "], %s",
3883 NEGATIVE_BIT_SET ? "-" : "");
3884 arm_decode_shift (given, func, stream, TRUE);
3885 }
3886 }
3887 if (NEGATIVE_BIT_SET)
3888 offset = -offset;
3889 }
3890
3891 return (signed long) offset;
3892 }
3893
3894 /* Print one neon instruction on INFO->STREAM.
3895 Return TRUE if the instuction matched, FALSE if this is not a
3896 recognised neon instruction. */
3897
3898 static bfd_boolean
3899 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3900 {
3901 const struct opcode32 *insn;
3902 void *stream = info->stream;
3903 fprintf_ftype func = info->fprintf_func;
3904
3905 if (thumb)
3906 {
3907 if ((given & 0xef000000) == 0xef000000)
3908 {
3909 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
3910 unsigned long bit28 = given & (1 << 28);
3911
3912 given &= 0x00ffffff;
3913 if (bit28)
3914 given |= 0xf3000000;
3915 else
3916 given |= 0xf2000000;
3917 }
3918 else if ((given & 0xff000000) == 0xf9000000)
3919 given ^= 0xf9000000 ^ 0xf4000000;
3920 else
3921 return FALSE;
3922 }
3923
3924 for (insn = neon_opcodes; insn->assembler; insn++)
3925 {
3926 if ((given & insn->mask) == insn->value)
3927 {
3928 signed long value_in_comment = 0;
3929 bfd_boolean is_unpredictable = FALSE;
3930 const char *c;
3931
3932 for (c = insn->assembler; *c; c++)
3933 {
3934 if (*c == '%')
3935 {
3936 switch (*++c)
3937 {
3938 case '%':
3939 func (stream, "%%");
3940 break;
3941
3942 case 'u':
3943 if (thumb && ifthen_state)
3944 is_unpredictable = TRUE;
3945
3946 /* Fall through. */
3947 case 'c':
3948 if (thumb && ifthen_state)
3949 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3950 break;
3951
3952 case 'A':
3953 {
3954 static const unsigned char enc[16] =
3955 {
3956 0x4, 0x14, /* st4 0,1 */
3957 0x4, /* st1 2 */
3958 0x4, /* st2 3 */
3959 0x3, /* st3 4 */
3960 0x13, /* st3 5 */
3961 0x3, /* st1 6 */
3962 0x1, /* st1 7 */
3963 0x2, /* st2 8 */
3964 0x12, /* st2 9 */
3965 0x2, /* st1 10 */
3966 0, 0, 0, 0, 0
3967 };
3968 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3969 int rn = ((given >> 16) & 0xf);
3970 int rm = ((given >> 0) & 0xf);
3971 int align = ((given >> 4) & 0x3);
3972 int type = ((given >> 8) & 0xf);
3973 int n = enc[type] & 0xf;
3974 int stride = (enc[type] >> 4) + 1;
3975 int ix;
3976
3977 func (stream, "{");
3978 if (stride > 1)
3979 for (ix = 0; ix != n; ix++)
3980 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3981 else if (n == 1)
3982 func (stream, "d%d", rd);
3983 else
3984 func (stream, "d%d-d%d", rd, rd + n - 1);
3985 func (stream, "}, [%s", arm_regnames[rn]);
3986 if (align)
3987 func (stream, " :%d", 32 << align);
3988 func (stream, "]");
3989 if (rm == 0xd)
3990 func (stream, "!");
3991 else if (rm != 0xf)
3992 func (stream, ", %s", arm_regnames[rm]);
3993 }
3994 break;
3995
3996 case 'B':
3997 {
3998 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3999 int rn = ((given >> 16) & 0xf);
4000 int rm = ((given >> 0) & 0xf);
4001 int idx_align = ((given >> 4) & 0xf);
4002 int align = 0;
4003 int size = ((given >> 10) & 0x3);
4004 int idx = idx_align >> (size + 1);
4005 int length = ((given >> 8) & 3) + 1;
4006 int stride = 1;
4007 int i;
4008
4009 if (length > 1 && size > 0)
4010 stride = (idx_align & (1 << size)) ? 2 : 1;
4011
4012 switch (length)
4013 {
4014 case 1:
4015 {
4016 int amask = (1 << size) - 1;
4017 if ((idx_align & (1 << size)) != 0)
4018 return FALSE;
4019 if (size > 0)
4020 {
4021 if ((idx_align & amask) == amask)
4022 align = 8 << size;
4023 else if ((idx_align & amask) != 0)
4024 return FALSE;
4025 }
4026 }
4027 break;
4028
4029 case 2:
4030 if (size == 2 && (idx_align & 2) != 0)
4031 return FALSE;
4032 align = (idx_align & 1) ? 16 << size : 0;
4033 break;
4034
4035 case 3:
4036 if ((size == 2 && (idx_align & 3) != 0)
4037 || (idx_align & 1) != 0)
4038 return FALSE;
4039 break;
4040
4041 case 4:
4042 if (size == 2)
4043 {
4044 if ((idx_align & 3) == 3)
4045 return FALSE;
4046 align = (idx_align & 3) * 64;
4047 }
4048 else
4049 align = (idx_align & 1) ? 32 << size : 0;
4050 break;
4051
4052 default:
4053 abort ();
4054 }
4055
4056 func (stream, "{");
4057 for (i = 0; i < length; i++)
4058 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4059 rd + i * stride, idx);
4060 func (stream, "}, [%s", arm_regnames[rn]);
4061 if (align)
4062 func (stream, " :%d", align);
4063 func (stream, "]");
4064 if (rm == 0xd)
4065 func (stream, "!");
4066 else if (rm != 0xf)
4067 func (stream, ", %s", arm_regnames[rm]);
4068 }
4069 break;
4070
4071 case 'C':
4072 {
4073 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4074 int rn = ((given >> 16) & 0xf);
4075 int rm = ((given >> 0) & 0xf);
4076 int align = ((given >> 4) & 0x1);
4077 int size = ((given >> 6) & 0x3);
4078 int type = ((given >> 8) & 0x3);
4079 int n = type + 1;
4080 int stride = ((given >> 5) & 0x1);
4081 int ix;
4082
4083 if (stride && (n == 1))
4084 n++;
4085 else
4086 stride++;
4087
4088 func (stream, "{");
4089 if (stride > 1)
4090 for (ix = 0; ix != n; ix++)
4091 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4092 else if (n == 1)
4093 func (stream, "d%d[]", rd);
4094 else
4095 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4096 func (stream, "}, [%s", arm_regnames[rn]);
4097 if (align)
4098 {
4099 align = (8 * (type + 1)) << size;
4100 if (type == 3)
4101 align = (size > 1) ? align >> 1 : align;
4102 if (type == 2 || (type == 0 && !size))
4103 func (stream, " :<bad align %d>", align);
4104 else
4105 func (stream, " :%d", align);
4106 }
4107 func (stream, "]");
4108 if (rm == 0xd)
4109 func (stream, "!");
4110 else if (rm != 0xf)
4111 func (stream, ", %s", arm_regnames[rm]);
4112 }
4113 break;
4114
4115 case 'D':
4116 {
4117 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4118 int size = (given >> 20) & 3;
4119 int reg = raw_reg & ((4 << size) - 1);
4120 int ix = raw_reg >> size >> 2;
4121
4122 func (stream, "d%d[%d]", reg, ix);
4123 }
4124 break;
4125
4126 case 'E':
4127 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4128 {
4129 int bits = 0;
4130 int cmode = (given >> 8) & 0xf;
4131 int op = (given >> 5) & 0x1;
4132 unsigned long value = 0, hival = 0;
4133 unsigned shift;
4134 int size = 0;
4135 int isfloat = 0;
4136
4137 bits |= ((given >> 24) & 1) << 7;
4138 bits |= ((given >> 16) & 7) << 4;
4139 bits |= ((given >> 0) & 15) << 0;
4140
4141 if (cmode < 8)
4142 {
4143 shift = (cmode >> 1) & 3;
4144 value = (unsigned long) bits << (8 * shift);
4145 size = 32;
4146 }
4147 else if (cmode < 12)
4148 {
4149 shift = (cmode >> 1) & 1;
4150 value = (unsigned long) bits << (8 * shift);
4151 size = 16;
4152 }
4153 else if (cmode < 14)
4154 {
4155 shift = (cmode & 1) + 1;
4156 value = (unsigned long) bits << (8 * shift);
4157 value |= (1ul << (8 * shift)) - 1;
4158 size = 32;
4159 }
4160 else if (cmode == 14)
4161 {
4162 if (op)
4163 {
4164 /* Bit replication into bytes. */
4165 int ix;
4166 unsigned long mask;
4167
4168 value = 0;
4169 hival = 0;
4170 for (ix = 7; ix >= 0; ix--)
4171 {
4172 mask = ((bits >> ix) & 1) ? 0xff : 0;
4173 if (ix <= 3)
4174 value = (value << 8) | mask;
4175 else
4176 hival = (hival << 8) | mask;
4177 }
4178 size = 64;
4179 }
4180 else
4181 {
4182 /* Byte replication. */
4183 value = (unsigned long) bits;
4184 size = 8;
4185 }
4186 }
4187 else if (!op)
4188 {
4189 /* Floating point encoding. */
4190 int tmp;
4191
4192 value = (unsigned long) (bits & 0x7f) << 19;
4193 value |= (unsigned long) (bits & 0x80) << 24;
4194 tmp = bits & 0x40 ? 0x3c : 0x40;
4195 value |= (unsigned long) tmp << 24;
4196 size = 32;
4197 isfloat = 1;
4198 }
4199 else
4200 {
4201 func (stream, "<illegal constant %.8x:%x:%x>",
4202 bits, cmode, op);
4203 size = 32;
4204 break;
4205 }
4206 switch (size)
4207 {
4208 case 8:
4209 func (stream, "#%ld\t; 0x%.2lx", value, value);
4210 break;
4211
4212 case 16:
4213 func (stream, "#%ld\t; 0x%.4lx", value, value);
4214 break;
4215
4216 case 32:
4217 if (isfloat)
4218 {
4219 unsigned char valbytes[4];
4220 double fvalue;
4221
4222 /* Do this a byte at a time so we don't have to
4223 worry about the host's endianness. */
4224 valbytes[0] = value & 0xff;
4225 valbytes[1] = (value >> 8) & 0xff;
4226 valbytes[2] = (value >> 16) & 0xff;
4227 valbytes[3] = (value >> 24) & 0xff;
4228
4229 floatformat_to_double
4230 (& floatformat_ieee_single_little, valbytes,
4231 & fvalue);
4232
4233 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4234 value);
4235 }
4236 else
4237 func (stream, "#%ld\t; 0x%.8lx",
4238 (long) (((value & 0x80000000L) != 0)
4239 ? value | ~0xffffffffL : value),
4240 value);
4241 break;
4242
4243 case 64:
4244 func (stream, "#0x%.8lx%.8lx", hival, value);
4245 break;
4246
4247 default:
4248 abort ();
4249 }
4250 }
4251 break;
4252
4253 case 'F':
4254 {
4255 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4256 int num = (given >> 8) & 0x3;
4257
4258 if (!num)
4259 func (stream, "{d%d}", regno);
4260 else if (num + regno >= 32)
4261 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4262 else
4263 func (stream, "{d%d-d%d}", regno, regno + num);
4264 }
4265 break;
4266
4267
4268 case '0': case '1': case '2': case '3': case '4':
4269 case '5': case '6': case '7': case '8': case '9':
4270 {
4271 int width;
4272 unsigned long value;
4273
4274 c = arm_decode_bitfield (c, given, &value, &width);
4275
4276 switch (*c)
4277 {
4278 case 'r':
4279 func (stream, "%s", arm_regnames[value]);
4280 break;
4281 case 'd':
4282 func (stream, "%ld", value);
4283 value_in_comment = value;
4284 break;
4285 case 'e':
4286 func (stream, "%ld", (1ul << width) - value);
4287 break;
4288
4289 case 'S':
4290 case 'T':
4291 case 'U':
4292 /* Various width encodings. */
4293 {
4294 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4295 int limit;
4296 unsigned low, high;
4297
4298 c++;
4299 if (*c >= '0' && *c <= '9')
4300 limit = *c - '0';
4301 else if (*c >= 'a' && *c <= 'f')
4302 limit = *c - 'a' + 10;
4303 else
4304 abort ();
4305 low = limit >> 2;
4306 high = limit & 3;
4307
4308 if (value < low || value > high)
4309 func (stream, "<illegal width %d>", base << value);
4310 else
4311 func (stream, "%d", base << value);
4312 }
4313 break;
4314 case 'R':
4315 if (given & (1 << 6))
4316 goto Q;
4317 /* FALLTHROUGH */
4318 case 'D':
4319 func (stream, "d%ld", value);
4320 break;
4321 case 'Q':
4322 Q:
4323 if (value & 1)
4324 func (stream, "<illegal reg q%ld.5>", value >> 1);
4325 else
4326 func (stream, "q%ld", value >> 1);
4327 break;
4328
4329 case '`':
4330 c++;
4331 if (value == 0)
4332 func (stream, "%c", *c);
4333 break;
4334 case '\'':
4335 c++;
4336 if (value == ((1ul << width) - 1))
4337 func (stream, "%c", *c);
4338 break;
4339 case '?':
4340 func (stream, "%c", c[(1 << width) - (int) value]);
4341 c += 1 << width;
4342 break;
4343 default:
4344 abort ();
4345 }
4346 break;
4347
4348 default:
4349 abort ();
4350 }
4351 }
4352 }
4353 else
4354 func (stream, "%c", *c);
4355 }
4356
4357 if (value_in_comment > 32 || value_in_comment < -16)
4358 func (stream, "\t; 0x%lx", value_in_comment);
4359
4360 if (is_unpredictable)
4361 func (stream, UNPREDICTABLE_INSTRUCTION);
4362
4363 return TRUE;
4364 }
4365 }
4366 return FALSE;
4367 }
4368
4369 /* Return the name of a v7A special register. */
4370
4371 static const char *
4372 banked_regname (unsigned reg)
4373 {
4374 switch (reg)
4375 {
4376 case 15: return "CPSR";
4377 case 32: return "R8_usr";
4378 case 33: return "R9_usr";
4379 case 34: return "R10_usr";
4380 case 35: return "R11_usr";
4381 case 36: return "R12_usr";
4382 case 37: return "SP_usr";
4383 case 38: return "LR_usr";
4384 case 40: return "R8_fiq";
4385 case 41: return "R9_fiq";
4386 case 42: return "R10_fiq";
4387 case 43: return "R11_fiq";
4388 case 44: return "R12_fiq";
4389 case 45: return "SP_fiq";
4390 case 46: return "LR_fiq";
4391 case 48: return "LR_irq";
4392 case 49: return "SP_irq";
4393 case 50: return "LR_svc";
4394 case 51: return "SP_svc";
4395 case 52: return "LR_abt";
4396 case 53: return "SP_abt";
4397 case 54: return "LR_und";
4398 case 55: return "SP_und";
4399 case 60: return "LR_mon";
4400 case 61: return "SP_mon";
4401 case 62: return "ELR_hyp";
4402 case 63: return "SP_hyp";
4403 case 79: return "SPSR";
4404 case 110: return "SPSR_fiq";
4405 case 112: return "SPSR_irq";
4406 case 114: return "SPSR_svc";
4407 case 116: return "SPSR_abt";
4408 case 118: return "SPSR_und";
4409 case 124: return "SPSR_mon";
4410 case 126: return "SPSR_hyp";
4411 default: return NULL;
4412 }
4413 }
4414
4415 /* Return the name of the DMB/DSB option. */
4416 static const char *
4417 data_barrier_option (unsigned option)
4418 {
4419 switch (option & 0xf)
4420 {
4421 case 0xf: return "sy";
4422 case 0xe: return "st";
4423 case 0xd: return "ld";
4424 case 0xb: return "ish";
4425 case 0xa: return "ishst";
4426 case 0x9: return "ishld";
4427 case 0x7: return "un";
4428 case 0x6: return "unst";
4429 case 0x5: return "nshld";
4430 case 0x3: return "osh";
4431 case 0x2: return "oshst";
4432 case 0x1: return "oshld";
4433 default: return NULL;
4434 }
4435 }
4436
4437 /* Print one ARM instruction from PC on INFO->STREAM. */
4438
4439 static void
4440 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4441 {
4442 const struct opcode32 *insn;
4443 void *stream = info->stream;
4444 fprintf_ftype func = info->fprintf_func;
4445 struct arm_private_data *private_data = info->private_data;
4446
4447 if (print_insn_coprocessor (pc, info, given, FALSE))
4448 return;
4449
4450 if (print_insn_neon (info, given, FALSE))
4451 return;
4452
4453 for (insn = arm_opcodes; insn->assembler; insn++)
4454 {
4455 if ((given & insn->mask) != insn->value)
4456 continue;
4457
4458 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4459 continue;
4460
4461 /* Special case: an instruction with all bits set in the condition field
4462 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4463 or by the catchall at the end of the table. */
4464 if ((given & 0xF0000000) != 0xF0000000
4465 || (insn->mask & 0xF0000000) == 0xF0000000
4466 || (insn->mask == 0 && insn->value == 0))
4467 {
4468 unsigned long u_reg = 16;
4469 unsigned long U_reg = 16;
4470 bfd_boolean is_unpredictable = FALSE;
4471 signed long value_in_comment = 0;
4472 const char *c;
4473
4474 for (c = insn->assembler; *c; c++)
4475 {
4476 if (*c == '%')
4477 {
4478 bfd_boolean allow_unpredictable = FALSE;
4479
4480 switch (*++c)
4481 {
4482 case '%':
4483 func (stream, "%%");
4484 break;
4485
4486 case 'a':
4487 value_in_comment = print_arm_address (pc, info, given);
4488 break;
4489
4490 case 'P':
4491 /* Set P address bit and use normal address
4492 printing routine. */
4493 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4494 break;
4495
4496 case 'S':
4497 allow_unpredictable = TRUE;
4498 case 's':
4499 if ((given & 0x004f0000) == 0x004f0000)
4500 {
4501 /* PC relative with immediate offset. */
4502 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4503
4504 if (PRE_BIT_SET)
4505 {
4506 /* Elide positive zero offset. */
4507 if (offset || NEGATIVE_BIT_SET)
4508 func (stream, "[pc, #%s%d]\t; ",
4509 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4510 else
4511 func (stream, "[pc]\t; ");
4512 if (NEGATIVE_BIT_SET)
4513 offset = -offset;
4514 info->print_address_func (offset + pc + 8, info);
4515 }
4516 else
4517 {
4518 /* Always show the offset. */
4519 func (stream, "[pc], #%s%d",
4520 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4521 if (! allow_unpredictable)
4522 is_unpredictable = TRUE;
4523 }
4524 }
4525 else
4526 {
4527 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4528
4529 func (stream, "[%s",
4530 arm_regnames[(given >> 16) & 0xf]);
4531
4532 if (PRE_BIT_SET)
4533 {
4534 if (IMMEDIATE_BIT_SET)
4535 {
4536 /* Elide offset for non-writeback
4537 positive zero. */
4538 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4539 || offset)
4540 func (stream, ", #%s%d",
4541 NEGATIVE_BIT_SET ? "-" : "", offset);
4542
4543 if (NEGATIVE_BIT_SET)
4544 offset = -offset;
4545
4546 value_in_comment = offset;
4547 }
4548 else
4549 {
4550 /* Register Offset or Register Pre-Indexed. */
4551 func (stream, ", %s%s",
4552 NEGATIVE_BIT_SET ? "-" : "",
4553 arm_regnames[given & 0xf]);
4554
4555 /* Writing back to the register that is the source/
4556 destination of the load/store is unpredictable. */
4557 if (! allow_unpredictable
4558 && WRITEBACK_BIT_SET
4559 && ((given & 0xf) == ((given >> 12) & 0xf)))
4560 is_unpredictable = TRUE;
4561 }
4562
4563 func (stream, "]%s",
4564 WRITEBACK_BIT_SET ? "!" : "");
4565 }
4566 else
4567 {
4568 if (IMMEDIATE_BIT_SET)
4569 {
4570 /* Immediate Post-indexed. */
4571 /* PR 10924: Offset must be printed, even if it is zero. */
4572 func (stream, "], #%s%d",
4573 NEGATIVE_BIT_SET ? "-" : "", offset);
4574 if (NEGATIVE_BIT_SET)
4575 offset = -offset;
4576 value_in_comment = offset;
4577 }
4578 else
4579 {
4580 /* Register Post-indexed. */
4581 func (stream, "], %s%s",
4582 NEGATIVE_BIT_SET ? "-" : "",
4583 arm_regnames[given & 0xf]);
4584
4585 /* Writing back to the register that is the source/
4586 destination of the load/store is unpredictable. */
4587 if (! allow_unpredictable
4588 && (given & 0xf) == ((given >> 12) & 0xf))
4589 is_unpredictable = TRUE;
4590 }
4591
4592 if (! allow_unpredictable)
4593 {
4594 /* Writeback is automatically implied by post- addressing.
4595 Setting the W bit is unnecessary and ARM specify it as
4596 being unpredictable. */
4597 if (WRITEBACK_BIT_SET
4598 /* Specifying the PC register as the post-indexed
4599 registers is also unpredictable. */
4600 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4601 is_unpredictable = TRUE;
4602 }
4603 }
4604 }
4605 break;
4606
4607 case 'b':
4608 {
4609 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4610 info->print_address_func (disp * 4 + pc + 8, info);
4611 }
4612 break;
4613
4614 case 'c':
4615 if (((given >> 28) & 0xf) != 0xe)
4616 func (stream, "%s",
4617 arm_conditional [(given >> 28) & 0xf]);
4618 break;
4619
4620 case 'm':
4621 {
4622 int started = 0;
4623 int reg;
4624
4625 func (stream, "{");
4626 for (reg = 0; reg < 16; reg++)
4627 if ((given & (1 << reg)) != 0)
4628 {
4629 if (started)
4630 func (stream, ", ");
4631 started = 1;
4632 func (stream, "%s", arm_regnames[reg]);
4633 }
4634 func (stream, "}");
4635 if (! started)
4636 is_unpredictable = TRUE;
4637 }
4638 break;
4639
4640 case 'q':
4641 arm_decode_shift (given, func, stream, FALSE);
4642 break;
4643
4644 case 'o':
4645 if ((given & 0x02000000) != 0)
4646 {
4647 unsigned int rotate = (given & 0xf00) >> 7;
4648 unsigned int immed = (given & 0xff);
4649 unsigned int a, i;
4650
4651 a = (((immed << (32 - rotate))
4652 | (immed >> rotate)) & 0xffffffff);
4653 /* If there is another encoding with smaller rotate,
4654 the rotate should be specified directly. */
4655 for (i = 0; i < 32; i += 2)
4656 if ((a << i | a >> (32 - i)) <= 0xff)
4657 break;
4658
4659 if (i != rotate)
4660 func (stream, "#%d, %d", immed, rotate);
4661 else
4662 func (stream, "#%d", a);
4663 value_in_comment = a;
4664 }
4665 else
4666 arm_decode_shift (given, func, stream, TRUE);
4667 break;
4668
4669 case 'p':
4670 if ((given & 0x0000f000) == 0x0000f000)
4671 {
4672 arm_feature_set arm_ext_v6 =
4673 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4674
4675 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4676 mechanism for setting PSR flag bits. They are
4677 obsolete in V6 onwards. */
4678 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4679 arm_ext_v6))
4680 func (stream, "p");
4681 else
4682 is_unpredictable = TRUE;
4683 }
4684 break;
4685
4686 case 't':
4687 if ((given & 0x01200000) == 0x00200000)
4688 func (stream, "t");
4689 break;
4690
4691 case 'A':
4692 {
4693 int offset = given & 0xff;
4694
4695 value_in_comment = offset * 4;
4696 if (NEGATIVE_BIT_SET)
4697 value_in_comment = - value_in_comment;
4698
4699 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4700
4701 if (PRE_BIT_SET)
4702 {
4703 if (offset)
4704 func (stream, ", #%d]%s",
4705 (int) value_in_comment,
4706 WRITEBACK_BIT_SET ? "!" : "");
4707 else
4708 func (stream, "]");
4709 }
4710 else
4711 {
4712 func (stream, "]");
4713
4714 if (WRITEBACK_BIT_SET)
4715 {
4716 if (offset)
4717 func (stream, ", #%d", (int) value_in_comment);
4718 }
4719 else
4720 {
4721 func (stream, ", {%d}", (int) offset);
4722 value_in_comment = offset;
4723 }
4724 }
4725 }
4726 break;
4727
4728 case 'B':
4729 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4730 {
4731 bfd_vma address;
4732 bfd_vma offset = 0;
4733
4734 if (! NEGATIVE_BIT_SET)
4735 /* Is signed, hi bits should be ones. */
4736 offset = (-1) ^ 0x00ffffff;
4737
4738 /* Offset is (SignExtend(offset field)<<2). */
4739 offset += given & 0x00ffffff;
4740 offset <<= 2;
4741 address = offset + pc + 8;
4742
4743 if (given & 0x01000000)
4744 /* H bit allows addressing to 2-byte boundaries. */
4745 address += 2;
4746
4747 info->print_address_func (address, info);
4748 }
4749 break;
4750
4751 case 'C':
4752 if ((given & 0x02000200) == 0x200)
4753 {
4754 const char * name;
4755 unsigned sysm = (given & 0x004f0000) >> 16;
4756
4757 sysm |= (given & 0x300) >> 4;
4758 name = banked_regname (sysm);
4759
4760 if (name != NULL)
4761 func (stream, "%s", name);
4762 else
4763 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4764 }
4765 else
4766 {
4767 func (stream, "%cPSR_",
4768 (given & 0x00400000) ? 'S' : 'C');
4769 if (given & 0x80000)
4770 func (stream, "f");
4771 if (given & 0x40000)
4772 func (stream, "s");
4773 if (given & 0x20000)
4774 func (stream, "x");
4775 if (given & 0x10000)
4776 func (stream, "c");
4777 }
4778 break;
4779
4780 case 'U':
4781 if ((given & 0xf0) == 0x60)
4782 {
4783 switch (given & 0xf)
4784 {
4785 case 0xf: func (stream, "sy"); break;
4786 default:
4787 func (stream, "#%d", (int) given & 0xf);
4788 break;
4789 }
4790 }
4791 else
4792 {
4793 const char * opt = data_barrier_option (given & 0xf);
4794 if (opt != NULL)
4795 func (stream, "%s", opt);
4796 else
4797 func (stream, "#%d", (int) given & 0xf);
4798 }
4799 break;
4800
4801 case '0': case '1': case '2': case '3': case '4':
4802 case '5': case '6': case '7': case '8': case '9':
4803 {
4804 int width;
4805 unsigned long value;
4806
4807 c = arm_decode_bitfield (c, given, &value, &width);
4808
4809 switch (*c)
4810 {
4811 case 'R':
4812 if (value == 15)
4813 is_unpredictable = TRUE;
4814 /* Fall through. */
4815 case 'r':
4816 case 'T':
4817 /* We want register + 1 when decoding T. */
4818 if (*c == 'T')
4819 ++value;
4820
4821 if (c[1] == 'u')
4822 {
4823 /* Eat the 'u' character. */
4824 ++ c;
4825
4826 if (u_reg == value)
4827 is_unpredictable = TRUE;
4828 u_reg = value;
4829 }
4830 if (c[1] == 'U')
4831 {
4832 /* Eat the 'U' character. */
4833 ++ c;
4834
4835 if (U_reg == value)
4836 is_unpredictable = TRUE;
4837 U_reg = value;
4838 }
4839 func (stream, "%s", arm_regnames[value]);
4840 break;
4841 case 'd':
4842 func (stream, "%ld", value);
4843 value_in_comment = value;
4844 break;
4845 case 'b':
4846 func (stream, "%ld", value * 8);
4847 value_in_comment = value * 8;
4848 break;
4849 case 'W':
4850 func (stream, "%ld", value + 1);
4851 value_in_comment = value + 1;
4852 break;
4853 case 'x':
4854 func (stream, "0x%08lx", value);
4855
4856 /* Some SWI instructions have special
4857 meanings. */
4858 if ((given & 0x0fffffff) == 0x0FF00000)
4859 func (stream, "\t; IMB");
4860 else if ((given & 0x0fffffff) == 0x0FF00001)
4861 func (stream, "\t; IMBRange");
4862 break;
4863 case 'X':
4864 func (stream, "%01lx", value & 0xf);
4865 value_in_comment = value;
4866 break;
4867 case '`':
4868 c++;
4869 if (value == 0)
4870 func (stream, "%c", *c);
4871 break;
4872 case '\'':
4873 c++;
4874 if (value == ((1ul << width) - 1))
4875 func (stream, "%c", *c);
4876 break;
4877 case '?':
4878 func (stream, "%c", c[(1 << width) - (int) value]);
4879 c += 1 << width;
4880 break;
4881 default:
4882 abort ();
4883 }
4884 break;
4885
4886 case 'e':
4887 {
4888 int imm;
4889
4890 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4891 func (stream, "%d", imm);
4892 value_in_comment = imm;
4893 }
4894 break;
4895
4896 case 'E':
4897 /* LSB and WIDTH fields of BFI or BFC. The machine-
4898 language instruction encodes LSB and MSB. */
4899 {
4900 long msb = (given & 0x001f0000) >> 16;
4901 long lsb = (given & 0x00000f80) >> 7;
4902 long w = msb - lsb + 1;
4903
4904 if (w > 0)
4905 func (stream, "#%lu, #%lu", lsb, w);
4906 else
4907 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4908 }
4909 break;
4910
4911 case 'R':
4912 /* Get the PSR/banked register name. */
4913 {
4914 const char * name;
4915 unsigned sysm = (given & 0x004f0000) >> 16;
4916
4917 sysm |= (given & 0x300) >> 4;
4918 name = banked_regname (sysm);
4919
4920 if (name != NULL)
4921 func (stream, "%s", name);
4922 else
4923 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4924 }
4925 break;
4926
4927 case 'V':
4928 /* 16-bit unsigned immediate from a MOVT or MOVW
4929 instruction, encoded in bits 0:11 and 15:19. */
4930 {
4931 long hi = (given & 0x000f0000) >> 4;
4932 long lo = (given & 0x00000fff);
4933 long imm16 = hi | lo;
4934
4935 func (stream, "#%lu", imm16);
4936 value_in_comment = imm16;
4937 }
4938 break;
4939
4940 default:
4941 abort ();
4942 }
4943 }
4944 }
4945 else
4946 func (stream, "%c", *c);
4947 }
4948
4949 if (value_in_comment > 32 || value_in_comment < -16)
4950 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4951
4952 if (is_unpredictable)
4953 func (stream, UNPREDICTABLE_INSTRUCTION);
4954
4955 return;
4956 }
4957 }
4958 abort ();
4959 }
4960
4961 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
4962
4963 static void
4964 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
4965 {
4966 const struct opcode16 *insn;
4967 void *stream = info->stream;
4968 fprintf_ftype func = info->fprintf_func;
4969
4970 for (insn = thumb_opcodes; insn->assembler; insn++)
4971 if ((given & insn->mask) == insn->value)
4972 {
4973 signed long value_in_comment = 0;
4974 const char *c = insn->assembler;
4975
4976 for (; *c; c++)
4977 {
4978 int domaskpc = 0;
4979 int domasklr = 0;
4980
4981 if (*c != '%')
4982 {
4983 func (stream, "%c", *c);
4984 continue;
4985 }
4986
4987 switch (*++c)
4988 {
4989 case '%':
4990 func (stream, "%%");
4991 break;
4992
4993 case 'c':
4994 if (ifthen_state)
4995 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4996 break;
4997
4998 case 'C':
4999 if (ifthen_state)
5000 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5001 else
5002 func (stream, "s");
5003 break;
5004
5005 case 'I':
5006 {
5007 unsigned int tmp;
5008
5009 ifthen_next_state = given & 0xff;
5010 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5011 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5012 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5013 }
5014 break;
5015
5016 case 'x':
5017 if (ifthen_next_state)
5018 func (stream, "\t; unpredictable branch in IT block\n");
5019 break;
5020
5021 case 'X':
5022 if (ifthen_state)
5023 func (stream, "\t; unpredictable <IT:%s>",
5024 arm_conditional[IFTHEN_COND]);
5025 break;
5026
5027 case 'S':
5028 {
5029 long reg;
5030
5031 reg = (given >> 3) & 0x7;
5032 if (given & (1 << 6))
5033 reg += 8;
5034
5035 func (stream, "%s", arm_regnames[reg]);
5036 }
5037 break;
5038
5039 case 'D':
5040 {
5041 long reg;
5042
5043 reg = given & 0x7;
5044 if (given & (1 << 7))
5045 reg += 8;
5046
5047 func (stream, "%s", arm_regnames[reg]);
5048 }
5049 break;
5050
5051 case 'N':
5052 if (given & (1 << 8))
5053 domasklr = 1;
5054 /* Fall through. */
5055 case 'O':
5056 if (*c == 'O' && (given & (1 << 8)))
5057 domaskpc = 1;
5058 /* Fall through. */
5059 case 'M':
5060 {
5061 int started = 0;
5062 int reg;
5063
5064 func (stream, "{");
5065
5066 /* It would be nice if we could spot
5067 ranges, and generate the rS-rE format: */
5068 for (reg = 0; (reg < 8); reg++)
5069 if ((given & (1 << reg)) != 0)
5070 {
5071 if (started)
5072 func (stream, ", ");
5073 started = 1;
5074 func (stream, "%s", arm_regnames[reg]);
5075 }
5076
5077 if (domasklr)
5078 {
5079 if (started)
5080 func (stream, ", ");
5081 started = 1;
5082 func (stream, "%s", arm_regnames[14] /* "lr" */);
5083 }
5084
5085 if (domaskpc)
5086 {
5087 if (started)
5088 func (stream, ", ");
5089 func (stream, "%s", arm_regnames[15] /* "pc" */);
5090 }
5091
5092 func (stream, "}");
5093 }
5094 break;
5095
5096 case 'W':
5097 /* Print writeback indicator for a LDMIA. We are doing a
5098 writeback if the base register is not in the register
5099 mask. */
5100 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5101 func (stream, "!");
5102 break;
5103
5104 case 'b':
5105 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5106 {
5107 bfd_vma address = (pc + 4
5108 + ((given & 0x00f8) >> 2)
5109 + ((given & 0x0200) >> 3));
5110 info->print_address_func (address, info);
5111 }
5112 break;
5113
5114 case 's':
5115 /* Right shift immediate -- bits 6..10; 1-31 print
5116 as themselves, 0 prints as 32. */
5117 {
5118 long imm = (given & 0x07c0) >> 6;
5119 if (imm == 0)
5120 imm = 32;
5121 func (stream, "#%ld", imm);
5122 }
5123 break;
5124
5125 case '0': case '1': case '2': case '3': case '4':
5126 case '5': case '6': case '7': case '8': case '9':
5127 {
5128 int bitstart = *c++ - '0';
5129 int bitend = 0;
5130
5131 while (*c >= '0' && *c <= '9')
5132 bitstart = (bitstart * 10) + *c++ - '0';
5133
5134 switch (*c)
5135 {
5136 case '-':
5137 {
5138 bfd_vma reg;
5139
5140 c++;
5141 while (*c >= '0' && *c <= '9')
5142 bitend = (bitend * 10) + *c++ - '0';
5143 if (!bitend)
5144 abort ();
5145 reg = given >> bitstart;
5146 reg &= (2 << (bitend - bitstart)) - 1;
5147
5148 switch (*c)
5149 {
5150 case 'r':
5151 func (stream, "%s", arm_regnames[reg]);
5152 break;
5153
5154 case 'd':
5155 func (stream, "%ld", (long) reg);
5156 value_in_comment = reg;
5157 break;
5158
5159 case 'H':
5160 func (stream, "%ld", (long) (reg << 1));
5161 value_in_comment = reg << 1;
5162 break;
5163
5164 case 'W':
5165 func (stream, "%ld", (long) (reg << 2));
5166 value_in_comment = reg << 2;
5167 break;
5168
5169 case 'a':
5170 /* PC-relative address -- the bottom two
5171 bits of the address are dropped
5172 before the calculation. */
5173 info->print_address_func
5174 (((pc + 4) & ~3) + (reg << 2), info);
5175 value_in_comment = 0;
5176 break;
5177
5178 case 'x':
5179 func (stream, "0x%04lx", (long) reg);
5180 break;
5181
5182 case 'B':
5183 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5184 info->print_address_func (reg * 2 + pc + 4, info);
5185 value_in_comment = 0;
5186 break;
5187
5188 case 'c':
5189 func (stream, "%s", arm_conditional [reg]);
5190 break;
5191
5192 default:
5193 abort ();
5194 }
5195 }
5196 break;
5197
5198 case '\'':
5199 c++;
5200 if ((given & (1 << bitstart)) != 0)
5201 func (stream, "%c", *c);
5202 break;
5203
5204 case '?':
5205 ++c;
5206 if ((given & (1 << bitstart)) != 0)
5207 func (stream, "%c", *c++);
5208 else
5209 func (stream, "%c", *++c);
5210 break;
5211
5212 default:
5213 abort ();
5214 }
5215 }
5216 break;
5217
5218 default:
5219 abort ();
5220 }
5221 }
5222
5223 if (value_in_comment > 32 || value_in_comment < -16)
5224 func (stream, "\t; 0x%lx", value_in_comment);
5225 return;
5226 }
5227
5228 /* No match. */
5229 abort ();
5230 }
5231
5232 /* Return the name of an V7M special register. */
5233
5234 static const char *
5235 psr_name (int regno)
5236 {
5237 switch (regno)
5238 {
5239 case 0: return "APSR";
5240 case 1: return "IAPSR";
5241 case 2: return "EAPSR";
5242 case 3: return "PSR";
5243 case 5: return "IPSR";
5244 case 6: return "EPSR";
5245 case 7: return "IEPSR";
5246 case 8: return "MSP";
5247 case 9: return "PSP";
5248 case 16: return "PRIMASK";
5249 case 17: return "BASEPRI";
5250 case 18: return "BASEPRI_MAX";
5251 case 19: return "FAULTMASK";
5252 case 20: return "CONTROL";
5253 default: return "<unknown>";
5254 }
5255 }
5256
5257 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5258
5259 static void
5260 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5261 {
5262 const struct opcode32 *insn;
5263 void *stream = info->stream;
5264 fprintf_ftype func = info->fprintf_func;
5265
5266 if (print_insn_coprocessor (pc, info, given, TRUE))
5267 return;
5268
5269 if (print_insn_neon (info, given, TRUE))
5270 return;
5271
5272 for (insn = thumb32_opcodes; insn->assembler; insn++)
5273 if ((given & insn->mask) == insn->value)
5274 {
5275 bfd_boolean is_unpredictable = FALSE;
5276 signed long value_in_comment = 0;
5277 const char *c = insn->assembler;
5278
5279 for (; *c; c++)
5280 {
5281 if (*c != '%')
5282 {
5283 func (stream, "%c", *c);
5284 continue;
5285 }
5286
5287 switch (*++c)
5288 {
5289 case '%':
5290 func (stream, "%%");
5291 break;
5292
5293 case 'c':
5294 if (ifthen_state)
5295 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5296 break;
5297
5298 case 'x':
5299 if (ifthen_next_state)
5300 func (stream, "\t; unpredictable branch in IT block\n");
5301 break;
5302
5303 case 'X':
5304 if (ifthen_state)
5305 func (stream, "\t; unpredictable <IT:%s>",
5306 arm_conditional[IFTHEN_COND]);
5307 break;
5308
5309 case 'I':
5310 {
5311 unsigned int imm12 = 0;
5312
5313 imm12 |= (given & 0x000000ffu);
5314 imm12 |= (given & 0x00007000u) >> 4;
5315 imm12 |= (given & 0x04000000u) >> 15;
5316 func (stream, "#%u", imm12);
5317 value_in_comment = imm12;
5318 }
5319 break;
5320
5321 case 'M':
5322 {
5323 unsigned int bits = 0, imm, imm8, mod;
5324
5325 bits |= (given & 0x000000ffu);
5326 bits |= (given & 0x00007000u) >> 4;
5327 bits |= (given & 0x04000000u) >> 15;
5328 imm8 = (bits & 0x0ff);
5329 mod = (bits & 0xf00) >> 8;
5330 switch (mod)
5331 {
5332 case 0: imm = imm8; break;
5333 case 1: imm = ((imm8 << 16) | imm8); break;
5334 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5335 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5336 default:
5337 mod = (bits & 0xf80) >> 7;
5338 imm8 = (bits & 0x07f) | 0x80;
5339 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5340 }
5341 func (stream, "#%u", imm);
5342 value_in_comment = imm;
5343 }
5344 break;
5345
5346 case 'J':
5347 {
5348 unsigned int imm = 0;
5349
5350 imm |= (given & 0x000000ffu);
5351 imm |= (given & 0x00007000u) >> 4;
5352 imm |= (given & 0x04000000u) >> 15;
5353 imm |= (given & 0x000f0000u) >> 4;
5354 func (stream, "#%u", imm);
5355 value_in_comment = imm;
5356 }
5357 break;
5358
5359 case 'K':
5360 {
5361 unsigned int imm = 0;
5362
5363 imm |= (given & 0x000f0000u) >> 16;
5364 imm |= (given & 0x00000ff0u) >> 0;
5365 imm |= (given & 0x0000000fu) << 12;
5366 func (stream, "#%u", imm);
5367 value_in_comment = imm;
5368 }
5369 break;
5370
5371 case 'H':
5372 {
5373 unsigned int imm = 0;
5374
5375 imm |= (given & 0x000f0000u) >> 4;
5376 imm |= (given & 0x00000fffu) >> 0;
5377 func (stream, "#%u", imm);
5378 value_in_comment = imm;
5379 }
5380 break;
5381
5382 case 'V':
5383 {
5384 unsigned int imm = 0;
5385
5386 imm |= (given & 0x00000fffu);
5387 imm |= (given & 0x000f0000u) >> 4;
5388 func (stream, "#%u", imm);
5389 value_in_comment = imm;
5390 }
5391 break;
5392
5393 case 'S':
5394 {
5395 unsigned int reg = (given & 0x0000000fu);
5396 unsigned int stp = (given & 0x00000030u) >> 4;
5397 unsigned int imm = 0;
5398 imm |= (given & 0x000000c0u) >> 6;
5399 imm |= (given & 0x00007000u) >> 10;
5400
5401 func (stream, "%s", arm_regnames[reg]);
5402 switch (stp)
5403 {
5404 case 0:
5405 if (imm > 0)
5406 func (stream, ", lsl #%u", imm);
5407 break;
5408
5409 case 1:
5410 if (imm == 0)
5411 imm = 32;
5412 func (stream, ", lsr #%u", imm);
5413 break;
5414
5415 case 2:
5416 if (imm == 0)
5417 imm = 32;
5418 func (stream, ", asr #%u", imm);
5419 break;
5420
5421 case 3:
5422 if (imm == 0)
5423 func (stream, ", rrx");
5424 else
5425 func (stream, ", ror #%u", imm);
5426 }
5427 }
5428 break;
5429
5430 case 'a':
5431 {
5432 unsigned int Rn = (given & 0x000f0000) >> 16;
5433 unsigned int U = ! NEGATIVE_BIT_SET;
5434 unsigned int op = (given & 0x00000f00) >> 8;
5435 unsigned int i12 = (given & 0x00000fff);
5436 unsigned int i8 = (given & 0x000000ff);
5437 bfd_boolean writeback = FALSE, postind = FALSE;
5438 bfd_vma offset = 0;
5439
5440 func (stream, "[%s", arm_regnames[Rn]);
5441 if (U) /* 12-bit positive immediate offset. */
5442 {
5443 offset = i12;
5444 if (Rn != 15)
5445 value_in_comment = offset;
5446 }
5447 else if (Rn == 15) /* 12-bit negative immediate offset. */
5448 offset = - (int) i12;
5449 else if (op == 0x0) /* Shifted register offset. */
5450 {
5451 unsigned int Rm = (i8 & 0x0f);
5452 unsigned int sh = (i8 & 0x30) >> 4;
5453
5454 func (stream, ", %s", arm_regnames[Rm]);
5455 if (sh)
5456 func (stream, ", lsl #%u", sh);
5457 func (stream, "]");
5458 break;
5459 }
5460 else switch (op)
5461 {
5462 case 0xE: /* 8-bit positive immediate offset. */
5463 offset = i8;
5464 break;
5465
5466 case 0xC: /* 8-bit negative immediate offset. */
5467 offset = -i8;
5468 break;
5469
5470 case 0xF: /* 8-bit + preindex with wb. */
5471 offset = i8;
5472 writeback = TRUE;
5473 break;
5474
5475 case 0xD: /* 8-bit - preindex with wb. */
5476 offset = -i8;
5477 writeback = TRUE;
5478 break;
5479
5480 case 0xB: /* 8-bit + postindex. */
5481 offset = i8;
5482 postind = TRUE;
5483 break;
5484
5485 case 0x9: /* 8-bit - postindex. */
5486 offset = -i8;
5487 postind = TRUE;
5488 break;
5489
5490 default:
5491 func (stream, ", <undefined>]");
5492 goto skip;
5493 }
5494
5495 if (postind)
5496 func (stream, "], #%d", (int) offset);
5497 else
5498 {
5499 if (offset)
5500 func (stream, ", #%d", (int) offset);
5501 func (stream, writeback ? "]!" : "]");
5502 }
5503
5504 if (Rn == 15)
5505 {
5506 func (stream, "\t; ");
5507 info->print_address_func (((pc + 4) & ~3) + offset, info);
5508 }
5509 }
5510 skip:
5511 break;
5512
5513 case 'A':
5514 {
5515 unsigned int U = ! NEGATIVE_BIT_SET;
5516 unsigned int W = WRITEBACK_BIT_SET;
5517 unsigned int Rn = (given & 0x000f0000) >> 16;
5518 unsigned int off = (given & 0x000000ff);
5519
5520 func (stream, "[%s", arm_regnames[Rn]);
5521
5522 if (PRE_BIT_SET)
5523 {
5524 if (off || !U)
5525 {
5526 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5527 value_in_comment = off * 4 * U ? 1 : -1;
5528 }
5529 func (stream, "]");
5530 if (W)
5531 func (stream, "!");
5532 }
5533 else
5534 {
5535 func (stream, "], ");
5536 if (W)
5537 {
5538 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5539 value_in_comment = off * 4 * U ? 1 : -1;
5540 }
5541 else
5542 {
5543 func (stream, "{%u}", off);
5544 value_in_comment = off;
5545 }
5546 }
5547 }
5548 break;
5549
5550 case 'w':
5551 {
5552 unsigned int Sbit = (given & 0x01000000) >> 24;
5553 unsigned int type = (given & 0x00600000) >> 21;
5554
5555 switch (type)
5556 {
5557 case 0: func (stream, Sbit ? "sb" : "b"); break;
5558 case 1: func (stream, Sbit ? "sh" : "h"); break;
5559 case 2:
5560 if (Sbit)
5561 func (stream, "??");
5562 break;
5563 case 3:
5564 func (stream, "??");
5565 break;
5566 }
5567 }
5568 break;
5569
5570 case 'm':
5571 {
5572 int started = 0;
5573 int reg;
5574
5575 func (stream, "{");
5576 for (reg = 0; reg < 16; reg++)
5577 if ((given & (1 << reg)) != 0)
5578 {
5579 if (started)
5580 func (stream, ", ");
5581 started = 1;
5582 func (stream, "%s", arm_regnames[reg]);
5583 }
5584 func (stream, "}");
5585 }
5586 break;
5587
5588 case 'E':
5589 {
5590 unsigned int msb = (given & 0x0000001f);
5591 unsigned int lsb = 0;
5592
5593 lsb |= (given & 0x000000c0u) >> 6;
5594 lsb |= (given & 0x00007000u) >> 10;
5595 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5596 }
5597 break;
5598
5599 case 'F':
5600 {
5601 unsigned int width = (given & 0x0000001f) + 1;
5602 unsigned int lsb = 0;
5603
5604 lsb |= (given & 0x000000c0u) >> 6;
5605 lsb |= (given & 0x00007000u) >> 10;
5606 func (stream, "#%u, #%u", lsb, width);
5607 }
5608 break;
5609
5610 case 'b':
5611 {
5612 unsigned int S = (given & 0x04000000u) >> 26;
5613 unsigned int J1 = (given & 0x00002000u) >> 13;
5614 unsigned int J2 = (given & 0x00000800u) >> 11;
5615 bfd_vma offset = 0;
5616
5617 offset |= !S << 20;
5618 offset |= J2 << 19;
5619 offset |= J1 << 18;
5620 offset |= (given & 0x003f0000) >> 4;
5621 offset |= (given & 0x000007ff) << 1;
5622 offset -= (1 << 20);
5623
5624 info->print_address_func (pc + 4 + offset, info);
5625 }
5626 break;
5627
5628 case 'B':
5629 {
5630 unsigned int S = (given & 0x04000000u) >> 26;
5631 unsigned int I1 = (given & 0x00002000u) >> 13;
5632 unsigned int I2 = (given & 0x00000800u) >> 11;
5633 bfd_vma offset = 0;
5634
5635 offset |= !S << 24;
5636 offset |= !(I1 ^ S) << 23;
5637 offset |= !(I2 ^ S) << 22;
5638 offset |= (given & 0x03ff0000u) >> 4;
5639 offset |= (given & 0x000007ffu) << 1;
5640 offset -= (1 << 24);
5641 offset += pc + 4;
5642
5643 /* BLX target addresses are always word aligned. */
5644 if ((given & 0x00001000u) == 0)
5645 offset &= ~2u;
5646
5647 info->print_address_func (offset, info);
5648 }
5649 break;
5650
5651 case 's':
5652 {
5653 unsigned int shift = 0;
5654
5655 shift |= (given & 0x000000c0u) >> 6;
5656 shift |= (given & 0x00007000u) >> 10;
5657 if (WRITEBACK_BIT_SET)
5658 func (stream, ", asr #%u", shift);
5659 else if (shift)
5660 func (stream, ", lsl #%u", shift);
5661 /* else print nothing - lsl #0 */
5662 }
5663 break;
5664
5665 case 'R':
5666 {
5667 unsigned int rot = (given & 0x00000030) >> 4;
5668
5669 if (rot)
5670 func (stream, ", ror #%u", rot * 8);
5671 }
5672 break;
5673
5674 case 'U':
5675 if ((given & 0xf0) == 0x60)
5676 {
5677 switch (given & 0xf)
5678 {
5679 case 0xf: func (stream, "sy"); break;
5680 default:
5681 func (stream, "#%d", (int) given & 0xf);
5682 break;
5683 }
5684 }
5685 else
5686 {
5687 const char * opt = data_barrier_option (given & 0xf);
5688 if (opt != NULL)
5689 func (stream, "%s", opt);
5690 else
5691 func (stream, "#%d", (int) given & 0xf);
5692 }
5693 break;
5694
5695 case 'C':
5696 if ((given & 0xff) == 0)
5697 {
5698 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5699 if (given & 0x800)
5700 func (stream, "f");
5701 if (given & 0x400)
5702 func (stream, "s");
5703 if (given & 0x200)
5704 func (stream, "x");
5705 if (given & 0x100)
5706 func (stream, "c");
5707 }
5708 else if ((given & 0x20) == 0x20)
5709 {
5710 char const* name;
5711 unsigned sysm = (given & 0xf00) >> 8;
5712
5713 sysm |= (given & 0x30);
5714 sysm |= (given & 0x00100000) >> 14;
5715 name = banked_regname (sysm);
5716
5717 if (name != NULL)
5718 func (stream, "%s", name);
5719 else
5720 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5721 }
5722 else
5723 {
5724 func (stream, "%s", psr_name (given & 0xff));
5725 }
5726 break;
5727
5728 case 'D':
5729 if (((given & 0xff) == 0)
5730 || ((given & 0x20) == 0x20))
5731 {
5732 char const* name;
5733 unsigned sm = (given & 0xf0000) >> 16;
5734
5735 sm |= (given & 0x30);
5736 sm |= (given & 0x00100000) >> 14;
5737 name = banked_regname (sm);
5738
5739 if (name != NULL)
5740 func (stream, "%s", name);
5741 else
5742 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5743 }
5744 else
5745 func (stream, "%s", psr_name (given & 0xff));
5746 break;
5747
5748 case '0': case '1': case '2': case '3': case '4':
5749 case '5': case '6': case '7': case '8': case '9':
5750 {
5751 int width;
5752 unsigned long val;
5753
5754 c = arm_decode_bitfield (c, given, &val, &width);
5755
5756 switch (*c)
5757 {
5758 case 'd':
5759 func (stream, "%lu", val);
5760 value_in_comment = val;
5761 break;
5762
5763 case 'D':
5764 func (stream, "%lu", val + 1);
5765 value_in_comment = val + 1;
5766 break;
5767
5768 case 'W':
5769 func (stream, "%lu", val * 4);
5770 value_in_comment = val * 4;
5771 break;
5772
5773 case 'S':
5774 if (val == 13)
5775 is_unpredictable = TRUE;
5776 /* Fall through. */
5777 case 'R':
5778 if (val == 15)
5779 is_unpredictable = TRUE;
5780 /* Fall through. */
5781 case 'r':
5782 func (stream, "%s", arm_regnames[val]);
5783 break;
5784
5785 case 'c':
5786 func (stream, "%s", arm_conditional[val]);
5787 break;
5788
5789 case '\'':
5790 c++;
5791 if (val == ((1ul << width) - 1))
5792 func (stream, "%c", *c);
5793 break;
5794
5795 case '`':
5796 c++;
5797 if (val == 0)
5798 func (stream, "%c", *c);
5799 break;
5800
5801 case '?':
5802 func (stream, "%c", c[(1 << width) - (int) val]);
5803 c += 1 << width;
5804 break;
5805
5806 case 'x':
5807 func (stream, "0x%lx", val & 0xffffffffUL);
5808 break;
5809
5810 default:
5811 abort ();
5812 }
5813 }
5814 break;
5815
5816 case 'L':
5817 /* PR binutils/12534
5818 If we have a PC relative offset in an LDRD or STRD
5819 instructions then display the decoded address. */
5820 if (((given >> 16) & 0xf) == 0xf)
5821 {
5822 bfd_vma offset = (given & 0xff) * 4;
5823
5824 if ((given & (1 << 23)) == 0)
5825 offset = - offset;
5826 func (stream, "\t; ");
5827 info->print_address_func ((pc & ~3) + 4 + offset, info);
5828 }
5829 break;
5830
5831 default:
5832 abort ();
5833 }
5834 }
5835
5836 if (value_in_comment > 32 || value_in_comment < -16)
5837 func (stream, "\t; 0x%lx", value_in_comment);
5838
5839 if (is_unpredictable)
5840 func (stream, UNPREDICTABLE_INSTRUCTION);
5841
5842 return;
5843 }
5844
5845 /* No match. */
5846 abort ();
5847 }
5848
5849 /* Print data bytes on INFO->STREAM. */
5850
5851 static void
5852 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5853 struct disassemble_info *info,
5854 long given)
5855 {
5856 switch (info->bytes_per_chunk)
5857 {
5858 case 1:
5859 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5860 break;
5861 case 2:
5862 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5863 break;
5864 case 4:
5865 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5866 break;
5867 default:
5868 abort ();
5869 }
5870 }
5871
5872 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
5873 being displayed in symbol relative addresses.
5874
5875 Also disallow private symbol, with __tagsym$$ prefix,
5876 from ARM RVCT toolchain being displayed. */
5877
5878 bfd_boolean
5879 arm_symbol_is_valid (asymbol * sym,
5880 struct disassemble_info * info ATTRIBUTE_UNUSED)
5881 {
5882 const char * name;
5883
5884 if (sym == NULL)
5885 return FALSE;
5886
5887 name = bfd_asymbol_name (sym);
5888
5889 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
5890 }
5891
5892 /* Parse an individual disassembler option. */
5893
5894 void
5895 parse_arm_disassembler_option (char *option)
5896 {
5897 if (option == NULL)
5898 return;
5899
5900 if (CONST_STRNEQ (option, "reg-names-"))
5901 {
5902 int i;
5903
5904 option += 10;
5905
5906 for (i = NUM_ARM_REGNAMES; i--;)
5907 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
5908 {
5909 regname_selected = i;
5910 break;
5911 }
5912
5913 if (i < 0)
5914 /* XXX - should break 'option' at following delimiter. */
5915 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
5916 }
5917 else if (CONST_STRNEQ (option, "force-thumb"))
5918 force_thumb = 1;
5919 else if (CONST_STRNEQ (option, "no-force-thumb"))
5920 force_thumb = 0;
5921 else
5922 /* XXX - should break 'option' at following delimiter. */
5923 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
5924
5925 return;
5926 }
5927
5928 /* Parse the string of disassembler options, spliting it at whitespaces
5929 or commas. (Whitespace separators supported for backwards compatibility). */
5930
5931 static void
5932 parse_disassembler_options (char *options)
5933 {
5934 if (options == NULL)
5935 return;
5936
5937 while (*options)
5938 {
5939 parse_arm_disassembler_option (options);
5940
5941 /* Skip forward to next seperator. */
5942 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5943 ++ options;
5944 /* Skip forward past seperators. */
5945 while (ISSPACE (*options) || (*options == ','))
5946 ++ options;
5947 }
5948 }
5949
5950 static bfd_boolean
5951 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
5952 enum map_type *map_symbol);
5953
5954 /* Search back through the insn stream to determine if this instruction is
5955 conditionally executed. */
5956
5957 static void
5958 find_ifthen_state (bfd_vma pc,
5959 struct disassemble_info *info,
5960 bfd_boolean little)
5961 {
5962 unsigned char b[2];
5963 unsigned int insn;
5964 int status;
5965 /* COUNT is twice the number of instructions seen. It will be odd if we
5966 just crossed an instruction boundary. */
5967 int count;
5968 int it_count;
5969 unsigned int seen_it;
5970 bfd_vma addr;
5971
5972 ifthen_address = pc;
5973 ifthen_state = 0;
5974
5975 addr = pc;
5976 count = 1;
5977 it_count = 0;
5978 seen_it = 0;
5979 /* Scan backwards looking for IT instructions, keeping track of where
5980 instruction boundaries are. We don't know if something is actually an
5981 IT instruction until we find a definite instruction boundary. */
5982 for (;;)
5983 {
5984 if (addr == 0 || info->symbol_at_address_func (addr, info))
5985 {
5986 /* A symbol must be on an instruction boundary, and will not
5987 be within an IT block. */
5988 if (seen_it && (count & 1))
5989 break;
5990
5991 return;
5992 }
5993 addr -= 2;
5994 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
5995 if (status)
5996 return;
5997
5998 if (little)
5999 insn = (b[0]) | (b[1] << 8);
6000 else
6001 insn = (b[1]) | (b[0] << 8);
6002 if (seen_it)
6003 {
6004 if ((insn & 0xf800) < 0xe800)
6005 {
6006 /* Addr + 2 is an instruction boundary. See if this matches
6007 the expected boundary based on the position of the last
6008 IT candidate. */
6009 if (count & 1)
6010 break;
6011 seen_it = 0;
6012 }
6013 }
6014 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6015 {
6016 enum map_type type = MAP_ARM;
6017 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6018
6019 if (!found || (found && type == MAP_THUMB))
6020 {
6021 /* This could be an IT instruction. */
6022 seen_it = insn;
6023 it_count = count >> 1;
6024 }
6025 }
6026 if ((insn & 0xf800) >= 0xe800)
6027 count++;
6028 else
6029 count = (count + 2) | 1;
6030 /* IT blocks contain at most 4 instructions. */
6031 if (count >= 8 && !seen_it)
6032 return;
6033 }
6034 /* We found an IT instruction. */
6035 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6036 if ((ifthen_state & 0xf) == 0)
6037 ifthen_state = 0;
6038 }
6039
6040 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6041 mapping symbol. */
6042
6043 static int
6044 is_mapping_symbol (struct disassemble_info *info, int n,
6045 enum map_type *map_type)
6046 {
6047 const char *name;
6048
6049 name = bfd_asymbol_name (info->symtab[n]);
6050 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6051 && (name[2] == 0 || name[2] == '.'))
6052 {
6053 *map_type = ((name[1] == 'a') ? MAP_ARM
6054 : (name[1] == 't') ? MAP_THUMB
6055 : MAP_DATA);
6056 return TRUE;
6057 }
6058
6059 return FALSE;
6060 }
6061
6062 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6063 Returns nonzero if *MAP_TYPE was set. */
6064
6065 static int
6066 get_map_sym_type (struct disassemble_info *info,
6067 int n,
6068 enum map_type *map_type)
6069 {
6070 /* If the symbol is in a different section, ignore it. */
6071 if (info->section != NULL && info->section != info->symtab[n]->section)
6072 return FALSE;
6073
6074 return is_mapping_symbol (info, n, map_type);
6075 }
6076
6077 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6078 Returns nonzero if *MAP_TYPE was set. */
6079
6080 static int
6081 get_sym_code_type (struct disassemble_info *info,
6082 int n,
6083 enum map_type *map_type)
6084 {
6085 elf_symbol_type *es;
6086 unsigned int type;
6087
6088 /* If the symbol is in a different section, ignore it. */
6089 if (info->section != NULL && info->section != info->symtab[n]->section)
6090 return FALSE;
6091
6092 es = *(elf_symbol_type **)(info->symtab + n);
6093 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6094
6095 /* If the symbol has function type then use that. */
6096 if (type == STT_FUNC || type == STT_GNU_IFUNC)
6097 {
6098 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6099 *map_type = MAP_THUMB;
6100 else
6101 *map_type = MAP_ARM;
6102 return TRUE;
6103 }
6104
6105 return FALSE;
6106 }
6107
6108 /* Search the mapping symbol state for instruction at pc. This is only
6109 applicable for elf target.
6110
6111 There is an assumption Here, info->private_data contains the correct AND
6112 up-to-date information about current scan process. The information will be
6113 used to speed this search process.
6114
6115 Return TRUE if the mapping state can be determined, and map_symbol
6116 will be updated accordingly. Otherwise, return FALSE. */
6117
6118 static bfd_boolean
6119 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6120 enum map_type *map_symbol)
6121 {
6122 bfd_vma addr;
6123 int n, start = 0;
6124 bfd_boolean found = FALSE;
6125 enum map_type type = MAP_ARM;
6126 struct arm_private_data *private_data;
6127
6128 if (info->private_data == NULL || info->symtab_size == 0
6129 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6130 return FALSE;
6131
6132 private_data = info->private_data;
6133 if (pc == 0)
6134 start = 0;
6135 else
6136 start = private_data->last_mapping_sym;
6137
6138 start = (start == -1)? 0 : start;
6139 addr = bfd_asymbol_value (info->symtab[start]);
6140
6141 if (pc >= addr)
6142 {
6143 if (get_map_sym_type (info, start, &type))
6144 found = TRUE;
6145 }
6146 else
6147 {
6148 for (n = start - 1; n >= 0; n--)
6149 {
6150 if (get_map_sym_type (info, n, &type))
6151 {
6152 found = TRUE;
6153 break;
6154 }
6155 }
6156 }
6157
6158 /* No mapping symbols were found. A leading $d may be
6159 omitted for sections which start with data; but for
6160 compatibility with legacy and stripped binaries, only
6161 assume the leading $d if there is at least one mapping
6162 symbol in the file. */
6163 if (!found && private_data->has_mapping_symbols == 1)
6164 {
6165 type = MAP_DATA;
6166 found = TRUE;
6167 }
6168
6169 *map_symbol = type;
6170 return found;
6171 }
6172
6173 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6174 of the supplied arm_feature_set structure with bitmasks indicating
6175 the support base architectures and coprocessor extensions.
6176
6177 FIXME: This could more efficiently implemented as a constant array,
6178 although it would also be less robust. */
6179
6180 static void
6181 select_arm_features (unsigned long mach,
6182 arm_feature_set * features)
6183 {
6184 #undef ARM_SET_FEATURES
6185 #define ARM_SET_FEATURES(FSET) \
6186 { \
6187 const arm_feature_set fset = FSET; \
6188 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6189 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6190 }
6191
6192 switch (mach)
6193 {
6194 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6195 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6196 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6197 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6198 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6199 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6200 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6201 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6202 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6203 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6204 case bfd_mach_arm_ep9312:
6205 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6206 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6207 break;
6208 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6209 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6210 /* If the machine type is unknown allow all
6211 architecture types and all extensions. */
6212 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6213 default:
6214 abort ();
6215 }
6216
6217 #undef ARM_SET_FEATURES
6218 }
6219
6220
6221 /* NOTE: There are no checks in these routines that
6222 the relevant number of data bytes exist. */
6223
6224 static int
6225 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6226 {
6227 unsigned char b[4];
6228 long given;
6229 int status;
6230 int is_thumb = FALSE;
6231 int is_data = FALSE;
6232 int little_code;
6233 unsigned int size = 4;
6234 void (*printer) (bfd_vma, struct disassemble_info *, long);
6235 bfd_boolean found = FALSE;
6236 struct arm_private_data *private_data;
6237
6238 if (info->disassembler_options)
6239 {
6240 parse_disassembler_options (info->disassembler_options);
6241
6242 /* To avoid repeated parsing of these options, we remove them here. */
6243 info->disassembler_options = NULL;
6244 }
6245
6246 /* PR 10288: Control which instructions will be disassembled. */
6247 if (info->private_data == NULL)
6248 {
6249 static struct arm_private_data private;
6250
6251 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6252 /* If the user did not use the -m command line switch then default to
6253 disassembling all types of ARM instruction.
6254
6255 The info->mach value has to be ignored as this will be based on
6256 the default archictecture for the target and/or hints in the notes
6257 section, but it will never be greater than the current largest arm
6258 machine value (iWMMXt2), which is only equivalent to the V5TE
6259 architecture. ARM architectures have advanced beyond the machine
6260 value encoding, and these newer architectures would be ignored if
6261 the machine value was used.
6262
6263 Ie the -m switch is used to restrict which instructions will be
6264 disassembled. If it is necessary to use the -m switch to tell
6265 objdump that an ARM binary is being disassembled, eg because the
6266 input is a raw binary file, but it is also desired to disassemble
6267 all ARM instructions then use "-marm". This will select the
6268 "unknown" arm architecture which is compatible with any ARM
6269 instruction. */
6270 info->mach = bfd_mach_arm_unknown;
6271
6272 /* Compute the architecture bitmask from the machine number.
6273 Note: This assumes that the machine number will not change
6274 during disassembly.... */
6275 select_arm_features (info->mach, & private.features);
6276
6277 private.has_mapping_symbols = -1;
6278 private.last_mapping_sym = -1;
6279 private.last_mapping_addr = 0;
6280
6281 info->private_data = & private;
6282 }
6283
6284 private_data = info->private_data;
6285
6286 /* Decide if our code is going to be little-endian, despite what the
6287 function argument might say. */
6288 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6289
6290 /* For ELF, consult the symbol table to determine what kind of code
6291 or data we have. */
6292 if (info->symtab_size != 0
6293 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6294 {
6295 bfd_vma addr;
6296 int n, start;
6297 int last_sym = -1;
6298 enum map_type type = MAP_ARM;
6299
6300 /* Start scanning at the start of the function, or wherever
6301 we finished last time. */
6302 /* PR 14006. When the address is 0 we are either at the start of the
6303 very first function, or else the first function in a new, unlinked
6304 executable section (eg because uf -ffunction-sections). Either way
6305 start scanning from the beginning of the symbol table, not where we
6306 left off last time. */
6307 if (pc == 0)
6308 start = 0;
6309 else
6310 {
6311 start = info->symtab_pos + 1;
6312 if (start < private_data->last_mapping_sym)
6313 start = private_data->last_mapping_sym;
6314 }
6315 found = FALSE;
6316
6317 /* First, look for mapping symbols. */
6318 if (private_data->has_mapping_symbols != 0)
6319 {
6320 /* Scan up to the location being disassembled. */
6321 for (n = start; n < info->symtab_size; n++)
6322 {
6323 addr = bfd_asymbol_value (info->symtab[n]);
6324 if (addr > pc)
6325 break;
6326 if (get_map_sym_type (info, n, &type))
6327 {
6328 last_sym = n;
6329 found = TRUE;
6330 }
6331 }
6332
6333 if (!found)
6334 {
6335 /* No mapping symbol found at this address. Look backwards
6336 for a preceding one. */
6337 for (n = start - 1; n >= 0; n--)
6338 {
6339 if (get_map_sym_type (info, n, &type))
6340 {
6341 last_sym = n;
6342 found = TRUE;
6343 break;
6344 }
6345 }
6346 }
6347
6348 if (found)
6349 private_data->has_mapping_symbols = 1;
6350
6351 /* No mapping symbols were found. A leading $d may be
6352 omitted for sections which start with data; but for
6353 compatibility with legacy and stripped binaries, only
6354 assume the leading $d if there is at least one mapping
6355 symbol in the file. */
6356 if (!found && private_data->has_mapping_symbols == -1)
6357 {
6358 /* Look for mapping symbols, in any section. */
6359 for (n = 0; n < info->symtab_size; n++)
6360 if (is_mapping_symbol (info, n, &type))
6361 {
6362 private_data->has_mapping_symbols = 1;
6363 break;
6364 }
6365 if (private_data->has_mapping_symbols == -1)
6366 private_data->has_mapping_symbols = 0;
6367 }
6368
6369 if (!found && private_data->has_mapping_symbols == 1)
6370 {
6371 type = MAP_DATA;
6372 found = TRUE;
6373 }
6374 }
6375
6376 /* Next search for function symbols to separate ARM from Thumb
6377 in binaries without mapping symbols. */
6378 if (!found)
6379 {
6380 /* Scan up to the location being disassembled. */
6381 for (n = start; n < info->symtab_size; n++)
6382 {
6383 addr = bfd_asymbol_value (info->symtab[n]);
6384 if (addr > pc)
6385 break;
6386 if (get_sym_code_type (info, n, &type))
6387 {
6388 last_sym = n;
6389 found = TRUE;
6390 }
6391 }
6392
6393 if (!found)
6394 {
6395 /* No mapping symbol found at this address. Look backwards
6396 for a preceding one. */
6397 for (n = start - 1; n >= 0; n--)
6398 {
6399 if (get_sym_code_type (info, n, &type))
6400 {
6401 last_sym = n;
6402 found = TRUE;
6403 break;
6404 }
6405 }
6406 }
6407 }
6408
6409 private_data->last_mapping_sym = last_sym;
6410 private_data->last_type = type;
6411 is_thumb = (private_data->last_type == MAP_THUMB);
6412 is_data = (private_data->last_type == MAP_DATA);
6413
6414 /* Look a little bit ahead to see if we should print out
6415 two or four bytes of data. If there's a symbol,
6416 mapping or otherwise, after two bytes then don't
6417 print more. */
6418 if (is_data)
6419 {
6420 size = 4 - (pc & 3);
6421 for (n = last_sym + 1; n < info->symtab_size; n++)
6422 {
6423 addr = bfd_asymbol_value (info->symtab[n]);
6424 if (addr > pc
6425 && (info->section == NULL
6426 || info->section == info->symtab[n]->section))
6427 {
6428 if (addr - pc < size)
6429 size = addr - pc;
6430 break;
6431 }
6432 }
6433 /* If the next symbol is after three bytes, we need to
6434 print only part of the data, so that we can use either
6435 .byte or .short. */
6436 if (size == 3)
6437 size = (pc & 1) ? 1 : 2;
6438 }
6439 }
6440
6441 if (info->symbols != NULL)
6442 {
6443 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6444 {
6445 coff_symbol_type * cs;
6446
6447 cs = coffsymbol (*info->symbols);
6448 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6449 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6450 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6451 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6452 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6453 }
6454 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6455 && !found)
6456 {
6457 /* If no mapping symbol has been found then fall back to the type
6458 of the function symbol. */
6459 elf_symbol_type * es;
6460 unsigned int type;
6461
6462 es = *(elf_symbol_type **)(info->symbols);
6463 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6464
6465 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6466 == ST_BRANCH_TO_THUMB)
6467 || type == STT_ARM_16BIT);
6468 }
6469 else if (bfd_asymbol_flavour (*info->symbols)
6470 == bfd_target_mach_o_flavour)
6471 {
6472 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6473
6474 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6475 }
6476 }
6477
6478 if (force_thumb)
6479 is_thumb = TRUE;
6480
6481 if (is_data)
6482 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6483 else
6484 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6485
6486 info->bytes_per_line = 4;
6487
6488 /* PR 10263: Disassemble data if requested to do so by the user. */
6489 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6490 {
6491 int i;
6492
6493 /* Size was already set above. */
6494 info->bytes_per_chunk = size;
6495 printer = print_insn_data;
6496
6497 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6498 given = 0;
6499 if (little)
6500 for (i = size - 1; i >= 0; i--)
6501 given = b[i] | (given << 8);
6502 else
6503 for (i = 0; i < (int) size; i++)
6504 given = b[i] | (given << 8);
6505 }
6506 else if (!is_thumb)
6507 {
6508 /* In ARM mode endianness is a straightforward issue: the instruction
6509 is four bytes long and is either ordered 0123 or 3210. */
6510 printer = print_insn_arm;
6511 info->bytes_per_chunk = 4;
6512 size = 4;
6513
6514 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6515 if (little_code)
6516 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6517 else
6518 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6519 }
6520 else
6521 {
6522 /* In Thumb mode we have the additional wrinkle of two
6523 instruction lengths. Fortunately, the bits that determine
6524 the length of the current instruction are always to be found
6525 in the first two bytes. */
6526 printer = print_insn_thumb16;
6527 info->bytes_per_chunk = 2;
6528 size = 2;
6529
6530 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6531 if (little_code)
6532 given = (b[0]) | (b[1] << 8);
6533 else
6534 given = (b[1]) | (b[0] << 8);
6535
6536 if (!status)
6537 {
6538 /* These bit patterns signal a four-byte Thumb
6539 instruction. */
6540 if ((given & 0xF800) == 0xF800
6541 || (given & 0xF800) == 0xF000
6542 || (given & 0xF800) == 0xE800)
6543 {
6544 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6545 if (little_code)
6546 given = (b[0]) | (b[1] << 8) | (given << 16);
6547 else
6548 given = (b[1]) | (b[0] << 8) | (given << 16);
6549
6550 printer = print_insn_thumb32;
6551 size = 4;
6552 }
6553 }
6554
6555 if (ifthen_address != pc)
6556 find_ifthen_state (pc, info, little_code);
6557
6558 if (ifthen_state)
6559 {
6560 if ((ifthen_state & 0xf) == 0x8)
6561 ifthen_next_state = 0;
6562 else
6563 ifthen_next_state = (ifthen_state & 0xe0)
6564 | ((ifthen_state & 0xf) << 1);
6565 }
6566 }
6567
6568 if (status)
6569 {
6570 info->memory_error_func (status, pc, info);
6571 return -1;
6572 }
6573 if (info->flags & INSN_HAS_RELOC)
6574 /* If the instruction has a reloc associated with it, then
6575 the offset field in the instruction will actually be the
6576 addend for the reloc. (We are using REL type relocs).
6577 In such cases, we can ignore the pc when computing
6578 addresses, since the addend is not currently pc-relative. */
6579 pc = 0;
6580
6581 printer (pc, info, given);
6582
6583 if (is_thumb)
6584 {
6585 ifthen_state = ifthen_next_state;
6586 ifthen_address += size;
6587 }
6588 return size;
6589 }
6590
6591 int
6592 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6593 {
6594 /* Detect BE8-ness and record it in the disassembler info. */
6595 if (info->flavour == bfd_target_elf_flavour
6596 && info->section != NULL
6597 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6598 info->endian_code = BFD_ENDIAN_LITTLE;
6599
6600 return print_insn (pc, info, FALSE);
6601 }
6602
6603 int
6604 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6605 {
6606 return print_insn (pc, info, TRUE);
6607 }
6608
6609 void
6610 print_arm_disassembler_options (FILE *stream)
6611 {
6612 int i;
6613
6614 fprintf (stream, _("\n\
6615 The following ARM specific disassembler options are supported for use with\n\
6616 the -M switch:\n"));
6617
6618 for (i = NUM_ARM_REGNAMES; i--;)
6619 fprintf (stream, " reg-names-%s %*c%s\n",
6620 regnames[i].name,
6621 (int)(14 - strlen (regnames[i].name)), ' ',
6622 regnames[i].description);
6623
6624 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
6625 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
6626 }
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