opcodes/bpf-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for bpf.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2020 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "bpf-desc.h"
  33 #include "bpf-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36 #include "xregex.h"
  37
  38 /* Attributes.  */
  39
  40 static const CGEN_ATTR_ENTRY bool_attr[] =
  41 {
  42   { "#f", 0 },
  43   { "#t", 1 },
  44   { 0, 0 }
  45 };
  46
  47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  48 {
  49   { "base", MACH_BASE },
  50   { "bpf", MACH_BPF },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  56 {
  57   { "ebpfle", ISA_EBPFLE },
  58   { "ebpfbe", ISA_EBPFBE },
  59   { "max", ISA_MAX },
  60   { 0, 0 }
  61 };
  62
  63 const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
  64 {
  65   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  66   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  67   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  68   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  69   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  70   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  71   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  72   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  73   { 0, 0, 0 }
  74 };
  75
  76 const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
  77 {
  78   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  79   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  80   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  81   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  82   { "PC", &bool_attr[0], &bool_attr[0] },
  83   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  84   { 0, 0, 0 }
  85 };
  86
  87 const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
  88 {
  89   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  90   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  91   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  92   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  93   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  94   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  95   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  96   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  97   { "RELAX", &bool_attr[0], &bool_attr[0] },
  98   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  99   { 0, 0, 0 }
 100 };
 101
 102 const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
 103 {
 104   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 105   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 106   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 107   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 108   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 109   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 110   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 111   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 112   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 113   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 114   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 115   { "PBB", &bool_attr[0], &bool_attr[0] },
 116   { 0, 0, 0 }
 117 };
 118
 119 /* Instruction set variants.  */
 120
 121 static const CGEN_ISA bpf_cgen_isa_table[] = {
 122   { "ebpfle", 64, 8, 64, 128 },
 123   { "ebpfbe", 64, 8, 64, 128 },
 124   { 0, 0, 0, 0, 0 }
 125 };
 126
 127 /* Machine variants.  */
 128
 129 static const CGEN_MACH bpf_cgen_mach_table[] = {
 130   { "bpf", "bpf", MACH_BPF, 0 },
 131   { 0, 0, 0, 0 }
 132 };
 133
 134 static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
 135 {
 136   { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 137   { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 138   { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 139   { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 140   { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 141   { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 142   { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 143   { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 144   { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 145   { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 146   { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
 147   { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 148   { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 149   { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
 150 };
 151
 152 CGEN_KEYWORD bpf_cgen_opval_h_gpr =
 153 {
 154   & bpf_cgen_opval_h_gpr_entries[0],
 155   14,
 156   0, 0, 0, 0, ""
 157 };
 158
 159
 160 /* The hardware table.  */
 161
 162 #define A(a) (1 << CGEN_HW_##a)
 163
 164 const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
 165 {
 166   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 167   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 168   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 169   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 170   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 171   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF), 0 } }, { { 1, "\xc0" } } } } },
 172   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 173   { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 174   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 175 };
 176
 177 #undef A
 178
 179
 180 /* The instruction field table.  */
 181
 182 #define A(a) (1 << CGEN_IFLD_##a)
 183
 184 const CGEN_IFLD bpf_cgen_ifld_table[] =
 185 {
 186   { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 187   { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 188   { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 189   { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 190   { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 191   { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 192   { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 193   { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 194   { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 195   { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 196   { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 197   { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 198   { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 199   { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 200   { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 201   { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 202   { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 203   { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 204   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 205 };
 206
 207 #undef A
 208
 209
 210
 211 /* multi ifield declarations */
 212
 213 const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
 214
 215
 216 /* multi ifield definitions */
 217
 218 const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
 219 {
 220     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
 221     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
 222     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
 223     { 0, { (const PTR) 0 } }
 224 };
 225
 226 /* The operand table.  */
 227
 228 #define A(a) (1 << CGEN_OPERAND_##a)
 229 #define OPERAND(op) BPF_OPERAND_##op
 230
 231 const CGEN_OPERAND bpf_cgen_operand_table[] =
 232 {
 233 /* pc: program counter */
 234   { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
 235     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
 236     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 237 /* dstle: destination register */
 238   { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
 239     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
 240     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 241 /* srcle: source register */
 242   { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
 243     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
 244     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 245 /* dstbe: destination register */
 246   { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
 247     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
 248     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 249 /* srcbe: source register */
 250   { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
 251     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
 252     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 253 /* disp16: 16-bit PC-relative address */
 254   { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
 255     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
 256     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 257 /* disp32: 32-bit PC-relative address */
 258   { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
 259     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
 260     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 261 /* imm32: 32-bit immediate */
 262   { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
 263     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
 264     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 265 /* offset16: 16-bit offset */
 266   { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
 267     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
 268     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 269 /* imm64: 64-bit immediate */
 270   { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
 271     { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
 272     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 273 /* endsize: endianness size immediate: 16, 32 or 64 */
 274   { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
 275     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
 276     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 277 /* sentinel */
 278   { 0, 0, 0, 0, 0,
 279     { 0, { (const PTR) 0 } },
 280     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 281 };
 282
 283 #undef A
 284
 285
 286 /* The instruction table.  */
 287
 288 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 289 #define A(a) (1 << CGEN_INSN_##a)
 290
 291 static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
 292 {
 293   /* Special null first entry.
 294      A `num' value of zero is thus invalid.
 295      Also, the special `invalid' insn resides here.  */
 296   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
 297 /* add $dstle,$imm32 */
 298   {
 299     BPF_INSN_ADDILE, "addile", "add", 64,
 300     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 301   },
 302 /* add $dstle,$srcle */
 303   {
 304     BPF_INSN_ADDRLE, "addrle", "add", 64,
 305     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 306   },
 307 /* add32 $dstle,$imm32 */
 308   {
 309     BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
 310     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 311   },
 312 /* add32 $dstle,$srcle */
 313   {
 314     BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
 315     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 316   },
 317 /* sub $dstle,$imm32 */
 318   {
 319     BPF_INSN_SUBILE, "subile", "sub", 64,
 320     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 321   },
 322 /* sub $dstle,$srcle */
 323   {
 324     BPF_INSN_SUBRLE, "subrle", "sub", 64,
 325     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 326   },
 327 /* sub32 $dstle,$imm32 */
 328   {
 329     BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
 330     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 331   },
 332 /* sub32 $dstle,$srcle */
 333   {
 334     BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
 335     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 336   },
 337 /* mul $dstle,$imm32 */
 338   {
 339     BPF_INSN_MULILE, "mulile", "mul", 64,
 340     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 341   },
 342 /* mul $dstle,$srcle */
 343   {
 344     BPF_INSN_MULRLE, "mulrle", "mul", 64,
 345     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 346   },
 347 /* mul32 $dstle,$imm32 */
 348   {
 349     BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
 350     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 351   },
 352 /* mul32 $dstle,$srcle */
 353   {
 354     BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
 355     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 356   },
 357 /* div $dstle,$imm32 */
 358   {
 359     BPF_INSN_DIVILE, "divile", "div", 64,
 360     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 361   },
 362 /* div $dstle,$srcle */
 363   {
 364     BPF_INSN_DIVRLE, "divrle", "div", 64,
 365     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 366   },
 367 /* div32 $dstle,$imm32 */
 368   {
 369     BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
 370     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 371   },
 372 /* div32 $dstle,$srcle */
 373   {
 374     BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
 375     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 376   },
 377 /* or $dstle,$imm32 */
 378   {
 379     BPF_INSN_ORILE, "orile", "or", 64,
 380     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 381   },
 382 /* or $dstle,$srcle */
 383   {
 384     BPF_INSN_ORRLE, "orrle", "or", 64,
 385     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 386   },
 387 /* or32 $dstle,$imm32 */
 388   {
 389     BPF_INSN_OR32ILE, "or32ile", "or32", 64,
 390     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 391   },
 392 /* or32 $dstle,$srcle */
 393   {
 394     BPF_INSN_OR32RLE, "or32rle", "or32", 64,
 395     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 396   },
 397 /* and $dstle,$imm32 */
 398   {
 399     BPF_INSN_ANDILE, "andile", "and", 64,
 400     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 401   },
 402 /* and $dstle,$srcle */
 403   {
 404     BPF_INSN_ANDRLE, "andrle", "and", 64,
 405     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 406   },
 407 /* and32 $dstle,$imm32 */
 408   {
 409     BPF_INSN_AND32ILE, "and32ile", "and32", 64,
 410     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 411   },
 412 /* and32 $dstle,$srcle */
 413   {
 414     BPF_INSN_AND32RLE, "and32rle", "and32", 64,
 415     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 416   },
 417 /* lsh $dstle,$imm32 */
 418   {
 419     BPF_INSN_LSHILE, "lshile", "lsh", 64,
 420     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 421   },
 422 /* lsh $dstle,$srcle */
 423   {
 424     BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
 425     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 426   },
 427 /* lsh32 $dstle,$imm32 */
 428   {
 429     BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
 430     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 431   },
 432 /* lsh32 $dstle,$srcle */
 433   {
 434     BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
 435     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 436   },
 437 /* rsh $dstle,$imm32 */
 438   {
 439     BPF_INSN_RSHILE, "rshile", "rsh", 64,
 440     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 441   },
 442 /* rsh $dstle,$srcle */
 443   {
 444     BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
 445     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 446   },
 447 /* rsh32 $dstle,$imm32 */
 448   {
 449     BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
 450     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 451   },
 452 /* rsh32 $dstle,$srcle */
 453   {
 454     BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
 455     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 456   },
 457 /* mod $dstle,$imm32 */
 458   {
 459     BPF_INSN_MODILE, "modile", "mod", 64,
 460     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 461   },
 462 /* mod $dstle,$srcle */
 463   {
 464     BPF_INSN_MODRLE, "modrle", "mod", 64,
 465     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 466   },
 467 /* mod32 $dstle,$imm32 */
 468   {
 469     BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
 470     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 471   },
 472 /* mod32 $dstle,$srcle */
 473   {
 474     BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
 475     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 476   },
 477 /* xor $dstle,$imm32 */
 478   {
 479     BPF_INSN_XORILE, "xorile", "xor", 64,
 480     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 481   },
 482 /* xor $dstle,$srcle */
 483   {
 484     BPF_INSN_XORRLE, "xorrle", "xor", 64,
 485     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 486   },
 487 /* xor32 $dstle,$imm32 */
 488   {
 489     BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
 490     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 491   },
 492 /* xor32 $dstle,$srcle */
 493   {
 494     BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
 495     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 496   },
 497 /* arsh $dstle,$imm32 */
 498   {
 499     BPF_INSN_ARSHILE, "arshile", "arsh", 64,
 500     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 501   },
 502 /* arsh $dstle,$srcle */
 503   {
 504     BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
 505     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 506   },
 507 /* arsh32 $dstle,$imm32 */
 508   {
 509     BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
 510     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 511   },
 512 /* arsh32 $dstle,$srcle */
 513   {
 514     BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
 515     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 516   },
 517 /* neg $dstle */
 518   {
 519     BPF_INSN_NEGLE, "negle", "neg", 64,
 520     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 521   },
 522 /* neg32 $dstle */
 523   {
 524     BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
 525     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 526   },
 527 /* mov $dstle,$imm32 */
 528   {
 529     BPF_INSN_MOVILE, "movile", "mov", 64,
 530     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 531   },
 532 /* mov $dstle,$srcle */
 533   {
 534     BPF_INSN_MOVRLE, "movrle", "mov", 64,
 535     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 536   },
 537 /* mov32 $dstle,$imm32 */
 538   {
 539     BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
 540     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 541   },
 542 /* mov32 $dstle,$srcle */
 543   {
 544     BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
 545     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 546   },
 547 /* add $dstbe,$imm32 */
 548   {
 549     BPF_INSN_ADDIBE, "addibe", "add", 64,
 550     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 551   },
 552 /* add $dstbe,$srcbe */
 553   {
 554     BPF_INSN_ADDRBE, "addrbe", "add", 64,
 555     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 556   },
 557 /* add32 $dstbe,$imm32 */
 558   {
 559     BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
 560     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 561   },
 562 /* add32 $dstbe,$srcbe */
 563   {
 564     BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
 565     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 566   },
 567 /* sub $dstbe,$imm32 */
 568   {
 569     BPF_INSN_SUBIBE, "subibe", "sub", 64,
 570     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 571   },
 572 /* sub $dstbe,$srcbe */
 573   {
 574     BPF_INSN_SUBRBE, "subrbe", "sub", 64,
 575     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 576   },
 577 /* sub32 $dstbe,$imm32 */
 578   {
 579     BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
 580     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 581   },
 582 /* sub32 $dstbe,$srcbe */
 583   {
 584     BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
 585     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 586   },
 587 /* mul $dstbe,$imm32 */
 588   {
 589     BPF_INSN_MULIBE, "mulibe", "mul", 64,
 590     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 591   },
 592 /* mul $dstbe,$srcbe */
 593   {
 594     BPF_INSN_MULRBE, "mulrbe", "mul", 64,
 595     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 596   },
 597 /* mul32 $dstbe,$imm32 */
 598   {
 599     BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
 600     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 601   },
 602 /* mul32 $dstbe,$srcbe */
 603   {
 604     BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
 605     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 606   },
 607 /* div $dstbe,$imm32 */
 608   {
 609     BPF_INSN_DIVIBE, "divibe", "div", 64,
 610     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 611   },
 612 /* div $dstbe,$srcbe */
 613   {
 614     BPF_INSN_DIVRBE, "divrbe", "div", 64,
 615     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 616   },
 617 /* div32 $dstbe,$imm32 */
 618   {
 619     BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
 620     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 621   },
 622 /* div32 $dstbe,$srcbe */
 623   {
 624     BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
 625     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 626   },
 627 /* or $dstbe,$imm32 */
 628   {
 629     BPF_INSN_ORIBE, "oribe", "or", 64,
 630     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 631   },
 632 /* or $dstbe,$srcbe */
 633   {
 634     BPF_INSN_ORRBE, "orrbe", "or", 64,
 635     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 636   },
 637 /* or32 $dstbe,$imm32 */
 638   {
 639     BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
 640     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 641   },
 642 /* or32 $dstbe,$srcbe */
 643   {
 644     BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
 645     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 646   },
 647 /* and $dstbe,$imm32 */
 648   {
 649     BPF_INSN_ANDIBE, "andibe", "and", 64,
 650     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 651   },
 652 /* and $dstbe,$srcbe */
 653   {
 654     BPF_INSN_ANDRBE, "andrbe", "and", 64,
 655     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 656   },
 657 /* and32 $dstbe,$imm32 */
 658   {
 659     BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
 660     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 661   },
 662 /* and32 $dstbe,$srcbe */
 663   {
 664     BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
 665     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 666   },
 667 /* lsh $dstbe,$imm32 */
 668   {
 669     BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
 670     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 671   },
 672 /* lsh $dstbe,$srcbe */
 673   {
 674     BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
 675     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 676   },
 677 /* lsh32 $dstbe,$imm32 */
 678   {
 679     BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
 680     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 681   },
 682 /* lsh32 $dstbe,$srcbe */
 683   {
 684     BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
 685     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 686   },
 687 /* rsh $dstbe,$imm32 */
 688   {
 689     BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
 690     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 691   },
 692 /* rsh $dstbe,$srcbe */
 693   {
 694     BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
 695     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 696   },
 697 /* rsh32 $dstbe,$imm32 */
 698   {
 699     BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
 700     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 701   },
 702 /* rsh32 $dstbe,$srcbe */
 703   {
 704     BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
 705     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 706   },
 707 /* mod $dstbe,$imm32 */
 708   {
 709     BPF_INSN_MODIBE, "modibe", "mod", 64,
 710     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 711   },
 712 /* mod $dstbe,$srcbe */
 713   {
 714     BPF_INSN_MODRBE, "modrbe", "mod", 64,
 715     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 716   },
 717 /* mod32 $dstbe,$imm32 */
 718   {
 719     BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
 720     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 721   },
 722 /* mod32 $dstbe,$srcbe */
 723   {
 724     BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
 725     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 726   },
 727 /* xor $dstbe,$imm32 */
 728   {
 729     BPF_INSN_XORIBE, "xoribe", "xor", 64,
 730     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 731   },
 732 /* xor $dstbe,$srcbe */
 733   {
 734     BPF_INSN_XORRBE, "xorrbe", "xor", 64,
 735     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 736   },
 737 /* xor32 $dstbe,$imm32 */
 738   {
 739     BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
 740     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 741   },
 742 /* xor32 $dstbe,$srcbe */
 743   {
 744     BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
 745     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 746   },
 747 /* arsh $dstbe,$imm32 */
 748   {
 749     BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
 750     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 751   },
 752 /* arsh $dstbe,$srcbe */
 753   {
 754     BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
 755     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 756   },
 757 /* arsh32 $dstbe,$imm32 */
 758   {
 759     BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
 760     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 761   },
 762 /* arsh32 $dstbe,$srcbe */
 763   {
 764     BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
 765     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 766   },
 767 /* neg $dstbe */
 768   {
 769     BPF_INSN_NEGBE, "negbe", "neg", 64,
 770     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 771   },
 772 /* neg32 $dstbe */
 773   {
 774     BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
 775     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 776   },
 777 /* mov $dstbe,$imm32 */
 778   {
 779     BPF_INSN_MOVIBE, "movibe", "mov", 64,
 780     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 781   },
 782 /* mov $dstbe,$srcbe */
 783   {
 784     BPF_INSN_MOVRBE, "movrbe", "mov", 64,
 785     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 786   },
 787 /* mov32 $dstbe,$imm32 */
 788   {
 789     BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
 790     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 791   },
 792 /* mov32 $dstbe,$srcbe */
 793   {
 794     BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
 795     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 796   },
 797 /* endle $dstle,$endsize */
 798   {
 799     BPF_INSN_ENDLELE, "endlele", "endle", 64,
 800     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 801   },
 802 /* endbe $dstle,$endsize */
 803   {
 804     BPF_INSN_ENDBELE, "endbele", "endbe", 64,
 805     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 806   },
 807 /* endle $dstbe,$endsize */
 808   {
 809     BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
 810     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 811   },
 812 /* endbe $dstbe,$endsize */
 813   {
 814     BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
 815     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 816   },
 817 /* lddw $dstle,$imm64 */
 818   {
 819     BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
 820     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 821   },
 822 /* lddw $dstbe,$imm64 */
 823   {
 824     BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
 825     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 826   },
 827 /* ldabsw $imm32 */
 828   {
 829     BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
 830     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
 831   },
 832 /* ldabsh $imm32 */
 833   {
 834     BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
 835     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
 836   },
 837 /* ldabsb $imm32 */
 838   {
 839     BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
 840     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
 841   },
 842 /* ldabsdw $imm32 */
 843   {
 844     BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
 845     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
 846   },
 847 /* ldindw $srcle,$imm32 */
 848   {
 849     BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
 850     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 851   },
 852 /* ldindh $srcle,$imm32 */
 853   {
 854     BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
 855     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 856   },
 857 /* ldindb $srcle,$imm32 */
 858   {
 859     BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
 860     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 861   },
 862 /* ldinddw $srcle,$imm32 */
 863   {
 864     BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
 865     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 866   },
 867 /* ldindw $srcbe,$imm32 */
 868   {
 869     BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
 870     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 871   },
 872 /* ldindh $srcbe,$imm32 */
 873   {
 874     BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
 875     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 876   },
 877 /* ldindb $srcbe,$imm32 */
 878   {
 879     BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
 880     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 881   },
 882 /* ldinddw $srcbe,$imm32 */
 883   {
 884     BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
 885     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 886   },
 887 /* ldxw $dstle,[$srcle+$offset16] */
 888   {
 889     BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
 890     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 891   },
 892 /* ldxh $dstle,[$srcle+$offset16] */
 893   {
 894     BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
 895     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 896   },
 897 /* ldxb $dstle,[$srcle+$offset16] */
 898   {
 899     BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
 900     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 901   },
 902 /* ldxdw $dstle,[$srcle+$offset16] */
 903   {
 904     BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
 905     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 906   },
 907 /* stxw [$dstle+$offset16],$srcle */
 908   {
 909     BPF_INSN_STXWLE, "stxwle", "stxw", 64,
 910     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 911   },
 912 /* stxh [$dstle+$offset16],$srcle */
 913   {
 914     BPF_INSN_STXHLE, "stxhle", "stxh", 64,
 915     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 916   },
 917 /* stxb [$dstle+$offset16],$srcle */
 918   {
 919     BPF_INSN_STXBLE, "stxble", "stxb", 64,
 920     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 921   },
 922 /* stxdw [$dstle+$offset16],$srcle */
 923   {
 924     BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
 925     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 926   },
 927 /* ldxw $dstbe,[$srcbe+$offset16] */
 928   {
 929     BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
 930     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 931   },
 932 /* ldxh $dstbe,[$srcbe+$offset16] */
 933   {
 934     BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
 935     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 936   },
 937 /* ldxb $dstbe,[$srcbe+$offset16] */
 938   {
 939     BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
 940     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 941   },
 942 /* ldxdw $dstbe,[$srcbe+$offset16] */
 943   {
 944     BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
 945     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 946   },
 947 /* stxw [$dstbe+$offset16],$srcbe */
 948   {
 949     BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
 950     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 951   },
 952 /* stxh [$dstbe+$offset16],$srcbe */
 953   {
 954     BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
 955     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 956   },
 957 /* stxb [$dstbe+$offset16],$srcbe */
 958   {
 959     BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
 960     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 961   },
 962 /* stxdw [$dstbe+$offset16],$srcbe */
 963   {
 964     BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
 965     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 966   },
 967 /* stb [$dstle+$offset16],$imm32 */
 968   {
 969     BPF_INSN_STBLE, "stble", "stb", 64,
 970     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 971   },
 972 /* sth [$dstle+$offset16],$imm32 */
 973   {
 974     BPF_INSN_STHLE, "sthle", "sth", 64,
 975     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 976   },
 977 /* stw [$dstle+$offset16],$imm32 */
 978   {
 979     BPF_INSN_STWLE, "stwle", "stw", 64,
 980     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 981   },
 982 /* stdw [$dstle+$offset16],$imm32 */
 983   {
 984     BPF_INSN_STDWLE, "stdwle", "stdw", 64,
 985     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
 986   },
 987 /* stb [$dstbe+$offset16],$imm32 */
 988   {
 989     BPF_INSN_STBBE, "stbbe", "stb", 64,
 990     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 991   },
 992 /* sth [$dstbe+$offset16],$imm32 */
 993   {
 994     BPF_INSN_STHBE, "sthbe", "sth", 64,
 995     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
 996   },
 997 /* stw [$dstbe+$offset16],$imm32 */
 998   {
 999     BPF_INSN_STWBE, "stwbe", "stw", 64,
1000     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1001   },
1002 /* stdw [$dstbe+$offset16],$imm32 */
1003   {
1004     BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
1005     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1006   },
1007 /* jeq $dstle,$imm32,$disp16 */
1008   {
1009     BPF_INSN_JEQILE, "jeqile", "jeq", 64,
1010     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1011   },
1012 /* jeq $dstle,$srcle,$disp16 */
1013   {
1014     BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
1015     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1016   },
1017 /* jeq32 $dstle,$imm32,$disp16 */
1018   {
1019     BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
1020     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1021   },
1022 /* jeq32 $dstle,$srcle,$disp16 */
1023   {
1024     BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
1025     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1026   },
1027 /* jgt $dstle,$imm32,$disp16 */
1028   {
1029     BPF_INSN_JGTILE, "jgtile", "jgt", 64,
1030     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1031   },
1032 /* jgt $dstle,$srcle,$disp16 */
1033   {
1034     BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
1035     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1036   },
1037 /* jgt32 $dstle,$imm32,$disp16 */
1038   {
1039     BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
1040     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1041   },
1042 /* jgt32 $dstle,$srcle,$disp16 */
1043   {
1044     BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
1045     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1046   },
1047 /* jge $dstle,$imm32,$disp16 */
1048   {
1049     BPF_INSN_JGEILE, "jgeile", "jge", 64,
1050     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1051   },
1052 /* jge $dstle,$srcle,$disp16 */
1053   {
1054     BPF_INSN_JGERLE, "jgerle", "jge", 64,
1055     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1056   },
1057 /* jge32 $dstle,$imm32,$disp16 */
1058   {
1059     BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
1060     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1061   },
1062 /* jge32 $dstle,$srcle,$disp16 */
1063   {
1064     BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
1065     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1066   },
1067 /* jlt $dstle,$imm32,$disp16 */
1068   {
1069     BPF_INSN_JLTILE, "jltile", "jlt", 64,
1070     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1071   },
1072 /* jlt $dstle,$srcle,$disp16 */
1073   {
1074     BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
1075     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1076   },
1077 /* jlt32 $dstle,$imm32,$disp16 */
1078   {
1079     BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
1080     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1081   },
1082 /* jlt32 $dstle,$srcle,$disp16 */
1083   {
1084     BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
1085     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1086   },
1087 /* jle $dstle,$imm32,$disp16 */
1088   {
1089     BPF_INSN_JLEILE, "jleile", "jle", 64,
1090     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1091   },
1092 /* jle $dstle,$srcle,$disp16 */
1093   {
1094     BPF_INSN_JLERLE, "jlerle", "jle", 64,
1095     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1096   },
1097 /* jle32 $dstle,$imm32,$disp16 */
1098   {
1099     BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
1100     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1101   },
1102 /* jle32 $dstle,$srcle,$disp16 */
1103   {
1104     BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
1105     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1106   },
1107 /* jset $dstle,$imm32,$disp16 */
1108   {
1109     BPF_INSN_JSETILE, "jsetile", "jset", 64,
1110     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1111   },
1112 /* jset $dstle,$srcle,$disp16 */
1113   {
1114     BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
1115     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1116   },
1117 /* jset32 $dstle,$imm32,$disp16 */
1118   {
1119     BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
1120     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1121   },
1122 /* jset32 $dstle,$srcle,$disp16 */
1123   {
1124     BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
1125     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1126   },
1127 /* jne $dstle,$imm32,$disp16 */
1128   {
1129     BPF_INSN_JNEILE, "jneile", "jne", 64,
1130     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1131   },
1132 /* jne $dstle,$srcle,$disp16 */
1133   {
1134     BPF_INSN_JNERLE, "jnerle", "jne", 64,
1135     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1136   },
1137 /* jne32 $dstle,$imm32,$disp16 */
1138   {
1139     BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
1140     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1141   },
1142 /* jne32 $dstle,$srcle,$disp16 */
1143   {
1144     BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
1145     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1146   },
1147 /* jsgt $dstle,$imm32,$disp16 */
1148   {
1149     BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
1150     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1151   },
1152 /* jsgt $dstle,$srcle,$disp16 */
1153   {
1154     BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
1155     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1156   },
1157 /* jsgt32 $dstle,$imm32,$disp16 */
1158   {
1159     BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
1160     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1161   },
1162 /* jsgt32 $dstle,$srcle,$disp16 */
1163   {
1164     BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
1165     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1166   },
1167 /* jsge $dstle,$imm32,$disp16 */
1168   {
1169     BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
1170     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1171   },
1172 /* jsge $dstle,$srcle,$disp16 */
1173   {
1174     BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
1175     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1176   },
1177 /* jsge32 $dstle,$imm32,$disp16 */
1178   {
1179     BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
1180     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1181   },
1182 /* jsge32 $dstle,$srcle,$disp16 */
1183   {
1184     BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
1185     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1186   },
1187 /* jslt $dstle,$imm32,$disp16 */
1188   {
1189     BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
1190     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1191   },
1192 /* jslt $dstle,$srcle,$disp16 */
1193   {
1194     BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
1195     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1196   },
1197 /* jslt32 $dstle,$imm32,$disp16 */
1198   {
1199     BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
1200     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1201   },
1202 /* jslt32 $dstle,$srcle,$disp16 */
1203   {
1204     BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
1205     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1206   },
1207 /* jsle $dstle,$imm32,$disp16 */
1208   {
1209     BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
1210     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1211   },
1212 /* jsle $dstle,$srcle,$disp16 */
1213   {
1214     BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
1215     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1216   },
1217 /* jsle32 $dstle,$imm32,$disp16 */
1218   {
1219     BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
1220     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1221   },
1222 /* jsle32 $dstle,$srcle,$disp16 */
1223   {
1224     BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
1225     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1226   },
1227 /* jeq $dstbe,$imm32,$disp16 */
1228   {
1229     BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
1230     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1231   },
1232 /* jeq $dstbe,$srcbe,$disp16 */
1233   {
1234     BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
1235     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1236   },
1237 /* jeq32 $dstbe,$imm32,$disp16 */
1238   {
1239     BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
1240     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1241   },
1242 /* jeq32 $dstbe,$srcbe,$disp16 */
1243   {
1244     BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
1245     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1246   },
1247 /* jgt $dstbe,$imm32,$disp16 */
1248   {
1249     BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
1250     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1251   },
1252 /* jgt $dstbe,$srcbe,$disp16 */
1253   {
1254     BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
1255     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1256   },
1257 /* jgt32 $dstbe,$imm32,$disp16 */
1258   {
1259     BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
1260     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1261   },
1262 /* jgt32 $dstbe,$srcbe,$disp16 */
1263   {
1264     BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
1265     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1266   },
1267 /* jge $dstbe,$imm32,$disp16 */
1268   {
1269     BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
1270     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1271   },
1272 /* jge $dstbe,$srcbe,$disp16 */
1273   {
1274     BPF_INSN_JGERBE, "jgerbe", "jge", 64,
1275     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1276   },
1277 /* jge32 $dstbe,$imm32,$disp16 */
1278   {
1279     BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
1280     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1281   },
1282 /* jge32 $dstbe,$srcbe,$disp16 */
1283   {
1284     BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
1285     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1286   },
1287 /* jlt $dstbe,$imm32,$disp16 */
1288   {
1289     BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
1290     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1291   },
1292 /* jlt $dstbe,$srcbe,$disp16 */
1293   {
1294     BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
1295     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1296   },
1297 /* jlt32 $dstbe,$imm32,$disp16 */
1298   {
1299     BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
1300     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1301   },
1302 /* jlt32 $dstbe,$srcbe,$disp16 */
1303   {
1304     BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
1305     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1306   },
1307 /* jle $dstbe,$imm32,$disp16 */
1308   {
1309     BPF_INSN_JLEIBE, "jleibe", "jle", 64,
1310     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1311   },
1312 /* jle $dstbe,$srcbe,$disp16 */
1313   {
1314     BPF_INSN_JLERBE, "jlerbe", "jle", 64,
1315     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1316   },
1317 /* jle32 $dstbe,$imm32,$disp16 */
1318   {
1319     BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
1320     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1321   },
1322 /* jle32 $dstbe,$srcbe,$disp16 */
1323   {
1324     BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
1325     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1326   },
1327 /* jset $dstbe,$imm32,$disp16 */
1328   {
1329     BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
1330     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1331   },
1332 /* jset $dstbe,$srcbe,$disp16 */
1333   {
1334     BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
1335     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1336   },
1337 /* jset32 $dstbe,$imm32,$disp16 */
1338   {
1339     BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
1340     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1341   },
1342 /* jset32 $dstbe,$srcbe,$disp16 */
1343   {
1344     BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
1345     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1346   },
1347 /* jne $dstbe,$imm32,$disp16 */
1348   {
1349     BPF_INSN_JNEIBE, "jneibe", "jne", 64,
1350     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1351   },
1352 /* jne $dstbe,$srcbe,$disp16 */
1353   {
1354     BPF_INSN_JNERBE, "jnerbe", "jne", 64,
1355     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1356   },
1357 /* jne32 $dstbe,$imm32,$disp16 */
1358   {
1359     BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
1360     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1361   },
1362 /* jne32 $dstbe,$srcbe,$disp16 */
1363   {
1364     BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
1365     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1366   },
1367 /* jsgt $dstbe,$imm32,$disp16 */
1368   {
1369     BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
1370     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1371   },
1372 /* jsgt $dstbe,$srcbe,$disp16 */
1373   {
1374     BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
1375     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1376   },
1377 /* jsgt32 $dstbe,$imm32,$disp16 */
1378   {
1379     BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
1380     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1381   },
1382 /* jsgt32 $dstbe,$srcbe,$disp16 */
1383   {
1384     BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
1385     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1386   },
1387 /* jsge $dstbe,$imm32,$disp16 */
1388   {
1389     BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
1390     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1391   },
1392 /* jsge $dstbe,$srcbe,$disp16 */
1393   {
1394     BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
1395     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1396   },
1397 /* jsge32 $dstbe,$imm32,$disp16 */
1398   {
1399     BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
1400     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1401   },
1402 /* jsge32 $dstbe,$srcbe,$disp16 */
1403   {
1404     BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
1405     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1406   },
1407 /* jslt $dstbe,$imm32,$disp16 */
1408   {
1409     BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
1410     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1411   },
1412 /* jslt $dstbe,$srcbe,$disp16 */
1413   {
1414     BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
1415     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1416   },
1417 /* jslt32 $dstbe,$imm32,$disp16 */
1418   {
1419     BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
1420     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1421   },
1422 /* jslt32 $dstbe,$srcbe,$disp16 */
1423   {
1424     BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
1425     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1426   },
1427 /* jsle $dstbe,$imm32,$disp16 */
1428   {
1429     BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
1430     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1431   },
1432 /* jsle $dstbe,$srcbe,$disp16 */
1433   {
1434     BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
1435     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1436   },
1437 /* jsle32 $dstbe,$imm32,$disp16 */
1438   {
1439     BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
1440     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1441   },
1442 /* jsle32 $dstbe,$srcbe,$disp16 */
1443   {
1444     BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
1445     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1446   },
1447 /* call $disp32 */
1448   {
1449     BPF_INSN_CALLLE, "callle", "call", 64,
1450     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1451   },
1452 /* call $disp32 */
1453   {
1454     BPF_INSN_CALLBE, "callbe", "call", 64,
1455     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1456   },
1457 /* ja $disp16 */
1458   {
1459     BPF_INSN_JA, "ja", "ja", 64,
1460     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
1461   },
1462 /* exit */
1463   {
1464     BPF_INSN_EXIT, "exit", "exit", 64,
1465     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
1466   },
1467 /* xadddw [$dstle+$offset16],$srcle */
1468   {
1469     BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
1470     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1471   },
1472 /* xaddw [$dstle+$offset16],$srcle */
1473   {
1474     BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
1475     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1476   },
1477 /* xadddw [$dstbe+$offset16],$srcbe */
1478   {
1479     BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
1480     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1481   },
1482 /* xaddw [$dstbe+$offset16],$srcbe */
1483   {
1484     BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
1485     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1486   },
1487 /* brkpt */
1488   {
1489     BPF_INSN_BRKPT, "brkpt", "brkpt", 64,
1490     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
1491   },
1492 };
1493
1494 #undef OP
1495 #undef A
1496
1497 /* Initialize anything needed to be done once, before any cpu_open call.  */
1498
1499 static void
1500 init_tables (void)
1501 {
1502 }
1503
1504 #ifndef opcodes_error_handler
1505 #define opcodes_error_handler(...) \
1506   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1507 #endif
1508
1509 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1510 static void build_hw_table      (CGEN_CPU_TABLE *);
1511 static void build_ifield_table  (CGEN_CPU_TABLE *);
1512 static void build_operand_table (CGEN_CPU_TABLE *);
1513 static void build_insn_table    (CGEN_CPU_TABLE *);
1514 static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1515
1516 /* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name.  */
1517
1518 static const CGEN_MACH *
1519 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1520 {
1521   while (table->name)
1522     {
1523       if (strcmp (name, table->bfd_name) == 0)
1524         return table;
1525       ++table;
1526     }
1527   return NULL;
1528 }
1529
1530 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.  */
1531
1532 static void
1533 build_hw_table (CGEN_CPU_TABLE *cd)
1534 {
1535   int i;
1536   int machs = cd->machs;
1537   const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
1538   /* MAX_HW is only an upper bound on the number of selected entries.
1539      However each entry is indexed by it's enum so there can be holes in
1540      the table.  */
1541   const CGEN_HW_ENTRY **selected =
1542     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1543
1544   cd->hw_table.init_entries = init;
1545   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1546   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1547   /* ??? For now we just use machs to determine which ones we want.  */
1548   for (i = 0; init[i].name != NULL; ++i)
1549     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1550         & machs)
1551       selected[init[i].type] = &init[i];
1552   cd->hw_table.entries = selected;
1553   cd->hw_table.num_entries = MAX_HW;
1554 }
1555
1556 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.  */
1557
1558 static void
1559 build_ifield_table (CGEN_CPU_TABLE *cd)
1560 {
1561   cd->ifld_table = & bpf_cgen_ifld_table[0];
1562 }
1563
1564 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.  */
1565
1566 static void
1567 build_operand_table (CGEN_CPU_TABLE *cd)
1568 {
1569   int i;
1570   int machs = cd->machs;
1571   const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
1572   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1573      However each entry is indexed by it's enum so there can be holes in
1574      the table.  */
1575   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1576
1577   cd->operand_table.init_entries = init;
1578   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1579   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1580   /* ??? For now we just use mach to determine which ones we want.  */
1581   for (i = 0; init[i].name != NULL; ++i)
1582     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1583         & machs)
1584       selected[init[i].type] = &init[i];
1585   cd->operand_table.entries = selected;
1586   cd->operand_table.num_entries = MAX_OPERANDS;
1587 }
1588
1589 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.
1590    ??? This could leave out insns not supported by the specified mach/isa,
1591    but that would cause errors like "foo only supported by bar" to become
1592    "unknown insn", so for now we include all insns and require the app to
1593    do the checking later.
1594    ??? On the other hand, parsing of such insns may require their hardware or
1595    operand elements to be in the table [which they mightn't be].  */
1596
1597 static void
1598 build_insn_table (CGEN_CPU_TABLE *cd)
1599 {
1600   int i;
1601   const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
1602   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1603
1604   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1605   for (i = 0; i < MAX_INSNS; ++i)
1606     insns[i].base = &ib[i];
1607   cd->insn_table.init_entries = insns;
1608   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1609   cd->insn_table.num_init_entries = MAX_INSNS;
1610 }
1611
1612 /* Subroutine of bpf_cgen_cpu_open to rebuild the tables.  */
1613
1614 static void
1615 bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1616 {
1617   int i;
1618   CGEN_BITSET *isas = cd->isas;
1619   unsigned int machs = cd->machs;
1620
1621   cd->int_insn_p = CGEN_INT_INSN_P;
1622
1623   /* Data derived from the isa spec.  */
1624 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1625   cd->default_insn_bitsize = UNSET;
1626   cd->base_insn_bitsize = UNSET;
1627   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1628   cd->max_insn_bitsize = 0;
1629   for (i = 0; i < MAX_ISAS; ++i)
1630     if (cgen_bitset_contains (isas, i))
1631       {
1632         const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
1633
1634         /* Default insn sizes of all selected isas must be
1635            equal or we set the result to 0, meaning "unknown".  */
1636         if (cd->default_insn_bitsize == UNSET)
1637           cd->default_insn_bitsize = isa->default_insn_bitsize;
1638         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1639           ; /* This is ok.  */
1640         else
1641           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1642
1643         /* Base insn sizes of all selected isas must be equal
1644            or we set the result to 0, meaning "unknown".  */
1645         if (cd->base_insn_bitsize == UNSET)
1646           cd->base_insn_bitsize = isa->base_insn_bitsize;
1647         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1648           ; /* This is ok.  */
1649         else
1650           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1651
1652         /* Set min,max insn sizes.  */
1653         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1654           cd->min_insn_bitsize = isa->min_insn_bitsize;
1655         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1656           cd->max_insn_bitsize = isa->max_insn_bitsize;
1657       }
1658
1659   /* Data derived from the mach spec.  */
1660   for (i = 0; i < MAX_MACHS; ++i)
1661     if (((1 << i) & machs) != 0)
1662       {
1663         const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
1664
1665         if (mach->insn_chunk_bitsize != 0)
1666         {
1667           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1668             {
1669               opcodes_error_handler
1670                 (/* xgettext:c-format */
1671                  _("internal error: bpf_cgen_rebuild_tables: "
1672                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1673                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1674               abort ();
1675             }
1676
1677           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1678         }
1679       }
1680
1681   /* Determine which hw elements are used by MACH.  */
1682   build_hw_table (cd);
1683
1684   /* Build the ifield table.  */
1685   build_ifield_table (cd);
1686
1687   /* Determine which operands are used by MACH/ISA.  */
1688   build_operand_table (cd);
1689
1690   /* Build the instruction table.  */
1691   build_insn_table (cd);
1692 }
1693
1694 /* Initialize a cpu table and return a descriptor.
1695    It's much like opening a file, and must be the first function called.
1696    The arguments are a set of (type/value) pairs, terminated with
1697    CGEN_CPU_OPEN_END.
1698
1699    Currently supported values:
1700    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1701    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1702    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1703    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1704    CGEN_CPU_OPEN_END:     terminates arguments
1705
1706    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1707    precluded.  */
1708
1709 CGEN_CPU_DESC
1710 bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1711 {
1712   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1713   static int init_p;
1714   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1715   unsigned int machs = 0; /* 0 = "unspecified" */
1716   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1717   va_list ap;
1718
1719   if (! init_p)
1720     {
1721       init_tables ();
1722       init_p = 1;
1723     }
1724
1725   memset (cd, 0, sizeof (*cd));
1726
1727   va_start (ap, arg_type);
1728   while (arg_type != CGEN_CPU_OPEN_END)
1729     {
1730       switch (arg_type)
1731         {
1732         case CGEN_CPU_OPEN_ISAS :
1733           isas = va_arg (ap, CGEN_BITSET *);
1734           break;
1735         case CGEN_CPU_OPEN_MACHS :
1736           machs = va_arg (ap, unsigned int);
1737           break;
1738         case CGEN_CPU_OPEN_BFDMACH :
1739           {
1740             const char *name = va_arg (ap, const char *);
1741             const CGEN_MACH *mach =
1742               lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
1743
1744             if (mach != NULL)
1745               machs |= 1 << mach->num;
1746             break;
1747           }
1748         case CGEN_CPU_OPEN_ENDIAN :
1749           endian = va_arg (ap, enum cgen_endian);
1750           break;
1751         default :
1752           opcodes_error_handler
1753             (/* xgettext:c-format */
1754              _("internal error: bpf_cgen_cpu_open: "
1755                "unsupported argument `%d'"),
1756              arg_type);
1757           abort (); /* ??? return NULL? */
1758         }
1759       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1760     }
1761   va_end (ap);
1762
1763   /* Mach unspecified means "all".  */
1764   if (machs == 0)
1765     machs = (1 << MAX_MACHS) - 1;
1766   /* Base mach is always selected.  */
1767   machs |= 1;
1768   if (endian == CGEN_ENDIAN_UNKNOWN)
1769     {
1770       /* ??? If target has only one, could have a default.  */
1771       opcodes_error_handler
1772         (/* xgettext:c-format */
1773          _("internal error: bpf_cgen_cpu_open: no endianness specified"));
1774       abort ();
1775     }
1776
1777   cd->isas = cgen_bitset_copy (isas);
1778   cd->machs = machs;
1779   cd->endian = endian;
1780   /* FIXME: for the sparc case we can determine insn-endianness statically.
1781      The worry here is where both data and insn endian can be independently
1782      chosen, in which case this function will need another argument.
1783      Actually, will want to allow for more arguments in the future anyway.  */
1784   cd->insn_endian = endian;
1785
1786   /* Table (re)builder.  */
1787   cd->rebuild_tables = bpf_cgen_rebuild_tables;
1788   bpf_cgen_rebuild_tables (cd);
1789
1790   /* Default to not allowing signed overflow.  */
1791   cd->signed_overflow_ok_p = 0;
1792
1793   return (CGEN_CPU_DESC) cd;
1794 }
1795
1796 /* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1797    MACH_NAME is the bfd name of the mach.  */
1798
1799 CGEN_CPU_DESC
1800 bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1801 {
1802   return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1803                                CGEN_CPU_OPEN_ENDIAN, endian,
1804                                CGEN_CPU_OPEN_END);
1805 }
1806
1807 /* Close a cpu table.
1808    ??? This can live in a machine independent file, but there's currently
1809    no place to put this file (there's no libcgen).  libopcodes is the wrong
1810    place as some simulator ports use this but they don't use libopcodes.  */
1811
1812 void
1813 bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
1814 {
1815   unsigned int i;
1816   const CGEN_INSN *insns;
1817
1818   if (cd->macro_insn_table.init_entries)
1819     {
1820       insns = cd->macro_insn_table.init_entries;
1821       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1822         if (CGEN_INSN_RX ((insns)))
1823           regfree (CGEN_INSN_RX (insns));
1824     }
1825
1826   if (cd->insn_table.init_entries)
1827     {
1828       insns = cd->insn_table.init_entries;
1829       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1830         if (CGEN_INSN_RX (insns))
1831           regfree (CGEN_INSN_RX (insns));
1832     }
1833
1834   free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1835   free ((CGEN_INSN *) cd->insn_table.init_entries);
1836   free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1837   free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1838   free (cd);
1839 }
1840