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1 /* Disassemble h8300 instructions.
2 Copyright (C) 1993-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #define DEFINE_TABLE
22
23 #include "sysdep.h"
24 #define h8_opcodes h8ops
25 #include "opcode/h8300.h"
26 #include "disassemble.h"
27 #include "opintl.h"
28 #include "libiberty.h"
29
30 struct h8_instruction
31 {
32 int length;
33 const struct h8_opcode *opcode;
34 };
35
36 struct h8_instruction *h8_instructions;
37
38 /* Run through the opcodes and sort them into order to make them easy
39 to disassemble. */
40
41 static void
42 bfd_h8_disassemble_init (void)
43 {
44 unsigned int i;
45 unsigned int nopcodes;
46 const struct h8_opcode *p;
47 struct h8_instruction *pi;
48
49 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
50
51 h8_instructions = xmalloc (nopcodes * sizeof (struct h8_instruction));
52
53 for (p = h8_opcodes, pi = h8_instructions; p->name; p++, pi++)
54 {
55 /* Just make sure there are an even number of nibbles in it, and
56 that the count is the same as the length. */
57 for (i = 0; p->data.nib[i] != (op_type) E; i++)
58 ;
59
60 if (i & 1)
61 {
62 /* xgettext:c-format */
63 opcodes_error_handler (_("internal error, h8_disassemble_init"));
64 abort ();
65 }
66
67 pi->length = i / 2;
68 pi->opcode = p;
69 }
70
71 /* Add entry for the NULL vector terminator. */
72 pi->length = 0;
73 pi->opcode = p;
74 }
75
76 static void
77 extract_immediate (FILE *stream,
78 op_type looking_for,
79 int thisnib,
80 unsigned char *data,
81 int *cst,
82 int *len,
83 const struct h8_opcode *q)
84 {
85 switch (looking_for & SIZE)
86 {
87 case L_2:
88 *len = 2;
89 *cst = thisnib & 3;
90
91 /* DISP2 special treatment. */
92 if ((looking_for & MODE) == DISP)
93 {
94 if (OP_KIND (q->how) == O_MOVAB
95 || OP_KIND (q->how) == O_MOVAW
96 || OP_KIND (q->how) == O_MOVAL)
97 {
98 /* Handling for mova insn. */
99 switch (q->args.nib[0] & MODE)
100 {
101 case INDEXB:
102 default:
103 break;
104 case INDEXW:
105 *cst *= 2;
106 break;
107 case INDEXL:
108 *cst *= 4;
109 break;
110 }
111 }
112 else
113 {
114 /* Handling for non-mova insn. */
115 switch (OP_SIZE (q->how))
116 {
117 default: break;
118 case SW:
119 *cst *= 2;
120 break;
121 case SL:
122 *cst *= 4;
123 break;
124 }
125 }
126 }
127 break;
128 case L_8:
129 *len = 8;
130 *cst = data[0];
131 break;
132 case L_16:
133 case L_16U:
134 *len = 16;
135 *cst = (data[0] << 8) + data [1];
136 #if 0
137 if ((looking_for & SIZE) == L_16)
138 *cst = (short) *cst; /* Sign extend. */
139 #endif
140 break;
141 case L_32:
142 *len = 32;
143 *cst = (((unsigned) data[0] << 24) + (data[1] << 16)
144 + (data[2] << 8) + data[3]);
145 break;
146 default:
147 *len = 0;
148 *cst = 0;
149 fprintf (stream, "DISP bad size\n");
150 break;
151 }
152 }
153
154 static const char *regnames[] =
155 {
156 "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h",
157 "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l"
158 };
159 static const char *wregnames[] =
160 {
161 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
162 "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"
163 };
164 static const char *lregnames[] =
165 {
166 "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7",
167 "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"
168 };
169 static const char *cregnames[] =
170 {
171 "ccr", "exr", "mach", "macl", "", "", "vbr", "sbr"
172 };
173
174 static void
175 print_one_arg (disassemble_info *info,
176 bfd_vma addr,
177 op_type x,
178 int cst,
179 int cstlen,
180 int rdisp_n,
181 int rn,
182 const char **pregnames,
183 int len)
184 {
185 void * stream = info->stream;
186 fprintf_ftype outfn = info->fprintf_func;
187
188 if ((x & SIZE) == L_3 || (x & SIZE) == L_3NZ)
189 outfn (stream, "#0x%x", (unsigned) cst);
190 else if ((x & MODE) == IMM)
191 outfn (stream, "#0x%x", (unsigned) cst);
192 else if ((x & MODE) == DBIT || (x & MODE) == KBIT)
193 outfn (stream, "#%d", (unsigned) cst);
194 else if ((x & MODE) == CONST_2)
195 outfn (stream, "#2");
196 else if ((x & MODE) == CONST_4)
197 outfn (stream, "#4");
198 else if ((x & MODE) == CONST_8)
199 outfn (stream, "#8");
200 else if ((x & MODE) == CONST_16)
201 outfn (stream, "#16");
202 else if ((x & MODE) == REG)
203 {
204 switch (x & SIZE)
205 {
206 case L_8:
207 outfn (stream, "%s", regnames[rn]);
208 break;
209 case L_16:
210 case L_16U:
211 outfn (stream, "%s", wregnames[rn]);
212 break;
213 case L_P:
214 case L_32:
215 outfn (stream, "%s", lregnames[rn]);
216 break;
217 }
218 }
219 else if ((x & MODE) == LOWREG)
220 {
221 switch (x & SIZE)
222 {
223 case L_8:
224 /* Always take low half of reg. */
225 outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]);
226 break;
227 case L_16:
228 case L_16U:
229 /* Always take low half of reg. */
230 outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn - 8]);
231 break;
232 case L_P:
233 case L_32:
234 outfn (stream, "%s.l", lregnames[rn]);
235 break;
236 }
237 }
238 else if ((x & MODE) == POSTINC)
239 outfn (stream, "@%s+", pregnames[rn]);
240
241 else if ((x & MODE) == POSTDEC)
242 outfn (stream, "@%s-", pregnames[rn]);
243
244 else if ((x & MODE) == PREINC)
245 outfn (stream, "@+%s", pregnames[rn]);
246
247 else if ((x & MODE) == PREDEC)
248 outfn (stream, "@-%s", pregnames[rn]);
249
250 else if ((x & MODE) == IND)
251 outfn (stream, "@%s", pregnames[rn]);
252
253 else if ((x & MODE) == ABS || (x & ABSJMP))
254 outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen);
255
256 else if ((x & MODE) == MEMIND)
257 outfn (stream, "@@%d (0x%x)", cst, cst);
258
259 else if ((x & MODE) == VECIND)
260 {
261 /* FIXME Multiplier should be 2 or 4, depending on processor mode,
262 by which is meant "normal" vs. "middle", "advanced", "maximum". */
263
264 int offset = (cst + 0x80) * 4;
265 outfn (stream, "@@%d (0x%x)", offset, offset);
266 }
267 else if ((x & MODE) == PCREL)
268 {
269 if ((x & SIZE) == L_16 ||
270 (x & SIZE) == L_16U)
271 {
272 outfn (stream, ".%s%d (0x%lx)",
273 (short) cst > 0 ? "+" : "",
274 (short) cst,
275 (long)(addr + (short) cst + len));
276 }
277 else
278 {
279 outfn (stream, ".%s%d (0x%lx)",
280 (char) cst > 0 ? "+" : "",
281 (char) cst,
282 (long)(addr + (char) cst + len));
283 }
284 }
285 else if ((x & MODE) == DISP)
286 outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]);
287
288 else if ((x & MODE) == INDEXB)
289 /* Always take low half of reg. */
290 outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
291 regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
292
293 else if ((x & MODE) == INDEXW)
294 /* Always take low half of reg. */
295 outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
296 wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
297
298 else if ((x & MODE) == INDEXL)
299 outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
300
301 else if (x & CTRL)
302 outfn (stream, "%s", cregnames[rn]);
303
304 else if ((x & MODE) == CCR)
305 outfn (stream, "ccr");
306
307 else if ((x & MODE) == EXR)
308 outfn (stream, "exr");
309
310 else if ((x & MODE) == MACREG)
311 outfn (stream, "mac%c", cst ? 'l' : 'h');
312
313 else
314 /* xgettext:c-format */
315 outfn (stream, _("Hmmmm 0x%x"), x);
316 }
317
318 static unsigned int
319 bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
320 {
321 /* Find the first entry in the table for this opcode. */
322 int regno[3] = { 0, 0, 0 };
323 int dispregno[3] = { 0, 0, 0 };
324 int cst[3] = { 0, 0, 0 };
325 int cstlen[3] = { 0, 0, 0 };
326 static bfd_boolean init = 0;
327 const struct h8_instruction *qi;
328 char const **pregnames = mach != 0 ? lregnames : wregnames;
329 int status;
330 unsigned int l;
331 unsigned char data[MAX_CODE_NIBBLES];
332 void *stream = info->stream;
333 fprintf_ftype outfn = info->fprintf_func;
334
335 if (!init)
336 {
337 bfd_h8_disassemble_init ();
338 init = 1;
339 }
340
341 status = info->read_memory_func (addr, data, 2, info);
342 if (status != 0)
343 {
344 info->memory_error_func (status, addr, info);
345 return -1;
346 }
347
348 for (l = 2; status == 0 && l < sizeof (data) / 2; l += 2)
349 status = info->read_memory_func (addr + l, data + l, 2, info);
350
351 /* Find the exact opcode/arg combo. */
352 for (qi = h8_instructions; qi->opcode->name; qi++)
353 {
354 const struct h8_opcode *q = qi->opcode;
355 const op_type *nib = q->data.nib;
356 unsigned int len = 0;
357
358 while (1)
359 {
360 op_type looking_for = *nib;
361 int thisnib = data[len / 2];
362 int opnr;
363
364 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib / 16) & 0xf);
365 opnr = ((looking_for & OP3) == OP3 ? 2
366 : (looking_for & DST) == DST ? 1 : 0);
367
368 if (looking_for < 16 && looking_for >= 0)
369 {
370 if (looking_for != thisnib)
371 goto fail;
372 }
373 else
374 {
375 if ((int) looking_for & (int) B31)
376 {
377 if (!((thisnib & 0x8) != 0))
378 goto fail;
379
380 looking_for = (op_type) ((int) looking_for & ~(int) B31);
381 thisnib &= 0x7;
382 }
383 else if ((int) looking_for & (int) B30)
384 {
385 if (!((thisnib & 0x8) == 0))
386 goto fail;
387
388 looking_for = (op_type) ((int) looking_for & ~(int) B30);
389 }
390
391 if ((int) looking_for & (int) B21)
392 {
393 if (!((thisnib & 0x4) != 0))
394 goto fail;
395
396 looking_for = (op_type) ((int) looking_for & ~(int) B21);
397 thisnib &= 0xb;
398 }
399 else if ((int) looking_for & (int) B20)
400 {
401 if (!((thisnib & 0x4) == 0))
402 goto fail;
403
404 looking_for = (op_type) ((int) looking_for & ~(int) B20);
405 }
406 if ((int) looking_for & (int) B11)
407 {
408 if (!((thisnib & 0x2) != 0))
409 goto fail;
410
411 looking_for = (op_type) ((int) looking_for & ~(int) B11);
412 thisnib &= 0xd;
413 }
414 else if ((int) looking_for & (int) B10)
415 {
416 if (!((thisnib & 0x2) == 0))
417 goto fail;
418
419 looking_for = (op_type) ((int) looking_for & ~(int) B10);
420 }
421
422 if ((int) looking_for & (int) B01)
423 {
424 if (!((thisnib & 0x1) != 0))
425 goto fail;
426
427 looking_for = (op_type) ((int) looking_for & ~(int) B01);
428 thisnib &= 0xe;
429 }
430 else if ((int) looking_for & (int) B00)
431 {
432 if (!((thisnib & 0x1) == 0))
433 goto fail;
434
435 looking_for = (op_type) ((int) looking_for & ~(int) B00);
436 }
437
438 if (looking_for & IGNORE)
439 {
440 /* Hitachi has declared that IGNORE must be zero. */
441 if (thisnib != 0)
442 goto fail;
443 }
444 else if ((looking_for & MODE) == DATA)
445 {
446 ; /* Skip embedded data. */
447 }
448 else if ((looking_for & MODE) == DBIT)
449 {
450 /* Exclude adds/subs by looking at bit 0 and 2, and
451 make sure the operand size, either w or l,
452 matches by looking at bit 1. */
453 if ((looking_for & 7) != (thisnib & 7))
454 goto fail;
455
456 cst[opnr] = (thisnib & 0x8) ? 2 : 1;
457 }
458 else if ((looking_for & MODE) == DISP
459 || (looking_for & MODE) == ABS
460 || (looking_for & MODE) == PCREL
461 || (looking_for & MODE) == INDEXB
462 || (looking_for & MODE) == INDEXW
463 || (looking_for & MODE) == INDEXL)
464 {
465 extract_immediate (stream, looking_for, thisnib,
466 data + len / 2, cst + opnr,
467 cstlen + opnr, q);
468 /* Even address == bra, odd == bra/s. */
469 if (q->how == O (O_BRAS, SB))
470 cst[opnr] -= 1;
471 }
472 else if ((looking_for & MODE) == REG
473 || (looking_for & MODE) == LOWREG
474 || (looking_for & MODE) == IND
475 || (looking_for & MODE) == PREINC
476 || (looking_for & MODE) == POSTINC
477 || (looking_for & MODE) == PREDEC
478 || (looking_for & MODE) == POSTDEC)
479 {
480 regno[opnr] = thisnib;
481 }
482 else if (looking_for & CTRL) /* Control Register. */
483 {
484 thisnib &= 7;
485 if (((looking_for & MODE) == CCR && (thisnib != C_CCR))
486 || ((looking_for & MODE) == EXR && (thisnib != C_EXR))
487 || ((looking_for & MODE) == MACH && (thisnib != C_MACH))
488 || ((looking_for & MODE) == MACL && (thisnib != C_MACL))
489 || ((looking_for & MODE) == VBR && (thisnib != C_VBR))
490 || ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
491 goto fail;
492 if (((looking_for & MODE) == CCR_EXR
493 && (thisnib != C_CCR && thisnib != C_EXR))
494 || ((looking_for & MODE) == VBR_SBR
495 && (thisnib != C_VBR && thisnib != C_SBR))
496 || ((looking_for & MODE) == MACREG
497 && (thisnib != C_MACH && thisnib != C_MACL)))
498 goto fail;
499 if (((looking_for & MODE) == CC_EX_VB_SB
500 && (thisnib != C_CCR && thisnib != C_EXR
501 && thisnib != C_VBR && thisnib != C_SBR)))
502 goto fail;
503
504 regno[opnr] = thisnib;
505 }
506 else if ((looking_for & SIZE) == L_5)
507 {
508 cst[opnr] = data[len / 2] & 31;
509 cstlen[opnr] = 5;
510 }
511 else if ((looking_for & SIZE) == L_4)
512 {
513 cst[opnr] = thisnib;
514 cstlen[opnr] = 4;
515 }
516 else if ((looking_for & SIZE) == L_16
517 || (looking_for & SIZE) == L_16U)
518 {
519 cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2];
520 cstlen[opnr] = 16;
521 }
522 else if ((looking_for & MODE) == MEMIND)
523 {
524 cst[opnr] = data[1];
525 }
526 else if ((looking_for & MODE) == VECIND)
527 {
528 cst[opnr] = data[1] & 0x7f;
529 }
530 else if ((looking_for & SIZE) == L_32)
531 {
532 int i = len / 2;
533
534 cst[opnr] = (((unsigned) data[i] << 24)
535 | (data[i + 1] << 16)
536 | (data[i + 2] << 8)
537 | (data[i + 3]));
538
539 cstlen[opnr] = 32;
540 }
541 else if ((looking_for & SIZE) == L_24)
542 {
543 int i = len / 2;
544
545 cst[opnr] =
546 (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
547 cstlen[opnr] = 24;
548 }
549 else if (looking_for & DISPREG)
550 {
551 dispregno[opnr] = thisnib & 7;
552 }
553 else if ((looking_for & MODE) == KBIT)
554 {
555 switch (thisnib)
556 {
557 case 9:
558 cst[opnr] = 4;
559 break;
560 case 8:
561 cst[opnr] = 2;
562 break;
563 case 0:
564 cst[opnr] = 1;
565 break;
566 default:
567 goto fail;
568 }
569 }
570 else if ((looking_for & SIZE) == L_8)
571 {
572 cstlen[opnr] = 8;
573 cst[opnr] = data[len / 2];
574 }
575 else if ((looking_for & SIZE) == L_3
576 || (looking_for & SIZE) == L_3NZ)
577 {
578 cst[opnr] = thisnib & 0x7;
579 if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ)
580 goto fail;
581 }
582 else if ((looking_for & SIZE) == L_2)
583 {
584 cstlen[opnr] = 2;
585 cst[opnr] = thisnib & 0x3;
586 }
587 else if ((looking_for & MODE) == MACREG)
588 {
589 cst[opnr] = (thisnib == 3);
590 }
591 else if (looking_for == (op_type) E)
592 {
593 outfn (stream, "%s\t", q->name);
594
595 /* Gross. Disgusting. */
596 if (strcmp (q->name, "ldm.l") == 0)
597 {
598 int count, high;
599
600 count = (data[1] / 16) & 0x3;
601 high = regno[1];
602
603 outfn (stream, "@sp+,er%d-er%d", high - count, high);
604 return qi->length;
605 }
606
607 if (strcmp (q->name, "stm.l") == 0)
608 {
609 int count, low;
610
611 count = (data[1] / 16) & 0x3;
612 low = regno[0];
613
614 outfn (stream, "er%d-er%d,@-sp", low, low + count);
615 return qi->length;
616 }
617 if (strcmp (q->name, "rte/l") == 0
618 || strcmp (q->name, "rts/l") == 0)
619 {
620 if (regno[0] == 0)
621 outfn (stream, "er%d", regno[1]);
622 else
623 outfn (stream, "er%d-er%d", regno[1] - regno[0],
624 regno[1]);
625 return qi->length;
626 }
627 if (CONST_STRNEQ (q->name, "mova"))
628 {
629 const op_type *args = q->args.nib;
630
631 if (args[1] == (op_type) E)
632 {
633 /* Short form. */
634 print_one_arg (info, addr, args[0], cst[0],
635 cstlen[0], dispregno[0], regno[0],
636 pregnames, qi->length);
637 outfn (stream, ",er%d", dispregno[0]);
638 }
639 else
640 {
641 outfn (stream, "@(0x%x:%d,", cst[0], cstlen[0]);
642 print_one_arg (info, addr, args[1], cst[1],
643 cstlen[1], dispregno[1], regno[1],
644 pregnames, qi->length);
645 outfn (stream, ".%c),",
646 (args[0] & MODE) == INDEXB ? 'b' : 'w');
647 print_one_arg (info, addr, args[2], cst[2],
648 cstlen[2], dispregno[2], regno[2],
649 pregnames, qi->length);
650 }
651 return qi->length;
652 }
653 /* Fill in the args. */
654 {
655 const op_type *args = q->args.nib;
656 int hadone = 0;
657 int nargs;
658
659 /* Special case handling for the adds and subs instructions
660 since in H8 mode thay can only take the r0-r7 registers
661 but in other (higher) modes they can take the er0-er7
662 registers as well. */
663 if (strcmp (qi->opcode->name, "adds") == 0
664 || strcmp (qi->opcode->name, "subs") == 0)
665 {
666 outfn (stream, "#%d,%s", cst[0], pregnames[regno[1] & 0x7]);
667 return qi->length;
668 }
669
670 for (nargs = 0;
671 nargs < 3 && args[nargs] != (op_type) E;
672 nargs++)
673 {
674 int x = args[nargs];
675
676 if (hadone)
677 outfn (stream, ",");
678
679 print_one_arg (info, addr, x,
680 cst[nargs], cstlen[nargs],
681 dispregno[nargs], regno[nargs],
682 pregnames, qi->length);
683
684 hadone = 1;
685 }
686 }
687
688 return qi->length;
689 }
690 else
691 /* xgettext:c-format */
692 outfn (stream, _("Don't understand 0x%x \n"), looking_for);
693 }
694
695 len++;
696 nib++;
697 }
698
699 fail:
700 ;
701 }
702
703 /* Fell off the end. */
704 outfn (stream, ".word\tH'%x,H'%x", data[0], data[1]);
705 return 2;
706 }
707
708 int
709 print_insn_h8300 (bfd_vma addr, disassemble_info *info)
710 {
711 return bfd_h8_disassemble (addr, info, 0);
712 }
713
714 int
715 print_insn_h8300h (bfd_vma addr, disassemble_info *info)
716 {
717 return bfd_h8_disassemble (addr, info, 1);
718 }
719
720 int
721 print_insn_h8300s (bfd_vma addr, disassemble_info *info)
722 {
723 return bfd_h8_disassemble (addr, info, 2);
724 }