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[thirdparty/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2023 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48
49 static bool OP_E (instr_info *, int, int);
50 static bool OP_E_memory (instr_info *, int, int);
51 static bool OP_indirE (instr_info *, int, int);
52 static bool OP_G (instr_info *, int, int);
53 static bool OP_ST (instr_info *, int, int);
54 static bool OP_STi (instr_info *, int, int);
55 static bool OP_Skip_MODRM (instr_info *, int, int);
56 static bool OP_REG (instr_info *, int, int);
57 static bool OP_IMREG (instr_info *, int, int);
58 static bool OP_I (instr_info *, int, int);
59 static bool OP_I64 (instr_info *, int, int);
60 static bool OP_sI (instr_info *, int, int);
61 static bool OP_J (instr_info *, int, int);
62 static bool OP_SEG (instr_info *, int, int);
63 static bool OP_DIR (instr_info *, int, int);
64 static bool OP_OFF (instr_info *, int, int);
65 static bool OP_OFF64 (instr_info *, int, int);
66 static bool OP_ESreg (instr_info *, int, int);
67 static bool OP_DSreg (instr_info *, int, int);
68 static bool OP_C (instr_info *, int, int);
69 static bool OP_D (instr_info *, int, int);
70 static bool OP_T (instr_info *, int, int);
71 static bool OP_MMX (instr_info *, int, int);
72 static bool OP_XMM (instr_info *, int, int);
73 static bool OP_EM (instr_info *, int, int);
74 static bool OP_EX (instr_info *, int, int);
75 static bool OP_EMC (instr_info *, int,int);
76 static bool OP_MXC (instr_info *, int,int);
77 static bool OP_MS (instr_info *, int, int);
78 static bool OP_XS (instr_info *, int, int);
79 static bool OP_M (instr_info *, int, int);
80 static bool OP_VEX (instr_info *, int, int);
81 static bool OP_VexR (instr_info *, int, int);
82 static bool OP_VexW (instr_info *, int, int);
83 static bool OP_Rounding (instr_info *, int, int);
84 static bool OP_REG_VexI4 (instr_info *, int, int);
85 static bool OP_VexI4 (instr_info *, int, int);
86 static bool OP_0f07 (instr_info *, int, int);
87 static bool OP_Monitor (instr_info *, int, int);
88 static bool OP_Mwait (instr_info *, int, int);
89
90 static bool PCLMUL_Fixup (instr_info *, int, int);
91 static bool VPCMP_Fixup (instr_info *, int, int);
92 static bool VPCOM_Fixup (instr_info *, int, int);
93 static bool NOP_Fixup (instr_info *, int, int);
94 static bool OP_3DNowSuffix (instr_info *, int, int);
95 static bool CMP_Fixup (instr_info *, int, int);
96 static bool REP_Fixup (instr_info *, int, int);
97 static bool SEP_Fixup (instr_info *, int, int);
98 static bool BND_Fixup (instr_info *, int, int);
99 static bool NOTRACK_Fixup (instr_info *, int, int);
100 static bool HLE_Fixup1 (instr_info *, int, int);
101 static bool HLE_Fixup2 (instr_info *, int, int);
102 static bool HLE_Fixup3 (instr_info *, int, int);
103 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
104 static bool XMM_Fixup (instr_info *, int, int);
105 static bool FXSAVE_Fixup (instr_info *, int, int);
106 static bool MOVSXD_Fixup (instr_info *, int, int);
107 static bool DistinctDest_Fixup (instr_info *, int, int);
108 static bool PREFETCHI_Fixup (instr_info *, int, int);
109
110 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
111 enum disassembler_style,
112 const char *, ...);
113
114 /* This character is used to encode style information within the output
115 buffers. See oappend_insert_style for more details. */
116 #define STYLE_MARKER_CHAR '\002'
117
118 /* The maximum operand buffer size. */
119 #define MAX_OPERAND_BUFFER_SIZE 128
120
121 enum address_mode
122 {
123 mode_16bit,
124 mode_32bit,
125 mode_64bit
126 };
127
128 static const char *prefix_name (enum address_mode, uint8_t, int);
129
130 enum x86_64_isa
131 {
132 amd64 = 1,
133 intel64
134 };
135
136 struct instr_info
137 {
138 enum address_mode address_mode;
139
140 /* Flags for the prefixes for the current instruction. See below. */
141 int prefixes;
142
143 /* REX prefix the current instruction. See below. */
144 uint8_t rex;
145 /* Bits of REX we've already used. */
146 uint8_t rex_used;
147
148 bool need_modrm;
149 bool need_vex;
150 bool has_sib;
151
152 /* Flags for ins->prefixes which we somehow handled when printing the
153 current instruction. */
154 int used_prefixes;
155
156 /* Flags for EVEX bits which we somehow handled when printing the
157 current instruction. */
158 int evex_used;
159
160 char obuf[MAX_OPERAND_BUFFER_SIZE];
161 char *obufp;
162 char *mnemonicendp;
163 const uint8_t *start_codep;
164 uint8_t *codep;
165 const uint8_t *end_codep;
166 unsigned char nr_prefixes;
167 signed char last_lock_prefix;
168 signed char last_repz_prefix;
169 signed char last_repnz_prefix;
170 signed char last_data_prefix;
171 signed char last_addr_prefix;
172 signed char last_rex_prefix;
173 signed char last_seg_prefix;
174 signed char fwait_prefix;
175 /* The active segment register prefix. */
176 unsigned char active_seg_prefix;
177
178 #define MAX_CODE_LENGTH 15
179 /* We can up to 14 ins->prefixes since the maximum instruction length is
180 15bytes. */
181 uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
182 disassemble_info *info;
183
184 struct
185 {
186 int mod;
187 int reg;
188 int rm;
189 }
190 modrm;
191
192 struct
193 {
194 int scale;
195 int index;
196 int base;
197 }
198 sib;
199
200 struct
201 {
202 int register_specifier;
203 int length;
204 int prefix;
205 int mask_register_specifier;
206 int ll;
207 bool w;
208 bool evex;
209 bool r;
210 bool v;
211 bool zeroing;
212 bool b;
213 bool no_broadcast;
214 }
215 vex;
216
217 /* Remember if the current op is a jump instruction. */
218 bool op_is_jump;
219
220 bool two_source_ops;
221
222 unsigned char op_ad;
223 signed char op_index[MAX_OPERANDS];
224 bool op_riprel[MAX_OPERANDS];
225 char *op_out[MAX_OPERANDS];
226 bfd_vma op_address[MAX_OPERANDS];
227 bfd_vma start_pc;
228
229 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
230 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
231 * section of the "Virtual 8086 Mode" chapter.)
232 * 'pc' should be the address of this instruction, it will
233 * be used to print the target address if this is a relative jump or call
234 * The function returns the length of this instruction in bytes.
235 */
236 char intel_syntax;
237 bool intel_mnemonic;
238 char open_char;
239 char close_char;
240 char separator_char;
241 char scale_char;
242
243 enum x86_64_isa isa64;
244 };
245
246 struct dis_private {
247 bfd_vma insn_start;
248 int orig_sizeflag;
249
250 /* Indexes first byte not fetched. */
251 unsigned int fetched;
252 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
253 };
254
255 /* Mark parts used in the REX prefix. When we are testing for
256 empty prefix (for 8bit register REX extension), just mask it
257 out. Otherwise test for REX bit is excuse for existence of REX
258 only in case value is nonzero. */
259 #define USED_REX(value) \
260 { \
261 if (value) \
262 { \
263 if ((ins->rex & value)) \
264 ins->rex_used |= (value) | REX_OPCODE; \
265 } \
266 else \
267 ins->rex_used |= REX_OPCODE; \
268 }
269
270
271 #define EVEX_b_used 1
272 #define EVEX_len_used 2
273
274 /* Flags stored in PREFIXES. */
275 #define PREFIX_REPZ 1
276 #define PREFIX_REPNZ 2
277 #define PREFIX_CS 4
278 #define PREFIX_SS 8
279 #define PREFIX_DS 0x10
280 #define PREFIX_ES 0x20
281 #define PREFIX_FS 0x40
282 #define PREFIX_GS 0x80
283 #define PREFIX_LOCK 0x100
284 #define PREFIX_DATA 0x200
285 #define PREFIX_ADDR 0x400
286 #define PREFIX_FWAIT 0x800
287
288 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
289 to ADDR (exclusive) are valid. Returns true for success, false
290 on error. */
291 static bool
292 fetch_code (struct disassemble_info *info, const uint8_t *until)
293 {
294 int status = -1;
295 struct dis_private *priv = info->private_data;
296 bfd_vma start = priv->insn_start + priv->fetched;
297 uint8_t *fetch_end = priv->the_buffer + priv->fetched;
298 ptrdiff_t needed = until - fetch_end;
299
300 if (needed <= 0)
301 return true;
302
303 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
304 status = (*info->read_memory_func) (start, fetch_end, needed, info);
305 if (status != 0)
306 {
307 /* If we did manage to read at least one byte, then
308 print_insn_i386 will do something sensible. Otherwise, print
309 an error. We do that here because this is where we know
310 STATUS. */
311 if (!priv->fetched)
312 (*info->memory_error_func) (status, start, info);
313 return false;
314 }
315
316 priv->fetched += needed;
317 return true;
318 }
319
320 static bool
321 fetch_modrm (instr_info *ins)
322 {
323 if (!fetch_code (ins->info, ins->codep + 1))
324 return false;
325
326 ins->modrm.mod = (*ins->codep >> 6) & 3;
327 ins->modrm.reg = (*ins->codep >> 3) & 7;
328 ins->modrm.rm = *ins->codep & 7;
329
330 return true;
331 }
332
333 static int
334 fetch_error (const instr_info *ins)
335 {
336 /* Getting here means we tried for data but didn't get it. That
337 means we have an incomplete instruction of some sort. Just
338 print the first byte as a prefix or a .byte pseudo-op. */
339 const struct dis_private *priv = ins->info->private_data;
340 const char *name = NULL;
341
342 if (ins->codep <= priv->the_buffer)
343 return -1;
344
345 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
346 name = prefix_name (ins->address_mode, priv->the_buffer[0],
347 priv->orig_sizeflag);
348 if (name != NULL)
349 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
350 else
351 {
352 /* Just print the first byte as a .byte instruction. */
353 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
354 i386_dis_printf (ins->info, dis_style_immediate, "%#x",
355 (unsigned int) priv->the_buffer[0]);
356 }
357
358 return 1;
359 }
360
361 /* Possible values for prefix requirement. */
362 #define PREFIX_IGNORED_SHIFT 16
363 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
364 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
365 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
366 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
367 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
368
369 /* Opcode prefixes. */
370 #define PREFIX_OPCODE (PREFIX_REPZ \
371 | PREFIX_REPNZ \
372 | PREFIX_DATA)
373
374 /* Prefixes ignored. */
375 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
376 | PREFIX_IGNORED_REPNZ \
377 | PREFIX_IGNORED_DATA)
378
379 #define XX { NULL, 0 }
380 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
381
382 #define Eb { OP_E, b_mode }
383 #define Ebnd { OP_E, bnd_mode }
384 #define EbS { OP_E, b_swap_mode }
385 #define EbndS { OP_E, bnd_swap_mode }
386 #define Ev { OP_E, v_mode }
387 #define Eva { OP_E, va_mode }
388 #define Ev_bnd { OP_E, v_bnd_mode }
389 #define EvS { OP_E, v_swap_mode }
390 #define Ed { OP_E, d_mode }
391 #define Edq { OP_E, dq_mode }
392 #define Edb { OP_E, db_mode }
393 #define Edw { OP_E, dw_mode }
394 #define Eq { OP_E, q_mode }
395 #define indirEv { OP_indirE, indir_v_mode }
396 #define indirEp { OP_indirE, f_mode }
397 #define stackEv { OP_E, stack_v_mode }
398 #define Em { OP_E, m_mode }
399 #define Ew { OP_E, w_mode }
400 #define M { OP_M, 0 } /* lea, lgdt, etc. */
401 #define Ma { OP_M, a_mode }
402 #define Mb { OP_M, b_mode }
403 #define Md { OP_M, d_mode }
404 #define Mdq { OP_M, dq_mode }
405 #define Mo { OP_M, o_mode }
406 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
407 #define Mq { OP_M, q_mode }
408 #define Mv { OP_M, v_mode }
409 #define Mv_bnd { OP_M, v_bndmk_mode }
410 #define Mw { OP_M, w_mode }
411 #define Mx { OP_M, x_mode }
412 #define Mxmm { OP_M, xmm_mode }
413 #define Gb { OP_G, b_mode }
414 #define Gbnd { OP_G, bnd_mode }
415 #define Gv { OP_G, v_mode }
416 #define Gd { OP_G, d_mode }
417 #define Gdq { OP_G, dq_mode }
418 #define Gm { OP_G, m_mode }
419 #define Gva { OP_G, va_mode }
420 #define Gw { OP_G, w_mode }
421 #define Ib { OP_I, b_mode }
422 #define sIb { OP_sI, b_mode } /* sign extened byte */
423 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
424 #define Iv { OP_I, v_mode }
425 #define sIv { OP_sI, v_mode }
426 #define Iv64 { OP_I64, v_mode }
427 #define Id { OP_I, d_mode }
428 #define Iw { OP_I, w_mode }
429 #define I1 { OP_I, const_1_mode }
430 #define Jb { OP_J, b_mode }
431 #define Jv { OP_J, v_mode }
432 #define Jdqw { OP_J, dqw_mode }
433 #define Cm { OP_C, m_mode }
434 #define Dm { OP_D, m_mode }
435 #define Td { OP_T, d_mode }
436 #define Skip_MODRM { OP_Skip_MODRM, 0 }
437
438 #define RMeAX { OP_REG, eAX_reg }
439 #define RMeBX { OP_REG, eBX_reg }
440 #define RMeCX { OP_REG, eCX_reg }
441 #define RMeDX { OP_REG, eDX_reg }
442 #define RMeSP { OP_REG, eSP_reg }
443 #define RMeBP { OP_REG, eBP_reg }
444 #define RMeSI { OP_REG, eSI_reg }
445 #define RMeDI { OP_REG, eDI_reg }
446 #define RMrAX { OP_REG, rAX_reg }
447 #define RMrBX { OP_REG, rBX_reg }
448 #define RMrCX { OP_REG, rCX_reg }
449 #define RMrDX { OP_REG, rDX_reg }
450 #define RMrSP { OP_REG, rSP_reg }
451 #define RMrBP { OP_REG, rBP_reg }
452 #define RMrSI { OP_REG, rSI_reg }
453 #define RMrDI { OP_REG, rDI_reg }
454 #define RMAL { OP_REG, al_reg }
455 #define RMCL { OP_REG, cl_reg }
456 #define RMDL { OP_REG, dl_reg }
457 #define RMBL { OP_REG, bl_reg }
458 #define RMAH { OP_REG, ah_reg }
459 #define RMCH { OP_REG, ch_reg }
460 #define RMDH { OP_REG, dh_reg }
461 #define RMBH { OP_REG, bh_reg }
462 #define RMAX { OP_REG, ax_reg }
463 #define RMDX { OP_REG, dx_reg }
464
465 #define eAX { OP_IMREG, eAX_reg }
466 #define AL { OP_IMREG, al_reg }
467 #define CL { OP_IMREG, cl_reg }
468 #define zAX { OP_IMREG, z_mode_ax_reg }
469 #define indirDX { OP_IMREG, indir_dx_reg }
470
471 #define Sw { OP_SEG, w_mode }
472 #define Sv { OP_SEG, v_mode }
473 #define Ap { OP_DIR, 0 }
474 #define Ob { OP_OFF64, b_mode }
475 #define Ov { OP_OFF64, v_mode }
476 #define Xb { OP_DSreg, eSI_reg }
477 #define Xv { OP_DSreg, eSI_reg }
478 #define Xz { OP_DSreg, eSI_reg }
479 #define Yb { OP_ESreg, eDI_reg }
480 #define Yv { OP_ESreg, eDI_reg }
481 #define DSBX { OP_DSreg, eBX_reg }
482
483 #define es { OP_REG, es_reg }
484 #define ss { OP_REG, ss_reg }
485 #define cs { OP_REG, cs_reg }
486 #define ds { OP_REG, ds_reg }
487 #define fs { OP_REG, fs_reg }
488 #define gs { OP_REG, gs_reg }
489
490 #define MX { OP_MMX, 0 }
491 #define XM { OP_XMM, 0 }
492 #define XMScalar { OP_XMM, scalar_mode }
493 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
494 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
495 #define XMM { OP_XMM, xmm_mode }
496 #define TMM { OP_XMM, tmm_mode }
497 #define XMxmmq { OP_XMM, xmmq_mode }
498 #define EM { OP_EM, v_mode }
499 #define EMS { OP_EM, v_swap_mode }
500 #define EMd { OP_EM, d_mode }
501 #define EMx { OP_EM, x_mode }
502 #define EXbwUnit { OP_EX, bw_unit_mode }
503 #define EXb { OP_EX, b_mode }
504 #define EXw { OP_EX, w_mode }
505 #define EXd { OP_EX, d_mode }
506 #define EXdS { OP_EX, d_swap_mode }
507 #define EXwS { OP_EX, w_swap_mode }
508 #define EXq { OP_EX, q_mode }
509 #define EXqS { OP_EX, q_swap_mode }
510 #define EXdq { OP_EX, dq_mode }
511 #define EXx { OP_EX, x_mode }
512 #define EXxh { OP_EX, xh_mode }
513 #define EXxS { OP_EX, x_swap_mode }
514 #define EXxmm { OP_EX, xmm_mode }
515 #define EXymm { OP_EX, ymm_mode }
516 #define EXtmm { OP_EX, tmm_mode }
517 #define EXxmmq { OP_EX, xmmq_mode }
518 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
519 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
520 #define EXxmmdw { OP_EX, xmmdw_mode }
521 #define EXxmmqd { OP_EX, xmmqd_mode }
522 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
523 #define EXymmq { OP_EX, ymmq_mode }
524 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
525 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
526 #define MS { OP_MS, v_mode }
527 #define XS { OP_XS, v_mode }
528 #define EMCq { OP_EMC, q_mode }
529 #define MXC { OP_MXC, 0 }
530 #define OPSUF { OP_3DNowSuffix, 0 }
531 #define SEP { SEP_Fixup, 0 }
532 #define CMP { CMP_Fixup, 0 }
533 #define XMM0 { XMM_Fixup, 0 }
534 #define FXSAVE { FXSAVE_Fixup, 0 }
535
536 #define Vex { OP_VEX, x_mode }
537 #define VexW { OP_VexW, x_mode }
538 #define VexScalar { OP_VEX, scalar_mode }
539 #define VexScalarR { OP_VexR, scalar_mode }
540 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
541 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
542 #define VexGdq { OP_VEX, dq_mode }
543 #define VexTmm { OP_VEX, tmm_mode }
544 #define XMVexI4 { OP_REG_VexI4, x_mode }
545 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
546 #define VexI4 { OP_VexI4, 0 }
547 #define PCLMUL { PCLMUL_Fixup, 0 }
548 #define VPCMP { VPCMP_Fixup, 0 }
549 #define VPCOM { VPCOM_Fixup, 0 }
550
551 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
552 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
553 #define EXxEVexS { OP_Rounding, evex_sae_mode }
554
555 #define MaskG { OP_G, mask_mode }
556 #define MaskE { OP_E, mask_mode }
557 #define MaskBDE { OP_E, mask_bd_mode }
558 #define MaskVex { OP_VEX, mask_mode }
559
560 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
561 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
562
563 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
564
565 /* Used handle "rep" prefix for string instructions. */
566 #define Xbr { REP_Fixup, eSI_reg }
567 #define Xvr { REP_Fixup, eSI_reg }
568 #define Ybr { REP_Fixup, eDI_reg }
569 #define Yvr { REP_Fixup, eDI_reg }
570 #define Yzr { REP_Fixup, eDI_reg }
571 #define indirDXr { REP_Fixup, indir_dx_reg }
572 #define ALr { REP_Fixup, al_reg }
573 #define eAXr { REP_Fixup, eAX_reg }
574
575 /* Used handle HLE prefix for lockable instructions. */
576 #define Ebh1 { HLE_Fixup1, b_mode }
577 #define Evh1 { HLE_Fixup1, v_mode }
578 #define Ebh2 { HLE_Fixup2, b_mode }
579 #define Evh2 { HLE_Fixup2, v_mode }
580 #define Ebh3 { HLE_Fixup3, b_mode }
581 #define Evh3 { HLE_Fixup3, v_mode }
582
583 #define BND { BND_Fixup, 0 }
584 #define NOTRACK { NOTRACK_Fixup, 0 }
585
586 #define cond_jump_flag { NULL, cond_jump_mode }
587 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
588
589 /* bits in sizeflag */
590 #define SUFFIX_ALWAYS 4
591 #define AFLAG 2
592 #define DFLAG 1
593
594 enum
595 {
596 /* byte operand */
597 b_mode = 1,
598 /* byte operand with operand swapped */
599 b_swap_mode,
600 /* byte operand, sign extend like 'T' suffix */
601 b_T_mode,
602 /* operand size depends on prefixes */
603 v_mode,
604 /* operand size depends on prefixes with operand swapped */
605 v_swap_mode,
606 /* operand size depends on address prefix */
607 va_mode,
608 /* word operand */
609 w_mode,
610 /* double word operand */
611 d_mode,
612 /* word operand with operand swapped */
613 w_swap_mode,
614 /* double word operand with operand swapped */
615 d_swap_mode,
616 /* quad word operand */
617 q_mode,
618 /* quad word operand with operand swapped */
619 q_swap_mode,
620 /* ten-byte operand */
621 t_mode,
622 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
623 broadcast enabled. */
624 x_mode,
625 /* Similar to x_mode, but with different EVEX mem shifts. */
626 evex_x_gscat_mode,
627 /* Similar to x_mode, but with yet different EVEX mem shifts. */
628 bw_unit_mode,
629 /* Similar to x_mode, but with disabled broadcast. */
630 evex_x_nobcst_mode,
631 /* Similar to x_mode, but with operands swapped and disabled broadcast
632 in EVEX. */
633 x_swap_mode,
634 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
635 broadcast of 16bit enabled. */
636 xh_mode,
637 /* 16-byte XMM operand */
638 xmm_mode,
639 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
640 memory operand (depending on vector length). Broadcast isn't
641 allowed. */
642 xmmq_mode,
643 /* Same as xmmq_mode, but broadcast is allowed. */
644 evex_half_bcst_xmmq_mode,
645 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
646 memory operand (depending on vector length). 16bit broadcast. */
647 evex_half_bcst_xmmqh_mode,
648 /* 16-byte XMM, word, double word or quad word operand. */
649 xmmdw_mode,
650 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
651 xmmqd_mode,
652 /* 16-byte XMM, double word, quad word operand or xmm word operand.
653 16bit broadcast. */
654 evex_half_bcst_xmmqdh_mode,
655 /* 32-byte YMM operand */
656 ymm_mode,
657 /* quad word, ymmword or zmmword memory operand. */
658 ymmq_mode,
659 /* TMM operand */
660 tmm_mode,
661 /* d_mode in 32bit, q_mode in 64bit mode. */
662 m_mode,
663 /* pair of v_mode operands */
664 a_mode,
665 cond_jump_mode,
666 loop_jcxz_mode,
667 movsxd_mode,
668 v_bnd_mode,
669 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
670 v_bndmk_mode,
671 /* operand size depends on REX.W / VEX.W. */
672 dq_mode,
673 /* Displacements like v_mode without considering Intel64 ISA. */
674 dqw_mode,
675 /* bounds operand */
676 bnd_mode,
677 /* bounds operand with operand swapped */
678 bnd_swap_mode,
679 /* 4- or 6-byte pointer operand */
680 f_mode,
681 const_1_mode,
682 /* v_mode for indirect branch opcodes. */
683 indir_v_mode,
684 /* v_mode for stack-related opcodes. */
685 stack_v_mode,
686 /* non-quad operand size depends on prefixes */
687 z_mode,
688 /* 16-byte operand */
689 o_mode,
690 /* registers like d_mode, memory like b_mode. */
691 db_mode,
692 /* registers like d_mode, memory like w_mode. */
693 dw_mode,
694
695 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
696 vex_vsib_d_w_dq_mode,
697 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
698 vex_vsib_q_w_dq_mode,
699 /* mandatory non-vector SIB. */
700 vex_sibmem_mode,
701
702 /* scalar, ignore vector length. */
703 scalar_mode,
704
705 /* Static rounding. */
706 evex_rounding_mode,
707 /* Static rounding, 64-bit mode only. */
708 evex_rounding_64_mode,
709 /* Supress all exceptions. */
710 evex_sae_mode,
711
712 /* Mask register operand. */
713 mask_mode,
714 /* Mask register operand. */
715 mask_bd_mode,
716
717 es_reg,
718 cs_reg,
719 ss_reg,
720 ds_reg,
721 fs_reg,
722 gs_reg,
723
724 eAX_reg,
725 eCX_reg,
726 eDX_reg,
727 eBX_reg,
728 eSP_reg,
729 eBP_reg,
730 eSI_reg,
731 eDI_reg,
732
733 al_reg,
734 cl_reg,
735 dl_reg,
736 bl_reg,
737 ah_reg,
738 ch_reg,
739 dh_reg,
740 bh_reg,
741
742 ax_reg,
743 cx_reg,
744 dx_reg,
745 bx_reg,
746 sp_reg,
747 bp_reg,
748 si_reg,
749 di_reg,
750
751 rAX_reg,
752 rCX_reg,
753 rDX_reg,
754 rBX_reg,
755 rSP_reg,
756 rBP_reg,
757 rSI_reg,
758 rDI_reg,
759
760 z_mode_ax_reg,
761 indir_dx_reg
762 };
763
764 enum
765 {
766 FLOATCODE = 1,
767 USE_REG_TABLE,
768 USE_MOD_TABLE,
769 USE_RM_TABLE,
770 USE_PREFIX_TABLE,
771 USE_X86_64_TABLE,
772 USE_3BYTE_TABLE,
773 USE_XOP_8F_TABLE,
774 USE_VEX_C4_TABLE,
775 USE_VEX_C5_TABLE,
776 USE_VEX_LEN_TABLE,
777 USE_VEX_W_TABLE,
778 USE_EVEX_TABLE,
779 USE_EVEX_LEN_TABLE
780 };
781
782 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
783
784 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
785 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
786 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
787 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
788 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
789 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
790 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
791 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
792 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
793 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
794 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
795 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
796 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
797 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
798 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
799 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
800
801 enum
802 {
803 REG_80 = 0,
804 REG_81,
805 REG_83,
806 REG_8F,
807 REG_C0,
808 REG_C1,
809 REG_C6,
810 REG_C7,
811 REG_D0,
812 REG_D1,
813 REG_D2,
814 REG_D3,
815 REG_F6,
816 REG_F7,
817 REG_FE,
818 REG_FF,
819 REG_0F00,
820 REG_0F01,
821 REG_0F0D,
822 REG_0F18,
823 REG_0F1C_P_0_MOD_0,
824 REG_0F1E_P_1_MOD_3,
825 REG_0F38D8_PREFIX_1,
826 REG_0F3A0F_PREFIX_1_MOD_3,
827 REG_0F71_MOD_0,
828 REG_0F72_MOD_0,
829 REG_0F73_MOD_0,
830 REG_0FA6,
831 REG_0FA7,
832 REG_0FAE,
833 REG_0FBA,
834 REG_0FC7,
835 REG_VEX_0F71_M_0,
836 REG_VEX_0F72_M_0,
837 REG_VEX_0F73_M_0,
838 REG_VEX_0FAE,
839 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
840 REG_VEX_0F38F3_L_0,
841
842 REG_XOP_09_01_L_0,
843 REG_XOP_09_02_L_0,
844 REG_XOP_09_12_M_1_L_0,
845 REG_XOP_0A_12_L_0,
846
847 REG_EVEX_0F71,
848 REG_EVEX_0F72,
849 REG_EVEX_0F73,
850 REG_EVEX_0F38C6_M_0_L_2,
851 REG_EVEX_0F38C7_M_0_L_2
852 };
853
854 enum
855 {
856 MOD_62_32BIT = 0,
857 MOD_8D,
858 MOD_C4_32BIT,
859 MOD_C5_32BIT,
860 MOD_C6_REG_7,
861 MOD_C7_REG_7,
862 MOD_FF_REG_3,
863 MOD_FF_REG_5,
864 MOD_0F01_REG_0,
865 MOD_0F01_REG_1,
866 MOD_0F01_REG_2,
867 MOD_0F01_REG_3,
868 MOD_0F01_REG_5,
869 MOD_0F01_REG_7,
870 MOD_0F02,
871 MOD_0F03,
872 MOD_0F12_PREFIX_0,
873 MOD_0F12_PREFIX_2,
874 MOD_0F13,
875 MOD_0F16_PREFIX_0,
876 MOD_0F16_PREFIX_2,
877 MOD_0F17,
878 MOD_0F18_REG_0,
879 MOD_0F18_REG_1,
880 MOD_0F18_REG_2,
881 MOD_0F18_REG_3,
882 MOD_0F18_REG_6,
883 MOD_0F18_REG_7,
884 MOD_0F1A_PREFIX_0,
885 MOD_0F1B_PREFIX_0,
886 MOD_0F1B_PREFIX_1,
887 MOD_0F1C_PREFIX_0,
888 MOD_0F1E_PREFIX_1,
889 MOD_0F2B_PREFIX_0,
890 MOD_0F2B_PREFIX_1,
891 MOD_0F2B_PREFIX_2,
892 MOD_0F2B_PREFIX_3,
893 MOD_0F50,
894 MOD_0F71,
895 MOD_0F72,
896 MOD_0F73,
897 MOD_0FAE_REG_0,
898 MOD_0FAE_REG_1,
899 MOD_0FAE_REG_2,
900 MOD_0FAE_REG_3,
901 MOD_0FAE_REG_4,
902 MOD_0FAE_REG_5,
903 MOD_0FAE_REG_6,
904 MOD_0FAE_REG_7,
905 MOD_0FB2,
906 MOD_0FB4,
907 MOD_0FB5,
908 MOD_0FC3,
909 MOD_0FC7_REG_3,
910 MOD_0FC7_REG_4,
911 MOD_0FC7_REG_5,
912 MOD_0FC7_REG_6,
913 MOD_0FC7_REG_7,
914 MOD_0FD7,
915 MOD_0FE7_PREFIX_2,
916 MOD_0FF0_PREFIX_3,
917 MOD_0F382A,
918 MOD_0F38DC_PREFIX_1,
919 MOD_0F38DD_PREFIX_1,
920 MOD_0F38DE_PREFIX_1,
921 MOD_0F38DF_PREFIX_1,
922 MOD_0F38F5,
923 MOD_0F38F6_PREFIX_0,
924 MOD_0F38F8_PREFIX_1,
925 MOD_0F38F8_PREFIX_2,
926 MOD_0F38F8_PREFIX_3,
927 MOD_0F38F9,
928 MOD_0F38FA_PREFIX_1,
929 MOD_0F38FB_PREFIX_1,
930 MOD_0F3A0F_PREFIX_1,
931
932 MOD_VEX_0F12_PREFIX_0,
933 MOD_VEX_0F12_PREFIX_2,
934 MOD_VEX_0F13,
935 MOD_VEX_0F16_PREFIX_0,
936 MOD_VEX_0F16_PREFIX_2,
937 MOD_VEX_0F17,
938 MOD_VEX_0F2B,
939 MOD_VEX_0F41_L_1,
940 MOD_VEX_0F42_L_1,
941 MOD_VEX_0F44_L_0,
942 MOD_VEX_0F45_L_1,
943 MOD_VEX_0F46_L_1,
944 MOD_VEX_0F47_L_1,
945 MOD_VEX_0F4A_L_1,
946 MOD_VEX_0F4B_L_1,
947 MOD_VEX_0F50,
948 MOD_VEX_0F71,
949 MOD_VEX_0F72,
950 MOD_VEX_0F73,
951 MOD_VEX_0F91_L_0,
952 MOD_VEX_0F92_L_0,
953 MOD_VEX_0F93_L_0,
954 MOD_VEX_0F98_L_0,
955 MOD_VEX_0F99_L_0,
956 MOD_VEX_0FAE_REG_2,
957 MOD_VEX_0FAE_REG_3,
958 MOD_VEX_0FD7,
959 MOD_VEX_0FE7,
960 MOD_VEX_0FF0_PREFIX_3,
961 MOD_VEX_0F381A,
962 MOD_VEX_0F382A,
963 MOD_VEX_0F382C,
964 MOD_VEX_0F382D,
965 MOD_VEX_0F382E,
966 MOD_VEX_0F382F,
967 MOD_VEX_0F3849_X86_64_L_0_W_0,
968 MOD_VEX_0F384B_X86_64_L_0_W_0,
969 MOD_VEX_0F385A,
970 MOD_VEX_0F385C_X86_64,
971 MOD_VEX_0F385E_X86_64,
972 MOD_VEX_0F386C_X86_64,
973 MOD_VEX_0F388C,
974 MOD_VEX_0F388E,
975 MOD_VEX_0F3A30_L_0,
976 MOD_VEX_0F3A31_L_0,
977 MOD_VEX_0F3A32_L_0,
978 MOD_VEX_0F3A33_L_0,
979
980 MOD_XOP_09_12,
981
982 MOD_EVEX_0F381A,
983 MOD_EVEX_0F381B,
984 MOD_EVEX_0F3828_P_1,
985 MOD_EVEX_0F382A_P_1_W_1,
986 MOD_EVEX_0F3838_P_1,
987 MOD_EVEX_0F383A_P_1_W_0,
988 MOD_EVEX_0F385A,
989 MOD_EVEX_0F385B,
990 MOD_EVEX_0F387A_W_0,
991 MOD_EVEX_0F387B_W_0,
992 MOD_EVEX_0F387C,
993 MOD_EVEX_0F38C6,
994 MOD_EVEX_0F38C7,
995 };
996
997 enum
998 {
999 RM_C6_REG_7 = 0,
1000 RM_C7_REG_7,
1001 RM_0F01_REG_0,
1002 RM_0F01_REG_1,
1003 RM_0F01_REG_2,
1004 RM_0F01_REG_3,
1005 RM_0F01_REG_5_MOD_3,
1006 RM_0F01_REG_7_MOD_3,
1007 RM_0F1E_P_1_MOD_3_REG_7,
1008 RM_0FAE_REG_6_MOD_3_P_0,
1009 RM_0FAE_REG_7_MOD_3,
1010 RM_0F3A0F_P_1_MOD_3_REG_0,
1011
1012 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
1013 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
1014 };
1015
1016 enum
1017 {
1018 PREFIX_90 = 0,
1019 PREFIX_0F00_REG_6_X86_64,
1020 PREFIX_0F01_REG_0_MOD_3_RM_6,
1021 PREFIX_0F01_REG_1_RM_2,
1022 PREFIX_0F01_REG_1_RM_4,
1023 PREFIX_0F01_REG_1_RM_5,
1024 PREFIX_0F01_REG_1_RM_6,
1025 PREFIX_0F01_REG_1_RM_7,
1026 PREFIX_0F01_REG_3_RM_1,
1027 PREFIX_0F01_REG_5_MOD_0,
1028 PREFIX_0F01_REG_5_MOD_3_RM_0,
1029 PREFIX_0F01_REG_5_MOD_3_RM_1,
1030 PREFIX_0F01_REG_5_MOD_3_RM_2,
1031 PREFIX_0F01_REG_5_MOD_3_RM_4,
1032 PREFIX_0F01_REG_5_MOD_3_RM_5,
1033 PREFIX_0F01_REG_5_MOD_3_RM_6,
1034 PREFIX_0F01_REG_5_MOD_3_RM_7,
1035 PREFIX_0F01_REG_7_MOD_3_RM_2,
1036 PREFIX_0F01_REG_7_MOD_3_RM_5,
1037 PREFIX_0F01_REG_7_MOD_3_RM_6,
1038 PREFIX_0F01_REG_7_MOD_3_RM_7,
1039 PREFIX_0F09,
1040 PREFIX_0F10,
1041 PREFIX_0F11,
1042 PREFIX_0F12,
1043 PREFIX_0F16,
1044 PREFIX_0F18_REG_6_MOD_0_X86_64,
1045 PREFIX_0F18_REG_7_MOD_0_X86_64,
1046 PREFIX_0F1A,
1047 PREFIX_0F1B,
1048 PREFIX_0F1C,
1049 PREFIX_0F1E,
1050 PREFIX_0F2A,
1051 PREFIX_0F2B,
1052 PREFIX_0F2C,
1053 PREFIX_0F2D,
1054 PREFIX_0F2E,
1055 PREFIX_0F2F,
1056 PREFIX_0F51,
1057 PREFIX_0F52,
1058 PREFIX_0F53,
1059 PREFIX_0F58,
1060 PREFIX_0F59,
1061 PREFIX_0F5A,
1062 PREFIX_0F5B,
1063 PREFIX_0F5C,
1064 PREFIX_0F5D,
1065 PREFIX_0F5E,
1066 PREFIX_0F5F,
1067 PREFIX_0F60,
1068 PREFIX_0F61,
1069 PREFIX_0F62,
1070 PREFIX_0F6F,
1071 PREFIX_0F70,
1072 PREFIX_0F78,
1073 PREFIX_0F79,
1074 PREFIX_0F7C,
1075 PREFIX_0F7D,
1076 PREFIX_0F7E,
1077 PREFIX_0F7F,
1078 PREFIX_0FAE_REG_0_MOD_3,
1079 PREFIX_0FAE_REG_1_MOD_3,
1080 PREFIX_0FAE_REG_2_MOD_3,
1081 PREFIX_0FAE_REG_3_MOD_3,
1082 PREFIX_0FAE_REG_4_MOD_0,
1083 PREFIX_0FAE_REG_4_MOD_3,
1084 PREFIX_0FAE_REG_5_MOD_3,
1085 PREFIX_0FAE_REG_6_MOD_0,
1086 PREFIX_0FAE_REG_6_MOD_3,
1087 PREFIX_0FAE_REG_7_MOD_0,
1088 PREFIX_0FB8,
1089 PREFIX_0FBC,
1090 PREFIX_0FBD,
1091 PREFIX_0FC2,
1092 PREFIX_0FC7_REG_6_MOD_0,
1093 PREFIX_0FC7_REG_6_MOD_3,
1094 PREFIX_0FC7_REG_7_MOD_3,
1095 PREFIX_0FD0,
1096 PREFIX_0FD6,
1097 PREFIX_0FE6,
1098 PREFIX_0FE7,
1099 PREFIX_0FF0,
1100 PREFIX_0FF7,
1101 PREFIX_0F38D8,
1102 PREFIX_0F38DC,
1103 PREFIX_0F38DD,
1104 PREFIX_0F38DE,
1105 PREFIX_0F38DF,
1106 PREFIX_0F38F0,
1107 PREFIX_0F38F1,
1108 PREFIX_0F38F6,
1109 PREFIX_0F38F8,
1110 PREFIX_0F38FA,
1111 PREFIX_0F38FB,
1112 PREFIX_0F38FC,
1113 PREFIX_0F3A0F,
1114 PREFIX_VEX_0F10,
1115 PREFIX_VEX_0F11,
1116 PREFIX_VEX_0F12,
1117 PREFIX_VEX_0F16,
1118 PREFIX_VEX_0F2A,
1119 PREFIX_VEX_0F2C,
1120 PREFIX_VEX_0F2D,
1121 PREFIX_VEX_0F2E,
1122 PREFIX_VEX_0F2F,
1123 PREFIX_VEX_0F41_L_1_M_1_W_0,
1124 PREFIX_VEX_0F41_L_1_M_1_W_1,
1125 PREFIX_VEX_0F42_L_1_M_1_W_0,
1126 PREFIX_VEX_0F42_L_1_M_1_W_1,
1127 PREFIX_VEX_0F44_L_0_M_1_W_0,
1128 PREFIX_VEX_0F44_L_0_M_1_W_1,
1129 PREFIX_VEX_0F45_L_1_M_1_W_0,
1130 PREFIX_VEX_0F45_L_1_M_1_W_1,
1131 PREFIX_VEX_0F46_L_1_M_1_W_0,
1132 PREFIX_VEX_0F46_L_1_M_1_W_1,
1133 PREFIX_VEX_0F47_L_1_M_1_W_0,
1134 PREFIX_VEX_0F47_L_1_M_1_W_1,
1135 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1136 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1137 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1138 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1139 PREFIX_VEX_0F51,
1140 PREFIX_VEX_0F52,
1141 PREFIX_VEX_0F53,
1142 PREFIX_VEX_0F58,
1143 PREFIX_VEX_0F59,
1144 PREFIX_VEX_0F5A,
1145 PREFIX_VEX_0F5B,
1146 PREFIX_VEX_0F5C,
1147 PREFIX_VEX_0F5D,
1148 PREFIX_VEX_0F5E,
1149 PREFIX_VEX_0F5F,
1150 PREFIX_VEX_0F6F,
1151 PREFIX_VEX_0F70,
1152 PREFIX_VEX_0F7C,
1153 PREFIX_VEX_0F7D,
1154 PREFIX_VEX_0F7E,
1155 PREFIX_VEX_0F7F,
1156 PREFIX_VEX_0F90_L_0_W_0,
1157 PREFIX_VEX_0F90_L_0_W_1,
1158 PREFIX_VEX_0F91_L_0_M_0_W_0,
1159 PREFIX_VEX_0F91_L_0_M_0_W_1,
1160 PREFIX_VEX_0F92_L_0_M_1_W_0,
1161 PREFIX_VEX_0F92_L_0_M_1_W_1,
1162 PREFIX_VEX_0F93_L_0_M_1_W_0,
1163 PREFIX_VEX_0F93_L_0_M_1_W_1,
1164 PREFIX_VEX_0F98_L_0_M_1_W_0,
1165 PREFIX_VEX_0F98_L_0_M_1_W_1,
1166 PREFIX_VEX_0F99_L_0_M_1_W_0,
1167 PREFIX_VEX_0F99_L_0_M_1_W_1,
1168 PREFIX_VEX_0FC2,
1169 PREFIX_VEX_0FD0,
1170 PREFIX_VEX_0FE6,
1171 PREFIX_VEX_0FF0,
1172 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1173 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1174 PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0,
1175 PREFIX_VEX_0F3850_W_0,
1176 PREFIX_VEX_0F3851_W_0,
1177 PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0,
1178 PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0,
1179 PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0,
1180 PREFIX_VEX_0F3872,
1181 PREFIX_VEX_0F38B0_W_0,
1182 PREFIX_VEX_0F38B1_W_0,
1183 PREFIX_VEX_0F38F5_L_0,
1184 PREFIX_VEX_0F38F6_L_0,
1185 PREFIX_VEX_0F38F7_L_0,
1186 PREFIX_VEX_0F3AF0_L_0,
1187
1188 PREFIX_EVEX_0F5B,
1189 PREFIX_EVEX_0F6F,
1190 PREFIX_EVEX_0F70,
1191 PREFIX_EVEX_0F78,
1192 PREFIX_EVEX_0F79,
1193 PREFIX_EVEX_0F7A,
1194 PREFIX_EVEX_0F7B,
1195 PREFIX_EVEX_0F7E,
1196 PREFIX_EVEX_0F7F,
1197 PREFIX_EVEX_0FC2,
1198 PREFIX_EVEX_0FE6,
1199 PREFIX_EVEX_0F3810,
1200 PREFIX_EVEX_0F3811,
1201 PREFIX_EVEX_0F3812,
1202 PREFIX_EVEX_0F3813,
1203 PREFIX_EVEX_0F3814,
1204 PREFIX_EVEX_0F3815,
1205 PREFIX_EVEX_0F3820,
1206 PREFIX_EVEX_0F3821,
1207 PREFIX_EVEX_0F3822,
1208 PREFIX_EVEX_0F3823,
1209 PREFIX_EVEX_0F3824,
1210 PREFIX_EVEX_0F3825,
1211 PREFIX_EVEX_0F3826,
1212 PREFIX_EVEX_0F3827,
1213 PREFIX_EVEX_0F3828,
1214 PREFIX_EVEX_0F3829,
1215 PREFIX_EVEX_0F382A,
1216 PREFIX_EVEX_0F3830,
1217 PREFIX_EVEX_0F3831,
1218 PREFIX_EVEX_0F3832,
1219 PREFIX_EVEX_0F3833,
1220 PREFIX_EVEX_0F3834,
1221 PREFIX_EVEX_0F3835,
1222 PREFIX_EVEX_0F3838,
1223 PREFIX_EVEX_0F3839,
1224 PREFIX_EVEX_0F383A,
1225 PREFIX_EVEX_0F3852,
1226 PREFIX_EVEX_0F3853,
1227 PREFIX_EVEX_0F3868,
1228 PREFIX_EVEX_0F3872,
1229 PREFIX_EVEX_0F389A,
1230 PREFIX_EVEX_0F389B,
1231 PREFIX_EVEX_0F38AA,
1232 PREFIX_EVEX_0F38AB,
1233
1234 PREFIX_EVEX_0F3A08,
1235 PREFIX_EVEX_0F3A0A,
1236 PREFIX_EVEX_0F3A26,
1237 PREFIX_EVEX_0F3A27,
1238 PREFIX_EVEX_0F3A56,
1239 PREFIX_EVEX_0F3A57,
1240 PREFIX_EVEX_0F3A66,
1241 PREFIX_EVEX_0F3A67,
1242 PREFIX_EVEX_0F3AC2,
1243
1244 PREFIX_EVEX_MAP5_10,
1245 PREFIX_EVEX_MAP5_11,
1246 PREFIX_EVEX_MAP5_1D,
1247 PREFIX_EVEX_MAP5_2A,
1248 PREFIX_EVEX_MAP5_2C,
1249 PREFIX_EVEX_MAP5_2D,
1250 PREFIX_EVEX_MAP5_2E,
1251 PREFIX_EVEX_MAP5_2F,
1252 PREFIX_EVEX_MAP5_51,
1253 PREFIX_EVEX_MAP5_58,
1254 PREFIX_EVEX_MAP5_59,
1255 PREFIX_EVEX_MAP5_5A,
1256 PREFIX_EVEX_MAP5_5B,
1257 PREFIX_EVEX_MAP5_5C,
1258 PREFIX_EVEX_MAP5_5D,
1259 PREFIX_EVEX_MAP5_5E,
1260 PREFIX_EVEX_MAP5_5F,
1261 PREFIX_EVEX_MAP5_78,
1262 PREFIX_EVEX_MAP5_79,
1263 PREFIX_EVEX_MAP5_7A,
1264 PREFIX_EVEX_MAP5_7B,
1265 PREFIX_EVEX_MAP5_7C,
1266 PREFIX_EVEX_MAP5_7D,
1267
1268 PREFIX_EVEX_MAP6_13,
1269 PREFIX_EVEX_MAP6_56,
1270 PREFIX_EVEX_MAP6_57,
1271 PREFIX_EVEX_MAP6_D6,
1272 PREFIX_EVEX_MAP6_D7,
1273 };
1274
1275 enum
1276 {
1277 X86_64_06 = 0,
1278 X86_64_07,
1279 X86_64_0E,
1280 X86_64_16,
1281 X86_64_17,
1282 X86_64_1E,
1283 X86_64_1F,
1284 X86_64_27,
1285 X86_64_2F,
1286 X86_64_37,
1287 X86_64_3F,
1288 X86_64_60,
1289 X86_64_61,
1290 X86_64_62,
1291 X86_64_63,
1292 X86_64_6D,
1293 X86_64_6F,
1294 X86_64_82,
1295 X86_64_9A,
1296 X86_64_C2,
1297 X86_64_C3,
1298 X86_64_C4,
1299 X86_64_C5,
1300 X86_64_CE,
1301 X86_64_D4,
1302 X86_64_D5,
1303 X86_64_E8,
1304 X86_64_E9,
1305 X86_64_EA,
1306 X86_64_0F00_REG_6,
1307 X86_64_0F01_REG_0,
1308 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1309 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1310 X86_64_0F01_REG_1,
1311 X86_64_0F01_REG_1_RM_2_PREFIX_1,
1312 X86_64_0F01_REG_1_RM_2_PREFIX_3,
1313 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1314 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1315 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1316 X86_64_0F01_REG_2,
1317 X86_64_0F01_REG_3,
1318 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1319 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1320 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1321 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1322 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1323 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1324 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1325 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1326 X86_64_0F18_REG_6_MOD_0,
1327 X86_64_0F18_REG_7_MOD_0,
1328 X86_64_0F24,
1329 X86_64_0F26,
1330 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1331
1332 X86_64_VEX_0F3849,
1333 X86_64_VEX_0F384B,
1334 X86_64_VEX_0F385C,
1335 X86_64_VEX_0F385E,
1336 X86_64_VEX_0F386C,
1337 X86_64_VEX_0F38E0,
1338 X86_64_VEX_0F38E1,
1339 X86_64_VEX_0F38E2,
1340 X86_64_VEX_0F38E3,
1341 X86_64_VEX_0F38E4,
1342 X86_64_VEX_0F38E5,
1343 X86_64_VEX_0F38E6,
1344 X86_64_VEX_0F38E7,
1345 X86_64_VEX_0F38E8,
1346 X86_64_VEX_0F38E9,
1347 X86_64_VEX_0F38EA,
1348 X86_64_VEX_0F38EB,
1349 X86_64_VEX_0F38EC,
1350 X86_64_VEX_0F38ED,
1351 X86_64_VEX_0F38EE,
1352 X86_64_VEX_0F38EF,
1353 };
1354
1355 enum
1356 {
1357 THREE_BYTE_0F38 = 0,
1358 THREE_BYTE_0F3A
1359 };
1360
1361 enum
1362 {
1363 XOP_08 = 0,
1364 XOP_09,
1365 XOP_0A
1366 };
1367
1368 enum
1369 {
1370 VEX_0F = 0,
1371 VEX_0F38,
1372 VEX_0F3A
1373 };
1374
1375 enum
1376 {
1377 EVEX_0F = 0,
1378 EVEX_0F38,
1379 EVEX_0F3A,
1380 EVEX_MAP5,
1381 EVEX_MAP6,
1382 };
1383
1384 enum
1385 {
1386 VEX_LEN_0F12_P_0_M_0 = 0,
1387 VEX_LEN_0F12_P_0_M_1,
1388 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1389 VEX_LEN_0F13_M_0,
1390 VEX_LEN_0F16_P_0_M_0,
1391 VEX_LEN_0F16_P_0_M_1,
1392 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1393 VEX_LEN_0F17_M_0,
1394 VEX_LEN_0F41,
1395 VEX_LEN_0F42,
1396 VEX_LEN_0F44,
1397 VEX_LEN_0F45,
1398 VEX_LEN_0F46,
1399 VEX_LEN_0F47,
1400 VEX_LEN_0F4A,
1401 VEX_LEN_0F4B,
1402 VEX_LEN_0F6E,
1403 VEX_LEN_0F77,
1404 VEX_LEN_0F7E_P_1,
1405 VEX_LEN_0F7E_P_2,
1406 VEX_LEN_0F90,
1407 VEX_LEN_0F91,
1408 VEX_LEN_0F92,
1409 VEX_LEN_0F93,
1410 VEX_LEN_0F98,
1411 VEX_LEN_0F99,
1412 VEX_LEN_0FAE_R_2_M_0,
1413 VEX_LEN_0FAE_R_3_M_0,
1414 VEX_LEN_0FC4,
1415 VEX_LEN_0FC5,
1416 VEX_LEN_0FD6,
1417 VEX_LEN_0FF7,
1418 VEX_LEN_0F3816,
1419 VEX_LEN_0F3819,
1420 VEX_LEN_0F381A_M_0,
1421 VEX_LEN_0F3836,
1422 VEX_LEN_0F3841,
1423 VEX_LEN_0F3849_X86_64,
1424 VEX_LEN_0F384B_X86_64,
1425 VEX_LEN_0F385A_M_0,
1426 VEX_LEN_0F385C_X86_64_M_1,
1427 VEX_LEN_0F385E_X86_64_M_1,
1428 VEX_LEN_0F386C_X86_64_M_1,
1429 VEX_LEN_0F38DB,
1430 VEX_LEN_0F38F2,
1431 VEX_LEN_0F38F3,
1432 VEX_LEN_0F38F5,
1433 VEX_LEN_0F38F6,
1434 VEX_LEN_0F38F7,
1435 VEX_LEN_0F3A00,
1436 VEX_LEN_0F3A01,
1437 VEX_LEN_0F3A06,
1438 VEX_LEN_0F3A14,
1439 VEX_LEN_0F3A15,
1440 VEX_LEN_0F3A16,
1441 VEX_LEN_0F3A17,
1442 VEX_LEN_0F3A18,
1443 VEX_LEN_0F3A19,
1444 VEX_LEN_0F3A20,
1445 VEX_LEN_0F3A21,
1446 VEX_LEN_0F3A22,
1447 VEX_LEN_0F3A30,
1448 VEX_LEN_0F3A31,
1449 VEX_LEN_0F3A32,
1450 VEX_LEN_0F3A33,
1451 VEX_LEN_0F3A38,
1452 VEX_LEN_0F3A39,
1453 VEX_LEN_0F3A41,
1454 VEX_LEN_0F3A46,
1455 VEX_LEN_0F3A60,
1456 VEX_LEN_0F3A61,
1457 VEX_LEN_0F3A62,
1458 VEX_LEN_0F3A63,
1459 VEX_LEN_0F3ADF,
1460 VEX_LEN_0F3AF0,
1461 VEX_LEN_0FXOP_08_85,
1462 VEX_LEN_0FXOP_08_86,
1463 VEX_LEN_0FXOP_08_87,
1464 VEX_LEN_0FXOP_08_8E,
1465 VEX_LEN_0FXOP_08_8F,
1466 VEX_LEN_0FXOP_08_95,
1467 VEX_LEN_0FXOP_08_96,
1468 VEX_LEN_0FXOP_08_97,
1469 VEX_LEN_0FXOP_08_9E,
1470 VEX_LEN_0FXOP_08_9F,
1471 VEX_LEN_0FXOP_08_A3,
1472 VEX_LEN_0FXOP_08_A6,
1473 VEX_LEN_0FXOP_08_B6,
1474 VEX_LEN_0FXOP_08_C0,
1475 VEX_LEN_0FXOP_08_C1,
1476 VEX_LEN_0FXOP_08_C2,
1477 VEX_LEN_0FXOP_08_C3,
1478 VEX_LEN_0FXOP_08_CC,
1479 VEX_LEN_0FXOP_08_CD,
1480 VEX_LEN_0FXOP_08_CE,
1481 VEX_LEN_0FXOP_08_CF,
1482 VEX_LEN_0FXOP_08_EC,
1483 VEX_LEN_0FXOP_08_ED,
1484 VEX_LEN_0FXOP_08_EE,
1485 VEX_LEN_0FXOP_08_EF,
1486 VEX_LEN_0FXOP_09_01,
1487 VEX_LEN_0FXOP_09_02,
1488 VEX_LEN_0FXOP_09_12_M_1,
1489 VEX_LEN_0FXOP_09_82_W_0,
1490 VEX_LEN_0FXOP_09_83_W_0,
1491 VEX_LEN_0FXOP_09_90,
1492 VEX_LEN_0FXOP_09_91,
1493 VEX_LEN_0FXOP_09_92,
1494 VEX_LEN_0FXOP_09_93,
1495 VEX_LEN_0FXOP_09_94,
1496 VEX_LEN_0FXOP_09_95,
1497 VEX_LEN_0FXOP_09_96,
1498 VEX_LEN_0FXOP_09_97,
1499 VEX_LEN_0FXOP_09_98,
1500 VEX_LEN_0FXOP_09_99,
1501 VEX_LEN_0FXOP_09_9A,
1502 VEX_LEN_0FXOP_09_9B,
1503 VEX_LEN_0FXOP_09_C1,
1504 VEX_LEN_0FXOP_09_C2,
1505 VEX_LEN_0FXOP_09_C3,
1506 VEX_LEN_0FXOP_09_C6,
1507 VEX_LEN_0FXOP_09_C7,
1508 VEX_LEN_0FXOP_09_CB,
1509 VEX_LEN_0FXOP_09_D1,
1510 VEX_LEN_0FXOP_09_D2,
1511 VEX_LEN_0FXOP_09_D3,
1512 VEX_LEN_0FXOP_09_D6,
1513 VEX_LEN_0FXOP_09_D7,
1514 VEX_LEN_0FXOP_09_DB,
1515 VEX_LEN_0FXOP_09_E1,
1516 VEX_LEN_0FXOP_09_E2,
1517 VEX_LEN_0FXOP_09_E3,
1518 VEX_LEN_0FXOP_0A_12,
1519 };
1520
1521 enum
1522 {
1523 EVEX_LEN_0F3816 = 0,
1524 EVEX_LEN_0F3819,
1525 EVEX_LEN_0F381A_M_0,
1526 EVEX_LEN_0F381B_M_0,
1527 EVEX_LEN_0F3836,
1528 EVEX_LEN_0F385A_M_0,
1529 EVEX_LEN_0F385B_M_0,
1530 EVEX_LEN_0F38C6_M_0,
1531 EVEX_LEN_0F38C7_M_0,
1532 EVEX_LEN_0F3A00,
1533 EVEX_LEN_0F3A01,
1534 EVEX_LEN_0F3A18,
1535 EVEX_LEN_0F3A19,
1536 EVEX_LEN_0F3A1A,
1537 EVEX_LEN_0F3A1B,
1538 EVEX_LEN_0F3A23,
1539 EVEX_LEN_0F3A38,
1540 EVEX_LEN_0F3A39,
1541 EVEX_LEN_0F3A3A,
1542 EVEX_LEN_0F3A3B,
1543 EVEX_LEN_0F3A43
1544 };
1545
1546 enum
1547 {
1548 VEX_W_0F41_L_1_M_1 = 0,
1549 VEX_W_0F42_L_1_M_1,
1550 VEX_W_0F44_L_0_M_1,
1551 VEX_W_0F45_L_1_M_1,
1552 VEX_W_0F46_L_1_M_1,
1553 VEX_W_0F47_L_1_M_1,
1554 VEX_W_0F4A_L_1_M_1,
1555 VEX_W_0F4B_L_1_M_1,
1556 VEX_W_0F90_L_0,
1557 VEX_W_0F91_L_0_M_0,
1558 VEX_W_0F92_L_0_M_1,
1559 VEX_W_0F93_L_0_M_1,
1560 VEX_W_0F98_L_0_M_1,
1561 VEX_W_0F99_L_0_M_1,
1562 VEX_W_0F380C,
1563 VEX_W_0F380D,
1564 VEX_W_0F380E,
1565 VEX_W_0F380F,
1566 VEX_W_0F3813,
1567 VEX_W_0F3816_L_1,
1568 VEX_W_0F3818,
1569 VEX_W_0F3819_L_1,
1570 VEX_W_0F381A_M_0_L_1,
1571 VEX_W_0F382C_M_0,
1572 VEX_W_0F382D_M_0,
1573 VEX_W_0F382E_M_0,
1574 VEX_W_0F382F_M_0,
1575 VEX_W_0F3836,
1576 VEX_W_0F3846,
1577 VEX_W_0F3849_X86_64_L_0,
1578 VEX_W_0F384B_X86_64_L_0,
1579 VEX_W_0F3850,
1580 VEX_W_0F3851,
1581 VEX_W_0F3852,
1582 VEX_W_0F3853,
1583 VEX_W_0F3858,
1584 VEX_W_0F3859,
1585 VEX_W_0F385A_M_0_L_0,
1586 VEX_W_0F385C_X86_64_M_1_L_0,
1587 VEX_W_0F385E_X86_64_M_1_L_0,
1588 VEX_W_0F386C_X86_64_M_1_L_0,
1589 VEX_W_0F3872_P_1,
1590 VEX_W_0F3878,
1591 VEX_W_0F3879,
1592 VEX_W_0F38B0,
1593 VEX_W_0F38B1,
1594 VEX_W_0F38B4,
1595 VEX_W_0F38B5,
1596 VEX_W_0F38CF,
1597 VEX_W_0F3A00_L_1,
1598 VEX_W_0F3A01_L_1,
1599 VEX_W_0F3A02,
1600 VEX_W_0F3A04,
1601 VEX_W_0F3A05,
1602 VEX_W_0F3A06_L_1,
1603 VEX_W_0F3A18_L_1,
1604 VEX_W_0F3A19_L_1,
1605 VEX_W_0F3A1D,
1606 VEX_W_0F3A38_L_1,
1607 VEX_W_0F3A39_L_1,
1608 VEX_W_0F3A46_L_1,
1609 VEX_W_0F3A4A,
1610 VEX_W_0F3A4B,
1611 VEX_W_0F3A4C,
1612 VEX_W_0F3ACE,
1613 VEX_W_0F3ACF,
1614
1615 VEX_W_0FXOP_08_85_L_0,
1616 VEX_W_0FXOP_08_86_L_0,
1617 VEX_W_0FXOP_08_87_L_0,
1618 VEX_W_0FXOP_08_8E_L_0,
1619 VEX_W_0FXOP_08_8F_L_0,
1620 VEX_W_0FXOP_08_95_L_0,
1621 VEX_W_0FXOP_08_96_L_0,
1622 VEX_W_0FXOP_08_97_L_0,
1623 VEX_W_0FXOP_08_9E_L_0,
1624 VEX_W_0FXOP_08_9F_L_0,
1625 VEX_W_0FXOP_08_A6_L_0,
1626 VEX_W_0FXOP_08_B6_L_0,
1627 VEX_W_0FXOP_08_C0_L_0,
1628 VEX_W_0FXOP_08_C1_L_0,
1629 VEX_W_0FXOP_08_C2_L_0,
1630 VEX_W_0FXOP_08_C3_L_0,
1631 VEX_W_0FXOP_08_CC_L_0,
1632 VEX_W_0FXOP_08_CD_L_0,
1633 VEX_W_0FXOP_08_CE_L_0,
1634 VEX_W_0FXOP_08_CF_L_0,
1635 VEX_W_0FXOP_08_EC_L_0,
1636 VEX_W_0FXOP_08_ED_L_0,
1637 VEX_W_0FXOP_08_EE_L_0,
1638 VEX_W_0FXOP_08_EF_L_0,
1639
1640 VEX_W_0FXOP_09_80,
1641 VEX_W_0FXOP_09_81,
1642 VEX_W_0FXOP_09_82,
1643 VEX_W_0FXOP_09_83,
1644 VEX_W_0FXOP_09_C1_L_0,
1645 VEX_W_0FXOP_09_C2_L_0,
1646 VEX_W_0FXOP_09_C3_L_0,
1647 VEX_W_0FXOP_09_C6_L_0,
1648 VEX_W_0FXOP_09_C7_L_0,
1649 VEX_W_0FXOP_09_CB_L_0,
1650 VEX_W_0FXOP_09_D1_L_0,
1651 VEX_W_0FXOP_09_D2_L_0,
1652 VEX_W_0FXOP_09_D3_L_0,
1653 VEX_W_0FXOP_09_D6_L_0,
1654 VEX_W_0FXOP_09_D7_L_0,
1655 VEX_W_0FXOP_09_DB_L_0,
1656 VEX_W_0FXOP_09_E1_L_0,
1657 VEX_W_0FXOP_09_E2_L_0,
1658 VEX_W_0FXOP_09_E3_L_0,
1659
1660 EVEX_W_0F5B_P_0,
1661 EVEX_W_0F62,
1662 EVEX_W_0F66,
1663 EVEX_W_0F6A,
1664 EVEX_W_0F6B,
1665 EVEX_W_0F6C,
1666 EVEX_W_0F6D,
1667 EVEX_W_0F6F_P_1,
1668 EVEX_W_0F6F_P_2,
1669 EVEX_W_0F6F_P_3,
1670 EVEX_W_0F70_P_2,
1671 EVEX_W_0F72_R_2,
1672 EVEX_W_0F72_R_6,
1673 EVEX_W_0F73_R_2,
1674 EVEX_W_0F73_R_6,
1675 EVEX_W_0F76,
1676 EVEX_W_0F78_P_0,
1677 EVEX_W_0F78_P_2,
1678 EVEX_W_0F79_P_0,
1679 EVEX_W_0F79_P_2,
1680 EVEX_W_0F7A_P_1,
1681 EVEX_W_0F7A_P_2,
1682 EVEX_W_0F7A_P_3,
1683 EVEX_W_0F7B_P_2,
1684 EVEX_W_0F7E_P_1,
1685 EVEX_W_0F7F_P_1,
1686 EVEX_W_0F7F_P_2,
1687 EVEX_W_0F7F_P_3,
1688 EVEX_W_0FD2,
1689 EVEX_W_0FD3,
1690 EVEX_W_0FD4,
1691 EVEX_W_0FD6,
1692 EVEX_W_0FE6_P_1,
1693 EVEX_W_0FE7,
1694 EVEX_W_0FF2,
1695 EVEX_W_0FF3,
1696 EVEX_W_0FF4,
1697 EVEX_W_0FFA,
1698 EVEX_W_0FFB,
1699 EVEX_W_0FFE,
1700
1701 EVEX_W_0F3810_P_1,
1702 EVEX_W_0F3810_P_2,
1703 EVEX_W_0F3811_P_1,
1704 EVEX_W_0F3811_P_2,
1705 EVEX_W_0F3812_P_1,
1706 EVEX_W_0F3812_P_2,
1707 EVEX_W_0F3813_P_1,
1708 EVEX_W_0F3814_P_1,
1709 EVEX_W_0F3815_P_1,
1710 EVEX_W_0F3819_L_n,
1711 EVEX_W_0F381A_M_0_L_n,
1712 EVEX_W_0F381B_M_0_L_2,
1713 EVEX_W_0F381E,
1714 EVEX_W_0F381F,
1715 EVEX_W_0F3820_P_1,
1716 EVEX_W_0F3821_P_1,
1717 EVEX_W_0F3822_P_1,
1718 EVEX_W_0F3823_P_1,
1719 EVEX_W_0F3824_P_1,
1720 EVEX_W_0F3825_P_1,
1721 EVEX_W_0F3825_P_2,
1722 EVEX_W_0F3828_P_2,
1723 EVEX_W_0F3829_P_2,
1724 EVEX_W_0F382A_P_1,
1725 EVEX_W_0F382A_P_2,
1726 EVEX_W_0F382B,
1727 EVEX_W_0F3830_P_1,
1728 EVEX_W_0F3831_P_1,
1729 EVEX_W_0F3832_P_1,
1730 EVEX_W_0F3833_P_1,
1731 EVEX_W_0F3834_P_1,
1732 EVEX_W_0F3835_P_1,
1733 EVEX_W_0F3835_P_2,
1734 EVEX_W_0F3837,
1735 EVEX_W_0F383A_P_1,
1736 EVEX_W_0F3859,
1737 EVEX_W_0F385A_M_0_L_n,
1738 EVEX_W_0F385B_M_0_L_2,
1739 EVEX_W_0F3870,
1740 EVEX_W_0F3872_P_2,
1741 EVEX_W_0F387A,
1742 EVEX_W_0F387B,
1743 EVEX_W_0F3883,
1744
1745 EVEX_W_0F3A18_L_n,
1746 EVEX_W_0F3A19_L_n,
1747 EVEX_W_0F3A1A_L_2,
1748 EVEX_W_0F3A1B_L_2,
1749 EVEX_W_0F3A21,
1750 EVEX_W_0F3A23_L_n,
1751 EVEX_W_0F3A38_L_n,
1752 EVEX_W_0F3A39_L_n,
1753 EVEX_W_0F3A3A_L_2,
1754 EVEX_W_0F3A3B_L_2,
1755 EVEX_W_0F3A42,
1756 EVEX_W_0F3A43_L_n,
1757 EVEX_W_0F3A70,
1758 EVEX_W_0F3A72,
1759
1760 EVEX_W_MAP5_5B_P_0,
1761 EVEX_W_MAP5_7A_P_3,
1762 };
1763
1764 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1765
1766 struct dis386 {
1767 const char *name;
1768 struct
1769 {
1770 op_rtn rtn;
1771 int bytemode;
1772 } op[MAX_OPERANDS];
1773 unsigned int prefix_requirement;
1774 };
1775
1776 /* Upper case letters in the instruction names here are macros.
1777 'A' => print 'b' if no register operands or suffix_always is true
1778 'B' => print 'b' if suffix_always is true
1779 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1780 size prefix
1781 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1782 suffix_always is true
1783 'E' => print 'e' if 32-bit form of jcxz
1784 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1785 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1786 'H' => print ",pt" or ",pn" branch hint
1787 'I' unused.
1788 'J' unused.
1789 'K' => print 'd' or 'q' if rex prefix is present.
1790 'L' unused.
1791 'M' => print 'r' if intel_mnemonic is false.
1792 'N' => print 'n' if instruction has no wait "prefix"
1793 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1794 'P' => behave as 'T' except with register operand outside of suffix_always
1795 mode
1796 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1797 is true
1798 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1799 'S' => print 'w', 'l' or 'q' if suffix_always is true
1800 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1801 prefix or if suffix_always is true.
1802 'U' unused.
1803 'V' unused.
1804 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1805 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1806 'Y' unused.
1807 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1808 '!' => change condition from true to false or from false to true.
1809 '%' => add 1 upper case letter to the macro.
1810 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1811 prefix or suffix_always is true (lcall/ljmp).
1812 '@' => in 64bit mode for Intel64 ISA or if instruction
1813 has no operand sizing prefix, print 'q' if suffix_always is true or
1814 nothing otherwise; behave as 'P' in all other cases
1815
1816 2 upper case letter macros:
1817 "XY" => print 'x' or 'y' if suffix_always is true or no register
1818 operands and no broadcast.
1819 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1820 register operands and no broadcast.
1821 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1822 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1823 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1824 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1825 "XV" => print "{vex} " pseudo prefix
1826 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1827 is used by an EVEX-encoded (AVX512VL) instruction.
1828 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1829 being false, or no operand at all in 64bit mode, or if suffix_always
1830 is true.
1831 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1832 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1833 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1834 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1835 "BW" => print 'b' or 'w' depending on the VEX.W bit
1836 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1837 an operand size prefix, or suffix_always is true. print
1838 'q' if rex prefix is present.
1839
1840 Many of the above letters print nothing in Intel mode. See "putop"
1841 for the details.
1842
1843 Braces '{' and '}', and vertical bars '|', indicate alternative
1844 mnemonic strings for AT&T and Intel. */
1845
1846 static const struct dis386 dis386[] = {
1847 /* 00 */
1848 { "addB", { Ebh1, Gb }, 0 },
1849 { "addS", { Evh1, Gv }, 0 },
1850 { "addB", { Gb, EbS }, 0 },
1851 { "addS", { Gv, EvS }, 0 },
1852 { "addB", { AL, Ib }, 0 },
1853 { "addS", { eAX, Iv }, 0 },
1854 { X86_64_TABLE (X86_64_06) },
1855 { X86_64_TABLE (X86_64_07) },
1856 /* 08 */
1857 { "orB", { Ebh1, Gb }, 0 },
1858 { "orS", { Evh1, Gv }, 0 },
1859 { "orB", { Gb, EbS }, 0 },
1860 { "orS", { Gv, EvS }, 0 },
1861 { "orB", { AL, Ib }, 0 },
1862 { "orS", { eAX, Iv }, 0 },
1863 { X86_64_TABLE (X86_64_0E) },
1864 { Bad_Opcode }, /* 0x0f extended opcode escape */
1865 /* 10 */
1866 { "adcB", { Ebh1, Gb }, 0 },
1867 { "adcS", { Evh1, Gv }, 0 },
1868 { "adcB", { Gb, EbS }, 0 },
1869 { "adcS", { Gv, EvS }, 0 },
1870 { "adcB", { AL, Ib }, 0 },
1871 { "adcS", { eAX, Iv }, 0 },
1872 { X86_64_TABLE (X86_64_16) },
1873 { X86_64_TABLE (X86_64_17) },
1874 /* 18 */
1875 { "sbbB", { Ebh1, Gb }, 0 },
1876 { "sbbS", { Evh1, Gv }, 0 },
1877 { "sbbB", { Gb, EbS }, 0 },
1878 { "sbbS", { Gv, EvS }, 0 },
1879 { "sbbB", { AL, Ib }, 0 },
1880 { "sbbS", { eAX, Iv }, 0 },
1881 { X86_64_TABLE (X86_64_1E) },
1882 { X86_64_TABLE (X86_64_1F) },
1883 /* 20 */
1884 { "andB", { Ebh1, Gb }, 0 },
1885 { "andS", { Evh1, Gv }, 0 },
1886 { "andB", { Gb, EbS }, 0 },
1887 { "andS", { Gv, EvS }, 0 },
1888 { "andB", { AL, Ib }, 0 },
1889 { "andS", { eAX, Iv }, 0 },
1890 { Bad_Opcode }, /* SEG ES prefix */
1891 { X86_64_TABLE (X86_64_27) },
1892 /* 28 */
1893 { "subB", { Ebh1, Gb }, 0 },
1894 { "subS", { Evh1, Gv }, 0 },
1895 { "subB", { Gb, EbS }, 0 },
1896 { "subS", { Gv, EvS }, 0 },
1897 { "subB", { AL, Ib }, 0 },
1898 { "subS", { eAX, Iv }, 0 },
1899 { Bad_Opcode }, /* SEG CS prefix */
1900 { X86_64_TABLE (X86_64_2F) },
1901 /* 30 */
1902 { "xorB", { Ebh1, Gb }, 0 },
1903 { "xorS", { Evh1, Gv }, 0 },
1904 { "xorB", { Gb, EbS }, 0 },
1905 { "xorS", { Gv, EvS }, 0 },
1906 { "xorB", { AL, Ib }, 0 },
1907 { "xorS", { eAX, Iv }, 0 },
1908 { Bad_Opcode }, /* SEG SS prefix */
1909 { X86_64_TABLE (X86_64_37) },
1910 /* 38 */
1911 { "cmpB", { Eb, Gb }, 0 },
1912 { "cmpS", { Ev, Gv }, 0 },
1913 { "cmpB", { Gb, EbS }, 0 },
1914 { "cmpS", { Gv, EvS }, 0 },
1915 { "cmpB", { AL, Ib }, 0 },
1916 { "cmpS", { eAX, Iv }, 0 },
1917 { Bad_Opcode }, /* SEG DS prefix */
1918 { X86_64_TABLE (X86_64_3F) },
1919 /* 40 */
1920 { "inc{S|}", { RMeAX }, 0 },
1921 { "inc{S|}", { RMeCX }, 0 },
1922 { "inc{S|}", { RMeDX }, 0 },
1923 { "inc{S|}", { RMeBX }, 0 },
1924 { "inc{S|}", { RMeSP }, 0 },
1925 { "inc{S|}", { RMeBP }, 0 },
1926 { "inc{S|}", { RMeSI }, 0 },
1927 { "inc{S|}", { RMeDI }, 0 },
1928 /* 48 */
1929 { "dec{S|}", { RMeAX }, 0 },
1930 { "dec{S|}", { RMeCX }, 0 },
1931 { "dec{S|}", { RMeDX }, 0 },
1932 { "dec{S|}", { RMeBX }, 0 },
1933 { "dec{S|}", { RMeSP }, 0 },
1934 { "dec{S|}", { RMeBP }, 0 },
1935 { "dec{S|}", { RMeSI }, 0 },
1936 { "dec{S|}", { RMeDI }, 0 },
1937 /* 50 */
1938 { "push{!P|}", { RMrAX }, 0 },
1939 { "push{!P|}", { RMrCX }, 0 },
1940 { "push{!P|}", { RMrDX }, 0 },
1941 { "push{!P|}", { RMrBX }, 0 },
1942 { "push{!P|}", { RMrSP }, 0 },
1943 { "push{!P|}", { RMrBP }, 0 },
1944 { "push{!P|}", { RMrSI }, 0 },
1945 { "push{!P|}", { RMrDI }, 0 },
1946 /* 58 */
1947 { "pop{!P|}", { RMrAX }, 0 },
1948 { "pop{!P|}", { RMrCX }, 0 },
1949 { "pop{!P|}", { RMrDX }, 0 },
1950 { "pop{!P|}", { RMrBX }, 0 },
1951 { "pop{!P|}", { RMrSP }, 0 },
1952 { "pop{!P|}", { RMrBP }, 0 },
1953 { "pop{!P|}", { RMrSI }, 0 },
1954 { "pop{!P|}", { RMrDI }, 0 },
1955 /* 60 */
1956 { X86_64_TABLE (X86_64_60) },
1957 { X86_64_TABLE (X86_64_61) },
1958 { X86_64_TABLE (X86_64_62) },
1959 { X86_64_TABLE (X86_64_63) },
1960 { Bad_Opcode }, /* seg fs */
1961 { Bad_Opcode }, /* seg gs */
1962 { Bad_Opcode }, /* op size prefix */
1963 { Bad_Opcode }, /* adr size prefix */
1964 /* 68 */
1965 { "pushP", { sIv }, 0 },
1966 { "imulS", { Gv, Ev, Iv }, 0 },
1967 { "pushP", { sIbT }, 0 },
1968 { "imulS", { Gv, Ev, sIb }, 0 },
1969 { "ins{b|}", { Ybr, indirDX }, 0 },
1970 { X86_64_TABLE (X86_64_6D) },
1971 { "outs{b|}", { indirDXr, Xb }, 0 },
1972 { X86_64_TABLE (X86_64_6F) },
1973 /* 70 */
1974 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1975 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1976 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1977 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1978 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1979 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1980 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1981 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1982 /* 78 */
1983 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1984 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1985 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1986 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1987 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1988 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1989 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1990 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1991 /* 80 */
1992 { REG_TABLE (REG_80) },
1993 { REG_TABLE (REG_81) },
1994 { X86_64_TABLE (X86_64_82) },
1995 { REG_TABLE (REG_83) },
1996 { "testB", { Eb, Gb }, 0 },
1997 { "testS", { Ev, Gv }, 0 },
1998 { "xchgB", { Ebh2, Gb }, 0 },
1999 { "xchgS", { Evh2, Gv }, 0 },
2000 /* 88 */
2001 { "movB", { Ebh3, Gb }, 0 },
2002 { "movS", { Evh3, Gv }, 0 },
2003 { "movB", { Gb, EbS }, 0 },
2004 { "movS", { Gv, EvS }, 0 },
2005 { "movD", { Sv, Sw }, 0 },
2006 { MOD_TABLE (MOD_8D) },
2007 { "movD", { Sw, Sv }, 0 },
2008 { REG_TABLE (REG_8F) },
2009 /* 90 */
2010 { PREFIX_TABLE (PREFIX_90) },
2011 { "xchgS", { RMeCX, eAX }, 0 },
2012 { "xchgS", { RMeDX, eAX }, 0 },
2013 { "xchgS", { RMeBX, eAX }, 0 },
2014 { "xchgS", { RMeSP, eAX }, 0 },
2015 { "xchgS", { RMeBP, eAX }, 0 },
2016 { "xchgS", { RMeSI, eAX }, 0 },
2017 { "xchgS", { RMeDI, eAX }, 0 },
2018 /* 98 */
2019 { "cW{t|}R", { XX }, 0 },
2020 { "cR{t|}O", { XX }, 0 },
2021 { X86_64_TABLE (X86_64_9A) },
2022 { Bad_Opcode }, /* fwait */
2023 { "pushfP", { XX }, 0 },
2024 { "popfP", { XX }, 0 },
2025 { "sahf", { XX }, 0 },
2026 { "lahf", { XX }, 0 },
2027 /* a0 */
2028 { "mov%LB", { AL, Ob }, 0 },
2029 { "mov%LS", { eAX, Ov }, 0 },
2030 { "mov%LB", { Ob, AL }, 0 },
2031 { "mov%LS", { Ov, eAX }, 0 },
2032 { "movs{b|}", { Ybr, Xb }, 0 },
2033 { "movs{R|}", { Yvr, Xv }, 0 },
2034 { "cmps{b|}", { Xb, Yb }, 0 },
2035 { "cmps{R|}", { Xv, Yv }, 0 },
2036 /* a8 */
2037 { "testB", { AL, Ib }, 0 },
2038 { "testS", { eAX, Iv }, 0 },
2039 { "stosB", { Ybr, AL }, 0 },
2040 { "stosS", { Yvr, eAX }, 0 },
2041 { "lodsB", { ALr, Xb }, 0 },
2042 { "lodsS", { eAXr, Xv }, 0 },
2043 { "scasB", { AL, Yb }, 0 },
2044 { "scasS", { eAX, Yv }, 0 },
2045 /* b0 */
2046 { "movB", { RMAL, Ib }, 0 },
2047 { "movB", { RMCL, Ib }, 0 },
2048 { "movB", { RMDL, Ib }, 0 },
2049 { "movB", { RMBL, Ib }, 0 },
2050 { "movB", { RMAH, Ib }, 0 },
2051 { "movB", { RMCH, Ib }, 0 },
2052 { "movB", { RMDH, Ib }, 0 },
2053 { "movB", { RMBH, Ib }, 0 },
2054 /* b8 */
2055 { "mov%LV", { RMeAX, Iv64 }, 0 },
2056 { "mov%LV", { RMeCX, Iv64 }, 0 },
2057 { "mov%LV", { RMeDX, Iv64 }, 0 },
2058 { "mov%LV", { RMeBX, Iv64 }, 0 },
2059 { "mov%LV", { RMeSP, Iv64 }, 0 },
2060 { "mov%LV", { RMeBP, Iv64 }, 0 },
2061 { "mov%LV", { RMeSI, Iv64 }, 0 },
2062 { "mov%LV", { RMeDI, Iv64 }, 0 },
2063 /* c0 */
2064 { REG_TABLE (REG_C0) },
2065 { REG_TABLE (REG_C1) },
2066 { X86_64_TABLE (X86_64_C2) },
2067 { X86_64_TABLE (X86_64_C3) },
2068 { X86_64_TABLE (X86_64_C4) },
2069 { X86_64_TABLE (X86_64_C5) },
2070 { REG_TABLE (REG_C6) },
2071 { REG_TABLE (REG_C7) },
2072 /* c8 */
2073 { "enterP", { Iw, Ib }, 0 },
2074 { "leaveP", { XX }, 0 },
2075 { "{l|}ret{|f}%LP", { Iw }, 0 },
2076 { "{l|}ret{|f}%LP", { XX }, 0 },
2077 { "int3", { XX }, 0 },
2078 { "int", { Ib }, 0 },
2079 { X86_64_TABLE (X86_64_CE) },
2080 { "iret%LP", { XX }, 0 },
2081 /* d0 */
2082 { REG_TABLE (REG_D0) },
2083 { REG_TABLE (REG_D1) },
2084 { REG_TABLE (REG_D2) },
2085 { REG_TABLE (REG_D3) },
2086 { X86_64_TABLE (X86_64_D4) },
2087 { X86_64_TABLE (X86_64_D5) },
2088 { Bad_Opcode },
2089 { "xlat", { DSBX }, 0 },
2090 /* d8 */
2091 { FLOAT },
2092 { FLOAT },
2093 { FLOAT },
2094 { FLOAT },
2095 { FLOAT },
2096 { FLOAT },
2097 { FLOAT },
2098 { FLOAT },
2099 /* e0 */
2100 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2101 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2102 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2103 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2104 { "inB", { AL, Ib }, 0 },
2105 { "inG", { zAX, Ib }, 0 },
2106 { "outB", { Ib, AL }, 0 },
2107 { "outG", { Ib, zAX }, 0 },
2108 /* e8 */
2109 { X86_64_TABLE (X86_64_E8) },
2110 { X86_64_TABLE (X86_64_E9) },
2111 { X86_64_TABLE (X86_64_EA) },
2112 { "jmp", { Jb, BND }, 0 },
2113 { "inB", { AL, indirDX }, 0 },
2114 { "inG", { zAX, indirDX }, 0 },
2115 { "outB", { indirDX, AL }, 0 },
2116 { "outG", { indirDX, zAX }, 0 },
2117 /* f0 */
2118 { Bad_Opcode }, /* lock prefix */
2119 { "int1", { XX }, 0 },
2120 { Bad_Opcode }, /* repne */
2121 { Bad_Opcode }, /* repz */
2122 { "hlt", { XX }, 0 },
2123 { "cmc", { XX }, 0 },
2124 { REG_TABLE (REG_F6) },
2125 { REG_TABLE (REG_F7) },
2126 /* f8 */
2127 { "clc", { XX }, 0 },
2128 { "stc", { XX }, 0 },
2129 { "cli", { XX }, 0 },
2130 { "sti", { XX }, 0 },
2131 { "cld", { XX }, 0 },
2132 { "std", { XX }, 0 },
2133 { REG_TABLE (REG_FE) },
2134 { REG_TABLE (REG_FF) },
2135 };
2136
2137 static const struct dis386 dis386_twobyte[] = {
2138 /* 00 */
2139 { REG_TABLE (REG_0F00 ) },
2140 { REG_TABLE (REG_0F01 ) },
2141 { MOD_TABLE (MOD_0F02) },
2142 { MOD_TABLE (MOD_0F03) },
2143 { Bad_Opcode },
2144 { "syscall", { XX }, 0 },
2145 { "clts", { XX }, 0 },
2146 { "sysret%LQ", { XX }, 0 },
2147 /* 08 */
2148 { "invd", { XX }, 0 },
2149 { PREFIX_TABLE (PREFIX_0F09) },
2150 { Bad_Opcode },
2151 { "ud2", { XX }, 0 },
2152 { Bad_Opcode },
2153 { REG_TABLE (REG_0F0D) },
2154 { "femms", { XX }, 0 },
2155 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2156 /* 10 */
2157 { PREFIX_TABLE (PREFIX_0F10) },
2158 { PREFIX_TABLE (PREFIX_0F11) },
2159 { PREFIX_TABLE (PREFIX_0F12) },
2160 { MOD_TABLE (MOD_0F13) },
2161 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2162 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2163 { PREFIX_TABLE (PREFIX_0F16) },
2164 { MOD_TABLE (MOD_0F17) },
2165 /* 18 */
2166 { REG_TABLE (REG_0F18) },
2167 { "nopQ", { Ev }, 0 },
2168 { PREFIX_TABLE (PREFIX_0F1A) },
2169 { PREFIX_TABLE (PREFIX_0F1B) },
2170 { PREFIX_TABLE (PREFIX_0F1C) },
2171 { "nopQ", { Ev }, 0 },
2172 { PREFIX_TABLE (PREFIX_0F1E) },
2173 { "nopQ", { Ev }, 0 },
2174 /* 20 */
2175 { "movZ", { Em, Cm }, 0 },
2176 { "movZ", { Em, Dm }, 0 },
2177 { "movZ", { Cm, Em }, 0 },
2178 { "movZ", { Dm, Em }, 0 },
2179 { X86_64_TABLE (X86_64_0F24) },
2180 { Bad_Opcode },
2181 { X86_64_TABLE (X86_64_0F26) },
2182 { Bad_Opcode },
2183 /* 28 */
2184 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2185 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2186 { PREFIX_TABLE (PREFIX_0F2A) },
2187 { PREFIX_TABLE (PREFIX_0F2B) },
2188 { PREFIX_TABLE (PREFIX_0F2C) },
2189 { PREFIX_TABLE (PREFIX_0F2D) },
2190 { PREFIX_TABLE (PREFIX_0F2E) },
2191 { PREFIX_TABLE (PREFIX_0F2F) },
2192 /* 30 */
2193 { "wrmsr", { XX }, 0 },
2194 { "rdtsc", { XX }, 0 },
2195 { "rdmsr", { XX }, 0 },
2196 { "rdpmc", { XX }, 0 },
2197 { "sysenter", { SEP }, 0 },
2198 { "sysexit%LQ", { SEP }, 0 },
2199 { Bad_Opcode },
2200 { "getsec", { XX }, 0 },
2201 /* 38 */
2202 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2203 { Bad_Opcode },
2204 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2205 { Bad_Opcode },
2206 { Bad_Opcode },
2207 { Bad_Opcode },
2208 { Bad_Opcode },
2209 { Bad_Opcode },
2210 /* 40 */
2211 { "cmovoS", { Gv, Ev }, 0 },
2212 { "cmovnoS", { Gv, Ev }, 0 },
2213 { "cmovbS", { Gv, Ev }, 0 },
2214 { "cmovaeS", { Gv, Ev }, 0 },
2215 { "cmoveS", { Gv, Ev }, 0 },
2216 { "cmovneS", { Gv, Ev }, 0 },
2217 { "cmovbeS", { Gv, Ev }, 0 },
2218 { "cmovaS", { Gv, Ev }, 0 },
2219 /* 48 */
2220 { "cmovsS", { Gv, Ev }, 0 },
2221 { "cmovnsS", { Gv, Ev }, 0 },
2222 { "cmovpS", { Gv, Ev }, 0 },
2223 { "cmovnpS", { Gv, Ev }, 0 },
2224 { "cmovlS", { Gv, Ev }, 0 },
2225 { "cmovgeS", { Gv, Ev }, 0 },
2226 { "cmovleS", { Gv, Ev }, 0 },
2227 { "cmovgS", { Gv, Ev }, 0 },
2228 /* 50 */
2229 { MOD_TABLE (MOD_0F50) },
2230 { PREFIX_TABLE (PREFIX_0F51) },
2231 { PREFIX_TABLE (PREFIX_0F52) },
2232 { PREFIX_TABLE (PREFIX_0F53) },
2233 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2234 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2235 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2236 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2237 /* 58 */
2238 { PREFIX_TABLE (PREFIX_0F58) },
2239 { PREFIX_TABLE (PREFIX_0F59) },
2240 { PREFIX_TABLE (PREFIX_0F5A) },
2241 { PREFIX_TABLE (PREFIX_0F5B) },
2242 { PREFIX_TABLE (PREFIX_0F5C) },
2243 { PREFIX_TABLE (PREFIX_0F5D) },
2244 { PREFIX_TABLE (PREFIX_0F5E) },
2245 { PREFIX_TABLE (PREFIX_0F5F) },
2246 /* 60 */
2247 { PREFIX_TABLE (PREFIX_0F60) },
2248 { PREFIX_TABLE (PREFIX_0F61) },
2249 { PREFIX_TABLE (PREFIX_0F62) },
2250 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2251 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2252 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2253 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2254 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2255 /* 68 */
2256 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2257 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2258 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2259 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2260 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2261 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2262 { "movK", { MX, Edq }, PREFIX_OPCODE },
2263 { PREFIX_TABLE (PREFIX_0F6F) },
2264 /* 70 */
2265 { PREFIX_TABLE (PREFIX_0F70) },
2266 { MOD_TABLE (MOD_0F71) },
2267 { MOD_TABLE (MOD_0F72) },
2268 { MOD_TABLE (MOD_0F73) },
2269 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2270 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2271 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2272 { "emms", { XX }, PREFIX_OPCODE },
2273 /* 78 */
2274 { PREFIX_TABLE (PREFIX_0F78) },
2275 { PREFIX_TABLE (PREFIX_0F79) },
2276 { Bad_Opcode },
2277 { Bad_Opcode },
2278 { PREFIX_TABLE (PREFIX_0F7C) },
2279 { PREFIX_TABLE (PREFIX_0F7D) },
2280 { PREFIX_TABLE (PREFIX_0F7E) },
2281 { PREFIX_TABLE (PREFIX_0F7F) },
2282 /* 80 */
2283 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2284 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2285 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2286 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2287 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2288 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2289 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2290 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2291 /* 88 */
2292 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2293 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2294 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2295 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2296 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2297 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2298 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2299 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2300 /* 90 */
2301 { "seto", { Eb }, 0 },
2302 { "setno", { Eb }, 0 },
2303 { "setb", { Eb }, 0 },
2304 { "setae", { Eb }, 0 },
2305 { "sete", { Eb }, 0 },
2306 { "setne", { Eb }, 0 },
2307 { "setbe", { Eb }, 0 },
2308 { "seta", { Eb }, 0 },
2309 /* 98 */
2310 { "sets", { Eb }, 0 },
2311 { "setns", { Eb }, 0 },
2312 { "setp", { Eb }, 0 },
2313 { "setnp", { Eb }, 0 },
2314 { "setl", { Eb }, 0 },
2315 { "setge", { Eb }, 0 },
2316 { "setle", { Eb }, 0 },
2317 { "setg", { Eb }, 0 },
2318 /* a0 */
2319 { "pushP", { fs }, 0 },
2320 { "popP", { fs }, 0 },
2321 { "cpuid", { XX }, 0 },
2322 { "btS", { Ev, Gv }, 0 },
2323 { "shldS", { Ev, Gv, Ib }, 0 },
2324 { "shldS", { Ev, Gv, CL }, 0 },
2325 { REG_TABLE (REG_0FA6) },
2326 { REG_TABLE (REG_0FA7) },
2327 /* a8 */
2328 { "pushP", { gs }, 0 },
2329 { "popP", { gs }, 0 },
2330 { "rsm", { XX }, 0 },
2331 { "btsS", { Evh1, Gv }, 0 },
2332 { "shrdS", { Ev, Gv, Ib }, 0 },
2333 { "shrdS", { Ev, Gv, CL }, 0 },
2334 { REG_TABLE (REG_0FAE) },
2335 { "imulS", { Gv, Ev }, 0 },
2336 /* b0 */
2337 { "cmpxchgB", { Ebh1, Gb }, 0 },
2338 { "cmpxchgS", { Evh1, Gv }, 0 },
2339 { MOD_TABLE (MOD_0FB2) },
2340 { "btrS", { Evh1, Gv }, 0 },
2341 { MOD_TABLE (MOD_0FB4) },
2342 { MOD_TABLE (MOD_0FB5) },
2343 { "movz{bR|x}", { Gv, Eb }, 0 },
2344 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2345 /* b8 */
2346 { PREFIX_TABLE (PREFIX_0FB8) },
2347 { "ud1S", { Gv, Ev }, 0 },
2348 { REG_TABLE (REG_0FBA) },
2349 { "btcS", { Evh1, Gv }, 0 },
2350 { PREFIX_TABLE (PREFIX_0FBC) },
2351 { PREFIX_TABLE (PREFIX_0FBD) },
2352 { "movs{bR|x}", { Gv, Eb }, 0 },
2353 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2354 /* c0 */
2355 { "xaddB", { Ebh1, Gb }, 0 },
2356 { "xaddS", { Evh1, Gv }, 0 },
2357 { PREFIX_TABLE (PREFIX_0FC2) },
2358 { MOD_TABLE (MOD_0FC3) },
2359 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2360 { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
2361 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2362 { REG_TABLE (REG_0FC7) },
2363 /* c8 */
2364 { "bswap", { RMeAX }, 0 },
2365 { "bswap", { RMeCX }, 0 },
2366 { "bswap", { RMeDX }, 0 },
2367 { "bswap", { RMeBX }, 0 },
2368 { "bswap", { RMeSP }, 0 },
2369 { "bswap", { RMeBP }, 0 },
2370 { "bswap", { RMeSI }, 0 },
2371 { "bswap", { RMeDI }, 0 },
2372 /* d0 */
2373 { PREFIX_TABLE (PREFIX_0FD0) },
2374 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2375 { "psrld", { MX, EM }, PREFIX_OPCODE },
2376 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2377 { "paddq", { MX, EM }, PREFIX_OPCODE },
2378 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2379 { PREFIX_TABLE (PREFIX_0FD6) },
2380 { MOD_TABLE (MOD_0FD7) },
2381 /* d8 */
2382 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2383 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2384 { "pminub", { MX, EM }, PREFIX_OPCODE },
2385 { "pand", { MX, EM }, PREFIX_OPCODE },
2386 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2387 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2388 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2389 { "pandn", { MX, EM }, PREFIX_OPCODE },
2390 /* e0 */
2391 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2392 { "psraw", { MX, EM }, PREFIX_OPCODE },
2393 { "psrad", { MX, EM }, PREFIX_OPCODE },
2394 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2395 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2396 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2397 { PREFIX_TABLE (PREFIX_0FE6) },
2398 { PREFIX_TABLE (PREFIX_0FE7) },
2399 /* e8 */
2400 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2401 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2402 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2403 { "por", { MX, EM }, PREFIX_OPCODE },
2404 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2405 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2406 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2407 { "pxor", { MX, EM }, PREFIX_OPCODE },
2408 /* f0 */
2409 { PREFIX_TABLE (PREFIX_0FF0) },
2410 { "psllw", { MX, EM }, PREFIX_OPCODE },
2411 { "pslld", { MX, EM }, PREFIX_OPCODE },
2412 { "psllq", { MX, EM }, PREFIX_OPCODE },
2413 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2414 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2415 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2416 { PREFIX_TABLE (PREFIX_0FF7) },
2417 /* f8 */
2418 { "psubb", { MX, EM }, PREFIX_OPCODE },
2419 { "psubw", { MX, EM }, PREFIX_OPCODE },
2420 { "psubd", { MX, EM }, PREFIX_OPCODE },
2421 { "psubq", { MX, EM }, PREFIX_OPCODE },
2422 { "paddb", { MX, EM }, PREFIX_OPCODE },
2423 { "paddw", { MX, EM }, PREFIX_OPCODE },
2424 { "paddd", { MX, EM }, PREFIX_OPCODE },
2425 { "ud0S", { Gv, Ev }, 0 },
2426 };
2427
2428 static const bool onebyte_has_modrm[256] = {
2429 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2430 /* ------------------------------- */
2431 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2432 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2433 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2434 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2435 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2436 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2437 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2438 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2439 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2440 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2441 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2442 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2443 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2444 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2445 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2446 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2447 /* ------------------------------- */
2448 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2449 };
2450
2451 static const bool twobyte_has_modrm[256] = {
2452 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2453 /* ------------------------------- */
2454 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2455 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2456 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2457 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2458 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2459 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2460 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2461 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2462 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2463 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2464 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2465 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2466 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2467 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2468 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2469 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2470 /* ------------------------------- */
2471 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2472 };
2473
2474
2475 struct op
2476 {
2477 const char *name;
2478 unsigned int len;
2479 };
2480
2481 /* If we are accessing mod/rm/reg without need_modrm set, then the
2482 values are stale. Hitting this abort likely indicates that you
2483 need to update onebyte_has_modrm or twobyte_has_modrm. */
2484 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2485
2486 static const char intel_index16[][6] = {
2487 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2488 };
2489
2490 static const char att_names64[][8] = {
2491 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2492 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2493 };
2494 static const char att_names32[][8] = {
2495 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2496 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2497 };
2498 static const char att_names16[][8] = {
2499 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2500 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2501 };
2502 static const char att_names8[][8] = {
2503 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2504 };
2505 static const char att_names8rex[][8] = {
2506 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2507 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2508 };
2509 static const char att_names_seg[][4] = {
2510 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2511 };
2512 static const char att_index64[] = "%riz";
2513 static const char att_index32[] = "%eiz";
2514 static const char att_index16[][8] = {
2515 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2516 };
2517
2518 static const char att_names_mm[][8] = {
2519 "%mm0", "%mm1", "%mm2", "%mm3",
2520 "%mm4", "%mm5", "%mm6", "%mm7"
2521 };
2522
2523 static const char att_names_bnd[][8] = {
2524 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2525 };
2526
2527 static const char att_names_xmm[][8] = {
2528 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2529 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2530 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2531 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2532 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2533 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2534 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2535 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2536 };
2537
2538 static const char att_names_ymm[][8] = {
2539 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2540 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2541 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2542 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2543 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2544 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2545 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2546 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2547 };
2548
2549 static const char att_names_zmm[][8] = {
2550 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2551 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2552 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2553 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2554 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2555 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2556 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2557 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2558 };
2559
2560 static const char att_names_tmm[][8] = {
2561 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2562 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2563 };
2564
2565 static const char att_names_mask[][8] = {
2566 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2567 };
2568
2569 static const char *const names_rounding[] =
2570 {
2571 "{rn-",
2572 "{rd-",
2573 "{ru-",
2574 "{rz-"
2575 };
2576
2577 static const struct dis386 reg_table[][8] = {
2578 /* REG_80 */
2579 {
2580 { "addA", { Ebh1, Ib }, 0 },
2581 { "orA", { Ebh1, Ib }, 0 },
2582 { "adcA", { Ebh1, Ib }, 0 },
2583 { "sbbA", { Ebh1, Ib }, 0 },
2584 { "andA", { Ebh1, Ib }, 0 },
2585 { "subA", { Ebh1, Ib }, 0 },
2586 { "xorA", { Ebh1, Ib }, 0 },
2587 { "cmpA", { Eb, Ib }, 0 },
2588 },
2589 /* REG_81 */
2590 {
2591 { "addQ", { Evh1, Iv }, 0 },
2592 { "orQ", { Evh1, Iv }, 0 },
2593 { "adcQ", { Evh1, Iv }, 0 },
2594 { "sbbQ", { Evh1, Iv }, 0 },
2595 { "andQ", { Evh1, Iv }, 0 },
2596 { "subQ", { Evh1, Iv }, 0 },
2597 { "xorQ", { Evh1, Iv }, 0 },
2598 { "cmpQ", { Ev, Iv }, 0 },
2599 },
2600 /* REG_83 */
2601 {
2602 { "addQ", { Evh1, sIb }, 0 },
2603 { "orQ", { Evh1, sIb }, 0 },
2604 { "adcQ", { Evh1, sIb }, 0 },
2605 { "sbbQ", { Evh1, sIb }, 0 },
2606 { "andQ", { Evh1, sIb }, 0 },
2607 { "subQ", { Evh1, sIb }, 0 },
2608 { "xorQ", { Evh1, sIb }, 0 },
2609 { "cmpQ", { Ev, sIb }, 0 },
2610 },
2611 /* REG_8F */
2612 {
2613 { "pop{P|}", { stackEv }, 0 },
2614 { XOP_8F_TABLE (XOP_09) },
2615 { Bad_Opcode },
2616 { Bad_Opcode },
2617 { Bad_Opcode },
2618 { XOP_8F_TABLE (XOP_09) },
2619 },
2620 /* REG_C0 */
2621 {
2622 { "rolA", { Eb, Ib }, 0 },
2623 { "rorA", { Eb, Ib }, 0 },
2624 { "rclA", { Eb, Ib }, 0 },
2625 { "rcrA", { Eb, Ib }, 0 },
2626 { "shlA", { Eb, Ib }, 0 },
2627 { "shrA", { Eb, Ib }, 0 },
2628 { "shlA", { Eb, Ib }, 0 },
2629 { "sarA", { Eb, Ib }, 0 },
2630 },
2631 /* REG_C1 */
2632 {
2633 { "rolQ", { Ev, Ib }, 0 },
2634 { "rorQ", { Ev, Ib }, 0 },
2635 { "rclQ", { Ev, Ib }, 0 },
2636 { "rcrQ", { Ev, Ib }, 0 },
2637 { "shlQ", { Ev, Ib }, 0 },
2638 { "shrQ", { Ev, Ib }, 0 },
2639 { "shlQ", { Ev, Ib }, 0 },
2640 { "sarQ", { Ev, Ib }, 0 },
2641 },
2642 /* REG_C6 */
2643 {
2644 { "movA", { Ebh3, Ib }, 0 },
2645 { Bad_Opcode },
2646 { Bad_Opcode },
2647 { Bad_Opcode },
2648 { Bad_Opcode },
2649 { Bad_Opcode },
2650 { Bad_Opcode },
2651 { MOD_TABLE (MOD_C6_REG_7) },
2652 },
2653 /* REG_C7 */
2654 {
2655 { "movQ", { Evh3, Iv }, 0 },
2656 { Bad_Opcode },
2657 { Bad_Opcode },
2658 { Bad_Opcode },
2659 { Bad_Opcode },
2660 { Bad_Opcode },
2661 { Bad_Opcode },
2662 { MOD_TABLE (MOD_C7_REG_7) },
2663 },
2664 /* REG_D0 */
2665 {
2666 { "rolA", { Eb, I1 }, 0 },
2667 { "rorA", { Eb, I1 }, 0 },
2668 { "rclA", { Eb, I1 }, 0 },
2669 { "rcrA", { Eb, I1 }, 0 },
2670 { "shlA", { Eb, I1 }, 0 },
2671 { "shrA", { Eb, I1 }, 0 },
2672 { "shlA", { Eb, I1 }, 0 },
2673 { "sarA", { Eb, I1 }, 0 },
2674 },
2675 /* REG_D1 */
2676 {
2677 { "rolQ", { Ev, I1 }, 0 },
2678 { "rorQ", { Ev, I1 }, 0 },
2679 { "rclQ", { Ev, I1 }, 0 },
2680 { "rcrQ", { Ev, I1 }, 0 },
2681 { "shlQ", { Ev, I1 }, 0 },
2682 { "shrQ", { Ev, I1 }, 0 },
2683 { "shlQ", { Ev, I1 }, 0 },
2684 { "sarQ", { Ev, I1 }, 0 },
2685 },
2686 /* REG_D2 */
2687 {
2688 { "rolA", { Eb, CL }, 0 },
2689 { "rorA", { Eb, CL }, 0 },
2690 { "rclA", { Eb, CL }, 0 },
2691 { "rcrA", { Eb, CL }, 0 },
2692 { "shlA", { Eb, CL }, 0 },
2693 { "shrA", { Eb, CL }, 0 },
2694 { "shlA", { Eb, CL }, 0 },
2695 { "sarA", { Eb, CL }, 0 },
2696 },
2697 /* REG_D3 */
2698 {
2699 { "rolQ", { Ev, CL }, 0 },
2700 { "rorQ", { Ev, CL }, 0 },
2701 { "rclQ", { Ev, CL }, 0 },
2702 { "rcrQ", { Ev, CL }, 0 },
2703 { "shlQ", { Ev, CL }, 0 },
2704 { "shrQ", { Ev, CL }, 0 },
2705 { "shlQ", { Ev, CL }, 0 },
2706 { "sarQ", { Ev, CL }, 0 },
2707 },
2708 /* REG_F6 */
2709 {
2710 { "testA", { Eb, Ib }, 0 },
2711 { "testA", { Eb, Ib }, 0 },
2712 { "notA", { Ebh1 }, 0 },
2713 { "negA", { Ebh1 }, 0 },
2714 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2715 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2716 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2717 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2718 },
2719 /* REG_F7 */
2720 {
2721 { "testQ", { Ev, Iv }, 0 },
2722 { "testQ", { Ev, Iv }, 0 },
2723 { "notQ", { Evh1 }, 0 },
2724 { "negQ", { Evh1 }, 0 },
2725 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2726 { "imulQ", { Ev }, 0 },
2727 { "divQ", { Ev }, 0 },
2728 { "idivQ", { Ev }, 0 },
2729 },
2730 /* REG_FE */
2731 {
2732 { "incA", { Ebh1 }, 0 },
2733 { "decA", { Ebh1 }, 0 },
2734 },
2735 /* REG_FF */
2736 {
2737 { "incQ", { Evh1 }, 0 },
2738 { "decQ", { Evh1 }, 0 },
2739 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2740 { MOD_TABLE (MOD_FF_REG_3) },
2741 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2742 { MOD_TABLE (MOD_FF_REG_5) },
2743 { "push{P|}", { stackEv }, 0 },
2744 { Bad_Opcode },
2745 },
2746 /* REG_0F00 */
2747 {
2748 { "sldtD", { Sv }, 0 },
2749 { "strD", { Sv }, 0 },
2750 { "lldt", { Ew }, 0 },
2751 { "ltr", { Ew }, 0 },
2752 { "verr", { Ew }, 0 },
2753 { "verw", { Ew }, 0 },
2754 { X86_64_TABLE (X86_64_0F00_REG_6) },
2755 { Bad_Opcode },
2756 },
2757 /* REG_0F01 */
2758 {
2759 { MOD_TABLE (MOD_0F01_REG_0) },
2760 { MOD_TABLE (MOD_0F01_REG_1) },
2761 { MOD_TABLE (MOD_0F01_REG_2) },
2762 { MOD_TABLE (MOD_0F01_REG_3) },
2763 { "smswD", { Sv }, 0 },
2764 { MOD_TABLE (MOD_0F01_REG_5) },
2765 { "lmsw", { Ew }, 0 },
2766 { MOD_TABLE (MOD_0F01_REG_7) },
2767 },
2768 /* REG_0F0D */
2769 {
2770 { "prefetch", { Mb }, 0 },
2771 { "prefetchw", { Mb }, 0 },
2772 { "prefetchwt1", { Mb }, 0 },
2773 { "prefetch", { Mb }, 0 },
2774 { "prefetch", { Mb }, 0 },
2775 { "prefetch", { Mb }, 0 },
2776 { "prefetch", { Mb }, 0 },
2777 { "prefetch", { Mb }, 0 },
2778 },
2779 /* REG_0F18 */
2780 {
2781 { MOD_TABLE (MOD_0F18_REG_0) },
2782 { MOD_TABLE (MOD_0F18_REG_1) },
2783 { MOD_TABLE (MOD_0F18_REG_2) },
2784 { MOD_TABLE (MOD_0F18_REG_3) },
2785 { "nopQ", { Ev }, 0 },
2786 { "nopQ", { Ev }, 0 },
2787 { MOD_TABLE (MOD_0F18_REG_6) },
2788 { MOD_TABLE (MOD_0F18_REG_7) },
2789 },
2790 /* REG_0F1C_P_0_MOD_0 */
2791 {
2792 { "cldemote", { Mb }, 0 },
2793 { "nopQ", { Ev }, 0 },
2794 { "nopQ", { Ev }, 0 },
2795 { "nopQ", { Ev }, 0 },
2796 { "nopQ", { Ev }, 0 },
2797 { "nopQ", { Ev }, 0 },
2798 { "nopQ", { Ev }, 0 },
2799 { "nopQ", { Ev }, 0 },
2800 },
2801 /* REG_0F1E_P_1_MOD_3 */
2802 {
2803 { "nopQ", { Ev }, PREFIX_IGNORED },
2804 { "rdsspK", { Edq }, 0 },
2805 { "nopQ", { Ev }, PREFIX_IGNORED },
2806 { "nopQ", { Ev }, PREFIX_IGNORED },
2807 { "nopQ", { Ev }, PREFIX_IGNORED },
2808 { "nopQ", { Ev }, PREFIX_IGNORED },
2809 { "nopQ", { Ev }, PREFIX_IGNORED },
2810 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2811 },
2812 /* REG_0F38D8_PREFIX_1 */
2813 {
2814 { "aesencwide128kl", { M }, 0 },
2815 { "aesdecwide128kl", { M }, 0 },
2816 { "aesencwide256kl", { M }, 0 },
2817 { "aesdecwide256kl", { M }, 0 },
2818 },
2819 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2820 {
2821 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2822 },
2823 /* REG_0F71_MOD_0 */
2824 {
2825 { Bad_Opcode },
2826 { Bad_Opcode },
2827 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2828 { Bad_Opcode },
2829 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2830 { Bad_Opcode },
2831 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2832 },
2833 /* REG_0F72_MOD_0 */
2834 {
2835 { Bad_Opcode },
2836 { Bad_Opcode },
2837 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2838 { Bad_Opcode },
2839 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2840 { Bad_Opcode },
2841 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2842 },
2843 /* REG_0F73_MOD_0 */
2844 {
2845 { Bad_Opcode },
2846 { Bad_Opcode },
2847 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2848 { "psrldq", { XS, Ib }, PREFIX_DATA },
2849 { Bad_Opcode },
2850 { Bad_Opcode },
2851 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2852 { "pslldq", { XS, Ib }, PREFIX_DATA },
2853 },
2854 /* REG_0FA6 */
2855 {
2856 { "montmul", { { OP_0f07, 0 } }, 0 },
2857 { "xsha1", { { OP_0f07, 0 } }, 0 },
2858 { "xsha256", { { OP_0f07, 0 } }, 0 },
2859 },
2860 /* REG_0FA7 */
2861 {
2862 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2863 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2864 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2865 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2866 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2867 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2868 },
2869 /* REG_0FAE */
2870 {
2871 { MOD_TABLE (MOD_0FAE_REG_0) },
2872 { MOD_TABLE (MOD_0FAE_REG_1) },
2873 { MOD_TABLE (MOD_0FAE_REG_2) },
2874 { MOD_TABLE (MOD_0FAE_REG_3) },
2875 { MOD_TABLE (MOD_0FAE_REG_4) },
2876 { MOD_TABLE (MOD_0FAE_REG_5) },
2877 { MOD_TABLE (MOD_0FAE_REG_6) },
2878 { MOD_TABLE (MOD_0FAE_REG_7) },
2879 },
2880 /* REG_0FBA */
2881 {
2882 { Bad_Opcode },
2883 { Bad_Opcode },
2884 { Bad_Opcode },
2885 { Bad_Opcode },
2886 { "btQ", { Ev, Ib }, 0 },
2887 { "btsQ", { Evh1, Ib }, 0 },
2888 { "btrQ", { Evh1, Ib }, 0 },
2889 { "btcQ", { Evh1, Ib }, 0 },
2890 },
2891 /* REG_0FC7 */
2892 {
2893 { Bad_Opcode },
2894 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2895 { Bad_Opcode },
2896 { MOD_TABLE (MOD_0FC7_REG_3) },
2897 { MOD_TABLE (MOD_0FC7_REG_4) },
2898 { MOD_TABLE (MOD_0FC7_REG_5) },
2899 { MOD_TABLE (MOD_0FC7_REG_6) },
2900 { MOD_TABLE (MOD_0FC7_REG_7) },
2901 },
2902 /* REG_VEX_0F71_M_0 */
2903 {
2904 { Bad_Opcode },
2905 { Bad_Opcode },
2906 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2907 { Bad_Opcode },
2908 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2909 { Bad_Opcode },
2910 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2911 },
2912 /* REG_VEX_0F72_M_0 */
2913 {
2914 { Bad_Opcode },
2915 { Bad_Opcode },
2916 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2917 { Bad_Opcode },
2918 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2919 { Bad_Opcode },
2920 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2921 },
2922 /* REG_VEX_0F73_M_0 */
2923 {
2924 { Bad_Opcode },
2925 { Bad_Opcode },
2926 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2927 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2928 { Bad_Opcode },
2929 { Bad_Opcode },
2930 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2931 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2932 },
2933 /* REG_VEX_0FAE */
2934 {
2935 { Bad_Opcode },
2936 { Bad_Opcode },
2937 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2938 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2939 },
2940 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2941 {
2942 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2943 },
2944 /* REG_VEX_0F38F3_L_0 */
2945 {
2946 { Bad_Opcode },
2947 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2948 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2949 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2950 },
2951 /* REG_XOP_09_01_L_0 */
2952 {
2953 { Bad_Opcode },
2954 { "blcfill", { VexGdq, Edq }, 0 },
2955 { "blsfill", { VexGdq, Edq }, 0 },
2956 { "blcs", { VexGdq, Edq }, 0 },
2957 { "tzmsk", { VexGdq, Edq }, 0 },
2958 { "blcic", { VexGdq, Edq }, 0 },
2959 { "blsic", { VexGdq, Edq }, 0 },
2960 { "t1mskc", { VexGdq, Edq }, 0 },
2961 },
2962 /* REG_XOP_09_02_L_0 */
2963 {
2964 { Bad_Opcode },
2965 { "blcmsk", { VexGdq, Edq }, 0 },
2966 { Bad_Opcode },
2967 { Bad_Opcode },
2968 { Bad_Opcode },
2969 { Bad_Opcode },
2970 { "blci", { VexGdq, Edq }, 0 },
2971 },
2972 /* REG_XOP_09_12_M_1_L_0 */
2973 {
2974 { "llwpcb", { Edq }, 0 },
2975 { "slwpcb", { Edq }, 0 },
2976 },
2977 /* REG_XOP_0A_12_L_0 */
2978 {
2979 { "lwpins", { VexGdq, Ed, Id }, 0 },
2980 { "lwpval", { VexGdq, Ed, Id }, 0 },
2981 },
2982
2983 #include "i386-dis-evex-reg.h"
2984 };
2985
2986 static const struct dis386 prefix_table[][4] = {
2987 /* PREFIX_90 */
2988 {
2989 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2990 { "pause", { XX }, 0 },
2991 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2992 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2993 },
2994
2995 /* PREFIX_0F00_REG_6_X86_64 */
2996 {
2997 { Bad_Opcode },
2998 { Bad_Opcode },
2999 { Bad_Opcode },
3000 { "lkgs", { Ew }, 0 },
3001 },
3002
3003 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3004 {
3005 { "wrmsrns", { Skip_MODRM }, 0 },
3006 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3007 { Bad_Opcode },
3008 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3009 },
3010
3011 /* PREFIX_0F01_REG_1_RM_2 */
3012 {
3013 { "clac", { Skip_MODRM }, 0 },
3014 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3015 { Bad_Opcode },
3016 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3017 },
3018
3019 /* PREFIX_0F01_REG_1_RM_4 */
3020 {
3021 { Bad_Opcode },
3022 { Bad_Opcode },
3023 { "tdcall", { Skip_MODRM }, 0 },
3024 { Bad_Opcode },
3025 },
3026
3027 /* PREFIX_0F01_REG_1_RM_5 */
3028 {
3029 { Bad_Opcode },
3030 { Bad_Opcode },
3031 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3032 { Bad_Opcode },
3033 },
3034
3035 /* PREFIX_0F01_REG_1_RM_6 */
3036 {
3037 { Bad_Opcode },
3038 { Bad_Opcode },
3039 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3040 { Bad_Opcode },
3041 },
3042
3043 /* PREFIX_0F01_REG_1_RM_7 */
3044 {
3045 { "encls", { Skip_MODRM }, 0 },
3046 { Bad_Opcode },
3047 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3048 { Bad_Opcode },
3049 },
3050
3051 /* PREFIX_0F01_REG_3_RM_1 */
3052 {
3053 { "vmmcall", { Skip_MODRM }, 0 },
3054 { "vmgexit", { Skip_MODRM }, 0 },
3055 { Bad_Opcode },
3056 { "vmgexit", { Skip_MODRM }, 0 },
3057 },
3058
3059 /* PREFIX_0F01_REG_5_MOD_0 */
3060 {
3061 { Bad_Opcode },
3062 { "rstorssp", { Mq }, PREFIX_OPCODE },
3063 },
3064
3065 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3066 {
3067 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3068 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3069 { Bad_Opcode },
3070 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3071 },
3072
3073 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3074 {
3075 { Bad_Opcode },
3076 { Bad_Opcode },
3077 { Bad_Opcode },
3078 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3079 },
3080
3081 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3082 {
3083 { Bad_Opcode },
3084 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3085 },
3086
3087 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3088 {
3089 { Bad_Opcode },
3090 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3091 },
3092
3093 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3094 {
3095 { Bad_Opcode },
3096 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3097 },
3098
3099 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3100 {
3101 { "rdpkru", { Skip_MODRM }, 0 },
3102 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3103 },
3104
3105 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3106 {
3107 { "wrpkru", { Skip_MODRM }, 0 },
3108 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3109 },
3110
3111 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3112 {
3113 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3114 { "mcommit", { Skip_MODRM }, 0 },
3115 },
3116
3117 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3118 {
3119 { "rdpru", { Skip_MODRM }, 0 },
3120 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3121 },
3122
3123 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3124 {
3125 { "invlpgb", { Skip_MODRM }, 0 },
3126 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3127 { Bad_Opcode },
3128 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3129 },
3130
3131 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3132 {
3133 { "tlbsync", { Skip_MODRM }, 0 },
3134 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3135 { Bad_Opcode },
3136 { "pvalidate", { Skip_MODRM }, 0 },
3137 },
3138
3139 /* PREFIX_0F09 */
3140 {
3141 { "wbinvd", { XX }, 0 },
3142 { "wbnoinvd", { XX }, 0 },
3143 },
3144
3145 /* PREFIX_0F10 */
3146 {
3147 { "movups", { XM, EXx }, PREFIX_OPCODE },
3148 { "movss", { XM, EXd }, PREFIX_OPCODE },
3149 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3150 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3151 },
3152
3153 /* PREFIX_0F11 */
3154 {
3155 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3156 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3157 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3158 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3159 },
3160
3161 /* PREFIX_0F12 */
3162 {
3163 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3164 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3165 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3166 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3167 },
3168
3169 /* PREFIX_0F16 */
3170 {
3171 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3172 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3173 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3174 },
3175
3176 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3177 {
3178 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3179 { "nopQ", { Ev }, 0 },
3180 { "nopQ", { Ev }, 0 },
3181 { "nopQ", { Ev }, 0 },
3182 },
3183
3184 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3185 {
3186 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3187 { "nopQ", { Ev }, 0 },
3188 { "nopQ", { Ev }, 0 },
3189 { "nopQ", { Ev }, 0 },
3190 },
3191
3192 /* PREFIX_0F1A */
3193 {
3194 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3195 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3196 { "bndmov", { Gbnd, Ebnd }, 0 },
3197 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3198 },
3199
3200 /* PREFIX_0F1B */
3201 {
3202 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3203 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3204 { "bndmov", { EbndS, Gbnd }, 0 },
3205 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3206 },
3207
3208 /* PREFIX_0F1C */
3209 {
3210 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3211 { "nopQ", { Ev }, PREFIX_IGNORED },
3212 { "nopQ", { Ev }, 0 },
3213 { "nopQ", { Ev }, PREFIX_IGNORED },
3214 },
3215
3216 /* PREFIX_0F1E */
3217 {
3218 { "nopQ", { Ev }, 0 },
3219 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3220 { "nopQ", { Ev }, 0 },
3221 { NULL, { XX }, PREFIX_IGNORED },
3222 },
3223
3224 /* PREFIX_0F2A */
3225 {
3226 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3227 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3228 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3229 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3230 },
3231
3232 /* PREFIX_0F2B */
3233 {
3234 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3235 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3236 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3237 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3238 },
3239
3240 /* PREFIX_0F2C */
3241 {
3242 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3243 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3244 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3245 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3246 },
3247
3248 /* PREFIX_0F2D */
3249 {
3250 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3251 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3252 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3253 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3254 },
3255
3256 /* PREFIX_0F2E */
3257 {
3258 { "ucomiss",{ XM, EXd }, 0 },
3259 { Bad_Opcode },
3260 { "ucomisd",{ XM, EXq }, 0 },
3261 },
3262
3263 /* PREFIX_0F2F */
3264 {
3265 { "comiss", { XM, EXd }, 0 },
3266 { Bad_Opcode },
3267 { "comisd", { XM, EXq }, 0 },
3268 },
3269
3270 /* PREFIX_0F51 */
3271 {
3272 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3273 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3274 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3275 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3276 },
3277
3278 /* PREFIX_0F52 */
3279 {
3280 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3281 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3282 },
3283
3284 /* PREFIX_0F53 */
3285 {
3286 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3287 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3288 },
3289
3290 /* PREFIX_0F58 */
3291 {
3292 { "addps", { XM, EXx }, PREFIX_OPCODE },
3293 { "addss", { XM, EXd }, PREFIX_OPCODE },
3294 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3295 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3296 },
3297
3298 /* PREFIX_0F59 */
3299 {
3300 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3301 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3302 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3303 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3304 },
3305
3306 /* PREFIX_0F5A */
3307 {
3308 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3309 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3310 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3311 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3312 },
3313
3314 /* PREFIX_0F5B */
3315 {
3316 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3317 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3318 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3319 },
3320
3321 /* PREFIX_0F5C */
3322 {
3323 { "subps", { XM, EXx }, PREFIX_OPCODE },
3324 { "subss", { XM, EXd }, PREFIX_OPCODE },
3325 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3326 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3327 },
3328
3329 /* PREFIX_0F5D */
3330 {
3331 { "minps", { XM, EXx }, PREFIX_OPCODE },
3332 { "minss", { XM, EXd }, PREFIX_OPCODE },
3333 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3334 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3335 },
3336
3337 /* PREFIX_0F5E */
3338 {
3339 { "divps", { XM, EXx }, PREFIX_OPCODE },
3340 { "divss", { XM, EXd }, PREFIX_OPCODE },
3341 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3342 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3343 },
3344
3345 /* PREFIX_0F5F */
3346 {
3347 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3348 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3349 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3350 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3351 },
3352
3353 /* PREFIX_0F60 */
3354 {
3355 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3356 { Bad_Opcode },
3357 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3358 },
3359
3360 /* PREFIX_0F61 */
3361 {
3362 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3363 { Bad_Opcode },
3364 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3365 },
3366
3367 /* PREFIX_0F62 */
3368 {
3369 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3370 { Bad_Opcode },
3371 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3372 },
3373
3374 /* PREFIX_0F6F */
3375 {
3376 { "movq", { MX, EM }, PREFIX_OPCODE },
3377 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3378 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3379 },
3380
3381 /* PREFIX_0F70 */
3382 {
3383 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3384 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3385 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3386 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3387 },
3388
3389 /* PREFIX_0F78 */
3390 {
3391 {"vmread", { Em, Gm }, 0 },
3392 { Bad_Opcode },
3393 {"extrq", { XS, Ib, Ib }, 0 },
3394 {"insertq", { XM, XS, Ib, Ib }, 0 },
3395 },
3396
3397 /* PREFIX_0F79 */
3398 {
3399 {"vmwrite", { Gm, Em }, 0 },
3400 { Bad_Opcode },
3401 {"extrq", { XM, XS }, 0 },
3402 {"insertq", { XM, XS }, 0 },
3403 },
3404
3405 /* PREFIX_0F7C */
3406 {
3407 { Bad_Opcode },
3408 { Bad_Opcode },
3409 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3410 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3411 },
3412
3413 /* PREFIX_0F7D */
3414 {
3415 { Bad_Opcode },
3416 { Bad_Opcode },
3417 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3418 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3419 },
3420
3421 /* PREFIX_0F7E */
3422 {
3423 { "movK", { Edq, MX }, PREFIX_OPCODE },
3424 { "movq", { XM, EXq }, PREFIX_OPCODE },
3425 { "movK", { Edq, XM }, PREFIX_OPCODE },
3426 },
3427
3428 /* PREFIX_0F7F */
3429 {
3430 { "movq", { EMS, MX }, PREFIX_OPCODE },
3431 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3432 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3433 },
3434
3435 /* PREFIX_0FAE_REG_0_MOD_3 */
3436 {
3437 { Bad_Opcode },
3438 { "rdfsbase", { Ev }, 0 },
3439 },
3440
3441 /* PREFIX_0FAE_REG_1_MOD_3 */
3442 {
3443 { Bad_Opcode },
3444 { "rdgsbase", { Ev }, 0 },
3445 },
3446
3447 /* PREFIX_0FAE_REG_2_MOD_3 */
3448 {
3449 { Bad_Opcode },
3450 { "wrfsbase", { Ev }, 0 },
3451 },
3452
3453 /* PREFIX_0FAE_REG_3_MOD_3 */
3454 {
3455 { Bad_Opcode },
3456 { "wrgsbase", { Ev }, 0 },
3457 },
3458
3459 /* PREFIX_0FAE_REG_4_MOD_0 */
3460 {
3461 { "xsave", { FXSAVE }, 0 },
3462 { "ptwrite{%LQ|}", { Edq }, 0 },
3463 },
3464
3465 /* PREFIX_0FAE_REG_4_MOD_3 */
3466 {
3467 { Bad_Opcode },
3468 { "ptwrite{%LQ|}", { Edq }, 0 },
3469 },
3470
3471 /* PREFIX_0FAE_REG_5_MOD_3 */
3472 {
3473 { "lfence", { Skip_MODRM }, 0 },
3474 { "incsspK", { Edq }, PREFIX_OPCODE },
3475 },
3476
3477 /* PREFIX_0FAE_REG_6_MOD_0 */
3478 {
3479 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3480 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3481 { "clwb", { Mb }, PREFIX_OPCODE },
3482 },
3483
3484 /* PREFIX_0FAE_REG_6_MOD_3 */
3485 {
3486 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3487 { "umonitor", { Eva }, PREFIX_OPCODE },
3488 { "tpause", { Edq }, PREFIX_OPCODE },
3489 { "umwait", { Edq }, PREFIX_OPCODE },
3490 },
3491
3492 /* PREFIX_0FAE_REG_7_MOD_0 */
3493 {
3494 { "clflush", { Mb }, 0 },
3495 { Bad_Opcode },
3496 { "clflushopt", { Mb }, 0 },
3497 },
3498
3499 /* PREFIX_0FB8 */
3500 {
3501 { Bad_Opcode },
3502 { "popcntS", { Gv, Ev }, 0 },
3503 },
3504
3505 /* PREFIX_0FBC */
3506 {
3507 { "bsfS", { Gv, Ev }, 0 },
3508 { "tzcntS", { Gv, Ev }, 0 },
3509 { "bsfS", { Gv, Ev }, 0 },
3510 },
3511
3512 /* PREFIX_0FBD */
3513 {
3514 { "bsrS", { Gv, Ev }, 0 },
3515 { "lzcntS", { Gv, Ev }, 0 },
3516 { "bsrS", { Gv, Ev }, 0 },
3517 },
3518
3519 /* PREFIX_0FC2 */
3520 {
3521 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3522 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3523 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3524 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3525 },
3526
3527 /* PREFIX_0FC7_REG_6_MOD_0 */
3528 {
3529 { "vmptrld",{ Mq }, 0 },
3530 { "vmxon", { Mq }, 0 },
3531 { "vmclear",{ Mq }, 0 },
3532 },
3533
3534 /* PREFIX_0FC7_REG_6_MOD_3 */
3535 {
3536 { "rdrand", { Ev }, 0 },
3537 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3538 { "rdrand", { Ev }, 0 }
3539 },
3540
3541 /* PREFIX_0FC7_REG_7_MOD_3 */
3542 {
3543 { "rdseed", { Ev }, 0 },
3544 { "rdpid", { Em }, 0 },
3545 { "rdseed", { Ev }, 0 },
3546 },
3547
3548 /* PREFIX_0FD0 */
3549 {
3550 { Bad_Opcode },
3551 { Bad_Opcode },
3552 { "addsubpd", { XM, EXx }, 0 },
3553 { "addsubps", { XM, EXx }, 0 },
3554 },
3555
3556 /* PREFIX_0FD6 */
3557 {
3558 { Bad_Opcode },
3559 { "movq2dq",{ XM, MS }, 0 },
3560 { "movq", { EXqS, XM }, 0 },
3561 { "movdq2q",{ MX, XS }, 0 },
3562 },
3563
3564 /* PREFIX_0FE6 */
3565 {
3566 { Bad_Opcode },
3567 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3568 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3569 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3570 },
3571
3572 /* PREFIX_0FE7 */
3573 {
3574 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3575 { Bad_Opcode },
3576 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3577 },
3578
3579 /* PREFIX_0FF0 */
3580 {
3581 { Bad_Opcode },
3582 { Bad_Opcode },
3583 { Bad_Opcode },
3584 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3585 },
3586
3587 /* PREFIX_0FF7 */
3588 {
3589 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3590 { Bad_Opcode },
3591 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3592 },
3593
3594 /* PREFIX_0F38D8 */
3595 {
3596 { Bad_Opcode },
3597 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3598 },
3599
3600 /* PREFIX_0F38DC */
3601 {
3602 { Bad_Opcode },
3603 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3604 { "aesenc", { XM, EXx }, 0 },
3605 },
3606
3607 /* PREFIX_0F38DD */
3608 {
3609 { Bad_Opcode },
3610 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3611 { "aesenclast", { XM, EXx }, 0 },
3612 },
3613
3614 /* PREFIX_0F38DE */
3615 {
3616 { Bad_Opcode },
3617 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3618 { "aesdec", { XM, EXx }, 0 },
3619 },
3620
3621 /* PREFIX_0F38DF */
3622 {
3623 { Bad_Opcode },
3624 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3625 { "aesdeclast", { XM, EXx }, 0 },
3626 },
3627
3628 /* PREFIX_0F38F0 */
3629 {
3630 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3631 { Bad_Opcode },
3632 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3633 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3634 },
3635
3636 /* PREFIX_0F38F1 */
3637 {
3638 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3639 { Bad_Opcode },
3640 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3641 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3642 },
3643
3644 /* PREFIX_0F38F6 */
3645 {
3646 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3647 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3648 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3649 { Bad_Opcode },
3650 },
3651
3652 /* PREFIX_0F38F8 */
3653 {
3654 { Bad_Opcode },
3655 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3656 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3657 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3658 },
3659 /* PREFIX_0F38FA */
3660 {
3661 { Bad_Opcode },
3662 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3663 },
3664
3665 /* PREFIX_0F38FB */
3666 {
3667 { Bad_Opcode },
3668 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3669 },
3670
3671 /* PREFIX_0F38FC */
3672 {
3673 { "aadd", { Mdq, Gdq }, 0 },
3674 { "axor", { Mdq, Gdq }, 0 },
3675 { "aand", { Mdq, Gdq }, 0 },
3676 { "aor", { Mdq, Gdq }, 0 },
3677 },
3678
3679 /* PREFIX_0F3A0F */
3680 {
3681 { Bad_Opcode },
3682 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3683 },
3684
3685 /* PREFIX_VEX_0F10 */
3686 {
3687 { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
3688 { "%XEvmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3689 { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
3690 { "%XEvmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3691 },
3692
3693 /* PREFIX_VEX_0F11 */
3694 {
3695 { "%XEvmovupX", { EXxS, XM }, 0 },
3696 { "%XEvmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3697 { "%XEvmovupX", { EXxS, XM }, 0 },
3698 { "%XEvmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3699 },
3700
3701 /* PREFIX_VEX_0F12 */
3702 {
3703 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3704 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3705 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3706 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3707 },
3708
3709 /* PREFIX_VEX_0F16 */
3710 {
3711 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3712 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3713 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3714 },
3715
3716 /* PREFIX_VEX_0F2A */
3717 {
3718 { Bad_Opcode },
3719 { "%XEvcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3720 { Bad_Opcode },
3721 { "%XEvcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3722 },
3723
3724 /* PREFIX_VEX_0F2C */
3725 {
3726 { Bad_Opcode },
3727 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3728 { Bad_Opcode },
3729 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3730 },
3731
3732 /* PREFIX_VEX_0F2D */
3733 {
3734 { Bad_Opcode },
3735 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3736 { Bad_Opcode },
3737 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3738 },
3739
3740 /* PREFIX_VEX_0F2E */
3741 {
3742 { "%XEvucomisX", { XMScalar, EXd, EXxEVexS }, 0 },
3743 { Bad_Opcode },
3744 { "%XEvucomisX", { XMScalar, EXq, EXxEVexS }, 0 },
3745 },
3746
3747 /* PREFIX_VEX_0F2F */
3748 {
3749 { "%XEvcomisX", { XMScalar, EXd, EXxEVexS }, 0 },
3750 { Bad_Opcode },
3751 { "%XEvcomisX", { XMScalar, EXq, EXxEVexS }, 0 },
3752 },
3753
3754 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3755 {
3756 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3757 { Bad_Opcode },
3758 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3759 },
3760
3761 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3762 {
3763 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3764 { Bad_Opcode },
3765 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3766 },
3767
3768 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3769 {
3770 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3771 { Bad_Opcode },
3772 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3773 },
3774
3775 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3776 {
3777 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3778 { Bad_Opcode },
3779 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3780 },
3781
3782 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3783 {
3784 { "knotw", { MaskG, MaskE }, 0 },
3785 { Bad_Opcode },
3786 { "knotb", { MaskG, MaskE }, 0 },
3787 },
3788
3789 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3790 {
3791 { "knotq", { MaskG, MaskE }, 0 },
3792 { Bad_Opcode },
3793 { "knotd", { MaskG, MaskE }, 0 },
3794 },
3795
3796 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3797 {
3798 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3799 { Bad_Opcode },
3800 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3801 },
3802
3803 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3804 {
3805 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3806 { Bad_Opcode },
3807 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3808 },
3809
3810 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3811 {
3812 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3813 { Bad_Opcode },
3814 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3815 },
3816
3817 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3818 {
3819 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3820 { Bad_Opcode },
3821 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3822 },
3823
3824 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3825 {
3826 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3827 { Bad_Opcode },
3828 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3829 },
3830
3831 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3832 {
3833 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3834 { Bad_Opcode },
3835 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3836 },
3837
3838 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3839 {
3840 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3841 { Bad_Opcode },
3842 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3843 },
3844
3845 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3846 {
3847 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3848 { Bad_Opcode },
3849 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3850 },
3851
3852 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3853 {
3854 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3855 { Bad_Opcode },
3856 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3857 },
3858
3859 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3860 {
3861 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3862 },
3863
3864 /* PREFIX_VEX_0F51 */
3865 {
3866 { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3867 { "%XEvsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3868 { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3869 { "%XEvsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F52 */
3873 {
3874 { "vrsqrtps", { XM, EXx }, 0 },
3875 { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3876 },
3877
3878 /* PREFIX_VEX_0F53 */
3879 {
3880 { "vrcpps", { XM, EXx }, 0 },
3881 { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3882 },
3883
3884 /* PREFIX_VEX_0F58 */
3885 {
3886 { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3887 { "%XEvadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3888 { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3889 { "%XEvadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3890 },
3891
3892 /* PREFIX_VEX_0F59 */
3893 {
3894 { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3895 { "%XEvmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3896 { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3897 { "%XEvmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3898 },
3899
3900 /* PREFIX_VEX_0F5A */
3901 {
3902 { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3903 { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3904 { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3905 { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3906 },
3907
3908 /* PREFIX_VEX_0F5B */
3909 {
3910 { "vcvtdq2ps", { XM, EXx }, 0 },
3911 { "vcvttps2dq", { XM, EXx }, 0 },
3912 { "vcvtps2dq", { XM, EXx }, 0 },
3913 },
3914
3915 /* PREFIX_VEX_0F5C */
3916 {
3917 { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3918 { "%XEvsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3919 { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3920 { "%XEvsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3921 },
3922
3923 /* PREFIX_VEX_0F5D */
3924 {
3925 { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3926 { "%XEvmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3927 { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3928 { "%XEvmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3929 },
3930
3931 /* PREFIX_VEX_0F5E */
3932 {
3933 { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3934 { "%XEvdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3935 { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3936 { "%XEvdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3937 },
3938
3939 /* PREFIX_VEX_0F5F */
3940 {
3941 { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3942 { "%XEvmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3943 { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3944 { "%XEvmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3945 },
3946
3947 /* PREFIX_VEX_0F6F */
3948 {
3949 { Bad_Opcode },
3950 { "vmovdqu", { XM, EXx }, 0 },
3951 { "vmovdqa", { XM, EXx }, 0 },
3952 },
3953
3954 /* PREFIX_VEX_0F70 */
3955 {
3956 { Bad_Opcode },
3957 { "vpshufhw", { XM, EXx, Ib }, 0 },
3958 { "vpshufd", { XM, EXx, Ib }, 0 },
3959 { "vpshuflw", { XM, EXx, Ib }, 0 },
3960 },
3961
3962 /* PREFIX_VEX_0F7C */
3963 {
3964 { Bad_Opcode },
3965 { Bad_Opcode },
3966 { "vhaddpd", { XM, Vex, EXx }, 0 },
3967 { "vhaddps", { XM, Vex, EXx }, 0 },
3968 },
3969
3970 /* PREFIX_VEX_0F7D */
3971 {
3972 { Bad_Opcode },
3973 { Bad_Opcode },
3974 { "vhsubpd", { XM, Vex, EXx }, 0 },
3975 { "vhsubps", { XM, Vex, EXx }, 0 },
3976 },
3977
3978 /* PREFIX_VEX_0F7E */
3979 {
3980 { Bad_Opcode },
3981 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3982 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3983 },
3984
3985 /* PREFIX_VEX_0F7F */
3986 {
3987 { Bad_Opcode },
3988 { "vmovdqu", { EXxS, XM }, 0 },
3989 { "vmovdqa", { EXxS, XM }, 0 },
3990 },
3991
3992 /* PREFIX_VEX_0F90_L_0_W_0 */
3993 {
3994 { "kmovw", { MaskG, MaskE }, 0 },
3995 { Bad_Opcode },
3996 { "kmovb", { MaskG, MaskBDE }, 0 },
3997 },
3998
3999 /* PREFIX_VEX_0F90_L_0_W_1 */
4000 {
4001 { "kmovq", { MaskG, MaskE }, 0 },
4002 { Bad_Opcode },
4003 { "kmovd", { MaskG, MaskBDE }, 0 },
4004 },
4005
4006 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
4007 {
4008 { "kmovw", { Ew, MaskG }, 0 },
4009 { Bad_Opcode },
4010 { "kmovb", { Eb, MaskG }, 0 },
4011 },
4012
4013 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
4014 {
4015 { "kmovq", { Eq, MaskG }, 0 },
4016 { Bad_Opcode },
4017 { "kmovd", { Ed, MaskG }, 0 },
4018 },
4019
4020 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
4021 {
4022 { "kmovw", { MaskG, Edq }, 0 },
4023 { Bad_Opcode },
4024 { "kmovb", { MaskG, Edq }, 0 },
4025 { "kmovd", { MaskG, Edq }, 0 },
4026 },
4027
4028 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
4029 {
4030 { Bad_Opcode },
4031 { Bad_Opcode },
4032 { Bad_Opcode },
4033 { "kmovK", { MaskG, Edq }, 0 },
4034 },
4035
4036 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
4037 {
4038 { "kmovw", { Gdq, MaskE }, 0 },
4039 { Bad_Opcode },
4040 { "kmovb", { Gdq, MaskE }, 0 },
4041 { "kmovd", { Gdq, MaskE }, 0 },
4042 },
4043
4044 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4045 {
4046 { Bad_Opcode },
4047 { Bad_Opcode },
4048 { Bad_Opcode },
4049 { "kmovK", { Gdq, MaskE }, 0 },
4050 },
4051
4052 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4053 {
4054 { "kortestw", { MaskG, MaskE }, 0 },
4055 { Bad_Opcode },
4056 { "kortestb", { MaskG, MaskE }, 0 },
4057 },
4058
4059 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4060 {
4061 { "kortestq", { MaskG, MaskE }, 0 },
4062 { Bad_Opcode },
4063 { "kortestd", { MaskG, MaskE }, 0 },
4064 },
4065
4066 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4067 {
4068 { "ktestw", { MaskG, MaskE }, 0 },
4069 { Bad_Opcode },
4070 { "ktestb", { MaskG, MaskE }, 0 },
4071 },
4072
4073 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4074 {
4075 { "ktestq", { MaskG, MaskE }, 0 },
4076 { Bad_Opcode },
4077 { "ktestd", { MaskG, MaskE }, 0 },
4078 },
4079
4080 /* PREFIX_VEX_0FC2 */
4081 {
4082 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4083 { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
4084 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4085 { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
4086 },
4087
4088 /* PREFIX_VEX_0FD0 */
4089 {
4090 { Bad_Opcode },
4091 { Bad_Opcode },
4092 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4093 { "vaddsubps", { XM, Vex, EXx }, 0 },
4094 },
4095
4096 /* PREFIX_VEX_0FE6 */
4097 {
4098 { Bad_Opcode },
4099 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4100 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4101 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4102 },
4103
4104 /* PREFIX_VEX_0FF0 */
4105 {
4106 { Bad_Opcode },
4107 { Bad_Opcode },
4108 { Bad_Opcode },
4109 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4110 },
4111
4112 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
4113 {
4114 { "ldtilecfg", { M }, 0 },
4115 { Bad_Opcode },
4116 { "sttilecfg", { M }, 0 },
4117 },
4118
4119 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
4120 {
4121 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
4122 { Bad_Opcode },
4123 { Bad_Opcode },
4124 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
4125 },
4126
4127 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0 */
4128 {
4129 { Bad_Opcode },
4130 { "tilestored", { MVexSIBMEM, TMM }, 0 },
4131 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
4132 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
4133 },
4134
4135 /* PREFIX_VEX_0F3850_W_0 */
4136 {
4137 { "vpdpbuud", { XM, Vex, EXx }, 0 },
4138 { "vpdpbsud", { XM, Vex, EXx }, 0 },
4139 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
4140 { "vpdpbssd", { XM, Vex, EXx }, 0 },
4141 },
4142
4143 /* PREFIX_VEX_0F3851_W_0 */
4144 {
4145 { "vpdpbuuds", { XM, Vex, EXx }, 0 },
4146 { "vpdpbsuds", { XM, Vex, EXx }, 0 },
4147 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4148 { "vpdpbssds", { XM, Vex, EXx }, 0 },
4149 },
4150 /* PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0 */
4151 {
4152 { Bad_Opcode },
4153 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
4154 { Bad_Opcode },
4155 { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
4156 },
4157
4158 /* PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0 */
4159 {
4160 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
4161 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
4162 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
4163 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
4164 },
4165
4166 /* PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0 */
4167 {
4168 { "tcmmrlfp16ps", { TMM, EXtmm, VexTmm }, 0 },
4169 { Bad_Opcode },
4170 { "tcmmimfp16ps", { TMM, EXtmm, VexTmm }, 0 },
4171 },
4172
4173 /* PREFIX_VEX_0F3872 */
4174 {
4175 { Bad_Opcode },
4176 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4177 },
4178
4179 /* PREFIX_VEX_0F38B0_W_0 */
4180 {
4181 { "vcvtneoph2ps", { XM, Mx }, 0 },
4182 { "vcvtneebf162ps", { XM, Mx }, 0 },
4183 { "vcvtneeph2ps", { XM, Mx }, 0 },
4184 { "vcvtneobf162ps", { XM, Mx }, 0 },
4185 },
4186
4187 /* PREFIX_VEX_0F38B1_W_0 */
4188 {
4189 { Bad_Opcode },
4190 { "vbcstnebf162ps", { XM, Mw }, 0 },
4191 { "vbcstnesh2ps", { XM, Mw }, 0 },
4192 },
4193
4194 /* PREFIX_VEX_0F38F5_L_0 */
4195 {
4196 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4197 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4198 { Bad_Opcode },
4199 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4200 },
4201
4202 /* PREFIX_VEX_0F38F6_L_0 */
4203 {
4204 { Bad_Opcode },
4205 { Bad_Opcode },
4206 { Bad_Opcode },
4207 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4208 },
4209
4210 /* PREFIX_VEX_0F38F7_L_0 */
4211 {
4212 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4213 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4214 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4215 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4216 },
4217
4218 /* PREFIX_VEX_0F3AF0_L_0 */
4219 {
4220 { Bad_Opcode },
4221 { Bad_Opcode },
4222 { Bad_Opcode },
4223 { "rorxS", { Gdq, Edq, Ib }, 0 },
4224 },
4225
4226 #include "i386-dis-evex-prefix.h"
4227 };
4228
4229 static const struct dis386 x86_64_table[][2] = {
4230 /* X86_64_06 */
4231 {
4232 { "pushP", { es }, 0 },
4233 },
4234
4235 /* X86_64_07 */
4236 {
4237 { "popP", { es }, 0 },
4238 },
4239
4240 /* X86_64_0E */
4241 {
4242 { "pushP", { cs }, 0 },
4243 },
4244
4245 /* X86_64_16 */
4246 {
4247 { "pushP", { ss }, 0 },
4248 },
4249
4250 /* X86_64_17 */
4251 {
4252 { "popP", { ss }, 0 },
4253 },
4254
4255 /* X86_64_1E */
4256 {
4257 { "pushP", { ds }, 0 },
4258 },
4259
4260 /* X86_64_1F */
4261 {
4262 { "popP", { ds }, 0 },
4263 },
4264
4265 /* X86_64_27 */
4266 {
4267 { "daa", { XX }, 0 },
4268 },
4269
4270 /* X86_64_2F */
4271 {
4272 { "das", { XX }, 0 },
4273 },
4274
4275 /* X86_64_37 */
4276 {
4277 { "aaa", { XX }, 0 },
4278 },
4279
4280 /* X86_64_3F */
4281 {
4282 { "aas", { XX }, 0 },
4283 },
4284
4285 /* X86_64_60 */
4286 {
4287 { "pushaP", { XX }, 0 },
4288 },
4289
4290 /* X86_64_61 */
4291 {
4292 { "popaP", { XX }, 0 },
4293 },
4294
4295 /* X86_64_62 */
4296 {
4297 { MOD_TABLE (MOD_62_32BIT) },
4298 { EVEX_TABLE (EVEX_0F) },
4299 },
4300
4301 /* X86_64_63 */
4302 {
4303 { "arpl", { Ew, Gw }, 0 },
4304 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4305 },
4306
4307 /* X86_64_6D */
4308 {
4309 { "ins{R|}", { Yzr, indirDX }, 0 },
4310 { "ins{G|}", { Yzr, indirDX }, 0 },
4311 },
4312
4313 /* X86_64_6F */
4314 {
4315 { "outs{R|}", { indirDXr, Xz }, 0 },
4316 { "outs{G|}", { indirDXr, Xz }, 0 },
4317 },
4318
4319 /* X86_64_82 */
4320 {
4321 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4322 { REG_TABLE (REG_80) },
4323 },
4324
4325 /* X86_64_9A */
4326 {
4327 { "{l|}call{P|}", { Ap }, 0 },
4328 },
4329
4330 /* X86_64_C2 */
4331 {
4332 { "retP", { Iw, BND }, 0 },
4333 { "ret@", { Iw, BND }, 0 },
4334 },
4335
4336 /* X86_64_C3 */
4337 {
4338 { "retP", { BND }, 0 },
4339 { "ret@", { BND }, 0 },
4340 },
4341
4342 /* X86_64_C4 */
4343 {
4344 { MOD_TABLE (MOD_C4_32BIT) },
4345 { VEX_C4_TABLE (VEX_0F) },
4346 },
4347
4348 /* X86_64_C5 */
4349 {
4350 { MOD_TABLE (MOD_C5_32BIT) },
4351 { VEX_C5_TABLE (VEX_0F) },
4352 },
4353
4354 /* X86_64_CE */
4355 {
4356 { "into", { XX }, 0 },
4357 },
4358
4359 /* X86_64_D4 */
4360 {
4361 { "aam", { Ib }, 0 },
4362 },
4363
4364 /* X86_64_D5 */
4365 {
4366 { "aad", { Ib }, 0 },
4367 },
4368
4369 /* X86_64_E8 */
4370 {
4371 { "callP", { Jv, BND }, 0 },
4372 { "call@", { Jv, BND }, 0 }
4373 },
4374
4375 /* X86_64_E9 */
4376 {
4377 { "jmpP", { Jv, BND }, 0 },
4378 { "jmp@", { Jv, BND }, 0 }
4379 },
4380
4381 /* X86_64_EA */
4382 {
4383 { "{l|}jmp{P|}", { Ap }, 0 },
4384 },
4385
4386 /* X86_64_0F00_REG_6 */
4387 {
4388 { Bad_Opcode },
4389 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4390 },
4391
4392 /* X86_64_0F01_REG_0 */
4393 {
4394 { "sgdt{Q|Q}", { M }, 0 },
4395 { "sgdt", { M }, 0 },
4396 },
4397
4398 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4399 {
4400 { Bad_Opcode },
4401 { "wrmsrlist", { Skip_MODRM }, 0 },
4402 },
4403
4404 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4405 {
4406 { Bad_Opcode },
4407 { "rdmsrlist", { Skip_MODRM }, 0 },
4408 },
4409
4410 /* X86_64_0F01_REG_1 */
4411 {
4412 { "sidt{Q|Q}", { M }, 0 },
4413 { "sidt", { M }, 0 },
4414 },
4415
4416 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4417 {
4418 { Bad_Opcode },
4419 { "eretu", { Skip_MODRM }, 0 },
4420 },
4421
4422 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4423 {
4424 { Bad_Opcode },
4425 { "erets", { Skip_MODRM }, 0 },
4426 },
4427
4428 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4429 {
4430 { Bad_Opcode },
4431 { "seamret", { Skip_MODRM }, 0 },
4432 },
4433
4434 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4435 {
4436 { Bad_Opcode },
4437 { "seamops", { Skip_MODRM }, 0 },
4438 },
4439
4440 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4441 {
4442 { Bad_Opcode },
4443 { "seamcall", { Skip_MODRM }, 0 },
4444 },
4445
4446 /* X86_64_0F01_REG_2 */
4447 {
4448 { "lgdt{Q|Q}", { M }, 0 },
4449 { "lgdt", { M }, 0 },
4450 },
4451
4452 /* X86_64_0F01_REG_3 */
4453 {
4454 { "lidt{Q|Q}", { M }, 0 },
4455 { "lidt", { M }, 0 },
4456 },
4457
4458 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4459 {
4460 { Bad_Opcode },
4461 { "uiret", { Skip_MODRM }, 0 },
4462 },
4463
4464 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4465 {
4466 { Bad_Opcode },
4467 { "testui", { Skip_MODRM }, 0 },
4468 },
4469
4470 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4471 {
4472 { Bad_Opcode },
4473 { "clui", { Skip_MODRM }, 0 },
4474 },
4475
4476 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4477 {
4478 { Bad_Opcode },
4479 { "stui", { Skip_MODRM }, 0 },
4480 },
4481
4482 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4483 {
4484 { Bad_Opcode },
4485 { "rmpquery", { Skip_MODRM }, 0 },
4486 },
4487
4488 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4489 {
4490 { Bad_Opcode },
4491 { "rmpadjust", { Skip_MODRM }, 0 },
4492 },
4493
4494 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4495 {
4496 { Bad_Opcode },
4497 { "rmpupdate", { Skip_MODRM }, 0 },
4498 },
4499
4500 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4501 {
4502 { Bad_Opcode },
4503 { "psmash", { Skip_MODRM }, 0 },
4504 },
4505
4506 /* X86_64_0F18_REG_6_MOD_0 */
4507 {
4508 { "nopQ", { Ev }, 0 },
4509 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4510 },
4511
4512 /* X86_64_0F18_REG_7_MOD_0 */
4513 {
4514 { "nopQ", { Ev }, 0 },
4515 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4516 },
4517
4518 {
4519 /* X86_64_0F24 */
4520 { "movZ", { Em, Td }, 0 },
4521 },
4522
4523 {
4524 /* X86_64_0F26 */
4525 { "movZ", { Td, Em }, 0 },
4526 },
4527
4528 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4529 {
4530 { Bad_Opcode },
4531 { "senduipi", { Eq }, 0 },
4532 },
4533
4534 /* X86_64_VEX_0F3849 */
4535 {
4536 { Bad_Opcode },
4537 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4538 },
4539
4540 /* X86_64_VEX_0F384B */
4541 {
4542 { Bad_Opcode },
4543 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4544 },
4545
4546 /* X86_64_VEX_0F385C */
4547 {
4548 { Bad_Opcode },
4549 { MOD_TABLE (MOD_VEX_0F385C_X86_64) },
4550 },
4551
4552 /* X86_64_VEX_0F385E */
4553 {
4554 { Bad_Opcode },
4555 { MOD_TABLE (MOD_VEX_0F385E_X86_64) },
4556 },
4557
4558 /* X86_64_VEX_0F386C */
4559 {
4560 { Bad_Opcode },
4561 { MOD_TABLE (MOD_VEX_0F386C_X86_64) },
4562 },
4563
4564 /* X86_64_VEX_0F38E0 */
4565 {
4566 { Bad_Opcode },
4567 { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4568 },
4569
4570 /* X86_64_VEX_0F38E1 */
4571 {
4572 { Bad_Opcode },
4573 { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4574 },
4575
4576 /* X86_64_VEX_0F38E2 */
4577 {
4578 { Bad_Opcode },
4579 { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4580 },
4581
4582 /* X86_64_VEX_0F38E3 */
4583 {
4584 { Bad_Opcode },
4585 { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4586 },
4587
4588 /* X86_64_VEX_0F38E4 */
4589 {
4590 { Bad_Opcode },
4591 { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4592 },
4593
4594 /* X86_64_VEX_0F38E5 */
4595 {
4596 { Bad_Opcode },
4597 { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4598 },
4599
4600 /* X86_64_VEX_0F38E6 */
4601 {
4602 { Bad_Opcode },
4603 { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4604 },
4605
4606 /* X86_64_VEX_0F38E7 */
4607 {
4608 { Bad_Opcode },
4609 { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4610 },
4611
4612 /* X86_64_VEX_0F38E8 */
4613 {
4614 { Bad_Opcode },
4615 { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4616 },
4617
4618 /* X86_64_VEX_0F38E9 */
4619 {
4620 { Bad_Opcode },
4621 { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4622 },
4623
4624 /* X86_64_VEX_0F38EA */
4625 {
4626 { Bad_Opcode },
4627 { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4628 },
4629
4630 /* X86_64_VEX_0F38EB */
4631 {
4632 { Bad_Opcode },
4633 { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4634 },
4635
4636 /* X86_64_VEX_0F38EC */
4637 {
4638 { Bad_Opcode },
4639 { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4640 },
4641
4642 /* X86_64_VEX_0F38ED */
4643 {
4644 { Bad_Opcode },
4645 { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4646 },
4647
4648 /* X86_64_VEX_0F38EE */
4649 {
4650 { Bad_Opcode },
4651 { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4652 },
4653
4654 /* X86_64_VEX_0F38EF */
4655 {
4656 { Bad_Opcode },
4657 { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4658 },
4659 };
4660
4661 static const struct dis386 three_byte_table[][256] = {
4662
4663 /* THREE_BYTE_0F38 */
4664 {
4665 /* 00 */
4666 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4667 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4668 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4669 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4670 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4671 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4672 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4673 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4674 /* 08 */
4675 { "psignb", { MX, EM }, PREFIX_OPCODE },
4676 { "psignw", { MX, EM }, PREFIX_OPCODE },
4677 { "psignd", { MX, EM }, PREFIX_OPCODE },
4678 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 /* 10 */
4684 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4689 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4690 { Bad_Opcode },
4691 { "ptest", { XM, EXx }, PREFIX_DATA },
4692 /* 18 */
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4698 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4699 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4700 { Bad_Opcode },
4701 /* 20 */
4702 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4703 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4704 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4705 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4706 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4707 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 /* 28 */
4711 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4712 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4713 { MOD_TABLE (MOD_0F382A) },
4714 { "packusdw", { XM, EXx }, PREFIX_DATA },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 /* 30 */
4720 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4721 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4722 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4723 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4724 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4725 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4726 { Bad_Opcode },
4727 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4728 /* 38 */
4729 { "pminsb", { XM, EXx }, PREFIX_DATA },
4730 { "pminsd", { XM, EXx }, PREFIX_DATA },
4731 { "pminuw", { XM, EXx }, PREFIX_DATA },
4732 { "pminud", { XM, EXx }, PREFIX_DATA },
4733 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4734 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4735 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4736 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4737 /* 40 */
4738 { "pmulld", { XM, EXx }, PREFIX_DATA },
4739 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 /* 48 */
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 /* 50 */
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 /* 58 */
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 /* 60 */
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 /* 68 */
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 /* 70 */
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 /* 78 */
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 /* 80 */
4810 { "invept", { Gm, Mo }, PREFIX_DATA },
4811 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4812 { "invpcid", { Gm, M }, PREFIX_DATA },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 /* 88 */
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 /* 90 */
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 /* 98 */
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 /* a0 */
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 /* a8 */
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 /* b0 */
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 /* b8 */
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 /* c0 */
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 /* c8 */
4891 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4892 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4893 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4894 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4895 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4896 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4897 { Bad_Opcode },
4898 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4899 /* d0 */
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 /* d8 */
4909 { PREFIX_TABLE (PREFIX_0F38D8) },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { "aesimc", { XM, EXx }, PREFIX_DATA },
4913 { PREFIX_TABLE (PREFIX_0F38DC) },
4914 { PREFIX_TABLE (PREFIX_0F38DD) },
4915 { PREFIX_TABLE (PREFIX_0F38DE) },
4916 { PREFIX_TABLE (PREFIX_0F38DF) },
4917 /* e0 */
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 /* e8 */
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 /* f0 */
4936 { PREFIX_TABLE (PREFIX_0F38F0) },
4937 { PREFIX_TABLE (PREFIX_0F38F1) },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { MOD_TABLE (MOD_0F38F5) },
4942 { PREFIX_TABLE (PREFIX_0F38F6) },
4943 { Bad_Opcode },
4944 /* f8 */
4945 { PREFIX_TABLE (PREFIX_0F38F8) },
4946 { MOD_TABLE (MOD_0F38F9) },
4947 { PREFIX_TABLE (PREFIX_0F38FA) },
4948 { PREFIX_TABLE (PREFIX_0F38FB) },
4949 { PREFIX_TABLE (PREFIX_0F38FC) },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 },
4954 /* THREE_BYTE_0F3A */
4955 {
4956 /* 00 */
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 /* 08 */
4966 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4967 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4968 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4969 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4970 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4971 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4972 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4973 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4974 /* 10 */
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4980 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4981 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4982 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4983 /* 18 */
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 /* 20 */
4993 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4994 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4995 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 /* 28 */
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 /* 30 */
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 /* 38 */
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 /* 40 */
5029 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
5030 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
5031 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
5032 { Bad_Opcode },
5033 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 /* 48 */
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 /* 50 */
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 /* 58 */
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 /* 60 */
5065 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5066 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5067 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5068 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 /* 68 */
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 /* 70 */
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 /* 78 */
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 /* 80 */
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 /* 88 */
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 /* 90 */
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 /* 98 */
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 /* a0 */
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 /* a8 */
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 /* b0 */
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 /* b8 */
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 /* c0 */
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 /* c8 */
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5187 { Bad_Opcode },
5188 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5189 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5190 /* d0 */
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 /* d8 */
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5208 /* e0 */
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 /* e8 */
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 /* f0 */
5227 { PREFIX_TABLE (PREFIX_0F3A0F) },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 /* f8 */
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 },
5245 };
5246
5247 static const struct dis386 xop_table[][256] = {
5248 /* XOP_08 */
5249 {
5250 /* 00 */
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 /* 08 */
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 /* 10 */
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 /* 18 */
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 /* 20 */
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 /* 28 */
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 /* 30 */
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 /* 38 */
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* 40 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 /* 48 */
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 /* 50 */
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 /* 58 */
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 /* 60 */
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 /* 68 */
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 /* 70 */
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 /* 78 */
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 /* 80 */
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5401 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5402 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5403 /* 88 */
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5411 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5412 /* 90 */
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5419 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5420 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5421 /* 98 */
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5429 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5430 /* a0 */
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5434 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5438 { Bad_Opcode },
5439 /* a8 */
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 /* b0 */
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5456 { Bad_Opcode },
5457 /* b8 */
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 /* c0 */
5467 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5468 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5469 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5470 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 /* c8 */
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5481 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5482 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5483 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5484 /* d0 */
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 /* d8 */
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 /* e0 */
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 /* e8 */
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5517 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5518 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5519 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5520 /* f0 */
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 /* f8 */
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 },
5539 /* XOP_09 */
5540 {
5541 /* 00 */
5542 { Bad_Opcode },
5543 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5544 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 /* 08 */
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 /* 10 */
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { MOD_TABLE (MOD_XOP_09_12) },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* 18 */
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 /* 20 */
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 /* 28 */
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* 30 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* 38 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* 40 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* 48 */
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* 50 */
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 /* 58 */
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 /* 60 */
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 /* 68 */
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* 70 */
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* 78 */
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 /* 80 */
5686 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5687 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5688 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5689 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 /* 88 */
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* 90 */
5704 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5705 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5706 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5707 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5708 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5709 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5710 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5711 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5712 /* 98 */
5713 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5714 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5715 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5716 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* a0 */
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 /* a8 */
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 /* b0 */
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 /* b8 */
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 /* c0 */
5758 { Bad_Opcode },
5759 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5760 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5761 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5765 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5766 /* c8 */
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 /* d0 */
5776 { Bad_Opcode },
5777 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5778 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5779 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5783 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5784 /* d8 */
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 /* e0 */
5794 { Bad_Opcode },
5795 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5797 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 /* e8 */
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 /* f0 */
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 /* f8 */
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 },
5830 /* XOP_0A */
5831 {
5832 /* 00 */
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 /* 08 */
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 /* 10 */
5851 { "bextrS", { Gdq, Edq, Id }, 0 },
5852 { Bad_Opcode },
5853 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 /* 18 */
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 /* 20 */
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 /* 28 */
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 /* 30 */
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 /* 38 */
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 /* 40 */
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 /* 48 */
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 /* 50 */
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 /* 58 */
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 /* 60 */
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 /* 68 */
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 /* 70 */
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 /* 78 */
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 /* 80 */
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 /* 88 */
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 /* 90 */
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 /* 98 */
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 /* a0 */
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 /* a8 */
6022 { Bad_Opcode },
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 /* b0 */
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 /* b8 */
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 /* c0 */
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 /* c8 */
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 /* d0 */
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 /* d8 */
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 /* e0 */
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 /* e8 */
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 /* f0 */
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 /* f8 */
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 { Bad_Opcode },
6119 { Bad_Opcode },
6120 },
6121 };
6122
6123 static const struct dis386 vex_table[][256] = {
6124 /* VEX_0F */
6125 {
6126 /* 00 */
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 /* 08 */
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 { Bad_Opcode },
6144 /* 10 */
6145 { PREFIX_TABLE (PREFIX_VEX_0F10) },
6146 { PREFIX_TABLE (PREFIX_VEX_0F11) },
6147 { PREFIX_TABLE (PREFIX_VEX_0F12) },
6148 { MOD_TABLE (MOD_VEX_0F13) },
6149 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6150 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6151 { PREFIX_TABLE (PREFIX_VEX_0F16) },
6152 { MOD_TABLE (MOD_VEX_0F17) },
6153 /* 18 */
6154 { Bad_Opcode },
6155 { Bad_Opcode },
6156 { Bad_Opcode },
6157 { Bad_Opcode },
6158 { Bad_Opcode },
6159 { Bad_Opcode },
6160 { Bad_Opcode },
6161 { Bad_Opcode },
6162 /* 20 */
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 /* 28 */
6172 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
6173 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
6174 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6175 { MOD_TABLE (MOD_VEX_0F2B) },
6176 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6177 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6178 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
6179 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
6180 /* 30 */
6181 { Bad_Opcode },
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 { Bad_Opcode },
6189 /* 38 */
6190 { Bad_Opcode },
6191 { Bad_Opcode },
6192 { Bad_Opcode },
6193 { Bad_Opcode },
6194 { Bad_Opcode },
6195 { Bad_Opcode },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 /* 40 */
6199 { Bad_Opcode },
6200 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6201 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6202 { Bad_Opcode },
6203 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6204 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6205 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6206 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6207 /* 48 */
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6211 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 { Bad_Opcode },
6216 /* 50 */
6217 { MOD_TABLE (MOD_VEX_0F50) },
6218 { PREFIX_TABLE (PREFIX_VEX_0F51) },
6219 { PREFIX_TABLE (PREFIX_VEX_0F52) },
6220 { PREFIX_TABLE (PREFIX_VEX_0F53) },
6221 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6222 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6223 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6224 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6225 /* 58 */
6226 { PREFIX_TABLE (PREFIX_VEX_0F58) },
6227 { PREFIX_TABLE (PREFIX_VEX_0F59) },
6228 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6229 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6230 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6231 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6232 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6233 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6234 /* 60 */
6235 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6236 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6237 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6238 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6239 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6240 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6241 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6242 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6243 /* 68 */
6244 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6245 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6246 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6247 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6248 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6249 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6250 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6251 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6252 /* 70 */
6253 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6254 { MOD_TABLE (MOD_VEX_0F71) },
6255 { MOD_TABLE (MOD_VEX_0F72) },
6256 { MOD_TABLE (MOD_VEX_0F73) },
6257 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6258 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6259 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6260 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6261 /* 78 */
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6267 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6268 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6269 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6270 /* 80 */
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 /* 88 */
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 /* 90 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6290 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6291 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6292 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 /* 98 */
6298 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6299 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 /* a0 */
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 /* a8 */
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { REG_TABLE (REG_VEX_0FAE) },
6323 { Bad_Opcode },
6324 /* b0 */
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 /* b8 */
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 /* c0 */
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6346 { Bad_Opcode },
6347 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6348 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6349 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6350 { Bad_Opcode },
6351 /* c8 */
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { Bad_Opcode },
6359 { Bad_Opcode },
6360 /* d0 */
6361 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6362 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6363 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6364 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6365 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6367 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6368 { MOD_TABLE (MOD_VEX_0FD7) },
6369 /* d8 */
6370 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6371 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6372 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6373 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6374 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6375 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6376 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6377 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6378 /* e0 */
6379 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6380 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6381 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6382 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6383 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6384 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6385 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6386 { MOD_TABLE (MOD_VEX_0FE7) },
6387 /* e8 */
6388 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6389 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6390 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6391 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6392 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6393 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6394 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6395 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6396 /* f0 */
6397 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6398 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6399 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6400 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6401 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6402 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6403 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6404 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6405 /* f8 */
6406 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6407 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6408 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6409 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6410 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6411 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6412 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6413 { Bad_Opcode },
6414 },
6415 /* VEX_0F38 */
6416 {
6417 /* 00 */
6418 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6419 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6420 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6421 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6422 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6423 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6424 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6425 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6426 /* 08 */
6427 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6428 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6429 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6430 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6431 { VEX_W_TABLE (VEX_W_0F380C) },
6432 { VEX_W_TABLE (VEX_W_0F380D) },
6433 { VEX_W_TABLE (VEX_W_0F380E) },
6434 { VEX_W_TABLE (VEX_W_0F380F) },
6435 /* 10 */
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { VEX_W_TABLE (VEX_W_0F3813) },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6443 { "vptest", { XM, EXx }, PREFIX_DATA },
6444 /* 18 */
6445 { VEX_W_TABLE (VEX_W_0F3818) },
6446 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6447 { MOD_TABLE (MOD_VEX_0F381A) },
6448 { Bad_Opcode },
6449 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6450 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6451 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6452 { Bad_Opcode },
6453 /* 20 */
6454 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6455 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6456 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6457 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6458 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6459 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 /* 28 */
6463 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6464 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6465 { MOD_TABLE (MOD_VEX_0F382A) },
6466 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6467 { MOD_TABLE (MOD_VEX_0F382C) },
6468 { MOD_TABLE (MOD_VEX_0F382D) },
6469 { MOD_TABLE (MOD_VEX_0F382E) },
6470 { MOD_TABLE (MOD_VEX_0F382F) },
6471 /* 30 */
6472 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6473 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6474 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6475 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6476 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6477 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6478 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6479 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6480 /* 38 */
6481 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6482 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6483 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6484 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6485 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6486 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6487 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6488 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6489 /* 40 */
6490 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6491 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6496 { VEX_W_TABLE (VEX_W_0F3846) },
6497 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6498 /* 48 */
6499 { Bad_Opcode },
6500 { X86_64_TABLE (X86_64_VEX_0F3849) },
6501 { Bad_Opcode },
6502 { X86_64_TABLE (X86_64_VEX_0F384B) },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 /* 50 */
6508 { VEX_W_TABLE (VEX_W_0F3850) },
6509 { VEX_W_TABLE (VEX_W_0F3851) },
6510 { VEX_W_TABLE (VEX_W_0F3852) },
6511 { VEX_W_TABLE (VEX_W_0F3853) },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 /* 58 */
6517 { VEX_W_TABLE (VEX_W_0F3858) },
6518 { VEX_W_TABLE (VEX_W_0F3859) },
6519 { MOD_TABLE (MOD_VEX_0F385A) },
6520 { Bad_Opcode },
6521 { X86_64_TABLE (X86_64_VEX_0F385C) },
6522 { Bad_Opcode },
6523 { X86_64_TABLE (X86_64_VEX_0F385E) },
6524 { Bad_Opcode },
6525 /* 60 */
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 /* 68 */
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { X86_64_TABLE (X86_64_VEX_0F386C) },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 /* 70 */
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 /* 78 */
6553 { VEX_W_TABLE (VEX_W_0F3878) },
6554 { VEX_W_TABLE (VEX_W_0F3879) },
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { Bad_Opcode },
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { Bad_Opcode },
6561 /* 80 */
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 /* 88 */
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 { MOD_TABLE (MOD_VEX_0F388C) },
6576 { Bad_Opcode },
6577 { MOD_TABLE (MOD_VEX_0F388E) },
6578 { Bad_Opcode },
6579 /* 90 */
6580 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6581 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6582 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6583 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6587 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6588 /* 98 */
6589 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6590 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6591 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6592 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6593 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6594 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6595 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6596 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6597 /* a0 */
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6605 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6606 /* a8 */
6607 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6608 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6609 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6610 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6611 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6612 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6613 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6614 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6615 /* b0 */
6616 { VEX_W_TABLE (VEX_W_0F38B0) },
6617 { VEX_W_TABLE (VEX_W_0F38B1) },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { VEX_W_TABLE (VEX_W_0F38B4) },
6621 { VEX_W_TABLE (VEX_W_0F38B5) },
6622 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6623 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6624 /* b8 */
6625 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6626 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6627 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6628 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6629 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6630 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6631 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6632 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6633 /* c0 */
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 /* c8 */
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { VEX_W_TABLE (VEX_W_0F38CF) },
6651 /* d0 */
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 /* d8 */
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6665 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6666 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6667 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6668 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6669 /* e0 */
6670 { X86_64_TABLE (X86_64_VEX_0F38E0) },
6671 { X86_64_TABLE (X86_64_VEX_0F38E1) },
6672 { X86_64_TABLE (X86_64_VEX_0F38E2) },
6673 { X86_64_TABLE (X86_64_VEX_0F38E3) },
6674 { X86_64_TABLE (X86_64_VEX_0F38E4) },
6675 { X86_64_TABLE (X86_64_VEX_0F38E5) },
6676 { X86_64_TABLE (X86_64_VEX_0F38E6) },
6677 { X86_64_TABLE (X86_64_VEX_0F38E7) },
6678 /* e8 */
6679 { X86_64_TABLE (X86_64_VEX_0F38E8) },
6680 { X86_64_TABLE (X86_64_VEX_0F38E9) },
6681 { X86_64_TABLE (X86_64_VEX_0F38EA) },
6682 { X86_64_TABLE (X86_64_VEX_0F38EB) },
6683 { X86_64_TABLE (X86_64_VEX_0F38EC) },
6684 { X86_64_TABLE (X86_64_VEX_0F38ED) },
6685 { X86_64_TABLE (X86_64_VEX_0F38EE) },
6686 { X86_64_TABLE (X86_64_VEX_0F38EF) },
6687 /* f0 */
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6691 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6692 { Bad_Opcode },
6693 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6694 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6695 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6696 /* f8 */
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 },
6706 /* VEX_0F3A */
6707 {
6708 /* 00 */
6709 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6710 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6711 { VEX_W_TABLE (VEX_W_0F3A02) },
6712 { Bad_Opcode },
6713 { VEX_W_TABLE (VEX_W_0F3A04) },
6714 { VEX_W_TABLE (VEX_W_0F3A05) },
6715 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6716 { Bad_Opcode },
6717 /* 08 */
6718 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6719 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6720 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6721 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6722 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6723 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6724 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6725 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6726 /* 10 */
6727 { Bad_Opcode },
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6733 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6734 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6735 /* 18 */
6736 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6737 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { VEX_W_TABLE (VEX_W_0F3A1D) },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 /* 20 */
6745 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6746 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6747 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { Bad_Opcode },
6753 /* 28 */
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 /* 30 */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6765 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6766 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 /* 38 */
6772 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6773 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6774 { Bad_Opcode },
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 /* 40 */
6781 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6782 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6783 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6784 { Bad_Opcode },
6785 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6786 { Bad_Opcode },
6787 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6788 { Bad_Opcode },
6789 /* 48 */
6790 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6791 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6792 { VEX_W_TABLE (VEX_W_0F3A4A) },
6793 { VEX_W_TABLE (VEX_W_0F3A4B) },
6794 { VEX_W_TABLE (VEX_W_0F3A4C) },
6795 { Bad_Opcode },
6796 { Bad_Opcode },
6797 { Bad_Opcode },
6798 /* 50 */
6799 { Bad_Opcode },
6800 { Bad_Opcode },
6801 { Bad_Opcode },
6802 { Bad_Opcode },
6803 { Bad_Opcode },
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { Bad_Opcode },
6807 /* 58 */
6808 { Bad_Opcode },
6809 { Bad_Opcode },
6810 { Bad_Opcode },
6811 { Bad_Opcode },
6812 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6813 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6814 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6815 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6816 /* 60 */
6817 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6818 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6819 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6820 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 /* 68 */
6826 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6827 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6828 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6829 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6830 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6831 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6832 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6833 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6834 /* 70 */
6835 { Bad_Opcode },
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { Bad_Opcode },
6843 /* 78 */
6844 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6845 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6846 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6847 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6848 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6849 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6850 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6851 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6852 /* 80 */
6853 { Bad_Opcode },
6854 { Bad_Opcode },
6855 { Bad_Opcode },
6856 { Bad_Opcode },
6857 { Bad_Opcode },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { Bad_Opcode },
6861 /* 88 */
6862 { Bad_Opcode },
6863 { Bad_Opcode },
6864 { Bad_Opcode },
6865 { Bad_Opcode },
6866 { Bad_Opcode },
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { Bad_Opcode },
6870 /* 90 */
6871 { Bad_Opcode },
6872 { Bad_Opcode },
6873 { Bad_Opcode },
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { Bad_Opcode },
6879 /* 98 */
6880 { Bad_Opcode },
6881 { Bad_Opcode },
6882 { Bad_Opcode },
6883 { Bad_Opcode },
6884 { Bad_Opcode },
6885 { Bad_Opcode },
6886 { Bad_Opcode },
6887 { Bad_Opcode },
6888 /* a0 */
6889 { Bad_Opcode },
6890 { Bad_Opcode },
6891 { Bad_Opcode },
6892 { Bad_Opcode },
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 /* a8 */
6898 { Bad_Opcode },
6899 { Bad_Opcode },
6900 { Bad_Opcode },
6901 { Bad_Opcode },
6902 { Bad_Opcode },
6903 { Bad_Opcode },
6904 { Bad_Opcode },
6905 { Bad_Opcode },
6906 /* b0 */
6907 { Bad_Opcode },
6908 { Bad_Opcode },
6909 { Bad_Opcode },
6910 { Bad_Opcode },
6911 { Bad_Opcode },
6912 { Bad_Opcode },
6913 { Bad_Opcode },
6914 { Bad_Opcode },
6915 /* b8 */
6916 { Bad_Opcode },
6917 { Bad_Opcode },
6918 { Bad_Opcode },
6919 { Bad_Opcode },
6920 { Bad_Opcode },
6921 { Bad_Opcode },
6922 { Bad_Opcode },
6923 { Bad_Opcode },
6924 /* c0 */
6925 { Bad_Opcode },
6926 { Bad_Opcode },
6927 { Bad_Opcode },
6928 { Bad_Opcode },
6929 { Bad_Opcode },
6930 { Bad_Opcode },
6931 { Bad_Opcode },
6932 { Bad_Opcode },
6933 /* c8 */
6934 { Bad_Opcode },
6935 { Bad_Opcode },
6936 { Bad_Opcode },
6937 { Bad_Opcode },
6938 { Bad_Opcode },
6939 { Bad_Opcode },
6940 { VEX_W_TABLE (VEX_W_0F3ACE) },
6941 { VEX_W_TABLE (VEX_W_0F3ACF) },
6942 /* d0 */
6943 { Bad_Opcode },
6944 { Bad_Opcode },
6945 { Bad_Opcode },
6946 { Bad_Opcode },
6947 { Bad_Opcode },
6948 { Bad_Opcode },
6949 { Bad_Opcode },
6950 { Bad_Opcode },
6951 /* d8 */
6952 { Bad_Opcode },
6953 { Bad_Opcode },
6954 { Bad_Opcode },
6955 { Bad_Opcode },
6956 { Bad_Opcode },
6957 { Bad_Opcode },
6958 { Bad_Opcode },
6959 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6960 /* e0 */
6961 { Bad_Opcode },
6962 { Bad_Opcode },
6963 { Bad_Opcode },
6964 { Bad_Opcode },
6965 { Bad_Opcode },
6966 { Bad_Opcode },
6967 { Bad_Opcode },
6968 { Bad_Opcode },
6969 /* e8 */
6970 { Bad_Opcode },
6971 { Bad_Opcode },
6972 { Bad_Opcode },
6973 { Bad_Opcode },
6974 { Bad_Opcode },
6975 { Bad_Opcode },
6976 { Bad_Opcode },
6977 { Bad_Opcode },
6978 /* f0 */
6979 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6980 { Bad_Opcode },
6981 { Bad_Opcode },
6982 { Bad_Opcode },
6983 { Bad_Opcode },
6984 { Bad_Opcode },
6985 { Bad_Opcode },
6986 { Bad_Opcode },
6987 /* f8 */
6988 { Bad_Opcode },
6989 { Bad_Opcode },
6990 { Bad_Opcode },
6991 { Bad_Opcode },
6992 { Bad_Opcode },
6993 { Bad_Opcode },
6994 { Bad_Opcode },
6995 { Bad_Opcode },
6996 },
6997 };
6998
6999 #include "i386-dis-evex.h"
7000
7001 static const struct dis386 vex_len_table[][2] = {
7002 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
7003 {
7004 { "%XEvmovlpX", { XM, Vex, EXq }, 0 },
7005 },
7006
7007 /* VEX_LEN_0F12_P_0_M_1 */
7008 {
7009 { "%XEvmovhlp%XS", { XM, Vex, EXq }, 0 },
7010 },
7011
7012 /* VEX_LEN_0F13_M_0 */
7013 {
7014 { "%XEvmovlpX", { EXq, XM }, PREFIX_OPCODE },
7015 },
7016
7017 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
7018 {
7019 { "%XEvmovhpX", { XM, Vex, EXq }, 0 },
7020 },
7021
7022 /* VEX_LEN_0F16_P_0_M_1 */
7023 {
7024 { "%XEvmovlhp%XS", { XM, Vex, EXq }, 0 },
7025 },
7026
7027 /* VEX_LEN_0F17_M_0 */
7028 {
7029 { "%XEvmovhpX", { EXq, XM }, PREFIX_OPCODE },
7030 },
7031
7032 /* VEX_LEN_0F41 */
7033 {
7034 { Bad_Opcode },
7035 { MOD_TABLE (MOD_VEX_0F41_L_1) },
7036 },
7037
7038 /* VEX_LEN_0F42 */
7039 {
7040 { Bad_Opcode },
7041 { MOD_TABLE (MOD_VEX_0F42_L_1) },
7042 },
7043
7044 /* VEX_LEN_0F44 */
7045 {
7046 { MOD_TABLE (MOD_VEX_0F44_L_0) },
7047 },
7048
7049 /* VEX_LEN_0F45 */
7050 {
7051 { Bad_Opcode },
7052 { MOD_TABLE (MOD_VEX_0F45_L_1) },
7053 },
7054
7055 /* VEX_LEN_0F46 */
7056 {
7057 { Bad_Opcode },
7058 { MOD_TABLE (MOD_VEX_0F46_L_1) },
7059 },
7060
7061 /* VEX_LEN_0F47 */
7062 {
7063 { Bad_Opcode },
7064 { MOD_TABLE (MOD_VEX_0F47_L_1) },
7065 },
7066
7067 /* VEX_LEN_0F4A */
7068 {
7069 { Bad_Opcode },
7070 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
7071 },
7072
7073 /* VEX_LEN_0F4B */
7074 {
7075 { Bad_Opcode },
7076 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
7077 },
7078
7079 /* VEX_LEN_0F6E */
7080 {
7081 { "%XEvmovK", { XMScalar, Edq }, PREFIX_DATA },
7082 },
7083
7084 /* VEX_LEN_0F77 */
7085 {
7086 { "vzeroupper", { XX }, 0 },
7087 { "vzeroall", { XX }, 0 },
7088 },
7089
7090 /* VEX_LEN_0F7E_P_1 */
7091 {
7092 { "%XEvmovq", { XMScalar, EXq }, 0 },
7093 },
7094
7095 /* VEX_LEN_0F7E_P_2 */
7096 {
7097 { "%XEvmovK", { Edq, XMScalar }, 0 },
7098 },
7099
7100 /* VEX_LEN_0F90 */
7101 {
7102 { VEX_W_TABLE (VEX_W_0F90_L_0) },
7103 },
7104
7105 /* VEX_LEN_0F91 */
7106 {
7107 { MOD_TABLE (MOD_VEX_0F91_L_0) },
7108 },
7109
7110 /* VEX_LEN_0F92 */
7111 {
7112 { MOD_TABLE (MOD_VEX_0F92_L_0) },
7113 },
7114
7115 /* VEX_LEN_0F93 */
7116 {
7117 { MOD_TABLE (MOD_VEX_0F93_L_0) },
7118 },
7119
7120 /* VEX_LEN_0F98 */
7121 {
7122 { MOD_TABLE (MOD_VEX_0F98_L_0) },
7123 },
7124
7125 /* VEX_LEN_0F99 */
7126 {
7127 { MOD_TABLE (MOD_VEX_0F99_L_0) },
7128 },
7129
7130 /* VEX_LEN_0FAE_R_2_M_0 */
7131 {
7132 { "vldmxcsr", { Md }, 0 },
7133 },
7134
7135 /* VEX_LEN_0FAE_R_3_M_0 */
7136 {
7137 { "vstmxcsr", { Md }, 0 },
7138 },
7139
7140 /* VEX_LEN_0FC4 */
7141 {
7142 { "%XEvpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
7143 },
7144
7145 /* VEX_LEN_0FC5 */
7146 {
7147 { "%XEvpextrw", { Gd, XS, Ib }, PREFIX_DATA },
7148 },
7149
7150 /* VEX_LEN_0FD6 */
7151 {
7152 { "%XEvmovq", { EXqS, XMScalar }, PREFIX_DATA },
7153 },
7154
7155 /* VEX_LEN_0FF7 */
7156 {
7157 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
7158 },
7159
7160 /* VEX_LEN_0F3816 */
7161 {
7162 { Bad_Opcode },
7163 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7164 },
7165
7166 /* VEX_LEN_0F3819 */
7167 {
7168 { Bad_Opcode },
7169 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7170 },
7171
7172 /* VEX_LEN_0F381A_M_0 */
7173 {
7174 { Bad_Opcode },
7175 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7176 },
7177
7178 /* VEX_LEN_0F3836 */
7179 {
7180 { Bad_Opcode },
7181 { VEX_W_TABLE (VEX_W_0F3836) },
7182 },
7183
7184 /* VEX_LEN_0F3841 */
7185 {
7186 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7187 },
7188
7189 /* VEX_LEN_0F3849_X86_64 */
7190 {
7191 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7192 },
7193
7194 /* VEX_LEN_0F384B_X86_64 */
7195 {
7196 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7197 },
7198
7199 /* VEX_LEN_0F385A_M_0 */
7200 {
7201 { Bad_Opcode },
7202 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7203 },
7204
7205 /* VEX_LEN_0F385C_X86_64_M_1 */
7206 {
7207 { VEX_W_TABLE (VEX_W_0F385C_X86_64_M_1_L_0) },
7208 },
7209
7210 /* VEX_LEN_0F385E_X86_64_M_1 */
7211 {
7212 { VEX_W_TABLE (VEX_W_0F385E_X86_64_M_1_L_0) },
7213 },
7214
7215 /* VEX_LEN_0F386C_X86_64_M_1 */
7216 {
7217 { VEX_W_TABLE (VEX_W_0F386C_X86_64_M_1_L_0) },
7218 },
7219
7220 /* VEX_LEN_0F38DB */
7221 {
7222 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7223 },
7224
7225 /* VEX_LEN_0F38F2 */
7226 {
7227 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7228 },
7229
7230 /* VEX_LEN_0F38F3 */
7231 {
7232 { REG_TABLE(REG_VEX_0F38F3_L_0) },
7233 },
7234
7235 /* VEX_LEN_0F38F5 */
7236 {
7237 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7238 },
7239
7240 /* VEX_LEN_0F38F6 */
7241 {
7242 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7243 },
7244
7245 /* VEX_LEN_0F38F7 */
7246 {
7247 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7248 },
7249
7250 /* VEX_LEN_0F3A00 */
7251 {
7252 { Bad_Opcode },
7253 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7254 },
7255
7256 /* VEX_LEN_0F3A01 */
7257 {
7258 { Bad_Opcode },
7259 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7260 },
7261
7262 /* VEX_LEN_0F3A06 */
7263 {
7264 { Bad_Opcode },
7265 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7266 },
7267
7268 /* VEX_LEN_0F3A14 */
7269 {
7270 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7271 },
7272
7273 /* VEX_LEN_0F3A15 */
7274 {
7275 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7276 },
7277
7278 /* VEX_LEN_0F3A16 */
7279 {
7280 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7281 },
7282
7283 /* VEX_LEN_0F3A17 */
7284 {
7285 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7286 },
7287
7288 /* VEX_LEN_0F3A18 */
7289 {
7290 { Bad_Opcode },
7291 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7292 },
7293
7294 /* VEX_LEN_0F3A19 */
7295 {
7296 { Bad_Opcode },
7297 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7298 },
7299
7300 /* VEX_LEN_0F3A20 */
7301 {
7302 { "%XEvpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7303 },
7304
7305 /* VEX_LEN_0F3A21 */
7306 {
7307 { "%XEvinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7308 },
7309
7310 /* VEX_LEN_0F3A22 */
7311 {
7312 { "%XEvpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7313 },
7314
7315 /* VEX_LEN_0F3A30 */
7316 {
7317 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7318 },
7319
7320 /* VEX_LEN_0F3A31 */
7321 {
7322 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7323 },
7324
7325 /* VEX_LEN_0F3A32 */
7326 {
7327 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7328 },
7329
7330 /* VEX_LEN_0F3A33 */
7331 {
7332 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7333 },
7334
7335 /* VEX_LEN_0F3A38 */
7336 {
7337 { Bad_Opcode },
7338 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7339 },
7340
7341 /* VEX_LEN_0F3A39 */
7342 {
7343 { Bad_Opcode },
7344 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7345 },
7346
7347 /* VEX_LEN_0F3A41 */
7348 {
7349 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7350 },
7351
7352 /* VEX_LEN_0F3A46 */
7353 {
7354 { Bad_Opcode },
7355 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7356 },
7357
7358 /* VEX_LEN_0F3A60 */
7359 {
7360 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7361 },
7362
7363 /* VEX_LEN_0F3A61 */
7364 {
7365 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7366 },
7367
7368 /* VEX_LEN_0F3A62 */
7369 {
7370 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7371 },
7372
7373 /* VEX_LEN_0F3A63 */
7374 {
7375 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7376 },
7377
7378 /* VEX_LEN_0F3ADF */
7379 {
7380 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7381 },
7382
7383 /* VEX_LEN_0F3AF0 */
7384 {
7385 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7386 },
7387
7388 /* VEX_LEN_0FXOP_08_85 */
7389 {
7390 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7391 },
7392
7393 /* VEX_LEN_0FXOP_08_86 */
7394 {
7395 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7396 },
7397
7398 /* VEX_LEN_0FXOP_08_87 */
7399 {
7400 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7401 },
7402
7403 /* VEX_LEN_0FXOP_08_8E */
7404 {
7405 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7406 },
7407
7408 /* VEX_LEN_0FXOP_08_8F */
7409 {
7410 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7411 },
7412
7413 /* VEX_LEN_0FXOP_08_95 */
7414 {
7415 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7416 },
7417
7418 /* VEX_LEN_0FXOP_08_96 */
7419 {
7420 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7421 },
7422
7423 /* VEX_LEN_0FXOP_08_97 */
7424 {
7425 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7426 },
7427
7428 /* VEX_LEN_0FXOP_08_9E */
7429 {
7430 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7431 },
7432
7433 /* VEX_LEN_0FXOP_08_9F */
7434 {
7435 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7436 },
7437
7438 /* VEX_LEN_0FXOP_08_A3 */
7439 {
7440 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7441 },
7442
7443 /* VEX_LEN_0FXOP_08_A6 */
7444 {
7445 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7446 },
7447
7448 /* VEX_LEN_0FXOP_08_B6 */
7449 {
7450 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7451 },
7452
7453 /* VEX_LEN_0FXOP_08_C0 */
7454 {
7455 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7456 },
7457
7458 /* VEX_LEN_0FXOP_08_C1 */
7459 {
7460 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7461 },
7462
7463 /* VEX_LEN_0FXOP_08_C2 */
7464 {
7465 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7466 },
7467
7468 /* VEX_LEN_0FXOP_08_C3 */
7469 {
7470 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7471 },
7472
7473 /* VEX_LEN_0FXOP_08_CC */
7474 {
7475 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7476 },
7477
7478 /* VEX_LEN_0FXOP_08_CD */
7479 {
7480 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7481 },
7482
7483 /* VEX_LEN_0FXOP_08_CE */
7484 {
7485 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7486 },
7487
7488 /* VEX_LEN_0FXOP_08_CF */
7489 {
7490 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7491 },
7492
7493 /* VEX_LEN_0FXOP_08_EC */
7494 {
7495 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7496 },
7497
7498 /* VEX_LEN_0FXOP_08_ED */
7499 {
7500 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7501 },
7502
7503 /* VEX_LEN_0FXOP_08_EE */
7504 {
7505 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7506 },
7507
7508 /* VEX_LEN_0FXOP_08_EF */
7509 {
7510 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7511 },
7512
7513 /* VEX_LEN_0FXOP_09_01 */
7514 {
7515 { REG_TABLE (REG_XOP_09_01_L_0) },
7516 },
7517
7518 /* VEX_LEN_0FXOP_09_02 */
7519 {
7520 { REG_TABLE (REG_XOP_09_02_L_0) },
7521 },
7522
7523 /* VEX_LEN_0FXOP_09_12_M_1 */
7524 {
7525 { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7526 },
7527
7528 /* VEX_LEN_0FXOP_09_82_W_0 */
7529 {
7530 { "vfrczss", { XM, EXd }, 0 },
7531 },
7532
7533 /* VEX_LEN_0FXOP_09_83_W_0 */
7534 {
7535 { "vfrczsd", { XM, EXq }, 0 },
7536 },
7537
7538 /* VEX_LEN_0FXOP_09_90 */
7539 {
7540 { "vprotb", { XM, EXx, VexW }, 0 },
7541 },
7542
7543 /* VEX_LEN_0FXOP_09_91 */
7544 {
7545 { "vprotw", { XM, EXx, VexW }, 0 },
7546 },
7547
7548 /* VEX_LEN_0FXOP_09_92 */
7549 {
7550 { "vprotd", { XM, EXx, VexW }, 0 },
7551 },
7552
7553 /* VEX_LEN_0FXOP_09_93 */
7554 {
7555 { "vprotq", { XM, EXx, VexW }, 0 },
7556 },
7557
7558 /* VEX_LEN_0FXOP_09_94 */
7559 {
7560 { "vpshlb", { XM, EXx, VexW }, 0 },
7561 },
7562
7563 /* VEX_LEN_0FXOP_09_95 */
7564 {
7565 { "vpshlw", { XM, EXx, VexW }, 0 },
7566 },
7567
7568 /* VEX_LEN_0FXOP_09_96 */
7569 {
7570 { "vpshld", { XM, EXx, VexW }, 0 },
7571 },
7572
7573 /* VEX_LEN_0FXOP_09_97 */
7574 {
7575 { "vpshlq", { XM, EXx, VexW }, 0 },
7576 },
7577
7578 /* VEX_LEN_0FXOP_09_98 */
7579 {
7580 { "vpshab", { XM, EXx, VexW }, 0 },
7581 },
7582
7583 /* VEX_LEN_0FXOP_09_99 */
7584 {
7585 { "vpshaw", { XM, EXx, VexW }, 0 },
7586 },
7587
7588 /* VEX_LEN_0FXOP_09_9A */
7589 {
7590 { "vpshad", { XM, EXx, VexW }, 0 },
7591 },
7592
7593 /* VEX_LEN_0FXOP_09_9B */
7594 {
7595 { "vpshaq", { XM, EXx, VexW }, 0 },
7596 },
7597
7598 /* VEX_LEN_0FXOP_09_C1 */
7599 {
7600 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7601 },
7602
7603 /* VEX_LEN_0FXOP_09_C2 */
7604 {
7605 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7606 },
7607
7608 /* VEX_LEN_0FXOP_09_C3 */
7609 {
7610 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7611 },
7612
7613 /* VEX_LEN_0FXOP_09_C6 */
7614 {
7615 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7616 },
7617
7618 /* VEX_LEN_0FXOP_09_C7 */
7619 {
7620 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7621 },
7622
7623 /* VEX_LEN_0FXOP_09_CB */
7624 {
7625 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7626 },
7627
7628 /* VEX_LEN_0FXOP_09_D1 */
7629 {
7630 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7631 },
7632
7633 /* VEX_LEN_0FXOP_09_D2 */
7634 {
7635 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7636 },
7637
7638 /* VEX_LEN_0FXOP_09_D3 */
7639 {
7640 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7641 },
7642
7643 /* VEX_LEN_0FXOP_09_D6 */
7644 {
7645 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7646 },
7647
7648 /* VEX_LEN_0FXOP_09_D7 */
7649 {
7650 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7651 },
7652
7653 /* VEX_LEN_0FXOP_09_DB */
7654 {
7655 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7656 },
7657
7658 /* VEX_LEN_0FXOP_09_E1 */
7659 {
7660 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7661 },
7662
7663 /* VEX_LEN_0FXOP_09_E2 */
7664 {
7665 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7666 },
7667
7668 /* VEX_LEN_0FXOP_09_E3 */
7669 {
7670 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7671 },
7672
7673 /* VEX_LEN_0FXOP_0A_12 */
7674 {
7675 { REG_TABLE (REG_XOP_0A_12_L_0) },
7676 },
7677 };
7678
7679 #include "i386-dis-evex-len.h"
7680
7681 static const struct dis386 vex_w_table[][2] = {
7682 {
7683 /* VEX_W_0F41_L_1_M_1 */
7684 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7685 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7686 },
7687 {
7688 /* VEX_W_0F42_L_1_M_1 */
7689 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7690 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7691 },
7692 {
7693 /* VEX_W_0F44_L_0_M_1 */
7694 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7695 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7696 },
7697 {
7698 /* VEX_W_0F45_L_1_M_1 */
7699 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7700 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7701 },
7702 {
7703 /* VEX_W_0F46_L_1_M_1 */
7704 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7705 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7706 },
7707 {
7708 /* VEX_W_0F47_L_1_M_1 */
7709 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7710 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7711 },
7712 {
7713 /* VEX_W_0F4A_L_1_M_1 */
7714 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7715 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7716 },
7717 {
7718 /* VEX_W_0F4B_L_1_M_1 */
7719 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7720 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7721 },
7722 {
7723 /* VEX_W_0F90_L_0 */
7724 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7725 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7726 },
7727 {
7728 /* VEX_W_0F91_L_0_M_0 */
7729 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7730 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7731 },
7732 {
7733 /* VEX_W_0F92_L_0_M_1 */
7734 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7735 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7736 },
7737 {
7738 /* VEX_W_0F93_L_0_M_1 */
7739 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7740 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7741 },
7742 {
7743 /* VEX_W_0F98_L_0_M_1 */
7744 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7745 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7746 },
7747 {
7748 /* VEX_W_0F99_L_0_M_1 */
7749 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7750 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7751 },
7752 {
7753 /* VEX_W_0F380C */
7754 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7755 },
7756 {
7757 /* VEX_W_0F380D */
7758 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7759 },
7760 {
7761 /* VEX_W_0F380E */
7762 { "vtestps", { XM, EXx }, PREFIX_DATA },
7763 },
7764 {
7765 /* VEX_W_0F380F */
7766 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7767 },
7768 {
7769 /* VEX_W_0F3813 */
7770 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7771 },
7772 {
7773 /* VEX_W_0F3816_L_1 */
7774 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7775 },
7776 {
7777 /* VEX_W_0F3818 */
7778 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7779 },
7780 {
7781 /* VEX_W_0F3819_L_1 */
7782 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7783 },
7784 {
7785 /* VEX_W_0F381A_M_0_L_1 */
7786 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7787 },
7788 {
7789 /* VEX_W_0F382C_M_0 */
7790 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7791 },
7792 {
7793 /* VEX_W_0F382D_M_0 */
7794 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7795 },
7796 {
7797 /* VEX_W_0F382E_M_0 */
7798 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7799 },
7800 {
7801 /* VEX_W_0F382F_M_0 */
7802 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7803 },
7804 {
7805 /* VEX_W_0F3836 */
7806 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7807 },
7808 {
7809 /* VEX_W_0F3846 */
7810 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7811 },
7812 {
7813 /* VEX_W_0F3849_X86_64_L_0 */
7814 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7815 },
7816 {
7817 /* VEX_W_0F384B_X86_64_L_0 */
7818 { MOD_TABLE (MOD_VEX_0F384B_X86_64_L_0_W_0) },
7819 },
7820 {
7821 /* VEX_W_0F3850 */
7822 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7823 },
7824 {
7825 /* VEX_W_0F3851 */
7826 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7827 },
7828 {
7829 /* VEX_W_0F3852 */
7830 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7831 },
7832 {
7833 /* VEX_W_0F3853 */
7834 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7835 },
7836 {
7837 /* VEX_W_0F3858 */
7838 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7839 },
7840 {
7841 /* VEX_W_0F3859 */
7842 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7843 },
7844 {
7845 /* VEX_W_0F385A_M_0_L_0 */
7846 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7847 },
7848 {
7849 /* VEX_W_0F385C_X86_64_M_1_L_0 */
7850 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0) },
7851 },
7852 {
7853 /* VEX_W_0F385E_X86_64_M_1_L_0 */
7854 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0) },
7855 },
7856 {
7857 /* VEX_W_0F386C_X86_64_M_1_L_0 */
7858 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0) },
7859 },
7860 {
7861 /* VEX_W_0F3872_P_1 */
7862 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7863 },
7864 {
7865 /* VEX_W_0F3878 */
7866 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7867 },
7868 {
7869 /* VEX_W_0F3879 */
7870 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7871 },
7872 {
7873 /* VEX_W_0F38B0 */
7874 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7875 },
7876 {
7877 /* VEX_W_0F38B1 */
7878 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7879 },
7880 {
7881 /* VEX_W_0F38B4 */
7882 { Bad_Opcode },
7883 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7884 },
7885 {
7886 /* VEX_W_0F38B5 */
7887 { Bad_Opcode },
7888 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7889 },
7890 {
7891 /* VEX_W_0F38CF */
7892 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7893 },
7894 {
7895 /* VEX_W_0F3A00_L_1 */
7896 { Bad_Opcode },
7897 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7898 },
7899 {
7900 /* VEX_W_0F3A01_L_1 */
7901 { Bad_Opcode },
7902 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7903 },
7904 {
7905 /* VEX_W_0F3A02 */
7906 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7907 },
7908 {
7909 /* VEX_W_0F3A04 */
7910 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7911 },
7912 {
7913 /* VEX_W_0F3A05 */
7914 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7915 },
7916 {
7917 /* VEX_W_0F3A06_L_1 */
7918 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7919 },
7920 {
7921 /* VEX_W_0F3A18_L_1 */
7922 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7923 },
7924 {
7925 /* VEX_W_0F3A19_L_1 */
7926 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7927 },
7928 {
7929 /* VEX_W_0F3A1D */
7930 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7931 },
7932 {
7933 /* VEX_W_0F3A38_L_1 */
7934 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7935 },
7936 {
7937 /* VEX_W_0F3A39_L_1 */
7938 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7939 },
7940 {
7941 /* VEX_W_0F3A46_L_1 */
7942 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7943 },
7944 {
7945 /* VEX_W_0F3A4A */
7946 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7947 },
7948 {
7949 /* VEX_W_0F3A4B */
7950 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7951 },
7952 {
7953 /* VEX_W_0F3A4C */
7954 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7955 },
7956 {
7957 /* VEX_W_0F3ACE */
7958 { Bad_Opcode },
7959 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7960 },
7961 {
7962 /* VEX_W_0F3ACF */
7963 { Bad_Opcode },
7964 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7965 },
7966 /* VEX_W_0FXOP_08_85_L_0 */
7967 {
7968 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7969 },
7970 /* VEX_W_0FXOP_08_86_L_0 */
7971 {
7972 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7973 },
7974 /* VEX_W_0FXOP_08_87_L_0 */
7975 {
7976 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7977 },
7978 /* VEX_W_0FXOP_08_8E_L_0 */
7979 {
7980 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7981 },
7982 /* VEX_W_0FXOP_08_8F_L_0 */
7983 {
7984 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7985 },
7986 /* VEX_W_0FXOP_08_95_L_0 */
7987 {
7988 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7989 },
7990 /* VEX_W_0FXOP_08_96_L_0 */
7991 {
7992 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7993 },
7994 /* VEX_W_0FXOP_08_97_L_0 */
7995 {
7996 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7997 },
7998 /* VEX_W_0FXOP_08_9E_L_0 */
7999 {
8000 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8001 },
8002 /* VEX_W_0FXOP_08_9F_L_0 */
8003 {
8004 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8005 },
8006 /* VEX_W_0FXOP_08_A6_L_0 */
8007 {
8008 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8009 },
8010 /* VEX_W_0FXOP_08_B6_L_0 */
8011 {
8012 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8013 },
8014 /* VEX_W_0FXOP_08_C0_L_0 */
8015 {
8016 { "vprotb", { XM, EXx, Ib }, 0 },
8017 },
8018 /* VEX_W_0FXOP_08_C1_L_0 */
8019 {
8020 { "vprotw", { XM, EXx, Ib }, 0 },
8021 },
8022 /* VEX_W_0FXOP_08_C2_L_0 */
8023 {
8024 { "vprotd", { XM, EXx, Ib }, 0 },
8025 },
8026 /* VEX_W_0FXOP_08_C3_L_0 */
8027 {
8028 { "vprotq", { XM, EXx, Ib }, 0 },
8029 },
8030 /* VEX_W_0FXOP_08_CC_L_0 */
8031 {
8032 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8033 },
8034 /* VEX_W_0FXOP_08_CD_L_0 */
8035 {
8036 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8037 },
8038 /* VEX_W_0FXOP_08_CE_L_0 */
8039 {
8040 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8041 },
8042 /* VEX_W_0FXOP_08_CF_L_0 */
8043 {
8044 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8045 },
8046 /* VEX_W_0FXOP_08_EC_L_0 */
8047 {
8048 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8049 },
8050 /* VEX_W_0FXOP_08_ED_L_0 */
8051 {
8052 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8053 },
8054 /* VEX_W_0FXOP_08_EE_L_0 */
8055 {
8056 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8057 },
8058 /* VEX_W_0FXOP_08_EF_L_0 */
8059 {
8060 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8061 },
8062 /* VEX_W_0FXOP_09_80 */
8063 {
8064 { "vfrczps", { XM, EXx }, 0 },
8065 },
8066 /* VEX_W_0FXOP_09_81 */
8067 {
8068 { "vfrczpd", { XM, EXx }, 0 },
8069 },
8070 /* VEX_W_0FXOP_09_82 */
8071 {
8072 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8073 },
8074 /* VEX_W_0FXOP_09_83 */
8075 {
8076 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8077 },
8078 /* VEX_W_0FXOP_09_C1_L_0 */
8079 {
8080 { "vphaddbw", { XM, EXxmm }, 0 },
8081 },
8082 /* VEX_W_0FXOP_09_C2_L_0 */
8083 {
8084 { "vphaddbd", { XM, EXxmm }, 0 },
8085 },
8086 /* VEX_W_0FXOP_09_C3_L_0 */
8087 {
8088 { "vphaddbq", { XM, EXxmm }, 0 },
8089 },
8090 /* VEX_W_0FXOP_09_C6_L_0 */
8091 {
8092 { "vphaddwd", { XM, EXxmm }, 0 },
8093 },
8094 /* VEX_W_0FXOP_09_C7_L_0 */
8095 {
8096 { "vphaddwq", { XM, EXxmm }, 0 },
8097 },
8098 /* VEX_W_0FXOP_09_CB_L_0 */
8099 {
8100 { "vphadddq", { XM, EXxmm }, 0 },
8101 },
8102 /* VEX_W_0FXOP_09_D1_L_0 */
8103 {
8104 { "vphaddubw", { XM, EXxmm }, 0 },
8105 },
8106 /* VEX_W_0FXOP_09_D2_L_0 */
8107 {
8108 { "vphaddubd", { XM, EXxmm }, 0 },
8109 },
8110 /* VEX_W_0FXOP_09_D3_L_0 */
8111 {
8112 { "vphaddubq", { XM, EXxmm }, 0 },
8113 },
8114 /* VEX_W_0FXOP_09_D6_L_0 */
8115 {
8116 { "vphadduwd", { XM, EXxmm }, 0 },
8117 },
8118 /* VEX_W_0FXOP_09_D7_L_0 */
8119 {
8120 { "vphadduwq", { XM, EXxmm }, 0 },
8121 },
8122 /* VEX_W_0FXOP_09_DB_L_0 */
8123 {
8124 { "vphaddudq", { XM, EXxmm }, 0 },
8125 },
8126 /* VEX_W_0FXOP_09_E1_L_0 */
8127 {
8128 { "vphsubbw", { XM, EXxmm }, 0 },
8129 },
8130 /* VEX_W_0FXOP_09_E2_L_0 */
8131 {
8132 { "vphsubwd", { XM, EXxmm }, 0 },
8133 },
8134 /* VEX_W_0FXOP_09_E3_L_0 */
8135 {
8136 { "vphsubdq", { XM, EXxmm }, 0 },
8137 },
8138
8139 #include "i386-dis-evex-w.h"
8140 };
8141
8142 static const struct dis386 mod_table[][2] = {
8143 {
8144 /* MOD_62_32BIT */
8145 { "bound{S|}", { Gv, Ma }, 0 },
8146 { EVEX_TABLE (EVEX_0F) },
8147 },
8148 {
8149 /* MOD_8D */
8150 { "leaS", { Gv, M }, 0 },
8151 },
8152 {
8153 /* MOD_C4_32BIT */
8154 { "lesS", { Gv, Mp }, 0 },
8155 { VEX_C4_TABLE (VEX_0F) },
8156 },
8157 {
8158 /* MOD_C5_32BIT */
8159 { "ldsS", { Gv, Mp }, 0 },
8160 { VEX_C5_TABLE (VEX_0F) },
8161 },
8162 {
8163 /* MOD_C6_REG_7 */
8164 { Bad_Opcode },
8165 { RM_TABLE (RM_C6_REG_7) },
8166 },
8167 {
8168 /* MOD_C7_REG_7 */
8169 { Bad_Opcode },
8170 { RM_TABLE (RM_C7_REG_7) },
8171 },
8172 {
8173 /* MOD_FF_REG_3 */
8174 { "{l|}call^", { indirEp }, 0 },
8175 },
8176 {
8177 /* MOD_FF_REG_5 */
8178 { "{l|}jmp^", { indirEp }, 0 },
8179 },
8180 {
8181 /* MOD_0F01_REG_0 */
8182 { X86_64_TABLE (X86_64_0F01_REG_0) },
8183 { RM_TABLE (RM_0F01_REG_0) },
8184 },
8185 {
8186 /* MOD_0F01_REG_1 */
8187 { X86_64_TABLE (X86_64_0F01_REG_1) },
8188 { RM_TABLE (RM_0F01_REG_1) },
8189 },
8190 {
8191 /* MOD_0F01_REG_2 */
8192 { X86_64_TABLE (X86_64_0F01_REG_2) },
8193 { RM_TABLE (RM_0F01_REG_2) },
8194 },
8195 {
8196 /* MOD_0F01_REG_3 */
8197 { X86_64_TABLE (X86_64_0F01_REG_3) },
8198 { RM_TABLE (RM_0F01_REG_3) },
8199 },
8200 {
8201 /* MOD_0F01_REG_5 */
8202 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8203 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8204 },
8205 {
8206 /* MOD_0F01_REG_7 */
8207 { "invlpg", { Mb }, 0 },
8208 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8209 },
8210 {
8211 /* MOD_0F02 */
8212 { "larS", { Gv, Mw }, 0 },
8213 { "larS", { Gv, Ev }, 0 },
8214 },
8215 {
8216 /* MOD_0F03 */
8217 { "lslS", { Gv, Mw }, 0 },
8218 { "lslS", { Gv, Ev }, 0 },
8219 },
8220 {
8221 /* MOD_0F12_PREFIX_0 */
8222 { "movlpX", { XM, EXq }, 0 },
8223 { "movhlps", { XM, EXq }, 0 },
8224 },
8225 {
8226 /* MOD_0F12_PREFIX_2 */
8227 { "movlpX", { XM, EXq }, 0 },
8228 },
8229 {
8230 /* MOD_0F13 */
8231 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
8232 },
8233 {
8234 /* MOD_0F16_PREFIX_0 */
8235 { "movhpX", { XM, EXq }, 0 },
8236 { "movlhps", { XM, EXq }, 0 },
8237 },
8238 {
8239 /* MOD_0F16_PREFIX_2 */
8240 { "movhpX", { XM, EXq }, 0 },
8241 },
8242 {
8243 /* MOD_0F17 */
8244 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8245 },
8246 {
8247 /* MOD_0F18_REG_0 */
8248 { "prefetchnta", { Mb }, 0 },
8249 { "nopQ", { Ev }, 0 },
8250 },
8251 {
8252 /* MOD_0F18_REG_1 */
8253 { "prefetcht0", { Mb }, 0 },
8254 { "nopQ", { Ev }, 0 },
8255 },
8256 {
8257 /* MOD_0F18_REG_2 */
8258 { "prefetcht1", { Mb }, 0 },
8259 { "nopQ", { Ev }, 0 },
8260 },
8261 {
8262 /* MOD_0F18_REG_3 */
8263 { "prefetcht2", { Mb }, 0 },
8264 { "nopQ", { Ev }, 0 },
8265 },
8266 {
8267 /* MOD_0F18_REG_6 */
8268 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8269 { "nopQ", { Ev }, 0 },
8270 },
8271 {
8272 /* MOD_0F18_REG_7 */
8273 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8274 { "nopQ", { Ev }, 0 },
8275 },
8276 {
8277 /* MOD_0F1A_PREFIX_0 */
8278 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8279 { "nopQ", { Ev }, 0 },
8280 },
8281 {
8282 /* MOD_0F1B_PREFIX_0 */
8283 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8284 { "nopQ", { Ev }, 0 },
8285 },
8286 {
8287 /* MOD_0F1B_PREFIX_1 */
8288 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8289 { "nopQ", { Ev }, PREFIX_IGNORED },
8290 },
8291 {
8292 /* MOD_0F1C_PREFIX_0 */
8293 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8294 { "nopQ", { Ev }, 0 },
8295 },
8296 {
8297 /* MOD_0F1E_PREFIX_1 */
8298 { "nopQ", { Ev }, PREFIX_IGNORED },
8299 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8300 },
8301 {
8302 /* MOD_0F2B_PREFIX_0 */
8303 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8304 },
8305 {
8306 /* MOD_0F2B_PREFIX_1 */
8307 {"movntss", { Md, XM }, PREFIX_OPCODE },
8308 },
8309 {
8310 /* MOD_0F2B_PREFIX_2 */
8311 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8312 },
8313 {
8314 /* MOD_0F2B_PREFIX_3 */
8315 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8316 },
8317 {
8318 /* MOD_0F50 */
8319 { Bad_Opcode },
8320 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8321 },
8322 {
8323 /* MOD_0F71 */
8324 { Bad_Opcode },
8325 { REG_TABLE (REG_0F71_MOD_0) },
8326 },
8327 {
8328 /* MOD_0F72 */
8329 { Bad_Opcode },
8330 { REG_TABLE (REG_0F72_MOD_0) },
8331 },
8332 {
8333 /* MOD_0F73 */
8334 { Bad_Opcode },
8335 { REG_TABLE (REG_0F73_MOD_0) },
8336 },
8337 {
8338 /* MOD_0FAE_REG_0 */
8339 { "fxsave", { FXSAVE }, 0 },
8340 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8341 },
8342 {
8343 /* MOD_0FAE_REG_1 */
8344 { "fxrstor", { FXSAVE }, 0 },
8345 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8346 },
8347 {
8348 /* MOD_0FAE_REG_2 */
8349 { "ldmxcsr", { Md }, 0 },
8350 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8351 },
8352 {
8353 /* MOD_0FAE_REG_3 */
8354 { "stmxcsr", { Md }, 0 },
8355 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8356 },
8357 {
8358 /* MOD_0FAE_REG_4 */
8359 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8360 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8361 },
8362 {
8363 /* MOD_0FAE_REG_5 */
8364 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8365 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8366 },
8367 {
8368 /* MOD_0FAE_REG_6 */
8369 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8370 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8371 },
8372 {
8373 /* MOD_0FAE_REG_7 */
8374 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8375 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8376 },
8377 {
8378 /* MOD_0FB2 */
8379 { "lssS", { Gv, Mp }, 0 },
8380 },
8381 {
8382 /* MOD_0FB4 */
8383 { "lfsS", { Gv, Mp }, 0 },
8384 },
8385 {
8386 /* MOD_0FB5 */
8387 { "lgsS", { Gv, Mp }, 0 },
8388 },
8389 {
8390 /* MOD_0FC3 */
8391 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8392 },
8393 {
8394 /* MOD_0FC7_REG_3 */
8395 { "xrstors", { FXSAVE }, 0 },
8396 },
8397 {
8398 /* MOD_0FC7_REG_4 */
8399 { "xsavec", { FXSAVE }, 0 },
8400 },
8401 {
8402 /* MOD_0FC7_REG_5 */
8403 { "xsaves", { FXSAVE }, 0 },
8404 },
8405 {
8406 /* MOD_0FC7_REG_6 */
8407 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8408 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8409 },
8410 {
8411 /* MOD_0FC7_REG_7 */
8412 { "vmptrst", { Mq }, 0 },
8413 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8414 },
8415 {
8416 /* MOD_0FD7 */
8417 { Bad_Opcode },
8418 { "pmovmskb", { Gdq, MS }, 0 },
8419 },
8420 {
8421 /* MOD_0FE7_PREFIX_2 */
8422 { "movntdq", { Mx, XM }, 0 },
8423 },
8424 {
8425 /* MOD_0FF0_PREFIX_3 */
8426 { "lddqu", { XM, M }, 0 },
8427 },
8428 {
8429 /* MOD_0F382A */
8430 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8431 },
8432 {
8433 /* MOD_0F38DC_PREFIX_1 */
8434 { "aesenc128kl", { XM, M }, 0 },
8435 { "loadiwkey", { XM, EXx }, 0 },
8436 },
8437 {
8438 /* MOD_0F38DD_PREFIX_1 */
8439 { "aesdec128kl", { XM, M }, 0 },
8440 },
8441 {
8442 /* MOD_0F38DE_PREFIX_1 */
8443 { "aesenc256kl", { XM, M }, 0 },
8444 },
8445 {
8446 /* MOD_0F38DF_PREFIX_1 */
8447 { "aesdec256kl", { XM, M }, 0 },
8448 },
8449 {
8450 /* MOD_0F38F5 */
8451 { "wrussK", { M, Gdq }, PREFIX_DATA },
8452 },
8453 {
8454 /* MOD_0F38F6_PREFIX_0 */
8455 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8456 },
8457 {
8458 /* MOD_0F38F8_PREFIX_1 */
8459 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8460 },
8461 {
8462 /* MOD_0F38F8_PREFIX_2 */
8463 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8464 },
8465 {
8466 /* MOD_0F38F8_PREFIX_3 */
8467 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8468 },
8469 {
8470 /* MOD_0F38F9 */
8471 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8472 },
8473 {
8474 /* MOD_0F38FA_PREFIX_1 */
8475 { Bad_Opcode },
8476 { "encodekey128", { Gd, Ed }, 0 },
8477 },
8478 {
8479 /* MOD_0F38FB_PREFIX_1 */
8480 { Bad_Opcode },
8481 { "encodekey256", { Gd, Ed }, 0 },
8482 },
8483 {
8484 /* MOD_0F3A0F_PREFIX_1 */
8485 { Bad_Opcode },
8486 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8487 },
8488 {
8489 /* MOD_VEX_0F12_PREFIX_0 */
8490 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8491 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8492 },
8493 {
8494 /* MOD_VEX_0F12_PREFIX_2 */
8495 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8496 },
8497 {
8498 /* MOD_VEX_0F13 */
8499 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8500 },
8501 {
8502 /* MOD_VEX_0F16_PREFIX_0 */
8503 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8504 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8505 },
8506 {
8507 /* MOD_VEX_0F16_PREFIX_2 */
8508 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8509 },
8510 {
8511 /* MOD_VEX_0F17 */
8512 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8513 },
8514 {
8515 /* MOD_VEX_0F2B */
8516 { "%XEvmovntpX", { Mx, XM }, PREFIX_OPCODE },
8517 },
8518 {
8519 /* MOD_VEX_0F41_L_1 */
8520 { Bad_Opcode },
8521 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8522 },
8523 {
8524 /* MOD_VEX_0F42_L_1 */
8525 { Bad_Opcode },
8526 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8527 },
8528 {
8529 /* MOD_VEX_0F44_L_0 */
8530 { Bad_Opcode },
8531 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8532 },
8533 {
8534 /* MOD_VEX_0F45_L_1 */
8535 { Bad_Opcode },
8536 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8537 },
8538 {
8539 /* MOD_VEX_0F46_L_1 */
8540 { Bad_Opcode },
8541 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8542 },
8543 {
8544 /* MOD_VEX_0F47_L_1 */
8545 { Bad_Opcode },
8546 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8547 },
8548 {
8549 /* MOD_VEX_0F4A_L_1 */
8550 { Bad_Opcode },
8551 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8552 },
8553 {
8554 /* MOD_VEX_0F4B_L_1 */
8555 { Bad_Opcode },
8556 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8557 },
8558 {
8559 /* MOD_VEX_0F50 */
8560 { Bad_Opcode },
8561 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8562 },
8563 {
8564 /* MOD_VEX_0F71 */
8565 { Bad_Opcode },
8566 { REG_TABLE (REG_VEX_0F71_M_0) },
8567 },
8568 {
8569 /* MOD_VEX_0F72 */
8570 { Bad_Opcode },
8571 { REG_TABLE (REG_VEX_0F72_M_0) },
8572 },
8573 {
8574 /* MOD_VEX_0F73 */
8575 { Bad_Opcode },
8576 { REG_TABLE (REG_VEX_0F73_M_0) },
8577 },
8578 {
8579 /* MOD_VEX_0F91_L_0 */
8580 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8581 },
8582 {
8583 /* MOD_VEX_0F92_L_0 */
8584 { Bad_Opcode },
8585 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8586 },
8587 {
8588 /* MOD_VEX_0F93_L_0 */
8589 { Bad_Opcode },
8590 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8591 },
8592 {
8593 /* MOD_VEX_0F98_L_0 */
8594 { Bad_Opcode },
8595 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8596 },
8597 {
8598 /* MOD_VEX_0F99_L_0 */
8599 { Bad_Opcode },
8600 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8601 },
8602 {
8603 /* MOD_VEX_0FAE_REG_2 */
8604 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8605 },
8606 {
8607 /* MOD_VEX_0FAE_REG_3 */
8608 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8609 },
8610 {
8611 /* MOD_VEX_0FD7 */
8612 { Bad_Opcode },
8613 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8614 },
8615 {
8616 /* MOD_VEX_0FE7 */
8617 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8618 },
8619 {
8620 /* MOD_VEX_0FF0_PREFIX_3 */
8621 { "vlddqu", { XM, M }, 0 },
8622 },
8623 {
8624 /* MOD_VEX_0F381A */
8625 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8626 },
8627 {
8628 /* MOD_VEX_0F382A */
8629 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8630 },
8631 {
8632 /* MOD_VEX_0F382C */
8633 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8634 },
8635 {
8636 /* MOD_VEX_0F382D */
8637 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8638 },
8639 {
8640 /* MOD_VEX_0F382E */
8641 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8642 },
8643 {
8644 /* MOD_VEX_0F382F */
8645 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8646 },
8647 {
8648 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8649 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8651 },
8652 {
8653 /* MOD_VEX_0F384B_X86_64_L_0_W_0 */
8654 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0) },
8655 },
8656 {
8657 /* MOD_VEX_0F385A */
8658 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8659 },
8660 {
8661 /* MOD_VEX_0F385C_X86_64 */
8662 { Bad_Opcode },
8663 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_M_1) },
8664 },
8665 {
8666 /* MOD_VEX_0F385E_X86_64 */
8667 { Bad_Opcode },
8668 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_M_1) },
8669 },
8670 {
8671 /* MOD_VEX_0F386C_X86_64 */
8672 { Bad_Opcode },
8673 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64_M_1) },
8674 },
8675 {
8676 /* MOD_VEX_0F388C */
8677 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8678 },
8679 {
8680 /* MOD_VEX_0F388E */
8681 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8682 },
8683 {
8684 /* MOD_VEX_0F3A30_L_0 */
8685 { Bad_Opcode },
8686 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8687 },
8688 {
8689 /* MOD_VEX_0F3A31_L_0 */
8690 { Bad_Opcode },
8691 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8692 },
8693 {
8694 /* MOD_VEX_0F3A32_L_0 */
8695 { Bad_Opcode },
8696 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8697 },
8698 {
8699 /* MOD_VEX_0F3A33_L_0 */
8700 { Bad_Opcode },
8701 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8702 },
8703 {
8704 /* MOD_XOP_09_12 */
8705 { Bad_Opcode },
8706 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8707 },
8708
8709 #include "i386-dis-evex-mod.h"
8710 };
8711
8712 static const struct dis386 rm_table[][8] = {
8713 {
8714 /* RM_C6_REG_7 */
8715 { "xabort", { Skip_MODRM, Ib }, 0 },
8716 },
8717 {
8718 /* RM_C7_REG_7 */
8719 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8720 },
8721 {
8722 /* RM_0F01_REG_0 */
8723 { "enclv", { Skip_MODRM }, 0 },
8724 { "vmcall", { Skip_MODRM }, 0 },
8725 { "vmlaunch", { Skip_MODRM }, 0 },
8726 { "vmresume", { Skip_MODRM }, 0 },
8727 { "vmxoff", { Skip_MODRM }, 0 },
8728 { "pconfig", { Skip_MODRM }, 0 },
8729 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8730 },
8731 {
8732 /* RM_0F01_REG_1 */
8733 { "monitor", { { OP_Monitor, 0 } }, 0 },
8734 { "mwait", { { OP_Mwait, 0 } }, 0 },
8735 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8736 { "stac", { Skip_MODRM }, 0 },
8737 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8738 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8739 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8740 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8741 },
8742 {
8743 /* RM_0F01_REG_2 */
8744 { "xgetbv", { Skip_MODRM }, 0 },
8745 { "xsetbv", { Skip_MODRM }, 0 },
8746 { Bad_Opcode },
8747 { Bad_Opcode },
8748 { "vmfunc", { Skip_MODRM }, 0 },
8749 { "xend", { Skip_MODRM }, 0 },
8750 { "xtest", { Skip_MODRM }, 0 },
8751 { "enclu", { Skip_MODRM }, 0 },
8752 },
8753 {
8754 /* RM_0F01_REG_3 */
8755 { "vmrun", { Skip_MODRM }, 0 },
8756 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8757 { "vmload", { Skip_MODRM }, 0 },
8758 { "vmsave", { Skip_MODRM }, 0 },
8759 { "stgi", { Skip_MODRM }, 0 },
8760 { "clgi", { Skip_MODRM }, 0 },
8761 { "skinit", { Skip_MODRM }, 0 },
8762 { "invlpga", { Skip_MODRM }, 0 },
8763 },
8764 {
8765 /* RM_0F01_REG_5_MOD_3 */
8766 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8767 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8768 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8769 { Bad_Opcode },
8770 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8771 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8772 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8773 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8774 },
8775 {
8776 /* RM_0F01_REG_7_MOD_3 */
8777 { "swapgs", { Skip_MODRM }, 0 },
8778 { "rdtscp", { Skip_MODRM }, 0 },
8779 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8780 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8781 { "clzero", { Skip_MODRM }, 0 },
8782 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8783 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8784 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8785 },
8786 {
8787 /* RM_0F1E_P_1_MOD_3_REG_7 */
8788 { "nopQ", { Ev }, PREFIX_IGNORED },
8789 { "nopQ", { Ev }, PREFIX_IGNORED },
8790 { "endbr64", { Skip_MODRM }, 0 },
8791 { "endbr32", { Skip_MODRM }, 0 },
8792 { "nopQ", { Ev }, PREFIX_IGNORED },
8793 { "nopQ", { Ev }, PREFIX_IGNORED },
8794 { "nopQ", { Ev }, PREFIX_IGNORED },
8795 { "nopQ", { Ev }, PREFIX_IGNORED },
8796 },
8797 {
8798 /* RM_0FAE_REG_6_MOD_3 */
8799 { "mfence", { Skip_MODRM }, 0 },
8800 },
8801 {
8802 /* RM_0FAE_REG_7_MOD_3 */
8803 { "sfence", { Skip_MODRM }, 0 },
8804 },
8805 {
8806 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8807 { "hreset", { Skip_MODRM, Ib }, 0 },
8808 },
8809 {
8810 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8811 { "tilerelease", { Skip_MODRM }, 0 },
8812 },
8813 {
8814 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8815 { "tilezero", { TMM, Skip_MODRM }, 0 },
8816 },
8817 };
8818
8819 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8820
8821 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8822 in conflict with actual prefix opcodes. */
8823 #define REP_PREFIX 0x01
8824 #define XACQUIRE_PREFIX 0x02
8825 #define XRELEASE_PREFIX 0x03
8826 #define BND_PREFIX 0x04
8827 #define NOTRACK_PREFIX 0x05
8828
8829 static enum {
8830 ckp_okay,
8831 ckp_bogus,
8832 ckp_fetch_error,
8833 }
8834 ckprefix (instr_info *ins)
8835 {
8836 int i, length;
8837 uint8_t newrex;
8838
8839 i = 0;
8840 length = 0;
8841 /* The maximum instruction length is 15bytes. */
8842 while (length < MAX_CODE_LENGTH - 1)
8843 {
8844 if (!fetch_code (ins->info, ins->codep + 1))
8845 return ckp_fetch_error;
8846 newrex = 0;
8847 switch (*ins->codep)
8848 {
8849 /* REX prefixes family. */
8850 case 0x40:
8851 case 0x41:
8852 case 0x42:
8853 case 0x43:
8854 case 0x44:
8855 case 0x45:
8856 case 0x46:
8857 case 0x47:
8858 case 0x48:
8859 case 0x49:
8860 case 0x4a:
8861 case 0x4b:
8862 case 0x4c:
8863 case 0x4d:
8864 case 0x4e:
8865 case 0x4f:
8866 if (ins->address_mode == mode_64bit)
8867 newrex = *ins->codep;
8868 else
8869 return ckp_okay;
8870 ins->last_rex_prefix = i;
8871 break;
8872 case 0xf3:
8873 ins->prefixes |= PREFIX_REPZ;
8874 ins->last_repz_prefix = i;
8875 break;
8876 case 0xf2:
8877 ins->prefixes |= PREFIX_REPNZ;
8878 ins->last_repnz_prefix = i;
8879 break;
8880 case 0xf0:
8881 ins->prefixes |= PREFIX_LOCK;
8882 ins->last_lock_prefix = i;
8883 break;
8884 case 0x2e:
8885 ins->prefixes |= PREFIX_CS;
8886 ins->last_seg_prefix = i;
8887 if (ins->address_mode != mode_64bit)
8888 ins->active_seg_prefix = PREFIX_CS;
8889 break;
8890 case 0x36:
8891 ins->prefixes |= PREFIX_SS;
8892 ins->last_seg_prefix = i;
8893 if (ins->address_mode != mode_64bit)
8894 ins->active_seg_prefix = PREFIX_SS;
8895 break;
8896 case 0x3e:
8897 ins->prefixes |= PREFIX_DS;
8898 ins->last_seg_prefix = i;
8899 if (ins->address_mode != mode_64bit)
8900 ins->active_seg_prefix = PREFIX_DS;
8901 break;
8902 case 0x26:
8903 ins->prefixes |= PREFIX_ES;
8904 ins->last_seg_prefix = i;
8905 if (ins->address_mode != mode_64bit)
8906 ins->active_seg_prefix = PREFIX_ES;
8907 break;
8908 case 0x64:
8909 ins->prefixes |= PREFIX_FS;
8910 ins->last_seg_prefix = i;
8911 ins->active_seg_prefix = PREFIX_FS;
8912 break;
8913 case 0x65:
8914 ins->prefixes |= PREFIX_GS;
8915 ins->last_seg_prefix = i;
8916 ins->active_seg_prefix = PREFIX_GS;
8917 break;
8918 case 0x66:
8919 ins->prefixes |= PREFIX_DATA;
8920 ins->last_data_prefix = i;
8921 break;
8922 case 0x67:
8923 ins->prefixes |= PREFIX_ADDR;
8924 ins->last_addr_prefix = i;
8925 break;
8926 case FWAIT_OPCODE:
8927 /* fwait is really an instruction. If there are prefixes
8928 before the fwait, they belong to the fwait, *not* to the
8929 following instruction. */
8930 ins->fwait_prefix = i;
8931 if (ins->prefixes || ins->rex)
8932 {
8933 ins->prefixes |= PREFIX_FWAIT;
8934 ins->codep++;
8935 /* This ensures that the previous REX prefixes are noticed
8936 as unused prefixes, as in the return case below. */
8937 return ins->rex ? ckp_bogus : ckp_okay;
8938 }
8939 ins->prefixes = PREFIX_FWAIT;
8940 break;
8941 default:
8942 return ckp_okay;
8943 }
8944 /* Rex is ignored when followed by another prefix. */
8945 if (ins->rex)
8946 return ckp_bogus;
8947 if (*ins->codep != FWAIT_OPCODE)
8948 ins->all_prefixes[i++] = *ins->codep;
8949 ins->rex = newrex;
8950 ins->codep++;
8951 length++;
8952 }
8953 return ckp_bogus;
8954 }
8955
8956 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8957 prefix byte. */
8958
8959 static const char *
8960 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8961 {
8962 static const char *rexes [16] =
8963 {
8964 "rex", /* 0x40 */
8965 "rex.B", /* 0x41 */
8966 "rex.X", /* 0x42 */
8967 "rex.XB", /* 0x43 */
8968 "rex.R", /* 0x44 */
8969 "rex.RB", /* 0x45 */
8970 "rex.RX", /* 0x46 */
8971 "rex.RXB", /* 0x47 */
8972 "rex.W", /* 0x48 */
8973 "rex.WB", /* 0x49 */
8974 "rex.WX", /* 0x4a */
8975 "rex.WXB", /* 0x4b */
8976 "rex.WR", /* 0x4c */
8977 "rex.WRB", /* 0x4d */
8978 "rex.WRX", /* 0x4e */
8979 "rex.WRXB", /* 0x4f */
8980 };
8981
8982 switch (pref)
8983 {
8984 /* REX prefixes family. */
8985 case 0x40:
8986 case 0x41:
8987 case 0x42:
8988 case 0x43:
8989 case 0x44:
8990 case 0x45:
8991 case 0x46:
8992 case 0x47:
8993 case 0x48:
8994 case 0x49:
8995 case 0x4a:
8996 case 0x4b:
8997 case 0x4c:
8998 case 0x4d:
8999 case 0x4e:
9000 case 0x4f:
9001 return rexes [pref - 0x40];
9002 case 0xf3:
9003 return "repz";
9004 case 0xf2:
9005 return "repnz";
9006 case 0xf0:
9007 return "lock";
9008 case 0x2e:
9009 return "cs";
9010 case 0x36:
9011 return "ss";
9012 case 0x3e:
9013 return "ds";
9014 case 0x26:
9015 return "es";
9016 case 0x64:
9017 return "fs";
9018 case 0x65:
9019 return "gs";
9020 case 0x66:
9021 return (sizeflag & DFLAG) ? "data16" : "data32";
9022 case 0x67:
9023 if (mode == mode_64bit)
9024 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9025 else
9026 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9027 case FWAIT_OPCODE:
9028 return "fwait";
9029 case REP_PREFIX:
9030 return "rep";
9031 case XACQUIRE_PREFIX:
9032 return "xacquire";
9033 case XRELEASE_PREFIX:
9034 return "xrelease";
9035 case BND_PREFIX:
9036 return "bnd";
9037 case NOTRACK_PREFIX:
9038 return "notrack";
9039 default:
9040 return NULL;
9041 }
9042 }
9043
9044 void
9045 print_i386_disassembler_options (FILE *stream)
9046 {
9047 fprintf (stream, _("\n\
9048 The following i386/x86-64 specific disassembler options are supported for use\n\
9049 with the -M switch (multiple options should be separated by commas):\n"));
9050
9051 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9052 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9053 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9054 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9055 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9056 fprintf (stream, _(" att-mnemonic\n"
9057 " Display instruction in AT&T mnemonic\n"));
9058 fprintf (stream, _(" intel-mnemonic\n"
9059 " Display instruction in Intel mnemonic\n"));
9060 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9061 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9062 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9063 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9064 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9065 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9066 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9067 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9068 }
9069
9070 /* Bad opcode. */
9071 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9072
9073 /* Fetch error indicator. */
9074 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
9075
9076 /* Get a pointer to struct dis386 with a valid name. */
9077
9078 static const struct dis386 *
9079 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9080 {
9081 int vindex, vex_table_index;
9082
9083 if (dp->name != NULL)
9084 return dp;
9085
9086 switch (dp->op[0].bytemode)
9087 {
9088 case USE_REG_TABLE:
9089 dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9090 break;
9091
9092 case USE_MOD_TABLE:
9093 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9094 dp = &mod_table[dp->op[1].bytemode][vindex];
9095 break;
9096
9097 case USE_RM_TABLE:
9098 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9099 break;
9100
9101 case USE_PREFIX_TABLE:
9102 if (ins->need_vex)
9103 {
9104 /* The prefix in VEX is implicit. */
9105 switch (ins->vex.prefix)
9106 {
9107 case 0:
9108 vindex = 0;
9109 break;
9110 case REPE_PREFIX_OPCODE:
9111 vindex = 1;
9112 break;
9113 case DATA_PREFIX_OPCODE:
9114 vindex = 2;
9115 break;
9116 case REPNE_PREFIX_OPCODE:
9117 vindex = 3;
9118 break;
9119 default:
9120 abort ();
9121 break;
9122 }
9123 }
9124 else
9125 {
9126 int last_prefix = -1;
9127 int prefix = 0;
9128 vindex = 0;
9129 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9130 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9131 last one wins. */
9132 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9133 {
9134 if (ins->last_repz_prefix > ins->last_repnz_prefix)
9135 {
9136 vindex = 1;
9137 prefix = PREFIX_REPZ;
9138 last_prefix = ins->last_repz_prefix;
9139 }
9140 else
9141 {
9142 vindex = 3;
9143 prefix = PREFIX_REPNZ;
9144 last_prefix = ins->last_repnz_prefix;
9145 }
9146
9147 /* Check if prefix should be ignored. */
9148 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9149 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9150 & prefix) != 0
9151 && !prefix_table[dp->op[1].bytemode][vindex].name)
9152 vindex = 0;
9153 }
9154
9155 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9156 {
9157 vindex = 2;
9158 prefix = PREFIX_DATA;
9159 last_prefix = ins->last_data_prefix;
9160 }
9161
9162 if (vindex != 0)
9163 {
9164 ins->used_prefixes |= prefix;
9165 ins->all_prefixes[last_prefix] = 0;
9166 }
9167 }
9168 dp = &prefix_table[dp->op[1].bytemode][vindex];
9169 break;
9170
9171 case USE_X86_64_TABLE:
9172 vindex = ins->address_mode == mode_64bit ? 1 : 0;
9173 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9174 break;
9175
9176 case USE_3BYTE_TABLE:
9177 if (!fetch_code (ins->info, ins->codep + 2))
9178 return &err_opcode;
9179 vindex = *ins->codep++;
9180 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9181 ins->end_codep = ins->codep;
9182 if (!fetch_modrm (ins))
9183 return &err_opcode;
9184 break;
9185
9186 case USE_VEX_LEN_TABLE:
9187 if (!ins->need_vex)
9188 abort ();
9189
9190 switch (ins->vex.length)
9191 {
9192 case 128:
9193 vindex = 0;
9194 break;
9195 case 512:
9196 /* This allows re-using in particular table entries where only
9197 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9198 if (ins->vex.evex)
9199 {
9200 case 256:
9201 vindex = 1;
9202 break;
9203 }
9204 /* Fall through. */
9205 default:
9206 abort ();
9207 break;
9208 }
9209
9210 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9211 break;
9212
9213 case USE_EVEX_LEN_TABLE:
9214 if (!ins->vex.evex)
9215 abort ();
9216
9217 switch (ins->vex.length)
9218 {
9219 case 128:
9220 vindex = 0;
9221 break;
9222 case 256:
9223 vindex = 1;
9224 break;
9225 case 512:
9226 vindex = 2;
9227 break;
9228 default:
9229 abort ();
9230 break;
9231 }
9232
9233 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9234 break;
9235
9236 case USE_XOP_8F_TABLE:
9237 if (!fetch_code (ins->info, ins->codep + 3))
9238 return &err_opcode;
9239 ins->rex = ~(*ins->codep >> 5) & 0x7;
9240
9241 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9242 switch ((*ins->codep & 0x1f))
9243 {
9244 default:
9245 dp = &bad_opcode;
9246 return dp;
9247 case 0x8:
9248 vex_table_index = XOP_08;
9249 break;
9250 case 0x9:
9251 vex_table_index = XOP_09;
9252 break;
9253 case 0xa:
9254 vex_table_index = XOP_0A;
9255 break;
9256 }
9257 ins->codep++;
9258 ins->vex.w = *ins->codep & 0x80;
9259 if (ins->vex.w && ins->address_mode == mode_64bit)
9260 ins->rex |= REX_W;
9261
9262 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9263 if (ins->address_mode != mode_64bit)
9264 {
9265 /* In 16/32-bit mode REX_B is silently ignored. */
9266 ins->rex &= ~REX_B;
9267 }
9268
9269 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9270 switch ((*ins->codep & 0x3))
9271 {
9272 case 0:
9273 break;
9274 case 1:
9275 ins->vex.prefix = DATA_PREFIX_OPCODE;
9276 break;
9277 case 2:
9278 ins->vex.prefix = REPE_PREFIX_OPCODE;
9279 break;
9280 case 3:
9281 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9282 break;
9283 }
9284 ins->need_vex = true;
9285 ins->codep++;
9286 vindex = *ins->codep++;
9287 dp = &xop_table[vex_table_index][vindex];
9288
9289 ins->end_codep = ins->codep;
9290 if (!fetch_modrm (ins))
9291 return &err_opcode;
9292
9293 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9294 having to decode the bits for every otherwise valid encoding. */
9295 if (ins->vex.prefix)
9296 return &bad_opcode;
9297 break;
9298
9299 case USE_VEX_C4_TABLE:
9300 /* VEX prefix. */
9301 if (!fetch_code (ins->info, ins->codep + 3))
9302 return &err_opcode;
9303 ins->rex = ~(*ins->codep >> 5) & 0x7;
9304 switch ((*ins->codep & 0x1f))
9305 {
9306 default:
9307 dp = &bad_opcode;
9308 return dp;
9309 case 0x1:
9310 vex_table_index = VEX_0F;
9311 break;
9312 case 0x2:
9313 vex_table_index = VEX_0F38;
9314 break;
9315 case 0x3:
9316 vex_table_index = VEX_0F3A;
9317 break;
9318 }
9319 ins->codep++;
9320 ins->vex.w = *ins->codep & 0x80;
9321 if (ins->address_mode == mode_64bit)
9322 {
9323 if (ins->vex.w)
9324 ins->rex |= REX_W;
9325 }
9326 else
9327 {
9328 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9329 is ignored, other REX bits are 0 and the highest bit in
9330 VEX.vvvv is also ignored (but we mustn't clear it here). */
9331 ins->rex = 0;
9332 }
9333 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9334 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9335 switch ((*ins->codep & 0x3))
9336 {
9337 case 0:
9338 break;
9339 case 1:
9340 ins->vex.prefix = DATA_PREFIX_OPCODE;
9341 break;
9342 case 2:
9343 ins->vex.prefix = REPE_PREFIX_OPCODE;
9344 break;
9345 case 3:
9346 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9347 break;
9348 }
9349 ins->need_vex = true;
9350 ins->codep++;
9351 vindex = *ins->codep++;
9352 dp = &vex_table[vex_table_index][vindex];
9353 ins->end_codep = ins->codep;
9354 /* There is no MODRM byte for VEX0F 77. */
9355 if ((vex_table_index != VEX_0F || vindex != 0x77)
9356 && !fetch_modrm (ins))
9357 return &err_opcode;
9358 break;
9359
9360 case USE_VEX_C5_TABLE:
9361 /* VEX prefix. */
9362 if (!fetch_code (ins->info, ins->codep + 2))
9363 return &err_opcode;
9364 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9365
9366 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9367 VEX.vvvv is 1. */
9368 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9369 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9370 switch ((*ins->codep & 0x3))
9371 {
9372 case 0:
9373 break;
9374 case 1:
9375 ins->vex.prefix = DATA_PREFIX_OPCODE;
9376 break;
9377 case 2:
9378 ins->vex.prefix = REPE_PREFIX_OPCODE;
9379 break;
9380 case 3:
9381 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9382 break;
9383 }
9384 ins->need_vex = true;
9385 ins->codep++;
9386 vindex = *ins->codep++;
9387 dp = &vex_table[dp->op[1].bytemode][vindex];
9388 ins->end_codep = ins->codep;
9389 /* There is no MODRM byte for VEX 77. */
9390 if (vindex != 0x77 && !fetch_modrm (ins))
9391 return &err_opcode;
9392 break;
9393
9394 case USE_VEX_W_TABLE:
9395 if (!ins->need_vex)
9396 abort ();
9397
9398 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9399 break;
9400
9401 case USE_EVEX_TABLE:
9402 ins->two_source_ops = false;
9403 /* EVEX prefix. */
9404 ins->vex.evex = true;
9405 if (!fetch_code (ins->info, ins->codep + 4))
9406 return &err_opcode;
9407 /* The first byte after 0x62. */
9408 ins->rex = ~(*ins->codep >> 5) & 0x7;
9409 ins->vex.r = *ins->codep & 0x10;
9410 switch ((*ins->codep & 0xf))
9411 {
9412 default:
9413 return &bad_opcode;
9414 case 0x1:
9415 vex_table_index = EVEX_0F;
9416 break;
9417 case 0x2:
9418 vex_table_index = EVEX_0F38;
9419 break;
9420 case 0x3:
9421 vex_table_index = EVEX_0F3A;
9422 break;
9423 case 0x5:
9424 vex_table_index = EVEX_MAP5;
9425 break;
9426 case 0x6:
9427 vex_table_index = EVEX_MAP6;
9428 break;
9429 }
9430
9431 /* The second byte after 0x62. */
9432 ins->codep++;
9433 ins->vex.w = *ins->codep & 0x80;
9434 if (ins->vex.w && ins->address_mode == mode_64bit)
9435 ins->rex |= REX_W;
9436
9437 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9438
9439 /* The U bit. */
9440 if (!(*ins->codep & 0x4))
9441 return &bad_opcode;
9442
9443 switch ((*ins->codep & 0x3))
9444 {
9445 case 0:
9446 break;
9447 case 1:
9448 ins->vex.prefix = DATA_PREFIX_OPCODE;
9449 break;
9450 case 2:
9451 ins->vex.prefix = REPE_PREFIX_OPCODE;
9452 break;
9453 case 3:
9454 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9455 break;
9456 }
9457
9458 /* The third byte after 0x62. */
9459 ins->codep++;
9460
9461 /* Remember the static rounding bits. */
9462 ins->vex.ll = (*ins->codep >> 5) & 3;
9463 ins->vex.b = *ins->codep & 0x10;
9464
9465 ins->vex.v = *ins->codep & 0x8;
9466 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9467 ins->vex.zeroing = *ins->codep & 0x80;
9468
9469 if (ins->address_mode != mode_64bit)
9470 {
9471 /* In 16/32-bit mode silently ignore following bits. */
9472 ins->rex &= ~REX_B;
9473 ins->vex.r = true;
9474 }
9475
9476 ins->need_vex = true;
9477 ins->codep++;
9478 vindex = *ins->codep++;
9479 dp = &evex_table[vex_table_index][vindex];
9480 ins->end_codep = ins->codep;
9481 if (!fetch_modrm (ins))
9482 return &err_opcode;
9483
9484 /* Set vector length. */
9485 if (ins->modrm.mod == 3 && ins->vex.b)
9486 ins->vex.length = 512;
9487 else
9488 {
9489 switch (ins->vex.ll)
9490 {
9491 case 0x0:
9492 ins->vex.length = 128;
9493 break;
9494 case 0x1:
9495 ins->vex.length = 256;
9496 break;
9497 case 0x2:
9498 ins->vex.length = 512;
9499 break;
9500 default:
9501 return &bad_opcode;
9502 }
9503 }
9504 break;
9505
9506 case 0:
9507 dp = &bad_opcode;
9508 break;
9509
9510 default:
9511 abort ();
9512 }
9513
9514 if (dp->name != NULL)
9515 return dp;
9516 else
9517 return get_valid_dis386 (dp, ins);
9518 }
9519
9520 static bool
9521 get_sib (instr_info *ins, int sizeflag)
9522 {
9523 /* If modrm.mod == 3, operand must be register. */
9524 if (ins->need_modrm
9525 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9526 && ins->modrm.mod != 3
9527 && ins->modrm.rm == 4)
9528 {
9529 if (!fetch_code (ins->info, ins->codep + 2))
9530 return false;
9531 ins->sib.index = (ins->codep[1] >> 3) & 7;
9532 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9533 ins->sib.base = ins->codep[1] & 7;
9534 ins->has_sib = true;
9535 }
9536 else
9537 ins->has_sib = false;
9538
9539 return true;
9540 }
9541
9542 /* Like oappend_with_style (below) but always with text style. */
9543
9544 static void
9545 oappend (instr_info *ins, const char *s)
9546 {
9547 oappend_with_style (ins, s, dis_style_text);
9548 }
9549
9550 /* Like oappend (above), but S is a string starting with '%'. In
9551 Intel syntax, the '%' is elided. */
9552
9553 static void
9554 oappend_register (instr_info *ins, const char *s)
9555 {
9556 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9557 }
9558
9559 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9560 STYLE is the default style to use in the fprintf_styled_func calls,
9561 however, FMT might include embedded style markers (see oappend_style),
9562 these embedded markers are not printed, but instead change the style
9563 used in the next fprintf_styled_func call. */
9564
9565 static void ATTRIBUTE_PRINTF_3
9566 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9567 const char *fmt, ...)
9568 {
9569 va_list ap;
9570 enum disassembler_style curr_style = style;
9571 const char *start, *curr;
9572 char staging_area[40];
9573
9574 va_start (ap, fmt);
9575 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9576 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9577 with the staging area. */
9578 if (strcmp (fmt, "%s"))
9579 {
9580 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9581
9582 va_end (ap);
9583
9584 if (res < 0)
9585 return;
9586
9587 if ((size_t) res >= sizeof (staging_area))
9588 abort ();
9589
9590 start = curr = staging_area;
9591 }
9592 else
9593 {
9594 start = curr = va_arg (ap, const char *);
9595 va_end (ap);
9596 }
9597
9598 do
9599 {
9600 if (*curr == '\0'
9601 || (*curr == STYLE_MARKER_CHAR
9602 && ISXDIGIT (*(curr + 1))
9603 && *(curr + 2) == STYLE_MARKER_CHAR))
9604 {
9605 /* Output content between our START position and CURR. */
9606 int len = curr - start;
9607 int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9608 "%.*s", len, start);
9609 if (n < 0)
9610 break;
9611
9612 if (*curr == '\0')
9613 break;
9614
9615 /* Skip over the initial STYLE_MARKER_CHAR. */
9616 ++curr;
9617
9618 /* Update the CURR_STYLE. As there are less than 16 styles, it
9619 is possible, that if the input is corrupted in some way, that
9620 we might set CURR_STYLE to an invalid value. Don't worry
9621 though, we check for this situation. */
9622 if (*curr >= '0' && *curr <= '9')
9623 curr_style = (enum disassembler_style) (*curr - '0');
9624 else if (*curr >= 'a' && *curr <= 'f')
9625 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9626 else
9627 curr_style = dis_style_text;
9628
9629 /* Check for an invalid style having been selected. This should
9630 never happen, but it doesn't hurt to be a little paranoid. */
9631 if (curr_style > dis_style_comment_start)
9632 curr_style = dis_style_text;
9633
9634 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9635 curr += 2;
9636
9637 /* Reset the START to after the style marker. */
9638 start = curr;
9639 }
9640 else
9641 ++curr;
9642 }
9643 while (true);
9644 }
9645
9646 static int
9647 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9648 {
9649 const struct dis386 *dp;
9650 int i;
9651 int ret;
9652 char *op_txt[MAX_OPERANDS];
9653 int needcomma;
9654 bool intel_swap_2_3;
9655 int sizeflag, orig_sizeflag;
9656 const char *p;
9657 struct dis_private priv;
9658 int prefix_length;
9659 int op_count;
9660 instr_info ins = {
9661 .info = info,
9662 .intel_syntax = intel_syntax >= 0
9663 ? intel_syntax
9664 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9665 .intel_mnemonic = !SYSV386_COMPAT,
9666 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9667 .start_pc = pc,
9668 .start_codep = priv.the_buffer,
9669 .codep = priv.the_buffer,
9670 .obufp = ins.obuf,
9671 .last_lock_prefix = -1,
9672 .last_repz_prefix = -1,
9673 .last_repnz_prefix = -1,
9674 .last_data_prefix = -1,
9675 .last_addr_prefix = -1,
9676 .last_rex_prefix = -1,
9677 .last_seg_prefix = -1,
9678 .fwait_prefix = -1,
9679 };
9680 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9681
9682 priv.orig_sizeflag = AFLAG | DFLAG;
9683 if ((info->mach & bfd_mach_i386_i386) != 0)
9684 ins.address_mode = mode_32bit;
9685 else if (info->mach == bfd_mach_i386_i8086)
9686 {
9687 ins.address_mode = mode_16bit;
9688 priv.orig_sizeflag = 0;
9689 }
9690 else
9691 ins.address_mode = mode_64bit;
9692
9693 for (p = info->disassembler_options; p != NULL;)
9694 {
9695 if (startswith (p, "amd64"))
9696 ins.isa64 = amd64;
9697 else if (startswith (p, "intel64"))
9698 ins.isa64 = intel64;
9699 else if (startswith (p, "x86-64"))
9700 {
9701 ins.address_mode = mode_64bit;
9702 priv.orig_sizeflag |= AFLAG | DFLAG;
9703 }
9704 else if (startswith (p, "i386"))
9705 {
9706 ins.address_mode = mode_32bit;
9707 priv.orig_sizeflag |= AFLAG | DFLAG;
9708 }
9709 else if (startswith (p, "i8086"))
9710 {
9711 ins.address_mode = mode_16bit;
9712 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9713 }
9714 else if (startswith (p, "intel"))
9715 {
9716 ins.intel_syntax = 1;
9717 if (startswith (p + 5, "-mnemonic"))
9718 ins.intel_mnemonic = true;
9719 }
9720 else if (startswith (p, "att"))
9721 {
9722 ins.intel_syntax = 0;
9723 if (startswith (p + 3, "-mnemonic"))
9724 ins.intel_mnemonic = false;
9725 }
9726 else if (startswith (p, "addr"))
9727 {
9728 if (ins.address_mode == mode_64bit)
9729 {
9730 if (p[4] == '3' && p[5] == '2')
9731 priv.orig_sizeflag &= ~AFLAG;
9732 else if (p[4] == '6' && p[5] == '4')
9733 priv.orig_sizeflag |= AFLAG;
9734 }
9735 else
9736 {
9737 if (p[4] == '1' && p[5] == '6')
9738 priv.orig_sizeflag &= ~AFLAG;
9739 else if (p[4] == '3' && p[5] == '2')
9740 priv.orig_sizeflag |= AFLAG;
9741 }
9742 }
9743 else if (startswith (p, "data"))
9744 {
9745 if (p[4] == '1' && p[5] == '6')
9746 priv.orig_sizeflag &= ~DFLAG;
9747 else if (p[4] == '3' && p[5] == '2')
9748 priv.orig_sizeflag |= DFLAG;
9749 }
9750 else if (startswith (p, "suffix"))
9751 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9752
9753 p = strchr (p, ',');
9754 if (p != NULL)
9755 p++;
9756 }
9757
9758 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9759 {
9760 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9761 return -1;
9762 }
9763
9764 if (ins.intel_syntax)
9765 {
9766 ins.open_char = '[';
9767 ins.close_char = ']';
9768 ins.separator_char = '+';
9769 ins.scale_char = '*';
9770 }
9771 else
9772 {
9773 ins.open_char = '(';
9774 ins.close_char = ')';
9775 ins.separator_char = ',';
9776 ins.scale_char = ',';
9777 }
9778
9779 /* The output looks better if we put 7 bytes on a line, since that
9780 puts most long word instructions on a single line. */
9781 info->bytes_per_line = 7;
9782
9783 info->private_data = &priv;
9784 priv.fetched = 0;
9785 priv.insn_start = pc;
9786
9787 for (i = 0; i < MAX_OPERANDS; ++i)
9788 {
9789 op_out[i][0] = 0;
9790 ins.op_out[i] = op_out[i];
9791 }
9792
9793 sizeflag = priv.orig_sizeflag;
9794
9795 switch (ckprefix (&ins))
9796 {
9797 case ckp_okay:
9798 break;
9799
9800 case ckp_bogus:
9801 /* Too many prefixes or unused REX prefixes. */
9802 for (i = 0;
9803 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9804 i++)
9805 i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9806 (i == 0 ? "" : " "),
9807 prefix_name (ins.address_mode, ins.all_prefixes[i],
9808 sizeflag));
9809 ret = i;
9810 goto out;
9811
9812 case ckp_fetch_error:
9813 goto fetch_error_out;
9814 }
9815
9816 ins.nr_prefixes = ins.codep - ins.start_codep;
9817
9818 if (!fetch_code (info, ins.codep + 1))
9819 {
9820 fetch_error_out:
9821 ret = fetch_error (&ins);
9822 goto out;
9823 }
9824
9825 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9826
9827 if ((ins.prefixes & PREFIX_FWAIT)
9828 && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9829 {
9830 /* Handle ins.prefixes before fwait. */
9831 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9832 i++)
9833 i386_dis_printf (info, dis_style_mnemonic, "%s ",
9834 prefix_name (ins.address_mode, ins.all_prefixes[i],
9835 sizeflag));
9836 i386_dis_printf (info, dis_style_mnemonic, "fwait");
9837 ret = i + 1;
9838 goto out;
9839 }
9840
9841 if (*ins.codep == 0x0f)
9842 {
9843 unsigned char threebyte;
9844
9845 ins.codep++;
9846 if (!fetch_code (info, ins.codep + 1))
9847 goto fetch_error_out;
9848 threebyte = *ins.codep;
9849 dp = &dis386_twobyte[threebyte];
9850 ins.need_modrm = twobyte_has_modrm[threebyte];
9851 ins.codep++;
9852 }
9853 else
9854 {
9855 dp = &dis386[*ins.codep];
9856 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9857 ins.codep++;
9858 }
9859
9860 /* Save sizeflag for printing the extra ins.prefixes later before updating
9861 it for mnemonic and operand processing. The prefix names depend
9862 only on the address mode. */
9863 orig_sizeflag = sizeflag;
9864 if (ins.prefixes & PREFIX_ADDR)
9865 sizeflag ^= AFLAG;
9866 if ((ins.prefixes & PREFIX_DATA))
9867 sizeflag ^= DFLAG;
9868
9869 ins.end_codep = ins.codep;
9870 if (ins.need_modrm && !fetch_modrm (&ins))
9871 goto fetch_error_out;
9872
9873 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9874 {
9875 if (!get_sib (&ins, sizeflag)
9876 || !dofloat (&ins, sizeflag))
9877 goto fetch_error_out;
9878 }
9879 else
9880 {
9881 dp = get_valid_dis386 (dp, &ins);
9882 if (dp == &err_opcode)
9883 goto fetch_error_out;
9884 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9885 {
9886 if (!get_sib (&ins, sizeflag))
9887 goto fetch_error_out;
9888 for (i = 0; i < MAX_OPERANDS; ++i)
9889 {
9890 ins.obufp = ins.op_out[i];
9891 ins.op_ad = MAX_OPERANDS - 1 - i;
9892 if (dp->op[i].rtn
9893 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9894 goto fetch_error_out;
9895 /* For EVEX instruction after the last operand masking
9896 should be printed. */
9897 if (i == 0 && ins.vex.evex)
9898 {
9899 /* Don't print {%k0}. */
9900 if (ins.vex.mask_register_specifier)
9901 {
9902 const char *reg_name
9903 = att_names_mask[ins.vex.mask_register_specifier];
9904
9905 oappend (&ins, "{");
9906 oappend_register (&ins, reg_name);
9907 oappend (&ins, "}");
9908 }
9909 if (ins.vex.zeroing)
9910 oappend (&ins, "{z}");
9911
9912 /* S/G insns require a mask and don't allow
9913 zeroing-masking. */
9914 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9915 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9916 && (ins.vex.mask_register_specifier == 0
9917 || ins.vex.zeroing))
9918 oappend (&ins, "/(bad)");
9919 }
9920 }
9921
9922 /* Check whether rounding control was enabled for an insn not
9923 supporting it. */
9924 if (ins.modrm.mod == 3 && ins.vex.b
9925 && !(ins.evex_used & EVEX_b_used))
9926 {
9927 for (i = 0; i < MAX_OPERANDS; ++i)
9928 {
9929 ins.obufp = ins.op_out[i];
9930 if (*ins.obufp)
9931 continue;
9932 oappend (&ins, names_rounding[ins.vex.ll]);
9933 oappend (&ins, "bad}");
9934 break;
9935 }
9936 }
9937 }
9938 }
9939
9940 /* Clear instruction information. */
9941 info->insn_info_valid = 0;
9942 info->branch_delay_insns = 0;
9943 info->data_size = 0;
9944 info->insn_type = dis_noninsn;
9945 info->target = 0;
9946 info->target2 = 0;
9947
9948 /* Reset jump operation indicator. */
9949 ins.op_is_jump = false;
9950 {
9951 int jump_detection = 0;
9952
9953 /* Extract flags. */
9954 for (i = 0; i < MAX_OPERANDS; ++i)
9955 {
9956 if ((dp->op[i].rtn == OP_J)
9957 || (dp->op[i].rtn == OP_indirE))
9958 jump_detection |= 1;
9959 else if ((dp->op[i].rtn == BND_Fixup)
9960 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9961 jump_detection |= 2;
9962 else if ((dp->op[i].bytemode == cond_jump_mode)
9963 || (dp->op[i].bytemode == loop_jcxz_mode))
9964 jump_detection |= 4;
9965 }
9966
9967 /* Determine if this is a jump or branch. */
9968 if ((jump_detection & 0x3) == 0x3)
9969 {
9970 ins.op_is_jump = true;
9971 if (jump_detection & 0x4)
9972 info->insn_type = dis_condbranch;
9973 else
9974 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9975 ? dis_jsr : dis_branch;
9976 }
9977 }
9978
9979 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9980 are all 0s in inverted form. */
9981 if (ins.need_vex && ins.vex.register_specifier != 0)
9982 {
9983 i386_dis_printf (info, dis_style_text, "(bad)");
9984 ret = ins.end_codep - priv.the_buffer;
9985 goto out;
9986 }
9987
9988 /* If EVEX.z is set, there must be an actual mask register in use. */
9989 if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
9990 {
9991 i386_dis_printf (info, dis_style_text, "(bad)");
9992 ret = ins.end_codep - priv.the_buffer;
9993 goto out;
9994 }
9995
9996 switch (dp->prefix_requirement)
9997 {
9998 case PREFIX_DATA:
9999 /* If only the data prefix is marked as mandatory, its absence renders
10000 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10001 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10002 {
10003 i386_dis_printf (info, dis_style_text, "(bad)");
10004 ret = ins.end_codep - priv.the_buffer;
10005 goto out;
10006 }
10007 ins.used_prefixes |= PREFIX_DATA;
10008 /* Fall through. */
10009 case PREFIX_OPCODE:
10010 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10011 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10012 used by putop and MMX/SSE operand and may be overridden by the
10013 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10014 separately. */
10015 if (((ins.need_vex
10016 ? ins.vex.prefix == REPE_PREFIX_OPCODE
10017 || ins.vex.prefix == REPNE_PREFIX_OPCODE
10018 : (ins.prefixes
10019 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10020 && (ins.used_prefixes
10021 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10022 || (((ins.need_vex
10023 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10024 : ((ins.prefixes
10025 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10026 == PREFIX_DATA))
10027 && (ins.used_prefixes & PREFIX_DATA) == 0))
10028 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10029 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10030 {
10031 i386_dis_printf (info, dis_style_text, "(bad)");
10032 ret = ins.end_codep - priv.the_buffer;
10033 goto out;
10034 }
10035 break;
10036
10037 case PREFIX_IGNORED:
10038 /* Zap data size and rep prefixes from used_prefixes and reinstate their
10039 origins in all_prefixes. */
10040 ins.used_prefixes &= ~PREFIX_OPCODE;
10041 if (ins.last_data_prefix >= 0)
10042 ins.all_prefixes[ins.last_data_prefix] = 0x66;
10043 if (ins.last_repz_prefix >= 0)
10044 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10045 if (ins.last_repnz_prefix >= 0)
10046 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10047 break;
10048 }
10049
10050 /* Check if the REX prefix is used. */
10051 if ((ins.rex ^ ins.rex_used) == 0
10052 && !ins.need_vex && ins.last_rex_prefix >= 0)
10053 ins.all_prefixes[ins.last_rex_prefix] = 0;
10054
10055 /* Check if the SEG prefix is used. */
10056 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10057 | PREFIX_FS | PREFIX_GS)) != 0
10058 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10059 ins.all_prefixes[ins.last_seg_prefix] = 0;
10060
10061 /* Check if the ADDR prefix is used. */
10062 if ((ins.prefixes & PREFIX_ADDR) != 0
10063 && (ins.used_prefixes & PREFIX_ADDR) != 0)
10064 ins.all_prefixes[ins.last_addr_prefix] = 0;
10065
10066 /* Check if the DATA prefix is used. */
10067 if ((ins.prefixes & PREFIX_DATA) != 0
10068 && (ins.used_prefixes & PREFIX_DATA) != 0
10069 && !ins.need_vex)
10070 ins.all_prefixes[ins.last_data_prefix] = 0;
10071
10072 /* Print the extra ins.prefixes. */
10073 prefix_length = 0;
10074 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10075 if (ins.all_prefixes[i])
10076 {
10077 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
10078 orig_sizeflag);
10079
10080 if (name == NULL)
10081 abort ();
10082 prefix_length += strlen (name) + 1;
10083 i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
10084 }
10085
10086 /* Check maximum code length. */
10087 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10088 {
10089 i386_dis_printf (info, dis_style_text, "(bad)");
10090 ret = MAX_CODE_LENGTH;
10091 goto out;
10092 }
10093
10094 /* Calculate the number of operands this instruction has. */
10095 op_count = 0;
10096 for (i = 0; i < MAX_OPERANDS; ++i)
10097 if (*ins.op_out[i] != '\0')
10098 ++op_count;
10099
10100 /* Calculate the number of spaces to print after the mnemonic. */
10101 ins.obufp = ins.mnemonicendp;
10102 if (op_count > 0)
10103 {
10104 i = strlen (ins.obuf) + prefix_length;
10105 if (i < 7)
10106 i = 7 - i;
10107 else
10108 i = 1;
10109 }
10110 else
10111 i = 0;
10112
10113 /* Print the instruction mnemonic along with any trailing whitespace. */
10114 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10115
10116 /* The enter and bound instructions are printed with operands in the same
10117 order as the intel book; everything else is printed in reverse order. */
10118 intel_swap_2_3 = false;
10119 if (ins.intel_syntax || ins.two_source_ops)
10120 {
10121 for (i = 0; i < MAX_OPERANDS; ++i)
10122 op_txt[i] = ins.op_out[i];
10123
10124 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10125 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10126 {
10127 op_txt[2] = ins.op_out[3];
10128 op_txt[3] = ins.op_out[2];
10129 intel_swap_2_3 = true;
10130 }
10131
10132 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10133 {
10134 bool riprel;
10135
10136 ins.op_ad = ins.op_index[i];
10137 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10138 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10139 riprel = ins.op_riprel[i];
10140 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10141 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10142 }
10143 }
10144 else
10145 {
10146 for (i = 0; i < MAX_OPERANDS; ++i)
10147 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10148 }
10149
10150 needcomma = 0;
10151 for (i = 0; i < MAX_OPERANDS; ++i)
10152 if (*op_txt[i])
10153 {
10154 /* In Intel syntax embedded rounding / SAE are not separate operands.
10155 Instead they're attached to the prior register operand. Simply
10156 suppress emission of the comma to achieve that effect. */
10157 switch (i & -(ins.intel_syntax && dp))
10158 {
10159 case 2:
10160 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10161 needcomma = 0;
10162 break;
10163 case 3:
10164 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10165 needcomma = 0;
10166 break;
10167 }
10168 if (needcomma)
10169 i386_dis_printf (info, dis_style_text, ",");
10170 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10171 {
10172 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10173
10174 if (ins.op_is_jump)
10175 {
10176 info->insn_info_valid = 1;
10177 info->branch_delay_insns = 0;
10178 info->data_size = 0;
10179 info->target = target;
10180 info->target2 = 0;
10181 }
10182 (*info->print_address_func) (target, info);
10183 }
10184 else
10185 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
10186 needcomma = 1;
10187 }
10188
10189 for (i = 0; i < MAX_OPERANDS; i++)
10190 if (ins.op_index[i] != -1 && ins.op_riprel[i])
10191 {
10192 i386_dis_printf (info, dis_style_comment_start, " # ");
10193 (*info->print_address_func)
10194 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10195 + ins.op_address[ins.op_index[i]]),
10196 info);
10197 break;
10198 }
10199 ret = ins.codep - priv.the_buffer;
10200 out:
10201 info->private_data = NULL;
10202 return ret;
10203 }
10204
10205 /* Here for backwards compatibility. When gdb stops using
10206 print_insn_i386_att and print_insn_i386_intel these functions can
10207 disappear, and print_insn_i386 be merged into print_insn. */
10208 int
10209 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10210 {
10211 return print_insn (pc, info, 0);
10212 }
10213
10214 int
10215 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10216 {
10217 return print_insn (pc, info, 1);
10218 }
10219
10220 int
10221 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10222 {
10223 return print_insn (pc, info, -1);
10224 }
10225
10226 static const char *float_mem[] = {
10227 /* d8 */
10228 "fadd{s|}",
10229 "fmul{s|}",
10230 "fcom{s|}",
10231 "fcomp{s|}",
10232 "fsub{s|}",
10233 "fsubr{s|}",
10234 "fdiv{s|}",
10235 "fdivr{s|}",
10236 /* d9 */
10237 "fld{s|}",
10238 "(bad)",
10239 "fst{s|}",
10240 "fstp{s|}",
10241 "fldenv{C|C}",
10242 "fldcw",
10243 "fNstenv{C|C}",
10244 "fNstcw",
10245 /* da */
10246 "fiadd{l|}",
10247 "fimul{l|}",
10248 "ficom{l|}",
10249 "ficomp{l|}",
10250 "fisub{l|}",
10251 "fisubr{l|}",
10252 "fidiv{l|}",
10253 "fidivr{l|}",
10254 /* db */
10255 "fild{l|}",
10256 "fisttp{l|}",
10257 "fist{l|}",
10258 "fistp{l|}",
10259 "(bad)",
10260 "fld{t|}",
10261 "(bad)",
10262 "fstp{t|}",
10263 /* dc */
10264 "fadd{l|}",
10265 "fmul{l|}",
10266 "fcom{l|}",
10267 "fcomp{l|}",
10268 "fsub{l|}",
10269 "fsubr{l|}",
10270 "fdiv{l|}",
10271 "fdivr{l|}",
10272 /* dd */
10273 "fld{l|}",
10274 "fisttp{ll|}",
10275 "fst{l||}",
10276 "fstp{l|}",
10277 "frstor{C|C}",
10278 "(bad)",
10279 "fNsave{C|C}",
10280 "fNstsw",
10281 /* de */
10282 "fiadd{s|}",
10283 "fimul{s|}",
10284 "ficom{s|}",
10285 "ficomp{s|}",
10286 "fisub{s|}",
10287 "fisubr{s|}",
10288 "fidiv{s|}",
10289 "fidivr{s|}",
10290 /* df */
10291 "fild{s|}",
10292 "fisttp{s|}",
10293 "fist{s|}",
10294 "fistp{s|}",
10295 "fbld",
10296 "fild{ll|}",
10297 "fbstp",
10298 "fistp{ll|}",
10299 };
10300
10301 static const unsigned char float_mem_mode[] = {
10302 /* d8 */
10303 d_mode,
10304 d_mode,
10305 d_mode,
10306 d_mode,
10307 d_mode,
10308 d_mode,
10309 d_mode,
10310 d_mode,
10311 /* d9 */
10312 d_mode,
10313 0,
10314 d_mode,
10315 d_mode,
10316 0,
10317 w_mode,
10318 0,
10319 w_mode,
10320 /* da */
10321 d_mode,
10322 d_mode,
10323 d_mode,
10324 d_mode,
10325 d_mode,
10326 d_mode,
10327 d_mode,
10328 d_mode,
10329 /* db */
10330 d_mode,
10331 d_mode,
10332 d_mode,
10333 d_mode,
10334 0,
10335 t_mode,
10336 0,
10337 t_mode,
10338 /* dc */
10339 q_mode,
10340 q_mode,
10341 q_mode,
10342 q_mode,
10343 q_mode,
10344 q_mode,
10345 q_mode,
10346 q_mode,
10347 /* dd */
10348 q_mode,
10349 q_mode,
10350 q_mode,
10351 q_mode,
10352 0,
10353 0,
10354 0,
10355 w_mode,
10356 /* de */
10357 w_mode,
10358 w_mode,
10359 w_mode,
10360 w_mode,
10361 w_mode,
10362 w_mode,
10363 w_mode,
10364 w_mode,
10365 /* df */
10366 w_mode,
10367 w_mode,
10368 w_mode,
10369 w_mode,
10370 t_mode,
10371 q_mode,
10372 t_mode,
10373 q_mode
10374 };
10375
10376 #define ST { OP_ST, 0 }
10377 #define STi { OP_STi, 0 }
10378
10379 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10380 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10381 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10382 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10383 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10384 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10385 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10386 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10387 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10388
10389 static const struct dis386 float_reg[][8] = {
10390 /* d8 */
10391 {
10392 { "fadd", { ST, STi }, 0 },
10393 { "fmul", { ST, STi }, 0 },
10394 { "fcom", { STi }, 0 },
10395 { "fcomp", { STi }, 0 },
10396 { "fsub", { ST, STi }, 0 },
10397 { "fsubr", { ST, STi }, 0 },
10398 { "fdiv", { ST, STi }, 0 },
10399 { "fdivr", { ST, STi }, 0 },
10400 },
10401 /* d9 */
10402 {
10403 { "fld", { STi }, 0 },
10404 { "fxch", { STi }, 0 },
10405 { FGRPd9_2 },
10406 { Bad_Opcode },
10407 { FGRPd9_4 },
10408 { FGRPd9_5 },
10409 { FGRPd9_6 },
10410 { FGRPd9_7 },
10411 },
10412 /* da */
10413 {
10414 { "fcmovb", { ST, STi }, 0 },
10415 { "fcmove", { ST, STi }, 0 },
10416 { "fcmovbe",{ ST, STi }, 0 },
10417 { "fcmovu", { ST, STi }, 0 },
10418 { Bad_Opcode },
10419 { FGRPda_5 },
10420 { Bad_Opcode },
10421 { Bad_Opcode },
10422 },
10423 /* db */
10424 {
10425 { "fcmovnb",{ ST, STi }, 0 },
10426 { "fcmovne",{ ST, STi }, 0 },
10427 { "fcmovnbe",{ ST, STi }, 0 },
10428 { "fcmovnu",{ ST, STi }, 0 },
10429 { FGRPdb_4 },
10430 { "fucomi", { ST, STi }, 0 },
10431 { "fcomi", { ST, STi }, 0 },
10432 { Bad_Opcode },
10433 },
10434 /* dc */
10435 {
10436 { "fadd", { STi, ST }, 0 },
10437 { "fmul", { STi, ST }, 0 },
10438 { Bad_Opcode },
10439 { Bad_Opcode },
10440 { "fsub{!M|r}", { STi, ST }, 0 },
10441 { "fsub{M|}", { STi, ST }, 0 },
10442 { "fdiv{!M|r}", { STi, ST }, 0 },
10443 { "fdiv{M|}", { STi, ST }, 0 },
10444 },
10445 /* dd */
10446 {
10447 { "ffree", { STi }, 0 },
10448 { Bad_Opcode },
10449 { "fst", { STi }, 0 },
10450 { "fstp", { STi }, 0 },
10451 { "fucom", { STi }, 0 },
10452 { "fucomp", { STi }, 0 },
10453 { Bad_Opcode },
10454 { Bad_Opcode },
10455 },
10456 /* de */
10457 {
10458 { "faddp", { STi, ST }, 0 },
10459 { "fmulp", { STi, ST }, 0 },
10460 { Bad_Opcode },
10461 { FGRPde_3 },
10462 { "fsub{!M|r}p", { STi, ST }, 0 },
10463 { "fsub{M|}p", { STi, ST }, 0 },
10464 { "fdiv{!M|r}p", { STi, ST }, 0 },
10465 { "fdiv{M|}p", { STi, ST }, 0 },
10466 },
10467 /* df */
10468 {
10469 { "ffreep", { STi }, 0 },
10470 { Bad_Opcode },
10471 { Bad_Opcode },
10472 { Bad_Opcode },
10473 { FGRPdf_4 },
10474 { "fucomip", { ST, STi }, 0 },
10475 { "fcomip", { ST, STi }, 0 },
10476 { Bad_Opcode },
10477 },
10478 };
10479
10480 static const char *const fgrps[][8] = {
10481 /* Bad opcode 0 */
10482 {
10483 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10484 },
10485
10486 /* d9_2 1 */
10487 {
10488 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10489 },
10490
10491 /* d9_4 2 */
10492 {
10493 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10494 },
10495
10496 /* d9_5 3 */
10497 {
10498 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10499 },
10500
10501 /* d9_6 4 */
10502 {
10503 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10504 },
10505
10506 /* d9_7 5 */
10507 {
10508 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10509 },
10510
10511 /* da_5 6 */
10512 {
10513 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10514 },
10515
10516 /* db_4 7 */
10517 {
10518 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10519 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10520 },
10521
10522 /* de_3 8 */
10523 {
10524 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10525 },
10526
10527 /* df_4 9 */
10528 {
10529 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10530 },
10531 };
10532
10533 static void
10534 swap_operand (instr_info *ins)
10535 {
10536 ins->mnemonicendp[0] = '.';
10537 ins->mnemonicendp[1] = 's';
10538 ins->mnemonicendp[2] = '\0';
10539 ins->mnemonicendp += 2;
10540 }
10541
10542 static bool
10543 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10544 int sizeflag ATTRIBUTE_UNUSED)
10545 {
10546 /* Skip mod/rm byte. */
10547 MODRM_CHECK;
10548 ins->codep++;
10549 return true;
10550 }
10551
10552 static bool
10553 dofloat (instr_info *ins, int sizeflag)
10554 {
10555 const struct dis386 *dp;
10556 unsigned char floatop = ins->codep[-1];
10557
10558 if (ins->modrm.mod != 3)
10559 {
10560 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10561
10562 putop (ins, float_mem[fp_indx], sizeflag);
10563 ins->obufp = ins->op_out[0];
10564 ins->op_ad = 2;
10565 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10566 }
10567 /* Skip mod/rm byte. */
10568 MODRM_CHECK;
10569 ins->codep++;
10570
10571 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10572 if (dp->name == NULL)
10573 {
10574 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10575
10576 /* Instruction fnstsw is only one with strange arg. */
10577 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10578 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10579 }
10580 else
10581 {
10582 putop (ins, dp->name, sizeflag);
10583
10584 ins->obufp = ins->op_out[0];
10585 ins->op_ad = 2;
10586 if (dp->op[0].rtn
10587 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10588 return false;
10589
10590 ins->obufp = ins->op_out[1];
10591 ins->op_ad = 1;
10592 if (dp->op[1].rtn
10593 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10594 return false;
10595 }
10596 return true;
10597 }
10598
10599 static bool
10600 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10601 int sizeflag ATTRIBUTE_UNUSED)
10602 {
10603 oappend_register (ins, "%st");
10604 return true;
10605 }
10606
10607 static bool
10608 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10609 int sizeflag ATTRIBUTE_UNUSED)
10610 {
10611 char scratch[8];
10612 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10613
10614 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10615 abort ();
10616 oappend_register (ins, scratch);
10617 return true;
10618 }
10619
10620 /* Capital letters in template are macros. */
10621 static int
10622 putop (instr_info *ins, const char *in_template, int sizeflag)
10623 {
10624 const char *p;
10625 int alt = 0;
10626 int cond = 1;
10627 unsigned int l = 0, len = 0;
10628 char last[4];
10629
10630 for (p = in_template; *p; p++)
10631 {
10632 if (len > l)
10633 {
10634 if (l >= sizeof (last) || !ISUPPER (*p))
10635 abort ();
10636 last[l++] = *p;
10637 continue;
10638 }
10639 switch (*p)
10640 {
10641 default:
10642 *ins->obufp++ = *p;
10643 break;
10644 case '%':
10645 len++;
10646 break;
10647 case '!':
10648 cond = 0;
10649 break;
10650 case '{':
10651 if (ins->intel_syntax)
10652 {
10653 while (*++p != '|')
10654 if (*p == '}' || *p == '\0')
10655 abort ();
10656 alt = 1;
10657 }
10658 break;
10659 case '|':
10660 while (*++p != '}')
10661 {
10662 if (*p == '\0')
10663 abort ();
10664 }
10665 break;
10666 case '}':
10667 alt = 0;
10668 break;
10669 case 'A':
10670 if (ins->intel_syntax)
10671 break;
10672 if ((ins->need_modrm && ins->modrm.mod != 3)
10673 || (sizeflag & SUFFIX_ALWAYS))
10674 *ins->obufp++ = 'b';
10675 break;
10676 case 'B':
10677 if (l == 0)
10678 {
10679 case_B:
10680 if (ins->intel_syntax)
10681 break;
10682 if (sizeflag & SUFFIX_ALWAYS)
10683 *ins->obufp++ = 'b';
10684 }
10685 else if (l == 1 && last[0] == 'L')
10686 {
10687 if (ins->address_mode == mode_64bit
10688 && !(ins->prefixes & PREFIX_ADDR))
10689 {
10690 *ins->obufp++ = 'a';
10691 *ins->obufp++ = 'b';
10692 *ins->obufp++ = 's';
10693 }
10694
10695 goto case_B;
10696 }
10697 else
10698 abort ();
10699 break;
10700 case 'C':
10701 if (ins->intel_syntax && !alt)
10702 break;
10703 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10704 {
10705 if (sizeflag & DFLAG)
10706 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10707 else
10708 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10709 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10710 }
10711 break;
10712 case 'D':
10713 if (l == 1)
10714 {
10715 switch (last[0])
10716 {
10717 case 'X':
10718 if (!ins->vex.evex || ins->vex.w)
10719 *ins->obufp++ = 'd';
10720 else
10721 oappend (ins, "{bad}");
10722 break;
10723 default:
10724 abort ();
10725 }
10726 break;
10727 }
10728 if (l)
10729 abort ();
10730 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10731 break;
10732 USED_REX (REX_W);
10733 if (ins->modrm.mod == 3)
10734 {
10735 if (ins->rex & REX_W)
10736 *ins->obufp++ = 'q';
10737 else
10738 {
10739 if (sizeflag & DFLAG)
10740 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10741 else
10742 *ins->obufp++ = 'w';
10743 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10744 }
10745 }
10746 else
10747 *ins->obufp++ = 'w';
10748 break;
10749 case 'E':
10750 if (l == 1)
10751 {
10752 switch (last[0])
10753 {
10754 case 'X':
10755 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10756 || !ins->vex.r
10757 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10758 || !ins->vex.v || ins->vex.mask_register_specifier)
10759 break;
10760 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10761 merely distinguished by EVEX.W. Look for a use of the
10762 respective macro. */
10763 if (ins->vex.w)
10764 {
10765 const char *pct = strchr (p + 1, '%');
10766
10767 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10768 break;
10769 }
10770 *ins->obufp++ = '{';
10771 *ins->obufp++ = 'e';
10772 *ins->obufp++ = 'v';
10773 *ins->obufp++ = 'e';
10774 *ins->obufp++ = 'x';
10775 *ins->obufp++ = '}';
10776 *ins->obufp++ = ' ';
10777 break;
10778 default:
10779 abort ();
10780 }
10781 break;
10782 }
10783 /* For jcxz/jecxz */
10784 if (ins->address_mode == mode_64bit)
10785 {
10786 if (sizeflag & AFLAG)
10787 *ins->obufp++ = 'r';
10788 else
10789 *ins->obufp++ = 'e';
10790 }
10791 else
10792 if (sizeflag & AFLAG)
10793 *ins->obufp++ = 'e';
10794 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10795 break;
10796 case 'F':
10797 if (ins->intel_syntax)
10798 break;
10799 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10800 {
10801 if (sizeflag & AFLAG)
10802 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10803 else
10804 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10805 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10806 }
10807 break;
10808 case 'G':
10809 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10810 && !(sizeflag & SUFFIX_ALWAYS)))
10811 break;
10812 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10813 *ins->obufp++ = 'l';
10814 else
10815 *ins->obufp++ = 'w';
10816 if (!(ins->rex & REX_W))
10817 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10818 break;
10819 case 'H':
10820 if (l == 0)
10821 {
10822 if (ins->intel_syntax)
10823 break;
10824 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10825 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10826 {
10827 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10828 *ins->obufp++ = ',';
10829 *ins->obufp++ = 'p';
10830
10831 /* Set active_seg_prefix even if not set in 64-bit mode
10832 because here it is a valid branch hint. */
10833 if (ins->prefixes & PREFIX_DS)
10834 {
10835 ins->active_seg_prefix = PREFIX_DS;
10836 *ins->obufp++ = 't';
10837 }
10838 else
10839 {
10840 ins->active_seg_prefix = PREFIX_CS;
10841 *ins->obufp++ = 'n';
10842 }
10843 }
10844 }
10845 else if (l == 1 && last[0] == 'X')
10846 {
10847 if (!ins->vex.w)
10848 *ins->obufp++ = 'h';
10849 else
10850 oappend (ins, "{bad}");
10851 }
10852 else
10853 abort ();
10854 break;
10855 case 'K':
10856 USED_REX (REX_W);
10857 if (ins->rex & REX_W)
10858 *ins->obufp++ = 'q';
10859 else
10860 *ins->obufp++ = 'd';
10861 break;
10862 case 'L':
10863 abort ();
10864 case 'M':
10865 if (ins->intel_mnemonic != cond)
10866 *ins->obufp++ = 'r';
10867 break;
10868 case 'N':
10869 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10870 *ins->obufp++ = 'n';
10871 else
10872 ins->used_prefixes |= PREFIX_FWAIT;
10873 break;
10874 case 'O':
10875 USED_REX (REX_W);
10876 if (ins->rex & REX_W)
10877 *ins->obufp++ = 'o';
10878 else if (ins->intel_syntax && (sizeflag & DFLAG))
10879 *ins->obufp++ = 'q';
10880 else
10881 *ins->obufp++ = 'd';
10882 if (!(ins->rex & REX_W))
10883 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10884 break;
10885 case '@':
10886 if (ins->address_mode == mode_64bit
10887 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10888 || !(ins->prefixes & PREFIX_DATA)))
10889 {
10890 if (sizeflag & SUFFIX_ALWAYS)
10891 *ins->obufp++ = 'q';
10892 break;
10893 }
10894 /* Fall through. */
10895 case 'P':
10896 if (l == 0)
10897 {
10898 if ((ins->modrm.mod == 3 || !cond)
10899 && !(sizeflag & SUFFIX_ALWAYS))
10900 break;
10901 /* Fall through. */
10902 case 'T':
10903 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10904 || ((sizeflag & SUFFIX_ALWAYS)
10905 && ins->address_mode != mode_64bit))
10906 {
10907 *ins->obufp++ = (sizeflag & DFLAG)
10908 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10909 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10910 }
10911 else if (sizeflag & SUFFIX_ALWAYS)
10912 *ins->obufp++ = 'q';
10913 }
10914 else if (l == 1 && last[0] == 'L')
10915 {
10916 if ((ins->prefixes & PREFIX_DATA)
10917 || (ins->rex & REX_W)
10918 || (sizeflag & SUFFIX_ALWAYS))
10919 {
10920 USED_REX (REX_W);
10921 if (ins->rex & REX_W)
10922 *ins->obufp++ = 'q';
10923 else
10924 {
10925 if (sizeflag & DFLAG)
10926 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10927 else
10928 *ins->obufp++ = 'w';
10929 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10930 }
10931 }
10932 }
10933 else
10934 abort ();
10935 break;
10936 case 'Q':
10937 if (l == 0)
10938 {
10939 if (ins->intel_syntax && !alt)
10940 break;
10941 USED_REX (REX_W);
10942 if ((ins->need_modrm && ins->modrm.mod != 3)
10943 || (sizeflag & SUFFIX_ALWAYS))
10944 {
10945 if (ins->rex & REX_W)
10946 *ins->obufp++ = 'q';
10947 else
10948 {
10949 if (sizeflag & DFLAG)
10950 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10951 else
10952 *ins->obufp++ = 'w';
10953 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10954 }
10955 }
10956 }
10957 else if (l == 1 && last[0] == 'D')
10958 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10959 else if (l == 1 && last[0] == 'L')
10960 {
10961 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10962 : ins->address_mode != mode_64bit)
10963 break;
10964 if ((ins->rex & REX_W))
10965 {
10966 USED_REX (REX_W);
10967 *ins->obufp++ = 'q';
10968 }
10969 else if ((ins->address_mode == mode_64bit && cond)
10970 || (sizeflag & SUFFIX_ALWAYS))
10971 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10972 }
10973 else
10974 abort ();
10975 break;
10976 case 'R':
10977 USED_REX (REX_W);
10978 if (ins->rex & REX_W)
10979 *ins->obufp++ = 'q';
10980 else if (sizeflag & DFLAG)
10981 {
10982 if (ins->intel_syntax)
10983 *ins->obufp++ = 'd';
10984 else
10985 *ins->obufp++ = 'l';
10986 }
10987 else
10988 *ins->obufp++ = 'w';
10989 if (ins->intel_syntax && !p[1]
10990 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10991 *ins->obufp++ = 'e';
10992 if (!(ins->rex & REX_W))
10993 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10994 break;
10995 case 'S':
10996 if (l == 0)
10997 {
10998 case_S:
10999 if (ins->intel_syntax)
11000 break;
11001 if (sizeflag & SUFFIX_ALWAYS)
11002 {
11003 if (ins->rex & REX_W)
11004 *ins->obufp++ = 'q';
11005 else
11006 {
11007 if (sizeflag & DFLAG)
11008 *ins->obufp++ = 'l';
11009 else
11010 *ins->obufp++ = 'w';
11011 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11012 }
11013 }
11014 break;
11015 }
11016 if (l != 1)
11017 abort ();
11018 switch (last[0])
11019 {
11020 case 'L':
11021 if (ins->address_mode == mode_64bit
11022 && !(ins->prefixes & PREFIX_ADDR))
11023 {
11024 *ins->obufp++ = 'a';
11025 *ins->obufp++ = 'b';
11026 *ins->obufp++ = 's';
11027 }
11028
11029 goto case_S;
11030 case 'X':
11031 if (!ins->vex.evex || !ins->vex.w)
11032 *ins->obufp++ = 's';
11033 else
11034 oappend (ins, "{bad}");
11035 break;
11036 default:
11037 abort ();
11038 }
11039 break;
11040 case 'V':
11041 if (l == 0)
11042 abort ();
11043 else if (l == 1)
11044 {
11045 switch (last[0])
11046 {
11047 case 'X':
11048 if (ins->vex.evex)
11049 break;
11050 *ins->obufp++ = '{';
11051 *ins->obufp++ = 'v';
11052 *ins->obufp++ = 'e';
11053 *ins->obufp++ = 'x';
11054 *ins->obufp++ = '}';
11055 *ins->obufp++ = ' ';
11056 break;
11057 case 'L':
11058 if (ins->rex & REX_W)
11059 {
11060 *ins->obufp++ = 'a';
11061 *ins->obufp++ = 'b';
11062 *ins->obufp++ = 's';
11063 }
11064 goto case_S;
11065 default:
11066 abort ();
11067 }
11068 }
11069 else
11070 abort ();
11071 break;
11072 case 'W':
11073 if (l == 0)
11074 {
11075 /* operand size flag for cwtl, cbtw */
11076 USED_REX (REX_W);
11077 if (ins->rex & REX_W)
11078 {
11079 if (ins->intel_syntax)
11080 *ins->obufp++ = 'd';
11081 else
11082 *ins->obufp++ = 'l';
11083 }
11084 else if (sizeflag & DFLAG)
11085 *ins->obufp++ = 'w';
11086 else
11087 *ins->obufp++ = 'b';
11088 if (!(ins->rex & REX_W))
11089 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11090 }
11091 else if (l == 1)
11092 {
11093 if (!ins->need_vex)
11094 abort ();
11095 if (last[0] == 'X')
11096 *ins->obufp++ = ins->vex.w ? 'd': 's';
11097 else if (last[0] == 'B')
11098 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11099 else
11100 abort ();
11101 }
11102 else
11103 abort ();
11104 break;
11105 case 'X':
11106 if (l != 0)
11107 abort ();
11108 if (ins->need_vex
11109 ? ins->vex.prefix == DATA_PREFIX_OPCODE
11110 : ins->prefixes & PREFIX_DATA)
11111 {
11112 *ins->obufp++ = 'd';
11113 ins->used_prefixes |= PREFIX_DATA;
11114 }
11115 else
11116 *ins->obufp++ = 's';
11117 break;
11118 case 'Y':
11119 if (l == 1 && last[0] == 'X')
11120 {
11121 if (!ins->need_vex)
11122 abort ();
11123 if (ins->intel_syntax
11124 || ((ins->modrm.mod == 3 || ins->vex.b)
11125 && !(sizeflag & SUFFIX_ALWAYS)))
11126 break;
11127 switch (ins->vex.length)
11128 {
11129 case 128:
11130 *ins->obufp++ = 'x';
11131 break;
11132 case 256:
11133 *ins->obufp++ = 'y';
11134 break;
11135 case 512:
11136 if (!ins->vex.evex)
11137 default:
11138 abort ();
11139 }
11140 }
11141 else
11142 abort ();
11143 break;
11144 case 'Z':
11145 if (l == 0)
11146 {
11147 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11148 ins->modrm.mod = 3;
11149 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11150 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11151 }
11152 else if (l == 1 && last[0] == 'X')
11153 {
11154 if (!ins->vex.evex)
11155 abort ();
11156 if (ins->intel_syntax
11157 || ((ins->modrm.mod == 3 || ins->vex.b)
11158 && !(sizeflag & SUFFIX_ALWAYS)))
11159 break;
11160 switch (ins->vex.length)
11161 {
11162 case 128:
11163 *ins->obufp++ = 'x';
11164 break;
11165 case 256:
11166 *ins->obufp++ = 'y';
11167 break;
11168 case 512:
11169 *ins->obufp++ = 'z';
11170 break;
11171 default:
11172 abort ();
11173 }
11174 }
11175 else
11176 abort ();
11177 break;
11178 case '^':
11179 if (ins->intel_syntax)
11180 break;
11181 if (ins->isa64 == intel64 && (ins->rex & REX_W))
11182 {
11183 USED_REX (REX_W);
11184 *ins->obufp++ = 'q';
11185 break;
11186 }
11187 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11188 {
11189 if (sizeflag & DFLAG)
11190 *ins->obufp++ = 'l';
11191 else
11192 *ins->obufp++ = 'w';
11193 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11194 }
11195 break;
11196 }
11197
11198 if (len == l)
11199 len = l = 0;
11200 }
11201 *ins->obufp = 0;
11202 ins->mnemonicendp = ins->obufp;
11203 return 0;
11204 }
11205
11206 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
11207 the buffer pointed to by INS->obufp has space. A style marker is made
11208 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11209 digit, followed by another STYLE_MARKER_CHAR. This function assumes
11210 that the number of styles is not greater than 16. */
11211
11212 static void
11213 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11214 {
11215 unsigned num = (unsigned) style;
11216
11217 /* We currently assume that STYLE can be encoded as a single hex
11218 character. If more styles are added then this might start to fail,
11219 and we'll need to expand this code. */
11220 if (num > 0xf)
11221 abort ();
11222
11223 *ins->obufp++ = STYLE_MARKER_CHAR;
11224 *ins->obufp++ = (num < 10 ? ('0' + num)
11225 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11226 *ins->obufp++ = STYLE_MARKER_CHAR;
11227
11228 /* This final null character is not strictly necessary, after inserting a
11229 style marker we should always be inserting some additional content.
11230 However, having the buffer null terminated doesn't cost much, and make
11231 it easier to debug what's going on. Also, if we do ever forget to add
11232 any additional content after this style marker, then the buffer will
11233 still be well formed. */
11234 *ins->obufp = '\0';
11235 }
11236
11237 static void
11238 oappend_with_style (instr_info *ins, const char *s,
11239 enum disassembler_style style)
11240 {
11241 oappend_insert_style (ins, style);
11242 ins->obufp = stpcpy (ins->obufp, s);
11243 }
11244
11245 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11246 the style for the character as STYLE. */
11247
11248 static void
11249 oappend_char_with_style (instr_info *ins, const char c,
11250 enum disassembler_style style)
11251 {
11252 oappend_insert_style (ins, style);
11253 *ins->obufp++ = c;
11254 *ins->obufp = '\0';
11255 }
11256
11257 /* Like oappend_char_with_style, but always uses dis_style_text. */
11258
11259 static void
11260 oappend_char (instr_info *ins, const char c)
11261 {
11262 oappend_char_with_style (ins, c, dis_style_text);
11263 }
11264
11265 static void
11266 append_seg (instr_info *ins)
11267 {
11268 /* Only print the active segment register. */
11269 if (!ins->active_seg_prefix)
11270 return;
11271
11272 ins->used_prefixes |= ins->active_seg_prefix;
11273 switch (ins->active_seg_prefix)
11274 {
11275 case PREFIX_CS:
11276 oappend_register (ins, att_names_seg[1]);
11277 break;
11278 case PREFIX_DS:
11279 oappend_register (ins, att_names_seg[3]);
11280 break;
11281 case PREFIX_SS:
11282 oappend_register (ins, att_names_seg[2]);
11283 break;
11284 case PREFIX_ES:
11285 oappend_register (ins, att_names_seg[0]);
11286 break;
11287 case PREFIX_FS:
11288 oappend_register (ins, att_names_seg[4]);
11289 break;
11290 case PREFIX_GS:
11291 oappend_register (ins, att_names_seg[5]);
11292 break;
11293 default:
11294 break;
11295 }
11296 oappend_char (ins, ':');
11297 }
11298
11299 static bool
11300 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11301 {
11302 if (!ins->intel_syntax)
11303 oappend (ins, "*");
11304 return OP_E (ins, bytemode, sizeflag);
11305 }
11306
11307 static void
11308 print_operand_value (instr_info *ins, bfd_vma disp,
11309 enum disassembler_style style)
11310 {
11311 char tmp[30];
11312
11313 if (ins->address_mode != mode_64bit)
11314 disp &= 0xffffffff;
11315 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11316 oappend_with_style (ins, tmp, style);
11317 }
11318
11319 /* Like oappend, but called for immediate operands. */
11320
11321 static void
11322 oappend_immediate (instr_info *ins, bfd_vma imm)
11323 {
11324 if (!ins->intel_syntax)
11325 oappend_char_with_style (ins, '$', dis_style_immediate);
11326 print_operand_value (ins, imm, dis_style_immediate);
11327 }
11328
11329 /* Put DISP in BUF as signed hex number. */
11330
11331 static void
11332 print_displacement (instr_info *ins, bfd_signed_vma val)
11333 {
11334 char tmp[30];
11335
11336 if (val < 0)
11337 {
11338 oappend_char_with_style (ins, '-', dis_style_address_offset);
11339 val = (bfd_vma) 0 - val;
11340
11341 /* Check for possible overflow. */
11342 if (val < 0)
11343 {
11344 switch (ins->address_mode)
11345 {
11346 case mode_64bit:
11347 oappend_with_style (ins, "0x8000000000000000",
11348 dis_style_address_offset);
11349 break;
11350 case mode_32bit:
11351 oappend_with_style (ins, "0x80000000",
11352 dis_style_address_offset);
11353 break;
11354 case mode_16bit:
11355 oappend_with_style (ins, "0x8000",
11356 dis_style_address_offset);
11357 break;
11358 }
11359 return;
11360 }
11361 }
11362
11363 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11364 oappend_with_style (ins, tmp, dis_style_address_offset);
11365 }
11366
11367 static void
11368 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11369 {
11370 if (ins->vex.b)
11371 {
11372 if (!ins->vex.no_broadcast)
11373 switch (bytemode)
11374 {
11375 case x_mode:
11376 case evex_half_bcst_xmmq_mode:
11377 if (ins->vex.w)
11378 oappend (ins, "QWORD BCST ");
11379 else
11380 oappend (ins, "DWORD BCST ");
11381 break;
11382 case xh_mode:
11383 case evex_half_bcst_xmmqh_mode:
11384 case evex_half_bcst_xmmqdh_mode:
11385 oappend (ins, "WORD BCST ");
11386 break;
11387 default:
11388 ins->vex.no_broadcast = true;
11389 break;
11390 }
11391 return;
11392 }
11393 switch (bytemode)
11394 {
11395 case b_mode:
11396 case b_swap_mode:
11397 case db_mode:
11398 oappend (ins, "BYTE PTR ");
11399 break;
11400 case w_mode:
11401 case w_swap_mode:
11402 case dw_mode:
11403 oappend (ins, "WORD PTR ");
11404 break;
11405 case indir_v_mode:
11406 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11407 {
11408 oappend (ins, "QWORD PTR ");
11409 break;
11410 }
11411 /* Fall through. */
11412 case stack_v_mode:
11413 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11414 || (ins->rex & REX_W)))
11415 {
11416 oappend (ins, "QWORD PTR ");
11417 break;
11418 }
11419 /* Fall through. */
11420 case v_mode:
11421 case v_swap_mode:
11422 case dq_mode:
11423 USED_REX (REX_W);
11424 if (ins->rex & REX_W)
11425 oappend (ins, "QWORD PTR ");
11426 else if (bytemode == dq_mode)
11427 oappend (ins, "DWORD PTR ");
11428 else
11429 {
11430 if (sizeflag & DFLAG)
11431 oappend (ins, "DWORD PTR ");
11432 else
11433 oappend (ins, "WORD PTR ");
11434 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11435 }
11436 break;
11437 case z_mode:
11438 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11439 *ins->obufp++ = 'D';
11440 oappend (ins, "WORD PTR ");
11441 if (!(ins->rex & REX_W))
11442 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11443 break;
11444 case a_mode:
11445 if (sizeflag & DFLAG)
11446 oappend (ins, "QWORD PTR ");
11447 else
11448 oappend (ins, "DWORD PTR ");
11449 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11450 break;
11451 case movsxd_mode:
11452 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11453 oappend (ins, "WORD PTR ");
11454 else
11455 oappend (ins, "DWORD PTR ");
11456 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11457 break;
11458 case d_mode:
11459 case d_swap_mode:
11460 oappend (ins, "DWORD PTR ");
11461 break;
11462 case q_mode:
11463 case q_swap_mode:
11464 oappend (ins, "QWORD PTR ");
11465 break;
11466 case m_mode:
11467 if (ins->address_mode == mode_64bit)
11468 oappend (ins, "QWORD PTR ");
11469 else
11470 oappend (ins, "DWORD PTR ");
11471 break;
11472 case f_mode:
11473 if (sizeflag & DFLAG)
11474 oappend (ins, "FWORD PTR ");
11475 else
11476 oappend (ins, "DWORD PTR ");
11477 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11478 break;
11479 case t_mode:
11480 oappend (ins, "TBYTE PTR ");
11481 break;
11482 case x_mode:
11483 case xh_mode:
11484 case x_swap_mode:
11485 case evex_x_gscat_mode:
11486 case evex_x_nobcst_mode:
11487 case bw_unit_mode:
11488 if (ins->need_vex)
11489 {
11490 switch (ins->vex.length)
11491 {
11492 case 128:
11493 oappend (ins, "XMMWORD PTR ");
11494 break;
11495 case 256:
11496 oappend (ins, "YMMWORD PTR ");
11497 break;
11498 case 512:
11499 oappend (ins, "ZMMWORD PTR ");
11500 break;
11501 default:
11502 abort ();
11503 }
11504 }
11505 else
11506 oappend (ins, "XMMWORD PTR ");
11507 break;
11508 case xmm_mode:
11509 oappend (ins, "XMMWORD PTR ");
11510 break;
11511 case ymm_mode:
11512 oappend (ins, "YMMWORD PTR ");
11513 break;
11514 case xmmq_mode:
11515 case evex_half_bcst_xmmqh_mode:
11516 case evex_half_bcst_xmmq_mode:
11517 if (!ins->need_vex)
11518 abort ();
11519
11520 switch (ins->vex.length)
11521 {
11522 case 128:
11523 oappend (ins, "QWORD PTR ");
11524 break;
11525 case 256:
11526 oappend (ins, "XMMWORD PTR ");
11527 break;
11528 case 512:
11529 oappend (ins, "YMMWORD PTR ");
11530 break;
11531 default:
11532 abort ();
11533 }
11534 break;
11535 case xmmdw_mode:
11536 if (!ins->need_vex)
11537 abort ();
11538
11539 switch (ins->vex.length)
11540 {
11541 case 128:
11542 oappend (ins, "WORD PTR ");
11543 break;
11544 case 256:
11545 oappend (ins, "DWORD PTR ");
11546 break;
11547 case 512:
11548 oappend (ins, "QWORD PTR ");
11549 break;
11550 default:
11551 abort ();
11552 }
11553 break;
11554 case xmmqd_mode:
11555 case evex_half_bcst_xmmqdh_mode:
11556 if (!ins->need_vex)
11557 abort ();
11558
11559 switch (ins->vex.length)
11560 {
11561 case 128:
11562 oappend (ins, "DWORD PTR ");
11563 break;
11564 case 256:
11565 oappend (ins, "QWORD PTR ");
11566 break;
11567 case 512:
11568 oappend (ins, "XMMWORD PTR ");
11569 break;
11570 default:
11571 abort ();
11572 }
11573 break;
11574 case ymmq_mode:
11575 if (!ins->need_vex)
11576 abort ();
11577
11578 switch (ins->vex.length)
11579 {
11580 case 128:
11581 oappend (ins, "QWORD PTR ");
11582 break;
11583 case 256:
11584 oappend (ins, "YMMWORD PTR ");
11585 break;
11586 case 512:
11587 oappend (ins, "ZMMWORD PTR ");
11588 break;
11589 default:
11590 abort ();
11591 }
11592 break;
11593 case o_mode:
11594 oappend (ins, "OWORD PTR ");
11595 break;
11596 case vex_vsib_d_w_dq_mode:
11597 case vex_vsib_q_w_dq_mode:
11598 if (!ins->need_vex)
11599 abort ();
11600 if (ins->vex.w)
11601 oappend (ins, "QWORD PTR ");
11602 else
11603 oappend (ins, "DWORD PTR ");
11604 break;
11605 case mask_bd_mode:
11606 if (!ins->need_vex || ins->vex.length != 128)
11607 abort ();
11608 if (ins->vex.w)
11609 oappend (ins, "DWORD PTR ");
11610 else
11611 oappend (ins, "BYTE PTR ");
11612 break;
11613 case mask_mode:
11614 if (!ins->need_vex)
11615 abort ();
11616 if (ins->vex.w)
11617 oappend (ins, "QWORD PTR ");
11618 else
11619 oappend (ins, "WORD PTR ");
11620 break;
11621 case v_bnd_mode:
11622 case v_bndmk_mode:
11623 default:
11624 break;
11625 }
11626 }
11627
11628 static void
11629 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11630 int bytemode, int sizeflag)
11631 {
11632 const char (*names)[8];
11633
11634 USED_REX (rexmask);
11635 if (ins->rex & rexmask)
11636 reg += 8;
11637
11638 switch (bytemode)
11639 {
11640 case b_mode:
11641 case b_swap_mode:
11642 if (reg & 4)
11643 USED_REX (0);
11644 if (ins->rex)
11645 names = att_names8rex;
11646 else
11647 names = att_names8;
11648 break;
11649 case w_mode:
11650 names = att_names16;
11651 break;
11652 case d_mode:
11653 case dw_mode:
11654 case db_mode:
11655 names = att_names32;
11656 break;
11657 case q_mode:
11658 names = att_names64;
11659 break;
11660 case m_mode:
11661 case v_bnd_mode:
11662 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11663 break;
11664 case bnd_mode:
11665 case bnd_swap_mode:
11666 if (reg > 0x3)
11667 {
11668 oappend (ins, "(bad)");
11669 return;
11670 }
11671 names = att_names_bnd;
11672 break;
11673 case indir_v_mode:
11674 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11675 {
11676 names = att_names64;
11677 break;
11678 }
11679 /* Fall through. */
11680 case stack_v_mode:
11681 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11682 || (ins->rex & REX_W)))
11683 {
11684 names = att_names64;
11685 break;
11686 }
11687 bytemode = v_mode;
11688 /* Fall through. */
11689 case v_mode:
11690 case v_swap_mode:
11691 case dq_mode:
11692 USED_REX (REX_W);
11693 if (ins->rex & REX_W)
11694 names = att_names64;
11695 else if (bytemode != v_mode && bytemode != v_swap_mode)
11696 names = att_names32;
11697 else
11698 {
11699 if (sizeflag & DFLAG)
11700 names = att_names32;
11701 else
11702 names = att_names16;
11703 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11704 }
11705 break;
11706 case movsxd_mode:
11707 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11708 names = att_names16;
11709 else
11710 names = att_names32;
11711 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11712 break;
11713 case va_mode:
11714 names = (ins->address_mode == mode_64bit
11715 ? att_names64 : att_names32);
11716 if (!(ins->prefixes & PREFIX_ADDR))
11717 names = (ins->address_mode == mode_16bit
11718 ? att_names16 : names);
11719 else
11720 {
11721 /* Remove "addr16/addr32". */
11722 ins->all_prefixes[ins->last_addr_prefix] = 0;
11723 names = (ins->address_mode != mode_32bit
11724 ? att_names32 : att_names16);
11725 ins->used_prefixes |= PREFIX_ADDR;
11726 }
11727 break;
11728 case mask_bd_mode:
11729 case mask_mode:
11730 if (reg > 0x7)
11731 {
11732 oappend (ins, "(bad)");
11733 return;
11734 }
11735 names = att_names_mask;
11736 break;
11737 case 0:
11738 return;
11739 default:
11740 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11741 return;
11742 }
11743 oappend_register (ins, names[reg]);
11744 }
11745
11746 static bool
11747 get8s (instr_info *ins, bfd_vma *res)
11748 {
11749 if (!fetch_code (ins->info, ins->codep + 1))
11750 return false;
11751 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11752 return true;
11753 }
11754
11755 static bool
11756 get16 (instr_info *ins, bfd_vma *res)
11757 {
11758 if (!fetch_code (ins->info, ins->codep + 2))
11759 return false;
11760 *res = *ins->codep++;
11761 *res |= (bfd_vma) *ins->codep++ << 8;
11762 return true;
11763 }
11764
11765 static bool
11766 get16s (instr_info *ins, bfd_vma *res)
11767 {
11768 if (!get16 (ins, res))
11769 return false;
11770 *res = (*res ^ 0x8000) - 0x8000;
11771 return true;
11772 }
11773
11774 static bool
11775 get32 (instr_info *ins, bfd_vma *res)
11776 {
11777 if (!fetch_code (ins->info, ins->codep + 4))
11778 return false;
11779 *res = *ins->codep++;
11780 *res |= (bfd_vma) *ins->codep++ << 8;
11781 *res |= (bfd_vma) *ins->codep++ << 16;
11782 *res |= (bfd_vma) *ins->codep++ << 24;
11783 return true;
11784 }
11785
11786 static bool
11787 get32s (instr_info *ins, bfd_vma *res)
11788 {
11789 if (!get32 (ins, res))
11790 return false;
11791
11792 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11793
11794 return true;
11795 }
11796
11797 static bool
11798 get64 (instr_info *ins, uint64_t *res)
11799 {
11800 unsigned int a;
11801 unsigned int b;
11802
11803 if (!fetch_code (ins->info, ins->codep + 8))
11804 return false;
11805 a = *ins->codep++;
11806 a |= (unsigned int) *ins->codep++ << 8;
11807 a |= (unsigned int) *ins->codep++ << 16;
11808 a |= (unsigned int) *ins->codep++ << 24;
11809 b = *ins->codep++;
11810 b |= (unsigned int) *ins->codep++ << 8;
11811 b |= (unsigned int) *ins->codep++ << 16;
11812 b |= (unsigned int) *ins->codep++ << 24;
11813 *res = a + ((uint64_t) b << 32);
11814 return true;
11815 }
11816
11817 static void
11818 set_op (instr_info *ins, bfd_vma op, bool riprel)
11819 {
11820 ins->op_index[ins->op_ad] = ins->op_ad;
11821 if (ins->address_mode == mode_64bit)
11822 ins->op_address[ins->op_ad] = op;
11823 else /* Mask to get a 32-bit address. */
11824 ins->op_address[ins->op_ad] = op & 0xffffffff;
11825 ins->op_riprel[ins->op_ad] = riprel;
11826 }
11827
11828 static bool
11829 BadOp (instr_info *ins)
11830 {
11831 /* Throw away prefixes and 1st. opcode byte. */
11832 struct dis_private *priv = ins->info->private_data;
11833
11834 ins->codep = priv->the_buffer + ins->nr_prefixes + 1;
11835 ins->obufp = stpcpy (ins->obufp, "(bad)");
11836 return true;
11837 }
11838
11839 static bool
11840 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11841 {
11842 int add = (ins->rex & REX_B) ? 8 : 0;
11843 int riprel = 0;
11844 int shift;
11845
11846 if (ins->vex.evex)
11847 {
11848 switch (bytemode)
11849 {
11850 case dw_mode:
11851 case w_mode:
11852 case w_swap_mode:
11853 shift = 1;
11854 break;
11855 case db_mode:
11856 case b_mode:
11857 shift = 0;
11858 break;
11859 case dq_mode:
11860 if (ins->address_mode != mode_64bit)
11861 {
11862 case d_mode:
11863 case d_swap_mode:
11864 shift = 2;
11865 break;
11866 }
11867 /* fall through */
11868 case vex_vsib_d_w_dq_mode:
11869 case vex_vsib_q_w_dq_mode:
11870 case evex_x_gscat_mode:
11871 shift = ins->vex.w ? 3 : 2;
11872 break;
11873 case xh_mode:
11874 case evex_half_bcst_xmmqh_mode:
11875 case evex_half_bcst_xmmqdh_mode:
11876 if (ins->vex.b)
11877 {
11878 shift = ins->vex.w ? 2 : 1;
11879 break;
11880 }
11881 /* Fall through. */
11882 case x_mode:
11883 case evex_half_bcst_xmmq_mode:
11884 if (ins->vex.b)
11885 {
11886 shift = ins->vex.w ? 3 : 2;
11887 break;
11888 }
11889 /* Fall through. */
11890 case xmmqd_mode:
11891 case xmmdw_mode:
11892 case xmmq_mode:
11893 case ymmq_mode:
11894 case evex_x_nobcst_mode:
11895 case x_swap_mode:
11896 switch (ins->vex.length)
11897 {
11898 case 128:
11899 shift = 4;
11900 break;
11901 case 256:
11902 shift = 5;
11903 break;
11904 case 512:
11905 shift = 6;
11906 break;
11907 default:
11908 abort ();
11909 }
11910 /* Make necessary corrections to shift for modes that need it. */
11911 if (bytemode == xmmq_mode
11912 || bytemode == evex_half_bcst_xmmqh_mode
11913 || bytemode == evex_half_bcst_xmmq_mode
11914 || (bytemode == ymmq_mode && ins->vex.length == 128))
11915 shift -= 1;
11916 else if (bytemode == xmmqd_mode
11917 || bytemode == evex_half_bcst_xmmqdh_mode)
11918 shift -= 2;
11919 else if (bytemode == xmmdw_mode)
11920 shift -= 3;
11921 break;
11922 case ymm_mode:
11923 shift = 5;
11924 break;
11925 case xmm_mode:
11926 shift = 4;
11927 break;
11928 case q_mode:
11929 case q_swap_mode:
11930 shift = 3;
11931 break;
11932 case bw_unit_mode:
11933 shift = ins->vex.w ? 1 : 0;
11934 break;
11935 default:
11936 abort ();
11937 }
11938 }
11939 else
11940 shift = 0;
11941
11942 USED_REX (REX_B);
11943 if (ins->intel_syntax)
11944 intel_operand_size (ins, bytemode, sizeflag);
11945 append_seg (ins);
11946
11947 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11948 {
11949 /* 32/64 bit address mode */
11950 bfd_vma disp = 0;
11951 int havedisp;
11952 int havebase;
11953 int needindex;
11954 int needaddr32;
11955 int base, rbase;
11956 int vindex = 0;
11957 int scale = 0;
11958 int addr32flag = !((sizeflag & AFLAG)
11959 || bytemode == v_bnd_mode
11960 || bytemode == v_bndmk_mode
11961 || bytemode == bnd_mode
11962 || bytemode == bnd_swap_mode);
11963 bool check_gather = false;
11964 const char (*indexes)[8] = NULL;
11965
11966 havebase = 1;
11967 base = ins->modrm.rm;
11968
11969 if (base == 4)
11970 {
11971 vindex = ins->sib.index;
11972 USED_REX (REX_X);
11973 if (ins->rex & REX_X)
11974 vindex += 8;
11975 switch (bytemode)
11976 {
11977 case vex_vsib_d_w_dq_mode:
11978 case vex_vsib_q_w_dq_mode:
11979 if (!ins->need_vex)
11980 abort ();
11981 if (ins->vex.evex)
11982 {
11983 if (!ins->vex.v)
11984 vindex += 16;
11985 check_gather = ins->obufp == ins->op_out[1];
11986 }
11987
11988 switch (ins->vex.length)
11989 {
11990 case 128:
11991 indexes = att_names_xmm;
11992 break;
11993 case 256:
11994 if (!ins->vex.w
11995 || bytemode == vex_vsib_q_w_dq_mode)
11996 indexes = att_names_ymm;
11997 else
11998 indexes = att_names_xmm;
11999 break;
12000 case 512:
12001 if (!ins->vex.w
12002 || bytemode == vex_vsib_q_w_dq_mode)
12003 indexes = att_names_zmm;
12004 else
12005 indexes = att_names_ymm;
12006 break;
12007 default:
12008 abort ();
12009 }
12010 break;
12011 default:
12012 if (vindex != 4)
12013 indexes = ins->address_mode == mode_64bit && !addr32flag
12014 ? att_names64 : att_names32;
12015 break;
12016 }
12017 scale = ins->sib.scale;
12018 base = ins->sib.base;
12019 ins->codep++;
12020 }
12021 else
12022 {
12023 /* Check for mandatory SIB. */
12024 if (bytemode == vex_vsib_d_w_dq_mode
12025 || bytemode == vex_vsib_q_w_dq_mode
12026 || bytemode == vex_sibmem_mode)
12027 {
12028 oappend (ins, "(bad)");
12029 return true;
12030 }
12031 }
12032 rbase = base + add;
12033
12034 switch (ins->modrm.mod)
12035 {
12036 case 0:
12037 if (base == 5)
12038 {
12039 havebase = 0;
12040 if (ins->address_mode == mode_64bit && !ins->has_sib)
12041 riprel = 1;
12042 if (!get32s (ins, &disp))
12043 return false;
12044 if (riprel && bytemode == v_bndmk_mode)
12045 {
12046 oappend (ins, "(bad)");
12047 return true;
12048 }
12049 }
12050 break;
12051 case 1:
12052 if (!get8s (ins, &disp))
12053 return false;
12054 if (ins->vex.evex && shift > 0)
12055 disp <<= shift;
12056 break;
12057 case 2:
12058 if (!get32s (ins, &disp))
12059 return false;
12060 break;
12061 }
12062
12063 needindex = 0;
12064 needaddr32 = 0;
12065 if (ins->has_sib
12066 && !havebase
12067 && !indexes
12068 && ins->address_mode != mode_16bit)
12069 {
12070 if (ins->address_mode == mode_64bit)
12071 {
12072 if (addr32flag)
12073 {
12074 /* Without base nor index registers, zero-extend the
12075 lower 32-bit displacement to 64 bits. */
12076 disp &= 0xffffffff;
12077 needindex = 1;
12078 }
12079 needaddr32 = 1;
12080 }
12081 else
12082 {
12083 /* In 32-bit mode, we need index register to tell [offset]
12084 from [eiz*1 + offset]. */
12085 needindex = 1;
12086 }
12087 }
12088
12089 havedisp = (havebase
12090 || needindex
12091 || (ins->has_sib && (indexes || scale != 0)));
12092
12093 if (!ins->intel_syntax)
12094 if (ins->modrm.mod != 0 || base == 5)
12095 {
12096 if (havedisp || riprel)
12097 print_displacement (ins, disp);
12098 else
12099 print_operand_value (ins, disp, dis_style_address_offset);
12100 if (riprel)
12101 {
12102 set_op (ins, disp, true);
12103 oappend_char (ins, '(');
12104 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12105 dis_style_register);
12106 oappend_char (ins, ')');
12107 }
12108 }
12109
12110 if ((havebase || indexes || needindex || needaddr32 || riprel)
12111 && (ins->address_mode != mode_64bit
12112 || ((bytemode != v_bnd_mode)
12113 && (bytemode != v_bndmk_mode)
12114 && (bytemode != bnd_mode)
12115 && (bytemode != bnd_swap_mode))))
12116 ins->used_prefixes |= PREFIX_ADDR;
12117
12118 if (havedisp || (ins->intel_syntax && riprel))
12119 {
12120 oappend_char (ins, ins->open_char);
12121 if (ins->intel_syntax && riprel)
12122 {
12123 set_op (ins, disp, true);
12124 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12125 dis_style_register);
12126 }
12127 if (havebase)
12128 oappend_register
12129 (ins,
12130 (ins->address_mode == mode_64bit && !addr32flag
12131 ? att_names64 : att_names32)[rbase]);
12132 if (ins->has_sib)
12133 {
12134 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12135 print index to tell base + index from base. */
12136 if (scale != 0
12137 || needindex
12138 || indexes
12139 || (havebase && base != ESP_REG_NUM))
12140 {
12141 if (!ins->intel_syntax || havebase)
12142 oappend_char (ins, ins->separator_char);
12143 if (indexes)
12144 {
12145 if (ins->address_mode == mode_64bit || vindex < 16)
12146 oappend_register (ins, indexes[vindex]);
12147 else
12148 oappend (ins, "(bad)");
12149 }
12150 else
12151 oappend_register (ins,
12152 ins->address_mode == mode_64bit
12153 && !addr32flag
12154 ? att_index64
12155 : att_index32);
12156
12157 oappend_char (ins, ins->scale_char);
12158 oappend_char_with_style (ins, '0' + (1 << scale),
12159 dis_style_immediate);
12160 }
12161 }
12162 if (ins->intel_syntax
12163 && (disp || ins->modrm.mod != 0 || base == 5))
12164 {
12165 if (!havedisp || (bfd_signed_vma) disp >= 0)
12166 oappend_char (ins, '+');
12167 if (havedisp)
12168 print_displacement (ins, disp);
12169 else
12170 print_operand_value (ins, disp, dis_style_address_offset);
12171 }
12172
12173 oappend_char (ins, ins->close_char);
12174
12175 if (check_gather)
12176 {
12177 /* Both XMM/YMM/ZMM registers must be distinct. */
12178 int modrm_reg = ins->modrm.reg;
12179
12180 if (ins->rex & REX_R)
12181 modrm_reg += 8;
12182 if (!ins->vex.r)
12183 modrm_reg += 16;
12184 if (vindex == modrm_reg)
12185 oappend (ins, "/(bad)");
12186 }
12187 }
12188 else if (ins->intel_syntax)
12189 {
12190 if (ins->modrm.mod != 0 || base == 5)
12191 {
12192 if (!ins->active_seg_prefix)
12193 {
12194 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12195 oappend (ins, ":");
12196 }
12197 print_operand_value (ins, disp, dis_style_text);
12198 }
12199 }
12200 }
12201 else if (bytemode == v_bnd_mode
12202 || bytemode == v_bndmk_mode
12203 || bytemode == bnd_mode
12204 || bytemode == bnd_swap_mode
12205 || bytemode == vex_vsib_d_w_dq_mode
12206 || bytemode == vex_vsib_q_w_dq_mode)
12207 {
12208 oappend (ins, "(bad)");
12209 return true;
12210 }
12211 else
12212 {
12213 /* 16 bit address mode */
12214 bfd_vma disp = 0;
12215
12216 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12217 switch (ins->modrm.mod)
12218 {
12219 case 0:
12220 if (ins->modrm.rm == 6)
12221 {
12222 case 2:
12223 if (!get16s (ins, &disp))
12224 return false;
12225 }
12226 break;
12227 case 1:
12228 if (!get8s (ins, &disp))
12229 return false;
12230 if (ins->vex.evex && shift > 0)
12231 disp <<= shift;
12232 break;
12233 }
12234
12235 if (!ins->intel_syntax)
12236 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12237 print_displacement (ins, disp);
12238
12239 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12240 {
12241 oappend_char (ins, ins->open_char);
12242 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12243 : att_index16[ins->modrm.rm]);
12244 if (ins->intel_syntax
12245 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12246 {
12247 if ((bfd_signed_vma) disp >= 0)
12248 oappend_char (ins, '+');
12249 print_displacement (ins, disp);
12250 }
12251
12252 oappend_char (ins, ins->close_char);
12253 }
12254 else if (ins->intel_syntax)
12255 {
12256 if (!ins->active_seg_prefix)
12257 {
12258 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12259 oappend (ins, ":");
12260 }
12261 print_operand_value (ins, disp & 0xffff, dis_style_text);
12262 }
12263 }
12264 if (ins->vex.b)
12265 {
12266 ins->evex_used |= EVEX_b_used;
12267
12268 /* Broadcast can only ever be valid for memory sources. */
12269 if (ins->obufp == ins->op_out[0])
12270 ins->vex.no_broadcast = true;
12271
12272 if (!ins->vex.no_broadcast
12273 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12274 {
12275 if (bytemode == xh_mode)
12276 {
12277 switch (ins->vex.length)
12278 {
12279 case 128:
12280 oappend (ins, "{1to8}");
12281 break;
12282 case 256:
12283 oappend (ins, "{1to16}");
12284 break;
12285 case 512:
12286 oappend (ins, "{1to32}");
12287 break;
12288 default:
12289 abort ();
12290 }
12291 }
12292 else if (bytemode == q_mode
12293 || bytemode == ymmq_mode)
12294 ins->vex.no_broadcast = true;
12295 else if (ins->vex.w
12296 || bytemode == evex_half_bcst_xmmqdh_mode
12297 || bytemode == evex_half_bcst_xmmq_mode)
12298 {
12299 switch (ins->vex.length)
12300 {
12301 case 128:
12302 oappend (ins, "{1to2}");
12303 break;
12304 case 256:
12305 oappend (ins, "{1to4}");
12306 break;
12307 case 512:
12308 oappend (ins, "{1to8}");
12309 break;
12310 default:
12311 abort ();
12312 }
12313 }
12314 else if (bytemode == x_mode
12315 || bytemode == evex_half_bcst_xmmqh_mode)
12316 {
12317 switch (ins->vex.length)
12318 {
12319 case 128:
12320 oappend (ins, "{1to4}");
12321 break;
12322 case 256:
12323 oappend (ins, "{1to8}");
12324 break;
12325 case 512:
12326 oappend (ins, "{1to16}");
12327 break;
12328 default:
12329 abort ();
12330 }
12331 }
12332 else
12333 ins->vex.no_broadcast = true;
12334 }
12335 if (ins->vex.no_broadcast)
12336 oappend (ins, "{bad}");
12337 }
12338
12339 return true;
12340 }
12341
12342 static bool
12343 OP_E (instr_info *ins, int bytemode, int sizeflag)
12344 {
12345 /* Skip mod/rm byte. */
12346 MODRM_CHECK;
12347 ins->codep++;
12348
12349 if (ins->modrm.mod == 3)
12350 {
12351 if ((sizeflag & SUFFIX_ALWAYS)
12352 && (bytemode == b_swap_mode
12353 || bytemode == bnd_swap_mode
12354 || bytemode == v_swap_mode))
12355 swap_operand (ins);
12356
12357 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12358 return true;
12359 }
12360
12361 return OP_E_memory (ins, bytemode, sizeflag);
12362 }
12363
12364 static bool
12365 OP_G (instr_info *ins, int bytemode, int sizeflag)
12366 {
12367 if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12368 oappend (ins, "(bad)");
12369 else
12370 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12371 return true;
12372 }
12373
12374 static bool
12375 OP_REG (instr_info *ins, int code, int sizeflag)
12376 {
12377 const char *s;
12378 int add;
12379
12380 switch (code)
12381 {
12382 case es_reg: case ss_reg: case cs_reg:
12383 case ds_reg: case fs_reg: case gs_reg:
12384 oappend_register (ins, att_names_seg[code - es_reg]);
12385 return true;
12386 }
12387
12388 USED_REX (REX_B);
12389 if (ins->rex & REX_B)
12390 add = 8;
12391 else
12392 add = 0;
12393
12394 switch (code)
12395 {
12396 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12397 case sp_reg: case bp_reg: case si_reg: case di_reg:
12398 s = att_names16[code - ax_reg + add];
12399 break;
12400 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12401 USED_REX (0);
12402 /* Fall through. */
12403 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12404 if (ins->rex)
12405 s = att_names8rex[code - al_reg + add];
12406 else
12407 s = att_names8[code - al_reg];
12408 break;
12409 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12410 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12411 if (ins->address_mode == mode_64bit
12412 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12413 {
12414 s = att_names64[code - rAX_reg + add];
12415 break;
12416 }
12417 code += eAX_reg - rAX_reg;
12418 /* Fall through. */
12419 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12420 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12421 USED_REX (REX_W);
12422 if (ins->rex & REX_W)
12423 s = att_names64[code - eAX_reg + add];
12424 else
12425 {
12426 if (sizeflag & DFLAG)
12427 s = att_names32[code - eAX_reg + add];
12428 else
12429 s = att_names16[code - eAX_reg + add];
12430 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12431 }
12432 break;
12433 default:
12434 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12435 return true;
12436 }
12437 oappend_register (ins, s);
12438 return true;
12439 }
12440
12441 static bool
12442 OP_IMREG (instr_info *ins, int code, int sizeflag)
12443 {
12444 const char *s;
12445
12446 switch (code)
12447 {
12448 case indir_dx_reg:
12449 if (!ins->intel_syntax)
12450 {
12451 oappend (ins, "(%dx)");
12452 return true;
12453 }
12454 s = att_names16[dx_reg - ax_reg];
12455 break;
12456 case al_reg: case cl_reg:
12457 s = att_names8[code - al_reg];
12458 break;
12459 case eAX_reg:
12460 USED_REX (REX_W);
12461 if (ins->rex & REX_W)
12462 {
12463 s = *att_names64;
12464 break;
12465 }
12466 /* Fall through. */
12467 case z_mode_ax_reg:
12468 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12469 s = *att_names32;
12470 else
12471 s = *att_names16;
12472 if (!(ins->rex & REX_W))
12473 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12474 break;
12475 default:
12476 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12477 return true;
12478 }
12479 oappend_register (ins, s);
12480 return true;
12481 }
12482
12483 static bool
12484 OP_I (instr_info *ins, int bytemode, int sizeflag)
12485 {
12486 bfd_vma op;
12487
12488 switch (bytemode)
12489 {
12490 case b_mode:
12491 if (!fetch_code (ins->info, ins->codep + 1))
12492 return false;
12493 op = *ins->codep++;
12494 break;
12495 case v_mode:
12496 USED_REX (REX_W);
12497 if (ins->rex & REX_W)
12498 {
12499 if (!get32s (ins, &op))
12500 return false;
12501 }
12502 else
12503 {
12504 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12505 if (sizeflag & DFLAG)
12506 {
12507 case d_mode:
12508 if (!get32 (ins, &op))
12509 return false;
12510 }
12511 else
12512 {
12513 /* Fall through. */
12514 case w_mode:
12515 if (!get16 (ins, &op))
12516 return false;
12517 }
12518 }
12519 break;
12520 case const_1_mode:
12521 if (ins->intel_syntax)
12522 oappend (ins, "1");
12523 return true;
12524 default:
12525 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12526 return true;
12527 }
12528
12529 oappend_immediate (ins, op);
12530 return true;
12531 }
12532
12533 static bool
12534 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12535 {
12536 uint64_t op;
12537
12538 if (bytemode != v_mode || ins->address_mode != mode_64bit
12539 || !(ins->rex & REX_W))
12540 return OP_I (ins, bytemode, sizeflag);
12541
12542 USED_REX (REX_W);
12543
12544 if (!get64 (ins, &op))
12545 return false;
12546
12547 oappend_immediate (ins, op);
12548 return true;
12549 }
12550
12551 static bool
12552 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12553 {
12554 bfd_vma op;
12555
12556 switch (bytemode)
12557 {
12558 case b_mode:
12559 case b_T_mode:
12560 if (!get8s (ins, &op))
12561 return false;
12562 if (bytemode == b_T_mode)
12563 {
12564 if (ins->address_mode != mode_64bit
12565 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12566 {
12567 /* The operand-size prefix is overridden by a REX prefix. */
12568 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12569 op &= 0xffffffff;
12570 else
12571 op &= 0xffff;
12572 }
12573 }
12574 else
12575 {
12576 if (!(ins->rex & REX_W))
12577 {
12578 if (sizeflag & DFLAG)
12579 op &= 0xffffffff;
12580 else
12581 op &= 0xffff;
12582 }
12583 }
12584 break;
12585 case v_mode:
12586 /* The operand-size prefix is overridden by a REX prefix. */
12587 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12588 {
12589 if (!get16 (ins, &op))
12590 return false;
12591 }
12592 else if (!get32s (ins, &op))
12593 return false;
12594 break;
12595 default:
12596 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12597 return true;
12598 }
12599
12600 oappend_immediate (ins, op);
12601 return true;
12602 }
12603
12604 static bool
12605 OP_J (instr_info *ins, int bytemode, int sizeflag)
12606 {
12607 bfd_vma disp;
12608 bfd_vma mask = -1;
12609 bfd_vma segment = 0;
12610
12611 switch (bytemode)
12612 {
12613 case b_mode:
12614 if (!get8s (ins, &disp))
12615 return false;
12616 break;
12617 case v_mode:
12618 case dqw_mode:
12619 if ((sizeflag & DFLAG)
12620 || (ins->address_mode == mode_64bit
12621 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12622 || (ins->rex & REX_W))))
12623 {
12624 if (!get32s (ins, &disp))
12625 return false;
12626 }
12627 else
12628 {
12629 if (!get16s (ins, &disp))
12630 return false;
12631 /* In 16bit mode, address is wrapped around at 64k within
12632 the same segment. Otherwise, a data16 prefix on a jump
12633 instruction means that the pc is masked to 16 bits after
12634 the displacement is added! */
12635 mask = 0xffff;
12636 if ((ins->prefixes & PREFIX_DATA) == 0)
12637 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12638 & ~((bfd_vma) 0xffff));
12639 }
12640 if (ins->address_mode != mode_64bit
12641 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12642 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12643 break;
12644 default:
12645 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12646 return true;
12647 }
12648 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12649 | segment;
12650 set_op (ins, disp, false);
12651 print_operand_value (ins, disp, dis_style_text);
12652 return true;
12653 }
12654
12655 static bool
12656 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12657 {
12658 if (bytemode == w_mode)
12659 {
12660 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12661 return true;
12662 }
12663 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12664 }
12665
12666 static bool
12667 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12668 {
12669 bfd_vma seg, offset;
12670 int res;
12671 char scratch[24];
12672
12673 if (sizeflag & DFLAG)
12674 {
12675 if (!get32 (ins, &offset))
12676 return false;;
12677 }
12678 else if (!get16 (ins, &offset))
12679 return false;
12680 if (!get16 (ins, &seg))
12681 return false;;
12682 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12683
12684 res = snprintf (scratch, ARRAY_SIZE (scratch),
12685 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12686 (unsigned) seg, (unsigned) offset);
12687 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12688 abort ();
12689 oappend (ins, scratch);
12690 return true;
12691 }
12692
12693 static bool
12694 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12695 {
12696 bfd_vma off;
12697
12698 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12699 intel_operand_size (ins, bytemode, sizeflag);
12700 append_seg (ins);
12701
12702 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12703 {
12704 if (!get32 (ins, &off))
12705 return false;
12706 }
12707 else
12708 {
12709 if (!get16 (ins, &off))
12710 return false;
12711 }
12712
12713 if (ins->intel_syntax)
12714 {
12715 if (!ins->active_seg_prefix)
12716 {
12717 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12718 oappend (ins, ":");
12719 }
12720 }
12721 print_operand_value (ins, off, dis_style_address_offset);
12722 return true;
12723 }
12724
12725 static bool
12726 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12727 {
12728 uint64_t off;
12729
12730 if (ins->address_mode != mode_64bit
12731 || (ins->prefixes & PREFIX_ADDR))
12732 return OP_OFF (ins, bytemode, sizeflag);
12733
12734 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12735 intel_operand_size (ins, bytemode, sizeflag);
12736 append_seg (ins);
12737
12738 if (!get64 (ins, &off))
12739 return false;
12740
12741 if (ins->intel_syntax)
12742 {
12743 if (!ins->active_seg_prefix)
12744 {
12745 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12746 oappend (ins, ":");
12747 }
12748 }
12749 print_operand_value (ins, off, dis_style_address_offset);
12750 return true;
12751 }
12752
12753 static void
12754 ptr_reg (instr_info *ins, int code, int sizeflag)
12755 {
12756 const char *s;
12757
12758 *ins->obufp++ = ins->open_char;
12759 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12760 if (ins->address_mode == mode_64bit)
12761 {
12762 if (!(sizeflag & AFLAG))
12763 s = att_names32[code - eAX_reg];
12764 else
12765 s = att_names64[code - eAX_reg];
12766 }
12767 else if (sizeflag & AFLAG)
12768 s = att_names32[code - eAX_reg];
12769 else
12770 s = att_names16[code - eAX_reg];
12771 oappend_register (ins, s);
12772 oappend_char (ins, ins->close_char);
12773 }
12774
12775 static bool
12776 OP_ESreg (instr_info *ins, int code, int sizeflag)
12777 {
12778 if (ins->intel_syntax)
12779 {
12780 switch (ins->codep[-1])
12781 {
12782 case 0x6d: /* insw/insl */
12783 intel_operand_size (ins, z_mode, sizeflag);
12784 break;
12785 case 0xa5: /* movsw/movsl/movsq */
12786 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12787 case 0xab: /* stosw/stosl */
12788 case 0xaf: /* scasw/scasl */
12789 intel_operand_size (ins, v_mode, sizeflag);
12790 break;
12791 default:
12792 intel_operand_size (ins, b_mode, sizeflag);
12793 }
12794 }
12795 oappend_register (ins, att_names_seg[0]);
12796 oappend_char (ins, ':');
12797 ptr_reg (ins, code, sizeflag);
12798 return true;
12799 }
12800
12801 static bool
12802 OP_DSreg (instr_info *ins, int code, int sizeflag)
12803 {
12804 if (ins->intel_syntax)
12805 {
12806 switch (ins->codep[-1])
12807 {
12808 case 0x6f: /* outsw/outsl */
12809 intel_operand_size (ins, z_mode, sizeflag);
12810 break;
12811 case 0xa5: /* movsw/movsl/movsq */
12812 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12813 case 0xad: /* lodsw/lodsl/lodsq */
12814 intel_operand_size (ins, v_mode, sizeflag);
12815 break;
12816 default:
12817 intel_operand_size (ins, b_mode, sizeflag);
12818 }
12819 }
12820 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12821 default segment register DS is printed. */
12822 if (!ins->active_seg_prefix)
12823 ins->active_seg_prefix = PREFIX_DS;
12824 append_seg (ins);
12825 ptr_reg (ins, code, sizeflag);
12826 return true;
12827 }
12828
12829 static bool
12830 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12831 int sizeflag ATTRIBUTE_UNUSED)
12832 {
12833 int add, res;
12834 char scratch[8];
12835
12836 if (ins->rex & REX_R)
12837 {
12838 USED_REX (REX_R);
12839 add = 8;
12840 }
12841 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12842 {
12843 ins->all_prefixes[ins->last_lock_prefix] = 0;
12844 ins->used_prefixes |= PREFIX_LOCK;
12845 add = 8;
12846 }
12847 else
12848 add = 0;
12849 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12850 ins->modrm.reg + add);
12851 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12852 abort ();
12853 oappend_register (ins, scratch);
12854 return true;
12855 }
12856
12857 static bool
12858 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12859 int sizeflag ATTRIBUTE_UNUSED)
12860 {
12861 int add, res;
12862 char scratch[8];
12863
12864 USED_REX (REX_R);
12865 if (ins->rex & REX_R)
12866 add = 8;
12867 else
12868 add = 0;
12869 res = snprintf (scratch, ARRAY_SIZE (scratch),
12870 ins->intel_syntax ? "dr%d" : "%%db%d",
12871 ins->modrm.reg + add);
12872 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12873 abort ();
12874 oappend (ins, scratch);
12875 return true;
12876 }
12877
12878 static bool
12879 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12880 int sizeflag ATTRIBUTE_UNUSED)
12881 {
12882 int res;
12883 char scratch[8];
12884
12885 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12886 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12887 abort ();
12888 oappend_register (ins, scratch);
12889 return true;
12890 }
12891
12892 static bool
12893 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12894 int sizeflag ATTRIBUTE_UNUSED)
12895 {
12896 int reg = ins->modrm.reg;
12897 const char (*names)[8];
12898
12899 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12900 if (ins->prefixes & PREFIX_DATA)
12901 {
12902 names = att_names_xmm;
12903 USED_REX (REX_R);
12904 if (ins->rex & REX_R)
12905 reg += 8;
12906 }
12907 else
12908 names = att_names_mm;
12909 oappend_register (ins, names[reg]);
12910 return true;
12911 }
12912
12913 static void
12914 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12915 {
12916 const char (*names)[8];
12917
12918 if (bytemode == xmmq_mode
12919 || bytemode == evex_half_bcst_xmmqh_mode
12920 || bytemode == evex_half_bcst_xmmq_mode)
12921 {
12922 switch (ins->vex.length)
12923 {
12924 case 128:
12925 case 256:
12926 names = att_names_xmm;
12927 break;
12928 case 512:
12929 names = att_names_ymm;
12930 ins->evex_used |= EVEX_len_used;
12931 break;
12932 default:
12933 abort ();
12934 }
12935 }
12936 else if (bytemode == ymm_mode)
12937 names = att_names_ymm;
12938 else if (bytemode == tmm_mode)
12939 {
12940 if (reg >= 8)
12941 {
12942 oappend (ins, "(bad)");
12943 return;
12944 }
12945 names = att_names_tmm;
12946 }
12947 else if (ins->need_vex
12948 && bytemode != xmm_mode
12949 && bytemode != scalar_mode
12950 && bytemode != xmmdw_mode
12951 && bytemode != xmmqd_mode
12952 && bytemode != evex_half_bcst_xmmqdh_mode
12953 && bytemode != w_swap_mode
12954 && bytemode != b_mode
12955 && bytemode != w_mode
12956 && bytemode != d_mode
12957 && bytemode != q_mode)
12958 {
12959 ins->evex_used |= EVEX_len_used;
12960 switch (ins->vex.length)
12961 {
12962 case 128:
12963 names = att_names_xmm;
12964 break;
12965 case 256:
12966 if (ins->vex.w
12967 || bytemode != vex_vsib_q_w_dq_mode)
12968 names = att_names_ymm;
12969 else
12970 names = att_names_xmm;
12971 break;
12972 case 512:
12973 if (ins->vex.w
12974 || bytemode != vex_vsib_q_w_dq_mode)
12975 names = att_names_zmm;
12976 else
12977 names = att_names_ymm;
12978 break;
12979 default:
12980 abort ();
12981 }
12982 }
12983 else
12984 names = att_names_xmm;
12985 oappend_register (ins, names[reg]);
12986 }
12987
12988 static bool
12989 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12990 {
12991 unsigned int reg = ins->modrm.reg;
12992
12993 USED_REX (REX_R);
12994 if (ins->rex & REX_R)
12995 reg += 8;
12996 if (ins->vex.evex)
12997 {
12998 if (!ins->vex.r)
12999 reg += 16;
13000 }
13001
13002 if (bytemode == tmm_mode)
13003 ins->modrm.reg = reg;
13004 else if (bytemode == scalar_mode)
13005 ins->vex.no_broadcast = true;
13006
13007 print_vector_reg (ins, reg, bytemode);
13008 return true;
13009 }
13010
13011 static bool
13012 OP_EM (instr_info *ins, int bytemode, int sizeflag)
13013 {
13014 int reg;
13015 const char (*names)[8];
13016
13017 if (ins->modrm.mod != 3)
13018 {
13019 if (ins->intel_syntax
13020 && (bytemode == v_mode || bytemode == v_swap_mode))
13021 {
13022 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13023 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13024 }
13025 return OP_E (ins, bytemode, sizeflag);
13026 }
13027
13028 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13029 swap_operand (ins);
13030
13031 /* Skip mod/rm byte. */
13032 MODRM_CHECK;
13033 ins->codep++;
13034 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13035 reg = ins->modrm.rm;
13036 if (ins->prefixes & PREFIX_DATA)
13037 {
13038 names = att_names_xmm;
13039 USED_REX (REX_B);
13040 if (ins->rex & REX_B)
13041 reg += 8;
13042 }
13043 else
13044 names = att_names_mm;
13045 oappend_register (ins, names[reg]);
13046 return true;
13047 }
13048
13049 /* cvt* are the only instructions in sse2 which have
13050 both SSE and MMX operands and also have 0x66 prefix
13051 in their opcode. 0x66 was originally used to differentiate
13052 between SSE and MMX instruction(operands). So we have to handle the
13053 cvt* separately using OP_EMC and OP_MXC */
13054 static bool
13055 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13056 {
13057 if (ins->modrm.mod != 3)
13058 {
13059 if (ins->intel_syntax && bytemode == v_mode)
13060 {
13061 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13062 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13063 }
13064 return OP_E (ins, bytemode, sizeflag);
13065 }
13066
13067 /* Skip mod/rm byte. */
13068 MODRM_CHECK;
13069 ins->codep++;
13070 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13071 oappend_register (ins, att_names_mm[ins->modrm.rm]);
13072 return true;
13073 }
13074
13075 static bool
13076 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13077 int sizeflag ATTRIBUTE_UNUSED)
13078 {
13079 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13080 oappend_register (ins, att_names_mm[ins->modrm.reg]);
13081 return true;
13082 }
13083
13084 static bool
13085 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13086 {
13087 int reg;
13088
13089 /* Skip mod/rm byte. */
13090 MODRM_CHECK;
13091 ins->codep++;
13092
13093 if (bytemode == dq_mode)
13094 bytemode = ins->vex.w ? q_mode : d_mode;
13095
13096 if (ins->modrm.mod != 3)
13097 return OP_E_memory (ins, bytemode, sizeflag);
13098
13099 reg = ins->modrm.rm;
13100 USED_REX (REX_B);
13101 if (ins->rex & REX_B)
13102 reg += 8;
13103 if (ins->vex.evex)
13104 {
13105 USED_REX (REX_X);
13106 if ((ins->rex & REX_X))
13107 reg += 16;
13108 }
13109
13110 if ((sizeflag & SUFFIX_ALWAYS)
13111 && (bytemode == x_swap_mode
13112 || bytemode == w_swap_mode
13113 || bytemode == d_swap_mode
13114 || bytemode == q_swap_mode))
13115 swap_operand (ins);
13116
13117 if (bytemode == tmm_mode)
13118 ins->modrm.rm = reg;
13119
13120 print_vector_reg (ins, reg, bytemode);
13121 return true;
13122 }
13123
13124 static bool
13125 OP_MS (instr_info *ins, int bytemode, int sizeflag)
13126 {
13127 if (ins->modrm.mod == 3)
13128 return OP_EM (ins, bytemode, sizeflag);
13129 return BadOp (ins);
13130 }
13131
13132 static bool
13133 OP_XS (instr_info *ins, int bytemode, int sizeflag)
13134 {
13135 if (ins->modrm.mod == 3)
13136 return OP_EX (ins, bytemode, sizeflag);
13137 return BadOp (ins);
13138 }
13139
13140 static bool
13141 OP_M (instr_info *ins, int bytemode, int sizeflag)
13142 {
13143 if (ins->modrm.mod == 3)
13144 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13145 return BadOp (ins);
13146 return OP_E (ins, bytemode, sizeflag);
13147 }
13148
13149 static bool
13150 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13151 {
13152 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13153 return BadOp (ins);
13154 return OP_E (ins, bytemode, sizeflag);
13155 }
13156
13157 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13158 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13159
13160 static bool
13161 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13162 {
13163 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13164 {
13165 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13166 return true;
13167 }
13168 if (opnd == 0)
13169 return OP_REG (ins, eAX_reg, sizeflag);
13170 return OP_IMREG (ins, eAX_reg, sizeflag);
13171 }
13172
13173 static const char *const Suffix3DNow[] = {
13174 /* 00 */ NULL, NULL, NULL, NULL,
13175 /* 04 */ NULL, NULL, NULL, NULL,
13176 /* 08 */ NULL, NULL, NULL, NULL,
13177 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13178 /* 10 */ NULL, NULL, NULL, NULL,
13179 /* 14 */ NULL, NULL, NULL, NULL,
13180 /* 18 */ NULL, NULL, NULL, NULL,
13181 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13182 /* 20 */ NULL, NULL, NULL, NULL,
13183 /* 24 */ NULL, NULL, NULL, NULL,
13184 /* 28 */ NULL, NULL, NULL, NULL,
13185 /* 2C */ NULL, NULL, NULL, NULL,
13186 /* 30 */ NULL, NULL, NULL, NULL,
13187 /* 34 */ NULL, NULL, NULL, NULL,
13188 /* 38 */ NULL, NULL, NULL, NULL,
13189 /* 3C */ NULL, NULL, NULL, NULL,
13190 /* 40 */ NULL, NULL, NULL, NULL,
13191 /* 44 */ NULL, NULL, NULL, NULL,
13192 /* 48 */ NULL, NULL, NULL, NULL,
13193 /* 4C */ NULL, NULL, NULL, NULL,
13194 /* 50 */ NULL, NULL, NULL, NULL,
13195 /* 54 */ NULL, NULL, NULL, NULL,
13196 /* 58 */ NULL, NULL, NULL, NULL,
13197 /* 5C */ NULL, NULL, NULL, NULL,
13198 /* 60 */ NULL, NULL, NULL, NULL,
13199 /* 64 */ NULL, NULL, NULL, NULL,
13200 /* 68 */ NULL, NULL, NULL, NULL,
13201 /* 6C */ NULL, NULL, NULL, NULL,
13202 /* 70 */ NULL, NULL, NULL, NULL,
13203 /* 74 */ NULL, NULL, NULL, NULL,
13204 /* 78 */ NULL, NULL, NULL, NULL,
13205 /* 7C */ NULL, NULL, NULL, NULL,
13206 /* 80 */ NULL, NULL, NULL, NULL,
13207 /* 84 */ NULL, NULL, NULL, NULL,
13208 /* 88 */ NULL, NULL, "pfnacc", NULL,
13209 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13210 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13211 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13212 /* 98 */ NULL, NULL, "pfsub", NULL,
13213 /* 9C */ NULL, NULL, "pfadd", NULL,
13214 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13215 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13216 /* A8 */ NULL, NULL, "pfsubr", NULL,
13217 /* AC */ NULL, NULL, "pfacc", NULL,
13218 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13219 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13220 /* B8 */ NULL, NULL, NULL, "pswapd",
13221 /* BC */ NULL, NULL, NULL, "pavgusb",
13222 /* C0 */ NULL, NULL, NULL, NULL,
13223 /* C4 */ NULL, NULL, NULL, NULL,
13224 /* C8 */ NULL, NULL, NULL, NULL,
13225 /* CC */ NULL, NULL, NULL, NULL,
13226 /* D0 */ NULL, NULL, NULL, NULL,
13227 /* D4 */ NULL, NULL, NULL, NULL,
13228 /* D8 */ NULL, NULL, NULL, NULL,
13229 /* DC */ NULL, NULL, NULL, NULL,
13230 /* E0 */ NULL, NULL, NULL, NULL,
13231 /* E4 */ NULL, NULL, NULL, NULL,
13232 /* E8 */ NULL, NULL, NULL, NULL,
13233 /* EC */ NULL, NULL, NULL, NULL,
13234 /* F0 */ NULL, NULL, NULL, NULL,
13235 /* F4 */ NULL, NULL, NULL, NULL,
13236 /* F8 */ NULL, NULL, NULL, NULL,
13237 /* FC */ NULL, NULL, NULL, NULL,
13238 };
13239
13240 static bool
13241 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13242 int sizeflag ATTRIBUTE_UNUSED)
13243 {
13244 const char *mnemonic;
13245
13246 if (!fetch_code (ins->info, ins->codep + 1))
13247 return false;
13248 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13249 place where an 8-bit immediate would normally go. ie. the last
13250 byte of the instruction. */
13251 ins->obufp = ins->mnemonicendp;
13252 mnemonic = Suffix3DNow[*ins->codep++];
13253 if (mnemonic)
13254 ins->obufp = stpcpy (ins->obufp, mnemonic);
13255 else
13256 {
13257 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13258 of the opcode (0x0f0f) and the opcode suffix, we need to do
13259 all the ins->modrm processing first, and don't know until now that
13260 we have a bad opcode. This necessitates some cleaning up. */
13261 ins->op_out[0][0] = '\0';
13262 ins->op_out[1][0] = '\0';
13263 BadOp (ins);
13264 }
13265 ins->mnemonicendp = ins->obufp;
13266 return true;
13267 }
13268
13269 static const struct op simd_cmp_op[] =
13270 {
13271 { STRING_COMMA_LEN ("eq") },
13272 { STRING_COMMA_LEN ("lt") },
13273 { STRING_COMMA_LEN ("le") },
13274 { STRING_COMMA_LEN ("unord") },
13275 { STRING_COMMA_LEN ("neq") },
13276 { STRING_COMMA_LEN ("nlt") },
13277 { STRING_COMMA_LEN ("nle") },
13278 { STRING_COMMA_LEN ("ord") }
13279 };
13280
13281 static const struct op vex_cmp_op[] =
13282 {
13283 { STRING_COMMA_LEN ("eq_uq") },
13284 { STRING_COMMA_LEN ("nge") },
13285 { STRING_COMMA_LEN ("ngt") },
13286 { STRING_COMMA_LEN ("false") },
13287 { STRING_COMMA_LEN ("neq_oq") },
13288 { STRING_COMMA_LEN ("ge") },
13289 { STRING_COMMA_LEN ("gt") },
13290 { STRING_COMMA_LEN ("true") },
13291 { STRING_COMMA_LEN ("eq_os") },
13292 { STRING_COMMA_LEN ("lt_oq") },
13293 { STRING_COMMA_LEN ("le_oq") },
13294 { STRING_COMMA_LEN ("unord_s") },
13295 { STRING_COMMA_LEN ("neq_us") },
13296 { STRING_COMMA_LEN ("nlt_uq") },
13297 { STRING_COMMA_LEN ("nle_uq") },
13298 { STRING_COMMA_LEN ("ord_s") },
13299 { STRING_COMMA_LEN ("eq_us") },
13300 { STRING_COMMA_LEN ("nge_uq") },
13301 { STRING_COMMA_LEN ("ngt_uq") },
13302 { STRING_COMMA_LEN ("false_os") },
13303 { STRING_COMMA_LEN ("neq_os") },
13304 { STRING_COMMA_LEN ("ge_oq") },
13305 { STRING_COMMA_LEN ("gt_oq") },
13306 { STRING_COMMA_LEN ("true_us") },
13307 };
13308
13309 static bool
13310 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13311 int sizeflag ATTRIBUTE_UNUSED)
13312 {
13313 unsigned int cmp_type;
13314
13315 if (!fetch_code (ins->info, ins->codep + 1))
13316 return false;
13317 cmp_type = *ins->codep++;
13318 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13319 {
13320 char suffix[3];
13321 char *p = ins->mnemonicendp - 2;
13322 suffix[0] = p[0];
13323 suffix[1] = p[1];
13324 suffix[2] = '\0';
13325 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13326 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13327 }
13328 else if (ins->need_vex
13329 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13330 {
13331 char suffix[3];
13332 char *p = ins->mnemonicendp - 2;
13333 suffix[0] = p[0];
13334 suffix[1] = p[1];
13335 suffix[2] = '\0';
13336 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13337 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13338 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13339 }
13340 else
13341 {
13342 /* We have a reserved extension byte. Output it directly. */
13343 oappend_immediate (ins, cmp_type);
13344 }
13345 return true;
13346 }
13347
13348 static bool
13349 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13350 {
13351 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13352 if (!ins->intel_syntax)
13353 {
13354 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13355 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13356 if (bytemode == eBX_reg)
13357 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13358 ins->two_source_ops = true;
13359 }
13360 /* Skip mod/rm byte. */
13361 MODRM_CHECK;
13362 ins->codep++;
13363 return true;
13364 }
13365
13366 static bool
13367 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13368 int sizeflag ATTRIBUTE_UNUSED)
13369 {
13370 /* monitor %{e,r,}ax,%ecx,%edx" */
13371 if (!ins->intel_syntax)
13372 {
13373 const char (*names)[8] = (ins->address_mode == mode_64bit
13374 ? att_names64 : att_names32);
13375
13376 if (ins->prefixes & PREFIX_ADDR)
13377 {
13378 /* Remove "addr16/addr32". */
13379 ins->all_prefixes[ins->last_addr_prefix] = 0;
13380 names = (ins->address_mode != mode_32bit
13381 ? att_names32 : att_names16);
13382 ins->used_prefixes |= PREFIX_ADDR;
13383 }
13384 else if (ins->address_mode == mode_16bit)
13385 names = att_names16;
13386 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13387 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13388 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13389 ins->two_source_ops = true;
13390 }
13391 /* Skip mod/rm byte. */
13392 MODRM_CHECK;
13393 ins->codep++;
13394 return true;
13395 }
13396
13397 static bool
13398 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13399 {
13400 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13401 lods and stos. */
13402 if (ins->prefixes & PREFIX_REPZ)
13403 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13404
13405 switch (bytemode)
13406 {
13407 case al_reg:
13408 case eAX_reg:
13409 case indir_dx_reg:
13410 return OP_IMREG (ins, bytemode, sizeflag);
13411 case eDI_reg:
13412 return OP_ESreg (ins, bytemode, sizeflag);
13413 case eSI_reg:
13414 return OP_DSreg (ins, bytemode, sizeflag);
13415 default:
13416 abort ();
13417 break;
13418 }
13419 return true;
13420 }
13421
13422 static bool
13423 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13424 int sizeflag ATTRIBUTE_UNUSED)
13425 {
13426 if (ins->isa64 != amd64)
13427 return true;
13428
13429 ins->obufp = ins->obuf;
13430 BadOp (ins);
13431 ins->mnemonicendp = ins->obufp;
13432 ++ins->codep;
13433 return true;
13434 }
13435
13436 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13437 "bnd". */
13438
13439 static bool
13440 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13441 int sizeflag ATTRIBUTE_UNUSED)
13442 {
13443 if (ins->prefixes & PREFIX_REPNZ)
13444 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13445 return true;
13446 }
13447
13448 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13449 "notrack". */
13450
13451 static bool
13452 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13453 int sizeflag ATTRIBUTE_UNUSED)
13454 {
13455 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13456 we've seen a PREFIX_DS. */
13457 if ((ins->prefixes & PREFIX_DS) != 0
13458 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13459 {
13460 /* NOTRACK prefix is only valid on indirect branch instructions.
13461 NB: DATA prefix is unsupported for Intel64. */
13462 ins->active_seg_prefix = 0;
13463 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13464 }
13465 return true;
13466 }
13467
13468 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13469 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13470 */
13471
13472 static bool
13473 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13474 {
13475 if (ins->modrm.mod != 3
13476 && (ins->prefixes & PREFIX_LOCK) != 0)
13477 {
13478 if (ins->prefixes & PREFIX_REPZ)
13479 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13480 if (ins->prefixes & PREFIX_REPNZ)
13481 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13482 }
13483
13484 return OP_E (ins, bytemode, sizeflag);
13485 }
13486
13487 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13488 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13489 */
13490
13491 static bool
13492 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13493 {
13494 if (ins->modrm.mod != 3)
13495 {
13496 if (ins->prefixes & PREFIX_REPZ)
13497 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13498 if (ins->prefixes & PREFIX_REPNZ)
13499 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13500 }
13501
13502 return OP_E (ins, bytemode, sizeflag);
13503 }
13504
13505 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13506 "xrelease" for memory operand. No check for LOCK prefix. */
13507
13508 static bool
13509 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13510 {
13511 if (ins->modrm.mod != 3
13512 && ins->last_repz_prefix > ins->last_repnz_prefix
13513 && (ins->prefixes & PREFIX_REPZ) != 0)
13514 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13515
13516 return OP_E (ins, bytemode, sizeflag);
13517 }
13518
13519 static bool
13520 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13521 {
13522 USED_REX (REX_W);
13523 if (ins->rex & REX_W)
13524 {
13525 /* Change cmpxchg8b to cmpxchg16b. */
13526 char *p = ins->mnemonicendp - 2;
13527 ins->mnemonicendp = stpcpy (p, "16b");
13528 bytemode = o_mode;
13529 }
13530 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13531 {
13532 if (ins->prefixes & PREFIX_REPZ)
13533 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13534 if (ins->prefixes & PREFIX_REPNZ)
13535 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13536 }
13537
13538 return OP_M (ins, bytemode, sizeflag);
13539 }
13540
13541 static bool
13542 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13543 {
13544 const char (*names)[8] = att_names_xmm;
13545
13546 if (ins->need_vex)
13547 {
13548 switch (ins->vex.length)
13549 {
13550 case 128:
13551 break;
13552 case 256:
13553 names = att_names_ymm;
13554 break;
13555 default:
13556 abort ();
13557 }
13558 }
13559 oappend_register (ins, names[reg]);
13560 return true;
13561 }
13562
13563 static bool
13564 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13565 {
13566 /* Add proper suffix to "fxsave" and "fxrstor". */
13567 USED_REX (REX_W);
13568 if (ins->rex & REX_W)
13569 {
13570 char *p = ins->mnemonicendp;
13571 *p++ = '6';
13572 *p++ = '4';
13573 *p = '\0';
13574 ins->mnemonicendp = p;
13575 }
13576 return OP_M (ins, bytemode, sizeflag);
13577 }
13578
13579 /* Display the destination register operand for instructions with
13580 VEX. */
13581
13582 static bool
13583 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13584 {
13585 int reg, modrm_reg, sib_index = -1;
13586 const char (*names)[8];
13587
13588 if (!ins->need_vex)
13589 abort ();
13590
13591 reg = ins->vex.register_specifier;
13592 ins->vex.register_specifier = 0;
13593 if (ins->address_mode != mode_64bit)
13594 {
13595 if (ins->vex.evex && !ins->vex.v)
13596 {
13597 oappend (ins, "(bad)");
13598 return true;
13599 }
13600
13601 reg &= 7;
13602 }
13603 else if (ins->vex.evex && !ins->vex.v)
13604 reg += 16;
13605
13606 switch (bytemode)
13607 {
13608 case scalar_mode:
13609 oappend_register (ins, att_names_xmm[reg]);
13610 return true;
13611
13612 case vex_vsib_d_w_dq_mode:
13613 case vex_vsib_q_w_dq_mode:
13614 /* This must be the 3rd operand. */
13615 if (ins->obufp != ins->op_out[2])
13616 abort ();
13617 if (ins->vex.length == 128
13618 || (bytemode != vex_vsib_d_w_dq_mode
13619 && !ins->vex.w))
13620 oappend_register (ins, att_names_xmm[reg]);
13621 else
13622 oappend_register (ins, att_names_ymm[reg]);
13623
13624 /* All 3 XMM/YMM registers must be distinct. */
13625 modrm_reg = ins->modrm.reg;
13626 if (ins->rex & REX_R)
13627 modrm_reg += 8;
13628
13629 if (ins->has_sib && ins->modrm.rm == 4)
13630 {
13631 sib_index = ins->sib.index;
13632 if (ins->rex & REX_X)
13633 sib_index += 8;
13634 }
13635
13636 if (reg == modrm_reg || reg == sib_index)
13637 strcpy (ins->obufp, "/(bad)");
13638 if (modrm_reg == sib_index || modrm_reg == reg)
13639 strcat (ins->op_out[0], "/(bad)");
13640 if (sib_index == modrm_reg || sib_index == reg)
13641 strcat (ins->op_out[1], "/(bad)");
13642
13643 return true;
13644
13645 case tmm_mode:
13646 /* All 3 TMM registers must be distinct. */
13647 if (reg >= 8)
13648 oappend (ins, "(bad)");
13649 else
13650 {
13651 /* This must be the 3rd operand. */
13652 if (ins->obufp != ins->op_out[2])
13653 abort ();
13654 oappend_register (ins, att_names_tmm[reg]);
13655 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13656 strcpy (ins->obufp, "/(bad)");
13657 }
13658
13659 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13660 || ins->modrm.rm == reg)
13661 {
13662 if (ins->modrm.reg <= 8
13663 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13664 strcat (ins->op_out[0], "/(bad)");
13665 if (ins->modrm.rm <= 8
13666 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13667 strcat (ins->op_out[1], "/(bad)");
13668 }
13669
13670 return true;
13671 }
13672
13673 switch (ins->vex.length)
13674 {
13675 case 128:
13676 switch (bytemode)
13677 {
13678 case x_mode:
13679 names = att_names_xmm;
13680 ins->evex_used |= EVEX_len_used;
13681 break;
13682 case dq_mode:
13683 if (ins->rex & REX_W)
13684 names = att_names64;
13685 else
13686 names = att_names32;
13687 break;
13688 case mask_bd_mode:
13689 case mask_mode:
13690 if (reg > 0x7)
13691 {
13692 oappend (ins, "(bad)");
13693 return true;
13694 }
13695 names = att_names_mask;
13696 break;
13697 default:
13698 abort ();
13699 return true;
13700 }
13701 break;
13702 case 256:
13703 switch (bytemode)
13704 {
13705 case x_mode:
13706 names = att_names_ymm;
13707 ins->evex_used |= EVEX_len_used;
13708 break;
13709 case mask_bd_mode:
13710 case mask_mode:
13711 if (reg <= 0x7)
13712 {
13713 names = att_names_mask;
13714 break;
13715 }
13716 /* Fall through. */
13717 default:
13718 /* See PR binutils/20893 for a reproducer. */
13719 oappend (ins, "(bad)");
13720 return true;
13721 }
13722 break;
13723 case 512:
13724 names = att_names_zmm;
13725 ins->evex_used |= EVEX_len_used;
13726 break;
13727 default:
13728 abort ();
13729 break;
13730 }
13731 oappend_register (ins, names[reg]);
13732 return true;
13733 }
13734
13735 static bool
13736 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13737 {
13738 if (ins->modrm.mod == 3)
13739 return OP_VEX (ins, bytemode, sizeflag);
13740 return true;
13741 }
13742
13743 static bool
13744 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13745 {
13746 OP_VEX (ins, bytemode, sizeflag);
13747
13748 if (ins->vex.w)
13749 {
13750 /* Swap 2nd and 3rd operands. */
13751 char *tmp = ins->op_out[2];
13752
13753 ins->op_out[2] = ins->op_out[1];
13754 ins->op_out[1] = tmp;
13755 }
13756 return true;
13757 }
13758
13759 static bool
13760 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13761 {
13762 int reg;
13763 const char (*names)[8] = att_names_xmm;
13764
13765 if (!fetch_code (ins->info, ins->codep + 1))
13766 return false;
13767 reg = *ins->codep++;
13768
13769 if (bytemode != x_mode && bytemode != scalar_mode)
13770 abort ();
13771
13772 reg >>= 4;
13773 if (ins->address_mode != mode_64bit)
13774 reg &= 7;
13775
13776 if (bytemode == x_mode && ins->vex.length == 256)
13777 names = att_names_ymm;
13778
13779 oappend_register (ins, names[reg]);
13780
13781 if (ins->vex.w)
13782 {
13783 /* Swap 3rd and 4th operands. */
13784 char *tmp = ins->op_out[3];
13785
13786 ins->op_out[3] = ins->op_out[2];
13787 ins->op_out[2] = tmp;
13788 }
13789 return true;
13790 }
13791
13792 static bool
13793 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13794 int sizeflag ATTRIBUTE_UNUSED)
13795 {
13796 oappend_immediate (ins, ins->codep[-1] & 0xf);
13797 return true;
13798 }
13799
13800 static bool
13801 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13802 int sizeflag ATTRIBUTE_UNUSED)
13803 {
13804 unsigned int cmp_type;
13805
13806 if (!ins->vex.evex)
13807 abort ();
13808
13809 if (!fetch_code (ins->info, ins->codep + 1))
13810 return false;
13811 cmp_type = *ins->codep++;
13812 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13813 If it's the case, print suffix, otherwise - print the immediate. */
13814 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13815 && cmp_type != 3
13816 && cmp_type != 7)
13817 {
13818 char suffix[3];
13819 char *p = ins->mnemonicendp - 2;
13820
13821 /* vpcmp* can have both one- and two-lettered suffix. */
13822 if (p[0] == 'p')
13823 {
13824 p++;
13825 suffix[0] = p[0];
13826 suffix[1] = '\0';
13827 }
13828 else
13829 {
13830 suffix[0] = p[0];
13831 suffix[1] = p[1];
13832 suffix[2] = '\0';
13833 }
13834
13835 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13836 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13837 }
13838 else
13839 {
13840 /* We have a reserved extension byte. Output it directly. */
13841 oappend_immediate (ins, cmp_type);
13842 }
13843 return true;
13844 }
13845
13846 static const struct op xop_cmp_op[] =
13847 {
13848 { STRING_COMMA_LEN ("lt") },
13849 { STRING_COMMA_LEN ("le") },
13850 { STRING_COMMA_LEN ("gt") },
13851 { STRING_COMMA_LEN ("ge") },
13852 { STRING_COMMA_LEN ("eq") },
13853 { STRING_COMMA_LEN ("neq") },
13854 { STRING_COMMA_LEN ("false") },
13855 { STRING_COMMA_LEN ("true") }
13856 };
13857
13858 static bool
13859 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13860 int sizeflag ATTRIBUTE_UNUSED)
13861 {
13862 unsigned int cmp_type;
13863
13864 if (!fetch_code (ins->info, ins->codep + 1))
13865 return false;
13866 cmp_type = *ins->codep++;
13867 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13868 {
13869 char suffix[3];
13870 char *p = ins->mnemonicendp - 2;
13871
13872 /* vpcom* can have both one- and two-lettered suffix. */
13873 if (p[0] == 'm')
13874 {
13875 p++;
13876 suffix[0] = p[0];
13877 suffix[1] = '\0';
13878 }
13879 else
13880 {
13881 suffix[0] = p[0];
13882 suffix[1] = p[1];
13883 suffix[2] = '\0';
13884 }
13885
13886 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13887 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13888 }
13889 else
13890 {
13891 /* We have a reserved extension byte. Output it directly. */
13892 oappend_immediate (ins, cmp_type);
13893 }
13894 return true;
13895 }
13896
13897 static const struct op pclmul_op[] =
13898 {
13899 { STRING_COMMA_LEN ("lql") },
13900 { STRING_COMMA_LEN ("hql") },
13901 { STRING_COMMA_LEN ("lqh") },
13902 { STRING_COMMA_LEN ("hqh") }
13903 };
13904
13905 static bool
13906 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13907 int sizeflag ATTRIBUTE_UNUSED)
13908 {
13909 unsigned int pclmul_type;
13910
13911 if (!fetch_code (ins->info, ins->codep + 1))
13912 return false;
13913 pclmul_type = *ins->codep++;
13914 switch (pclmul_type)
13915 {
13916 case 0x10:
13917 pclmul_type = 2;
13918 break;
13919 case 0x11:
13920 pclmul_type = 3;
13921 break;
13922 default:
13923 break;
13924 }
13925 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13926 {
13927 char suffix[4];
13928 char *p = ins->mnemonicendp - 3;
13929 suffix[0] = p[0];
13930 suffix[1] = p[1];
13931 suffix[2] = p[2];
13932 suffix[3] = '\0';
13933 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13934 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13935 }
13936 else
13937 {
13938 /* We have a reserved extension byte. Output it directly. */
13939 oappend_immediate (ins, pclmul_type);
13940 }
13941 return true;
13942 }
13943
13944 static bool
13945 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13946 {
13947 /* Add proper suffix to "movsxd". */
13948 char *p = ins->mnemonicendp;
13949
13950 switch (bytemode)
13951 {
13952 case movsxd_mode:
13953 if (!ins->intel_syntax)
13954 {
13955 USED_REX (REX_W);
13956 if (ins->rex & REX_W)
13957 {
13958 *p++ = 'l';
13959 *p++ = 'q';
13960 break;
13961 }
13962 }
13963
13964 *p++ = 'x';
13965 *p++ = 'd';
13966 break;
13967 default:
13968 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13969 break;
13970 }
13971
13972 ins->mnemonicendp = p;
13973 *p = '\0';
13974 return OP_E (ins, bytemode, sizeflag);
13975 }
13976
13977 static bool
13978 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13979 {
13980 unsigned int reg = ins->vex.register_specifier;
13981 unsigned int modrm_reg = ins->modrm.reg;
13982 unsigned int modrm_rm = ins->modrm.rm;
13983
13984 /* Calc destination register number. */
13985 if (ins->rex & REX_R)
13986 modrm_reg += 8;
13987 if (!ins->vex.r)
13988 modrm_reg += 16;
13989
13990 /* Calc src1 register number. */
13991 if (ins->address_mode != mode_64bit)
13992 reg &= 7;
13993 else if (ins->vex.evex && !ins->vex.v)
13994 reg += 16;
13995
13996 /* Calc src2 register number. */
13997 if (ins->modrm.mod == 3)
13998 {
13999 if (ins->rex & REX_B)
14000 modrm_rm += 8;
14001 if (ins->rex & REX_X)
14002 modrm_rm += 16;
14003 }
14004
14005 /* Destination and source registers must be distinct, output bad if
14006 dest == src1 or dest == src2. */
14007 if (modrm_reg == reg
14008 || (ins->modrm.mod == 3
14009 && modrm_reg == modrm_rm))
14010 {
14011 oappend (ins, "(bad)");
14012 return true;
14013 }
14014 return OP_XMM (ins, bytemode, sizeflag);
14015 }
14016
14017 static bool
14018 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14019 {
14020 if (ins->modrm.mod != 3 || !ins->vex.b)
14021 return true;
14022
14023 switch (bytemode)
14024 {
14025 case evex_rounding_64_mode:
14026 if (ins->address_mode != mode_64bit || !ins->vex.w)
14027 return true;
14028 /* Fall through. */
14029 case evex_rounding_mode:
14030 ins->evex_used |= EVEX_b_used;
14031 oappend (ins, names_rounding[ins->vex.ll]);
14032 break;
14033 case evex_sae_mode:
14034 ins->evex_used |= EVEX_b_used;
14035 oappend (ins, "{");
14036 break;
14037 default:
14038 abort ();
14039 }
14040 oappend (ins, "sae}");
14041 return true;
14042 }
14043
14044 static bool
14045 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14046 {
14047 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14048 {
14049 if (ins->intel_syntax)
14050 {
14051 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
14052 }
14053 else
14054 {
14055 USED_REX (REX_W);
14056 if (ins->rex & REX_W)
14057 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
14058 else
14059 {
14060 if (sizeflag & DFLAG)
14061 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
14062 else
14063 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
14064 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14065 }
14066 }
14067 bytemode = v_mode;
14068 }
14069
14070 return OP_M (ins, bytemode, sizeflag);
14071 }
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