opcodes/v850-opc.c

   1 #include "ansidecl.h"
   2 #include "opcode/v850.h"
   3
   4 /* TODO:
   5
   6    * ld.h, ld.w st.h and st.w will need special insert/extract code.
   7
   8    * All sld instructions will need special insert/extrat code. */
   9
  10 /* Local insertion and extraction functions.  */
  11 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
  12 static long extract_d9 PARAMS ((unsigned long, int *));
  13 static unsigned long insert_d22 PARAMS ((unsigned long, long, const char **));
  14 static long extract_d22 PARAMS ((unsigned long, int *));
  15
  16 /* regular opcode */
  17 #define OP(x)           ((x & 0x3f) << 5)
  18 #define OP_MASK         OP(0x3f)
  19
  20 /* conditional branch opcode */
  21 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  22 #define BOP_MASK        ((0x0b << 7) | 0x0f)
  23
  24 /* one-word opcodes */
  25 #define one(x)          ((unsigned int) (x))
  26
  27 /* two-word opcodes */
  28 #define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
  29
  30
  31 \f
  32 const struct v850_operand v850_operands[] = {
  33 #define UNUSED  0
  34   { 0, 0, 0, 0, 0 },
  35
  36 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  37 #define R1      (UNUSED+1)
  38   { 5, 0, 0, 0, V850_OPERAND_REG },
  39
  40 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  41 #define R2      (R1+1)
  42   { 5, 11, 0, 0, V850_OPERAND_REG },
  43
  44 /* The IMM5 field in a format 2 insn. */
  45 #define I5      (R2+1)
  46   { 5, 0, 0, 0, V850_OPERAND_SIGNED },
  47
  48 #define I5U     (I5+1)
  49   { 5, 0, 0, 0, 0 },
  50
  51 /* The IMM16 field in a format 6 insn. */
  52 #define I16     (I5U+1)
  53   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  54
  55 /* The signed DISP7 field in a format 4 insn. */
  56 #define D7S     (I16+1)
  57   { 7, 0, 0, 0, V850_OPERAND_SIGNED },
  58
  59 /* The DISP9 field in a format 3 insn. */
  60 #define D9      (D7S+1)
  61   { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
  62
  63 /* The DISP16 field in a format 6 insn. */
  64 #define D16     (D9+1)
  65   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  66
  67 /* The DISP22 field in a format 4 insn. */
  68 #define D22     (D16+1)
  69   { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED },
  70
  71 #define B3      (D22+1)
  72 /* The 3 bit immediate field in format 8 insn.  */
  73   { 3, 11, 0, 0, 0 },
  74
  75 #define CCCC    (B3+1)
  76 /* The 4 bit condition code in a setf instruction */
  77   { 4, 0, 0, 0, V850_OPERAND_CC },
  78
  79 /* The unsigned DISP8 field in a format 4 insn. */
  80 #define D8      (CCCC+1)
  81   { 8, 0, 0, 0, 0 },
  82
  83 /* System register operands.  */
  84 #define SR1     (D8+1)
  85   { 5, 0, 0, 0, V850_OPERAND_SRG },
  86
  87 /* EP Register.  */
  88 #define EP      (SR1+1)
  89   { 0, 0, 0, 0, V850_OPERAND_EP },
  90
  91 /* The IMM16 field (unsigned0 in a format 6 insn. */
  92 #define I16U    (EP+1)
  93   { 16, 16, 0, 0, 0},
  94
  95 /* The R2 field as a system register.  */
  96 #define SR2     (I16U+1)
  97   { 5, 11, 0, 0, V850_OPERAND_SRG },
  98
  99 } ;
 100
 101 \f
 102 /* reg-reg instruction format (Format I) */
 103 #define IF1     {R1, R2}
 104
 105 /* imm-reg instruction format (Format II) */
 106 #define IF2     {I5, R2}
 107
 108 /* conditional branch instruction format (Format III) */
 109 #define IF3     {D9}
 110
 111 /* 16-bit load/store instruction (Format IV) */
 112 #define IF4A    {D7S, EP, R2}
 113 #define IF4B    {R2, D7S, EP}
 114 #define IF4C    {D8, EP, R2}
 115 #define IF4D    {R2, D8, EP}
 116
 117 /* Jump instruction (Format V) */
 118 #define IF5     {D22}
 119
 120 /* 3 operand instruction (Format VI) */
 121 #define IF6     {I16, R1, R2}
 122
 123 /* 3 operand instruction (Format VI) */
 124 #define IF6U    {I16U, R1, R2}
 125
 126 /* 32-bit load/store instruction (Format VII) */
 127 #define IF7A    {D16, R1, R2}
 128 #define IF7B    {R2, D16, R1}
 129
 130 /* Bit manipulation function.  */
 131
 132
 133 \f
 134 /* The opcode table.
 135
 136    The format of the opcode table is:
 137
 138    NAME         OPCODE          MASK            { OPERANDS }
 139
 140    NAME is the name of the instruction.
 141    OPCODE is the instruction opcode.
 142    MASK is the opcode mask; this is used to tell the disassembler
 143      which bits in the actual opcode must match OPCODE.
 144    OPERANDS is the list of operands.
 145
 146    The disassembler reads the table in order and prints the first
 147    instruction which matches, so this table is sorted to put more
 148    specific instructions before more general instructions.  It is also
 149    sorted by major opcode.  */
 150
 151 const struct v850_opcode v850_opcodes[] = {
 152 /* load/store instructions */
 153 { "sld.b",      one(0x0300),            one(0x0780),    IF4A, 2 },
 154 { "sld.h",      one(0x0400),            one(0x0780),    IF4A, 2 },
 155 { "sld.w",      one(0x0500),            one(0x0781),    IF4A, 2 },
 156 { "sst.b",      one(0x0380),            one(0x0780),    IF4B, 2 },
 157 { "sst.h",      one(0x0480),            one(0x0780),    IF4D, 2 },
 158 { "sst.w",      one(0x0501),            one(0x0781),    IF4D, 2 },
 159
 160 { "ld.b",       two(0x0700,0x0000),     two (0x07e0,0x0000),    IF7A, 4 },
 161 { "ld.h",       two(0x0720,0x0000),     two (0x07e0,0x0001),    IF7A, 4 },
 162 { "ld.w",       two(0x0720,0x0001),     two (0x07e0,0x0001),    IF7A, 4 },
 163 { "st.b",       two(0x0740,0x0000),     two (0x07e0,0x0000),    IF7B, 4 },
 164 { "st.h",       two(0x0760,0x0000),     two (0x07e0,0x0001),    IF7B, 4 },
 165 { "st.w",       two(0x0760,0x0001),     two (0x07e0,0x0001),    IF7B, 4 },
 166
 167 /* arithmetic operation instructions */
 168 { "mov",        OP(0x00),               OP_MASK,        IF1, 2 },
 169 { "mov",        OP(0x10),               OP_MASK,        IF2, 2 },
 170 { "movea",      OP(0x31),               OP_MASK,        IF6, 4 },
 171 { "movhi",      OP(0x32),               OP_MASK,        IF6, 4 },
 172 { "add",        OP(0x0e),               OP_MASK,        IF1, 2 },
 173 { "add",        OP(0x12),               OP_MASK,        IF2, 2 },
 174 { "addi",       OP(0x30),               OP_MASK,        IF6, 4 },
 175 { "sub",        OP(0x0d),               OP_MASK,        IF1, 2 },
 176 { "subr",       OP(0x0c),               OP_MASK,        IF1, 2 },
 177 { "mulh",       OP(0x07),               OP_MASK,        IF1, 2 },
 178 { "mulh",       OP(0x17),               OP_MASK,        IF2, 2 },
 179 { "mulhi",      OP(0x37),               OP_MASK,        IF6, 4 },
 180 { "divh",       OP(0x02),               OP_MASK,        IF1, 2 },
 181 { "cmp",        OP(0x0f),               OP_MASK,        IF1, 2 },
 182 { "cmp",        OP(0x13),               OP_MASK,        IF2, 2 },
 183 { "setf",       two(0x07e0,0x0000),     two(0x07f0,0xffff), {CCCC,R2}, 4 },
 184
 185 /* saturated operation instructions */
 186 { "satadd",     OP(0x06),               OP_MASK,        IF1, 2 },
 187 { "satadd",     OP(0x11),               OP_MASK,        IF2, 2 },
 188 { "satsub",     OP(0x05),               OP_MASK,        IF1, 2 },
 189 { "satsubi",    OP(0x33),               OP_MASK,        IF6, 4 },
 190 { "satsubr",    OP(0x04),               OP_MASK,        IF1, 2 },
 191
 192 /* logical operation instructions */
 193 { "tst",        OP(0x0b),               OP_MASK,        IF1, 2 },
 194 { "or",         OP(0x08),               OP_MASK,        IF1, 2 },
 195 { "ori",        OP(0x34),               OP_MASK,        IF6U, 4 },
 196 { "and",        OP(0x0a),               OP_MASK,        IF1, 2 },
 197 { "andi",       OP(0x36),               OP_MASK,        IF6U, 4 },
 198 { "xor",        OP(0x09),               OP_MASK,        IF1, 2 },
 199 { "xori",       OP(0x35),               OP_MASK,        IF6U, 4 },
 200 { "not",        OP(0x01),               OP_MASK,        IF1, 2 },
 201 { "sar",        OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 202 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 203 { "shl",        OP(0x16),               OP_MASK,                {I5U, R2}, 2 },
 204 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 205 { "shr",        OP(0x14),               OP_MASK,                {I5U, R2}, 2 },
 206 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 207
 208 /* branch instructions */
 209         /* signed integer */
 210 { "bgt",        BOP(0xf),               BOP_MASK,       IF3, 2 },
 211 { "bge",        BOP(0xe),               BOP_MASK,       IF3, 2 },
 212 { "blt",        BOP(0x6),               BOP_MASK,       IF3, 2 },
 213 { "ble",        BOP(0x7),               BOP_MASK,       IF3, 2 },
 214         /* unsigned integer */
 215 { "bh",         BOP(0xb),               BOP_MASK,       IF3, 2 },
 216 { "bnh",        BOP(0x3),               BOP_MASK,       IF3, 2 },
 217 { "bl",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 218 { "bnl",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 219         /* common */
 220 { "be",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 221 { "bne",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 222         /* others */
 223 { "bv",         BOP(0x0),               BOP_MASK,       IF3, 2 },
 224 { "bnv",        BOP(0x8),               BOP_MASK,       IF3, 2 },
 225 { "bn",         BOP(0x4),               BOP_MASK,       IF3, 2 },
 226 { "bp",         BOP(0xc),               BOP_MASK,       IF3, 2 },
 227 { "bc",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 228 { "bnc",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 229 { "bz",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 230 { "bnz",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 231 { "br",         BOP(0x5),               BOP_MASK,       IF3, 2 },
 232 { "bsa",        BOP(0xd),               BOP_MASK,       IF3, 2 },
 233
 234 { "jmp",        one(0x0060),            one(0xffe0),    { R1}, 2 },
 235 { "jarl",       one(0x0780),            one(0xf83f),    { D22, R2 }, 4 },
 236 { "jr",         one(0x0780),            one(0xffe0),    { D22 }, 4 },
 237
 238 /* bit manipulation instructions */
 239 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 240 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 241 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 242 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 243
 244 /* special instructions */
 245 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 246 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 247 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 4 },
 248 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 4 },
 249 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 4 },
 250 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R1,SR2}, 4 },
 251 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 4 },
 252 { "nop",        one(0x00),              one(0xffff),            {0}, 2 },
 253 { 0, 0, 0, {0}, 0 },
 254
 255 } ;
 256
 257 const int v850_num_opcodes =
 258   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 259
 260 \f
 261 /* The functions used to insert and extract complicated operands.  */
 262
 263 static unsigned long
 264 insert_d9 (insn, value, errmsg)
 265      unsigned long insn;
 266      long value;
 267      const char **errmsg;
 268 {
 269   if (value > 255 || value <= -256)
 270     *errmsg = "branch value out of range";
 271
 272   if ((value % 2) != 0)
 273     *errmsg = "branch to odd offset";
 274
 275   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 276 }
 277
 278 static long
 279 extract_d9 (insn, invalid)
 280      unsigned long insn;
 281      int *invalid;
 282 {
 283   long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 284
 285   if ((insn & 0x8000) != 0)
 286     ret -= 0x0200;
 287
 288   return ret;
 289 }
 290
 291 static unsigned long
 292 insert_d22 (insn, value, errmsg)
 293      unsigned long insn;
 294      long value;
 295      const char **errmsg;
 296 {
 297   if (value > 0xfffff || value <= -0x100000)
 298     *errmsg = "value out of range";
 299
 300   if ((value % 2) != 0)
 301     *errmsg = "branch to odd offset";
 302
 303   return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
 304 }
 305
 306 static long
 307 extract_d22 (insn, invalid)
 308      unsigned long insn;
 309      int *invalid;
 310 {
 311   int ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
 312
 313   return ((ret << 10) >> 10);
 314 }