sim/arm/arminit.c

   1 /*  arminit.c -- ARMulator initialization:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 2 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, write to the Free Software
  16     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17
  18 #include "armdefs.h"
  19 #include "armemu.h"
  20
  21 /***************************************************************************\
  22 *                 Definitions for the emulator architecture                 *
  23 \***************************************************************************/
  24
  25 void ARMul_EmulateInit (void);
  26 ARMul_State *ARMul_NewState (void);
  27 void ARMul_Reset (ARMul_State * state);
  28 ARMword ARMul_DoCycle (ARMul_State * state);
  29 unsigned ARMul_DoCoPro (ARMul_State * state);
  30 ARMword ARMul_DoProg (ARMul_State * state);
  31 ARMword ARMul_DoInstr (ARMul_State * state);
  32 void ARMul_Abort (ARMul_State * state, ARMword address);
  33
  34 unsigned ARMul_MultTable[32] =
  35   { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
  36   10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
  37 };
  38 ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
  39 char ARMul_BitList[256];        /* number of bits in a byte table */
  40
  41 /***************************************************************************\
  42 *         Call this routine once to set up the emulator's tables.           *
  43 \***************************************************************************/
  44
  45 void
  46 ARMul_EmulateInit (void)
  47 {
  48   unsigned long i, j;
  49
  50   for (i = 0; i < 4096; i++)
  51     {                           /* the values of 12 bit dp rhs's */
  52       ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
  53     }
  54
  55   for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
  56   for (j = 1; j < 256; j <<= 1)
  57     for (i = 0; i < 256; i++)
  58       if ((i & j) > 0)
  59         ARMul_BitList[i]++;
  60
  61   for (i = 0; i < 256; i++)
  62     ARMul_BitList[i] *= 4;      /* you always need 4 times these values */
  63
  64 }
  65
  66 /***************************************************************************\
  67 *            Returns a new instantiation of the ARMulator's state           *
  68 \***************************************************************************/
  69
  70 ARMul_State *
  71 ARMul_NewState (void)
  72 {
  73   ARMul_State *state;
  74   unsigned i, j;
  75
  76   state = (ARMul_State *) malloc (sizeof (ARMul_State));
  77   memset (state, 0, sizeof (ARMul_State));
  78
  79   state->Emulate = RUN;
  80   for (i = 0; i < 16; i++)
  81     {
  82       state->Reg[i] = 0;
  83       for (j = 0; j < 7; j++)
  84         state->RegBank[j][i] = 0;
  85     }
  86   for (i = 0; i < 7; i++)
  87     state->Spsr[i] = 0;
  88
  89   state->Mode = USER26MODE;
  90
  91   state->CallDebug = FALSE;
  92   state->Debug = FALSE;
  93   state->VectorCatch = 0;
  94   state->Aborted = FALSE;
  95   state->Reseted = FALSE;
  96   state->Inted = 3;
  97   state->LastInted = 3;
  98
  99   state->MemDataPtr = NULL;
 100   state->MemInPtr = NULL;
 101   state->MemOutPtr = NULL;
 102   state->MemSparePtr = NULL;
 103   state->MemSize = 0;
 104
 105   state->OSptr = NULL;
 106   state->CommandLine = NULL;
 107
 108   state->EventSet = 0;
 109   state->Now = 0;
 110   state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
 111                                                   sizeof (struct EventNode
 112                                                           *));
 113   for (i = 0; i < EVENTLISTSIZE; i++)
 114     *(state->EventPtr + i) = NULL;
 115
 116 #ifdef ARM61
 117   state->prog32Sig = LOW;
 118   state->data32Sig = LOW;
 119 #else
 120   state->prog32Sig = HIGH;
 121   state->data32Sig = HIGH;
 122 #endif
 123
 124   state->lateabtSig = LOW;
 125   state->bigendSig = LOW;
 126
 127   ARMul_Reset (state);
 128   return (state);
 129 }
 130
 131 /***************************************************************************\
 132 *       Call this routine to set ARMulator to model a certain processor     *
 133 \***************************************************************************/
 134
 135 void
 136 ARMul_SelectProcessor (ARMul_State * state, unsigned processor)
 137 {
 138   if (processor & ARM_Fix26_Prop)
 139     {
 140       state->prog32Sig = LOW;
 141       state->data32Sig = LOW;
 142     }
 143   else
 144     {
 145       state->prog32Sig = HIGH;
 146       state->data32Sig = HIGH;
 147     }
 148
 149   state->lateabtSig = LOW;
 150 }
 151
 152 /***************************************************************************\
 153 * Call this routine to set up the initial machine state (or perform a RESET *
 154 \***************************************************************************/
 155
 156 void
 157 ARMul_Reset (ARMul_State * state)
 158 {
 159   state->NextInstr = 0;
 160
 161   if (state->prog32Sig)
 162     {
 163       state->Reg[15] = 0;
 164       state->Cpsr = INTBITS | SVC32MODE;
 165       state->Mode = SVC32MODE;
 166     }
 167   else
 168     {
 169       state->Reg[15] = R15INTBITS | SVC26MODE;
 170       state->Cpsr = INTBITS | SVC26MODE;
 171       state->Mode = SVC26MODE;
 172     }
 173
 174   ARMul_CPSRAltered (state);
 175   state->Bank = SVCBANK;
 176
 177   FLUSHPIPE;
 178
 179   state->EndCondition = 0;
 180   state->ErrorCode = 0;
 181
 182   state->Exception = FALSE;
 183   state->NresetSig = HIGH;
 184   state->NfiqSig = HIGH;
 185   state->NirqSig = HIGH;
 186   state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
 187   state->abortSig = LOW;
 188   state->AbortAddr = 1;
 189
 190   state->NumInstrs = 0;
 191   state->NumNcycles = 0;
 192   state->NumScycles = 0;
 193   state->NumIcycles = 0;
 194   state->NumCcycles = 0;
 195   state->NumFcycles = 0;
 196 #ifdef ASIM
 197   (void) ARMul_MemoryInit ();
 198   ARMul_OSInit (state);
 199 #endif
 200 }
 201
 202
 203 /***************************************************************************\
 204 * Emulate the execution of an entire program.  Start the correct emulator   *
 205 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
 206 * address of the last instruction that is executed.                         *
 207 \***************************************************************************/
 208
 209 ARMword
 210 ARMul_DoProg (ARMul_State * state)
 211 {
 212   ARMword pc = 0;
 213
 214   state->Emulate = RUN;
 215   while (state->Emulate != STOP)
 216     {
 217       state->Emulate = RUN;
 218       if (state->prog32Sig && ARMul_MODE32BIT)
 219         pc = ARMul_Emulate32 (state);
 220       else
 221         pc = ARMul_Emulate26 (state);
 222     }
 223   return (pc);
 224 }
 225
 226 /***************************************************************************\
 227 * Emulate the execution of one instruction.  Start the correct emulator     *
 228 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
 229 * address of the instruction that is executed.                              *
 230 \***************************************************************************/
 231
 232 ARMword
 233 ARMul_DoInstr (ARMul_State * state)
 234 {
 235   ARMword pc = 0;
 236
 237   state->Emulate = ONCE;
 238   if (state->prog32Sig && ARMul_MODE32BIT)
 239     pc = ARMul_Emulate32 (state);
 240   else
 241     pc = ARMul_Emulate26 (state);
 242
 243   return (pc);
 244 }
 245
 246 /***************************************************************************\
 247 * This routine causes an Abort to occur, including selecting the correct    *
 248 * mode, register bank, and the saving of registers.  Call with the          *
 249 * appropriate vector's memory address (0,4,8 ....)                          *
 250 \***************************************************************************/
 251
 252 void
 253 ARMul_Abort (ARMul_State * state, ARMword vector)
 254 {
 255   ARMword temp;
 256
 257   state->Aborted = FALSE;
 258
 259   if (ARMul_OSException (state, vector, ARMul_GetPC (state)))
 260     return;
 261
 262   if (state->prog32Sig)
 263     if (ARMul_MODE26BIT)
 264       temp = R15PC;
 265     else
 266       temp = state->Reg[15];
 267   else
 268     temp = R15PC | ECC | ER15INT | EMODE;
 269
 270   switch (vector)
 271     {
 272     case ARMul_ResetV:          /* RESET */
 273       state->Spsr[SVCBANK] = CPSR;
 274       SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE);
 275       ARMul_CPSRAltered (state);
 276       state->Reg[14] = temp;
 277       break;
 278     case ARMul_UndefinedInstrV: /* Undefined Instruction */
 279       state->Spsr[state->prog32Sig ? UNDEFBANK : SVCBANK] = CPSR;
 280       SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE);
 281       ARMul_CPSRAltered (state);
 282       state->Reg[14] = temp - 4;
 283       break;
 284     case ARMul_SWIV:            /* Software Interrupt */
 285       state->Spsr[SVCBANK] = CPSR;
 286       SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE);
 287       ARMul_CPSRAltered (state);
 288       state->Reg[14] = temp - 4;
 289       break;
 290     case ARMul_PrefetchAbortV:  /* Prefetch Abort */
 291       state->AbortAddr = 1;
 292       state->Spsr[state->prog32Sig ? ABORTBANK : SVCBANK] = CPSR;
 293       SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE);
 294       ARMul_CPSRAltered (state);
 295       state->Reg[14] = temp - 4;
 296       break;
 297     case ARMul_DataAbortV:      /* Data Abort */
 298       state->Spsr[state->prog32Sig ? ABORTBANK : SVCBANK] = CPSR;
 299       SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE);
 300       ARMul_CPSRAltered (state);
 301       state->Reg[14] = temp - 4;        /* the PC must have been incremented */
 302       break;
 303     case ARMul_AddrExceptnV:    /* Address Exception */
 304       state->Spsr[SVCBANK] = CPSR;
 305       SETABORT (IBIT, SVC26MODE);
 306       ARMul_CPSRAltered (state);
 307       state->Reg[14] = temp - 4;
 308       break;
 309     case ARMul_IRQV:            /* IRQ */
 310       state->Spsr[IRQBANK] = CPSR;
 311       SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE);
 312       ARMul_CPSRAltered (state);
 313       state->Reg[14] = temp - 4;
 314       break;
 315     case ARMul_FIQV:            /* FIQ */
 316       state->Spsr[FIQBANK] = CPSR;
 317       SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE);
 318       ARMul_CPSRAltered (state);
 319       state->Reg[14] = temp - 4;
 320       break;
 321     }
 322   if (ARMul_MODE32BIT)
 323     ARMul_SetR15 (state, vector);
 324   else
 325     ARMul_SetR15 (state, R15CCINTMODE | vector);
 326 }