sim/erc32/README.erc32

   1
   2 1. MEC and ERC32 emulation
   3
   4 The file 'erc32.c' contains a model of the MEC, 512 K rom and 4 M ram.
   5
   6 The following paragraphs outline the implemented MEC functions.
   7
   8 1.1 UARTs
   9
  10 The UARTs are connected to two pseudo-devices, /dev/ttypc and /dev/ttypd.
  11 The following registers are implemeted:
  12
  13 - UART A RX and TX register     (0x01f800e0)
  14 - UART B RX and TX register     (0x01f800e4)
  15 - UART status register          (0x01f800e8)
  16
  17 To speed up simulation, the UARTs operate at approximately 115200 baud.
  18 The UARTs generate interrupt 4 and 5 after each received or transmitted
  19 character.  The error interrupt is generated if overflow occurs - other
  20 errors cannot occure.
  21
  22 1.2 Real-time clock and general pupose timer A
  23
  24 The following registers are implemeted:
  25
  26 - Real-time clock timer                         (0x01f80080, read-only)
  27 - Real-time clock scaler program register       (0x01f80084, write-only)
  28 - Real-time clock counter program register      (0x01f80080, write-only)
  29
  30 - Genearl pupose timer                          (0x01f80088, read-only)
  31 - Real-time clock scaler program register       (0x01f8008c, write-only)
  32 - General purpose timer counter prog. register  (0x01f80088, write-only)
  33
  34 - Timer control register                        (0x01f80098, write-only)
  35
  36 1.3 Interrupt controller
  37
  38 The interrupt controller is implemented as in the MEC specification with
  39 the exception of the interrupt shape register. Since external interrupts
  40 are not possible, the interrupt shape register is not implemented. The
  41 only internal interrupts that are generated are the real-time clock,
  42 the general purpose timer and UARTs. However, all 15 interrupts
  43 can be tested via the interrupt force register.
  44
  45 The following registers are implemeted:
  46
  47 - Interrupt pending register                   (0x01f80048, read-only)
  48 - Interrupt mask register                      (0x01f8004c, read-write)
  49 - Interrupt clear register                     (0x01f80050, write-only)
  50 - Interrupt force register                     (0x01f80054, read-write)
  51
  52 1.4 Breakpoint and watchpoint register
  53
  54 The breakpoint and watchpoint functions are implemented as in the MEC
  55 specification. Traps are correctly generated, and the system fault status
  56 register is updated accordingly. Implemeted registers are:
  57
  58 - Debug control register                        (0x01f800c0, read-write)
  59 - Breakpoint register                           (0x01f800c4, write-only)
  60 - Watchpoint register                           (0x01f800c8, write-only)
  61 - System fault status register                  (0x01f800a0, read-write)
  62 - Firts failing address register                (0x01f800a4, read-write)
  63
  64
  65 1.5 Memory interface
  66
  67 The following memory areas are valid for the ERC32 simulator:
  68
  69 0x00000000 - 0x00080000         ROM (512 Kbyte, loaded at start-up)
  70 0x02000000 - 0x02400000         RAM (4 Mbyte, initialised to 0x0)
  71 0x01f80000 - 0x01f800ff         MEC registers
  72
  73 Access to unimplemented MEC registers or non-existing memory will result
  74 in a memory exception trap. However, access to unimplemented MEC registers
  75 in the area 0x01f80000 - 0x01f80100 will not cause a memory exception trap.
  76 The written value will be stored in a register and can be read back. It
  77 does however not affect the function in any way.
  78
  79 The memory configuartion register is used to define available memory
  80 in the system. The fields RSIZ and PSIZ are used to set RAM and ROM
  81 size, the remaining fields are not used.  NOTE: after reset, the MEC
  82 is set to decode 4 Kbyte of ROM and 256 Kbyte of RAM. The memory
  83 configuration register has to be updated to reflect the available memory.
  84
  85 The waitstate configuration register is used to generate waitstates.
  86 This register must also be updated with the correct configuration after
  87 reset.
  88
  89 The memory protection scheme is implemented - it is enabled through bit 3
  90 in the MEC control register.
  91
  92 The following registers are implemeted:
  93
  94 - MEC control register (bit 3 only)             (0x01f80000, read-write)
  95 - Memory control register                       (0x01f80010, read-write)
  96 - Waitstate configuration register              (0x01f80018, read-write)
  97 - Memory access register 0                      (0x01f80020, read-write)
  98 - Memory access register 1                      (0x01f80024, read-write)
  99
 100 1.6 Watchdog
 101
 102 The watchdog is implemented as in the specification. The input clock is
 103 always the system clock regardsless of WDCS bit in mec configuration
 104 register.
 105
 106 The following registers are implemeted:
 107
 108 - Watchdog program and acknowledge register     (0x01f80060, write-only)
 109 - Watchdog trap door set register               (0x01f80064, write-only)
 110
 111 1.7 Software reset register
 112
 113 Implemented as in the specification (0x01f800004, write-only).
 114
 115 1.8 Power-down mode
 116
 117 The power-down register (0x01f800008) is implemented as in the specification.
 118 However, if the simulator event queue is empty, power-down mode is not
 119 entered since no interrupt would be generated to exit from the mode. A
 120 Ctrl-C in the simulator window will exit the power-down mode.
 121
 122 1.9 MEC control register
 123
 124 The following bits are implemented in the MEC control register:
 125
 126 Bit     Name    Function
 127 0       PRD     Power-down mode enable
 128 1       SWR     Soft reset enable
 129 3       APR     Access protection enable
 130