sim/mips/mips3d.igen

   1 // -*- C -*-
   2
   3 // Simulator definition for the MIPS MIPS-3D ASE.
   4 // Copyright (C) 2002, 2010 Free Software Foundation, Inc.
   5 // Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
   6 // Corporation (SiByte).
   7 //
   8 // This file is part of GDB, the GNU debugger.
   9 //
  10 // This program is free software; you can redistribute it and/or modify
  11 // it under the terms of the GNU General Public License as published by
  12 // the Free Software Foundation; either version 3 of the License, or
  13 // (at your option) any later version.
  14 //
  15 // This program is distributed in the hope that it will be useful,
  16 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 // GNU General Public License for more details.
  19 //
  20 // You should have received a copy of the GNU General Public License
  21 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
  22
  23 //  Reference: MIPS64 Architecture for Programmers Volume IV-c:
  24 //             The MIPS-3D Application-Specific Extension to the
  25 //             MIPS64 Architecture.  (MIPS Document MD00099)
  26
  27
  28 010001,10,110,5.FT,5.FS,5.FD,011000:COP1:64,f::ADDR.PS
  29 "addr.ps f<FD>, f<FS>, f<FT>"
  30 *mips3d:
  31 {
  32   /* fd.PL = ft.PU + ft.PL;  fd.PU = fs.PU + fs.PL;  */
  33   check_fpu (SD_);
  34   check_u64 (SD_, instruction_0);
  35   StoreFPR (FD, fmt_ps, AddR (ValueFPR (FS, fmt_ps),
  36                               ValueFPR (FT, fmt_ps), fmt_ps));
  37 }
  38
  39
  40 010001,01001,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY2tf
  41 "bc1any2%s<TF> <CC>, %#lx<OFFSET>"
  42 *mips3d:
  43 {
  44   address_word offset;
  45   int cc = CC;
  46   check_fpu (SD_);
  47   check_u64 (SD_, instruction_0);
  48   if ((cc & 0x1) != 0)
  49     Unpredictable ();
  50   if ((GETFCC (cc) == TF) || (GETFCC (cc + 1) == TF))
  51     {
  52       offset = (EXTEND16 (OFFSET) << 2);
  53       DELAY_SLOT (NIA + offset);
  54     }
  55 }
  56
  57
  58 010001,01010,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY4tf
  59 "bc1any4%s<TF> <CC>, %#lx<OFFSET>"
  60 *mips3d:
  61 {
  62   address_word offset;
  63   int cc = CC;
  64   check_fpu (SD_);
  65   check_u64 (SD_, instruction_0);
  66   if ((cc & 0x3) != 0)
  67     Unpredictable ();
  68   if ((GETFCC (cc) == TF)
  69       || (GETFCC (cc + 1) == TF)
  70       || (GETFCC (cc + 2) == TF)
  71       || (GETFCC (cc + 3) == TF))
  72     {
  73       offset = (EXTEND16 (OFFSET) << 2);
  74       DELAY_SLOT (NIA + offset);
  75     }
  76 }
  77
  78
  79 010001,10,3.FMT,5.FT,5.FS,3.CC,01,11,4.COND:COP1:64,f::CABS.cond.fmt
  80 "cabs.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
  81 *mips3d:
  82 {
  83   int fmt = FMT;
  84   check_fpu (SD_);
  85   check_u64 (SD_, instruction_0);
  86   check_fmt_p (SD_, fmt, instruction_0);
  87   CompareAbs (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
  88   TRACE_ALU_RESULT (ValueFCR (31));
  89 }
  90
  91
  92 010001,10,110,00000,5.FS,5.FD,100100:COP1:64,f::CVT.PW.PS
  93 "cvt.pw.ps f<FD>, f<FS>"
  94 *mips3d:
  95 {
  96   /* fd.pu = cvt_rnd (fs.pu); fd.pl = cvt_rnd (fs.pl);  */
  97   /* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word.  */
  98   check_fpu (SD_);
  99   check_u64 (SD_, instruction_0);
 100   StoreFPR (FD, fmt_pw, ConvertPS (GETRM (), ValueFPR (FS, fmt_ps),
 101                                    fmt_ps, fmt_word));
 102 }
 103
 104
 105 010001,10,100,00000,5.FS,5.FD,100110:COP1:64,f::CVT.PS.PW
 106 "cvt.ps.pw f<FD>, f<FS>"
 107 *mips3d:
 108 {
 109   /* fd.pl = cvt_rnd (fs.pl); fd.pu = cvt_rnd (fs.pu);  */
 110   /* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word.  */
 111   check_fpu (SD_);
 112   check_u64 (SD_, instruction_0);
 113   StoreFPR (FD, fmt_ps, ConvertPS (GETRM (), ValueFPR (FS, fmt_pw),
 114                                    fmt_word, fmt_ps));
 115 }
 116
 117
 118 010001,10,110,5.FT,5.FS,5.FD,011010:COP1:64,f::MULR.PS
 119 "mulr.ps f<FD>, f<FS>, f<FT>"
 120 *mips3d:
 121 {
 122   /* fd.PL = ft.PU * ft.PL;  fd.PU = fs.PU * fs.PL;  */
 123   check_fpu (SD_);
 124   check_u64 (SD_, instruction_0);
 125   StoreFPR (FD, fmt_ps, MultiplyR (ValueFPR (FS, fmt_ps),
 126                                    ValueFPR (FT, fmt_ps), fmt_ps));
 127 }
 128
 129
 130 010001,10,3.FMT,00000,5.FS,5.FD,011101:COP1:64,f::RECIP1.fmt
 131 "recip1.%s<FMT> f<FD>, f<FS>"
 132 *mips3d:
 133 {
 134   int fmt = FMT;
 135   check_fpu (SD_);
 136   check_u64 (SD_, instruction_0);
 137   check_fmt_p (SD_, fmt, instruction_0);
 138   StoreFPR (FD, fmt, Recip1 (ValueFPR (FS, fmt), fmt));
 139 }
 140
 141
 142 010001,10,3.FMT,5.FT,5.FS,5.FD,011100:COP1:64,f::RECIP2.fmt
 143 "recip2.%s<FMT> f<FD>, f<FS>, f<FT>"
 144 *mips3d:
 145 {
 146   int fmt = FMT;
 147   check_fpu (SD_);
 148   check_u64 (SD_, instruction_0);
 149   check_fmt_p (SD_, fmt, instruction_0);
 150   StoreFPR (FD, fmt, Recip2 (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 151 }
 152
 153
 154 010001,10,3.FMT,00000,5.FS,5.FD,011110:COP1:64,f::RSQRT1.fmt
 155 "rsqrt1.%s<FMT> f<FD>, f<FS>"
 156 *mips3d:
 157 {
 158   int fmt = FMT;
 159   check_fpu (SD_);
 160   check_u64 (SD_, instruction_0);
 161   check_fmt_p (SD_, fmt, instruction_0);
 162   StoreFPR (FD, fmt, RSquareRoot1 (ValueFPR (FS, fmt), fmt));
 163 }
 164
 165
 166 010001,10,3.FMT,5.FT,5.FS,5.FD,011111:COP1:64,f::RSQRT2.fmt
 167 "rsqrt2.%s<FMT> f<FD>, f<FS>, f<FT>"
 168 *mips3d:
 169 {
 170   int fmt = FMT;
 171   check_fpu (SD_);
 172   check_u64 (SD_, instruction_0);
 173   check_fmt_p (SD_, fmt, instruction_0);
 174   StoreFPR (FD, fmt, RSquareRoot2 (ValueFPR (FS, fmt),
 175                                    ValueFPR (FT, fmt), fmt));
 176 }