sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S

   1 //Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp
   2 // Spec Reference: mmr ppopm illegal address
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 include(gen_int.inc)
  11 include(selfcheck.inc)
  12 include(std.inc)
  13 include(mmrs.inc)
  14
  15 #ifndef STACKSIZE
  16 #define STACKSIZE 0x10
  17 #endif
  18 #ifndef ITABLE
  19 #define ITABLE 0xF0000000
  20 #endif
  21
  22 GEN_INT_INIT(ITABLE) // set location for interrupt table
  23
  24 //
  25 // Reset/Bootstrap Code
  26 //   (Here we set the processor operating modes, initialize registers
  27 //    etc.)
  28 //
  29
  30 BOOT:
  31
  32 INIT_R_REGS(0);
  33 INIT_P_REGS(0);
  34 INIT_I_REGS(0);     // initialize the dsp address regs
  35 INIT_M_REGS(0);
  36 INIT_L_REGS(0);
  37 INIT_B_REGS(0);
  38     //CHECK_INIT(p5, 0xe0000000);
  39 include(symtable.inc)
  40 CHECK_INIT_DEF(p5);
  41
  42 CLI R1;           // inhibit events during MMR writes
  43
  44 LD32_LABEL(sp, USTACK);   // setup the user stack pointer
  45 USP = SP;                  // and frame pointer
  46
  47 LD32_LABEL(sp, KSTACK);   // setup the stack pointer
  48 FP = SP;                  // and frame pointer
  49
  50 LD32(p0, EVT0);      // Setup Event Vectors and Handlers
  51 LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
  52     [ P0 ++ ] = R0;
  53
  54 LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
  55     [ P0 ++ ] = R0;
  56
  57 LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
  58     [ P0 ++ ] = R0;
  59
  60 LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
  61     [ P0 ++ ] = R0;
  62
  63     [ P0 ++ ] = R0;          // EVT4 not used global Interr Enable (INT4)
  64
  65 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  66     [ P0 ++ ] = R0;
  67
  68 LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
  69     [ P0 ++ ] = R0;
  70
  71 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  72     [ P0 ++ ] = R0;
  73
  74 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  75     [ P0 ++ ] = R0;
  76
  77 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  78     [ P0 ++ ] = R0;
  79
  80 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  81     [ P0 ++ ] = R0;
  82
  83 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  84     [ P0 ++ ] = R0;
  85
  86 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  87     [ P0 ++ ] = R0;
  88
  89 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  90     [ P0 ++ ] = R0;
  91
  92 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  93     [ P0 ++ ] = R0;
  94
  95 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
  96     [ P0 ++ ] = R0;
  97
  98 LD32(p0, EVT_OVERRIDE);
  99     R0 = 0;
 100     [ P0 ++ ] = R0;
 101
 102     R1 = -1;     // Change this to mask interrupts (*)
 103 CSYNC;       // wait for MMR writes to finish
 104 STI R1;      // sync and reenable events (implicit write to IMASK)
 105
 106 DUMMY:
 107
 108     R0 = 0 (Z);
 109
 110 LT0 = r0;       // set loop counters to something deterministic
 111 LB0 = r0;
 112 LC0 = r0;
 113 LT1 = r0;
 114 LB1 = r0;
 115 LC1 = r0;
 116
 117 ASTAT = r0;     // reset other internal regs
 118 SYSCFG = r0;
 119 RETS = r0;      // prevent X's breaking LINK instruction
 120
 121 // The following code sets up the test for running in USER mode
 122
 123 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 124                         // ReturnFromInterrupt (RTI)
 125 RETI = r0;      // We need to load the return address
 126
 127 // Comment the following line for a USER Mode test
 128
 129 JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
 130
 131 RTI;
 132
 133 STARTSUP:
 134 LD32_LABEL(p1, BEGIN);
 135
 136 LD32(p0, EVT15);
 137
 138 CLI R1;    // inhibit events during write to MMR
 139     [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 140 CSYNC;       // wait for it
 141 STI R1;      // reenable events with proper imask
 142
 143 RAISE 15;       // after we RTI, INT 15 should be taken
 144
 145 RTI;
 146
 147 //
 148 // The Main Program
 149 //
 150 STARTUSER:
 151 LINK 0;     // change for how much stack frame space you need.
 152
 153 JUMP BEGIN;
 154
 155
 156
 157 //*********************************************************************
 158
 159 BEGIN:
 160
 161                 // COMMENT the following line for USER MODE tests
 162     [ -- SP ] = RETI;  // enable interrupts in supervisor mode
 163
 164                 // **** YOUR CODE GOES HERE ****
 165
 166 LD32(r0, 0206037020);
 167 LD32(r1, 0x10070030);
 168 LD32(r2, 0xe2000043);
 169 LD32(r3, 0x30305050);
 170 LD32(r4, 0x0f040860);
 171 LD32(r5, 0x0a0050d0);
 172 LD32(r6, 0x00000000);
 173 LD32(r7, 0x0f060071);
 174     [ -- SP ] = ( R7:7 );
 175 LD32(r7, 0x123456af);
 176     [ -- SP ] = ( R7:6 );
 177 //  [--sp] = r7;
 178 //  [--sp] = r6;
 179 .dd 0xffff
 180     R1 += 2;
 181
 182 CHECKREG(r1, 0x10070034);
 183 CHECKREG(r2, 0xE2000046);
 184 CHECKREG(r3, 0x30305054);
 185 CHECKREG(r4, 0x0f040865);
 186 CHECKREG(r5, 0x0a0050d6);
 187 CHECKREG(r6, 0x00000007);
 188 CHECKREG(r7, 0x123456b7);
 189     R7 = [ SP ++ ];
 190 CHECKREG(r7, 0x123456af);
 191
 192 dbg_pass;            // End the test
 193
 194 //*********************************************************************
 195
 196 //
 197 // Handlers for Events
 198 //
 199
 200 EHANDLE:            // Emulation Handler 0
 201 RTE;
 202
 203 RHANDLE:            // Reset Handler 1
 204 RTI;
 205
 206 NHANDLE:            // NMI Handler 2
 207     R0 = 2;
 208 RTN;
 209
 210 XHANDLE:            // Exception Handler 3
 211 R0 = RETX;   // error handler:RETX has the address of the same Illegal instr
 212     R1 += 2;
 213     R2 += 3;
 214     R3 += 4;
 215     R4 += 5;
 216     R5 += 6;
 217     R6 += 7;
 218     R7 += 8;
 219 R0 += 2;     // we have to add 2 to point to next instr after return (16-bit illegal instr)
 220 RETX = R0;
 221 NOP; NOP; NOP; NOP;
 222
 223
 224 RTX;
 225
 226 HWHANDLE:           // HW Error Handler 5
 227     R2 = 5;
 228 RTI;
 229
 230 THANDLE:            // Timer Handler 6
 231     R3 = 6;
 232 RTI;
 233
 234 I7HANDLE:           // IVG 7 Handler
 235     R4 = 7;
 236 RTI;
 237
 238 I8HANDLE:           // IVG 8 Handler
 239     R5 = 8;
 240 RTI;
 241
 242 I9HANDLE:           // IVG 9 Handler
 243     R6 = 9;
 244 RTI;
 245
 246 I10HANDLE:          // IVG 10 Handler
 247     R7 = 10;
 248 RTI;
 249
 250 I11HANDLE:          // IVG 11 Handler
 251     R0 = 11;
 252 RTI;
 253
 254 I12HANDLE:          // IVG 12 Handler
 255     R1 = 12;
 256 RTI;
 257
 258 I13HANDLE:          // IVG 13 Handler
 259     R2 = 13;
 260 RTI;
 261
 262 I14HANDLE:          // IVG 14 Handler
 263     R3 = 14;
 264 RTI;
 265
 266 I15HANDLE:          // IVG 15 Handler
 267     R4 = 15;
 268 RTI;
 269
 270 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
 271
 272 //
 273 // Data Segment
 274 //
 275
 276 .section MEM_DATA_ADDR_1,"aw"
 277 DATA0:
 278 .dd 0x000a0000
 279 .dd 0x000b0001
 280 .dd 0x000c0002
 281 .dd 0x000d0003
 282 .dd 0x000e0004
 283 .dd 0x000f0005
 284 .dd 0x00100006
 285 .dd 0x00200007
 286 .dd 0x00300008
 287 .dd 0x00400009
 288 .dd 0x0050000a
 289 .dd 0x0060000b
 290 .dd 0x0070000c
 291 .dd 0x0080000d
 292 .dd 0x0090000e
 293 .dd 0x0100000f
 294 .dd 0x02000010
 295 .dd 0x03000011
 296 .dd 0x04000012
 297 .dd 0x05000013
 298 .dd 0x06000014
 299 .dd 0x001a0000
 300 .dd 0x001b0001
 301 .dd 0x001c0002
 302 // Stack Segments (Both Kernel and User)
 303
 304     .space (STACKSIZE);
 305 KSTACK:
 306
 307     .space (STACKSIZE);
 308 USTACK: