sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s

   1 //Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp
   2 // Spec Reference: pushpopmultiple dreg preg in group pair
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         FP = SP;
   9
  10         imm32 r0, 0x00000000;
  11         ASTAT = r0;
  12
  13         R0 = 0x01;
  14         R1 = 0x02;
  15         R2 = 0x03;
  16         R3 = 0x04;
  17         R4 = 0x05;
  18         R5 = 0x06;
  19         R6 = 0x07;
  20         R7 = 0x08;
  21
  22         P1 = 0xa1 (X);
  23         P2 = 0xa2 (X);
  24         P3 = 0xa3 (X);
  25         P4 = 0xa4 (X);
  26         P5 = 0xa5 (X);
  27         [ -- SP ] = ( R7:0, P5:1 );
  28
  29         R1 = 0x12;
  30         R2 = 0x13;
  31         R3 = 0x14;
  32         R4 = 0x15;
  33         R5 = 0x16;
  34         R6 = 0x17;
  35         R7 = 0x18;
  36
  37         P2 = 0xb2 (X);
  38         P3 = 0xb3 (X);
  39         P4 = 0xb4 (X);
  40         P5 = 0xb5 (X);
  41         [ -- SP ] = ( R7:1, P5:2 );
  42
  43         R2 = 0x23;
  44         R3 = 0x24;
  45         R4 = 0x25;
  46         R5 = 0x26;
  47         R6 = 0x27;
  48         R7 = 0x28;
  49
  50         P3 = 0xc3 (X);
  51         P4 = 0xc4 (X);
  52         P5 = 0xc5 (X);
  53         [ -- SP ] = ( R7:2, P5:3 );
  54
  55         R3 = 0x34;
  56         R4 = 0x35;
  57         R5 = 0x36;
  58         R6 = 0x37;
  59         R7 = 0x38;
  60
  61         P4 = 0xd4 (X);
  62         P5 = 0xd5 (X);
  63         [ -- SP ] = ( R7:3, P5:4 );
  64
  65         R4 = 0x45 (X);
  66         R5 = 0x46 (X);
  67         R6 = 0x47 (X);
  68         R7 = 0x48 (X);
  69         P5 = 0xe5 (X);
  70         [ -- SP ] = ( R7:4, P5:5 );
  71
  72         R5 = 0x56 (X);
  73         R6 = 0x57 (X);
  74         R7 = 0x58 (X);
  75         [ -- SP ] = ( R7:5 );
  76         R6 = 0x67 (X);
  77         R7 = 0x68 (X);
  78         [ -- SP ] = ( R7:6 );
  79         R7 = 0x78 (X);
  80         [ -- SP ] = ( R7:7 );
  81         R0 = 0;
  82         R1 = 0;
  83         R2 = 0;
  84         R3 = 0;
  85         R4 = 0;
  86         R5 = 0;
  87         R6 = 0;
  88         R7 = 0;
  89         P1 = 0;
  90         P2 = 0;
  91         P3 = 0;
  92         P4 = 0;
  93         P5 = 0;
  94         ( R7:7 ) = [ SP ++ ];
  95         CHECKREG r0, 0x00000000;
  96         CHECKREG r1, 0x00000000;
  97         CHECKREG r2, 0x00000000;
  98         CHECKREG r3, 0x00000000;
  99         CHECKREG r4, 0x00000000;
 100         CHECKREG r5, 0x00000000;
 101         CHECKREG r6, 0x00000000;
 102         CHECKREG r7, 0x00000078;
 103
 104         ( R7:6 ) = [ SP ++ ];
 105         CHECKREG r0, 0x00000000;
 106         CHECKREG r1, 0x00000000;
 107         CHECKREG r2, 0x00000000;
 108         CHECKREG r3, 0x00000000;
 109         CHECKREG r4, 0x00000000;
 110         CHECKREG r5, 0x00000000;
 111         CHECKREG r6, 0x00000067;
 112         CHECKREG r7, 0x00000068;
 113
 114         ( R7:5 ) = [ SP ++ ];
 115         CHECKREG r0, 0x00000000;
 116         CHECKREG r1, 0x00000000;
 117         CHECKREG r2, 0x00000000;
 118         CHECKREG r3, 0x00000000;
 119         CHECKREG r4, 0x00000000;
 120         CHECKREG r5, 0x00000056;
 121         CHECKREG r6, 0x00000057;
 122         CHECKREG r7, 0x00000058;
 123
 124         ( R7:4, P5:5 ) = [ SP ++ ];
 125         CHECKREG p1, 0x00000000;
 126         CHECKREG p2, 0x00000000;
 127         CHECKREG p3, 0x00000000;
 128         CHECKREG p4, 0x00000000;
 129         CHECKREG p5, 0x000000e5;
 130
 131         CHECKREG r0, 0x00000000;
 132         CHECKREG r1, 0x00000000;
 133         CHECKREG r2, 0x00000000;
 134         CHECKREG r3, 0x00000000;
 135         CHECKREG r4, 0x00000045;
 136         CHECKREG r5, 0x00000046;
 137         CHECKREG r6, 0x00000047;
 138         CHECKREG r7, 0x00000048;
 139
 140         ( R7:3, P5:4 ) = [ SP ++ ];
 141         CHECKREG p1, 0x00000000;
 142         CHECKREG p2, 0x00000000;
 143         CHECKREG p3, 0x00000000;
 144         CHECKREG p4, 0x000000d4;
 145         CHECKREG p5, 0x000000d5;
 146
 147         CHECKREG r0, 0x00000000;
 148         CHECKREG r1, 0x00000000;
 149         CHECKREG r2, 0x00000000;
 150         CHECKREG r3, 0x00000034;
 151         CHECKREG r4, 0x00000035;
 152         CHECKREG r5, 0x00000036;
 153         CHECKREG r6, 0x00000037;
 154         CHECKREG r7, 0x00000038;
 155
 156         ( R7:2, P5:3 ) = [ SP ++ ];
 157         CHECKREG p1, 0x00000000;
 158         CHECKREG p2, 0x00000000;
 159         CHECKREG p3, 0x000000c3;
 160         CHECKREG p4, 0x000000c4;
 161         CHECKREG p5, 0x000000c5;
 162
 163         CHECKREG r0, 0x00000000;
 164         CHECKREG r1, 0x00000000;
 165         CHECKREG r2, 0x00000023;
 166         CHECKREG r3, 0x00000024;
 167         CHECKREG r4, 0x00000025;
 168         CHECKREG r5, 0x00000026;
 169         CHECKREG r6, 0x00000027;
 170         CHECKREG r7, 0x00000028;
 171
 172         ( R7:1, P5:2 ) = [ SP ++ ];
 173         CHECKREG p1, 0x00000000;
 174         CHECKREG p2, 0x000000b2;
 175         CHECKREG p3, 0x000000b3;
 176         CHECKREG p4, 0x000000b4;
 177         CHECKREG p5, 0x000000b5;
 178
 179         CHECKREG r0, 0x00000000;
 180         CHECKREG r1, 0x00000012;
 181         CHECKREG r2, 0x00000013;
 182         CHECKREG r3, 0x00000014;
 183         CHECKREG r4, 0x00000015;
 184         CHECKREG r5, 0x00000016;
 185         CHECKREG r6, 0x00000017;
 186         CHECKREG r7, 0x00000018;
 187
 188         ( R7:0, P5:1 ) = [ SP ++ ];
 189         CHECKREG p1, 0x000000a1;
 190         CHECKREG p2, 0x000000a2;
 191         CHECKREG p3, 0x000000a3;
 192         CHECKREG p4, 0x000000a4;
 193         CHECKREG p5, 0x000000a5;
 194
 195         CHECKREG r0, 0x00000001;
 196         CHECKREG r1, 0x00000002;
 197         CHECKREG r2, 0x00000003;
 198         CHECKREG r3, 0x00000004;
 199         CHECKREG r4, 0x00000005;
 200         CHECKREG r5, 0x00000006;
 201         CHECKREG r6, 0x00000007;
 202         CHECKREG r7, 0x00000008;
 203         pass