sim/testsuite/sim/frv/csubcc.cgs

   1 # frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global csubcc
   9 csubcc:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_gr_immed    1,gr7
  13         set_gr_immed    2,gr8
  14         set_icc         0x0f,0          ; Set mask opposite of expected
  15         csubcc          gr8,gr7,gr8,cc0,1
  16         test_icc        0 0 0 0 icc0
  17         test_gr_immed   1,gr8
  18
  19         set_gr_immed    1,gr7
  20         set_gr_limmed   0x8000,0x0000,gr8
  21         set_icc         0x0d,0          ; Set mask opposite of expected
  22         csubcc          gr8,gr7,gr8,cc0,1
  23         test_icc        0 0 1 0 icc0
  24         test_gr_limmed  0x7fff,0xffff,gr8
  25
  26         set_icc         0x0b,0          ; Set mask opposite of expected
  27         csubcc          gr8,gr8,gr8,cc4,1
  28         test_icc        0 1 0 0 icc0
  29         test_gr_immed   0,gr8
  30
  31         set_icc         0x06,0          ; Set mask opposite of expected
  32         csubcc          gr8,gr7,gr8,cc4,1
  33         test_icc        1 0 0 1 icc0
  34         test_gr_limmed  0xffff,0xffff,gr8
  35
  36         set_gr_immed    1,gr7
  37         set_gr_immed    2,gr8
  38         set_icc         0x0f,0          ; Set mask opposite of expected
  39         csubcc          gr8,gr7,gr8,cc0,0
  40         test_icc        1 1 1 1 icc0
  41         test_gr_immed   2,gr8
  42
  43         set_gr_immed    1,gr7
  44         set_gr_limmed   0x8000,0x0000,gr8
  45         set_icc         0x0d,0          ; Set mask opposite of expected
  46         csubcc          gr8,gr7,gr8,cc0,0
  47         test_icc        1 1 0 1 icc0
  48         test_gr_limmed  0x8000,0x0000,gr8
  49
  50         set_icc         0x0b,0          ; Set mask opposite of expected
  51         csubcc          gr8,gr8,gr8,cc4,0
  52         test_icc        1 0 1 1 icc0
  53         test_gr_limmed  0x8000,0x0000,gr8
  54
  55         set_icc         0x06,0          ; Set mask opposite of expected
  56         csubcc          gr8,gr7,gr8,cc4,0
  57         test_icc        0 1 1 0 icc0
  58         test_gr_limmed  0x8000,0x0000,gr8
  59
  60         set_gr_immed    1,gr7
  61         set_gr_immed    2,gr8
  62         set_icc         0x0f,1          ; Set mask opposite of expected
  63         csubcc          gr8,gr7,gr8,cc1,0
  64         test_icc        0 0 0 0 icc1
  65         test_gr_immed   1,gr8
  66
  67         set_gr_immed    1,gr7
  68         set_gr_limmed   0x8000,0x0000,gr8
  69         set_icc         0x0d,1          ; Set mask opposite of expected
  70         csubcc          gr8,gr7,gr8,cc1,0
  71         test_icc        0 0 1 0 icc1
  72         test_gr_limmed  0x7fff,0xffff,gr8
  73
  74         set_icc         0x0b,1          ; Set mask opposite of expected
  75         csubcc          gr8,gr8,gr8,cc5,0
  76         test_icc        0 1 0 0 icc1
  77         test_gr_immed   0,gr8
  78
  79         set_icc         0x06,1          ; Set mask opposite of expected
  80         csubcc          gr8,gr7,gr8,cc5,0
  81         test_icc        1 0 0 1 icc1
  82         test_gr_limmed  0xffff,0xffff,gr8
  83
  84         set_gr_immed    1,gr7
  85         set_gr_immed    2,gr8
  86         set_icc         0x0f,1          ; Set mask opposite of expected
  87         csubcc          gr8,gr7,gr8,cc1,1
  88         test_icc        1 1 1 1 icc1
  89         test_gr_immed   2,gr8
  90
  91         set_gr_immed    1,gr7
  92         set_gr_limmed   0x8000,0x0000,gr8
  93         set_icc         0x0d,1          ; Set mask opposite of expected
  94         csubcc          gr8,gr7,gr8,cc1,1
  95         test_icc        1 1 0 1 icc1
  96         test_gr_limmed  0x8000,0x0000,gr8
  97
  98         set_icc         0x0b,1          ; Set mask opposite of expected
  99         csubcc          gr8,gr8,gr8,cc5,1
 100         test_icc        1 0 1 1 icc1
 101         test_gr_limmed  0x8000,0x0000,gr8
 102
 103         set_icc         0x06,1          ; Set mask opposite of expected
 104         csubcc          gr8,gr7,gr8,cc5,1
 105         test_icc        0 1 1 0 icc1
 106         test_gr_limmed  0x8000,0x0000,gr8
 107
 108         set_gr_immed    1,gr7
 109         set_gr_immed    2,gr8
 110         set_icc         0x0f,2          ; Set mask opposite of expected
 111         csubcc          gr8,gr7,gr8,cc2,0
 112         test_icc        1 1 1 1 icc2
 113         test_gr_immed   2,gr8
 114
 115         set_gr_immed    1,gr7
 116         set_gr_limmed   0x8000,0x0000,gr8
 117         set_icc         0x0d,2          ; Set mask opposite of expected
 118         csubcc          gr8,gr7,gr8,cc2,0
 119         test_icc        1 1 0 1 icc2
 120         test_gr_limmed  0x8000,0x0000,gr8
 121
 122         set_icc         0x0b,2          ; Set mask opposite of expected
 123         csubcc          gr8,gr8,gr8,cc6,1
 124         test_icc        1 0 1 1 icc2
 125         test_gr_limmed  0x8000,0x0000,gr8
 126
 127         set_icc         0x06,2          ; Set mask opposite of expected
 128         csubcc          gr8,gr7,gr8,cc6,1
 129         test_icc        0 1 1 0 icc2
 130         test_gr_limmed  0x8000,0x0000,gr8
 131
 132         set_gr_immed    1,gr7
 133         set_gr_immed    2,gr8
 134         set_icc         0x0f,3          ; Set mask opposite of expected
 135         csubcc          gr8,gr7,gr8,cc3,0
 136         test_icc        1 1 1 1 icc3
 137         test_gr_immed   2,gr8
 138
 139         set_gr_immed    1,gr7
 140         set_gr_limmed   0x8000,0x0000,gr8
 141         set_icc         0x0d,3          ; Set mask opposite of expected
 142         csubcc          gr8,gr7,gr8,cc3,0
 143         test_icc        1 1 0 1 icc3
 144         test_gr_limmed  0x8000,0x0000,gr8
 145
 146         set_icc         0x0b,3          ; Set mask opposite of expected
 147         csubcc          gr8,gr8,gr8,cc7,1
 148         test_icc        1 0 1 1 icc3
 149         test_gr_limmed  0x8000,0x0000,gr8
 150
 151         set_icc         0x06,3          ; Set mask opposite of expected
 152         csubcc          gr8,gr7,gr8,cc7,1
 153         test_icc        0 1 1 0 icc3
 154         test_gr_limmed  0x8000,0x0000,gr8
 155
 156         pass